1 /**
2   ******************************************************************************
3   * @file    stm32f103x6.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32F1xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2017-2021 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 
28 /** @addtogroup CMSIS
29   * @{
30   */
31 
32 /** @addtogroup stm32f103x6
33   * @{
34   */
35 
36 #ifndef __STM32F103x6_H
37 #define __STM32F103x6_H
38 
39 #ifdef __cplusplus
40  extern "C" {
41 #endif
42 
43 /** @addtogroup Configuration_section_for_CMSIS
44   * @{
45   */
46 /**
47   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
48  */
49 #define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */
50  #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */
51 #define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */
52 #define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */
53 
54 /**
55   * @}
56   */
57 
58 /** @addtogroup Peripheral_interrupt_number_definition
59   * @{
60   */
61 
62 /**
63  * @brief STM32F10x Interrupt Number Definition, according to the selected device
64  *        in @ref Library_configuration_section
65  */
66 
67  /*!< Interrupt Number Definition */
68 typedef enum
69 {
70 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
71   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
72   HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */
73   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
74   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
75   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
76   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
77   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
78   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
79   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
80 
81 /******  STM32 specific Interrupt Numbers *********************************************************/
82   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
83   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
84   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
85   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
86   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
87   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
88   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
89   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
90   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
91   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
92   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
93   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
94   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
95   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
96   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
97   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
98   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
99   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
100   ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */
101   USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */
102   USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */
103   CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */
104   CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */
105   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
106   TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */
107   TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */
108   TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */
109   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
110   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
111   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
112   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
113   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
114   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
115   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
116   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
117   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
118   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
119   USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
120 } IRQn_Type;
121 
122 /**
123   * @}
124   */
125 
126 #include "core_cm3.h"
127 #include "system_stm32f1xx.h"
128 #include <stdint.h>
129 
130 /** @addtogroup Peripheral_registers_structures
131   * @{
132   */
133 
134 /**
135   * @brief Analog to Digital Converter
136   */
137 
138 typedef struct
139 {
140   __IO uint32_t SR;
141   __IO uint32_t CR1;
142   __IO uint32_t CR2;
143   __IO uint32_t SMPR1;
144   __IO uint32_t SMPR2;
145   __IO uint32_t JOFR1;
146   __IO uint32_t JOFR2;
147   __IO uint32_t JOFR3;
148   __IO uint32_t JOFR4;
149   __IO uint32_t HTR;
150   __IO uint32_t LTR;
151   __IO uint32_t SQR1;
152   __IO uint32_t SQR2;
153   __IO uint32_t SQR3;
154   __IO uint32_t JSQR;
155   __IO uint32_t JDR1;
156   __IO uint32_t JDR2;
157   __IO uint32_t JDR3;
158   __IO uint32_t JDR4;
159   __IO uint32_t DR;
160 } ADC_TypeDef;
161 
162 typedef struct
163 {
164   __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */
165   __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */
166   __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */
167   uint32_t  RESERVED[16];
168   __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */
169 } ADC_Common_TypeDef;
170 
171 /**
172   * @brief Backup Registers
173   */
174 
175 typedef struct
176 {
177   uint32_t  RESERVED0;
178   __IO uint32_t DR1;
179   __IO uint32_t DR2;
180   __IO uint32_t DR3;
181   __IO uint32_t DR4;
182   __IO uint32_t DR5;
183   __IO uint32_t DR6;
184   __IO uint32_t DR7;
185   __IO uint32_t DR8;
186   __IO uint32_t DR9;
187   __IO uint32_t DR10;
188   __IO uint32_t RTCCR;
189   __IO uint32_t CR;
190   __IO uint32_t CSR;
191 } BKP_TypeDef;
192 
193 /**
194   * @brief Controller Area Network TxMailBox
195   */
196 
197 typedef struct
198 {
199   __IO uint32_t TIR;
200   __IO uint32_t TDTR;
201   __IO uint32_t TDLR;
202   __IO uint32_t TDHR;
203 } CAN_TxMailBox_TypeDef;
204 
205 /**
206   * @brief Controller Area Network FIFOMailBox
207   */
208 
209 typedef struct
210 {
211   __IO uint32_t RIR;
212   __IO uint32_t RDTR;
213   __IO uint32_t RDLR;
214   __IO uint32_t RDHR;
215 } CAN_FIFOMailBox_TypeDef;
216 
217 /**
218   * @brief Controller Area Network FilterRegister
219   */
220 
221 typedef struct
222 {
223   __IO uint32_t FR1;
224   __IO uint32_t FR2;
225 } CAN_FilterRegister_TypeDef;
226 
227 /**
228   * @brief Controller Area Network
229   */
230 
231 typedef struct
232 {
233   __IO uint32_t MCR;
234   __IO uint32_t MSR;
235   __IO uint32_t TSR;
236   __IO uint32_t RF0R;
237   __IO uint32_t RF1R;
238   __IO uint32_t IER;
239   __IO uint32_t ESR;
240   __IO uint32_t BTR;
241   uint32_t  RESERVED0[88];
242   CAN_TxMailBox_TypeDef sTxMailBox[3];
243   CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
244   uint32_t  RESERVED1[12];
245   __IO uint32_t FMR;
246   __IO uint32_t FM1R;
247   uint32_t  RESERVED2;
248   __IO uint32_t FS1R;
249   uint32_t  RESERVED3;
250   __IO uint32_t FFA1R;
251   uint32_t  RESERVED4;
252   __IO uint32_t FA1R;
253   uint32_t  RESERVED5[8];
254   CAN_FilterRegister_TypeDef sFilterRegister[14];
255 } CAN_TypeDef;
256 
257 /**
258   * @brief CRC calculation unit
259   */
260 
261 typedef struct
262 {
263   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
264   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
265   uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
266   uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
267   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
268 } CRC_TypeDef;
269 
270 
271 /**
272   * @brief Debug MCU
273   */
274 
275 typedef struct
276 {
277   __IO uint32_t IDCODE;
278   __IO uint32_t CR;
279 }DBGMCU_TypeDef;
280 
281 /**
282   * @brief DMA Controller
283   */
284 
285 typedef struct
286 {
287   __IO uint32_t CCR;
288   __IO uint32_t CNDTR;
289   __IO uint32_t CPAR;
290   __IO uint32_t CMAR;
291 } DMA_Channel_TypeDef;
292 
293 typedef struct
294 {
295   __IO uint32_t ISR;
296   __IO uint32_t IFCR;
297 } DMA_TypeDef;
298 
299 
300 
301 /**
302   * @brief External Interrupt/Event Controller
303   */
304 
305 typedef struct
306 {
307   __IO uint32_t IMR;
308   __IO uint32_t EMR;
309   __IO uint32_t RTSR;
310   __IO uint32_t FTSR;
311   __IO uint32_t SWIER;
312   __IO uint32_t PR;
313 } EXTI_TypeDef;
314 
315 /**
316   * @brief FLASH Registers
317   */
318 
319 typedef struct
320 {
321   __IO uint32_t ACR;
322   __IO uint32_t KEYR;
323   __IO uint32_t OPTKEYR;
324   __IO uint32_t SR;
325   __IO uint32_t CR;
326   __IO uint32_t AR;
327   __IO uint32_t RESERVED;
328   __IO uint32_t OBR;
329   __IO uint32_t WRPR;
330 } FLASH_TypeDef;
331 
332 /**
333   * @brief Option Bytes Registers
334   */
335 
336 typedef struct
337 {
338   __IO uint16_t RDP;
339   __IO uint16_t USER;
340   __IO uint16_t Data0;
341   __IO uint16_t Data1;
342   __IO uint16_t WRP0;
343   __IO uint16_t WRP1;
344   __IO uint16_t WRP2;
345   __IO uint16_t WRP3;
346 } OB_TypeDef;
347 
348 /**
349   * @brief General Purpose I/O
350   */
351 
352 typedef struct
353 {
354   __IO uint32_t CRL;
355   __IO uint32_t CRH;
356   __IO uint32_t IDR;
357   __IO uint32_t ODR;
358   __IO uint32_t BSRR;
359   __IO uint32_t BRR;
360   __IO uint32_t LCKR;
361 } GPIO_TypeDef;
362 
363 /**
364   * @brief Alternate Function I/O
365   */
366 
367 typedef struct
368 {
369   __IO uint32_t EVCR;
370   __IO uint32_t MAPR;
371   __IO uint32_t EXTICR[4];
372   uint32_t RESERVED0;
373   __IO uint32_t MAPR2;
374 } AFIO_TypeDef;
375 /**
376   * @brief Inter Integrated Circuit Interface
377   */
378 
379 typedef struct
380 {
381   __IO uint32_t CR1;
382   __IO uint32_t CR2;
383   __IO uint32_t OAR1;
384   __IO uint32_t OAR2;
385   __IO uint32_t DR;
386   __IO uint32_t SR1;
387   __IO uint32_t SR2;
388   __IO uint32_t CCR;
389   __IO uint32_t TRISE;
390 } I2C_TypeDef;
391 
392 /**
393   * @brief Independent WATCHDOG
394   */
395 
396 typedef struct
397 {
398   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
399   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
400   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
401   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
402 } IWDG_TypeDef;
403 
404 /**
405   * @brief Power Control
406   */
407 
408 typedef struct
409 {
410   __IO uint32_t CR;
411   __IO uint32_t CSR;
412 } PWR_TypeDef;
413 
414 /**
415   * @brief Reset and Clock Control
416   */
417 
418 typedef struct
419 {
420   __IO uint32_t CR;
421   __IO uint32_t CFGR;
422   __IO uint32_t CIR;
423   __IO uint32_t APB2RSTR;
424   __IO uint32_t APB1RSTR;
425   __IO uint32_t AHBENR;
426   __IO uint32_t APB2ENR;
427   __IO uint32_t APB1ENR;
428   __IO uint32_t BDCR;
429   __IO uint32_t CSR;
430 
431 
432 } RCC_TypeDef;
433 
434 /**
435   * @brief Real-Time Clock
436   */
437 
438 typedef struct
439 {
440   __IO uint32_t CRH;
441   __IO uint32_t CRL;
442   __IO uint32_t PRLH;
443   __IO uint32_t PRLL;
444   __IO uint32_t DIVH;
445   __IO uint32_t DIVL;
446   __IO uint32_t CNTH;
447   __IO uint32_t CNTL;
448   __IO uint32_t ALRH;
449   __IO uint32_t ALRL;
450 } RTC_TypeDef;
451 
452 /**
453   * @brief Serial Peripheral Interface
454   */
455 
456 typedef struct
457 {
458   __IO uint32_t CR1;
459   __IO uint32_t CR2;
460   __IO uint32_t SR;
461   __IO uint32_t DR;
462   __IO uint32_t CRCPR;
463   __IO uint32_t RXCRCR;
464   __IO uint32_t TXCRCR;
465   __IO uint32_t I2SCFGR;
466 } SPI_TypeDef;
467 
468 /**
469   * @brief TIM Timers
470   */
471 typedef struct
472 {
473   __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
474   __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
475   __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
476   __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
477   __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
478   __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
479   __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
480   __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
481   __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
482   __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
483   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
484   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
485   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
486   __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
487   __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
488   __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
489   __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
490   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
491   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
492   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
493   __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
494 }TIM_TypeDef;
495 
496 
497 /**
498   * @brief Universal Synchronous Asynchronous Receiver Transmitter
499   */
500 
501 typedef struct
502 {
503   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
504   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
505   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
506   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
507   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
508   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
509   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
510 } USART_TypeDef;
511 
512 /**
513   * @brief Universal Serial Bus Full Speed Device
514   */
515 
516 typedef struct
517 {
518   __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */
519   __IO uint16_t RESERVED0;            /*!< Reserved */
520   __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */
521   __IO uint16_t RESERVED1;            /*!< Reserved */
522   __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */
523   __IO uint16_t RESERVED2;            /*!< Reserved */
524   __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */
525   __IO uint16_t RESERVED3;            /*!< Reserved */
526   __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */
527   __IO uint16_t RESERVED4;            /*!< Reserved */
528   __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */
529   __IO uint16_t RESERVED5;            /*!< Reserved */
530   __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */
531   __IO uint16_t RESERVED6;            /*!< Reserved */
532   __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */
533   __IO uint16_t RESERVED7[17];        /*!< Reserved */
534   __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */
535   __IO uint16_t RESERVED8;            /*!< Reserved */
536   __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */
537   __IO uint16_t RESERVED9;            /*!< Reserved */
538   __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */
539   __IO uint16_t RESERVEDA;            /*!< Reserved */
540   __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */
541   __IO uint16_t RESERVEDB;            /*!< Reserved */
542   __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */
543   __IO uint16_t RESERVEDC;            /*!< Reserved */
544 } USB_TypeDef;
545 
546 
547 /**
548   * @brief Window WATCHDOG
549   */
550 
551 typedef struct
552 {
553   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
554   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
555   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
556 } WWDG_TypeDef;
557 
558 /**
559   * @}
560   */
561 
562 /** @addtogroup Peripheral_memory_map
563   * @{
564   */
565 
566 
567 #define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */
568 #define FLASH_BANK1_END       0x08007FFFUL /*!< FLASH END address of bank1 */
569 #define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */
570 #define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */
571 
572 #define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */
573 #define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */
574 
575 
576 /*!< Peripheral memory map */
577 #define APB1PERIPH_BASE       PERIPH_BASE
578 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
579 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
580 
581 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)
582 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)
583 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)
584 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)
585 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)
586 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)
587 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)
588 #define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400UL)
589 #define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00UL)
590 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)
591 #define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000UL)
592 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)
593 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800UL)
594 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00UL)
595 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000UL)
596 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400UL)
597 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)
598 #define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800UL)
599 #define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)
600 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)
601 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)
602 
603 
604 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)
605 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008UL)
606 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CUL)
607 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030UL)
608 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044UL)
609 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058UL)
610 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CUL)
611 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080UL)
612 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
613 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
614 
615 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
616 #define FLASHSIZE_BASE        0x1FFFF7E0UL    /*!< FLASH Size register base address */
617 #define UID_BASE              0x1FFFF7E8UL    /*!< Unique device ID register base address */
618 #define OB_BASE               0x1FFFF800UL    /*!< Flash Option Bytes base address */
619 
620 
621 
622 #define DBGMCU_BASE          0xE0042000UL /*!< Debug MCU registers base address */
623 
624 /* USB device FS */
625 #define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
626 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
627 
628 
629 /**
630   * @}
631   */
632 
633 /** @addtogroup Peripheral_declaration
634   * @{
635   */
636 
637 #define TIM2                ((TIM_TypeDef *)TIM2_BASE)
638 #define TIM3                ((TIM_TypeDef *)TIM3_BASE)
639 #define RTC                 ((RTC_TypeDef *)RTC_BASE)
640 #define WWDG                ((WWDG_TypeDef *)WWDG_BASE)
641 #define IWDG                ((IWDG_TypeDef *)IWDG_BASE)
642 #define USART2              ((USART_TypeDef *)USART2_BASE)
643 #define I2C1                ((I2C_TypeDef *)I2C1_BASE)
644 #define USB                 ((USB_TypeDef *)USB_BASE)
645 #define CAN1                ((CAN_TypeDef *)CAN1_BASE)
646 #define BKP                 ((BKP_TypeDef *)BKP_BASE)
647 #define PWR                 ((PWR_TypeDef *)PWR_BASE)
648 #define AFIO                ((AFIO_TypeDef *)AFIO_BASE)
649 #define EXTI                ((EXTI_TypeDef *)EXTI_BASE)
650 #define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)
651 #define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)
652 #define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)
653 #define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)
654 #define ADC1                ((ADC_TypeDef *)ADC1_BASE)
655 #define ADC2                ((ADC_TypeDef *)ADC2_BASE)
656 #define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)
657 #define TIM1                ((TIM_TypeDef *)TIM1_BASE)
658 #define SPI1                ((SPI_TypeDef *)SPI1_BASE)
659 #define USART1              ((USART_TypeDef *)USART1_BASE)
660 #define DMA1                ((DMA_TypeDef *)DMA1_BASE)
661 #define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
662 #define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
663 #define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
664 #define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
665 #define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
666 #define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
667 #define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
668 #define RCC                 ((RCC_TypeDef *)RCC_BASE)
669 #define CRC                 ((CRC_TypeDef *)CRC_BASE)
670 #define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)
671 #define OB                  ((OB_TypeDef *)OB_BASE)
672 #define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)
673 
674 
675 /**
676   * @}
677   */
678 
679 /** @addtogroup Exported_constants
680   * @{
681   */
682 
683   /** @addtogroup Hardware_Constant_Definition
684     * @{
685     */
686 #define LSI_STARTUP_TIME                85U /*!< LSI Maximum startup time in us */
687   /**
688     * @}
689     */
690 
691   /** @addtogroup Peripheral_Registers_Bits_Definition
692   * @{
693   */
694 
695 /******************************************************************************/
696 /*                         Peripheral Registers_Bits_Definition               */
697 /******************************************************************************/
698 
699 /******************************************************************************/
700 /*                                                                            */
701 /*                       CRC calculation unit (CRC)                           */
702 /*                                                                            */
703 /******************************************************************************/
704 
705 /*******************  Bit definition for CRC_DR register  *********************/
706 #define CRC_DR_DR_Pos                       (0U)
707 #define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
708 #define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
709 
710 /*******************  Bit definition for CRC_IDR register  ********************/
711 #define CRC_IDR_IDR_Pos                     (0U)
712 #define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
713 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
714 
715 /********************  Bit definition for CRC_CR register  ********************/
716 #define CRC_CR_RESET_Pos                    (0U)
717 #define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
718 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
719 
720 /******************************************************************************/
721 /*                                                                            */
722 /*                             Power Control                                  */
723 /*                                                                            */
724 /******************************************************************************/
725 
726 /********************  Bit definition for PWR_CR register  ********************/
727 #define PWR_CR_LPDS_Pos                     (0U)
728 #define PWR_CR_LPDS_Msk                     (0x1UL << PWR_CR_LPDS_Pos)          /*!< 0x00000001 */
729 #define PWR_CR_LPDS                         PWR_CR_LPDS_Msk                    /*!< Low-Power Deepsleep */
730 #define PWR_CR_PDDS_Pos                     (1U)
731 #define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
732 #define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
733 #define PWR_CR_CWUF_Pos                     (2U)
734 #define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
735 #define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
736 #define PWR_CR_CSBF_Pos                     (3U)
737 #define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
738 #define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
739 #define PWR_CR_PVDE_Pos                     (4U)
740 #define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
741 #define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
742 
743 #define PWR_CR_PLS_Pos                      (5U)
744 #define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
745 #define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
746 #define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
747 #define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
748 #define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
749 
750 /*!< PVD level configuration */
751 #define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */
752 #define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */
753 #define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */
754 #define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */
755 #define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */
756 #define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */
757 #define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */
758 #define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */
759 
760 /* Legacy defines */
761 #define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0
762 #define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1
763 #define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2
764 #define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3
765 #define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4
766 #define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5
767 #define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6
768 #define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7
769 
770 #define PWR_CR_DBP_Pos                      (8U)
771 #define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
772 #define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
773 
774 
775 /*******************  Bit definition for PWR_CSR register  ********************/
776 #define PWR_CSR_WUF_Pos                     (0U)
777 #define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
778 #define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
779 #define PWR_CSR_SBF_Pos                     (1U)
780 #define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
781 #define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
782 #define PWR_CSR_PVDO_Pos                    (2U)
783 #define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
784 #define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
785 #define PWR_CSR_EWUP_Pos                    (8U)
786 #define PWR_CSR_EWUP_Msk                    (0x1UL << PWR_CSR_EWUP_Pos)         /*!< 0x00000100 */
787 #define PWR_CSR_EWUP                        PWR_CSR_EWUP_Msk                   /*!< Enable WKUP pin */
788 
789 /******************************************************************************/
790 /*                                                                            */
791 /*                            Backup registers                                */
792 /*                                                                            */
793 /******************************************************************************/
794 
795 /*******************  Bit definition for BKP_DR1 register  ********************/
796 #define BKP_DR1_D_Pos                       (0U)
797 #define BKP_DR1_D_Msk                       (0xFFFFUL << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */
798 #define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */
799 
800 /*******************  Bit definition for BKP_DR2 register  ********************/
801 #define BKP_DR2_D_Pos                       (0U)
802 #define BKP_DR2_D_Msk                       (0xFFFFUL << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */
803 #define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */
804 
805 /*******************  Bit definition for BKP_DR3 register  ********************/
806 #define BKP_DR3_D_Pos                       (0U)
807 #define BKP_DR3_D_Msk                       (0xFFFFUL << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */
808 #define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */
809 
810 /*******************  Bit definition for BKP_DR4 register  ********************/
811 #define BKP_DR4_D_Pos                       (0U)
812 #define BKP_DR4_D_Msk                       (0xFFFFUL << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */
813 #define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */
814 
815 /*******************  Bit definition for BKP_DR5 register  ********************/
816 #define BKP_DR5_D_Pos                       (0U)
817 #define BKP_DR5_D_Msk                       (0xFFFFUL << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */
818 #define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */
819 
820 /*******************  Bit definition for BKP_DR6 register  ********************/
821 #define BKP_DR6_D_Pos                       (0U)
822 #define BKP_DR6_D_Msk                       (0xFFFFUL << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */
823 #define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */
824 
825 /*******************  Bit definition for BKP_DR7 register  ********************/
826 #define BKP_DR7_D_Pos                       (0U)
827 #define BKP_DR7_D_Msk                       (0xFFFFUL << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */
828 #define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */
829 
830 /*******************  Bit definition for BKP_DR8 register  ********************/
831 #define BKP_DR8_D_Pos                       (0U)
832 #define BKP_DR8_D_Msk                       (0xFFFFUL << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */
833 #define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */
834 
835 /*******************  Bit definition for BKP_DR9 register  ********************/
836 #define BKP_DR9_D_Pos                       (0U)
837 #define BKP_DR9_D_Msk                       (0xFFFFUL << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */
838 #define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */
839 
840 /*******************  Bit definition for BKP_DR10 register  *******************/
841 #define BKP_DR10_D_Pos                      (0U)
842 #define BKP_DR10_D_Msk                      (0xFFFFUL << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */
843 #define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */
844 
845 #define RTC_BKP_NUMBER 10
846 
847 /******************  Bit definition for BKP_RTCCR register  *******************/
848 #define BKP_RTCCR_CAL_Pos                   (0U)
849 #define BKP_RTCCR_CAL_Msk                   (0x7FUL << BKP_RTCCR_CAL_Pos)       /*!< 0x0000007F */
850 #define BKP_RTCCR_CAL                       BKP_RTCCR_CAL_Msk                  /*!< Calibration value */
851 #define BKP_RTCCR_CCO_Pos                   (7U)
852 #define BKP_RTCCR_CCO_Msk                   (0x1UL << BKP_RTCCR_CCO_Pos)        /*!< 0x00000080 */
853 #define BKP_RTCCR_CCO                       BKP_RTCCR_CCO_Msk                  /*!< Calibration Clock Output */
854 #define BKP_RTCCR_ASOE_Pos                  (8U)
855 #define BKP_RTCCR_ASOE_Msk                  (0x1UL << BKP_RTCCR_ASOE_Pos)       /*!< 0x00000100 */
856 #define BKP_RTCCR_ASOE                      BKP_RTCCR_ASOE_Msk                 /*!< Alarm or Second Output Enable */
857 #define BKP_RTCCR_ASOS_Pos                  (9U)
858 #define BKP_RTCCR_ASOS_Msk                  (0x1UL << BKP_RTCCR_ASOS_Pos)       /*!< 0x00000200 */
859 #define BKP_RTCCR_ASOS                      BKP_RTCCR_ASOS_Msk                 /*!< Alarm or Second Output Selection */
860 
861 /********************  Bit definition for BKP_CR register  ********************/
862 #define BKP_CR_TPE_Pos                      (0U)
863 #define BKP_CR_TPE_Msk                      (0x1UL << BKP_CR_TPE_Pos)           /*!< 0x00000001 */
864 #define BKP_CR_TPE                          BKP_CR_TPE_Msk                     /*!< TAMPER pin enable */
865 #define BKP_CR_TPAL_Pos                     (1U)
866 #define BKP_CR_TPAL_Msk                     (0x1UL << BKP_CR_TPAL_Pos)          /*!< 0x00000002 */
867 #define BKP_CR_TPAL                         BKP_CR_TPAL_Msk                    /*!< TAMPER pin active level */
868 
869 /*******************  Bit definition for BKP_CSR register  ********************/
870 #define BKP_CSR_CTE_Pos                     (0U)
871 #define BKP_CSR_CTE_Msk                     (0x1UL << BKP_CSR_CTE_Pos)          /*!< 0x00000001 */
872 #define BKP_CSR_CTE                         BKP_CSR_CTE_Msk                    /*!< Clear Tamper event */
873 #define BKP_CSR_CTI_Pos                     (1U)
874 #define BKP_CSR_CTI_Msk                     (0x1UL << BKP_CSR_CTI_Pos)          /*!< 0x00000002 */
875 #define BKP_CSR_CTI                         BKP_CSR_CTI_Msk                    /*!< Clear Tamper Interrupt */
876 #define BKP_CSR_TPIE_Pos                    (2U)
877 #define BKP_CSR_TPIE_Msk                    (0x1UL << BKP_CSR_TPIE_Pos)         /*!< 0x00000004 */
878 #define BKP_CSR_TPIE                        BKP_CSR_TPIE_Msk                   /*!< TAMPER Pin interrupt enable */
879 #define BKP_CSR_TEF_Pos                     (8U)
880 #define BKP_CSR_TEF_Msk                     (0x1UL << BKP_CSR_TEF_Pos)          /*!< 0x00000100 */
881 #define BKP_CSR_TEF                         BKP_CSR_TEF_Msk                    /*!< Tamper Event Flag */
882 #define BKP_CSR_TIF_Pos                     (9U)
883 #define BKP_CSR_TIF_Msk                     (0x1UL << BKP_CSR_TIF_Pos)          /*!< 0x00000200 */
884 #define BKP_CSR_TIF                         BKP_CSR_TIF_Msk                    /*!< Tamper Interrupt Flag */
885 
886 /******************************************************************************/
887 /*                                                                            */
888 /*                         Reset and Clock Control                            */
889 /*                                                                            */
890 /******************************************************************************/
891 
892 /********************  Bit definition for RCC_CR register  ********************/
893 #define RCC_CR_HSION_Pos                     (0U)
894 #define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)        /*!< 0x00000001 */
895 #define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed clock enable */
896 #define RCC_CR_HSIRDY_Pos                    (1U)
897 #define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)       /*!< 0x00000002 */
898 #define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed clock ready flag */
899 #define RCC_CR_HSITRIM_Pos                   (3U)
900 #define RCC_CR_HSITRIM_Msk                   (0x1FUL << RCC_CR_HSITRIM_Pos)     /*!< 0x000000F8 */
901 #define RCC_CR_HSITRIM                       RCC_CR_HSITRIM_Msk                /*!< Internal High Speed clock trimming */
902 #define RCC_CR_HSICAL_Pos                    (8U)
903 #define RCC_CR_HSICAL_Msk                    (0xFFUL << RCC_CR_HSICAL_Pos)      /*!< 0x0000FF00 */
904 #define RCC_CR_HSICAL                        RCC_CR_HSICAL_Msk                 /*!< Internal High Speed clock Calibration */
905 #define RCC_CR_HSEON_Pos                     (16U)
906 #define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */
907 #define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed clock enable */
908 #define RCC_CR_HSERDY_Pos                    (17U)
909 #define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */
910 #define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed clock ready flag */
911 #define RCC_CR_HSEBYP_Pos                    (18U)
912 #define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */
913 #define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed clock Bypass */
914 #define RCC_CR_CSSON_Pos                     (19U)
915 #define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */
916 #define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< Clock Security System enable */
917 #define RCC_CR_PLLON_Pos                     (24U)
918 #define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */
919 #define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< PLL enable */
920 #define RCC_CR_PLLRDY_Pos                    (25U)
921 #define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */
922 #define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */
923 
924 
925 /*******************  Bit definition for RCC_CFGR register  *******************/
926 /*!< SW configuration */
927 #define RCC_CFGR_SW_Pos                      (0U)
928 #define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */
929 #define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
930 #define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */
931 #define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */
932 
933 #define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */
934 #define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */
935 #define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */
936 
937 /*!< SWS configuration */
938 #define RCC_CFGR_SWS_Pos                     (2U)
939 #define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */
940 #define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
941 #define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */
942 #define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */
943 
944 #define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */
945 #define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */
946 #define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */
947 
948 /*!< HPRE configuration */
949 #define RCC_CFGR_HPRE_Pos                    (4U)
950 #define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */
951 #define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
952 #define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */
953 #define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */
954 #define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */
955 #define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */
956 
957 #define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */
958 #define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */
959 #define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */
960 #define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */
961 #define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */
962 #define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */
963 #define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */
964 #define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */
965 #define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */
966 
967 /*!< PPRE1 configuration */
968 #define RCC_CFGR_PPRE1_Pos                   (8U)
969 #define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */
970 #define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
971 #define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */
972 #define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */
973 #define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */
974 
975 #define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */
976 #define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */
977 #define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */
978 #define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */
979 #define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */
980 
981 /*!< PPRE2 configuration */
982 #define RCC_CFGR_PPRE2_Pos                   (11U)
983 #define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */
984 #define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
985 #define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */
986 #define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */
987 #define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */
988 
989 #define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */
990 #define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */
991 #define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */
992 #define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */
993 #define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */
994 
995 /*!< ADCPPRE configuration */
996 #define RCC_CFGR_ADCPRE_Pos                  (14U)
997 #define RCC_CFGR_ADCPRE_Msk                  (0x3UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x0000C000 */
998 #define RCC_CFGR_ADCPRE                      RCC_CFGR_ADCPRE_Msk               /*!< ADCPRE[1:0] bits (ADC prescaler) */
999 #define RCC_CFGR_ADCPRE_0                    (0x1UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */
1000 #define RCC_CFGR_ADCPRE_1                    (0x2UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */
1001 
1002 #define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */
1003 #define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */
1004 #define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */
1005 #define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */
1006 
1007 #define RCC_CFGR_PLLSRC_Pos                  (16U)
1008 #define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */
1009 #define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */
1010 
1011 #define RCC_CFGR_PLLXTPRE_Pos                (17U)
1012 #define RCC_CFGR_PLLXTPRE_Msk                (0x1UL << RCC_CFGR_PLLXTPRE_Pos)   /*!< 0x00020000 */
1013 #define RCC_CFGR_PLLXTPRE                    RCC_CFGR_PLLXTPRE_Msk             /*!< HSE divider for PLL entry */
1014 
1015 /*!< PLLMUL configuration */
1016 #define RCC_CFGR_PLLMULL_Pos                 (18U)
1017 #define RCC_CFGR_PLLMULL_Msk                 (0xFUL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x003C0000 */
1018 #define RCC_CFGR_PLLMULL                     RCC_CFGR_PLLMULL_Msk              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1019 #define RCC_CFGR_PLLMULL_0                   (0x1UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00040000 */
1020 #define RCC_CFGR_PLLMULL_1                   (0x2UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00080000 */
1021 #define RCC_CFGR_PLLMULL_2                   (0x4UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */
1022 #define RCC_CFGR_PLLMULL_3                   (0x8UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */
1023 
1024 #define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */
1025 #define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */
1026 
1027 #define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */
1028 #define RCC_CFGR_PLLMULL3_Pos                (18U)
1029 #define RCC_CFGR_PLLMULL3_Msk                (0x1UL << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */
1030 #define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */
1031 #define RCC_CFGR_PLLMULL4_Pos                (19U)
1032 #define RCC_CFGR_PLLMULL4_Msk                (0x1UL << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */
1033 #define RCC_CFGR_PLLMULL4                    RCC_CFGR_PLLMULL4_Msk             /*!< PLL input clock*4 */
1034 #define RCC_CFGR_PLLMULL5_Pos                (18U)
1035 #define RCC_CFGR_PLLMULL5_Msk                (0x3UL << RCC_CFGR_PLLMULL5_Pos)   /*!< 0x000C0000 */
1036 #define RCC_CFGR_PLLMULL5                    RCC_CFGR_PLLMULL5_Msk             /*!< PLL input clock*5 */
1037 #define RCC_CFGR_PLLMULL6_Pos                (20U)
1038 #define RCC_CFGR_PLLMULL6_Msk                (0x1UL << RCC_CFGR_PLLMULL6_Pos)   /*!< 0x00100000 */
1039 #define RCC_CFGR_PLLMULL6                    RCC_CFGR_PLLMULL6_Msk             /*!< PLL input clock*6 */
1040 #define RCC_CFGR_PLLMULL7_Pos                (18U)
1041 #define RCC_CFGR_PLLMULL7_Msk                (0x5UL << RCC_CFGR_PLLMULL7_Pos)   /*!< 0x00140000 */
1042 #define RCC_CFGR_PLLMULL7                    RCC_CFGR_PLLMULL7_Msk             /*!< PLL input clock*7 */
1043 #define RCC_CFGR_PLLMULL8_Pos                (19U)
1044 #define RCC_CFGR_PLLMULL8_Msk                (0x3UL << RCC_CFGR_PLLMULL8_Pos)   /*!< 0x00180000 */
1045 #define RCC_CFGR_PLLMULL8                    RCC_CFGR_PLLMULL8_Msk             /*!< PLL input clock*8 */
1046 #define RCC_CFGR_PLLMULL9_Pos                (18U)
1047 #define RCC_CFGR_PLLMULL9_Msk                (0x7UL << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */
1048 #define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock*9 */
1049 #define RCC_CFGR_PLLMULL10_Pos               (21U)
1050 #define RCC_CFGR_PLLMULL10_Msk               (0x1UL << RCC_CFGR_PLLMULL10_Pos)  /*!< 0x00200000 */
1051 #define RCC_CFGR_PLLMULL10                   RCC_CFGR_PLLMULL10_Msk            /*!< PLL input clock10 */
1052 #define RCC_CFGR_PLLMULL11_Pos               (18U)
1053 #define RCC_CFGR_PLLMULL11_Msk               (0x9UL << RCC_CFGR_PLLMULL11_Pos)  /*!< 0x00240000 */
1054 #define RCC_CFGR_PLLMULL11                   RCC_CFGR_PLLMULL11_Msk            /*!< PLL input clock*11 */
1055 #define RCC_CFGR_PLLMULL12_Pos               (19U)
1056 #define RCC_CFGR_PLLMULL12_Msk               (0x5UL << RCC_CFGR_PLLMULL12_Pos)  /*!< 0x00280000 */
1057 #define RCC_CFGR_PLLMULL12                   RCC_CFGR_PLLMULL12_Msk            /*!< PLL input clock*12 */
1058 #define RCC_CFGR_PLLMULL13_Pos               (18U)
1059 #define RCC_CFGR_PLLMULL13_Msk               (0xBUL << RCC_CFGR_PLLMULL13_Pos)  /*!< 0x002C0000 */
1060 #define RCC_CFGR_PLLMULL13                   RCC_CFGR_PLLMULL13_Msk            /*!< PLL input clock*13 */
1061 #define RCC_CFGR_PLLMULL14_Pos               (20U)
1062 #define RCC_CFGR_PLLMULL14_Msk               (0x3UL << RCC_CFGR_PLLMULL14_Pos)  /*!< 0x00300000 */
1063 #define RCC_CFGR_PLLMULL14                   RCC_CFGR_PLLMULL14_Msk            /*!< PLL input clock*14 */
1064 #define RCC_CFGR_PLLMULL15_Pos               (18U)
1065 #define RCC_CFGR_PLLMULL15_Msk               (0xDUL << RCC_CFGR_PLLMULL15_Pos)  /*!< 0x00340000 */
1066 #define RCC_CFGR_PLLMULL15                   RCC_CFGR_PLLMULL15_Msk            /*!< PLL input clock*15 */
1067 #define RCC_CFGR_PLLMULL16_Pos               (19U)
1068 #define RCC_CFGR_PLLMULL16_Msk               (0x7UL << RCC_CFGR_PLLMULL16_Pos)  /*!< 0x00380000 */
1069 #define RCC_CFGR_PLLMULL16                   RCC_CFGR_PLLMULL16_Msk            /*!< PLL input clock*16 */
1070 #define RCC_CFGR_USBPRE_Pos                  (22U)
1071 #define RCC_CFGR_USBPRE_Msk                  (0x1UL << RCC_CFGR_USBPRE_Pos)     /*!< 0x00400000 */
1072 #define RCC_CFGR_USBPRE                      RCC_CFGR_USBPRE_Msk               /*!< USB Device prescaler */
1073 
1074 /*!< MCO configuration */
1075 #define RCC_CFGR_MCO_Pos                     (24U)
1076 #define RCC_CFGR_MCO_Msk                     (0x7UL << RCC_CFGR_MCO_Pos)        /*!< 0x07000000 */
1077 #define RCC_CFGR_MCO                         RCC_CFGR_MCO_Msk                  /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1078 #define RCC_CFGR_MCO_0                       (0x1UL << RCC_CFGR_MCO_Pos)        /*!< 0x01000000 */
1079 #define RCC_CFGR_MCO_1                       (0x2UL << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */
1080 #define RCC_CFGR_MCO_2                       (0x4UL << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */
1081 
1082 #define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */
1083 #define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */
1084 #define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */
1085 #define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */
1086 #define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */
1087 
1088  /* Reference defines */
1089  #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO
1090  #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0
1091  #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1
1092  #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2
1093  #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK
1094  #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK
1095  #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI
1096  #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE
1097  #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2
1098 
1099 /*!<******************  Bit definition for RCC_CIR register  ********************/
1100 #define RCC_CIR_LSIRDYF_Pos                  (0U)
1101 #define RCC_CIR_LSIRDYF_Msk                  (0x1UL << RCC_CIR_LSIRDYF_Pos)     /*!< 0x00000001 */
1102 #define RCC_CIR_LSIRDYF                      RCC_CIR_LSIRDYF_Msk               /*!< LSI Ready Interrupt flag */
1103 #define RCC_CIR_LSERDYF_Pos                  (1U)
1104 #define RCC_CIR_LSERDYF_Msk                  (0x1UL << RCC_CIR_LSERDYF_Pos)     /*!< 0x00000002 */
1105 #define RCC_CIR_LSERDYF                      RCC_CIR_LSERDYF_Msk               /*!< LSE Ready Interrupt flag */
1106 #define RCC_CIR_HSIRDYF_Pos                  (2U)
1107 #define RCC_CIR_HSIRDYF_Msk                  (0x1UL << RCC_CIR_HSIRDYF_Pos)     /*!< 0x00000004 */
1108 #define RCC_CIR_HSIRDYF                      RCC_CIR_HSIRDYF_Msk               /*!< HSI Ready Interrupt flag */
1109 #define RCC_CIR_HSERDYF_Pos                  (3U)
1110 #define RCC_CIR_HSERDYF_Msk                  (0x1UL << RCC_CIR_HSERDYF_Pos)     /*!< 0x00000008 */
1111 #define RCC_CIR_HSERDYF                      RCC_CIR_HSERDYF_Msk               /*!< HSE Ready Interrupt flag */
1112 #define RCC_CIR_PLLRDYF_Pos                  (4U)
1113 #define RCC_CIR_PLLRDYF_Msk                  (0x1UL << RCC_CIR_PLLRDYF_Pos)     /*!< 0x00000010 */
1114 #define RCC_CIR_PLLRDYF                      RCC_CIR_PLLRDYF_Msk               /*!< PLL Ready Interrupt flag */
1115 #define RCC_CIR_CSSF_Pos                     (7U)
1116 #define RCC_CIR_CSSF_Msk                     (0x1UL << RCC_CIR_CSSF_Pos)        /*!< 0x00000080 */
1117 #define RCC_CIR_CSSF                         RCC_CIR_CSSF_Msk                  /*!< Clock Security System Interrupt flag */
1118 #define RCC_CIR_LSIRDYIE_Pos                 (8U)
1119 #define RCC_CIR_LSIRDYIE_Msk                 (0x1UL << RCC_CIR_LSIRDYIE_Pos)    /*!< 0x00000100 */
1120 #define RCC_CIR_LSIRDYIE                     RCC_CIR_LSIRDYIE_Msk              /*!< LSI Ready Interrupt Enable */
1121 #define RCC_CIR_LSERDYIE_Pos                 (9U)
1122 #define RCC_CIR_LSERDYIE_Msk                 (0x1UL << RCC_CIR_LSERDYIE_Pos)    /*!< 0x00000200 */
1123 #define RCC_CIR_LSERDYIE                     RCC_CIR_LSERDYIE_Msk              /*!< LSE Ready Interrupt Enable */
1124 #define RCC_CIR_HSIRDYIE_Pos                 (10U)
1125 #define RCC_CIR_HSIRDYIE_Msk                 (0x1UL << RCC_CIR_HSIRDYIE_Pos)    /*!< 0x00000400 */
1126 #define RCC_CIR_HSIRDYIE                     RCC_CIR_HSIRDYIE_Msk              /*!< HSI Ready Interrupt Enable */
1127 #define RCC_CIR_HSERDYIE_Pos                 (11U)
1128 #define RCC_CIR_HSERDYIE_Msk                 (0x1UL << RCC_CIR_HSERDYIE_Pos)    /*!< 0x00000800 */
1129 #define RCC_CIR_HSERDYIE                     RCC_CIR_HSERDYIE_Msk              /*!< HSE Ready Interrupt Enable */
1130 #define RCC_CIR_PLLRDYIE_Pos                 (12U)
1131 #define RCC_CIR_PLLRDYIE_Msk                 (0x1UL << RCC_CIR_PLLRDYIE_Pos)    /*!< 0x00001000 */
1132 #define RCC_CIR_PLLRDYIE                     RCC_CIR_PLLRDYIE_Msk              /*!< PLL Ready Interrupt Enable */
1133 #define RCC_CIR_LSIRDYC_Pos                  (16U)
1134 #define RCC_CIR_LSIRDYC_Msk                  (0x1UL << RCC_CIR_LSIRDYC_Pos)     /*!< 0x00010000 */
1135 #define RCC_CIR_LSIRDYC                      RCC_CIR_LSIRDYC_Msk               /*!< LSI Ready Interrupt Clear */
1136 #define RCC_CIR_LSERDYC_Pos                  (17U)
1137 #define RCC_CIR_LSERDYC_Msk                  (0x1UL << RCC_CIR_LSERDYC_Pos)     /*!< 0x00020000 */
1138 #define RCC_CIR_LSERDYC                      RCC_CIR_LSERDYC_Msk               /*!< LSE Ready Interrupt Clear */
1139 #define RCC_CIR_HSIRDYC_Pos                  (18U)
1140 #define RCC_CIR_HSIRDYC_Msk                  (0x1UL << RCC_CIR_HSIRDYC_Pos)     /*!< 0x00040000 */
1141 #define RCC_CIR_HSIRDYC                      RCC_CIR_HSIRDYC_Msk               /*!< HSI Ready Interrupt Clear */
1142 #define RCC_CIR_HSERDYC_Pos                  (19U)
1143 #define RCC_CIR_HSERDYC_Msk                  (0x1UL << RCC_CIR_HSERDYC_Pos)     /*!< 0x00080000 */
1144 #define RCC_CIR_HSERDYC                      RCC_CIR_HSERDYC_Msk               /*!< HSE Ready Interrupt Clear */
1145 #define RCC_CIR_PLLRDYC_Pos                  (20U)
1146 #define RCC_CIR_PLLRDYC_Msk                  (0x1UL << RCC_CIR_PLLRDYC_Pos)     /*!< 0x00100000 */
1147 #define RCC_CIR_PLLRDYC                      RCC_CIR_PLLRDYC_Msk               /*!< PLL Ready Interrupt Clear */
1148 #define RCC_CIR_CSSC_Pos                     (23U)
1149 #define RCC_CIR_CSSC_Msk                     (0x1UL << RCC_CIR_CSSC_Pos)        /*!< 0x00800000 */
1150 #define RCC_CIR_CSSC                         RCC_CIR_CSSC_Msk                  /*!< Clock Security System Interrupt Clear */
1151 
1152 
1153 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
1154 #define RCC_APB2RSTR_AFIORST_Pos             (0U)
1155 #define RCC_APB2RSTR_AFIORST_Msk             (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1156 #define RCC_APB2RSTR_AFIORST                 RCC_APB2RSTR_AFIORST_Msk          /*!< Alternate Function I/O reset */
1157 #define RCC_APB2RSTR_IOPARST_Pos             (2U)
1158 #define RCC_APB2RSTR_IOPARST_Msk             (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1159 #define RCC_APB2RSTR_IOPARST                 RCC_APB2RSTR_IOPARST_Msk          /*!< I/O port A reset */
1160 #define RCC_APB2RSTR_IOPBRST_Pos             (3U)
1161 #define RCC_APB2RSTR_IOPBRST_Msk             (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1162 #define RCC_APB2RSTR_IOPBRST                 RCC_APB2RSTR_IOPBRST_Msk          /*!< I/O port B reset */
1163 #define RCC_APB2RSTR_IOPCRST_Pos             (4U)
1164 #define RCC_APB2RSTR_IOPCRST_Msk             (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1165 #define RCC_APB2RSTR_IOPCRST                 RCC_APB2RSTR_IOPCRST_Msk          /*!< I/O port C reset */
1166 #define RCC_APB2RSTR_IOPDRST_Pos             (5U)
1167 #define RCC_APB2RSTR_IOPDRST_Msk             (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1168 #define RCC_APB2RSTR_IOPDRST                 RCC_APB2RSTR_IOPDRST_Msk          /*!< I/O port D reset */
1169 #define RCC_APB2RSTR_ADC1RST_Pos             (9U)
1170 #define RCC_APB2RSTR_ADC1RST_Msk             (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1171 #define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */
1172 
1173 #define RCC_APB2RSTR_ADC2RST_Pos             (10U)
1174 #define RCC_APB2RSTR_ADC2RST_Msk             (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
1175 #define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */
1176 
1177 #define RCC_APB2RSTR_TIM1RST_Pos             (11U)
1178 #define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1179 #define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          /*!< TIM1 Timer reset */
1180 #define RCC_APB2RSTR_SPI1RST_Pos             (12U)
1181 #define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1182 #define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          /*!< SPI 1 reset */
1183 #define RCC_APB2RSTR_USART1RST_Pos           (14U)
1184 #define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1185 #define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        /*!< USART1 reset */
1186 
1187 
1188 
1189 
1190 
1191 
1192 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
1193 #define RCC_APB1RSTR_TIM2RST_Pos             (0U)
1194 #define RCC_APB1RSTR_TIM2RST_Msk             (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1195 #define RCC_APB1RSTR_TIM2RST                 RCC_APB1RSTR_TIM2RST_Msk          /*!< Timer 2 reset */
1196 #define RCC_APB1RSTR_TIM3RST_Pos             (1U)
1197 #define RCC_APB1RSTR_TIM3RST_Msk             (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1198 #define RCC_APB1RSTR_TIM3RST                 RCC_APB1RSTR_TIM3RST_Msk          /*!< Timer 3 reset */
1199 #define RCC_APB1RSTR_WWDGRST_Pos             (11U)
1200 #define RCC_APB1RSTR_WWDGRST_Msk             (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1201 #define RCC_APB1RSTR_WWDGRST                 RCC_APB1RSTR_WWDGRST_Msk          /*!< Window Watchdog reset */
1202 #define RCC_APB1RSTR_USART2RST_Pos           (17U)
1203 #define RCC_APB1RSTR_USART2RST_Msk           (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1204 #define RCC_APB1RSTR_USART2RST               RCC_APB1RSTR_USART2RST_Msk        /*!< USART 2 reset */
1205 #define RCC_APB1RSTR_I2C1RST_Pos             (21U)
1206 #define RCC_APB1RSTR_I2C1RST_Msk             (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1207 #define RCC_APB1RSTR_I2C1RST                 RCC_APB1RSTR_I2C1RST_Msk          /*!< I2C 1 reset */
1208 
1209 #define RCC_APB1RSTR_CAN1RST_Pos             (25U)
1210 #define RCC_APB1RSTR_CAN1RST_Msk             (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
1211 #define RCC_APB1RSTR_CAN1RST                 RCC_APB1RSTR_CAN1RST_Msk          /*!< CAN1 reset */
1212 
1213 #define RCC_APB1RSTR_BKPRST_Pos              (27U)
1214 #define RCC_APB1RSTR_BKPRST_Msk              (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1215 #define RCC_APB1RSTR_BKPRST                  RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */
1216 #define RCC_APB1RSTR_PWRRST_Pos              (28U)
1217 #define RCC_APB1RSTR_PWRRST_Msk              (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1218 #define RCC_APB1RSTR_PWRRST                  RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */
1219 
1220 
1221 #define RCC_APB1RSTR_USBRST_Pos              (23U)
1222 #define RCC_APB1RSTR_USBRST_Msk              (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
1223 #define RCC_APB1RSTR_USBRST                  RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */
1224 
1225 
1226 
1227 
1228 
1229 
1230 /******************  Bit definition for RCC_AHBENR register  ******************/
1231 #define RCC_AHBENR_DMA1EN_Pos                (0U)
1232 #define RCC_AHBENR_DMA1EN_Msk                (0x1UL << RCC_AHBENR_DMA1EN_Pos)   /*!< 0x00000001 */
1233 #define RCC_AHBENR_DMA1EN                    RCC_AHBENR_DMA1EN_Msk             /*!< DMA1 clock enable */
1234 #define RCC_AHBENR_SRAMEN_Pos                (2U)
1235 #define RCC_AHBENR_SRAMEN_Msk                (0x1UL << RCC_AHBENR_SRAMEN_Pos)   /*!< 0x00000004 */
1236 #define RCC_AHBENR_SRAMEN                    RCC_AHBENR_SRAMEN_Msk             /*!< SRAM interface clock enable */
1237 #define RCC_AHBENR_FLITFEN_Pos               (4U)
1238 #define RCC_AHBENR_FLITFEN_Msk               (0x1UL << RCC_AHBENR_FLITFEN_Pos)  /*!< 0x00000010 */
1239 #define RCC_AHBENR_FLITFEN                   RCC_AHBENR_FLITFEN_Msk            /*!< FLITF clock enable */
1240 #define RCC_AHBENR_CRCEN_Pos                 (6U)
1241 #define RCC_AHBENR_CRCEN_Msk                 (0x1UL << RCC_AHBENR_CRCEN_Pos)    /*!< 0x00000040 */
1242 #define RCC_AHBENR_CRCEN                     RCC_AHBENR_CRCEN_Msk              /*!< CRC clock enable */
1243 
1244 
1245 
1246 
1247 /******************  Bit definition for RCC_APB2ENR register  *****************/
1248 #define RCC_APB2ENR_AFIOEN_Pos               (0U)
1249 #define RCC_APB2ENR_AFIOEN_Msk               (0x1UL << RCC_APB2ENR_AFIOEN_Pos)  /*!< 0x00000001 */
1250 #define RCC_APB2ENR_AFIOEN                   RCC_APB2ENR_AFIOEN_Msk            /*!< Alternate Function I/O clock enable */
1251 #define RCC_APB2ENR_IOPAEN_Pos               (2U)
1252 #define RCC_APB2ENR_IOPAEN_Msk               (0x1UL << RCC_APB2ENR_IOPAEN_Pos)  /*!< 0x00000004 */
1253 #define RCC_APB2ENR_IOPAEN                   RCC_APB2ENR_IOPAEN_Msk            /*!< I/O port A clock enable */
1254 #define RCC_APB2ENR_IOPBEN_Pos               (3U)
1255 #define RCC_APB2ENR_IOPBEN_Msk               (0x1UL << RCC_APB2ENR_IOPBEN_Pos)  /*!< 0x00000008 */
1256 #define RCC_APB2ENR_IOPBEN                   RCC_APB2ENR_IOPBEN_Msk            /*!< I/O port B clock enable */
1257 #define RCC_APB2ENR_IOPCEN_Pos               (4U)
1258 #define RCC_APB2ENR_IOPCEN_Msk               (0x1UL << RCC_APB2ENR_IOPCEN_Pos)  /*!< 0x00000010 */
1259 #define RCC_APB2ENR_IOPCEN                   RCC_APB2ENR_IOPCEN_Msk            /*!< I/O port C clock enable */
1260 #define RCC_APB2ENR_IOPDEN_Pos               (5U)
1261 #define RCC_APB2ENR_IOPDEN_Msk               (0x1UL << RCC_APB2ENR_IOPDEN_Pos)  /*!< 0x00000020 */
1262 #define RCC_APB2ENR_IOPDEN                   RCC_APB2ENR_IOPDEN_Msk            /*!< I/O port D clock enable */
1263 #define RCC_APB2ENR_ADC1EN_Pos               (9U)
1264 #define RCC_APB2ENR_ADC1EN_Msk               (0x1UL << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */
1265 #define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */
1266 
1267 #define RCC_APB2ENR_ADC2EN_Pos               (10U)
1268 #define RCC_APB2ENR_ADC2EN_Msk               (0x1UL << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */
1269 #define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */
1270 
1271 #define RCC_APB2ENR_TIM1EN_Pos               (11U)
1272 #define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
1273 #define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            /*!< TIM1 Timer clock enable */
1274 #define RCC_APB2ENR_SPI1EN_Pos               (12U)
1275 #define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
1276 #define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            /*!< SPI 1 clock enable */
1277 #define RCC_APB2ENR_USART1EN_Pos             (14U)
1278 #define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1279 #define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          /*!< USART1 clock enable */
1280 
1281 
1282 
1283 
1284 
1285 
1286 /*****************  Bit definition for RCC_APB1ENR register  ******************/
1287 #define RCC_APB1ENR_TIM2EN_Pos               (0U)
1288 #define RCC_APB1ENR_TIM2EN_Msk               (0x1UL << RCC_APB1ENR_TIM2EN_Pos)  /*!< 0x00000001 */
1289 #define RCC_APB1ENR_TIM2EN                   RCC_APB1ENR_TIM2EN_Msk            /*!< Timer 2 clock enabled*/
1290 #define RCC_APB1ENR_TIM3EN_Pos               (1U)
1291 #define RCC_APB1ENR_TIM3EN_Msk               (0x1UL << RCC_APB1ENR_TIM3EN_Pos)  /*!< 0x00000002 */
1292 #define RCC_APB1ENR_TIM3EN                   RCC_APB1ENR_TIM3EN_Msk            /*!< Timer 3 clock enable */
1293 #define RCC_APB1ENR_WWDGEN_Pos               (11U)
1294 #define RCC_APB1ENR_WWDGEN_Msk               (0x1UL << RCC_APB1ENR_WWDGEN_Pos)  /*!< 0x00000800 */
1295 #define RCC_APB1ENR_WWDGEN                   RCC_APB1ENR_WWDGEN_Msk            /*!< Window Watchdog clock enable */
1296 #define RCC_APB1ENR_USART2EN_Pos             (17U)
1297 #define RCC_APB1ENR_USART2EN_Msk             (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1298 #define RCC_APB1ENR_USART2EN                 RCC_APB1ENR_USART2EN_Msk          /*!< USART 2 clock enable */
1299 #define RCC_APB1ENR_I2C1EN_Pos               (21U)
1300 #define RCC_APB1ENR_I2C1EN_Msk               (0x1UL << RCC_APB1ENR_I2C1EN_Pos)  /*!< 0x00200000 */
1301 #define RCC_APB1ENR_I2C1EN                   RCC_APB1ENR_I2C1EN_Msk            /*!< I2C 1 clock enable */
1302 
1303 #define RCC_APB1ENR_CAN1EN_Pos               (25U)
1304 #define RCC_APB1ENR_CAN1EN_Msk               (0x1UL << RCC_APB1ENR_CAN1EN_Pos)  /*!< 0x02000000 */
1305 #define RCC_APB1ENR_CAN1EN                   RCC_APB1ENR_CAN1EN_Msk            /*!< CAN1 clock enable */
1306 
1307 #define RCC_APB1ENR_BKPEN_Pos                (27U)
1308 #define RCC_APB1ENR_BKPEN_Msk                (0x1UL << RCC_APB1ENR_BKPEN_Pos)   /*!< 0x08000000 */
1309 #define RCC_APB1ENR_BKPEN                    RCC_APB1ENR_BKPEN_Msk             /*!< Backup interface clock enable */
1310 #define RCC_APB1ENR_PWREN_Pos                (28U)
1311 #define RCC_APB1ENR_PWREN_Msk                (0x1UL << RCC_APB1ENR_PWREN_Pos)   /*!< 0x10000000 */
1312 #define RCC_APB1ENR_PWREN                    RCC_APB1ENR_PWREN_Msk             /*!< Power interface clock enable */
1313 
1314 
1315 #define RCC_APB1ENR_USBEN_Pos                (23U)
1316 #define RCC_APB1ENR_USBEN_Msk                (0x1UL << RCC_APB1ENR_USBEN_Pos)   /*!< 0x00800000 */
1317 #define RCC_APB1ENR_USBEN                    RCC_APB1ENR_USBEN_Msk             /*!< USB Device clock enable */
1318 
1319 
1320 
1321 
1322 
1323 
1324 /*******************  Bit definition for RCC_BDCR register  *******************/
1325 #define RCC_BDCR_LSEON_Pos                   (0U)
1326 #define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
1327 #define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                /*!< External Low Speed oscillator enable */
1328 #define RCC_BDCR_LSERDY_Pos                  (1U)
1329 #define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
1330 #define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               /*!< External Low Speed oscillator Ready */
1331 #define RCC_BDCR_LSEBYP_Pos                  (2U)
1332 #define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
1333 #define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               /*!< External Low Speed oscillator Bypass */
1334 
1335 #define RCC_BDCR_RTCSEL_Pos                  (8U)
1336 #define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
1337 #define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1338 #define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
1339 #define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
1340 
1341 /*!< RTC configuration */
1342 #define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */
1343 #define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */
1344 #define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */
1345 #define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */
1346 
1347 #define RCC_BDCR_RTCEN_Pos                   (15U)
1348 #define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
1349 #define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                /*!< RTC clock enable */
1350 #define RCC_BDCR_BDRST_Pos                   (16U)
1351 #define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
1352 #define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                /*!< Backup domain software reset  */
1353 
1354 /*******************  Bit definition for RCC_CSR register  ********************/
1355 #define RCC_CSR_LSION_Pos                    (0U)
1356 #define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */
1357 #define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 /*!< Internal Low Speed oscillator enable */
1358 #define RCC_CSR_LSIRDY_Pos                   (1U)
1359 #define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */
1360 #define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                /*!< Internal Low Speed oscillator Ready */
1361 #define RCC_CSR_RMVF_Pos                     (24U)
1362 #define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x01000000 */
1363 #define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  /*!< Remove reset flag */
1364 #define RCC_CSR_PINRSTF_Pos                  (26U)
1365 #define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
1366 #define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               /*!< PIN reset flag */
1367 #define RCC_CSR_PORRSTF_Pos                  (27U)
1368 #define RCC_CSR_PORRSTF_Msk                  (0x1UL << RCC_CSR_PORRSTF_Pos)     /*!< 0x08000000 */
1369 #define RCC_CSR_PORRSTF                      RCC_CSR_PORRSTF_Msk               /*!< POR/PDR reset flag */
1370 #define RCC_CSR_SFTRSTF_Pos                  (28U)
1371 #define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
1372 #define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               /*!< Software Reset flag */
1373 #define RCC_CSR_IWDGRSTF_Pos                 (29U)
1374 #define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
1375 #define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              /*!< Independent Watchdog reset flag */
1376 #define RCC_CSR_WWDGRSTF_Pos                 (30U)
1377 #define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
1378 #define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              /*!< Window watchdog reset flag */
1379 #define RCC_CSR_LPWRRSTF_Pos                 (31U)
1380 #define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
1381 #define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              /*!< Low-Power reset flag */
1382 
1383 
1384 
1385 /******************************************************************************/
1386 /*                                                                            */
1387 /*                General Purpose and Alternate Function I/O                  */
1388 /*                                                                            */
1389 /******************************************************************************/
1390 
1391 /*******************  Bit definition for GPIO_CRL register  *******************/
1392 #define GPIO_CRL_MODE_Pos                    (0U)
1393 #define GPIO_CRL_MODE_Msk                    (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1394 #define GPIO_CRL_MODE                        GPIO_CRL_MODE_Msk                 /*!< Port x mode bits */
1395 
1396 #define GPIO_CRL_MODE0_Pos                   (0U)
1397 #define GPIO_CRL_MODE0_Msk                   (0x3UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000003 */
1398 #define GPIO_CRL_MODE0                       GPIO_CRL_MODE0_Msk                /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1399 #define GPIO_CRL_MODE0_0                     (0x1UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000001 */
1400 #define GPIO_CRL_MODE0_1                     (0x2UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000002 */
1401 
1402 #define GPIO_CRL_MODE1_Pos                   (4U)
1403 #define GPIO_CRL_MODE1_Msk                   (0x3UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000030 */
1404 #define GPIO_CRL_MODE1                       GPIO_CRL_MODE1_Msk                /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1405 #define GPIO_CRL_MODE1_0                     (0x1UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000010 */
1406 #define GPIO_CRL_MODE1_1                     (0x2UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000020 */
1407 
1408 #define GPIO_CRL_MODE2_Pos                   (8U)
1409 #define GPIO_CRL_MODE2_Msk                   (0x3UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000300 */
1410 #define GPIO_CRL_MODE2                       GPIO_CRL_MODE2_Msk                /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1411 #define GPIO_CRL_MODE2_0                     (0x1UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000100 */
1412 #define GPIO_CRL_MODE2_1                     (0x2UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000200 */
1413 
1414 #define GPIO_CRL_MODE3_Pos                   (12U)
1415 #define GPIO_CRL_MODE3_Msk                   (0x3UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00003000 */
1416 #define GPIO_CRL_MODE3                       GPIO_CRL_MODE3_Msk                /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1417 #define GPIO_CRL_MODE3_0                     (0x1UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00001000 */
1418 #define GPIO_CRL_MODE3_1                     (0x2UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00002000 */
1419 
1420 #define GPIO_CRL_MODE4_Pos                   (16U)
1421 #define GPIO_CRL_MODE4_Msk                   (0x3UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00030000 */
1422 #define GPIO_CRL_MODE4                       GPIO_CRL_MODE4_Msk                /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1423 #define GPIO_CRL_MODE4_0                     (0x1UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00010000 */
1424 #define GPIO_CRL_MODE4_1                     (0x2UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00020000 */
1425 
1426 #define GPIO_CRL_MODE5_Pos                   (20U)
1427 #define GPIO_CRL_MODE5_Msk                   (0x3UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00300000 */
1428 #define GPIO_CRL_MODE5                       GPIO_CRL_MODE5_Msk                /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1429 #define GPIO_CRL_MODE5_0                     (0x1UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00100000 */
1430 #define GPIO_CRL_MODE5_1                     (0x2UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00200000 */
1431 
1432 #define GPIO_CRL_MODE6_Pos                   (24U)
1433 #define GPIO_CRL_MODE6_Msk                   (0x3UL << GPIO_CRL_MODE6_Pos)      /*!< 0x03000000 */
1434 #define GPIO_CRL_MODE6                       GPIO_CRL_MODE6_Msk                /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1435 #define GPIO_CRL_MODE6_0                     (0x1UL << GPIO_CRL_MODE6_Pos)      /*!< 0x01000000 */
1436 #define GPIO_CRL_MODE6_1                     (0x2UL << GPIO_CRL_MODE6_Pos)      /*!< 0x02000000 */
1437 
1438 #define GPIO_CRL_MODE7_Pos                   (28U)
1439 #define GPIO_CRL_MODE7_Msk                   (0x3UL << GPIO_CRL_MODE7_Pos)      /*!< 0x30000000 */
1440 #define GPIO_CRL_MODE7                       GPIO_CRL_MODE7_Msk                /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1441 #define GPIO_CRL_MODE7_0                     (0x1UL << GPIO_CRL_MODE7_Pos)      /*!< 0x10000000 */
1442 #define GPIO_CRL_MODE7_1                     (0x2UL << GPIO_CRL_MODE7_Pos)      /*!< 0x20000000 */
1443 
1444 #define GPIO_CRL_CNF_Pos                     (2U)
1445 #define GPIO_CRL_CNF_Msk                     (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1446 #define GPIO_CRL_CNF                         GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */
1447 
1448 #define GPIO_CRL_CNF0_Pos                    (2U)
1449 #define GPIO_CRL_CNF0_Msk                    (0x3UL << GPIO_CRL_CNF0_Pos)       /*!< 0x0000000C */
1450 #define GPIO_CRL_CNF0                        GPIO_CRL_CNF0_Msk                 /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1451 #define GPIO_CRL_CNF0_0                      (0x1UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000004 */
1452 #define GPIO_CRL_CNF0_1                      (0x2UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000008 */
1453 
1454 #define GPIO_CRL_CNF1_Pos                    (6U)
1455 #define GPIO_CRL_CNF1_Msk                    (0x3UL << GPIO_CRL_CNF1_Pos)       /*!< 0x000000C0 */
1456 #define GPIO_CRL_CNF1                        GPIO_CRL_CNF1_Msk                 /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1457 #define GPIO_CRL_CNF1_0                      (0x1UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000040 */
1458 #define GPIO_CRL_CNF1_1                      (0x2UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000080 */
1459 
1460 #define GPIO_CRL_CNF2_Pos                    (10U)
1461 #define GPIO_CRL_CNF2_Msk                    (0x3UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000C00 */
1462 #define GPIO_CRL_CNF2                        GPIO_CRL_CNF2_Msk                 /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1463 #define GPIO_CRL_CNF2_0                      (0x1UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000400 */
1464 #define GPIO_CRL_CNF2_1                      (0x2UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000800 */
1465 
1466 #define GPIO_CRL_CNF3_Pos                    (14U)
1467 #define GPIO_CRL_CNF3_Msk                    (0x3UL << GPIO_CRL_CNF3_Pos)       /*!< 0x0000C000 */
1468 #define GPIO_CRL_CNF3                        GPIO_CRL_CNF3_Msk                 /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1469 #define GPIO_CRL_CNF3_0                      (0x1UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00004000 */
1470 #define GPIO_CRL_CNF3_1                      (0x2UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00008000 */
1471 
1472 #define GPIO_CRL_CNF4_Pos                    (18U)
1473 #define GPIO_CRL_CNF4_Msk                    (0x3UL << GPIO_CRL_CNF4_Pos)       /*!< 0x000C0000 */
1474 #define GPIO_CRL_CNF4                        GPIO_CRL_CNF4_Msk                 /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1475 #define GPIO_CRL_CNF4_0                      (0x1UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00040000 */
1476 #define GPIO_CRL_CNF4_1                      (0x2UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00080000 */
1477 
1478 #define GPIO_CRL_CNF5_Pos                    (22U)
1479 #define GPIO_CRL_CNF5_Msk                    (0x3UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00C00000 */
1480 #define GPIO_CRL_CNF5                        GPIO_CRL_CNF5_Msk                 /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1481 #define GPIO_CRL_CNF5_0                      (0x1UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00400000 */
1482 #define GPIO_CRL_CNF5_1                      (0x2UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00800000 */
1483 
1484 #define GPIO_CRL_CNF6_Pos                    (26U)
1485 #define GPIO_CRL_CNF6_Msk                    (0x3UL << GPIO_CRL_CNF6_Pos)       /*!< 0x0C000000 */
1486 #define GPIO_CRL_CNF6                        GPIO_CRL_CNF6_Msk                 /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1487 #define GPIO_CRL_CNF6_0                      (0x1UL << GPIO_CRL_CNF6_Pos)       /*!< 0x04000000 */
1488 #define GPIO_CRL_CNF6_1                      (0x2UL << GPIO_CRL_CNF6_Pos)       /*!< 0x08000000 */
1489 
1490 #define GPIO_CRL_CNF7_Pos                    (30U)
1491 #define GPIO_CRL_CNF7_Msk                    (0x3UL << GPIO_CRL_CNF7_Pos)       /*!< 0xC0000000 */
1492 #define GPIO_CRL_CNF7                        GPIO_CRL_CNF7_Msk                 /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1493 #define GPIO_CRL_CNF7_0                      (0x1UL << GPIO_CRL_CNF7_Pos)       /*!< 0x40000000 */
1494 #define GPIO_CRL_CNF7_1                      (0x2UL << GPIO_CRL_CNF7_Pos)       /*!< 0x80000000 */
1495 
1496 /*******************  Bit definition for GPIO_CRH register  *******************/
1497 #define GPIO_CRH_MODE_Pos                    (0U)
1498 #define GPIO_CRH_MODE_Msk                    (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
1499 #define GPIO_CRH_MODE                        GPIO_CRH_MODE_Msk                 /*!< Port x mode bits */
1500 
1501 #define GPIO_CRH_MODE8_Pos                   (0U)
1502 #define GPIO_CRH_MODE8_Msk                   (0x3UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000003 */
1503 #define GPIO_CRH_MODE8                       GPIO_CRH_MODE8_Msk                /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1504 #define GPIO_CRH_MODE8_0                     (0x1UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000001 */
1505 #define GPIO_CRH_MODE8_1                     (0x2UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000002 */
1506 
1507 #define GPIO_CRH_MODE9_Pos                   (4U)
1508 #define GPIO_CRH_MODE9_Msk                   (0x3UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000030 */
1509 #define GPIO_CRH_MODE9                       GPIO_CRH_MODE9_Msk                /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1510 #define GPIO_CRH_MODE9_0                     (0x1UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000010 */
1511 #define GPIO_CRH_MODE9_1                     (0x2UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000020 */
1512 
1513 #define GPIO_CRH_MODE10_Pos                  (8U)
1514 #define GPIO_CRH_MODE10_Msk                  (0x3UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000300 */
1515 #define GPIO_CRH_MODE10                      GPIO_CRH_MODE10_Msk               /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1516 #define GPIO_CRH_MODE10_0                    (0x1UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000100 */
1517 #define GPIO_CRH_MODE10_1                    (0x2UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000200 */
1518 
1519 #define GPIO_CRH_MODE11_Pos                  (12U)
1520 #define GPIO_CRH_MODE11_Msk                  (0x3UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00003000 */
1521 #define GPIO_CRH_MODE11                      GPIO_CRH_MODE11_Msk               /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
1522 #define GPIO_CRH_MODE11_0                    (0x1UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00001000 */
1523 #define GPIO_CRH_MODE11_1                    (0x2UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00002000 */
1524 
1525 #define GPIO_CRH_MODE12_Pos                  (16U)
1526 #define GPIO_CRH_MODE12_Msk                  (0x3UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00030000 */
1527 #define GPIO_CRH_MODE12                      GPIO_CRH_MODE12_Msk               /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
1528 #define GPIO_CRH_MODE12_0                    (0x1UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00010000 */
1529 #define GPIO_CRH_MODE12_1                    (0x2UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00020000 */
1530 
1531 #define GPIO_CRH_MODE13_Pos                  (20U)
1532 #define GPIO_CRH_MODE13_Msk                  (0x3UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00300000 */
1533 #define GPIO_CRH_MODE13                      GPIO_CRH_MODE13_Msk               /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
1534 #define GPIO_CRH_MODE13_0                    (0x1UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00100000 */
1535 #define GPIO_CRH_MODE13_1                    (0x2UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00200000 */
1536 
1537 #define GPIO_CRH_MODE14_Pos                  (24U)
1538 #define GPIO_CRH_MODE14_Msk                  (0x3UL << GPIO_CRH_MODE14_Pos)     /*!< 0x03000000 */
1539 #define GPIO_CRH_MODE14                      GPIO_CRH_MODE14_Msk               /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
1540 #define GPIO_CRH_MODE14_0                    (0x1UL << GPIO_CRH_MODE14_Pos)     /*!< 0x01000000 */
1541 #define GPIO_CRH_MODE14_1                    (0x2UL << GPIO_CRH_MODE14_Pos)     /*!< 0x02000000 */
1542 
1543 #define GPIO_CRH_MODE15_Pos                  (28U)
1544 #define GPIO_CRH_MODE15_Msk                  (0x3UL << GPIO_CRH_MODE15_Pos)     /*!< 0x30000000 */
1545 #define GPIO_CRH_MODE15                      GPIO_CRH_MODE15_Msk               /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
1546 #define GPIO_CRH_MODE15_0                    (0x1UL << GPIO_CRH_MODE15_Pos)     /*!< 0x10000000 */
1547 #define GPIO_CRH_MODE15_1                    (0x2UL << GPIO_CRH_MODE15_Pos)     /*!< 0x20000000 */
1548 
1549 #define GPIO_CRH_CNF_Pos                     (2U)
1550 #define GPIO_CRH_CNF_Msk                     (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
1551 #define GPIO_CRH_CNF                         GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */
1552 
1553 #define GPIO_CRH_CNF8_Pos                    (2U)
1554 #define GPIO_CRH_CNF8_Msk                    (0x3UL << GPIO_CRH_CNF8_Pos)       /*!< 0x0000000C */
1555 #define GPIO_CRH_CNF8                        GPIO_CRH_CNF8_Msk                 /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
1556 #define GPIO_CRH_CNF8_0                      (0x1UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000004 */
1557 #define GPIO_CRH_CNF8_1                      (0x2UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000008 */
1558 
1559 #define GPIO_CRH_CNF9_Pos                    (6U)
1560 #define GPIO_CRH_CNF9_Msk                    (0x3UL << GPIO_CRH_CNF9_Pos)       /*!< 0x000000C0 */
1561 #define GPIO_CRH_CNF9                        GPIO_CRH_CNF9_Msk                 /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
1562 #define GPIO_CRH_CNF9_0                      (0x1UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000040 */
1563 #define GPIO_CRH_CNF9_1                      (0x2UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000080 */
1564 
1565 #define GPIO_CRH_CNF10_Pos                   (10U)
1566 #define GPIO_CRH_CNF10_Msk                   (0x3UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000C00 */
1567 #define GPIO_CRH_CNF10                       GPIO_CRH_CNF10_Msk                /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
1568 #define GPIO_CRH_CNF10_0                     (0x1UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000400 */
1569 #define GPIO_CRH_CNF10_1                     (0x2UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000800 */
1570 
1571 #define GPIO_CRH_CNF11_Pos                   (14U)
1572 #define GPIO_CRH_CNF11_Msk                   (0x3UL << GPIO_CRH_CNF11_Pos)      /*!< 0x0000C000 */
1573 #define GPIO_CRH_CNF11                       GPIO_CRH_CNF11_Msk                /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
1574 #define GPIO_CRH_CNF11_0                     (0x1UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00004000 */
1575 #define GPIO_CRH_CNF11_1                     (0x2UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00008000 */
1576 
1577 #define GPIO_CRH_CNF12_Pos                   (18U)
1578 #define GPIO_CRH_CNF12_Msk                   (0x3UL << GPIO_CRH_CNF12_Pos)      /*!< 0x000C0000 */
1579 #define GPIO_CRH_CNF12                       GPIO_CRH_CNF12_Msk                /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
1580 #define GPIO_CRH_CNF12_0                     (0x1UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00040000 */
1581 #define GPIO_CRH_CNF12_1                     (0x2UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00080000 */
1582 
1583 #define GPIO_CRH_CNF13_Pos                   (22U)
1584 #define GPIO_CRH_CNF13_Msk                   (0x3UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00C00000 */
1585 #define GPIO_CRH_CNF13                       GPIO_CRH_CNF13_Msk                /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
1586 #define GPIO_CRH_CNF13_0                     (0x1UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00400000 */
1587 #define GPIO_CRH_CNF13_1                     (0x2UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00800000 */
1588 
1589 #define GPIO_CRH_CNF14_Pos                   (26U)
1590 #define GPIO_CRH_CNF14_Msk                   (0x3UL << GPIO_CRH_CNF14_Pos)      /*!< 0x0C000000 */
1591 #define GPIO_CRH_CNF14                       GPIO_CRH_CNF14_Msk                /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
1592 #define GPIO_CRH_CNF14_0                     (0x1UL << GPIO_CRH_CNF14_Pos)      /*!< 0x04000000 */
1593 #define GPIO_CRH_CNF14_1                     (0x2UL << GPIO_CRH_CNF14_Pos)      /*!< 0x08000000 */
1594 
1595 #define GPIO_CRH_CNF15_Pos                   (30U)
1596 #define GPIO_CRH_CNF15_Msk                   (0x3UL << GPIO_CRH_CNF15_Pos)      /*!< 0xC0000000 */
1597 #define GPIO_CRH_CNF15                       GPIO_CRH_CNF15_Msk                /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
1598 #define GPIO_CRH_CNF15_0                     (0x1UL << GPIO_CRH_CNF15_Pos)      /*!< 0x40000000 */
1599 #define GPIO_CRH_CNF15_1                     (0x2UL << GPIO_CRH_CNF15_Pos)      /*!< 0x80000000 */
1600 
1601 /*!<******************  Bit definition for GPIO_IDR register  *******************/
1602 #define GPIO_IDR_IDR0_Pos                    (0U)
1603 #define GPIO_IDR_IDR0_Msk                    (0x1UL << GPIO_IDR_IDR0_Pos)       /*!< 0x00000001 */
1604 #define GPIO_IDR_IDR0                        GPIO_IDR_IDR0_Msk                 /*!< Port input data, bit 0 */
1605 #define GPIO_IDR_IDR1_Pos                    (1U)
1606 #define GPIO_IDR_IDR1_Msk                    (0x1UL << GPIO_IDR_IDR1_Pos)       /*!< 0x00000002 */
1607 #define GPIO_IDR_IDR1                        GPIO_IDR_IDR1_Msk                 /*!< Port input data, bit 1 */
1608 #define GPIO_IDR_IDR2_Pos                    (2U)
1609 #define GPIO_IDR_IDR2_Msk                    (0x1UL << GPIO_IDR_IDR2_Pos)       /*!< 0x00000004 */
1610 #define GPIO_IDR_IDR2                        GPIO_IDR_IDR2_Msk                 /*!< Port input data, bit 2 */
1611 #define GPIO_IDR_IDR3_Pos                    (3U)
1612 #define GPIO_IDR_IDR3_Msk                    (0x1UL << GPIO_IDR_IDR3_Pos)       /*!< 0x00000008 */
1613 #define GPIO_IDR_IDR3                        GPIO_IDR_IDR3_Msk                 /*!< Port input data, bit 3 */
1614 #define GPIO_IDR_IDR4_Pos                    (4U)
1615 #define GPIO_IDR_IDR4_Msk                    (0x1UL << GPIO_IDR_IDR4_Pos)       /*!< 0x00000010 */
1616 #define GPIO_IDR_IDR4                        GPIO_IDR_IDR4_Msk                 /*!< Port input data, bit 4 */
1617 #define GPIO_IDR_IDR5_Pos                    (5U)
1618 #define GPIO_IDR_IDR5_Msk                    (0x1UL << GPIO_IDR_IDR5_Pos)       /*!< 0x00000020 */
1619 #define GPIO_IDR_IDR5                        GPIO_IDR_IDR5_Msk                 /*!< Port input data, bit 5 */
1620 #define GPIO_IDR_IDR6_Pos                    (6U)
1621 #define GPIO_IDR_IDR6_Msk                    (0x1UL << GPIO_IDR_IDR6_Pos)       /*!< 0x00000040 */
1622 #define GPIO_IDR_IDR6                        GPIO_IDR_IDR6_Msk                 /*!< Port input data, bit 6 */
1623 #define GPIO_IDR_IDR7_Pos                    (7U)
1624 #define GPIO_IDR_IDR7_Msk                    (0x1UL << GPIO_IDR_IDR7_Pos)       /*!< 0x00000080 */
1625 #define GPIO_IDR_IDR7                        GPIO_IDR_IDR7_Msk                 /*!< Port input data, bit 7 */
1626 #define GPIO_IDR_IDR8_Pos                    (8U)
1627 #define GPIO_IDR_IDR8_Msk                    (0x1UL << GPIO_IDR_IDR8_Pos)       /*!< 0x00000100 */
1628 #define GPIO_IDR_IDR8                        GPIO_IDR_IDR8_Msk                 /*!< Port input data, bit 8 */
1629 #define GPIO_IDR_IDR9_Pos                    (9U)
1630 #define GPIO_IDR_IDR9_Msk                    (0x1UL << GPIO_IDR_IDR9_Pos)       /*!< 0x00000200 */
1631 #define GPIO_IDR_IDR9                        GPIO_IDR_IDR9_Msk                 /*!< Port input data, bit 9 */
1632 #define GPIO_IDR_IDR10_Pos                   (10U)
1633 #define GPIO_IDR_IDR10_Msk                   (0x1UL << GPIO_IDR_IDR10_Pos)      /*!< 0x00000400 */
1634 #define GPIO_IDR_IDR10                       GPIO_IDR_IDR10_Msk                /*!< Port input data, bit 10 */
1635 #define GPIO_IDR_IDR11_Pos                   (11U)
1636 #define GPIO_IDR_IDR11_Msk                   (0x1UL << GPIO_IDR_IDR11_Pos)      /*!< 0x00000800 */
1637 #define GPIO_IDR_IDR11                       GPIO_IDR_IDR11_Msk                /*!< Port input data, bit 11 */
1638 #define GPIO_IDR_IDR12_Pos                   (12U)
1639 #define GPIO_IDR_IDR12_Msk                   (0x1UL << GPIO_IDR_IDR12_Pos)      /*!< 0x00001000 */
1640 #define GPIO_IDR_IDR12                       GPIO_IDR_IDR12_Msk                /*!< Port input data, bit 12 */
1641 #define GPIO_IDR_IDR13_Pos                   (13U)
1642 #define GPIO_IDR_IDR13_Msk                   (0x1UL << GPIO_IDR_IDR13_Pos)      /*!< 0x00002000 */
1643 #define GPIO_IDR_IDR13                       GPIO_IDR_IDR13_Msk                /*!< Port input data, bit 13 */
1644 #define GPIO_IDR_IDR14_Pos                   (14U)
1645 #define GPIO_IDR_IDR14_Msk                   (0x1UL << GPIO_IDR_IDR14_Pos)      /*!< 0x00004000 */
1646 #define GPIO_IDR_IDR14                       GPIO_IDR_IDR14_Msk                /*!< Port input data, bit 14 */
1647 #define GPIO_IDR_IDR15_Pos                   (15U)
1648 #define GPIO_IDR_IDR15_Msk                   (0x1UL << GPIO_IDR_IDR15_Pos)      /*!< 0x00008000 */
1649 #define GPIO_IDR_IDR15                       GPIO_IDR_IDR15_Msk                /*!< Port input data, bit 15 */
1650 
1651 /*******************  Bit definition for GPIO_ODR register  *******************/
1652 #define GPIO_ODR_ODR0_Pos                    (0U)
1653 #define GPIO_ODR_ODR0_Msk                    (0x1UL << GPIO_ODR_ODR0_Pos)       /*!< 0x00000001 */
1654 #define GPIO_ODR_ODR0                        GPIO_ODR_ODR0_Msk                 /*!< Port output data, bit 0 */
1655 #define GPIO_ODR_ODR1_Pos                    (1U)
1656 #define GPIO_ODR_ODR1_Msk                    (0x1UL << GPIO_ODR_ODR1_Pos)       /*!< 0x00000002 */
1657 #define GPIO_ODR_ODR1                        GPIO_ODR_ODR1_Msk                 /*!< Port output data, bit 1 */
1658 #define GPIO_ODR_ODR2_Pos                    (2U)
1659 #define GPIO_ODR_ODR2_Msk                    (0x1UL << GPIO_ODR_ODR2_Pos)       /*!< 0x00000004 */
1660 #define GPIO_ODR_ODR2                        GPIO_ODR_ODR2_Msk                 /*!< Port output data, bit 2 */
1661 #define GPIO_ODR_ODR3_Pos                    (3U)
1662 #define GPIO_ODR_ODR3_Msk                    (0x1UL << GPIO_ODR_ODR3_Pos)       /*!< 0x00000008 */
1663 #define GPIO_ODR_ODR3                        GPIO_ODR_ODR3_Msk                 /*!< Port output data, bit 3 */
1664 #define GPIO_ODR_ODR4_Pos                    (4U)
1665 #define GPIO_ODR_ODR4_Msk                    (0x1UL << GPIO_ODR_ODR4_Pos)       /*!< 0x00000010 */
1666 #define GPIO_ODR_ODR4                        GPIO_ODR_ODR4_Msk                 /*!< Port output data, bit 4 */
1667 #define GPIO_ODR_ODR5_Pos                    (5U)
1668 #define GPIO_ODR_ODR5_Msk                    (0x1UL << GPIO_ODR_ODR5_Pos)       /*!< 0x00000020 */
1669 #define GPIO_ODR_ODR5                        GPIO_ODR_ODR5_Msk                 /*!< Port output data, bit 5 */
1670 #define GPIO_ODR_ODR6_Pos                    (6U)
1671 #define GPIO_ODR_ODR6_Msk                    (0x1UL << GPIO_ODR_ODR6_Pos)       /*!< 0x00000040 */
1672 #define GPIO_ODR_ODR6                        GPIO_ODR_ODR6_Msk                 /*!< Port output data, bit 6 */
1673 #define GPIO_ODR_ODR7_Pos                    (7U)
1674 #define GPIO_ODR_ODR7_Msk                    (0x1UL << GPIO_ODR_ODR7_Pos)       /*!< 0x00000080 */
1675 #define GPIO_ODR_ODR7                        GPIO_ODR_ODR7_Msk                 /*!< Port output data, bit 7 */
1676 #define GPIO_ODR_ODR8_Pos                    (8U)
1677 #define GPIO_ODR_ODR8_Msk                    (0x1UL << GPIO_ODR_ODR8_Pos)       /*!< 0x00000100 */
1678 #define GPIO_ODR_ODR8                        GPIO_ODR_ODR8_Msk                 /*!< Port output data, bit 8 */
1679 #define GPIO_ODR_ODR9_Pos                    (9U)
1680 #define GPIO_ODR_ODR9_Msk                    (0x1UL << GPIO_ODR_ODR9_Pos)       /*!< 0x00000200 */
1681 #define GPIO_ODR_ODR9                        GPIO_ODR_ODR9_Msk                 /*!< Port output data, bit 9 */
1682 #define GPIO_ODR_ODR10_Pos                   (10U)
1683 #define GPIO_ODR_ODR10_Msk                   (0x1UL << GPIO_ODR_ODR10_Pos)      /*!< 0x00000400 */
1684 #define GPIO_ODR_ODR10                       GPIO_ODR_ODR10_Msk                /*!< Port output data, bit 10 */
1685 #define GPIO_ODR_ODR11_Pos                   (11U)
1686 #define GPIO_ODR_ODR11_Msk                   (0x1UL << GPIO_ODR_ODR11_Pos)      /*!< 0x00000800 */
1687 #define GPIO_ODR_ODR11                       GPIO_ODR_ODR11_Msk                /*!< Port output data, bit 11 */
1688 #define GPIO_ODR_ODR12_Pos                   (12U)
1689 #define GPIO_ODR_ODR12_Msk                   (0x1UL << GPIO_ODR_ODR12_Pos)      /*!< 0x00001000 */
1690 #define GPIO_ODR_ODR12                       GPIO_ODR_ODR12_Msk                /*!< Port output data, bit 12 */
1691 #define GPIO_ODR_ODR13_Pos                   (13U)
1692 #define GPIO_ODR_ODR13_Msk                   (0x1UL << GPIO_ODR_ODR13_Pos)      /*!< 0x00002000 */
1693 #define GPIO_ODR_ODR13                       GPIO_ODR_ODR13_Msk                /*!< Port output data, bit 13 */
1694 #define GPIO_ODR_ODR14_Pos                   (14U)
1695 #define GPIO_ODR_ODR14_Msk                   (0x1UL << GPIO_ODR_ODR14_Pos)      /*!< 0x00004000 */
1696 #define GPIO_ODR_ODR14                       GPIO_ODR_ODR14_Msk                /*!< Port output data, bit 14 */
1697 #define GPIO_ODR_ODR15_Pos                   (15U)
1698 #define GPIO_ODR_ODR15_Msk                   (0x1UL << GPIO_ODR_ODR15_Pos)      /*!< 0x00008000 */
1699 #define GPIO_ODR_ODR15                       GPIO_ODR_ODR15_Msk                /*!< Port output data, bit 15 */
1700 
1701 /******************  Bit definition for GPIO_BSRR register  *******************/
1702 #define GPIO_BSRR_BS0_Pos                    (0U)
1703 #define GPIO_BSRR_BS0_Msk                    (0x1UL << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */
1704 #define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 /*!< Port x Set bit 0 */
1705 #define GPIO_BSRR_BS1_Pos                    (1U)
1706 #define GPIO_BSRR_BS1_Msk                    (0x1UL << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */
1707 #define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 /*!< Port x Set bit 1 */
1708 #define GPIO_BSRR_BS2_Pos                    (2U)
1709 #define GPIO_BSRR_BS2_Msk                    (0x1UL << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */
1710 #define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 /*!< Port x Set bit 2 */
1711 #define GPIO_BSRR_BS3_Pos                    (3U)
1712 #define GPIO_BSRR_BS3_Msk                    (0x1UL << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */
1713 #define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 /*!< Port x Set bit 3 */
1714 #define GPIO_BSRR_BS4_Pos                    (4U)
1715 #define GPIO_BSRR_BS4_Msk                    (0x1UL << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */
1716 #define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 /*!< Port x Set bit 4 */
1717 #define GPIO_BSRR_BS5_Pos                    (5U)
1718 #define GPIO_BSRR_BS5_Msk                    (0x1UL << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */
1719 #define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 /*!< Port x Set bit 5 */
1720 #define GPIO_BSRR_BS6_Pos                    (6U)
1721 #define GPIO_BSRR_BS6_Msk                    (0x1UL << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */
1722 #define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 /*!< Port x Set bit 6 */
1723 #define GPIO_BSRR_BS7_Pos                    (7U)
1724 #define GPIO_BSRR_BS7_Msk                    (0x1UL << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */
1725 #define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 /*!< Port x Set bit 7 */
1726 #define GPIO_BSRR_BS8_Pos                    (8U)
1727 #define GPIO_BSRR_BS8_Msk                    (0x1UL << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */
1728 #define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 /*!< Port x Set bit 8 */
1729 #define GPIO_BSRR_BS9_Pos                    (9U)
1730 #define GPIO_BSRR_BS9_Msk                    (0x1UL << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */
1731 #define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 /*!< Port x Set bit 9 */
1732 #define GPIO_BSRR_BS10_Pos                   (10U)
1733 #define GPIO_BSRR_BS10_Msk                   (0x1UL << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */
1734 #define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                /*!< Port x Set bit 10 */
1735 #define GPIO_BSRR_BS11_Pos                   (11U)
1736 #define GPIO_BSRR_BS11_Msk                   (0x1UL << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */
1737 #define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                /*!< Port x Set bit 11 */
1738 #define GPIO_BSRR_BS12_Pos                   (12U)
1739 #define GPIO_BSRR_BS12_Msk                   (0x1UL << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */
1740 #define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                /*!< Port x Set bit 12 */
1741 #define GPIO_BSRR_BS13_Pos                   (13U)
1742 #define GPIO_BSRR_BS13_Msk                   (0x1UL << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */
1743 #define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                /*!< Port x Set bit 13 */
1744 #define GPIO_BSRR_BS14_Pos                   (14U)
1745 #define GPIO_BSRR_BS14_Msk                   (0x1UL << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */
1746 #define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                /*!< Port x Set bit 14 */
1747 #define GPIO_BSRR_BS15_Pos                   (15U)
1748 #define GPIO_BSRR_BS15_Msk                   (0x1UL << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */
1749 #define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                /*!< Port x Set bit 15 */
1750 
1751 #define GPIO_BSRR_BR0_Pos                    (16U)
1752 #define GPIO_BSRR_BR0_Msk                    (0x1UL << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */
1753 #define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 /*!< Port x Reset bit 0 */
1754 #define GPIO_BSRR_BR1_Pos                    (17U)
1755 #define GPIO_BSRR_BR1_Msk                    (0x1UL << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */
1756 #define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 /*!< Port x Reset bit 1 */
1757 #define GPIO_BSRR_BR2_Pos                    (18U)
1758 #define GPIO_BSRR_BR2_Msk                    (0x1UL << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */
1759 #define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 /*!< Port x Reset bit 2 */
1760 #define GPIO_BSRR_BR3_Pos                    (19U)
1761 #define GPIO_BSRR_BR3_Msk                    (0x1UL << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */
1762 #define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 /*!< Port x Reset bit 3 */
1763 #define GPIO_BSRR_BR4_Pos                    (20U)
1764 #define GPIO_BSRR_BR4_Msk                    (0x1UL << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */
1765 #define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 /*!< Port x Reset bit 4 */
1766 #define GPIO_BSRR_BR5_Pos                    (21U)
1767 #define GPIO_BSRR_BR5_Msk                    (0x1UL << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */
1768 #define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 /*!< Port x Reset bit 5 */
1769 #define GPIO_BSRR_BR6_Pos                    (22U)
1770 #define GPIO_BSRR_BR6_Msk                    (0x1UL << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */
1771 #define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 /*!< Port x Reset bit 6 */
1772 #define GPIO_BSRR_BR7_Pos                    (23U)
1773 #define GPIO_BSRR_BR7_Msk                    (0x1UL << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */
1774 #define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 /*!< Port x Reset bit 7 */
1775 #define GPIO_BSRR_BR8_Pos                    (24U)
1776 #define GPIO_BSRR_BR8_Msk                    (0x1UL << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */
1777 #define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 /*!< Port x Reset bit 8 */
1778 #define GPIO_BSRR_BR9_Pos                    (25U)
1779 #define GPIO_BSRR_BR9_Msk                    (0x1UL << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */
1780 #define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 /*!< Port x Reset bit 9 */
1781 #define GPIO_BSRR_BR10_Pos                   (26U)
1782 #define GPIO_BSRR_BR10_Msk                   (0x1UL << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */
1783 #define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                /*!< Port x Reset bit 10 */
1784 #define GPIO_BSRR_BR11_Pos                   (27U)
1785 #define GPIO_BSRR_BR11_Msk                   (0x1UL << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */
1786 #define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                /*!< Port x Reset bit 11 */
1787 #define GPIO_BSRR_BR12_Pos                   (28U)
1788 #define GPIO_BSRR_BR12_Msk                   (0x1UL << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */
1789 #define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                /*!< Port x Reset bit 12 */
1790 #define GPIO_BSRR_BR13_Pos                   (29U)
1791 #define GPIO_BSRR_BR13_Msk                   (0x1UL << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */
1792 #define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                /*!< Port x Reset bit 13 */
1793 #define GPIO_BSRR_BR14_Pos                   (30U)
1794 #define GPIO_BSRR_BR14_Msk                   (0x1UL << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */
1795 #define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                /*!< Port x Reset bit 14 */
1796 #define GPIO_BSRR_BR15_Pos                   (31U)
1797 #define GPIO_BSRR_BR15_Msk                   (0x1UL << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */
1798 #define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                /*!< Port x Reset bit 15 */
1799 
1800 /*******************  Bit definition for GPIO_BRR register  *******************/
1801 #define GPIO_BRR_BR0_Pos                     (0U)
1802 #define GPIO_BRR_BR0_Msk                     (0x1UL << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */
1803 #define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  /*!< Port x Reset bit 0 */
1804 #define GPIO_BRR_BR1_Pos                     (1U)
1805 #define GPIO_BRR_BR1_Msk                     (0x1UL << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */
1806 #define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  /*!< Port x Reset bit 1 */
1807 #define GPIO_BRR_BR2_Pos                     (2U)
1808 #define GPIO_BRR_BR2_Msk                     (0x1UL << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */
1809 #define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  /*!< Port x Reset bit 2 */
1810 #define GPIO_BRR_BR3_Pos                     (3U)
1811 #define GPIO_BRR_BR3_Msk                     (0x1UL << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */
1812 #define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  /*!< Port x Reset bit 3 */
1813 #define GPIO_BRR_BR4_Pos                     (4U)
1814 #define GPIO_BRR_BR4_Msk                     (0x1UL << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */
1815 #define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  /*!< Port x Reset bit 4 */
1816 #define GPIO_BRR_BR5_Pos                     (5U)
1817 #define GPIO_BRR_BR5_Msk                     (0x1UL << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */
1818 #define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  /*!< Port x Reset bit 5 */
1819 #define GPIO_BRR_BR6_Pos                     (6U)
1820 #define GPIO_BRR_BR6_Msk                     (0x1UL << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */
1821 #define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  /*!< Port x Reset bit 6 */
1822 #define GPIO_BRR_BR7_Pos                     (7U)
1823 #define GPIO_BRR_BR7_Msk                     (0x1UL << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */
1824 #define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  /*!< Port x Reset bit 7 */
1825 #define GPIO_BRR_BR8_Pos                     (8U)
1826 #define GPIO_BRR_BR8_Msk                     (0x1UL << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */
1827 #define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  /*!< Port x Reset bit 8 */
1828 #define GPIO_BRR_BR9_Pos                     (9U)
1829 #define GPIO_BRR_BR9_Msk                     (0x1UL << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */
1830 #define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  /*!< Port x Reset bit 9 */
1831 #define GPIO_BRR_BR10_Pos                    (10U)
1832 #define GPIO_BRR_BR10_Msk                    (0x1UL << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */
1833 #define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 /*!< Port x Reset bit 10 */
1834 #define GPIO_BRR_BR11_Pos                    (11U)
1835 #define GPIO_BRR_BR11_Msk                    (0x1UL << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */
1836 #define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 /*!< Port x Reset bit 11 */
1837 #define GPIO_BRR_BR12_Pos                    (12U)
1838 #define GPIO_BRR_BR12_Msk                    (0x1UL << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */
1839 #define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 /*!< Port x Reset bit 12 */
1840 #define GPIO_BRR_BR13_Pos                    (13U)
1841 #define GPIO_BRR_BR13_Msk                    (0x1UL << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */
1842 #define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 /*!< Port x Reset bit 13 */
1843 #define GPIO_BRR_BR14_Pos                    (14U)
1844 #define GPIO_BRR_BR14_Msk                    (0x1UL << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */
1845 #define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 /*!< Port x Reset bit 14 */
1846 #define GPIO_BRR_BR15_Pos                    (15U)
1847 #define GPIO_BRR_BR15_Msk                    (0x1UL << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */
1848 #define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 /*!< Port x Reset bit 15 */
1849 
1850 /******************  Bit definition for GPIO_LCKR register  *******************/
1851 #define GPIO_LCKR_LCK0_Pos                   (0U)
1852 #define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
1853 #define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                /*!< Port x Lock bit 0 */
1854 #define GPIO_LCKR_LCK1_Pos                   (1U)
1855 #define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
1856 #define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                /*!< Port x Lock bit 1 */
1857 #define GPIO_LCKR_LCK2_Pos                   (2U)
1858 #define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
1859 #define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                /*!< Port x Lock bit 2 */
1860 #define GPIO_LCKR_LCK3_Pos                   (3U)
1861 #define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
1862 #define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                /*!< Port x Lock bit 3 */
1863 #define GPIO_LCKR_LCK4_Pos                   (4U)
1864 #define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
1865 #define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                /*!< Port x Lock bit 4 */
1866 #define GPIO_LCKR_LCK5_Pos                   (5U)
1867 #define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
1868 #define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                /*!< Port x Lock bit 5 */
1869 #define GPIO_LCKR_LCK6_Pos                   (6U)
1870 #define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
1871 #define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                /*!< Port x Lock bit 6 */
1872 #define GPIO_LCKR_LCK7_Pos                   (7U)
1873 #define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
1874 #define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                /*!< Port x Lock bit 7 */
1875 #define GPIO_LCKR_LCK8_Pos                   (8U)
1876 #define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
1877 #define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                /*!< Port x Lock bit 8 */
1878 #define GPIO_LCKR_LCK9_Pos                   (9U)
1879 #define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
1880 #define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                /*!< Port x Lock bit 9 */
1881 #define GPIO_LCKR_LCK10_Pos                  (10U)
1882 #define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
1883 #define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               /*!< Port x Lock bit 10 */
1884 #define GPIO_LCKR_LCK11_Pos                  (11U)
1885 #define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
1886 #define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               /*!< Port x Lock bit 11 */
1887 #define GPIO_LCKR_LCK12_Pos                  (12U)
1888 #define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
1889 #define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               /*!< Port x Lock bit 12 */
1890 #define GPIO_LCKR_LCK13_Pos                  (13U)
1891 #define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
1892 #define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               /*!< Port x Lock bit 13 */
1893 #define GPIO_LCKR_LCK14_Pos                  (14U)
1894 #define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
1895 #define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               /*!< Port x Lock bit 14 */
1896 #define GPIO_LCKR_LCK15_Pos                  (15U)
1897 #define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
1898 #define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               /*!< Port x Lock bit 15 */
1899 #define GPIO_LCKR_LCKK_Pos                   (16U)
1900 #define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
1901 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                /*!< Lock key */
1902 
1903 /*----------------------------------------------------------------------------*/
1904 
1905 /******************  Bit definition for AFIO_EVCR register  *******************/
1906 #define AFIO_EVCR_PIN_Pos                    (0U)
1907 #define AFIO_EVCR_PIN_Msk                    (0xFUL << AFIO_EVCR_PIN_Pos)       /*!< 0x0000000F */
1908 #define AFIO_EVCR_PIN                        AFIO_EVCR_PIN_Msk                 /*!< PIN[3:0] bits (Pin selection) */
1909 #define AFIO_EVCR_PIN_0                      (0x1UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000001 */
1910 #define AFIO_EVCR_PIN_1                      (0x2UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000002 */
1911 #define AFIO_EVCR_PIN_2                      (0x4UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000004 */
1912 #define AFIO_EVCR_PIN_3                      (0x8UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */
1913 
1914 /*!< PIN configuration */
1915 #define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */
1916 #define AFIO_EVCR_PIN_PX1_Pos                (0U)
1917 #define AFIO_EVCR_PIN_PX1_Msk                (0x1UL << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */
1918 #define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */
1919 #define AFIO_EVCR_PIN_PX2_Pos                (1U)
1920 #define AFIO_EVCR_PIN_PX2_Msk                (0x1UL << AFIO_EVCR_PIN_PX2_Pos)   /*!< 0x00000002 */
1921 #define AFIO_EVCR_PIN_PX2                    AFIO_EVCR_PIN_PX2_Msk             /*!< Pin 2 selected */
1922 #define AFIO_EVCR_PIN_PX3_Pos                (0U)
1923 #define AFIO_EVCR_PIN_PX3_Msk                (0x3UL << AFIO_EVCR_PIN_PX3_Pos)   /*!< 0x00000003 */
1924 #define AFIO_EVCR_PIN_PX3                    AFIO_EVCR_PIN_PX3_Msk             /*!< Pin 3 selected */
1925 #define AFIO_EVCR_PIN_PX4_Pos                (2U)
1926 #define AFIO_EVCR_PIN_PX4_Msk                (0x1UL << AFIO_EVCR_PIN_PX4_Pos)   /*!< 0x00000004 */
1927 #define AFIO_EVCR_PIN_PX4                    AFIO_EVCR_PIN_PX4_Msk             /*!< Pin 4 selected */
1928 #define AFIO_EVCR_PIN_PX5_Pos                (0U)
1929 #define AFIO_EVCR_PIN_PX5_Msk                (0x5UL << AFIO_EVCR_PIN_PX5_Pos)   /*!< 0x00000005 */
1930 #define AFIO_EVCR_PIN_PX5                    AFIO_EVCR_PIN_PX5_Msk             /*!< Pin 5 selected */
1931 #define AFIO_EVCR_PIN_PX6_Pos                (1U)
1932 #define AFIO_EVCR_PIN_PX6_Msk                (0x3UL << AFIO_EVCR_PIN_PX6_Pos)   /*!< 0x00000006 */
1933 #define AFIO_EVCR_PIN_PX6                    AFIO_EVCR_PIN_PX6_Msk             /*!< Pin 6 selected */
1934 #define AFIO_EVCR_PIN_PX7_Pos                (0U)
1935 #define AFIO_EVCR_PIN_PX7_Msk                (0x7UL << AFIO_EVCR_PIN_PX7_Pos)   /*!< 0x00000007 */
1936 #define AFIO_EVCR_PIN_PX7                    AFIO_EVCR_PIN_PX7_Msk             /*!< Pin 7 selected */
1937 #define AFIO_EVCR_PIN_PX8_Pos                (3U)
1938 #define AFIO_EVCR_PIN_PX8_Msk                (0x1UL << AFIO_EVCR_PIN_PX8_Pos)   /*!< 0x00000008 */
1939 #define AFIO_EVCR_PIN_PX8                    AFIO_EVCR_PIN_PX8_Msk             /*!< Pin 8 selected */
1940 #define AFIO_EVCR_PIN_PX9_Pos                (0U)
1941 #define AFIO_EVCR_PIN_PX9_Msk                (0x9UL << AFIO_EVCR_PIN_PX9_Pos)   /*!< 0x00000009 */
1942 #define AFIO_EVCR_PIN_PX9                    AFIO_EVCR_PIN_PX9_Msk             /*!< Pin 9 selected */
1943 #define AFIO_EVCR_PIN_PX10_Pos               (1U)
1944 #define AFIO_EVCR_PIN_PX10_Msk               (0x5UL << AFIO_EVCR_PIN_PX10_Pos)  /*!< 0x0000000A */
1945 #define AFIO_EVCR_PIN_PX10                   AFIO_EVCR_PIN_PX10_Msk            /*!< Pin 10 selected */
1946 #define AFIO_EVCR_PIN_PX11_Pos               (0U)
1947 #define AFIO_EVCR_PIN_PX11_Msk               (0xBUL << AFIO_EVCR_PIN_PX11_Pos)  /*!< 0x0000000B */
1948 #define AFIO_EVCR_PIN_PX11                   AFIO_EVCR_PIN_PX11_Msk            /*!< Pin 11 selected */
1949 #define AFIO_EVCR_PIN_PX12_Pos               (2U)
1950 #define AFIO_EVCR_PIN_PX12_Msk               (0x3UL << AFIO_EVCR_PIN_PX12_Pos)  /*!< 0x0000000C */
1951 #define AFIO_EVCR_PIN_PX12                   AFIO_EVCR_PIN_PX12_Msk            /*!< Pin 12 selected */
1952 #define AFIO_EVCR_PIN_PX13_Pos               (0U)
1953 #define AFIO_EVCR_PIN_PX13_Msk               (0xDUL << AFIO_EVCR_PIN_PX13_Pos)  /*!< 0x0000000D */
1954 #define AFIO_EVCR_PIN_PX13                   AFIO_EVCR_PIN_PX13_Msk            /*!< Pin 13 selected */
1955 #define AFIO_EVCR_PIN_PX14_Pos               (1U)
1956 #define AFIO_EVCR_PIN_PX14_Msk               (0x7UL << AFIO_EVCR_PIN_PX14_Pos)  /*!< 0x0000000E */
1957 #define AFIO_EVCR_PIN_PX14                   AFIO_EVCR_PIN_PX14_Msk            /*!< Pin 14 selected */
1958 #define AFIO_EVCR_PIN_PX15_Pos               (0U)
1959 #define AFIO_EVCR_PIN_PX15_Msk               (0xFUL << AFIO_EVCR_PIN_PX15_Pos)  /*!< 0x0000000F */
1960 #define AFIO_EVCR_PIN_PX15                   AFIO_EVCR_PIN_PX15_Msk            /*!< Pin 15 selected */
1961 
1962 #define AFIO_EVCR_PORT_Pos                   (4U)
1963 #define AFIO_EVCR_PORT_Msk                   (0x7UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000070 */
1964 #define AFIO_EVCR_PORT                       AFIO_EVCR_PORT_Msk                /*!< PORT[2:0] bits (Port selection) */
1965 #define AFIO_EVCR_PORT_0                     (0x1UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000010 */
1966 #define AFIO_EVCR_PORT_1                     (0x2UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000020 */
1967 #define AFIO_EVCR_PORT_2                     (0x4UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */
1968 
1969 /*!< PORT configuration */
1970 #define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */
1971 #define AFIO_EVCR_PORT_PB_Pos                (4U)
1972 #define AFIO_EVCR_PORT_PB_Msk                (0x1UL << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */
1973 #define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */
1974 #define AFIO_EVCR_PORT_PC_Pos                (5U)
1975 #define AFIO_EVCR_PORT_PC_Msk                (0x1UL << AFIO_EVCR_PORT_PC_Pos)   /*!< 0x00000020 */
1976 #define AFIO_EVCR_PORT_PC                    AFIO_EVCR_PORT_PC_Msk             /*!< Port C selected */
1977 #define AFIO_EVCR_PORT_PD_Pos                (4U)
1978 #define AFIO_EVCR_PORT_PD_Msk                (0x3UL << AFIO_EVCR_PORT_PD_Pos)   /*!< 0x00000030 */
1979 #define AFIO_EVCR_PORT_PD                    AFIO_EVCR_PORT_PD_Msk             /*!< Port D selected */
1980 #define AFIO_EVCR_PORT_PE_Pos                (6U)
1981 #define AFIO_EVCR_PORT_PE_Msk                (0x1UL << AFIO_EVCR_PORT_PE_Pos)   /*!< 0x00000040 */
1982 #define AFIO_EVCR_PORT_PE                    AFIO_EVCR_PORT_PE_Msk             /*!< Port E selected */
1983 
1984 #define AFIO_EVCR_EVOE_Pos                   (7U)
1985 #define AFIO_EVCR_EVOE_Msk                   (0x1UL << AFIO_EVCR_EVOE_Pos)      /*!< 0x00000080 */
1986 #define AFIO_EVCR_EVOE                       AFIO_EVCR_EVOE_Msk                /*!< Event Output Enable */
1987 
1988 /******************  Bit definition for AFIO_MAPR register  *******************/
1989 #define AFIO_MAPR_SPI1_REMAP_Pos             (0U)
1990 #define AFIO_MAPR_SPI1_REMAP_Msk             (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
1991 #define AFIO_MAPR_SPI1_REMAP                 AFIO_MAPR_SPI1_REMAP_Msk          /*!< SPI1 remapping */
1992 #define AFIO_MAPR_I2C1_REMAP_Pos             (1U)
1993 #define AFIO_MAPR_I2C1_REMAP_Msk             (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
1994 #define AFIO_MAPR_I2C1_REMAP                 AFIO_MAPR_I2C1_REMAP_Msk          /*!< I2C1 remapping */
1995 #define AFIO_MAPR_USART1_REMAP_Pos           (2U)
1996 #define AFIO_MAPR_USART1_REMAP_Msk           (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
1997 #define AFIO_MAPR_USART1_REMAP               AFIO_MAPR_USART1_REMAP_Msk        /*!< USART1 remapping */
1998 #define AFIO_MAPR_USART2_REMAP_Pos           (3U)
1999 #define AFIO_MAPR_USART2_REMAP_Msk           (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
2000 #define AFIO_MAPR_USART2_REMAP               AFIO_MAPR_USART2_REMAP_Msk        /*!< USART2 remapping */
2001 
2002 
2003 #define AFIO_MAPR_TIM1_REMAP_Pos             (6U)
2004 #define AFIO_MAPR_TIM1_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
2005 #define AFIO_MAPR_TIM1_REMAP                 AFIO_MAPR_TIM1_REMAP_Msk          /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2006 #define AFIO_MAPR_TIM1_REMAP_0               (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
2007 #define AFIO_MAPR_TIM1_REMAP_1               (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
2008 
2009 /*!< TIM1_REMAP configuration */
2010 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2011 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2012 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
2013 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2014 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos   (6U)
2015 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
2016 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2017 
2018 #define AFIO_MAPR_TIM2_REMAP_Pos             (8U)
2019 #define AFIO_MAPR_TIM2_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
2020 #define AFIO_MAPR_TIM2_REMAP                 AFIO_MAPR_TIM2_REMAP_Msk          /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2021 #define AFIO_MAPR_TIM2_REMAP_0               (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
2022 #define AFIO_MAPR_TIM2_REMAP_1               (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
2023 
2024 /*!< TIM2_REMAP configuration */
2025 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2026 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2027 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
2028 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2029 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2030 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
2031 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2032 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos   (8U)
2033 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
2034 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2035 
2036 #define AFIO_MAPR_TIM3_REMAP_Pos             (10U)
2037 #define AFIO_MAPR_TIM3_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2038 #define AFIO_MAPR_TIM3_REMAP                 AFIO_MAPR_TIM3_REMAP_Msk          /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2039 #define AFIO_MAPR_TIM3_REMAP_0               (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2040 #define AFIO_MAPR_TIM3_REMAP_1               (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2041 
2042 /*!< TIM3_REMAP configuration */
2043 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2044 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2045 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2046 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2047 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos   (10U)
2048 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2049 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2050 
2051 
2052 #define AFIO_MAPR_CAN_REMAP_Pos              (13U)
2053 #define AFIO_MAPR_CAN_REMAP_Msk              (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
2054 #define AFIO_MAPR_CAN_REMAP                  AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2055 #define AFIO_MAPR_CAN_REMAP_0                (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
2056 #define AFIO_MAPR_CAN_REMAP_1                (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
2057 
2058 /*!< CAN_REMAP configuration */
2059 #define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2060 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)
2061 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
2062 #define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2063 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos       (13U)
2064 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk       (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
2065 #define AFIO_MAPR_CAN_REMAP_REMAP3           AFIO_MAPR_CAN_REMAP_REMAP3_Msk    /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2066 
2067 #define AFIO_MAPR_PD01_REMAP_Pos             (15U)
2068 #define AFIO_MAPR_PD01_REMAP_Msk             (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2069 #define AFIO_MAPR_PD01_REMAP                 AFIO_MAPR_PD01_REMAP_Msk          /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2070 
2071 /*!< SWJ_CFG configuration */
2072 #define AFIO_MAPR_SWJ_CFG_Pos                (24U)
2073 #define AFIO_MAPR_SWJ_CFG_Msk                (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x07000000 */
2074 #define AFIO_MAPR_SWJ_CFG                    AFIO_MAPR_SWJ_CFG_Msk             /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2075 #define AFIO_MAPR_SWJ_CFG_0                  (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x01000000 */
2076 #define AFIO_MAPR_SWJ_CFG_1                  (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */
2077 #define AFIO_MAPR_SWJ_CFG_2                  (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */
2078 
2079 #define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2080 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)
2081 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2082 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2083 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos    (25U)
2084 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk    (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2085 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2086 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos        (26U)
2087 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk        (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2088 #define AFIO_MAPR_SWJ_CFG_DISABLE            AFIO_MAPR_SWJ_CFG_DISABLE_Msk     /*!< JTAG-DP Disabled and SW-DP Disabled */
2089 
2090 
2091 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
2092 #define AFIO_EXTICR1_EXTI0_Pos               (0U)
2093 #define AFIO_EXTICR1_EXTI0_Msk               (0xFUL << AFIO_EXTICR1_EXTI0_Pos)  /*!< 0x0000000F */
2094 #define AFIO_EXTICR1_EXTI0                   AFIO_EXTICR1_EXTI0_Msk            /*!< EXTI 0 configuration */
2095 #define AFIO_EXTICR1_EXTI1_Pos               (4U)
2096 #define AFIO_EXTICR1_EXTI1_Msk               (0xFUL << AFIO_EXTICR1_EXTI1_Pos)  /*!< 0x000000F0 */
2097 #define AFIO_EXTICR1_EXTI1                   AFIO_EXTICR1_EXTI1_Msk            /*!< EXTI 1 configuration */
2098 #define AFIO_EXTICR1_EXTI2_Pos               (8U)
2099 #define AFIO_EXTICR1_EXTI2_Msk               (0xFUL << AFIO_EXTICR1_EXTI2_Pos)  /*!< 0x00000F00 */
2100 #define AFIO_EXTICR1_EXTI2                   AFIO_EXTICR1_EXTI2_Msk            /*!< EXTI 2 configuration */
2101 #define AFIO_EXTICR1_EXTI3_Pos               (12U)
2102 #define AFIO_EXTICR1_EXTI3_Msk               (0xFUL << AFIO_EXTICR1_EXTI3_Pos)  /*!< 0x0000F000 */
2103 #define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */
2104 
2105 /*!< EXTI0 configuration */
2106 #define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */
2107 #define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)
2108 #define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2109 #define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */
2110 #define AFIO_EXTICR1_EXTI0_PC_Pos            (1U)
2111 #define AFIO_EXTICR1_EXTI0_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2112 #define AFIO_EXTICR1_EXTI0_PC                AFIO_EXTICR1_EXTI0_PC_Msk         /*!< PC[0] pin */
2113 #define AFIO_EXTICR1_EXTI0_PD_Pos            (0U)
2114 #define AFIO_EXTICR1_EXTI0_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2115 #define AFIO_EXTICR1_EXTI0_PD                AFIO_EXTICR1_EXTI0_PD_Msk         /*!< PD[0] pin */
2116 #define AFIO_EXTICR1_EXTI0_PE_Pos            (2U)
2117 #define AFIO_EXTICR1_EXTI0_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2118 #define AFIO_EXTICR1_EXTI0_PE                AFIO_EXTICR1_EXTI0_PE_Msk         /*!< PE[0] pin */
2119 #define AFIO_EXTICR1_EXTI0_PF_Pos            (0U)
2120 #define AFIO_EXTICR1_EXTI0_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2121 #define AFIO_EXTICR1_EXTI0_PF                AFIO_EXTICR1_EXTI0_PF_Msk         /*!< PF[0] pin */
2122 #define AFIO_EXTICR1_EXTI0_PG_Pos            (1U)
2123 #define AFIO_EXTICR1_EXTI0_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2124 #define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */
2125 
2126 /*!< EXTI1 configuration */
2127 #define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */
2128 #define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)
2129 #define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2130 #define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */
2131 #define AFIO_EXTICR1_EXTI1_PC_Pos            (5U)
2132 #define AFIO_EXTICR1_EXTI1_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2133 #define AFIO_EXTICR1_EXTI1_PC                AFIO_EXTICR1_EXTI1_PC_Msk         /*!< PC[1] pin */
2134 #define AFIO_EXTICR1_EXTI1_PD_Pos            (4U)
2135 #define AFIO_EXTICR1_EXTI1_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2136 #define AFIO_EXTICR1_EXTI1_PD                AFIO_EXTICR1_EXTI1_PD_Msk         /*!< PD[1] pin */
2137 #define AFIO_EXTICR1_EXTI1_PE_Pos            (6U)
2138 #define AFIO_EXTICR1_EXTI1_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2139 #define AFIO_EXTICR1_EXTI1_PE                AFIO_EXTICR1_EXTI1_PE_Msk         /*!< PE[1] pin */
2140 #define AFIO_EXTICR1_EXTI1_PF_Pos            (4U)
2141 #define AFIO_EXTICR1_EXTI1_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2142 #define AFIO_EXTICR1_EXTI1_PF                AFIO_EXTICR1_EXTI1_PF_Msk         /*!< PF[1] pin */
2143 #define AFIO_EXTICR1_EXTI1_PG_Pos            (5U)
2144 #define AFIO_EXTICR1_EXTI1_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2145 #define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */
2146 
2147 /*!< EXTI2 configuration */
2148 #define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */
2149 #define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)
2150 #define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2151 #define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */
2152 #define AFIO_EXTICR1_EXTI2_PC_Pos            (9U)
2153 #define AFIO_EXTICR1_EXTI2_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2154 #define AFIO_EXTICR1_EXTI2_PC                AFIO_EXTICR1_EXTI2_PC_Msk         /*!< PC[2] pin */
2155 #define AFIO_EXTICR1_EXTI2_PD_Pos            (8U)
2156 #define AFIO_EXTICR1_EXTI2_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2157 #define AFIO_EXTICR1_EXTI2_PD                AFIO_EXTICR1_EXTI2_PD_Msk         /*!< PD[2] pin */
2158 #define AFIO_EXTICR1_EXTI2_PE_Pos            (10U)
2159 #define AFIO_EXTICR1_EXTI2_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2160 #define AFIO_EXTICR1_EXTI2_PE                AFIO_EXTICR1_EXTI2_PE_Msk         /*!< PE[2] pin */
2161 #define AFIO_EXTICR1_EXTI2_PF_Pos            (8U)
2162 #define AFIO_EXTICR1_EXTI2_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2163 #define AFIO_EXTICR1_EXTI2_PF                AFIO_EXTICR1_EXTI2_PF_Msk         /*!< PF[2] pin */
2164 #define AFIO_EXTICR1_EXTI2_PG_Pos            (9U)
2165 #define AFIO_EXTICR1_EXTI2_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2166 #define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */
2167 
2168 /*!< EXTI3 configuration */
2169 #define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */
2170 #define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)
2171 #define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2172 #define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */
2173 #define AFIO_EXTICR1_EXTI3_PC_Pos            (13U)
2174 #define AFIO_EXTICR1_EXTI3_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2175 #define AFIO_EXTICR1_EXTI3_PC                AFIO_EXTICR1_EXTI3_PC_Msk         /*!< PC[3] pin */
2176 #define AFIO_EXTICR1_EXTI3_PD_Pos            (12U)
2177 #define AFIO_EXTICR1_EXTI3_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2178 #define AFIO_EXTICR1_EXTI3_PD                AFIO_EXTICR1_EXTI3_PD_Msk         /*!< PD[3] pin */
2179 #define AFIO_EXTICR1_EXTI3_PE_Pos            (14U)
2180 #define AFIO_EXTICR1_EXTI3_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2181 #define AFIO_EXTICR1_EXTI3_PE                AFIO_EXTICR1_EXTI3_PE_Msk         /*!< PE[3] pin */
2182 #define AFIO_EXTICR1_EXTI3_PF_Pos            (12U)
2183 #define AFIO_EXTICR1_EXTI3_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2184 #define AFIO_EXTICR1_EXTI3_PF                AFIO_EXTICR1_EXTI3_PF_Msk         /*!< PF[3] pin */
2185 #define AFIO_EXTICR1_EXTI3_PG_Pos            (13U)
2186 #define AFIO_EXTICR1_EXTI3_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2187 #define AFIO_EXTICR1_EXTI3_PG                AFIO_EXTICR1_EXTI3_PG_Msk         /*!< PG[3] pin */
2188 
2189 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
2190 #define AFIO_EXTICR2_EXTI4_Pos               (0U)
2191 #define AFIO_EXTICR2_EXTI4_Msk               (0xFUL << AFIO_EXTICR2_EXTI4_Pos)  /*!< 0x0000000F */
2192 #define AFIO_EXTICR2_EXTI4                   AFIO_EXTICR2_EXTI4_Msk            /*!< EXTI 4 configuration */
2193 #define AFIO_EXTICR2_EXTI5_Pos               (4U)
2194 #define AFIO_EXTICR2_EXTI5_Msk               (0xFUL << AFIO_EXTICR2_EXTI5_Pos)  /*!< 0x000000F0 */
2195 #define AFIO_EXTICR2_EXTI5                   AFIO_EXTICR2_EXTI5_Msk            /*!< EXTI 5 configuration */
2196 #define AFIO_EXTICR2_EXTI6_Pos               (8U)
2197 #define AFIO_EXTICR2_EXTI6_Msk               (0xFUL << AFIO_EXTICR2_EXTI6_Pos)  /*!< 0x00000F00 */
2198 #define AFIO_EXTICR2_EXTI6                   AFIO_EXTICR2_EXTI6_Msk            /*!< EXTI 6 configuration */
2199 #define AFIO_EXTICR2_EXTI7_Pos               (12U)
2200 #define AFIO_EXTICR2_EXTI7_Msk               (0xFUL << AFIO_EXTICR2_EXTI7_Pos)  /*!< 0x0000F000 */
2201 #define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */
2202 
2203 /*!< EXTI4 configuration */
2204 #define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */
2205 #define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)
2206 #define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2207 #define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */
2208 #define AFIO_EXTICR2_EXTI4_PC_Pos            (1U)
2209 #define AFIO_EXTICR2_EXTI4_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2210 #define AFIO_EXTICR2_EXTI4_PC                AFIO_EXTICR2_EXTI4_PC_Msk         /*!< PC[4] pin */
2211 #define AFIO_EXTICR2_EXTI4_PD_Pos            (0U)
2212 #define AFIO_EXTICR2_EXTI4_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2213 #define AFIO_EXTICR2_EXTI4_PD                AFIO_EXTICR2_EXTI4_PD_Msk         /*!< PD[4] pin */
2214 #define AFIO_EXTICR2_EXTI4_PE_Pos            (2U)
2215 #define AFIO_EXTICR2_EXTI4_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2216 #define AFIO_EXTICR2_EXTI4_PE                AFIO_EXTICR2_EXTI4_PE_Msk         /*!< PE[4] pin */
2217 #define AFIO_EXTICR2_EXTI4_PF_Pos            (0U)
2218 #define AFIO_EXTICR2_EXTI4_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2219 #define AFIO_EXTICR2_EXTI4_PF                AFIO_EXTICR2_EXTI4_PF_Msk         /*!< PF[4] pin */
2220 #define AFIO_EXTICR2_EXTI4_PG_Pos            (1U)
2221 #define AFIO_EXTICR2_EXTI4_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2222 #define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */
2223 
2224 /* EXTI5 configuration */
2225 #define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */
2226 #define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)
2227 #define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2228 #define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */
2229 #define AFIO_EXTICR2_EXTI5_PC_Pos            (5U)
2230 #define AFIO_EXTICR2_EXTI5_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2231 #define AFIO_EXTICR2_EXTI5_PC                AFIO_EXTICR2_EXTI5_PC_Msk         /*!< PC[5] pin */
2232 #define AFIO_EXTICR2_EXTI5_PD_Pos            (4U)
2233 #define AFIO_EXTICR2_EXTI5_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2234 #define AFIO_EXTICR2_EXTI5_PD                AFIO_EXTICR2_EXTI5_PD_Msk         /*!< PD[5] pin */
2235 #define AFIO_EXTICR2_EXTI5_PE_Pos            (6U)
2236 #define AFIO_EXTICR2_EXTI5_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2237 #define AFIO_EXTICR2_EXTI5_PE                AFIO_EXTICR2_EXTI5_PE_Msk         /*!< PE[5] pin */
2238 #define AFIO_EXTICR2_EXTI5_PF_Pos            (4U)
2239 #define AFIO_EXTICR2_EXTI5_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2240 #define AFIO_EXTICR2_EXTI5_PF                AFIO_EXTICR2_EXTI5_PF_Msk         /*!< PF[5] pin */
2241 #define AFIO_EXTICR2_EXTI5_PG_Pos            (5U)
2242 #define AFIO_EXTICR2_EXTI5_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2243 #define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */
2244 
2245 /*!< EXTI6 configuration */
2246 #define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */
2247 #define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)
2248 #define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2249 #define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */
2250 #define AFIO_EXTICR2_EXTI6_PC_Pos            (9U)
2251 #define AFIO_EXTICR2_EXTI6_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2252 #define AFIO_EXTICR2_EXTI6_PC                AFIO_EXTICR2_EXTI6_PC_Msk         /*!< PC[6] pin */
2253 #define AFIO_EXTICR2_EXTI6_PD_Pos            (8U)
2254 #define AFIO_EXTICR2_EXTI6_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2255 #define AFIO_EXTICR2_EXTI6_PD                AFIO_EXTICR2_EXTI6_PD_Msk         /*!< PD[6] pin */
2256 #define AFIO_EXTICR2_EXTI6_PE_Pos            (10U)
2257 #define AFIO_EXTICR2_EXTI6_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2258 #define AFIO_EXTICR2_EXTI6_PE                AFIO_EXTICR2_EXTI6_PE_Msk         /*!< PE[6] pin */
2259 #define AFIO_EXTICR2_EXTI6_PF_Pos            (8U)
2260 #define AFIO_EXTICR2_EXTI6_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2261 #define AFIO_EXTICR2_EXTI6_PF                AFIO_EXTICR2_EXTI6_PF_Msk         /*!< PF[6] pin */
2262 #define AFIO_EXTICR2_EXTI6_PG_Pos            (9U)
2263 #define AFIO_EXTICR2_EXTI6_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2264 #define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */
2265 
2266 /*!< EXTI7 configuration */
2267 #define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */
2268 #define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)
2269 #define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2270 #define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */
2271 #define AFIO_EXTICR2_EXTI7_PC_Pos            (13U)
2272 #define AFIO_EXTICR2_EXTI7_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2273 #define AFIO_EXTICR2_EXTI7_PC                AFIO_EXTICR2_EXTI7_PC_Msk         /*!< PC[7] pin */
2274 #define AFIO_EXTICR2_EXTI7_PD_Pos            (12U)
2275 #define AFIO_EXTICR2_EXTI7_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2276 #define AFIO_EXTICR2_EXTI7_PD                AFIO_EXTICR2_EXTI7_PD_Msk         /*!< PD[7] pin */
2277 #define AFIO_EXTICR2_EXTI7_PE_Pos            (14U)
2278 #define AFIO_EXTICR2_EXTI7_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2279 #define AFIO_EXTICR2_EXTI7_PE                AFIO_EXTICR2_EXTI7_PE_Msk         /*!< PE[7] pin */
2280 #define AFIO_EXTICR2_EXTI7_PF_Pos            (12U)
2281 #define AFIO_EXTICR2_EXTI7_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2282 #define AFIO_EXTICR2_EXTI7_PF                AFIO_EXTICR2_EXTI7_PF_Msk         /*!< PF[7] pin */
2283 #define AFIO_EXTICR2_EXTI7_PG_Pos            (13U)
2284 #define AFIO_EXTICR2_EXTI7_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2285 #define AFIO_EXTICR2_EXTI7_PG                AFIO_EXTICR2_EXTI7_PG_Msk         /*!< PG[7] pin */
2286 
2287 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
2288 #define AFIO_EXTICR3_EXTI8_Pos               (0U)
2289 #define AFIO_EXTICR3_EXTI8_Msk               (0xFUL << AFIO_EXTICR3_EXTI8_Pos)  /*!< 0x0000000F */
2290 #define AFIO_EXTICR3_EXTI8                   AFIO_EXTICR3_EXTI8_Msk            /*!< EXTI 8 configuration */
2291 #define AFIO_EXTICR3_EXTI9_Pos               (4U)
2292 #define AFIO_EXTICR3_EXTI9_Msk               (0xFUL << AFIO_EXTICR3_EXTI9_Pos)  /*!< 0x000000F0 */
2293 #define AFIO_EXTICR3_EXTI9                   AFIO_EXTICR3_EXTI9_Msk            /*!< EXTI 9 configuration */
2294 #define AFIO_EXTICR3_EXTI10_Pos              (8U)
2295 #define AFIO_EXTICR3_EXTI10_Msk              (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2296 #define AFIO_EXTICR3_EXTI10                  AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */
2297 #define AFIO_EXTICR3_EXTI11_Pos              (12U)
2298 #define AFIO_EXTICR3_EXTI11_Msk              (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2299 #define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */
2300 
2301 /*!< EXTI8 configuration */
2302 #define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */
2303 #define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)
2304 #define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2305 #define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */
2306 #define AFIO_EXTICR3_EXTI8_PC_Pos            (1U)
2307 #define AFIO_EXTICR3_EXTI8_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2308 #define AFIO_EXTICR3_EXTI8_PC                AFIO_EXTICR3_EXTI8_PC_Msk         /*!< PC[8] pin */
2309 #define AFIO_EXTICR3_EXTI8_PD_Pos            (0U)
2310 #define AFIO_EXTICR3_EXTI8_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2311 #define AFIO_EXTICR3_EXTI8_PD                AFIO_EXTICR3_EXTI8_PD_Msk         /*!< PD[8] pin */
2312 #define AFIO_EXTICR3_EXTI8_PE_Pos            (2U)
2313 #define AFIO_EXTICR3_EXTI8_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2314 #define AFIO_EXTICR3_EXTI8_PE                AFIO_EXTICR3_EXTI8_PE_Msk         /*!< PE[8] pin */
2315 #define AFIO_EXTICR3_EXTI8_PF_Pos            (0U)
2316 #define AFIO_EXTICR3_EXTI8_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2317 #define AFIO_EXTICR3_EXTI8_PF                AFIO_EXTICR3_EXTI8_PF_Msk         /*!< PF[8] pin */
2318 #define AFIO_EXTICR3_EXTI8_PG_Pos            (1U)
2319 #define AFIO_EXTICR3_EXTI8_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2320 #define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */
2321 
2322 /*!< EXTI9 configuration */
2323 #define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */
2324 #define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)
2325 #define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2326 #define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */
2327 #define AFIO_EXTICR3_EXTI9_PC_Pos            (5U)
2328 #define AFIO_EXTICR3_EXTI9_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2329 #define AFIO_EXTICR3_EXTI9_PC                AFIO_EXTICR3_EXTI9_PC_Msk         /*!< PC[9] pin */
2330 #define AFIO_EXTICR3_EXTI9_PD_Pos            (4U)
2331 #define AFIO_EXTICR3_EXTI9_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2332 #define AFIO_EXTICR3_EXTI9_PD                AFIO_EXTICR3_EXTI9_PD_Msk         /*!< PD[9] pin */
2333 #define AFIO_EXTICR3_EXTI9_PE_Pos            (6U)
2334 #define AFIO_EXTICR3_EXTI9_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2335 #define AFIO_EXTICR3_EXTI9_PE                AFIO_EXTICR3_EXTI9_PE_Msk         /*!< PE[9] pin */
2336 #define AFIO_EXTICR3_EXTI9_PF_Pos            (4U)
2337 #define AFIO_EXTICR3_EXTI9_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2338 #define AFIO_EXTICR3_EXTI9_PF                AFIO_EXTICR3_EXTI9_PF_Msk         /*!< PF[9] pin */
2339 #define AFIO_EXTICR3_EXTI9_PG_Pos            (5U)
2340 #define AFIO_EXTICR3_EXTI9_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2341 #define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */
2342 
2343 /*!< EXTI10 configuration */
2344 #define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */
2345 #define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)
2346 #define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2347 #define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */
2348 #define AFIO_EXTICR3_EXTI10_PC_Pos           (9U)
2349 #define AFIO_EXTICR3_EXTI10_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2350 #define AFIO_EXTICR3_EXTI10_PC               AFIO_EXTICR3_EXTI10_PC_Msk        /*!< PC[10] pin */
2351 #define AFIO_EXTICR3_EXTI10_PD_Pos           (8U)
2352 #define AFIO_EXTICR3_EXTI10_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2353 #define AFIO_EXTICR3_EXTI10_PD               AFIO_EXTICR3_EXTI10_PD_Msk        /*!< PD[10] pin */
2354 #define AFIO_EXTICR3_EXTI10_PE_Pos           (10U)
2355 #define AFIO_EXTICR3_EXTI10_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2356 #define AFIO_EXTICR3_EXTI10_PE               AFIO_EXTICR3_EXTI10_PE_Msk        /*!< PE[10] pin */
2357 #define AFIO_EXTICR3_EXTI10_PF_Pos           (8U)
2358 #define AFIO_EXTICR3_EXTI10_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2359 #define AFIO_EXTICR3_EXTI10_PF               AFIO_EXTICR3_EXTI10_PF_Msk        /*!< PF[10] pin */
2360 #define AFIO_EXTICR3_EXTI10_PG_Pos           (9U)
2361 #define AFIO_EXTICR3_EXTI10_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2362 #define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */
2363 
2364 /*!< EXTI11 configuration */
2365 #define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */
2366 #define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)
2367 #define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2368 #define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */
2369 #define AFIO_EXTICR3_EXTI11_PC_Pos           (13U)
2370 #define AFIO_EXTICR3_EXTI11_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2371 #define AFIO_EXTICR3_EXTI11_PC               AFIO_EXTICR3_EXTI11_PC_Msk        /*!< PC[11] pin */
2372 #define AFIO_EXTICR3_EXTI11_PD_Pos           (12U)
2373 #define AFIO_EXTICR3_EXTI11_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2374 #define AFIO_EXTICR3_EXTI11_PD               AFIO_EXTICR3_EXTI11_PD_Msk        /*!< PD[11] pin */
2375 #define AFIO_EXTICR3_EXTI11_PE_Pos           (14U)
2376 #define AFIO_EXTICR3_EXTI11_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2377 #define AFIO_EXTICR3_EXTI11_PE               AFIO_EXTICR3_EXTI11_PE_Msk        /*!< PE[11] pin */
2378 #define AFIO_EXTICR3_EXTI11_PF_Pos           (12U)
2379 #define AFIO_EXTICR3_EXTI11_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2380 #define AFIO_EXTICR3_EXTI11_PF               AFIO_EXTICR3_EXTI11_PF_Msk        /*!< PF[11] pin */
2381 #define AFIO_EXTICR3_EXTI11_PG_Pos           (13U)
2382 #define AFIO_EXTICR3_EXTI11_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2383 #define AFIO_EXTICR3_EXTI11_PG               AFIO_EXTICR3_EXTI11_PG_Msk        /*!< PG[11] pin */
2384 
2385 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
2386 #define AFIO_EXTICR4_EXTI12_Pos              (0U)
2387 #define AFIO_EXTICR4_EXTI12_Msk              (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2388 #define AFIO_EXTICR4_EXTI12                  AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */
2389 #define AFIO_EXTICR4_EXTI13_Pos              (4U)
2390 #define AFIO_EXTICR4_EXTI13_Msk              (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2391 #define AFIO_EXTICR4_EXTI13                  AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */
2392 #define AFIO_EXTICR4_EXTI14_Pos              (8U)
2393 #define AFIO_EXTICR4_EXTI14_Msk              (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2394 #define AFIO_EXTICR4_EXTI14                  AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */
2395 #define AFIO_EXTICR4_EXTI15_Pos              (12U)
2396 #define AFIO_EXTICR4_EXTI15_Msk              (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2397 #define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */
2398 
2399 /* EXTI12 configuration */
2400 #define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */
2401 #define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)
2402 #define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2403 #define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */
2404 #define AFIO_EXTICR4_EXTI12_PC_Pos           (1U)
2405 #define AFIO_EXTICR4_EXTI12_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2406 #define AFIO_EXTICR4_EXTI12_PC               AFIO_EXTICR4_EXTI12_PC_Msk        /*!< PC[12] pin */
2407 #define AFIO_EXTICR4_EXTI12_PD_Pos           (0U)
2408 #define AFIO_EXTICR4_EXTI12_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2409 #define AFIO_EXTICR4_EXTI12_PD               AFIO_EXTICR4_EXTI12_PD_Msk        /*!< PD[12] pin */
2410 #define AFIO_EXTICR4_EXTI12_PE_Pos           (2U)
2411 #define AFIO_EXTICR4_EXTI12_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2412 #define AFIO_EXTICR4_EXTI12_PE               AFIO_EXTICR4_EXTI12_PE_Msk        /*!< PE[12] pin */
2413 #define AFIO_EXTICR4_EXTI12_PF_Pos           (0U)
2414 #define AFIO_EXTICR4_EXTI12_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2415 #define AFIO_EXTICR4_EXTI12_PF               AFIO_EXTICR4_EXTI12_PF_Msk        /*!< PF[12] pin */
2416 #define AFIO_EXTICR4_EXTI12_PG_Pos           (1U)
2417 #define AFIO_EXTICR4_EXTI12_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2418 #define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */
2419 
2420 /* EXTI13 configuration */
2421 #define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */
2422 #define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)
2423 #define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
2424 #define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */
2425 #define AFIO_EXTICR4_EXTI13_PC_Pos           (5U)
2426 #define AFIO_EXTICR4_EXTI13_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
2427 #define AFIO_EXTICR4_EXTI13_PC               AFIO_EXTICR4_EXTI13_PC_Msk        /*!< PC[13] pin */
2428 #define AFIO_EXTICR4_EXTI13_PD_Pos           (4U)
2429 #define AFIO_EXTICR4_EXTI13_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
2430 #define AFIO_EXTICR4_EXTI13_PD               AFIO_EXTICR4_EXTI13_PD_Msk        /*!< PD[13] pin */
2431 #define AFIO_EXTICR4_EXTI13_PE_Pos           (6U)
2432 #define AFIO_EXTICR4_EXTI13_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
2433 #define AFIO_EXTICR4_EXTI13_PE               AFIO_EXTICR4_EXTI13_PE_Msk        /*!< PE[13] pin */
2434 #define AFIO_EXTICR4_EXTI13_PF_Pos           (4U)
2435 #define AFIO_EXTICR4_EXTI13_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
2436 #define AFIO_EXTICR4_EXTI13_PF               AFIO_EXTICR4_EXTI13_PF_Msk        /*!< PF[13] pin */
2437 #define AFIO_EXTICR4_EXTI13_PG_Pos           (5U)
2438 #define AFIO_EXTICR4_EXTI13_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
2439 #define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */
2440 
2441 /*!< EXTI14 configuration */
2442 #define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */
2443 #define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)
2444 #define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
2445 #define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */
2446 #define AFIO_EXTICR4_EXTI14_PC_Pos           (9U)
2447 #define AFIO_EXTICR4_EXTI14_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
2448 #define AFIO_EXTICR4_EXTI14_PC               AFIO_EXTICR4_EXTI14_PC_Msk        /*!< PC[14] pin */
2449 #define AFIO_EXTICR4_EXTI14_PD_Pos           (8U)
2450 #define AFIO_EXTICR4_EXTI14_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
2451 #define AFIO_EXTICR4_EXTI14_PD               AFIO_EXTICR4_EXTI14_PD_Msk        /*!< PD[14] pin */
2452 #define AFIO_EXTICR4_EXTI14_PE_Pos           (10U)
2453 #define AFIO_EXTICR4_EXTI14_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
2454 #define AFIO_EXTICR4_EXTI14_PE               AFIO_EXTICR4_EXTI14_PE_Msk        /*!< PE[14] pin */
2455 #define AFIO_EXTICR4_EXTI14_PF_Pos           (8U)
2456 #define AFIO_EXTICR4_EXTI14_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
2457 #define AFIO_EXTICR4_EXTI14_PF               AFIO_EXTICR4_EXTI14_PF_Msk        /*!< PF[14] pin */
2458 #define AFIO_EXTICR4_EXTI14_PG_Pos           (9U)
2459 #define AFIO_EXTICR4_EXTI14_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
2460 #define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */
2461 
2462 /*!< EXTI15 configuration */
2463 #define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */
2464 #define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)
2465 #define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
2466 #define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */
2467 #define AFIO_EXTICR4_EXTI15_PC_Pos           (13U)
2468 #define AFIO_EXTICR4_EXTI15_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
2469 #define AFIO_EXTICR4_EXTI15_PC               AFIO_EXTICR4_EXTI15_PC_Msk        /*!< PC[15] pin */
2470 #define AFIO_EXTICR4_EXTI15_PD_Pos           (12U)
2471 #define AFIO_EXTICR4_EXTI15_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
2472 #define AFIO_EXTICR4_EXTI15_PD               AFIO_EXTICR4_EXTI15_PD_Msk        /*!< PD[15] pin */
2473 #define AFIO_EXTICR4_EXTI15_PE_Pos           (14U)
2474 #define AFIO_EXTICR4_EXTI15_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
2475 #define AFIO_EXTICR4_EXTI15_PE               AFIO_EXTICR4_EXTI15_PE_Msk        /*!< PE[15] pin */
2476 #define AFIO_EXTICR4_EXTI15_PF_Pos           (12U)
2477 #define AFIO_EXTICR4_EXTI15_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
2478 #define AFIO_EXTICR4_EXTI15_PF               AFIO_EXTICR4_EXTI15_PF_Msk        /*!< PF[15] pin */
2479 #define AFIO_EXTICR4_EXTI15_PG_Pos           (13U)
2480 #define AFIO_EXTICR4_EXTI15_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
2481 #define AFIO_EXTICR4_EXTI15_PG               AFIO_EXTICR4_EXTI15_PG_Msk        /*!< PG[15] pin */
2482 
2483 /******************  Bit definition for AFIO_MAPR2 register  ******************/
2484 
2485 
2486 
2487 /******************************************************************************/
2488 /*                                                                            */
2489 /*                    External Interrupt/Event Controller                     */
2490 /*                                                                            */
2491 /******************************************************************************/
2492 
2493 /*******************  Bit definition for EXTI_IMR register  *******************/
2494 #define EXTI_IMR_MR0_Pos                    (0U)
2495 #define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
2496 #define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
2497 #define EXTI_IMR_MR1_Pos                    (1U)
2498 #define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
2499 #define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
2500 #define EXTI_IMR_MR2_Pos                    (2U)
2501 #define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
2502 #define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
2503 #define EXTI_IMR_MR3_Pos                    (3U)
2504 #define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
2505 #define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
2506 #define EXTI_IMR_MR4_Pos                    (4U)
2507 #define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
2508 #define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
2509 #define EXTI_IMR_MR5_Pos                    (5U)
2510 #define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
2511 #define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
2512 #define EXTI_IMR_MR6_Pos                    (6U)
2513 #define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
2514 #define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
2515 #define EXTI_IMR_MR7_Pos                    (7U)
2516 #define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
2517 #define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
2518 #define EXTI_IMR_MR8_Pos                    (8U)
2519 #define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
2520 #define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
2521 #define EXTI_IMR_MR9_Pos                    (9U)
2522 #define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
2523 #define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
2524 #define EXTI_IMR_MR10_Pos                   (10U)
2525 #define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
2526 #define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
2527 #define EXTI_IMR_MR11_Pos                   (11U)
2528 #define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
2529 #define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
2530 #define EXTI_IMR_MR12_Pos                   (12U)
2531 #define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
2532 #define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
2533 #define EXTI_IMR_MR13_Pos                   (13U)
2534 #define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
2535 #define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
2536 #define EXTI_IMR_MR14_Pos                   (14U)
2537 #define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
2538 #define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
2539 #define EXTI_IMR_MR15_Pos                   (15U)
2540 #define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
2541 #define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
2542 #define EXTI_IMR_MR16_Pos                   (16U)
2543 #define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
2544 #define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
2545 #define EXTI_IMR_MR17_Pos                   (17U)
2546 #define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
2547 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
2548 #define EXTI_IMR_MR18_Pos                   (18U)
2549 #define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
2550 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
2551 
2552 /* References Defines */
2553 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
2554 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
2555 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
2556 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
2557 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
2558 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
2559 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
2560 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
2561 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
2562 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
2563 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
2564 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
2565 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
2566 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
2567 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
2568 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
2569 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
2570 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
2571 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
2572 #define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */
2573 
2574 /*******************  Bit definition for EXTI_EMR register  *******************/
2575 #define EXTI_EMR_MR0_Pos                    (0U)
2576 #define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
2577 #define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
2578 #define EXTI_EMR_MR1_Pos                    (1U)
2579 #define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
2580 #define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
2581 #define EXTI_EMR_MR2_Pos                    (2U)
2582 #define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
2583 #define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
2584 #define EXTI_EMR_MR3_Pos                    (3U)
2585 #define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
2586 #define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
2587 #define EXTI_EMR_MR4_Pos                    (4U)
2588 #define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
2589 #define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
2590 #define EXTI_EMR_MR5_Pos                    (5U)
2591 #define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
2592 #define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
2593 #define EXTI_EMR_MR6_Pos                    (6U)
2594 #define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
2595 #define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
2596 #define EXTI_EMR_MR7_Pos                    (7U)
2597 #define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
2598 #define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
2599 #define EXTI_EMR_MR8_Pos                    (8U)
2600 #define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
2601 #define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
2602 #define EXTI_EMR_MR9_Pos                    (9U)
2603 #define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
2604 #define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
2605 #define EXTI_EMR_MR10_Pos                   (10U)
2606 #define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
2607 #define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
2608 #define EXTI_EMR_MR11_Pos                   (11U)
2609 #define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
2610 #define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
2611 #define EXTI_EMR_MR12_Pos                   (12U)
2612 #define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
2613 #define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
2614 #define EXTI_EMR_MR13_Pos                   (13U)
2615 #define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
2616 #define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
2617 #define EXTI_EMR_MR14_Pos                   (14U)
2618 #define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
2619 #define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
2620 #define EXTI_EMR_MR15_Pos                   (15U)
2621 #define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
2622 #define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
2623 #define EXTI_EMR_MR16_Pos                   (16U)
2624 #define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
2625 #define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
2626 #define EXTI_EMR_MR17_Pos                   (17U)
2627 #define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
2628 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
2629 #define EXTI_EMR_MR18_Pos                   (18U)
2630 #define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
2631 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
2632 
2633 /* References Defines */
2634 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
2635 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
2636 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
2637 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
2638 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
2639 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
2640 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
2641 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
2642 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
2643 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
2644 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
2645 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
2646 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
2647 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
2648 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
2649 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
2650 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
2651 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
2652 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
2653 
2654 /******************  Bit definition for EXTI_RTSR register  *******************/
2655 #define EXTI_RTSR_TR0_Pos                   (0U)
2656 #define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
2657 #define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
2658 #define EXTI_RTSR_TR1_Pos                   (1U)
2659 #define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
2660 #define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
2661 #define EXTI_RTSR_TR2_Pos                   (2U)
2662 #define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
2663 #define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
2664 #define EXTI_RTSR_TR3_Pos                   (3U)
2665 #define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
2666 #define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
2667 #define EXTI_RTSR_TR4_Pos                   (4U)
2668 #define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
2669 #define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
2670 #define EXTI_RTSR_TR5_Pos                   (5U)
2671 #define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
2672 #define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
2673 #define EXTI_RTSR_TR6_Pos                   (6U)
2674 #define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
2675 #define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
2676 #define EXTI_RTSR_TR7_Pos                   (7U)
2677 #define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
2678 #define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
2679 #define EXTI_RTSR_TR8_Pos                   (8U)
2680 #define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
2681 #define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
2682 #define EXTI_RTSR_TR9_Pos                   (9U)
2683 #define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
2684 #define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
2685 #define EXTI_RTSR_TR10_Pos                  (10U)
2686 #define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
2687 #define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
2688 #define EXTI_RTSR_TR11_Pos                  (11U)
2689 #define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
2690 #define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
2691 #define EXTI_RTSR_TR12_Pos                  (12U)
2692 #define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
2693 #define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
2694 #define EXTI_RTSR_TR13_Pos                  (13U)
2695 #define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
2696 #define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
2697 #define EXTI_RTSR_TR14_Pos                  (14U)
2698 #define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
2699 #define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
2700 #define EXTI_RTSR_TR15_Pos                  (15U)
2701 #define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
2702 #define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
2703 #define EXTI_RTSR_TR16_Pos                  (16U)
2704 #define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
2705 #define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
2706 #define EXTI_RTSR_TR17_Pos                  (17U)
2707 #define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
2708 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
2709 #define EXTI_RTSR_TR18_Pos                  (18U)
2710 #define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
2711 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
2712 
2713 /* References Defines */
2714 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
2715 #define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
2716 #define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
2717 #define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
2718 #define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
2719 #define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
2720 #define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
2721 #define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
2722 #define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
2723 #define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
2724 #define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
2725 #define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
2726 #define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
2727 #define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
2728 #define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
2729 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
2730 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
2731 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
2732 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
2733 
2734 /******************  Bit definition for EXTI_FTSR register  *******************/
2735 #define EXTI_FTSR_TR0_Pos                   (0U)
2736 #define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
2737 #define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
2738 #define EXTI_FTSR_TR1_Pos                   (1U)
2739 #define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
2740 #define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
2741 #define EXTI_FTSR_TR2_Pos                   (2U)
2742 #define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
2743 #define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
2744 #define EXTI_FTSR_TR3_Pos                   (3U)
2745 #define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
2746 #define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
2747 #define EXTI_FTSR_TR4_Pos                   (4U)
2748 #define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
2749 #define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
2750 #define EXTI_FTSR_TR5_Pos                   (5U)
2751 #define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
2752 #define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
2753 #define EXTI_FTSR_TR6_Pos                   (6U)
2754 #define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
2755 #define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
2756 #define EXTI_FTSR_TR7_Pos                   (7U)
2757 #define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
2758 #define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
2759 #define EXTI_FTSR_TR8_Pos                   (8U)
2760 #define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
2761 #define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
2762 #define EXTI_FTSR_TR9_Pos                   (9U)
2763 #define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
2764 #define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
2765 #define EXTI_FTSR_TR10_Pos                  (10U)
2766 #define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
2767 #define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
2768 #define EXTI_FTSR_TR11_Pos                  (11U)
2769 #define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
2770 #define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
2771 #define EXTI_FTSR_TR12_Pos                  (12U)
2772 #define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
2773 #define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
2774 #define EXTI_FTSR_TR13_Pos                  (13U)
2775 #define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
2776 #define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
2777 #define EXTI_FTSR_TR14_Pos                  (14U)
2778 #define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
2779 #define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
2780 #define EXTI_FTSR_TR15_Pos                  (15U)
2781 #define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
2782 #define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
2783 #define EXTI_FTSR_TR16_Pos                  (16U)
2784 #define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
2785 #define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
2786 #define EXTI_FTSR_TR17_Pos                  (17U)
2787 #define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
2788 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
2789 #define EXTI_FTSR_TR18_Pos                  (18U)
2790 #define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
2791 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
2792 
2793 /* References Defines */
2794 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
2795 #define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
2796 #define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
2797 #define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
2798 #define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
2799 #define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
2800 #define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
2801 #define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
2802 #define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
2803 #define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
2804 #define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
2805 #define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
2806 #define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
2807 #define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
2808 #define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
2809 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
2810 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
2811 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
2812 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
2813 
2814 /******************  Bit definition for EXTI_SWIER register  ******************/
2815 #define EXTI_SWIER_SWIER0_Pos               (0U)
2816 #define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
2817 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
2818 #define EXTI_SWIER_SWIER1_Pos               (1U)
2819 #define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
2820 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
2821 #define EXTI_SWIER_SWIER2_Pos               (2U)
2822 #define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
2823 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
2824 #define EXTI_SWIER_SWIER3_Pos               (3U)
2825 #define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
2826 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
2827 #define EXTI_SWIER_SWIER4_Pos               (4U)
2828 #define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
2829 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
2830 #define EXTI_SWIER_SWIER5_Pos               (5U)
2831 #define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
2832 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
2833 #define EXTI_SWIER_SWIER6_Pos               (6U)
2834 #define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
2835 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
2836 #define EXTI_SWIER_SWIER7_Pos               (7U)
2837 #define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
2838 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
2839 #define EXTI_SWIER_SWIER8_Pos               (8U)
2840 #define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
2841 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
2842 #define EXTI_SWIER_SWIER9_Pos               (9U)
2843 #define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
2844 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
2845 #define EXTI_SWIER_SWIER10_Pos              (10U)
2846 #define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
2847 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
2848 #define EXTI_SWIER_SWIER11_Pos              (11U)
2849 #define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
2850 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
2851 #define EXTI_SWIER_SWIER12_Pos              (12U)
2852 #define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
2853 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
2854 #define EXTI_SWIER_SWIER13_Pos              (13U)
2855 #define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
2856 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
2857 #define EXTI_SWIER_SWIER14_Pos              (14U)
2858 #define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
2859 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
2860 #define EXTI_SWIER_SWIER15_Pos              (15U)
2861 #define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
2862 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
2863 #define EXTI_SWIER_SWIER16_Pos              (16U)
2864 #define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
2865 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
2866 #define EXTI_SWIER_SWIER17_Pos              (17U)
2867 #define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
2868 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
2869 #define EXTI_SWIER_SWIER18_Pos              (18U)
2870 #define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
2871 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
2872 
2873 /* References Defines */
2874 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2875 #define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2876 #define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2877 #define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2878 #define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2879 #define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2880 #define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2881 #define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2882 #define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2883 #define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2884 #define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2885 #define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2886 #define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2887 #define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2888 #define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2889 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2890 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2891 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2892 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
2893 
2894 /*******************  Bit definition for EXTI_PR register  ********************/
2895 #define EXTI_PR_PR0_Pos                     (0U)
2896 #define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
2897 #define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
2898 #define EXTI_PR_PR1_Pos                     (1U)
2899 #define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
2900 #define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
2901 #define EXTI_PR_PR2_Pos                     (2U)
2902 #define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
2903 #define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
2904 #define EXTI_PR_PR3_Pos                     (3U)
2905 #define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
2906 #define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
2907 #define EXTI_PR_PR4_Pos                     (4U)
2908 #define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
2909 #define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
2910 #define EXTI_PR_PR5_Pos                     (5U)
2911 #define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
2912 #define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
2913 #define EXTI_PR_PR6_Pos                     (6U)
2914 #define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
2915 #define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
2916 #define EXTI_PR_PR7_Pos                     (7U)
2917 #define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
2918 #define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
2919 #define EXTI_PR_PR8_Pos                     (8U)
2920 #define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
2921 #define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
2922 #define EXTI_PR_PR9_Pos                     (9U)
2923 #define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
2924 #define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
2925 #define EXTI_PR_PR10_Pos                    (10U)
2926 #define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
2927 #define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
2928 #define EXTI_PR_PR11_Pos                    (11U)
2929 #define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
2930 #define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
2931 #define EXTI_PR_PR12_Pos                    (12U)
2932 #define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
2933 #define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
2934 #define EXTI_PR_PR13_Pos                    (13U)
2935 #define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
2936 #define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
2937 #define EXTI_PR_PR14_Pos                    (14U)
2938 #define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
2939 #define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
2940 #define EXTI_PR_PR15_Pos                    (15U)
2941 #define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
2942 #define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
2943 #define EXTI_PR_PR16_Pos                    (16U)
2944 #define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
2945 #define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
2946 #define EXTI_PR_PR17_Pos                    (17U)
2947 #define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
2948 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
2949 #define EXTI_PR_PR18_Pos                    (18U)
2950 #define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
2951 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
2952 
2953 /* References Defines */
2954 #define  EXTI_PR_PIF0 EXTI_PR_PR0
2955 #define  EXTI_PR_PIF1 EXTI_PR_PR1
2956 #define  EXTI_PR_PIF2 EXTI_PR_PR2
2957 #define  EXTI_PR_PIF3 EXTI_PR_PR3
2958 #define  EXTI_PR_PIF4 EXTI_PR_PR4
2959 #define  EXTI_PR_PIF5 EXTI_PR_PR5
2960 #define  EXTI_PR_PIF6 EXTI_PR_PR6
2961 #define  EXTI_PR_PIF7 EXTI_PR_PR7
2962 #define  EXTI_PR_PIF8 EXTI_PR_PR8
2963 #define  EXTI_PR_PIF9 EXTI_PR_PR9
2964 #define  EXTI_PR_PIF10 EXTI_PR_PR10
2965 #define  EXTI_PR_PIF11 EXTI_PR_PR11
2966 #define  EXTI_PR_PIF12 EXTI_PR_PR12
2967 #define  EXTI_PR_PIF13 EXTI_PR_PR13
2968 #define  EXTI_PR_PIF14 EXTI_PR_PR14
2969 #define  EXTI_PR_PIF15 EXTI_PR_PR15
2970 #define  EXTI_PR_PIF16 EXTI_PR_PR16
2971 #define  EXTI_PR_PIF17 EXTI_PR_PR17
2972 #define  EXTI_PR_PIF18 EXTI_PR_PR18
2973 
2974 /******************************************************************************/
2975 /*                                                                            */
2976 /*                             DMA Controller                                 */
2977 /*                                                                            */
2978 /******************************************************************************/
2979 
2980 /*******************  Bit definition for DMA_ISR register  ********************/
2981 #define DMA_ISR_GIF1_Pos                    (0U)
2982 #define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
2983 #define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
2984 #define DMA_ISR_TCIF1_Pos                   (1U)
2985 #define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
2986 #define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
2987 #define DMA_ISR_HTIF1_Pos                   (2U)
2988 #define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
2989 #define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
2990 #define DMA_ISR_TEIF1_Pos                   (3U)
2991 #define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
2992 #define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
2993 #define DMA_ISR_GIF2_Pos                    (4U)
2994 #define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
2995 #define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
2996 #define DMA_ISR_TCIF2_Pos                   (5U)
2997 #define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
2998 #define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
2999 #define DMA_ISR_HTIF2_Pos                   (6U)
3000 #define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
3001 #define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
3002 #define DMA_ISR_TEIF2_Pos                   (7U)
3003 #define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
3004 #define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
3005 #define DMA_ISR_GIF3_Pos                    (8U)
3006 #define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
3007 #define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
3008 #define DMA_ISR_TCIF3_Pos                   (9U)
3009 #define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
3010 #define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
3011 #define DMA_ISR_HTIF3_Pos                   (10U)
3012 #define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
3013 #define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
3014 #define DMA_ISR_TEIF3_Pos                   (11U)
3015 #define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
3016 #define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
3017 #define DMA_ISR_GIF4_Pos                    (12U)
3018 #define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
3019 #define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
3020 #define DMA_ISR_TCIF4_Pos                   (13U)
3021 #define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
3022 #define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
3023 #define DMA_ISR_HTIF4_Pos                   (14U)
3024 #define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
3025 #define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
3026 #define DMA_ISR_TEIF4_Pos                   (15U)
3027 #define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
3028 #define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
3029 #define DMA_ISR_GIF5_Pos                    (16U)
3030 #define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
3031 #define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
3032 #define DMA_ISR_TCIF5_Pos                   (17U)
3033 #define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
3034 #define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
3035 #define DMA_ISR_HTIF5_Pos                   (18U)
3036 #define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
3037 #define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
3038 #define DMA_ISR_TEIF5_Pos                   (19U)
3039 #define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
3040 #define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
3041 #define DMA_ISR_GIF6_Pos                    (20U)
3042 #define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
3043 #define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
3044 #define DMA_ISR_TCIF6_Pos                   (21U)
3045 #define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
3046 #define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
3047 #define DMA_ISR_HTIF6_Pos                   (22U)
3048 #define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
3049 #define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
3050 #define DMA_ISR_TEIF6_Pos                   (23U)
3051 #define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
3052 #define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
3053 #define DMA_ISR_GIF7_Pos                    (24U)
3054 #define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
3055 #define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
3056 #define DMA_ISR_TCIF7_Pos                   (25U)
3057 #define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
3058 #define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
3059 #define DMA_ISR_HTIF7_Pos                   (26U)
3060 #define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
3061 #define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
3062 #define DMA_ISR_TEIF7_Pos                   (27U)
3063 #define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
3064 #define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
3065 
3066 /*******************  Bit definition for DMA_IFCR register  *******************/
3067 #define DMA_IFCR_CGIF1_Pos                  (0U)
3068 #define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
3069 #define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
3070 #define DMA_IFCR_CTCIF1_Pos                 (1U)
3071 #define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
3072 #define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
3073 #define DMA_IFCR_CHTIF1_Pos                 (2U)
3074 #define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
3075 #define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
3076 #define DMA_IFCR_CTEIF1_Pos                 (3U)
3077 #define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
3078 #define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
3079 #define DMA_IFCR_CGIF2_Pos                  (4U)
3080 #define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
3081 #define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
3082 #define DMA_IFCR_CTCIF2_Pos                 (5U)
3083 #define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
3084 #define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
3085 #define DMA_IFCR_CHTIF2_Pos                 (6U)
3086 #define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
3087 #define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
3088 #define DMA_IFCR_CTEIF2_Pos                 (7U)
3089 #define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
3090 #define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
3091 #define DMA_IFCR_CGIF3_Pos                  (8U)
3092 #define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
3093 #define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
3094 #define DMA_IFCR_CTCIF3_Pos                 (9U)
3095 #define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
3096 #define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
3097 #define DMA_IFCR_CHTIF3_Pos                 (10U)
3098 #define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
3099 #define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
3100 #define DMA_IFCR_CTEIF3_Pos                 (11U)
3101 #define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
3102 #define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
3103 #define DMA_IFCR_CGIF4_Pos                  (12U)
3104 #define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
3105 #define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
3106 #define DMA_IFCR_CTCIF4_Pos                 (13U)
3107 #define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
3108 #define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
3109 #define DMA_IFCR_CHTIF4_Pos                 (14U)
3110 #define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
3111 #define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
3112 #define DMA_IFCR_CTEIF4_Pos                 (15U)
3113 #define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
3114 #define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
3115 #define DMA_IFCR_CGIF5_Pos                  (16U)
3116 #define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
3117 #define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
3118 #define DMA_IFCR_CTCIF5_Pos                 (17U)
3119 #define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
3120 #define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
3121 #define DMA_IFCR_CHTIF5_Pos                 (18U)
3122 #define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
3123 #define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
3124 #define DMA_IFCR_CTEIF5_Pos                 (19U)
3125 #define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
3126 #define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
3127 #define DMA_IFCR_CGIF6_Pos                  (20U)
3128 #define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
3129 #define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
3130 #define DMA_IFCR_CTCIF6_Pos                 (21U)
3131 #define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
3132 #define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
3133 #define DMA_IFCR_CHTIF6_Pos                 (22U)
3134 #define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
3135 #define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
3136 #define DMA_IFCR_CTEIF6_Pos                 (23U)
3137 #define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
3138 #define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
3139 #define DMA_IFCR_CGIF7_Pos                  (24U)
3140 #define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
3141 #define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
3142 #define DMA_IFCR_CTCIF7_Pos                 (25U)
3143 #define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
3144 #define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
3145 #define DMA_IFCR_CHTIF7_Pos                 (26U)
3146 #define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
3147 #define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
3148 #define DMA_IFCR_CTEIF7_Pos                 (27U)
3149 #define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
3150 #define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
3151 
3152 /*******************  Bit definition for DMA_CCR register   *******************/
3153 #define DMA_CCR_EN_Pos                      (0U)
3154 #define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
3155 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable */
3156 #define DMA_CCR_TCIE_Pos                    (1U)
3157 #define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
3158 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
3159 #define DMA_CCR_HTIE_Pos                    (2U)
3160 #define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
3161 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
3162 #define DMA_CCR_TEIE_Pos                    (3U)
3163 #define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
3164 #define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
3165 #define DMA_CCR_DIR_Pos                     (4U)
3166 #define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
3167 #define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
3168 #define DMA_CCR_CIRC_Pos                    (5U)
3169 #define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
3170 #define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
3171 #define DMA_CCR_PINC_Pos                    (6U)
3172 #define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
3173 #define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
3174 #define DMA_CCR_MINC_Pos                    (7U)
3175 #define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
3176 #define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
3177 
3178 #define DMA_CCR_PSIZE_Pos                   (8U)
3179 #define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
3180 #define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
3181 #define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
3182 #define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
3183 
3184 #define DMA_CCR_MSIZE_Pos                   (10U)
3185 #define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
3186 #define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
3187 #define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
3188 #define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
3189 
3190 #define DMA_CCR_PL_Pos                      (12U)
3191 #define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
3192 #define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
3193 #define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
3194 #define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
3195 
3196 #define DMA_CCR_MEM2MEM_Pos                 (14U)
3197 #define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
3198 #define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
3199 
3200 /******************  Bit definition for DMA_CNDTR  register  ******************/
3201 #define DMA_CNDTR_NDT_Pos                   (0U)
3202 #define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
3203 #define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
3204 
3205 /******************  Bit definition for DMA_CPAR  register  *******************/
3206 #define DMA_CPAR_PA_Pos                     (0U)
3207 #define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
3208 #define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
3209 
3210 /******************  Bit definition for DMA_CMAR  register  *******************/
3211 #define DMA_CMAR_MA_Pos                     (0U)
3212 #define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
3213 #define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
3214 
3215 /******************************************************************************/
3216 /*                                                                            */
3217 /*                      Analog to Digital Converter (ADC)                     */
3218 /*                                                                            */
3219 /******************************************************************************/
3220 
3221 /*
3222  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3223  */
3224 #define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3225 
3226 /********************  Bit definition for ADC_SR register  ********************/
3227 #define ADC_SR_AWD_Pos                      (0U)
3228 #define ADC_SR_AWD_Msk                      (0x1UL << ADC_SR_AWD_Pos)           /*!< 0x00000001 */
3229 #define ADC_SR_AWD                          ADC_SR_AWD_Msk                     /*!< ADC analog watchdog 1 flag */
3230 #define ADC_SR_EOS_Pos                      (1U)
3231 #define ADC_SR_EOS_Msk                      (0x1UL << ADC_SR_EOS_Pos)           /*!< 0x00000002 */
3232 #define ADC_SR_EOS                          ADC_SR_EOS_Msk                     /*!< ADC group regular end of sequence conversions flag */
3233 #define ADC_SR_JEOS_Pos                     (2U)
3234 #define ADC_SR_JEOS_Msk                     (0x1UL << ADC_SR_JEOS_Pos)          /*!< 0x00000004 */
3235 #define ADC_SR_JEOS                         ADC_SR_JEOS_Msk                    /*!< ADC group injected end of sequence conversions flag */
3236 #define ADC_SR_JSTRT_Pos                    (3U)
3237 #define ADC_SR_JSTRT_Msk                    (0x1UL << ADC_SR_JSTRT_Pos)         /*!< 0x00000008 */
3238 #define ADC_SR_JSTRT                        ADC_SR_JSTRT_Msk                   /*!< ADC group injected conversion start flag */
3239 #define ADC_SR_STRT_Pos                     (4U)
3240 #define ADC_SR_STRT_Msk                     (0x1UL << ADC_SR_STRT_Pos)          /*!< 0x00000010 */
3241 #define ADC_SR_STRT                         ADC_SR_STRT_Msk                    /*!< ADC group regular conversion start flag */
3242 
3243 /* Legacy defines */
3244 #define  ADC_SR_EOC                          (ADC_SR_EOS)
3245 #define  ADC_SR_JEOC                         (ADC_SR_JEOS)
3246 
3247 /*******************  Bit definition for ADC_CR1 register  ********************/
3248 #define ADC_CR1_AWDCH_Pos                   (0U)
3249 #define ADC_CR1_AWDCH_Msk                   (0x1FUL << ADC_CR1_AWDCH_Pos)       /*!< 0x0000001F */
3250 #define ADC_CR1_AWDCH                       ADC_CR1_AWDCH_Msk                  /*!< ADC analog watchdog 1 monitored channel selection */
3251 #define ADC_CR1_AWDCH_0                     (0x01UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000001 */
3252 #define ADC_CR1_AWDCH_1                     (0x02UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000002 */
3253 #define ADC_CR1_AWDCH_2                     (0x04UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000004 */
3254 #define ADC_CR1_AWDCH_3                     (0x08UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000008 */
3255 #define ADC_CR1_AWDCH_4                     (0x10UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000010 */
3256 
3257 #define ADC_CR1_EOSIE_Pos                   (5U)
3258 #define ADC_CR1_EOSIE_Msk                   (0x1UL << ADC_CR1_EOSIE_Pos)        /*!< 0x00000020 */
3259 #define ADC_CR1_EOSIE                       ADC_CR1_EOSIE_Msk                  /*!< ADC group regular end of sequence conversions interrupt */
3260 #define ADC_CR1_AWDIE_Pos                   (6U)
3261 #define ADC_CR1_AWDIE_Msk                   (0x1UL << ADC_CR1_AWDIE_Pos)        /*!< 0x00000040 */
3262 #define ADC_CR1_AWDIE                       ADC_CR1_AWDIE_Msk                  /*!< ADC analog watchdog 1 interrupt */
3263 #define ADC_CR1_JEOSIE_Pos                  (7U)
3264 #define ADC_CR1_JEOSIE_Msk                  (0x1UL << ADC_CR1_JEOSIE_Pos)       /*!< 0x00000080 */
3265 #define ADC_CR1_JEOSIE                      ADC_CR1_JEOSIE_Msk                 /*!< ADC group injected end of sequence conversions interrupt */
3266 #define ADC_CR1_SCAN_Pos                    (8U)
3267 #define ADC_CR1_SCAN_Msk                    (0x1UL << ADC_CR1_SCAN_Pos)         /*!< 0x00000100 */
3268 #define ADC_CR1_SCAN                        ADC_CR1_SCAN_Msk                   /*!< ADC scan mode */
3269 #define ADC_CR1_AWDSGL_Pos                  (9U)
3270 #define ADC_CR1_AWDSGL_Msk                  (0x1UL << ADC_CR1_AWDSGL_Pos)       /*!< 0x00000200 */
3271 #define ADC_CR1_AWDSGL                      ADC_CR1_AWDSGL_Msk                 /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3272 #define ADC_CR1_JAUTO_Pos                   (10U)
3273 #define ADC_CR1_JAUTO_Msk                   (0x1UL << ADC_CR1_JAUTO_Pos)        /*!< 0x00000400 */
3274 #define ADC_CR1_JAUTO                       ADC_CR1_JAUTO_Msk                  /*!< ADC group injected automatic trigger mode */
3275 #define ADC_CR1_DISCEN_Pos                  (11U)
3276 #define ADC_CR1_DISCEN_Msk                  (0x1UL << ADC_CR1_DISCEN_Pos)       /*!< 0x00000800 */
3277 #define ADC_CR1_DISCEN                      ADC_CR1_DISCEN_Msk                 /*!< ADC group regular sequencer discontinuous mode */
3278 #define ADC_CR1_JDISCEN_Pos                 (12U)
3279 #define ADC_CR1_JDISCEN_Msk                 (0x1UL << ADC_CR1_JDISCEN_Pos)      /*!< 0x00001000 */
3280 #define ADC_CR1_JDISCEN                     ADC_CR1_JDISCEN_Msk                /*!< ADC group injected sequencer discontinuous mode */
3281 
3282 #define ADC_CR1_DISCNUM_Pos                 (13U)
3283 #define ADC_CR1_DISCNUM_Msk                 (0x7UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x0000E000 */
3284 #define ADC_CR1_DISCNUM                     ADC_CR1_DISCNUM_Msk                /*!< ADC group regular sequencer discontinuous number of ranks */
3285 #define ADC_CR1_DISCNUM_0                   (0x1UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00002000 */
3286 #define ADC_CR1_DISCNUM_1                   (0x2UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */
3287 #define ADC_CR1_DISCNUM_2                   (0x4UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */
3288 
3289 #define ADC_CR1_DUALMOD_Pos                 (16U)
3290 #define ADC_CR1_DUALMOD_Msk                 (0xFUL << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */
3291 #define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */
3292 #define ADC_CR1_DUALMOD_0                   (0x1UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */
3293 #define ADC_CR1_DUALMOD_1                   (0x2UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */
3294 #define ADC_CR1_DUALMOD_2                   (0x4UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */
3295 #define ADC_CR1_DUALMOD_3                   (0x8UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */
3296 
3297 #define ADC_CR1_JAWDEN_Pos                  (22U)
3298 #define ADC_CR1_JAWDEN_Msk                  (0x1UL << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */
3299 #define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3300 #define ADC_CR1_AWDEN_Pos                   (23U)
3301 #define ADC_CR1_AWDEN_Msk                   (0x1UL << ADC_CR1_AWDEN_Pos)        /*!< 0x00800000 */
3302 #define ADC_CR1_AWDEN                       ADC_CR1_AWDEN_Msk                  /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3303 
3304 /* Legacy defines */
3305 #define  ADC_CR1_EOCIE                       (ADC_CR1_EOSIE)
3306 #define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
3307 
3308 /*******************  Bit definition for ADC_CR2 register  ********************/
3309 #define ADC_CR2_ADON_Pos                    (0U)
3310 #define ADC_CR2_ADON_Msk                    (0x1UL << ADC_CR2_ADON_Pos)         /*!< 0x00000001 */
3311 #define ADC_CR2_ADON                        ADC_CR2_ADON_Msk                   /*!< ADC enable */
3312 #define ADC_CR2_CONT_Pos                    (1U)
3313 #define ADC_CR2_CONT_Msk                    (0x1UL << ADC_CR2_CONT_Pos)         /*!< 0x00000002 */
3314 #define ADC_CR2_CONT                        ADC_CR2_CONT_Msk                   /*!< ADC group regular continuous conversion mode */
3315 #define ADC_CR2_CAL_Pos                     (2U)
3316 #define ADC_CR2_CAL_Msk                     (0x1UL << ADC_CR2_CAL_Pos)          /*!< 0x00000004 */
3317 #define ADC_CR2_CAL                         ADC_CR2_CAL_Msk                    /*!< ADC calibration start */
3318 #define ADC_CR2_RSTCAL_Pos                  (3U)
3319 #define ADC_CR2_RSTCAL_Msk                  (0x1UL << ADC_CR2_RSTCAL_Pos)       /*!< 0x00000008 */
3320 #define ADC_CR2_RSTCAL                      ADC_CR2_RSTCAL_Msk                 /*!< ADC calibration reset */
3321 #define ADC_CR2_DMA_Pos                     (8U)
3322 #define ADC_CR2_DMA_Msk                     (0x1UL << ADC_CR2_DMA_Pos)          /*!< 0x00000100 */
3323 #define ADC_CR2_DMA                         ADC_CR2_DMA_Msk                    /*!< ADC DMA transfer enable */
3324 #define ADC_CR2_ALIGN_Pos                   (11U)
3325 #define ADC_CR2_ALIGN_Msk                   (0x1UL << ADC_CR2_ALIGN_Pos)        /*!< 0x00000800 */
3326 #define ADC_CR2_ALIGN                       ADC_CR2_ALIGN_Msk                  /*!< ADC data alignment */
3327 
3328 #define ADC_CR2_JEXTSEL_Pos                 (12U)
3329 #define ADC_CR2_JEXTSEL_Msk                 (0x7UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00007000 */
3330 #define ADC_CR2_JEXTSEL                     ADC_CR2_JEXTSEL_Msk                /*!< ADC group injected external trigger source */
3331 #define ADC_CR2_JEXTSEL_0                   (0x1UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00001000 */
3332 #define ADC_CR2_JEXTSEL_1                   (0x2UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00002000 */
3333 #define ADC_CR2_JEXTSEL_2                   (0x4UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00004000 */
3334 
3335 #define ADC_CR2_JEXTTRIG_Pos                (15U)
3336 #define ADC_CR2_JEXTTRIG_Msk                (0x1UL << ADC_CR2_JEXTTRIG_Pos)     /*!< 0x00008000 */
3337 #define ADC_CR2_JEXTTRIG                    ADC_CR2_JEXTTRIG_Msk               /*!< ADC group injected external trigger enable */
3338 
3339 #define ADC_CR2_EXTSEL_Pos                  (17U)
3340 #define ADC_CR2_EXTSEL_Msk                  (0x7UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x000E0000 */
3341 #define ADC_CR2_EXTSEL                      ADC_CR2_EXTSEL_Msk                 /*!< ADC group regular external trigger source */
3342 #define ADC_CR2_EXTSEL_0                    (0x1UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00020000 */
3343 #define ADC_CR2_EXTSEL_1                    (0x2UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00040000 */
3344 #define ADC_CR2_EXTSEL_2                    (0x4UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00080000 */
3345 
3346 #define ADC_CR2_EXTTRIG_Pos                 (20U)
3347 #define ADC_CR2_EXTTRIG_Msk                 (0x1UL << ADC_CR2_EXTTRIG_Pos)      /*!< 0x00100000 */
3348 #define ADC_CR2_EXTTRIG                     ADC_CR2_EXTTRIG_Msk                /*!< ADC group regular external trigger enable */
3349 #define ADC_CR2_JSWSTART_Pos                (21U)
3350 #define ADC_CR2_JSWSTART_Msk                (0x1UL << ADC_CR2_JSWSTART_Pos)     /*!< 0x00200000 */
3351 #define ADC_CR2_JSWSTART                    ADC_CR2_JSWSTART_Msk               /*!< ADC group injected conversion start */
3352 #define ADC_CR2_SWSTART_Pos                 (22U)
3353 #define ADC_CR2_SWSTART_Msk                 (0x1UL << ADC_CR2_SWSTART_Pos)      /*!< 0x00400000 */
3354 #define ADC_CR2_SWSTART                     ADC_CR2_SWSTART_Msk                /*!< ADC group regular conversion start */
3355 #define ADC_CR2_TSVREFE_Pos                 (23U)
3356 #define ADC_CR2_TSVREFE_Msk                 (0x1UL << ADC_CR2_TSVREFE_Pos)      /*!< 0x00800000 */
3357 #define ADC_CR2_TSVREFE                     ADC_CR2_TSVREFE_Msk                /*!< ADC internal path to VrefInt and temperature sensor enable */
3358 
3359 /******************  Bit definition for ADC_SMPR1 register  *******************/
3360 #define ADC_SMPR1_SMP10_Pos                 (0U)
3361 #define ADC_SMPR1_SMP10_Msk                 (0x7UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000007 */
3362 #define ADC_SMPR1_SMP10                     ADC_SMPR1_SMP10_Msk                /*!< ADC channel 10 sampling time selection  */
3363 #define ADC_SMPR1_SMP10_0                   (0x1UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000001 */
3364 #define ADC_SMPR1_SMP10_1                   (0x2UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000002 */
3365 #define ADC_SMPR1_SMP10_2                   (0x4UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000004 */
3366 
3367 #define ADC_SMPR1_SMP11_Pos                 (3U)
3368 #define ADC_SMPR1_SMP11_Msk                 (0x7UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000038 */
3369 #define ADC_SMPR1_SMP11                     ADC_SMPR1_SMP11_Msk                /*!< ADC channel 11 sampling time selection  */
3370 #define ADC_SMPR1_SMP11_0                   (0x1UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000008 */
3371 #define ADC_SMPR1_SMP11_1                   (0x2UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000010 */
3372 #define ADC_SMPR1_SMP11_2                   (0x4UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000020 */
3373 
3374 #define ADC_SMPR1_SMP12_Pos                 (6U)
3375 #define ADC_SMPR1_SMP12_Msk                 (0x7UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x000001C0 */
3376 #define ADC_SMPR1_SMP12                     ADC_SMPR1_SMP12_Msk                /*!< ADC channel 12 sampling time selection  */
3377 #define ADC_SMPR1_SMP12_0                   (0x1UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000040 */
3378 #define ADC_SMPR1_SMP12_1                   (0x2UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000080 */
3379 #define ADC_SMPR1_SMP12_2                   (0x4UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000100 */
3380 
3381 #define ADC_SMPR1_SMP13_Pos                 (9U)
3382 #define ADC_SMPR1_SMP13_Msk                 (0x7UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000E00 */
3383 #define ADC_SMPR1_SMP13                     ADC_SMPR1_SMP13_Msk                /*!< ADC channel 13 sampling time selection  */
3384 #define ADC_SMPR1_SMP13_0                   (0x1UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000200 */
3385 #define ADC_SMPR1_SMP13_1                   (0x2UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000400 */
3386 #define ADC_SMPR1_SMP13_2                   (0x4UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000800 */
3387 
3388 #define ADC_SMPR1_SMP14_Pos                 (12U)
3389 #define ADC_SMPR1_SMP14_Msk                 (0x7UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00007000 */
3390 #define ADC_SMPR1_SMP14                     ADC_SMPR1_SMP14_Msk                /*!< ADC channel 14 sampling time selection  */
3391 #define ADC_SMPR1_SMP14_0                   (0x1UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00001000 */
3392 #define ADC_SMPR1_SMP14_1                   (0x2UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00002000 */
3393 #define ADC_SMPR1_SMP14_2                   (0x4UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00004000 */
3394 
3395 #define ADC_SMPR1_SMP15_Pos                 (15U)
3396 #define ADC_SMPR1_SMP15_Msk                 (0x7UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00038000 */
3397 #define ADC_SMPR1_SMP15                     ADC_SMPR1_SMP15_Msk                /*!< ADC channel 15 sampling time selection  */
3398 #define ADC_SMPR1_SMP15_0                   (0x1UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00008000 */
3399 #define ADC_SMPR1_SMP15_1                   (0x2UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00010000 */
3400 #define ADC_SMPR1_SMP15_2                   (0x4UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00020000 */
3401 
3402 #define ADC_SMPR1_SMP16_Pos                 (18U)
3403 #define ADC_SMPR1_SMP16_Msk                 (0x7UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x001C0000 */
3404 #define ADC_SMPR1_SMP16                     ADC_SMPR1_SMP16_Msk                /*!< ADC channel 16 sampling time selection  */
3405 #define ADC_SMPR1_SMP16_0                   (0x1UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00040000 */
3406 #define ADC_SMPR1_SMP16_1                   (0x2UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00080000 */
3407 #define ADC_SMPR1_SMP16_2                   (0x4UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00100000 */
3408 
3409 #define ADC_SMPR1_SMP17_Pos                 (21U)
3410 #define ADC_SMPR1_SMP17_Msk                 (0x7UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00E00000 */
3411 #define ADC_SMPR1_SMP17                     ADC_SMPR1_SMP17_Msk                /*!< ADC channel 17 sampling time selection  */
3412 #define ADC_SMPR1_SMP17_0                   (0x1UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00200000 */
3413 #define ADC_SMPR1_SMP17_1                   (0x2UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00400000 */
3414 #define ADC_SMPR1_SMP17_2                   (0x4UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00800000 */
3415 
3416 /******************  Bit definition for ADC_SMPR2 register  *******************/
3417 #define ADC_SMPR2_SMP0_Pos                  (0U)
3418 #define ADC_SMPR2_SMP0_Msk                  (0x7UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000007 */
3419 #define ADC_SMPR2_SMP0                      ADC_SMPR2_SMP0_Msk                 /*!< ADC channel 0 sampling time selection  */
3420 #define ADC_SMPR2_SMP0_0                    (0x1UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000001 */
3421 #define ADC_SMPR2_SMP0_1                    (0x2UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000002 */
3422 #define ADC_SMPR2_SMP0_2                    (0x4UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000004 */
3423 
3424 #define ADC_SMPR2_SMP1_Pos                  (3U)
3425 #define ADC_SMPR2_SMP1_Msk                  (0x7UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000038 */
3426 #define ADC_SMPR2_SMP1                      ADC_SMPR2_SMP1_Msk                 /*!< ADC channel 1 sampling time selection  */
3427 #define ADC_SMPR2_SMP1_0                    (0x1UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000008 */
3428 #define ADC_SMPR2_SMP1_1                    (0x2UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000010 */
3429 #define ADC_SMPR2_SMP1_2                    (0x4UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000020 */
3430 
3431 #define ADC_SMPR2_SMP2_Pos                  (6U)
3432 #define ADC_SMPR2_SMP2_Msk                  (0x7UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x000001C0 */
3433 #define ADC_SMPR2_SMP2                      ADC_SMPR2_SMP2_Msk                 /*!< ADC channel 2 sampling time selection  */
3434 #define ADC_SMPR2_SMP2_0                    (0x1UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000040 */
3435 #define ADC_SMPR2_SMP2_1                    (0x2UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000080 */
3436 #define ADC_SMPR2_SMP2_2                    (0x4UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000100 */
3437 
3438 #define ADC_SMPR2_SMP3_Pos                  (9U)
3439 #define ADC_SMPR2_SMP3_Msk                  (0x7UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000E00 */
3440 #define ADC_SMPR2_SMP3                      ADC_SMPR2_SMP3_Msk                 /*!< ADC channel 3 sampling time selection  */
3441 #define ADC_SMPR2_SMP3_0                    (0x1UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000200 */
3442 #define ADC_SMPR2_SMP3_1                    (0x2UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000400 */
3443 #define ADC_SMPR2_SMP3_2                    (0x4UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000800 */
3444 
3445 #define ADC_SMPR2_SMP4_Pos                  (12U)
3446 #define ADC_SMPR2_SMP4_Msk                  (0x7UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00007000 */
3447 #define ADC_SMPR2_SMP4                      ADC_SMPR2_SMP4_Msk                 /*!< ADC channel 4 sampling time selection  */
3448 #define ADC_SMPR2_SMP4_0                    (0x1UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00001000 */
3449 #define ADC_SMPR2_SMP4_1                    (0x2UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00002000 */
3450 #define ADC_SMPR2_SMP4_2                    (0x4UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00004000 */
3451 
3452 #define ADC_SMPR2_SMP5_Pos                  (15U)
3453 #define ADC_SMPR2_SMP5_Msk                  (0x7UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00038000 */
3454 #define ADC_SMPR2_SMP5                      ADC_SMPR2_SMP5_Msk                 /*!< ADC channel 5 sampling time selection  */
3455 #define ADC_SMPR2_SMP5_0                    (0x1UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00008000 */
3456 #define ADC_SMPR2_SMP5_1                    (0x2UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00010000 */
3457 #define ADC_SMPR2_SMP5_2                    (0x4UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00020000 */
3458 
3459 #define ADC_SMPR2_SMP6_Pos                  (18U)
3460 #define ADC_SMPR2_SMP6_Msk                  (0x7UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x001C0000 */
3461 #define ADC_SMPR2_SMP6                      ADC_SMPR2_SMP6_Msk                 /*!< ADC channel 6 sampling time selection  */
3462 #define ADC_SMPR2_SMP6_0                    (0x1UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00040000 */
3463 #define ADC_SMPR2_SMP6_1                    (0x2UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00080000 */
3464 #define ADC_SMPR2_SMP6_2                    (0x4UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00100000 */
3465 
3466 #define ADC_SMPR2_SMP7_Pos                  (21U)
3467 #define ADC_SMPR2_SMP7_Msk                  (0x7UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00E00000 */
3468 #define ADC_SMPR2_SMP7                      ADC_SMPR2_SMP7_Msk                 /*!< ADC channel 7 sampling time selection  */
3469 #define ADC_SMPR2_SMP7_0                    (0x1UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00200000 */
3470 #define ADC_SMPR2_SMP7_1                    (0x2UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00400000 */
3471 #define ADC_SMPR2_SMP7_2                    (0x4UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00800000 */
3472 
3473 #define ADC_SMPR2_SMP8_Pos                  (24U)
3474 #define ADC_SMPR2_SMP8_Msk                  (0x7UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x07000000 */
3475 #define ADC_SMPR2_SMP8                      ADC_SMPR2_SMP8_Msk                 /*!< ADC channel 8 sampling time selection  */
3476 #define ADC_SMPR2_SMP8_0                    (0x1UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x01000000 */
3477 #define ADC_SMPR2_SMP8_1                    (0x2UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x02000000 */
3478 #define ADC_SMPR2_SMP8_2                    (0x4UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x04000000 */
3479 
3480 #define ADC_SMPR2_SMP9_Pos                  (27U)
3481 #define ADC_SMPR2_SMP9_Msk                  (0x7UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x38000000 */
3482 #define ADC_SMPR2_SMP9                      ADC_SMPR2_SMP9_Msk                 /*!< ADC channel 9 sampling time selection  */
3483 #define ADC_SMPR2_SMP9_0                    (0x1UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x08000000 */
3484 #define ADC_SMPR2_SMP9_1                    (0x2UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x10000000 */
3485 #define ADC_SMPR2_SMP9_2                    (0x4UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x20000000 */
3486 
3487 /******************  Bit definition for ADC_JOFR1 register  *******************/
3488 #define ADC_JOFR1_JOFFSET1_Pos              (0U)
3489 #define ADC_JOFR1_JOFFSET1_Msk              (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
3490 #define ADC_JOFR1_JOFFSET1                  ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */
3491 
3492 /******************  Bit definition for ADC_JOFR2 register  *******************/
3493 #define ADC_JOFR2_JOFFSET2_Pos              (0U)
3494 #define ADC_JOFR2_JOFFSET2_Msk              (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
3495 #define ADC_JOFR2_JOFFSET2                  ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */
3496 
3497 /******************  Bit definition for ADC_JOFR3 register  *******************/
3498 #define ADC_JOFR3_JOFFSET3_Pos              (0U)
3499 #define ADC_JOFR3_JOFFSET3_Msk              (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
3500 #define ADC_JOFR3_JOFFSET3                  ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */
3501 
3502 /******************  Bit definition for ADC_JOFR4 register  *******************/
3503 #define ADC_JOFR4_JOFFSET4_Pos              (0U)
3504 #define ADC_JOFR4_JOFFSET4_Msk              (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
3505 #define ADC_JOFR4_JOFFSET4                  ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */
3506 
3507 /*******************  Bit definition for ADC_HTR register  ********************/
3508 #define ADC_HTR_HT_Pos                      (0U)
3509 #define ADC_HTR_HT_Msk                      (0xFFFUL << ADC_HTR_HT_Pos)         /*!< 0x00000FFF */
3510 #define ADC_HTR_HT                          ADC_HTR_HT_Msk                     /*!< ADC analog watchdog 1 threshold high */
3511 
3512 /*******************  Bit definition for ADC_LTR register  ********************/
3513 #define ADC_LTR_LT_Pos                      (0U)
3514 #define ADC_LTR_LT_Msk                      (0xFFFUL << ADC_LTR_LT_Pos)         /*!< 0x00000FFF */
3515 #define ADC_LTR_LT                          ADC_LTR_LT_Msk                     /*!< ADC analog watchdog 1 threshold low */
3516 
3517 /*******************  Bit definition for ADC_SQR1 register  *******************/
3518 #define ADC_SQR1_SQ13_Pos                   (0U)
3519 #define ADC_SQR1_SQ13_Msk                   (0x1FUL << ADC_SQR1_SQ13_Pos)       /*!< 0x0000001F */
3520 #define ADC_SQR1_SQ13                       ADC_SQR1_SQ13_Msk                  /*!< ADC group regular sequencer rank 13 */
3521 #define ADC_SQR1_SQ13_0                     (0x01UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000001 */
3522 #define ADC_SQR1_SQ13_1                     (0x02UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000002 */
3523 #define ADC_SQR1_SQ13_2                     (0x04UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000004 */
3524 #define ADC_SQR1_SQ13_3                     (0x08UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000008 */
3525 #define ADC_SQR1_SQ13_4                     (0x10UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000010 */
3526 
3527 #define ADC_SQR1_SQ14_Pos                   (5U)
3528 #define ADC_SQR1_SQ14_Msk                   (0x1FUL << ADC_SQR1_SQ14_Pos)       /*!< 0x000003E0 */
3529 #define ADC_SQR1_SQ14                       ADC_SQR1_SQ14_Msk                  /*!< ADC group regular sequencer rank 14 */
3530 #define ADC_SQR1_SQ14_0                     (0x01UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000020 */
3531 #define ADC_SQR1_SQ14_1                     (0x02UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000040 */
3532 #define ADC_SQR1_SQ14_2                     (0x04UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000080 */
3533 #define ADC_SQR1_SQ14_3                     (0x08UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000100 */
3534 #define ADC_SQR1_SQ14_4                     (0x10UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000200 */
3535 
3536 #define ADC_SQR1_SQ15_Pos                   (10U)
3537 #define ADC_SQR1_SQ15_Msk                   (0x1FUL << ADC_SQR1_SQ15_Pos)       /*!< 0x00007C00 */
3538 #define ADC_SQR1_SQ15                       ADC_SQR1_SQ15_Msk                  /*!< ADC group regular sequencer rank 15 */
3539 #define ADC_SQR1_SQ15_0                     (0x01UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000400 */
3540 #define ADC_SQR1_SQ15_1                     (0x02UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000800 */
3541 #define ADC_SQR1_SQ15_2                     (0x04UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00001000 */
3542 #define ADC_SQR1_SQ15_3                     (0x08UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00002000 */
3543 #define ADC_SQR1_SQ15_4                     (0x10UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00004000 */
3544 
3545 #define ADC_SQR1_SQ16_Pos                   (15U)
3546 #define ADC_SQR1_SQ16_Msk                   (0x1FUL << ADC_SQR1_SQ16_Pos)       /*!< 0x000F8000 */
3547 #define ADC_SQR1_SQ16                       ADC_SQR1_SQ16_Msk                  /*!< ADC group regular sequencer rank 16 */
3548 #define ADC_SQR1_SQ16_0                     (0x01UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00008000 */
3549 #define ADC_SQR1_SQ16_1                     (0x02UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00010000 */
3550 #define ADC_SQR1_SQ16_2                     (0x04UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00020000 */
3551 #define ADC_SQR1_SQ16_3                     (0x08UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00040000 */
3552 #define ADC_SQR1_SQ16_4                     (0x10UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00080000 */
3553 
3554 #define ADC_SQR1_L_Pos                      (20U)
3555 #define ADC_SQR1_L_Msk                      (0xFUL << ADC_SQR1_L_Pos)           /*!< 0x00F00000 */
3556 #define ADC_SQR1_L                          ADC_SQR1_L_Msk                     /*!< ADC group regular sequencer scan length */
3557 #define ADC_SQR1_L_0                        (0x1UL << ADC_SQR1_L_Pos)           /*!< 0x00100000 */
3558 #define ADC_SQR1_L_1                        (0x2UL << ADC_SQR1_L_Pos)           /*!< 0x00200000 */
3559 #define ADC_SQR1_L_2                        (0x4UL << ADC_SQR1_L_Pos)           /*!< 0x00400000 */
3560 #define ADC_SQR1_L_3                        (0x8UL << ADC_SQR1_L_Pos)           /*!< 0x00800000 */
3561 
3562 /*******************  Bit definition for ADC_SQR2 register  *******************/
3563 #define ADC_SQR2_SQ7_Pos                    (0U)
3564 #define ADC_SQR2_SQ7_Msk                    (0x1FUL << ADC_SQR2_SQ7_Pos)        /*!< 0x0000001F */
3565 #define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                   /*!< ADC group regular sequencer rank 7 */
3566 #define ADC_SQR2_SQ7_0                      (0x01UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000001 */
3567 #define ADC_SQR2_SQ7_1                      (0x02UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000002 */
3568 #define ADC_SQR2_SQ7_2                      (0x04UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000004 */
3569 #define ADC_SQR2_SQ7_3                      (0x08UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000008 */
3570 #define ADC_SQR2_SQ7_4                      (0x10UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000010 */
3571 
3572 #define ADC_SQR2_SQ8_Pos                    (5U)
3573 #define ADC_SQR2_SQ8_Msk                    (0x1FUL << ADC_SQR2_SQ8_Pos)        /*!< 0x000003E0 */
3574 #define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                   /*!< ADC group regular sequencer rank 8 */
3575 #define ADC_SQR2_SQ8_0                      (0x01UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000020 */
3576 #define ADC_SQR2_SQ8_1                      (0x02UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000040 */
3577 #define ADC_SQR2_SQ8_2                      (0x04UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000080 */
3578 #define ADC_SQR2_SQ8_3                      (0x08UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000100 */
3579 #define ADC_SQR2_SQ8_4                      (0x10UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000200 */
3580 
3581 #define ADC_SQR2_SQ9_Pos                    (10U)
3582 #define ADC_SQR2_SQ9_Msk                    (0x1FUL << ADC_SQR2_SQ9_Pos)        /*!< 0x00007C00 */
3583 #define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                   /*!< ADC group regular sequencer rank 9 */
3584 #define ADC_SQR2_SQ9_0                      (0x01UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000400 */
3585 #define ADC_SQR2_SQ9_1                      (0x02UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000800 */
3586 #define ADC_SQR2_SQ9_2                      (0x04UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00001000 */
3587 #define ADC_SQR2_SQ9_3                      (0x08UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00002000 */
3588 #define ADC_SQR2_SQ9_4                      (0x10UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00004000 */
3589 
3590 #define ADC_SQR2_SQ10_Pos                   (15U)
3591 #define ADC_SQR2_SQ10_Msk                   (0x1FUL << ADC_SQR2_SQ10_Pos)       /*!< 0x000F8000 */
3592 #define ADC_SQR2_SQ10                       ADC_SQR2_SQ10_Msk                  /*!< ADC group regular sequencer rank 10 */
3593 #define ADC_SQR2_SQ10_0                     (0x01UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00008000 */
3594 #define ADC_SQR2_SQ10_1                     (0x02UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00010000 */
3595 #define ADC_SQR2_SQ10_2                     (0x04UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00020000 */
3596 #define ADC_SQR2_SQ10_3                     (0x08UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00040000 */
3597 #define ADC_SQR2_SQ10_4                     (0x10UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00080000 */
3598 
3599 #define ADC_SQR2_SQ11_Pos                   (20U)
3600 #define ADC_SQR2_SQ11_Msk                   (0x1FUL << ADC_SQR2_SQ11_Pos)       /*!< 0x01F00000 */
3601 #define ADC_SQR2_SQ11                       ADC_SQR2_SQ11_Msk                  /*!< ADC group regular sequencer rank 1 */
3602 #define ADC_SQR2_SQ11_0                     (0x01UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00100000 */
3603 #define ADC_SQR2_SQ11_1                     (0x02UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00200000 */
3604 #define ADC_SQR2_SQ11_2                     (0x04UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00400000 */
3605 #define ADC_SQR2_SQ11_3                     (0x08UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00800000 */
3606 #define ADC_SQR2_SQ11_4                     (0x10UL << ADC_SQR2_SQ11_Pos)       /*!< 0x01000000 */
3607 
3608 #define ADC_SQR2_SQ12_Pos                   (25U)
3609 #define ADC_SQR2_SQ12_Msk                   (0x1FUL << ADC_SQR2_SQ12_Pos)       /*!< 0x3E000000 */
3610 #define ADC_SQR2_SQ12                       ADC_SQR2_SQ12_Msk                  /*!< ADC group regular sequencer rank 12 */
3611 #define ADC_SQR2_SQ12_0                     (0x01UL << ADC_SQR2_SQ12_Pos)       /*!< 0x02000000 */
3612 #define ADC_SQR2_SQ12_1                     (0x02UL << ADC_SQR2_SQ12_Pos)       /*!< 0x04000000 */
3613 #define ADC_SQR2_SQ12_2                     (0x04UL << ADC_SQR2_SQ12_Pos)       /*!< 0x08000000 */
3614 #define ADC_SQR2_SQ12_3                     (0x08UL << ADC_SQR2_SQ12_Pos)       /*!< 0x10000000 */
3615 #define ADC_SQR2_SQ12_4                     (0x10UL << ADC_SQR2_SQ12_Pos)       /*!< 0x20000000 */
3616 
3617 /*******************  Bit definition for ADC_SQR3 register  *******************/
3618 #define ADC_SQR3_SQ1_Pos                    (0U)
3619 #define ADC_SQR3_SQ1_Msk                    (0x1FUL << ADC_SQR3_SQ1_Pos)        /*!< 0x0000001F */
3620 #define ADC_SQR3_SQ1                        ADC_SQR3_SQ1_Msk                   /*!< ADC group regular sequencer rank 1 */
3621 #define ADC_SQR3_SQ1_0                      (0x01UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000001 */
3622 #define ADC_SQR3_SQ1_1                      (0x02UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000002 */
3623 #define ADC_SQR3_SQ1_2                      (0x04UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000004 */
3624 #define ADC_SQR3_SQ1_3                      (0x08UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000008 */
3625 #define ADC_SQR3_SQ1_4                      (0x10UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000010 */
3626 
3627 #define ADC_SQR3_SQ2_Pos                    (5U)
3628 #define ADC_SQR3_SQ2_Msk                    (0x1FUL << ADC_SQR3_SQ2_Pos)        /*!< 0x000003E0 */
3629 #define ADC_SQR3_SQ2                        ADC_SQR3_SQ2_Msk                   /*!< ADC group regular sequencer rank 2 */
3630 #define ADC_SQR3_SQ2_0                      (0x01UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000020 */
3631 #define ADC_SQR3_SQ2_1                      (0x02UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000040 */
3632 #define ADC_SQR3_SQ2_2                      (0x04UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000080 */
3633 #define ADC_SQR3_SQ2_3                      (0x08UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000100 */
3634 #define ADC_SQR3_SQ2_4                      (0x10UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000200 */
3635 
3636 #define ADC_SQR3_SQ3_Pos                    (10U)
3637 #define ADC_SQR3_SQ3_Msk                    (0x1FUL << ADC_SQR3_SQ3_Pos)        /*!< 0x00007C00 */
3638 #define ADC_SQR3_SQ3                        ADC_SQR3_SQ3_Msk                   /*!< ADC group regular sequencer rank 3 */
3639 #define ADC_SQR3_SQ3_0                      (0x01UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000400 */
3640 #define ADC_SQR3_SQ3_1                      (0x02UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000800 */
3641 #define ADC_SQR3_SQ3_2                      (0x04UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00001000 */
3642 #define ADC_SQR3_SQ3_3                      (0x08UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00002000 */
3643 #define ADC_SQR3_SQ3_4                      (0x10UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00004000 */
3644 
3645 #define ADC_SQR3_SQ4_Pos                    (15U)
3646 #define ADC_SQR3_SQ4_Msk                    (0x1FUL << ADC_SQR3_SQ4_Pos)        /*!< 0x000F8000 */
3647 #define ADC_SQR3_SQ4                        ADC_SQR3_SQ4_Msk                   /*!< ADC group regular sequencer rank 4 */
3648 #define ADC_SQR3_SQ4_0                      (0x01UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00008000 */
3649 #define ADC_SQR3_SQ4_1                      (0x02UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00010000 */
3650 #define ADC_SQR3_SQ4_2                      (0x04UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00020000 */
3651 #define ADC_SQR3_SQ4_3                      (0x08UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00040000 */
3652 #define ADC_SQR3_SQ4_4                      (0x10UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00080000 */
3653 
3654 #define ADC_SQR3_SQ5_Pos                    (20U)
3655 #define ADC_SQR3_SQ5_Msk                    (0x1FUL << ADC_SQR3_SQ5_Pos)        /*!< 0x01F00000 */
3656 #define ADC_SQR3_SQ5                        ADC_SQR3_SQ5_Msk                   /*!< ADC group regular sequencer rank 5 */
3657 #define ADC_SQR3_SQ5_0                      (0x01UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00100000 */
3658 #define ADC_SQR3_SQ5_1                      (0x02UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00200000 */
3659 #define ADC_SQR3_SQ5_2                      (0x04UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00400000 */
3660 #define ADC_SQR3_SQ5_3                      (0x08UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00800000 */
3661 #define ADC_SQR3_SQ5_4                      (0x10UL << ADC_SQR3_SQ5_Pos)        /*!< 0x01000000 */
3662 
3663 #define ADC_SQR3_SQ6_Pos                    (25U)
3664 #define ADC_SQR3_SQ6_Msk                    (0x1FUL << ADC_SQR3_SQ6_Pos)        /*!< 0x3E000000 */
3665 #define ADC_SQR3_SQ6                        ADC_SQR3_SQ6_Msk                   /*!< ADC group regular sequencer rank 6 */
3666 #define ADC_SQR3_SQ6_0                      (0x01UL << ADC_SQR3_SQ6_Pos)        /*!< 0x02000000 */
3667 #define ADC_SQR3_SQ6_1                      (0x02UL << ADC_SQR3_SQ6_Pos)        /*!< 0x04000000 */
3668 #define ADC_SQR3_SQ6_2                      (0x04UL << ADC_SQR3_SQ6_Pos)        /*!< 0x08000000 */
3669 #define ADC_SQR3_SQ6_3                      (0x08UL << ADC_SQR3_SQ6_Pos)        /*!< 0x10000000 */
3670 #define ADC_SQR3_SQ6_4                      (0x10UL << ADC_SQR3_SQ6_Pos)        /*!< 0x20000000 */
3671 
3672 /*******************  Bit definition for ADC_JSQR register  *******************/
3673 #define ADC_JSQR_JSQ1_Pos                   (0U)
3674 #define ADC_JSQR_JSQ1_Msk                   (0x1FUL << ADC_JSQR_JSQ1_Pos)       /*!< 0x0000001F */
3675 #define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                  /*!< ADC group injected sequencer rank 1 */
3676 #define ADC_JSQR_JSQ1_0                     (0x01UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000001 */
3677 #define ADC_JSQR_JSQ1_1                     (0x02UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000002 */
3678 #define ADC_JSQR_JSQ1_2                     (0x04UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000004 */
3679 #define ADC_JSQR_JSQ1_3                     (0x08UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000008 */
3680 #define ADC_JSQR_JSQ1_4                     (0x10UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000010 */
3681 
3682 #define ADC_JSQR_JSQ2_Pos                   (5U)
3683 #define ADC_JSQR_JSQ2_Msk                   (0x1FUL << ADC_JSQR_JSQ2_Pos)       /*!< 0x000003E0 */
3684 #define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                  /*!< ADC group injected sequencer rank 2 */
3685 #define ADC_JSQR_JSQ2_0                     (0x01UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000020 */
3686 #define ADC_JSQR_JSQ2_1                     (0x02UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000040 */
3687 #define ADC_JSQR_JSQ2_2                     (0x04UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000080 */
3688 #define ADC_JSQR_JSQ2_3                     (0x08UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000100 */
3689 #define ADC_JSQR_JSQ2_4                     (0x10UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000200 */
3690 
3691 #define ADC_JSQR_JSQ3_Pos                   (10U)
3692 #define ADC_JSQR_JSQ3_Msk                   (0x1FUL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00007C00 */
3693 #define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                  /*!< ADC group injected sequencer rank 3 */
3694 #define ADC_JSQR_JSQ3_0                     (0x01UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000400 */
3695 #define ADC_JSQR_JSQ3_1                     (0x02UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000800 */
3696 #define ADC_JSQR_JSQ3_2                     (0x04UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00001000 */
3697 #define ADC_JSQR_JSQ3_3                     (0x08UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00002000 */
3698 #define ADC_JSQR_JSQ3_4                     (0x10UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00004000 */
3699 
3700 #define ADC_JSQR_JSQ4_Pos                   (15U)
3701 #define ADC_JSQR_JSQ4_Msk                   (0x1FUL << ADC_JSQR_JSQ4_Pos)       /*!< 0x000F8000 */
3702 #define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                  /*!< ADC group injected sequencer rank 4 */
3703 #define ADC_JSQR_JSQ4_0                     (0x01UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00008000 */
3704 #define ADC_JSQR_JSQ4_1                     (0x02UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00010000 */
3705 #define ADC_JSQR_JSQ4_2                     (0x04UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00020000 */
3706 #define ADC_JSQR_JSQ4_3                     (0x08UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00040000 */
3707 #define ADC_JSQR_JSQ4_4                     (0x10UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00080000 */
3708 
3709 #define ADC_JSQR_JL_Pos                     (20U)
3710 #define ADC_JSQR_JL_Msk                     (0x3UL << ADC_JSQR_JL_Pos)          /*!< 0x00300000 */
3711 #define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                    /*!< ADC group injected sequencer scan length */
3712 #define ADC_JSQR_JL_0                       (0x1UL << ADC_JSQR_JL_Pos)          /*!< 0x00100000 */
3713 #define ADC_JSQR_JL_1                       (0x2UL << ADC_JSQR_JL_Pos)          /*!< 0x00200000 */
3714 
3715 /*******************  Bit definition for ADC_JDR1 register  *******************/
3716 #define ADC_JDR1_JDATA_Pos                  (0U)
3717 #define ADC_JDR1_JDATA_Msk                  (0xFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0x0000FFFF */
3718 #define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                 /*!< ADC group injected sequencer rank 1 conversion data */
3719 
3720 /*******************  Bit definition for ADC_JDR2 register  *******************/
3721 #define ADC_JDR2_JDATA_Pos                  (0U)
3722 #define ADC_JDR2_JDATA_Msk                  (0xFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0x0000FFFF */
3723 #define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                 /*!< ADC group injected sequencer rank 2 conversion data */
3724 
3725 /*******************  Bit definition for ADC_JDR3 register  *******************/
3726 #define ADC_JDR3_JDATA_Pos                  (0U)
3727 #define ADC_JDR3_JDATA_Msk                  (0xFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0x0000FFFF */
3728 #define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                 /*!< ADC group injected sequencer rank 3 conversion data */
3729 
3730 /*******************  Bit definition for ADC_JDR4 register  *******************/
3731 #define ADC_JDR4_JDATA_Pos                  (0U)
3732 #define ADC_JDR4_JDATA_Msk                  (0xFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0x0000FFFF */
3733 #define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                 /*!< ADC group injected sequencer rank 4 conversion data */
3734 
3735 /********************  Bit definition for ADC_DR register  ********************/
3736 #define ADC_DR_DATA_Pos                     (0U)
3737 #define ADC_DR_DATA_Msk                     (0xFFFFUL << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */
3738 #define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */
3739 #define ADC_DR_ADC2DATA_Pos                 (16U)
3740 #define ADC_DR_ADC2DATA_Msk                 (0xFFFFUL << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */
3741 #define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */
3742 
3743 
3744 /*****************************************************************************/
3745 /*                                                                           */
3746 /*                               Timers (TIM)                                */
3747 /*                                                                           */
3748 /*****************************************************************************/
3749 /*******************  Bit definition for TIM_CR1 register  *******************/
3750 #define TIM_CR1_CEN_Pos                     (0U)
3751 #define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
3752 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
3753 #define TIM_CR1_UDIS_Pos                    (1U)
3754 #define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
3755 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
3756 #define TIM_CR1_URS_Pos                     (2U)
3757 #define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
3758 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
3759 #define TIM_CR1_OPM_Pos                     (3U)
3760 #define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
3761 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
3762 #define TIM_CR1_DIR_Pos                     (4U)
3763 #define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
3764 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
3765 
3766 #define TIM_CR1_CMS_Pos                     (5U)
3767 #define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
3768 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
3769 #define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
3770 #define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
3771 
3772 #define TIM_CR1_ARPE_Pos                    (7U)
3773 #define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
3774 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
3775 
3776 #define TIM_CR1_CKD_Pos                     (8U)
3777 #define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
3778 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
3779 #define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
3780 #define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
3781 
3782 /*******************  Bit definition for TIM_CR2 register  *******************/
3783 #define TIM_CR2_CCPC_Pos                    (0U)
3784 #define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)         /*!< 0x00000001 */
3785 #define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                   /*!<Capture/Compare Preloaded Control */
3786 #define TIM_CR2_CCUS_Pos                    (2U)
3787 #define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)         /*!< 0x00000004 */
3788 #define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                   /*!<Capture/Compare Control Update Selection */
3789 #define TIM_CR2_CCDS_Pos                    (3U)
3790 #define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
3791 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
3792 
3793 #define TIM_CR2_MMS_Pos                     (4U)
3794 #define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
3795 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
3796 #define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
3797 #define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
3798 #define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
3799 
3800 #define TIM_CR2_TI1S_Pos                    (7U)
3801 #define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
3802 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
3803 #define TIM_CR2_OIS1_Pos                    (8U)
3804 #define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)         /*!< 0x00000100 */
3805 #define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                   /*!<Output Idle state 1 (OC1 output) */
3806 #define TIM_CR2_OIS1N_Pos                   (9U)
3807 #define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)        /*!< 0x00000200 */
3808 #define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                  /*!<Output Idle state 1 (OC1N output) */
3809 #define TIM_CR2_OIS2_Pos                    (10U)
3810 #define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)         /*!< 0x00000400 */
3811 #define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                   /*!<Output Idle state 2 (OC2 output) */
3812 #define TIM_CR2_OIS2N_Pos                   (11U)
3813 #define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)        /*!< 0x00000800 */
3814 #define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                  /*!<Output Idle state 2 (OC2N output) */
3815 #define TIM_CR2_OIS3_Pos                    (12U)
3816 #define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)         /*!< 0x00001000 */
3817 #define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                   /*!<Output Idle state 3 (OC3 output) */
3818 #define TIM_CR2_OIS3N_Pos                   (13U)
3819 #define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)        /*!< 0x00002000 */
3820 #define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                  /*!<Output Idle state 3 (OC3N output) */
3821 #define TIM_CR2_OIS4_Pos                    (14U)
3822 #define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)         /*!< 0x00004000 */
3823 #define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                   /*!<Output Idle state 4 (OC4 output) */
3824 
3825 /*******************  Bit definition for TIM_SMCR register  ******************/
3826 #define TIM_SMCR_SMS_Pos                    (0U)
3827 #define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
3828 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
3829 #define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
3830 #define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
3831 #define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
3832 
3833 #define TIM_SMCR_TS_Pos                     (4U)
3834 #define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
3835 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
3836 #define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
3837 #define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
3838 #define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
3839 
3840 #define TIM_SMCR_MSM_Pos                    (7U)
3841 #define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
3842 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
3843 
3844 #define TIM_SMCR_ETF_Pos                    (8U)
3845 #define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
3846 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
3847 #define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
3848 #define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
3849 #define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
3850 #define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
3851 
3852 #define TIM_SMCR_ETPS_Pos                   (12U)
3853 #define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
3854 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
3855 #define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
3856 #define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
3857 
3858 #define TIM_SMCR_ECE_Pos                    (14U)
3859 #define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
3860 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
3861 #define TIM_SMCR_ETP_Pos                    (15U)
3862 #define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
3863 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
3864 
3865 /*******************  Bit definition for TIM_DIER register  ******************/
3866 #define TIM_DIER_UIE_Pos                    (0U)
3867 #define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
3868 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
3869 #define TIM_DIER_CC1IE_Pos                  (1U)
3870 #define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
3871 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
3872 #define TIM_DIER_CC2IE_Pos                  (2U)
3873 #define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
3874 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
3875 #define TIM_DIER_CC3IE_Pos                  (3U)
3876 #define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
3877 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
3878 #define TIM_DIER_CC4IE_Pos                  (4U)
3879 #define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
3880 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
3881 #define TIM_DIER_COMIE_Pos                  (5U)
3882 #define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)       /*!< 0x00000020 */
3883 #define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                 /*!<COM interrupt enable */
3884 #define TIM_DIER_TIE_Pos                    (6U)
3885 #define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
3886 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
3887 #define TIM_DIER_BIE_Pos                    (7U)
3888 #define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)         /*!< 0x00000080 */
3889 #define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                   /*!<Break interrupt enable */
3890 #define TIM_DIER_UDE_Pos                    (8U)
3891 #define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
3892 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
3893 #define TIM_DIER_CC1DE_Pos                  (9U)
3894 #define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
3895 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
3896 #define TIM_DIER_CC2DE_Pos                  (10U)
3897 #define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
3898 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
3899 #define TIM_DIER_CC3DE_Pos                  (11U)
3900 #define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
3901 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
3902 #define TIM_DIER_CC4DE_Pos                  (12U)
3903 #define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
3904 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
3905 #define TIM_DIER_COMDE_Pos                  (13U)
3906 #define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)       /*!< 0x00002000 */
3907 #define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                 /*!<COM DMA request enable */
3908 #define TIM_DIER_TDE_Pos                    (14U)
3909 #define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
3910 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
3911 
3912 /********************  Bit definition for TIM_SR register  *******************/
3913 #define TIM_SR_UIF_Pos                      (0U)
3914 #define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
3915 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
3916 #define TIM_SR_CC1IF_Pos                    (1U)
3917 #define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
3918 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
3919 #define TIM_SR_CC2IF_Pos                    (2U)
3920 #define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
3921 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
3922 #define TIM_SR_CC3IF_Pos                    (3U)
3923 #define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
3924 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
3925 #define TIM_SR_CC4IF_Pos                    (4U)
3926 #define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
3927 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
3928 #define TIM_SR_COMIF_Pos                    (5U)
3929 #define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)         /*!< 0x00000020 */
3930 #define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                   /*!<COM interrupt Flag */
3931 #define TIM_SR_TIF_Pos                      (6U)
3932 #define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
3933 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
3934 #define TIM_SR_BIF_Pos                      (7U)
3935 #define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)           /*!< 0x00000080 */
3936 #define TIM_SR_BIF                          TIM_SR_BIF_Msk                     /*!<Break interrupt Flag */
3937 #define TIM_SR_CC1OF_Pos                    (9U)
3938 #define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
3939 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
3940 #define TIM_SR_CC2OF_Pos                    (10U)
3941 #define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
3942 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
3943 #define TIM_SR_CC3OF_Pos                    (11U)
3944 #define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
3945 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
3946 #define TIM_SR_CC4OF_Pos                    (12U)
3947 #define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
3948 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
3949 
3950 /*******************  Bit definition for TIM_EGR register  *******************/
3951 #define TIM_EGR_UG_Pos                      (0U)
3952 #define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
3953 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
3954 #define TIM_EGR_CC1G_Pos                    (1U)
3955 #define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
3956 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
3957 #define TIM_EGR_CC2G_Pos                    (2U)
3958 #define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
3959 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
3960 #define TIM_EGR_CC3G_Pos                    (3U)
3961 #define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
3962 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
3963 #define TIM_EGR_CC4G_Pos                    (4U)
3964 #define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
3965 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
3966 #define TIM_EGR_COMG_Pos                    (5U)
3967 #define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)         /*!< 0x00000020 */
3968 #define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                   /*!<Capture/Compare Control Update Generation */
3969 #define TIM_EGR_TG_Pos                      (6U)
3970 #define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
3971 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
3972 #define TIM_EGR_BG_Pos                      (7U)
3973 #define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)           /*!< 0x00000080 */
3974 #define TIM_EGR_BG                          TIM_EGR_BG_Msk                     /*!<Break Generation */
3975 
3976 /******************  Bit definition for TIM_CCMR1 register  ******************/
3977 #define TIM_CCMR1_CC1S_Pos                  (0U)
3978 #define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
3979 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
3980 #define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
3981 #define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
3982 
3983 #define TIM_CCMR1_OC1FE_Pos                 (2U)
3984 #define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
3985 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
3986 #define TIM_CCMR1_OC1PE_Pos                 (3U)
3987 #define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
3988 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
3989 
3990 #define TIM_CCMR1_OC1M_Pos                  (4U)
3991 #define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
3992 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
3993 #define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
3994 #define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
3995 #define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
3996 
3997 #define TIM_CCMR1_OC1CE_Pos                 (7U)
3998 #define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
3999 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
4000 
4001 #define TIM_CCMR1_CC2S_Pos                  (8U)
4002 #define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
4003 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4004 #define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
4005 #define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
4006 
4007 #define TIM_CCMR1_OC2FE_Pos                 (10U)
4008 #define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
4009 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
4010 #define TIM_CCMR1_OC2PE_Pos                 (11U)
4011 #define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
4012 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
4013 
4014 #define TIM_CCMR1_OC2M_Pos                  (12U)
4015 #define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
4016 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4017 #define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
4018 #define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
4019 #define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
4020 
4021 #define TIM_CCMR1_OC2CE_Pos                 (15U)
4022 #define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
4023 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
4024 
4025 /*---------------------------------------------------------------------------*/
4026 
4027 #define TIM_CCMR1_IC1PSC_Pos                (2U)
4028 #define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
4029 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4030 #define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
4031 #define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
4032 
4033 #define TIM_CCMR1_IC1F_Pos                  (4U)
4034 #define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
4035 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4036 #define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
4037 #define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
4038 #define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
4039 #define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
4040 
4041 #define TIM_CCMR1_IC2PSC_Pos                (10U)
4042 #define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
4043 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4044 #define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
4045 #define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
4046 
4047 #define TIM_CCMR1_IC2F_Pos                  (12U)
4048 #define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
4049 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4050 #define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
4051 #define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
4052 #define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
4053 #define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
4054 
4055 /******************  Bit definition for TIM_CCMR2 register  ******************/
4056 #define TIM_CCMR2_CC3S_Pos                  (0U)
4057 #define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
4058 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4059 #define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
4060 #define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
4061 
4062 #define TIM_CCMR2_OC3FE_Pos                 (2U)
4063 #define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
4064 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
4065 #define TIM_CCMR2_OC3PE_Pos                 (3U)
4066 #define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
4067 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
4068 
4069 #define TIM_CCMR2_OC3M_Pos                  (4U)
4070 #define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
4071 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4072 #define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
4073 #define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
4074 #define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
4075 
4076 #define TIM_CCMR2_OC3CE_Pos                 (7U)
4077 #define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
4078 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
4079 
4080 #define TIM_CCMR2_CC4S_Pos                  (8U)
4081 #define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
4082 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4083 #define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
4084 #define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
4085 
4086 #define TIM_CCMR2_OC4FE_Pos                 (10U)
4087 #define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
4088 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
4089 #define TIM_CCMR2_OC4PE_Pos                 (11U)
4090 #define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
4091 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
4092 
4093 #define TIM_CCMR2_OC4M_Pos                  (12U)
4094 #define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
4095 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4096 #define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
4097 #define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
4098 #define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
4099 
4100 #define TIM_CCMR2_OC4CE_Pos                 (15U)
4101 #define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
4102 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
4103 
4104 /*---------------------------------------------------------------------------*/
4105 
4106 #define TIM_CCMR2_IC3PSC_Pos                (2U)
4107 #define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
4108 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4109 #define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
4110 #define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
4111 
4112 #define TIM_CCMR2_IC3F_Pos                  (4U)
4113 #define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
4114 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4115 #define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
4116 #define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
4117 #define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
4118 #define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
4119 
4120 #define TIM_CCMR2_IC4PSC_Pos                (10U)
4121 #define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
4122 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4123 #define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
4124 #define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
4125 
4126 #define TIM_CCMR2_IC4F_Pos                  (12U)
4127 #define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
4128 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4129 #define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
4130 #define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
4131 #define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
4132 #define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
4133 
4134 /*******************  Bit definition for TIM_CCER register  ******************/
4135 #define TIM_CCER_CC1E_Pos                   (0U)
4136 #define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
4137 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
4138 #define TIM_CCER_CC1P_Pos                   (1U)
4139 #define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
4140 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
4141 #define TIM_CCER_CC1NE_Pos                  (2U)
4142 #define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)       /*!< 0x00000004 */
4143 #define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                 /*!<Capture/Compare 1 Complementary output enable */
4144 #define TIM_CCER_CC1NP_Pos                  (3U)
4145 #define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
4146 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
4147 #define TIM_CCER_CC2E_Pos                   (4U)
4148 #define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
4149 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
4150 #define TIM_CCER_CC2P_Pos                   (5U)
4151 #define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
4152 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
4153 #define TIM_CCER_CC2NE_Pos                  (6U)
4154 #define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)       /*!< 0x00000040 */
4155 #define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                 /*!<Capture/Compare 2 Complementary output enable */
4156 #define TIM_CCER_CC2NP_Pos                  (7U)
4157 #define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
4158 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
4159 #define TIM_CCER_CC3E_Pos                   (8U)
4160 #define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
4161 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
4162 #define TIM_CCER_CC3P_Pos                   (9U)
4163 #define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
4164 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
4165 #define TIM_CCER_CC3NE_Pos                  (10U)
4166 #define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)       /*!< 0x00000400 */
4167 #define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                 /*!<Capture/Compare 3 Complementary output enable */
4168 #define TIM_CCER_CC3NP_Pos                  (11U)
4169 #define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
4170 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
4171 #define TIM_CCER_CC4E_Pos                   (12U)
4172 #define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
4173 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
4174 #define TIM_CCER_CC4P_Pos                   (13U)
4175 #define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
4176 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
4177 
4178 /*******************  Bit definition for TIM_CNT register  *******************/
4179 #define TIM_CNT_CNT_Pos                     (0U)
4180 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
4181 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
4182 
4183 /*******************  Bit definition for TIM_PSC register  *******************/
4184 #define TIM_PSC_PSC_Pos                     (0U)
4185 #define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
4186 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
4187 
4188 /*******************  Bit definition for TIM_ARR register  *******************/
4189 #define TIM_ARR_ARR_Pos                     (0U)
4190 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
4191 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
4192 
4193 /*******************  Bit definition for TIM_RCR register  *******************/
4194 #define TIM_RCR_REP_Pos                     (0U)
4195 #define TIM_RCR_REP_Msk                     (0xFFUL << TIM_RCR_REP_Pos)         /*!< 0x000000FF */
4196 #define TIM_RCR_REP                         TIM_RCR_REP_Msk                    /*!<Repetition Counter Value */
4197 
4198 /*******************  Bit definition for TIM_CCR1 register  ******************/
4199 #define TIM_CCR1_CCR1_Pos                   (0U)
4200 #define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
4201 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
4202 
4203 /*******************  Bit definition for TIM_CCR2 register  ******************/
4204 #define TIM_CCR2_CCR2_Pos                   (0U)
4205 #define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
4206 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
4207 
4208 /*******************  Bit definition for TIM_CCR3 register  ******************/
4209 #define TIM_CCR3_CCR3_Pos                   (0U)
4210 #define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
4211 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
4212 
4213 /*******************  Bit definition for TIM_CCR4 register  ******************/
4214 #define TIM_CCR4_CCR4_Pos                   (0U)
4215 #define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
4216 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
4217 
4218 /*******************  Bit definition for TIM_BDTR register  ******************/
4219 #define TIM_BDTR_DTG_Pos                    (0U)
4220 #define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)        /*!< 0x000000FF */
4221 #define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                   /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4222 #define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000001 */
4223 #define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000002 */
4224 #define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000004 */
4225 #define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000008 */
4226 #define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000010 */
4227 #define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000020 */
4228 #define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000040 */
4229 #define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000080 */
4230 
4231 #define TIM_BDTR_LOCK_Pos                   (8U)
4232 #define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000300 */
4233 #define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                  /*!<LOCK[1:0] bits (Lock Configuration) */
4234 #define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000100 */
4235 #define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000200 */
4236 
4237 #define TIM_BDTR_OSSI_Pos                   (10U)
4238 #define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)        /*!< 0x00000400 */
4239 #define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                  /*!<Off-State Selection for Idle mode */
4240 #define TIM_BDTR_OSSR_Pos                   (11U)
4241 #define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)        /*!< 0x00000800 */
4242 #define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                  /*!<Off-State Selection for Run mode */
4243 #define TIM_BDTR_BKE_Pos                    (12U)
4244 #define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)         /*!< 0x00001000 */
4245 #define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                   /*!<Break enable */
4246 #define TIM_BDTR_BKP_Pos                    (13U)
4247 #define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)         /*!< 0x00002000 */
4248 #define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                   /*!<Break Polarity */
4249 #define TIM_BDTR_AOE_Pos                    (14U)
4250 #define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)         /*!< 0x00004000 */
4251 #define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                   /*!<Automatic Output enable */
4252 #define TIM_BDTR_MOE_Pos                    (15U)
4253 #define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)         /*!< 0x00008000 */
4254 #define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                   /*!<Main Output enable */
4255 
4256 /*******************  Bit definition for TIM_DCR register  *******************/
4257 #define TIM_DCR_DBA_Pos                     (0U)
4258 #define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
4259 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
4260 #define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
4261 #define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
4262 #define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
4263 #define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
4264 #define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
4265 
4266 #define TIM_DCR_DBL_Pos                     (8U)
4267 #define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
4268 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
4269 #define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
4270 #define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
4271 #define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
4272 #define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
4273 #define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
4274 
4275 /*******************  Bit definition for TIM_DMAR register  ******************/
4276 #define TIM_DMAR_DMAB_Pos                   (0U)
4277 #define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
4278 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
4279 
4280 /******************************************************************************/
4281 /*                                                                            */
4282 /*                             Real-Time Clock                                */
4283 /*                                                                            */
4284 /******************************************************************************/
4285 
4286 /*******************  Bit definition for RTC_CRH register  ********************/
4287 #define RTC_CRH_SECIE_Pos                   (0U)
4288 #define RTC_CRH_SECIE_Msk                   (0x1UL << RTC_CRH_SECIE_Pos)        /*!< 0x00000001 */
4289 #define RTC_CRH_SECIE                       RTC_CRH_SECIE_Msk                  /*!< Second Interrupt Enable */
4290 #define RTC_CRH_ALRIE_Pos                   (1U)
4291 #define RTC_CRH_ALRIE_Msk                   (0x1UL << RTC_CRH_ALRIE_Pos)        /*!< 0x00000002 */
4292 #define RTC_CRH_ALRIE                       RTC_CRH_ALRIE_Msk                  /*!< Alarm Interrupt Enable */
4293 #define RTC_CRH_OWIE_Pos                    (2U)
4294 #define RTC_CRH_OWIE_Msk                    (0x1UL << RTC_CRH_OWIE_Pos)         /*!< 0x00000004 */
4295 #define RTC_CRH_OWIE                        RTC_CRH_OWIE_Msk                   /*!< OverfloW Interrupt Enable */
4296 
4297 /*******************  Bit definition for RTC_CRL register  ********************/
4298 #define RTC_CRL_SECF_Pos                    (0U)
4299 #define RTC_CRL_SECF_Msk                    (0x1UL << RTC_CRL_SECF_Pos)         /*!< 0x00000001 */
4300 #define RTC_CRL_SECF                        RTC_CRL_SECF_Msk                   /*!< Second Flag */
4301 #define RTC_CRL_ALRF_Pos                    (1U)
4302 #define RTC_CRL_ALRF_Msk                    (0x1UL << RTC_CRL_ALRF_Pos)         /*!< 0x00000002 */
4303 #define RTC_CRL_ALRF                        RTC_CRL_ALRF_Msk                   /*!< Alarm Flag */
4304 #define RTC_CRL_OWF_Pos                     (2U)
4305 #define RTC_CRL_OWF_Msk                     (0x1UL << RTC_CRL_OWF_Pos)          /*!< 0x00000004 */
4306 #define RTC_CRL_OWF                         RTC_CRL_OWF_Msk                    /*!< OverfloW Flag */
4307 #define RTC_CRL_RSF_Pos                     (3U)
4308 #define RTC_CRL_RSF_Msk                     (0x1UL << RTC_CRL_RSF_Pos)          /*!< 0x00000008 */
4309 #define RTC_CRL_RSF                         RTC_CRL_RSF_Msk                    /*!< Registers Synchronized Flag */
4310 #define RTC_CRL_CNF_Pos                     (4U)
4311 #define RTC_CRL_CNF_Msk                     (0x1UL << RTC_CRL_CNF_Pos)          /*!< 0x00000010 */
4312 #define RTC_CRL_CNF                         RTC_CRL_CNF_Msk                    /*!< Configuration Flag */
4313 #define RTC_CRL_RTOFF_Pos                   (5U)
4314 #define RTC_CRL_RTOFF_Msk                   (0x1UL << RTC_CRL_RTOFF_Pos)        /*!< 0x00000020 */
4315 #define RTC_CRL_RTOFF                       RTC_CRL_RTOFF_Msk                  /*!< RTC operation OFF */
4316 
4317 /*******************  Bit definition for RTC_PRLH register  *******************/
4318 #define RTC_PRLH_PRL_Pos                    (0U)
4319 #define RTC_PRLH_PRL_Msk                    (0xFUL << RTC_PRLH_PRL_Pos)         /*!< 0x0000000F */
4320 #define RTC_PRLH_PRL                        RTC_PRLH_PRL_Msk                   /*!< RTC Prescaler Reload Value High */
4321 
4322 /*******************  Bit definition for RTC_PRLL register  *******************/
4323 #define RTC_PRLL_PRL_Pos                    (0U)
4324 #define RTC_PRLL_PRL_Msk                    (0xFFFFUL << RTC_PRLL_PRL_Pos)      /*!< 0x0000FFFF */
4325 #define RTC_PRLL_PRL                        RTC_PRLL_PRL_Msk                   /*!< RTC Prescaler Reload Value Low */
4326 
4327 /*******************  Bit definition for RTC_DIVH register  *******************/
4328 #define RTC_DIVH_RTC_DIV_Pos                (0U)
4329 #define RTC_DIVH_RTC_DIV_Msk                (0xFUL << RTC_DIVH_RTC_DIV_Pos)     /*!< 0x0000000F */
4330 #define RTC_DIVH_RTC_DIV                    RTC_DIVH_RTC_DIV_Msk               /*!< RTC Clock Divider High */
4331 
4332 /*******************  Bit definition for RTC_DIVL register  *******************/
4333 #define RTC_DIVL_RTC_DIV_Pos                (0U)
4334 #define RTC_DIVL_RTC_DIV_Msk                (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)  /*!< 0x0000FFFF */
4335 #define RTC_DIVL_RTC_DIV                    RTC_DIVL_RTC_DIV_Msk               /*!< RTC Clock Divider Low */
4336 
4337 /*******************  Bit definition for RTC_CNTH register  *******************/
4338 #define RTC_CNTH_RTC_CNT_Pos                (0U)
4339 #define RTC_CNTH_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)  /*!< 0x0000FFFF */
4340 #define RTC_CNTH_RTC_CNT                    RTC_CNTH_RTC_CNT_Msk               /*!< RTC Counter High */
4341 
4342 /*******************  Bit definition for RTC_CNTL register  *******************/
4343 #define RTC_CNTL_RTC_CNT_Pos                (0U)
4344 #define RTC_CNTL_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)  /*!< 0x0000FFFF */
4345 #define RTC_CNTL_RTC_CNT                    RTC_CNTL_RTC_CNT_Msk               /*!< RTC Counter Low */
4346 
4347 /*******************  Bit definition for RTC_ALRH register  *******************/
4348 #define RTC_ALRH_RTC_ALR_Pos                (0U)
4349 #define RTC_ALRH_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)  /*!< 0x0000FFFF */
4350 #define RTC_ALRH_RTC_ALR                    RTC_ALRH_RTC_ALR_Msk               /*!< RTC Alarm High */
4351 
4352 /*******************  Bit definition for RTC_ALRL register  *******************/
4353 #define RTC_ALRL_RTC_ALR_Pos                (0U)
4354 #define RTC_ALRL_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)  /*!< 0x0000FFFF */
4355 #define RTC_ALRL_RTC_ALR                    RTC_ALRL_RTC_ALR_Msk               /*!< RTC Alarm Low */
4356 
4357 /******************************************************************************/
4358 /*                                                                            */
4359 /*                        Independent WATCHDOG (IWDG)                         */
4360 /*                                                                            */
4361 /******************************************************************************/
4362 
4363 /*******************  Bit definition for IWDG_KR register  ********************/
4364 #define IWDG_KR_KEY_Pos                     (0U)
4365 #define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
4366 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
4367 
4368 /*******************  Bit definition for IWDG_PR register  ********************/
4369 #define IWDG_PR_PR_Pos                      (0U)
4370 #define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
4371 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
4372 #define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
4373 #define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
4374 #define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
4375 
4376 /*******************  Bit definition for IWDG_RLR register  *******************/
4377 #define IWDG_RLR_RL_Pos                     (0U)
4378 #define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
4379 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
4380 
4381 /*******************  Bit definition for IWDG_SR register  ********************/
4382 #define IWDG_SR_PVU_Pos                     (0U)
4383 #define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
4384 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
4385 #define IWDG_SR_RVU_Pos                     (1U)
4386 #define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
4387 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
4388 
4389 /******************************************************************************/
4390 /*                                                                            */
4391 /*                         Window WATCHDOG (WWDG)                             */
4392 /*                                                                            */
4393 /******************************************************************************/
4394 
4395 /*******************  Bit definition for WWDG_CR register  ********************/
4396 #define WWDG_CR_T_Pos                       (0U)
4397 #define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */
4398 #define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
4399 #define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */
4400 #define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */
4401 #define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */
4402 #define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */
4403 #define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */
4404 #define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */
4405 #define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */
4406 
4407 /* Legacy defines */
4408 #define  WWDG_CR_T0 WWDG_CR_T_0
4409 #define  WWDG_CR_T1 WWDG_CR_T_1
4410 #define  WWDG_CR_T2 WWDG_CR_T_2
4411 #define  WWDG_CR_T3 WWDG_CR_T_3
4412 #define  WWDG_CR_T4 WWDG_CR_T_4
4413 #define  WWDG_CR_T5 WWDG_CR_T_5
4414 #define  WWDG_CR_T6 WWDG_CR_T_6
4415 
4416 #define WWDG_CR_WDGA_Pos                    (7U)
4417 #define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
4418 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
4419 
4420 /*******************  Bit definition for WWDG_CFR register  *******************/
4421 #define WWDG_CFR_W_Pos                      (0U)
4422 #define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
4423 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
4424 #define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
4425 #define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
4426 #define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
4427 #define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
4428 #define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
4429 #define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
4430 #define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
4431 
4432 /* Legacy defines */
4433 #define  WWDG_CFR_W0 WWDG_CFR_W_0
4434 #define  WWDG_CFR_W1 WWDG_CFR_W_1
4435 #define  WWDG_CFR_W2 WWDG_CFR_W_2
4436 #define  WWDG_CFR_W3 WWDG_CFR_W_3
4437 #define  WWDG_CFR_W4 WWDG_CFR_W_4
4438 #define  WWDG_CFR_W5 WWDG_CFR_W_5
4439 #define  WWDG_CFR_W6 WWDG_CFR_W_6
4440 
4441 #define WWDG_CFR_WDGTB_Pos                  (7U)
4442 #define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
4443 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
4444 #define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
4445 #define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
4446 
4447 /* Legacy defines */
4448 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
4449 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
4450 
4451 #define WWDG_CFR_EWI_Pos                    (9U)
4452 #define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
4453 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
4454 
4455 /*******************  Bit definition for WWDG_SR register  ********************/
4456 #define WWDG_SR_EWIF_Pos                    (0U)
4457 #define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
4458 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
4459 
4460 /******************************************************************************/
4461 /*                                                                            */
4462 /*                                   USB Device FS                            */
4463 /*                                                                            */
4464 /******************************************************************************/
4465 
4466 /*!< Endpoint-specific registers */
4467 #define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */
4468 #define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */
4469 #define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */
4470 #define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */
4471 #define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */
4472 #define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */
4473 #define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */
4474 #define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */
4475 
4476 /* bit positions */
4477 #define USB_EP_CTR_RX_Pos                       (15U)
4478 #define USB_EP_CTR_RX_Msk                       (0x1UL << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */
4479 #define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */
4480 #define USB_EP_DTOG_RX_Pos                      (14U)
4481 #define USB_EP_DTOG_RX_Msk                      (0x1UL << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */
4482 #define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */
4483 #define USB_EPRX_STAT_Pos                       (12U)
4484 #define USB_EPRX_STAT_Msk                       (0x3UL << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */
4485 #define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */
4486 #define USB_EP_SETUP_Pos                        (11U)
4487 #define USB_EP_SETUP_Msk                        (0x1UL << USB_EP_SETUP_Pos)     /*!< 0x00000800 */
4488 #define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */
4489 #define USB_EP_T_FIELD_Pos                      (9U)
4490 #define USB_EP_T_FIELD_Msk                      (0x3UL << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */
4491 #define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */
4492 #define USB_EP_KIND_Pos                         (8U)
4493 #define USB_EP_KIND_Msk                         (0x1UL << USB_EP_KIND_Pos)      /*!< 0x00000100 */
4494 #define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */
4495 #define USB_EP_CTR_TX_Pos                       (7U)
4496 #define USB_EP_CTR_TX_Msk                       (0x1UL << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */
4497 #define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */
4498 #define USB_EP_DTOG_TX_Pos                      (6U)
4499 #define USB_EP_DTOG_TX_Msk                      (0x1UL << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */
4500 #define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */
4501 #define USB_EPTX_STAT_Pos                       (4U)
4502 #define USB_EPTX_STAT_Msk                       (0x3UL << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */
4503 #define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */
4504 #define USB_EPADDR_FIELD_Pos                    (0U)
4505 #define USB_EPADDR_FIELD_Msk                    (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
4506 #define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */
4507 
4508 /* EndPoint REGister MASK (no toggle fields) */
4509 #define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4510                                                                            /*!< EP_TYPE[1:0] EndPoint TYPE */
4511 #define USB_EP_TYPE_MASK_Pos                    (9U)
4512 #define USB_EP_TYPE_MASK_Msk                    (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
4513 #define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */
4514 #define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */
4515 #define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */
4516 #define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */
4517 #define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */
4518 #define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)
4519 
4520 #define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */
4521                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
4522 #define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */
4523 #define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */
4524 #define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */
4525 #define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */
4526 #define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */
4527 #define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */
4528 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
4529                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
4530 #define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */
4531 #define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */
4532 #define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */
4533 #define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */
4534 #define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */
4535 #define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */
4536 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
4537 
4538 /*******************  Bit definition for USB_EP0R register  *******************/
4539 #define USB_EP0R_EA_Pos                         (0U)
4540 #define USB_EP0R_EA_Msk                         (0xFUL << USB_EP0R_EA_Pos)      /*!< 0x0000000F */
4541 #define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */
4542 
4543 #define USB_EP0R_STAT_TX_Pos                    (4U)
4544 #define USB_EP0R_STAT_TX_Msk                    (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
4545 #define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4546 #define USB_EP0R_STAT_TX_0                      (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
4547 #define USB_EP0R_STAT_TX_1                      (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
4548 
4549 #define USB_EP0R_DTOG_TX_Pos                    (6U)
4550 #define USB_EP0R_DTOG_TX_Msk                    (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
4551 #define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4552 #define USB_EP0R_CTR_TX_Pos                     (7U)
4553 #define USB_EP0R_CTR_TX_Msk                     (0x1UL << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */
4554 #define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4555 #define USB_EP0R_EP_KIND_Pos                    (8U)
4556 #define USB_EP0R_EP_KIND_Msk                    (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
4557 #define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */
4558 
4559 #define USB_EP0R_EP_TYPE_Pos                    (9U)
4560 #define USB_EP0R_EP_TYPE_Msk                    (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
4561 #define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4562 #define USB_EP0R_EP_TYPE_0                      (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
4563 #define USB_EP0R_EP_TYPE_1                      (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
4564 
4565 #define USB_EP0R_SETUP_Pos                      (11U)
4566 #define USB_EP0R_SETUP_Msk                      (0x1UL << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */
4567 #define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */
4568 
4569 #define USB_EP0R_STAT_RX_Pos                    (12U)
4570 #define USB_EP0R_STAT_RX_Msk                    (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
4571 #define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4572 #define USB_EP0R_STAT_RX_0                      (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
4573 #define USB_EP0R_STAT_RX_1                      (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
4574 
4575 #define USB_EP0R_DTOG_RX_Pos                    (14U)
4576 #define USB_EP0R_DTOG_RX_Msk                    (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
4577 #define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4578 #define USB_EP0R_CTR_RX_Pos                     (15U)
4579 #define USB_EP0R_CTR_RX_Msk                     (0x1UL << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */
4580 #define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4581 
4582 /*******************  Bit definition for USB_EP1R register  *******************/
4583 #define USB_EP1R_EA_Pos                         (0U)
4584 #define USB_EP1R_EA_Msk                         (0xFUL << USB_EP1R_EA_Pos)      /*!< 0x0000000F */
4585 #define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */
4586 
4587 #define USB_EP1R_STAT_TX_Pos                    (4U)
4588 #define USB_EP1R_STAT_TX_Msk                    (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
4589 #define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4590 #define USB_EP1R_STAT_TX_0                      (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
4591 #define USB_EP1R_STAT_TX_1                      (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
4592 
4593 #define USB_EP1R_DTOG_TX_Pos                    (6U)
4594 #define USB_EP1R_DTOG_TX_Msk                    (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
4595 #define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4596 #define USB_EP1R_CTR_TX_Pos                     (7U)
4597 #define USB_EP1R_CTR_TX_Msk                     (0x1UL << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */
4598 #define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4599 #define USB_EP1R_EP_KIND_Pos                    (8U)
4600 #define USB_EP1R_EP_KIND_Msk                    (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
4601 #define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */
4602 
4603 #define USB_EP1R_EP_TYPE_Pos                    (9U)
4604 #define USB_EP1R_EP_TYPE_Msk                    (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
4605 #define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4606 #define USB_EP1R_EP_TYPE_0                      (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
4607 #define USB_EP1R_EP_TYPE_1                      (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
4608 
4609 #define USB_EP1R_SETUP_Pos                      (11U)
4610 #define USB_EP1R_SETUP_Msk                      (0x1UL << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */
4611 #define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */
4612 
4613 #define USB_EP1R_STAT_RX_Pos                    (12U)
4614 #define USB_EP1R_STAT_RX_Msk                    (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
4615 #define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4616 #define USB_EP1R_STAT_RX_0                      (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
4617 #define USB_EP1R_STAT_RX_1                      (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
4618 
4619 #define USB_EP1R_DTOG_RX_Pos                    (14U)
4620 #define USB_EP1R_DTOG_RX_Msk                    (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
4621 #define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4622 #define USB_EP1R_CTR_RX_Pos                     (15U)
4623 #define USB_EP1R_CTR_RX_Msk                     (0x1UL << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */
4624 #define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4625 
4626 /*******************  Bit definition for USB_EP2R register  *******************/
4627 #define USB_EP2R_EA_Pos                         (0U)
4628 #define USB_EP2R_EA_Msk                         (0xFUL << USB_EP2R_EA_Pos)      /*!< 0x0000000F */
4629 #define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */
4630 
4631 #define USB_EP2R_STAT_TX_Pos                    (4U)
4632 #define USB_EP2R_STAT_TX_Msk                    (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
4633 #define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4634 #define USB_EP2R_STAT_TX_0                      (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
4635 #define USB_EP2R_STAT_TX_1                      (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
4636 
4637 #define USB_EP2R_DTOG_TX_Pos                    (6U)
4638 #define USB_EP2R_DTOG_TX_Msk                    (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
4639 #define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4640 #define USB_EP2R_CTR_TX_Pos                     (7U)
4641 #define USB_EP2R_CTR_TX_Msk                     (0x1UL << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */
4642 #define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4643 #define USB_EP2R_EP_KIND_Pos                    (8U)
4644 #define USB_EP2R_EP_KIND_Msk                    (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
4645 #define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */
4646 
4647 #define USB_EP2R_EP_TYPE_Pos                    (9U)
4648 #define USB_EP2R_EP_TYPE_Msk                    (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
4649 #define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4650 #define USB_EP2R_EP_TYPE_0                      (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
4651 #define USB_EP2R_EP_TYPE_1                      (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
4652 
4653 #define USB_EP2R_SETUP_Pos                      (11U)
4654 #define USB_EP2R_SETUP_Msk                      (0x1UL << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */
4655 #define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */
4656 
4657 #define USB_EP2R_STAT_RX_Pos                    (12U)
4658 #define USB_EP2R_STAT_RX_Msk                    (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
4659 #define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4660 #define USB_EP2R_STAT_RX_0                      (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
4661 #define USB_EP2R_STAT_RX_1                      (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
4662 
4663 #define USB_EP2R_DTOG_RX_Pos                    (14U)
4664 #define USB_EP2R_DTOG_RX_Msk                    (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
4665 #define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4666 #define USB_EP2R_CTR_RX_Pos                     (15U)
4667 #define USB_EP2R_CTR_RX_Msk                     (0x1UL << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */
4668 #define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4669 
4670 /*******************  Bit definition for USB_EP3R register  *******************/
4671 #define USB_EP3R_EA_Pos                         (0U)
4672 #define USB_EP3R_EA_Msk                         (0xFUL << USB_EP3R_EA_Pos)      /*!< 0x0000000F */
4673 #define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */
4674 
4675 #define USB_EP3R_STAT_TX_Pos                    (4U)
4676 #define USB_EP3R_STAT_TX_Msk                    (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
4677 #define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4678 #define USB_EP3R_STAT_TX_0                      (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
4679 #define USB_EP3R_STAT_TX_1                      (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
4680 
4681 #define USB_EP3R_DTOG_TX_Pos                    (6U)
4682 #define USB_EP3R_DTOG_TX_Msk                    (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
4683 #define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4684 #define USB_EP3R_CTR_TX_Pos                     (7U)
4685 #define USB_EP3R_CTR_TX_Msk                     (0x1UL << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */
4686 #define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4687 #define USB_EP3R_EP_KIND_Pos                    (8U)
4688 #define USB_EP3R_EP_KIND_Msk                    (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
4689 #define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */
4690 
4691 #define USB_EP3R_EP_TYPE_Pos                    (9U)
4692 #define USB_EP3R_EP_TYPE_Msk                    (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
4693 #define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4694 #define USB_EP3R_EP_TYPE_0                      (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
4695 #define USB_EP3R_EP_TYPE_1                      (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
4696 
4697 #define USB_EP3R_SETUP_Pos                      (11U)
4698 #define USB_EP3R_SETUP_Msk                      (0x1UL << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */
4699 #define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */
4700 
4701 #define USB_EP3R_STAT_RX_Pos                    (12U)
4702 #define USB_EP3R_STAT_RX_Msk                    (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
4703 #define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4704 #define USB_EP3R_STAT_RX_0                      (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
4705 #define USB_EP3R_STAT_RX_1                      (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
4706 
4707 #define USB_EP3R_DTOG_RX_Pos                    (14U)
4708 #define USB_EP3R_DTOG_RX_Msk                    (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
4709 #define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4710 #define USB_EP3R_CTR_RX_Pos                     (15U)
4711 #define USB_EP3R_CTR_RX_Msk                     (0x1UL << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */
4712 #define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4713 
4714 /*******************  Bit definition for USB_EP4R register  *******************/
4715 #define USB_EP4R_EA_Pos                         (0U)
4716 #define USB_EP4R_EA_Msk                         (0xFUL << USB_EP4R_EA_Pos)      /*!< 0x0000000F */
4717 #define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */
4718 
4719 #define USB_EP4R_STAT_TX_Pos                    (4U)
4720 #define USB_EP4R_STAT_TX_Msk                    (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
4721 #define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4722 #define USB_EP4R_STAT_TX_0                      (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
4723 #define USB_EP4R_STAT_TX_1                      (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
4724 
4725 #define USB_EP4R_DTOG_TX_Pos                    (6U)
4726 #define USB_EP4R_DTOG_TX_Msk                    (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
4727 #define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4728 #define USB_EP4R_CTR_TX_Pos                     (7U)
4729 #define USB_EP4R_CTR_TX_Msk                     (0x1UL << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */
4730 #define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4731 #define USB_EP4R_EP_KIND_Pos                    (8U)
4732 #define USB_EP4R_EP_KIND_Msk                    (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
4733 #define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */
4734 
4735 #define USB_EP4R_EP_TYPE_Pos                    (9U)
4736 #define USB_EP4R_EP_TYPE_Msk                    (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
4737 #define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4738 #define USB_EP4R_EP_TYPE_0                      (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
4739 #define USB_EP4R_EP_TYPE_1                      (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
4740 
4741 #define USB_EP4R_SETUP_Pos                      (11U)
4742 #define USB_EP4R_SETUP_Msk                      (0x1UL << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */
4743 #define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */
4744 
4745 #define USB_EP4R_STAT_RX_Pos                    (12U)
4746 #define USB_EP4R_STAT_RX_Msk                    (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
4747 #define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4748 #define USB_EP4R_STAT_RX_0                      (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
4749 #define USB_EP4R_STAT_RX_1                      (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
4750 
4751 #define USB_EP4R_DTOG_RX_Pos                    (14U)
4752 #define USB_EP4R_DTOG_RX_Msk                    (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
4753 #define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4754 #define USB_EP4R_CTR_RX_Pos                     (15U)
4755 #define USB_EP4R_CTR_RX_Msk                     (0x1UL << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */
4756 #define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4757 
4758 /*******************  Bit definition for USB_EP5R register  *******************/
4759 #define USB_EP5R_EA_Pos                         (0U)
4760 #define USB_EP5R_EA_Msk                         (0xFUL << USB_EP5R_EA_Pos)      /*!< 0x0000000F */
4761 #define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */
4762 
4763 #define USB_EP5R_STAT_TX_Pos                    (4U)
4764 #define USB_EP5R_STAT_TX_Msk                    (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
4765 #define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4766 #define USB_EP5R_STAT_TX_0                      (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
4767 #define USB_EP5R_STAT_TX_1                      (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
4768 
4769 #define USB_EP5R_DTOG_TX_Pos                    (6U)
4770 #define USB_EP5R_DTOG_TX_Msk                    (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
4771 #define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4772 #define USB_EP5R_CTR_TX_Pos                     (7U)
4773 #define USB_EP5R_CTR_TX_Msk                     (0x1UL << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */
4774 #define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4775 #define USB_EP5R_EP_KIND_Pos                    (8U)
4776 #define USB_EP5R_EP_KIND_Msk                    (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
4777 #define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */
4778 
4779 #define USB_EP5R_EP_TYPE_Pos                    (9U)
4780 #define USB_EP5R_EP_TYPE_Msk                    (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
4781 #define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4782 #define USB_EP5R_EP_TYPE_0                      (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
4783 #define USB_EP5R_EP_TYPE_1                      (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
4784 
4785 #define USB_EP5R_SETUP_Pos                      (11U)
4786 #define USB_EP5R_SETUP_Msk                      (0x1UL << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */
4787 #define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */
4788 
4789 #define USB_EP5R_STAT_RX_Pos                    (12U)
4790 #define USB_EP5R_STAT_RX_Msk                    (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
4791 #define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4792 #define USB_EP5R_STAT_RX_0                      (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
4793 #define USB_EP5R_STAT_RX_1                      (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
4794 
4795 #define USB_EP5R_DTOG_RX_Pos                    (14U)
4796 #define USB_EP5R_DTOG_RX_Msk                    (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
4797 #define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4798 #define USB_EP5R_CTR_RX_Pos                     (15U)
4799 #define USB_EP5R_CTR_RX_Msk                     (0x1UL << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */
4800 #define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4801 
4802 /*******************  Bit definition for USB_EP6R register  *******************/
4803 #define USB_EP6R_EA_Pos                         (0U)
4804 #define USB_EP6R_EA_Msk                         (0xFUL << USB_EP6R_EA_Pos)      /*!< 0x0000000F */
4805 #define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */
4806 
4807 #define USB_EP6R_STAT_TX_Pos                    (4U)
4808 #define USB_EP6R_STAT_TX_Msk                    (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
4809 #define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4810 #define USB_EP6R_STAT_TX_0                      (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
4811 #define USB_EP6R_STAT_TX_1                      (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
4812 
4813 #define USB_EP6R_DTOG_TX_Pos                    (6U)
4814 #define USB_EP6R_DTOG_TX_Msk                    (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
4815 #define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4816 #define USB_EP6R_CTR_TX_Pos                     (7U)
4817 #define USB_EP6R_CTR_TX_Msk                     (0x1UL << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */
4818 #define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4819 #define USB_EP6R_EP_KIND_Pos                    (8U)
4820 #define USB_EP6R_EP_KIND_Msk                    (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
4821 #define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */
4822 
4823 #define USB_EP6R_EP_TYPE_Pos                    (9U)
4824 #define USB_EP6R_EP_TYPE_Msk                    (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
4825 #define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4826 #define USB_EP6R_EP_TYPE_0                      (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
4827 #define USB_EP6R_EP_TYPE_1                      (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
4828 
4829 #define USB_EP6R_SETUP_Pos                      (11U)
4830 #define USB_EP6R_SETUP_Msk                      (0x1UL << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */
4831 #define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */
4832 
4833 #define USB_EP6R_STAT_RX_Pos                    (12U)
4834 #define USB_EP6R_STAT_RX_Msk                    (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
4835 #define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4836 #define USB_EP6R_STAT_RX_0                      (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
4837 #define USB_EP6R_STAT_RX_1                      (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
4838 
4839 #define USB_EP6R_DTOG_RX_Pos                    (14U)
4840 #define USB_EP6R_DTOG_RX_Msk                    (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
4841 #define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4842 #define USB_EP6R_CTR_RX_Pos                     (15U)
4843 #define USB_EP6R_CTR_RX_Msk                     (0x1UL << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */
4844 #define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4845 
4846 /*******************  Bit definition for USB_EP7R register  *******************/
4847 #define USB_EP7R_EA_Pos                         (0U)
4848 #define USB_EP7R_EA_Msk                         (0xFUL << USB_EP7R_EA_Pos)      /*!< 0x0000000F */
4849 #define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */
4850 
4851 #define USB_EP7R_STAT_TX_Pos                    (4U)
4852 #define USB_EP7R_STAT_TX_Msk                    (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
4853 #define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4854 #define USB_EP7R_STAT_TX_0                      (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
4855 #define USB_EP7R_STAT_TX_1                      (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
4856 
4857 #define USB_EP7R_DTOG_TX_Pos                    (6U)
4858 #define USB_EP7R_DTOG_TX_Msk                    (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
4859 #define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
4860 #define USB_EP7R_CTR_TX_Pos                     (7U)
4861 #define USB_EP7R_CTR_TX_Msk                     (0x1UL << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */
4862 #define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
4863 #define USB_EP7R_EP_KIND_Pos                    (8U)
4864 #define USB_EP7R_EP_KIND_Msk                    (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
4865 #define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */
4866 
4867 #define USB_EP7R_EP_TYPE_Pos                    (9U)
4868 #define USB_EP7R_EP_TYPE_Msk                    (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
4869 #define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
4870 #define USB_EP7R_EP_TYPE_0                      (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
4871 #define USB_EP7R_EP_TYPE_1                      (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
4872 
4873 #define USB_EP7R_SETUP_Pos                      (11U)
4874 #define USB_EP7R_SETUP_Msk                      (0x1UL << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */
4875 #define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */
4876 
4877 #define USB_EP7R_STAT_RX_Pos                    (12U)
4878 #define USB_EP7R_STAT_RX_Msk                    (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
4879 #define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4880 #define USB_EP7R_STAT_RX_0                      (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
4881 #define USB_EP7R_STAT_RX_1                      (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
4882 
4883 #define USB_EP7R_DTOG_RX_Pos                    (14U)
4884 #define USB_EP7R_DTOG_RX_Msk                    (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
4885 #define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
4886 #define USB_EP7R_CTR_RX_Pos                     (15U)
4887 #define USB_EP7R_CTR_RX_Msk                     (0x1UL << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */
4888 #define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */
4889 
4890 /*!< Common registers */
4891 /*******************  Bit definition for USB_CNTR register  *******************/
4892 #define USB_CNTR_FRES_Pos                       (0U)
4893 #define USB_CNTR_FRES_Msk                       (0x1UL << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */
4894 #define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */
4895 #define USB_CNTR_PDWN_Pos                       (1U)
4896 #define USB_CNTR_PDWN_Msk                       (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
4897 #define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */
4898 #define USB_CNTR_LP_MODE_Pos                    (2U)
4899 #define USB_CNTR_LP_MODE_Msk                    (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
4900 #define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */
4901 #define USB_CNTR_FSUSP_Pos                      (3U)
4902 #define USB_CNTR_FSUSP_Msk                      (0x1UL << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */
4903 #define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */
4904 #define USB_CNTR_RESUME_Pos                     (4U)
4905 #define USB_CNTR_RESUME_Msk                     (0x1UL << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */
4906 #define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */
4907 #define USB_CNTR_ESOFM_Pos                      (8U)
4908 #define USB_CNTR_ESOFM_Msk                      (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
4909 #define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */
4910 #define USB_CNTR_SOFM_Pos                       (9U)
4911 #define USB_CNTR_SOFM_Msk                       (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
4912 #define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */
4913 #define USB_CNTR_RESETM_Pos                     (10U)
4914 #define USB_CNTR_RESETM_Msk                     (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
4915 #define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */
4916 #define USB_CNTR_SUSPM_Pos                      (11U)
4917 #define USB_CNTR_SUSPM_Msk                      (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
4918 #define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */
4919 #define USB_CNTR_WKUPM_Pos                      (12U)
4920 #define USB_CNTR_WKUPM_Msk                      (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
4921 #define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */
4922 #define USB_CNTR_ERRM_Pos                       (13U)
4923 #define USB_CNTR_ERRM_Msk                       (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
4924 #define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */
4925 #define USB_CNTR_PMAOVRM_Pos                    (14U)
4926 #define USB_CNTR_PMAOVRM_Msk                    (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
4927 #define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */
4928 #define USB_CNTR_CTRM_Pos                       (15U)
4929 #define USB_CNTR_CTRM_Msk                       (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
4930 #define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */
4931 
4932 /*******************  Bit definition for USB_ISTR register  *******************/
4933 #define USB_ISTR_EP_ID_Pos                      (0U)
4934 #define USB_ISTR_EP_ID_Msk                      (0xFUL << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */
4935 #define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */
4936 #define USB_ISTR_DIR_Pos                        (4U)
4937 #define USB_ISTR_DIR_Msk                        (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
4938 #define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */
4939 #define USB_ISTR_ESOF_Pos                       (8U)
4940 #define USB_ISTR_ESOF_Msk                       (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
4941 #define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */
4942 #define USB_ISTR_SOF_Pos                        (9U)
4943 #define USB_ISTR_SOF_Msk                        (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
4944 #define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */
4945 #define USB_ISTR_RESET_Pos                      (10U)
4946 #define USB_ISTR_RESET_Msk                      (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
4947 #define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */
4948 #define USB_ISTR_SUSP_Pos                       (11U)
4949 #define USB_ISTR_SUSP_Msk                       (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
4950 #define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */
4951 #define USB_ISTR_WKUP_Pos                       (12U)
4952 #define USB_ISTR_WKUP_Msk                       (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
4953 #define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */
4954 #define USB_ISTR_ERR_Pos                        (13U)
4955 #define USB_ISTR_ERR_Msk                        (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
4956 #define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */
4957 #define USB_ISTR_PMAOVR_Pos                     (14U)
4958 #define USB_ISTR_PMAOVR_Msk                     (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
4959 #define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */
4960 #define USB_ISTR_CTR_Pos                        (15U)
4961 #define USB_ISTR_CTR_Msk                        (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
4962 #define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */
4963 
4964 /*******************  Bit definition for USB_FNR register  ********************/
4965 #define USB_FNR_FN_Pos                          (0U)
4966 #define USB_FNR_FN_Msk                          (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
4967 #define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */
4968 #define USB_FNR_LSOF_Pos                        (11U)
4969 #define USB_FNR_LSOF_Msk                        (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
4970 #define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */
4971 #define USB_FNR_LCK_Pos                         (13U)
4972 #define USB_FNR_LCK_Msk                         (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
4973 #define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */
4974 #define USB_FNR_RXDM_Pos                        (14U)
4975 #define USB_FNR_RXDM_Msk                        (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
4976 #define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */
4977 #define USB_FNR_RXDP_Pos                        (15U)
4978 #define USB_FNR_RXDP_Msk                        (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
4979 #define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */
4980 
4981 /******************  Bit definition for USB_DADDR register  *******************/
4982 #define USB_DADDR_ADD_Pos                       (0U)
4983 #define USB_DADDR_ADD_Msk                       (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
4984 #define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */
4985 #define USB_DADDR_ADD0_Pos                      (0U)
4986 #define USB_DADDR_ADD0_Msk                      (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
4987 #define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */
4988 #define USB_DADDR_ADD1_Pos                      (1U)
4989 #define USB_DADDR_ADD1_Msk                      (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
4990 #define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */
4991 #define USB_DADDR_ADD2_Pos                      (2U)
4992 #define USB_DADDR_ADD2_Msk                      (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
4993 #define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */
4994 #define USB_DADDR_ADD3_Pos                      (3U)
4995 #define USB_DADDR_ADD3_Msk                      (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
4996 #define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */
4997 #define USB_DADDR_ADD4_Pos                      (4U)
4998 #define USB_DADDR_ADD4_Msk                      (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
4999 #define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */
5000 #define USB_DADDR_ADD5_Pos                      (5U)
5001 #define USB_DADDR_ADD5_Msk                      (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
5002 #define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */
5003 #define USB_DADDR_ADD6_Pos                      (6U)
5004 #define USB_DADDR_ADD6_Msk                      (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
5005 #define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */
5006 
5007 #define USB_DADDR_EF_Pos                        (7U)
5008 #define USB_DADDR_EF_Msk                        (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
5009 #define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */
5010 
5011 /******************  Bit definition for USB_BTABLE register  ******************/
5012 #define USB_BTABLE_BTABLE_Pos                   (3U)
5013 #define USB_BTABLE_BTABLE_Msk                   (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
5014 #define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */
5015 
5016 /*!< Buffer descriptor table */
5017 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
5018 #define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)
5019 #define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
5020 #define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */
5021 
5022 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
5023 #define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)
5024 #define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
5025 #define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */
5026 
5027 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
5028 #define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)
5029 #define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
5030 #define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */
5031 
5032 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
5033 #define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)
5034 #define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
5035 #define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */
5036 
5037 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
5038 #define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)
5039 #define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
5040 #define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */
5041 
5042 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
5043 #define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)
5044 #define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
5045 #define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */
5046 
5047 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
5048 #define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)
5049 #define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
5050 #define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */
5051 
5052 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
5053 #define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)
5054 #define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
5055 #define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */
5056 
5057 /*----------------------------------------------------------------------------*/
5058 
5059 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
5060 #define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)
5061 #define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
5062 #define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */
5063 
5064 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
5065 #define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)
5066 #define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
5067 #define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */
5068 
5069 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
5070 #define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)
5071 #define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
5072 #define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */
5073 
5074 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
5075 #define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)
5076 #define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
5077 #define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */
5078 
5079 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
5080 #define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)
5081 #define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
5082 #define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */
5083 
5084 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
5085 #define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)
5086 #define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
5087 #define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */
5088 
5089 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
5090 #define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)
5091 #define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
5092 #define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */
5093 
5094 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
5095 #define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)
5096 #define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
5097 #define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */
5098 
5099 /*----------------------------------------------------------------------------*/
5100 
5101 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
5102 #define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */
5103 
5104 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
5105 #define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */
5106 
5107 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
5108 #define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */
5109 
5110 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
5111 #define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */
5112 
5113 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
5114 #define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */
5115 
5116 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
5117 #define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */
5118 
5119 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
5120 #define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */
5121 
5122 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
5123 #define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */
5124 
5125 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
5126 #define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */
5127 
5128 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
5129 #define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */
5130 
5131 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
5132 #define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */
5133 
5134 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
5135 #define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */
5136 
5137 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
5138 #define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */
5139 
5140 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
5141 #define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */
5142 
5143 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
5144 #define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */
5145 
5146 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
5147 #define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */
5148 
5149 /*----------------------------------------------------------------------------*/
5150 
5151 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
5152 #define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)
5153 #define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
5154 #define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */
5155 
5156 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
5157 #define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)
5158 #define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
5159 #define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */
5160 
5161 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
5162 #define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)
5163 #define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
5164 #define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */
5165 
5166 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
5167 #define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)
5168 #define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
5169 #define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */
5170 
5171 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
5172 #define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)
5173 #define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
5174 #define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */
5175 
5176 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
5177 #define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)
5178 #define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
5179 #define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */
5180 
5181 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
5182 #define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)
5183 #define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
5184 #define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */
5185 
5186 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
5187 #define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)
5188 #define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
5189 #define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */
5190 
5191 /*----------------------------------------------------------------------------*/
5192 
5193 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
5194 #define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)
5195 #define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
5196 #define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */
5197 
5198 #define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)
5199 #define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5200 #define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5201 #define USB_COUNT0_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5202 #define USB_COUNT0_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5203 #define USB_COUNT0_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5204 #define USB_COUNT0_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5205 #define USB_COUNT0_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5206 
5207 #define USB_COUNT0_RX_BLSIZE_Pos                (15U)
5208 #define USB_COUNT0_RX_BLSIZE_Msk                (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
5209 #define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */
5210 
5211 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
5212 #define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)
5213 #define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
5214 #define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */
5215 
5216 #define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)
5217 #define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5218 #define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5219 #define USB_COUNT1_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5220 #define USB_COUNT1_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5221 #define USB_COUNT1_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5222 #define USB_COUNT1_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5223 #define USB_COUNT1_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5224 
5225 #define USB_COUNT1_RX_BLSIZE_Pos                (15U)
5226 #define USB_COUNT1_RX_BLSIZE_Msk                (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
5227 #define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */
5228 
5229 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
5230 #define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)
5231 #define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
5232 #define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */
5233 
5234 #define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)
5235 #define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5236 #define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5237 #define USB_COUNT2_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5238 #define USB_COUNT2_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5239 #define USB_COUNT2_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5240 #define USB_COUNT2_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5241 #define USB_COUNT2_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5242 
5243 #define USB_COUNT2_RX_BLSIZE_Pos                (15U)
5244 #define USB_COUNT2_RX_BLSIZE_Msk                (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
5245 #define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */
5246 
5247 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
5248 #define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)
5249 #define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
5250 #define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */
5251 
5252 #define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)
5253 #define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5254 #define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5255 #define USB_COUNT3_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5256 #define USB_COUNT3_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5257 #define USB_COUNT3_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5258 #define USB_COUNT3_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5259 #define USB_COUNT3_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5260 
5261 #define USB_COUNT3_RX_BLSIZE_Pos                (15U)
5262 #define USB_COUNT3_RX_BLSIZE_Msk                (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
5263 #define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */
5264 
5265 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
5266 #define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)
5267 #define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
5268 #define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */
5269 
5270 #define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)
5271 #define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5272 #define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5273 #define USB_COUNT4_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5274 #define USB_COUNT4_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5275 #define USB_COUNT4_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5276 #define USB_COUNT4_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5277 #define USB_COUNT4_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5278 
5279 #define USB_COUNT4_RX_BLSIZE_Pos                (15U)
5280 #define USB_COUNT4_RX_BLSIZE_Msk                (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
5281 #define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */
5282 
5283 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
5284 #define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)
5285 #define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
5286 #define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */
5287 
5288 #define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)
5289 #define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5290 #define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5291 #define USB_COUNT5_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5292 #define USB_COUNT5_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5293 #define USB_COUNT5_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5294 #define USB_COUNT5_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5295 #define USB_COUNT5_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5296 
5297 #define USB_COUNT5_RX_BLSIZE_Pos                (15U)
5298 #define USB_COUNT5_RX_BLSIZE_Msk                (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
5299 #define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */
5300 
5301 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
5302 #define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)
5303 #define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
5304 #define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */
5305 
5306 #define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)
5307 #define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5308 #define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5309 #define USB_COUNT6_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5310 #define USB_COUNT6_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5311 #define USB_COUNT6_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5312 #define USB_COUNT6_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5313 #define USB_COUNT6_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5314 
5315 #define USB_COUNT6_RX_BLSIZE_Pos                (15U)
5316 #define USB_COUNT6_RX_BLSIZE_Msk                (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
5317 #define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */
5318 
5319 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
5320 #define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)
5321 #define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
5322 #define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */
5323 
5324 #define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)
5325 #define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5326 #define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5327 #define USB_COUNT7_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5328 #define USB_COUNT7_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5329 #define USB_COUNT7_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5330 #define USB_COUNT7_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5331 #define USB_COUNT7_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5332 
5333 #define USB_COUNT7_RX_BLSIZE_Pos                (15U)
5334 #define USB_COUNT7_RX_BLSIZE_Msk                (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
5335 #define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */
5336 
5337 /*----------------------------------------------------------------------------*/
5338 
5339 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
5340 #define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5341 
5342 #define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5343 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5344 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5345 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5346 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5347 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5348 
5349 #define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5350 
5351 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
5352 #define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5353 
5354 #define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5355 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */
5356 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5357 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5358 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5359 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5360 
5361 #define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5362 
5363 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
5364 #define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5365 
5366 #define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5367 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5368 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5369 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5370 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5371 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5372 
5373 #define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5374 
5375 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
5376 #define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5377 
5378 #define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5379 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5380 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5381 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5382 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5383 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5384 
5385 #define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5386 
5387 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
5388 #define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5389 
5390 #define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5391 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5392 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5393 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5394 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5395 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5396 
5397 #define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5398 
5399 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
5400 #define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5401 
5402 #define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5403 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5404 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5405 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5406 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5407 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5408 
5409 #define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5410 
5411 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
5412 #define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5413 
5414 #define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5415 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5416 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5417 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5418 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5419 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5420 
5421 #define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5422 
5423 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
5424 #define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5425 
5426 #define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5427 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5428 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5429 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5430 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5431 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5432 
5433 #define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5434 
5435 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
5436 #define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5437 
5438 #define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5439 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5440 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5441 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5442 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5443 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5444 
5445 #define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5446 
5447 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
5448 #define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5449 
5450 #define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5451 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5452 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5453 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5454 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5455 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5456 
5457 #define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5458 
5459 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
5460 #define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5461 
5462 #define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5463 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5464 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5465 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5466 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5467 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5468 
5469 #define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5470 
5471 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
5472 #define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5473 
5474 #define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5475 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5476 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5477 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5478 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5479 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5480 
5481 #define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5482 
5483 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
5484 #define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5485 
5486 #define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5487 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5488 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5489 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5490 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5491 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5492 
5493 #define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5494 
5495 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
5496 #define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */
5497 
5498 #define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5499 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */
5500 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */
5501 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */
5502 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */
5503 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */
5504 
5505 #define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */
5506 
5507 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
5508 #define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
5509 
5510 #define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5511 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
5512 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
5513 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
5514 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
5515 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
5516 
5517 #define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
5518 
5519 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
5520 #define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
5521 
5522 #define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5523 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
5524 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
5525 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
5526 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
5527 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
5528 
5529 #define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
5530 
5531 /******************************************************************************/
5532 /*                                                                            */
5533 /*                         Controller Area Network                            */
5534 /*                                                                            */
5535 /******************************************************************************/
5536 
5537 /*!< CAN control and status registers */
5538 /*******************  Bit definition for CAN_MCR register  ********************/
5539 #define CAN_MCR_INRQ_Pos                     (0U)
5540 #define CAN_MCR_INRQ_Msk                     (0x1UL << CAN_MCR_INRQ_Pos)        /*!< 0x00000001 */
5541 #define CAN_MCR_INRQ                         CAN_MCR_INRQ_Msk                  /*!< Initialization Request */
5542 #define CAN_MCR_SLEEP_Pos                    (1U)
5543 #define CAN_MCR_SLEEP_Msk                    (0x1UL << CAN_MCR_SLEEP_Pos)       /*!< 0x00000002 */
5544 #define CAN_MCR_SLEEP                        CAN_MCR_SLEEP_Msk                 /*!< Sleep Mode Request */
5545 #define CAN_MCR_TXFP_Pos                     (2U)
5546 #define CAN_MCR_TXFP_Msk                     (0x1UL << CAN_MCR_TXFP_Pos)        /*!< 0x00000004 */
5547 #define CAN_MCR_TXFP                         CAN_MCR_TXFP_Msk                  /*!< Transmit FIFO Priority */
5548 #define CAN_MCR_RFLM_Pos                     (3U)
5549 #define CAN_MCR_RFLM_Msk                     (0x1UL << CAN_MCR_RFLM_Pos)        /*!< 0x00000008 */
5550 #define CAN_MCR_RFLM                         CAN_MCR_RFLM_Msk                  /*!< Receive FIFO Locked Mode */
5551 #define CAN_MCR_NART_Pos                     (4U)
5552 #define CAN_MCR_NART_Msk                     (0x1UL << CAN_MCR_NART_Pos)        /*!< 0x00000010 */
5553 #define CAN_MCR_NART                         CAN_MCR_NART_Msk                  /*!< No Automatic Retransmission */
5554 #define CAN_MCR_AWUM_Pos                     (5U)
5555 #define CAN_MCR_AWUM_Msk                     (0x1UL << CAN_MCR_AWUM_Pos)        /*!< 0x00000020 */
5556 #define CAN_MCR_AWUM                         CAN_MCR_AWUM_Msk                  /*!< Automatic Wakeup Mode */
5557 #define CAN_MCR_ABOM_Pos                     (6U)
5558 #define CAN_MCR_ABOM_Msk                     (0x1UL << CAN_MCR_ABOM_Pos)        /*!< 0x00000040 */
5559 #define CAN_MCR_ABOM                         CAN_MCR_ABOM_Msk                  /*!< Automatic Bus-Off Management */
5560 #define CAN_MCR_TTCM_Pos                     (7U)
5561 #define CAN_MCR_TTCM_Msk                     (0x1UL << CAN_MCR_TTCM_Pos)        /*!< 0x00000080 */
5562 #define CAN_MCR_TTCM                         CAN_MCR_TTCM_Msk                  /*!< Time Triggered Communication Mode */
5563 #define CAN_MCR_RESET_Pos                    (15U)
5564 #define CAN_MCR_RESET_Msk                    (0x1UL << CAN_MCR_RESET_Pos)       /*!< 0x00008000 */
5565 #define CAN_MCR_RESET                        CAN_MCR_RESET_Msk                 /*!< CAN software master reset */
5566 #define CAN_MCR_DBF_Pos                      (16U)
5567 #define CAN_MCR_DBF_Msk                      (0x1UL << CAN_MCR_DBF_Pos)         /*!< 0x00010000 */
5568 #define CAN_MCR_DBF                          CAN_MCR_DBF_Msk                   /*!< CAN Debug freeze */
5569 
5570 /*******************  Bit definition for CAN_MSR register  ********************/
5571 #define CAN_MSR_INAK_Pos                     (0U)
5572 #define CAN_MSR_INAK_Msk                     (0x1UL << CAN_MSR_INAK_Pos)        /*!< 0x00000001 */
5573 #define CAN_MSR_INAK                         CAN_MSR_INAK_Msk                  /*!< Initialization Acknowledge */
5574 #define CAN_MSR_SLAK_Pos                     (1U)
5575 #define CAN_MSR_SLAK_Msk                     (0x1UL << CAN_MSR_SLAK_Pos)        /*!< 0x00000002 */
5576 #define CAN_MSR_SLAK                         CAN_MSR_SLAK_Msk                  /*!< Sleep Acknowledge */
5577 #define CAN_MSR_ERRI_Pos                     (2U)
5578 #define CAN_MSR_ERRI_Msk                     (0x1UL << CAN_MSR_ERRI_Pos)        /*!< 0x00000004 */
5579 #define CAN_MSR_ERRI                         CAN_MSR_ERRI_Msk                  /*!< Error Interrupt */
5580 #define CAN_MSR_WKUI_Pos                     (3U)
5581 #define CAN_MSR_WKUI_Msk                     (0x1UL << CAN_MSR_WKUI_Pos)        /*!< 0x00000008 */
5582 #define CAN_MSR_WKUI                         CAN_MSR_WKUI_Msk                  /*!< Wakeup Interrupt */
5583 #define CAN_MSR_SLAKI_Pos                    (4U)
5584 #define CAN_MSR_SLAKI_Msk                    (0x1UL << CAN_MSR_SLAKI_Pos)       /*!< 0x00000010 */
5585 #define CAN_MSR_SLAKI                        CAN_MSR_SLAKI_Msk                 /*!< Sleep Acknowledge Interrupt */
5586 #define CAN_MSR_TXM_Pos                      (8U)
5587 #define CAN_MSR_TXM_Msk                      (0x1UL << CAN_MSR_TXM_Pos)         /*!< 0x00000100 */
5588 #define CAN_MSR_TXM                          CAN_MSR_TXM_Msk                   /*!< Transmit Mode */
5589 #define CAN_MSR_RXM_Pos                      (9U)
5590 #define CAN_MSR_RXM_Msk                      (0x1UL << CAN_MSR_RXM_Pos)         /*!< 0x00000200 */
5591 #define CAN_MSR_RXM                          CAN_MSR_RXM_Msk                   /*!< Receive Mode */
5592 #define CAN_MSR_SAMP_Pos                     (10U)
5593 #define CAN_MSR_SAMP_Msk                     (0x1UL << CAN_MSR_SAMP_Pos)        /*!< 0x00000400 */
5594 #define CAN_MSR_SAMP                         CAN_MSR_SAMP_Msk                  /*!< Last Sample Point */
5595 #define CAN_MSR_RX_Pos                       (11U)
5596 #define CAN_MSR_RX_Msk                       (0x1UL << CAN_MSR_RX_Pos)          /*!< 0x00000800 */
5597 #define CAN_MSR_RX                           CAN_MSR_RX_Msk                    /*!< CAN Rx Signal */
5598 
5599 /*******************  Bit definition for CAN_TSR register  ********************/
5600 #define CAN_TSR_RQCP0_Pos                    (0U)
5601 #define CAN_TSR_RQCP0_Msk                    (0x1UL << CAN_TSR_RQCP0_Pos)       /*!< 0x00000001 */
5602 #define CAN_TSR_RQCP0                        CAN_TSR_RQCP0_Msk                 /*!< Request Completed Mailbox0 */
5603 #define CAN_TSR_TXOK0_Pos                    (1U)
5604 #define CAN_TSR_TXOK0_Msk                    (0x1UL << CAN_TSR_TXOK0_Pos)       /*!< 0x00000002 */
5605 #define CAN_TSR_TXOK0                        CAN_TSR_TXOK0_Msk                 /*!< Transmission OK of Mailbox0 */
5606 #define CAN_TSR_ALST0_Pos                    (2U)
5607 #define CAN_TSR_ALST0_Msk                    (0x1UL << CAN_TSR_ALST0_Pos)       /*!< 0x00000004 */
5608 #define CAN_TSR_ALST0                        CAN_TSR_ALST0_Msk                 /*!< Arbitration Lost for Mailbox0 */
5609 #define CAN_TSR_TERR0_Pos                    (3U)
5610 #define CAN_TSR_TERR0_Msk                    (0x1UL << CAN_TSR_TERR0_Pos)       /*!< 0x00000008 */
5611 #define CAN_TSR_TERR0                        CAN_TSR_TERR0_Msk                 /*!< Transmission Error of Mailbox0 */
5612 #define CAN_TSR_ABRQ0_Pos                    (7U)
5613 #define CAN_TSR_ABRQ0_Msk                    (0x1UL << CAN_TSR_ABRQ0_Pos)       /*!< 0x00000080 */
5614 #define CAN_TSR_ABRQ0                        CAN_TSR_ABRQ0_Msk                 /*!< Abort Request for Mailbox0 */
5615 #define CAN_TSR_RQCP1_Pos                    (8U)
5616 #define CAN_TSR_RQCP1_Msk                    (0x1UL << CAN_TSR_RQCP1_Pos)       /*!< 0x00000100 */
5617 #define CAN_TSR_RQCP1                        CAN_TSR_RQCP1_Msk                 /*!< Request Completed Mailbox1 */
5618 #define CAN_TSR_TXOK1_Pos                    (9U)
5619 #define CAN_TSR_TXOK1_Msk                    (0x1UL << CAN_TSR_TXOK1_Pos)       /*!< 0x00000200 */
5620 #define CAN_TSR_TXOK1                        CAN_TSR_TXOK1_Msk                 /*!< Transmission OK of Mailbox1 */
5621 #define CAN_TSR_ALST1_Pos                    (10U)
5622 #define CAN_TSR_ALST1_Msk                    (0x1UL << CAN_TSR_ALST1_Pos)       /*!< 0x00000400 */
5623 #define CAN_TSR_ALST1                        CAN_TSR_ALST1_Msk                 /*!< Arbitration Lost for Mailbox1 */
5624 #define CAN_TSR_TERR1_Pos                    (11U)
5625 #define CAN_TSR_TERR1_Msk                    (0x1UL << CAN_TSR_TERR1_Pos)       /*!< 0x00000800 */
5626 #define CAN_TSR_TERR1                        CAN_TSR_TERR1_Msk                 /*!< Transmission Error of Mailbox1 */
5627 #define CAN_TSR_ABRQ1_Pos                    (15U)
5628 #define CAN_TSR_ABRQ1_Msk                    (0x1UL << CAN_TSR_ABRQ1_Pos)       /*!< 0x00008000 */
5629 #define CAN_TSR_ABRQ1                        CAN_TSR_ABRQ1_Msk                 /*!< Abort Request for Mailbox 1 */
5630 #define CAN_TSR_RQCP2_Pos                    (16U)
5631 #define CAN_TSR_RQCP2_Msk                    (0x1UL << CAN_TSR_RQCP2_Pos)       /*!< 0x00010000 */
5632 #define CAN_TSR_RQCP2                        CAN_TSR_RQCP2_Msk                 /*!< Request Completed Mailbox2 */
5633 #define CAN_TSR_TXOK2_Pos                    (17U)
5634 #define CAN_TSR_TXOK2_Msk                    (0x1UL << CAN_TSR_TXOK2_Pos)       /*!< 0x00020000 */
5635 #define CAN_TSR_TXOK2                        CAN_TSR_TXOK2_Msk                 /*!< Transmission OK of Mailbox 2 */
5636 #define CAN_TSR_ALST2_Pos                    (18U)
5637 #define CAN_TSR_ALST2_Msk                    (0x1UL << CAN_TSR_ALST2_Pos)       /*!< 0x00040000 */
5638 #define CAN_TSR_ALST2                        CAN_TSR_ALST2_Msk                 /*!< Arbitration Lost for mailbox 2 */
5639 #define CAN_TSR_TERR2_Pos                    (19U)
5640 #define CAN_TSR_TERR2_Msk                    (0x1UL << CAN_TSR_TERR2_Pos)       /*!< 0x00080000 */
5641 #define CAN_TSR_TERR2                        CAN_TSR_TERR2_Msk                 /*!< Transmission Error of Mailbox 2 */
5642 #define CAN_TSR_ABRQ2_Pos                    (23U)
5643 #define CAN_TSR_ABRQ2_Msk                    (0x1UL << CAN_TSR_ABRQ2_Pos)       /*!< 0x00800000 */
5644 #define CAN_TSR_ABRQ2                        CAN_TSR_ABRQ2_Msk                 /*!< Abort Request for Mailbox 2 */
5645 #define CAN_TSR_CODE_Pos                     (24U)
5646 #define CAN_TSR_CODE_Msk                     (0x3UL << CAN_TSR_CODE_Pos)        /*!< 0x03000000 */
5647 #define CAN_TSR_CODE                         CAN_TSR_CODE_Msk                  /*!< Mailbox Code */
5648 
5649 #define CAN_TSR_TME_Pos                      (26U)
5650 #define CAN_TSR_TME_Msk                      (0x7UL << CAN_TSR_TME_Pos)         /*!< 0x1C000000 */
5651 #define CAN_TSR_TME                          CAN_TSR_TME_Msk                   /*!< TME[2:0] bits */
5652 #define CAN_TSR_TME0_Pos                     (26U)
5653 #define CAN_TSR_TME0_Msk                     (0x1UL << CAN_TSR_TME0_Pos)        /*!< 0x04000000 */
5654 #define CAN_TSR_TME0                         CAN_TSR_TME0_Msk                  /*!< Transmit Mailbox 0 Empty */
5655 #define CAN_TSR_TME1_Pos                     (27U)
5656 #define CAN_TSR_TME1_Msk                     (0x1UL << CAN_TSR_TME1_Pos)        /*!< 0x08000000 */
5657 #define CAN_TSR_TME1                         CAN_TSR_TME1_Msk                  /*!< Transmit Mailbox 1 Empty */
5658 #define CAN_TSR_TME2_Pos                     (28U)
5659 #define CAN_TSR_TME2_Msk                     (0x1UL << CAN_TSR_TME2_Pos)        /*!< 0x10000000 */
5660 #define CAN_TSR_TME2                         CAN_TSR_TME2_Msk                  /*!< Transmit Mailbox 2 Empty */
5661 
5662 #define CAN_TSR_LOW_Pos                      (29U)
5663 #define CAN_TSR_LOW_Msk                      (0x7UL << CAN_TSR_LOW_Pos)         /*!< 0xE0000000 */
5664 #define CAN_TSR_LOW                          CAN_TSR_LOW_Msk                   /*!< LOW[2:0] bits */
5665 #define CAN_TSR_LOW0_Pos                     (29U)
5666 #define CAN_TSR_LOW0_Msk                     (0x1UL << CAN_TSR_LOW0_Pos)        /*!< 0x20000000 */
5667 #define CAN_TSR_LOW0                         CAN_TSR_LOW0_Msk                  /*!< Lowest Priority Flag for Mailbox 0 */
5668 #define CAN_TSR_LOW1_Pos                     (30U)
5669 #define CAN_TSR_LOW1_Msk                     (0x1UL << CAN_TSR_LOW1_Pos)        /*!< 0x40000000 */
5670 #define CAN_TSR_LOW1                         CAN_TSR_LOW1_Msk                  /*!< Lowest Priority Flag for Mailbox 1 */
5671 #define CAN_TSR_LOW2_Pos                     (31U)
5672 #define CAN_TSR_LOW2_Msk                     (0x1UL << CAN_TSR_LOW2_Pos)        /*!< 0x80000000 */
5673 #define CAN_TSR_LOW2                         CAN_TSR_LOW2_Msk                  /*!< Lowest Priority Flag for Mailbox 2 */
5674 
5675 /*******************  Bit definition for CAN_RF0R register  *******************/
5676 #define CAN_RF0R_FMP0_Pos                    (0U)
5677 #define CAN_RF0R_FMP0_Msk                    (0x3UL << CAN_RF0R_FMP0_Pos)       /*!< 0x00000003 */
5678 #define CAN_RF0R_FMP0                        CAN_RF0R_FMP0_Msk                 /*!< FIFO 0 Message Pending */
5679 #define CAN_RF0R_FULL0_Pos                   (3U)
5680 #define CAN_RF0R_FULL0_Msk                   (0x1UL << CAN_RF0R_FULL0_Pos)      /*!< 0x00000008 */
5681 #define CAN_RF0R_FULL0                       CAN_RF0R_FULL0_Msk                /*!< FIFO 0 Full */
5682 #define CAN_RF0R_FOVR0_Pos                   (4U)
5683 #define CAN_RF0R_FOVR0_Msk                   (0x1UL << CAN_RF0R_FOVR0_Pos)      /*!< 0x00000010 */
5684 #define CAN_RF0R_FOVR0                       CAN_RF0R_FOVR0_Msk                /*!< FIFO 0 Overrun */
5685 #define CAN_RF0R_RFOM0_Pos                   (5U)
5686 #define CAN_RF0R_RFOM0_Msk                   (0x1UL << CAN_RF0R_RFOM0_Pos)      /*!< 0x00000020 */
5687 #define CAN_RF0R_RFOM0                       CAN_RF0R_RFOM0_Msk                /*!< Release FIFO 0 Output Mailbox */
5688 
5689 /*******************  Bit definition for CAN_RF1R register  *******************/
5690 #define CAN_RF1R_FMP1_Pos                    (0U)
5691 #define CAN_RF1R_FMP1_Msk                    (0x3UL << CAN_RF1R_FMP1_Pos)       /*!< 0x00000003 */
5692 #define CAN_RF1R_FMP1                        CAN_RF1R_FMP1_Msk                 /*!< FIFO 1 Message Pending */
5693 #define CAN_RF1R_FULL1_Pos                   (3U)
5694 #define CAN_RF1R_FULL1_Msk                   (0x1UL << CAN_RF1R_FULL1_Pos)      /*!< 0x00000008 */
5695 #define CAN_RF1R_FULL1                       CAN_RF1R_FULL1_Msk                /*!< FIFO 1 Full */
5696 #define CAN_RF1R_FOVR1_Pos                   (4U)
5697 #define CAN_RF1R_FOVR1_Msk                   (0x1UL << CAN_RF1R_FOVR1_Pos)      /*!< 0x00000010 */
5698 #define CAN_RF1R_FOVR1                       CAN_RF1R_FOVR1_Msk                /*!< FIFO 1 Overrun */
5699 #define CAN_RF1R_RFOM1_Pos                   (5U)
5700 #define CAN_RF1R_RFOM1_Msk                   (0x1UL << CAN_RF1R_RFOM1_Pos)      /*!< 0x00000020 */
5701 #define CAN_RF1R_RFOM1                       CAN_RF1R_RFOM1_Msk                /*!< Release FIFO 1 Output Mailbox */
5702 
5703 /********************  Bit definition for CAN_IER register  *******************/
5704 #define CAN_IER_TMEIE_Pos                    (0U)
5705 #define CAN_IER_TMEIE_Msk                    (0x1UL << CAN_IER_TMEIE_Pos)       /*!< 0x00000001 */
5706 #define CAN_IER_TMEIE                        CAN_IER_TMEIE_Msk                 /*!< Transmit Mailbox Empty Interrupt Enable */
5707 #define CAN_IER_FMPIE0_Pos                   (1U)
5708 #define CAN_IER_FMPIE0_Msk                   (0x1UL << CAN_IER_FMPIE0_Pos)      /*!< 0x00000002 */
5709 #define CAN_IER_FMPIE0                       CAN_IER_FMPIE0_Msk                /*!< FIFO Message Pending Interrupt Enable */
5710 #define CAN_IER_FFIE0_Pos                    (2U)
5711 #define CAN_IER_FFIE0_Msk                    (0x1UL << CAN_IER_FFIE0_Pos)       /*!< 0x00000004 */
5712 #define CAN_IER_FFIE0                        CAN_IER_FFIE0_Msk                 /*!< FIFO Full Interrupt Enable */
5713 #define CAN_IER_FOVIE0_Pos                   (3U)
5714 #define CAN_IER_FOVIE0_Msk                   (0x1UL << CAN_IER_FOVIE0_Pos)      /*!< 0x00000008 */
5715 #define CAN_IER_FOVIE0                       CAN_IER_FOVIE0_Msk                /*!< FIFO Overrun Interrupt Enable */
5716 #define CAN_IER_FMPIE1_Pos                   (4U)
5717 #define CAN_IER_FMPIE1_Msk                   (0x1UL << CAN_IER_FMPIE1_Pos)      /*!< 0x00000010 */
5718 #define CAN_IER_FMPIE1                       CAN_IER_FMPIE1_Msk                /*!< FIFO Message Pending Interrupt Enable */
5719 #define CAN_IER_FFIE1_Pos                    (5U)
5720 #define CAN_IER_FFIE1_Msk                    (0x1UL << CAN_IER_FFIE1_Pos)       /*!< 0x00000020 */
5721 #define CAN_IER_FFIE1                        CAN_IER_FFIE1_Msk                 /*!< FIFO Full Interrupt Enable */
5722 #define CAN_IER_FOVIE1_Pos                   (6U)
5723 #define CAN_IER_FOVIE1_Msk                   (0x1UL << CAN_IER_FOVIE1_Pos)      /*!< 0x00000040 */
5724 #define CAN_IER_FOVIE1                       CAN_IER_FOVIE1_Msk                /*!< FIFO Overrun Interrupt Enable */
5725 #define CAN_IER_EWGIE_Pos                    (8U)
5726 #define CAN_IER_EWGIE_Msk                    (0x1UL << CAN_IER_EWGIE_Pos)       /*!< 0x00000100 */
5727 #define CAN_IER_EWGIE                        CAN_IER_EWGIE_Msk                 /*!< Error Warning Interrupt Enable */
5728 #define CAN_IER_EPVIE_Pos                    (9U)
5729 #define CAN_IER_EPVIE_Msk                    (0x1UL << CAN_IER_EPVIE_Pos)       /*!< 0x00000200 */
5730 #define CAN_IER_EPVIE                        CAN_IER_EPVIE_Msk                 /*!< Error Passive Interrupt Enable */
5731 #define CAN_IER_BOFIE_Pos                    (10U)
5732 #define CAN_IER_BOFIE_Msk                    (0x1UL << CAN_IER_BOFIE_Pos)       /*!< 0x00000400 */
5733 #define CAN_IER_BOFIE                        CAN_IER_BOFIE_Msk                 /*!< Bus-Off Interrupt Enable */
5734 #define CAN_IER_LECIE_Pos                    (11U)
5735 #define CAN_IER_LECIE_Msk                    (0x1UL << CAN_IER_LECIE_Pos)       /*!< 0x00000800 */
5736 #define CAN_IER_LECIE                        CAN_IER_LECIE_Msk                 /*!< Last Error Code Interrupt Enable */
5737 #define CAN_IER_ERRIE_Pos                    (15U)
5738 #define CAN_IER_ERRIE_Msk                    (0x1UL << CAN_IER_ERRIE_Pos)       /*!< 0x00008000 */
5739 #define CAN_IER_ERRIE                        CAN_IER_ERRIE_Msk                 /*!< Error Interrupt Enable */
5740 #define CAN_IER_WKUIE_Pos                    (16U)
5741 #define CAN_IER_WKUIE_Msk                    (0x1UL << CAN_IER_WKUIE_Pos)       /*!< 0x00010000 */
5742 #define CAN_IER_WKUIE                        CAN_IER_WKUIE_Msk                 /*!< Wakeup Interrupt Enable */
5743 #define CAN_IER_SLKIE_Pos                    (17U)
5744 #define CAN_IER_SLKIE_Msk                    (0x1UL << CAN_IER_SLKIE_Pos)       /*!< 0x00020000 */
5745 #define CAN_IER_SLKIE                        CAN_IER_SLKIE_Msk                 /*!< Sleep Interrupt Enable */
5746 
5747 /********************  Bit definition for CAN_ESR register  *******************/
5748 #define CAN_ESR_EWGF_Pos                     (0U)
5749 #define CAN_ESR_EWGF_Msk                     (0x1UL << CAN_ESR_EWGF_Pos)        /*!< 0x00000001 */
5750 #define CAN_ESR_EWGF                         CAN_ESR_EWGF_Msk                  /*!< Error Warning Flag */
5751 #define CAN_ESR_EPVF_Pos                     (1U)
5752 #define CAN_ESR_EPVF_Msk                     (0x1UL << CAN_ESR_EPVF_Pos)        /*!< 0x00000002 */
5753 #define CAN_ESR_EPVF                         CAN_ESR_EPVF_Msk                  /*!< Error Passive Flag */
5754 #define CAN_ESR_BOFF_Pos                     (2U)
5755 #define CAN_ESR_BOFF_Msk                     (0x1UL << CAN_ESR_BOFF_Pos)        /*!< 0x00000004 */
5756 #define CAN_ESR_BOFF                         CAN_ESR_BOFF_Msk                  /*!< Bus-Off Flag */
5757 
5758 #define CAN_ESR_LEC_Pos                      (4U)
5759 #define CAN_ESR_LEC_Msk                      (0x7UL << CAN_ESR_LEC_Pos)         /*!< 0x00000070 */
5760 #define CAN_ESR_LEC                          CAN_ESR_LEC_Msk                   /*!< LEC[2:0] bits (Last Error Code) */
5761 #define CAN_ESR_LEC_0                        (0x1UL << CAN_ESR_LEC_Pos)         /*!< 0x00000010 */
5762 #define CAN_ESR_LEC_1                        (0x2UL << CAN_ESR_LEC_Pos)         /*!< 0x00000020 */
5763 #define CAN_ESR_LEC_2                        (0x4UL << CAN_ESR_LEC_Pos)         /*!< 0x00000040 */
5764 
5765 #define CAN_ESR_TEC_Pos                      (16U)
5766 #define CAN_ESR_TEC_Msk                      (0xFFUL << CAN_ESR_TEC_Pos)        /*!< 0x00FF0000 */
5767 #define CAN_ESR_TEC                          CAN_ESR_TEC_Msk                   /*!< Least significant byte of the 9-bit Transmit Error Counter */
5768 #define CAN_ESR_REC_Pos                      (24U)
5769 #define CAN_ESR_REC_Msk                      (0xFFUL << CAN_ESR_REC_Pos)        /*!< 0xFF000000 */
5770 #define CAN_ESR_REC                          CAN_ESR_REC_Msk                   /*!< Receive Error Counter */
5771 
5772 /*******************  Bit definition for CAN_BTR register  ********************/
5773 #define CAN_BTR_BRP_Pos                      (0U)
5774 #define CAN_BTR_BRP_Msk                      (0x3FFUL << CAN_BTR_BRP_Pos)       /*!< 0x000003FF */
5775 #define CAN_BTR_BRP                          CAN_BTR_BRP_Msk                   /*!<Baud Rate Prescaler */
5776 #define CAN_BTR_TS1_Pos                      (16U)
5777 #define CAN_BTR_TS1_Msk                      (0xFUL << CAN_BTR_TS1_Pos)         /*!< 0x000F0000 */
5778 #define CAN_BTR_TS1                          CAN_BTR_TS1_Msk                   /*!<Time Segment 1 */
5779 #define CAN_BTR_TS1_0                        (0x1UL << CAN_BTR_TS1_Pos)         /*!< 0x00010000 */
5780 #define CAN_BTR_TS1_1                        (0x2UL << CAN_BTR_TS1_Pos)         /*!< 0x00020000 */
5781 #define CAN_BTR_TS1_2                        (0x4UL << CAN_BTR_TS1_Pos)         /*!< 0x00040000 */
5782 #define CAN_BTR_TS1_3                        (0x8UL << CAN_BTR_TS1_Pos)         /*!< 0x00080000 */
5783 #define CAN_BTR_TS2_Pos                      (20U)
5784 #define CAN_BTR_TS2_Msk                      (0x7UL << CAN_BTR_TS2_Pos)         /*!< 0x00700000 */
5785 #define CAN_BTR_TS2                          CAN_BTR_TS2_Msk                   /*!<Time Segment 2 */
5786 #define CAN_BTR_TS2_0                        (0x1UL << CAN_BTR_TS2_Pos)         /*!< 0x00100000 */
5787 #define CAN_BTR_TS2_1                        (0x2UL << CAN_BTR_TS2_Pos)         /*!< 0x00200000 */
5788 #define CAN_BTR_TS2_2                        (0x4UL << CAN_BTR_TS2_Pos)         /*!< 0x00400000 */
5789 #define CAN_BTR_SJW_Pos                      (24U)
5790 #define CAN_BTR_SJW_Msk                      (0x3UL << CAN_BTR_SJW_Pos)         /*!< 0x03000000 */
5791 #define CAN_BTR_SJW                          CAN_BTR_SJW_Msk                   /*!<Resynchronization Jump Width */
5792 #define CAN_BTR_SJW_0                        (0x1UL << CAN_BTR_SJW_Pos)         /*!< 0x01000000 */
5793 #define CAN_BTR_SJW_1                        (0x2UL << CAN_BTR_SJW_Pos)         /*!< 0x02000000 */
5794 #define CAN_BTR_LBKM_Pos                     (30U)
5795 #define CAN_BTR_LBKM_Msk                     (0x1UL << CAN_BTR_LBKM_Pos)        /*!< 0x40000000 */
5796 #define CAN_BTR_LBKM                         CAN_BTR_LBKM_Msk                  /*!<Loop Back Mode (Debug) */
5797 #define CAN_BTR_SILM_Pos                     (31U)
5798 #define CAN_BTR_SILM_Msk                     (0x1UL << CAN_BTR_SILM_Pos)        /*!< 0x80000000 */
5799 #define CAN_BTR_SILM                         CAN_BTR_SILM_Msk                  /*!<Silent Mode */
5800 
5801 /*!< Mailbox registers */
5802 /******************  Bit definition for CAN_TI0R register  ********************/
5803 #define CAN_TI0R_TXRQ_Pos                    (0U)
5804 #define CAN_TI0R_TXRQ_Msk                    (0x1UL << CAN_TI0R_TXRQ_Pos)       /*!< 0x00000001 */
5805 #define CAN_TI0R_TXRQ                        CAN_TI0R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
5806 #define CAN_TI0R_RTR_Pos                     (1U)
5807 #define CAN_TI0R_RTR_Msk                     (0x1UL << CAN_TI0R_RTR_Pos)        /*!< 0x00000002 */
5808 #define CAN_TI0R_RTR                         CAN_TI0R_RTR_Msk                  /*!< Remote Transmission Request */
5809 #define CAN_TI0R_IDE_Pos                     (2U)
5810 #define CAN_TI0R_IDE_Msk                     (0x1UL << CAN_TI0R_IDE_Pos)        /*!< 0x00000004 */
5811 #define CAN_TI0R_IDE                         CAN_TI0R_IDE_Msk                  /*!< Identifier Extension */
5812 #define CAN_TI0R_EXID_Pos                    (3U)
5813 #define CAN_TI0R_EXID_Msk                    (0x3FFFFUL << CAN_TI0R_EXID_Pos)   /*!< 0x001FFFF8 */
5814 #define CAN_TI0R_EXID                        CAN_TI0R_EXID_Msk                 /*!< Extended Identifier */
5815 #define CAN_TI0R_STID_Pos                    (21U)
5816 #define CAN_TI0R_STID_Msk                    (0x7FFUL << CAN_TI0R_STID_Pos)     /*!< 0xFFE00000 */
5817 #define CAN_TI0R_STID                        CAN_TI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
5818 
5819 /******************  Bit definition for CAN_TDT0R register  *******************/
5820 #define CAN_TDT0R_DLC_Pos                    (0U)
5821 #define CAN_TDT0R_DLC_Msk                    (0xFUL << CAN_TDT0R_DLC_Pos)       /*!< 0x0000000F */
5822 #define CAN_TDT0R_DLC                        CAN_TDT0R_DLC_Msk                 /*!< Data Length Code */
5823 #define CAN_TDT0R_TGT_Pos                    (8U)
5824 #define CAN_TDT0R_TGT_Msk                    (0x1UL << CAN_TDT0R_TGT_Pos)       /*!< 0x00000100 */
5825 #define CAN_TDT0R_TGT                        CAN_TDT0R_TGT_Msk                 /*!< Transmit Global Time */
5826 #define CAN_TDT0R_TIME_Pos                   (16U)
5827 #define CAN_TDT0R_TIME_Msk                   (0xFFFFUL << CAN_TDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
5828 #define CAN_TDT0R_TIME                       CAN_TDT0R_TIME_Msk                /*!< Message Time Stamp */
5829 
5830 /******************  Bit definition for CAN_TDL0R register  *******************/
5831 #define CAN_TDL0R_DATA0_Pos                  (0U)
5832 #define CAN_TDL0R_DATA0_Msk                  (0xFFUL << CAN_TDL0R_DATA0_Pos)    /*!< 0x000000FF */
5833 #define CAN_TDL0R_DATA0                      CAN_TDL0R_DATA0_Msk               /*!< Data byte 0 */
5834 #define CAN_TDL0R_DATA1_Pos                  (8U)
5835 #define CAN_TDL0R_DATA1_Msk                  (0xFFUL << CAN_TDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
5836 #define CAN_TDL0R_DATA1                      CAN_TDL0R_DATA1_Msk               /*!< Data byte 1 */
5837 #define CAN_TDL0R_DATA2_Pos                  (16U)
5838 #define CAN_TDL0R_DATA2_Msk                  (0xFFUL << CAN_TDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
5839 #define CAN_TDL0R_DATA2                      CAN_TDL0R_DATA2_Msk               /*!< Data byte 2 */
5840 #define CAN_TDL0R_DATA3_Pos                  (24U)
5841 #define CAN_TDL0R_DATA3_Msk                  (0xFFUL << CAN_TDL0R_DATA3_Pos)    /*!< 0xFF000000 */
5842 #define CAN_TDL0R_DATA3                      CAN_TDL0R_DATA3_Msk               /*!< Data byte 3 */
5843 
5844 /******************  Bit definition for CAN_TDH0R register  *******************/
5845 #define CAN_TDH0R_DATA4_Pos                  (0U)
5846 #define CAN_TDH0R_DATA4_Msk                  (0xFFUL << CAN_TDH0R_DATA4_Pos)    /*!< 0x000000FF */
5847 #define CAN_TDH0R_DATA4                      CAN_TDH0R_DATA4_Msk               /*!< Data byte 4 */
5848 #define CAN_TDH0R_DATA5_Pos                  (8U)
5849 #define CAN_TDH0R_DATA5_Msk                  (0xFFUL << CAN_TDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
5850 #define CAN_TDH0R_DATA5                      CAN_TDH0R_DATA5_Msk               /*!< Data byte 5 */
5851 #define CAN_TDH0R_DATA6_Pos                  (16U)
5852 #define CAN_TDH0R_DATA6_Msk                  (0xFFUL << CAN_TDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
5853 #define CAN_TDH0R_DATA6                      CAN_TDH0R_DATA6_Msk               /*!< Data byte 6 */
5854 #define CAN_TDH0R_DATA7_Pos                  (24U)
5855 #define CAN_TDH0R_DATA7_Msk                  (0xFFUL << CAN_TDH0R_DATA7_Pos)    /*!< 0xFF000000 */
5856 #define CAN_TDH0R_DATA7                      CAN_TDH0R_DATA7_Msk               /*!< Data byte 7 */
5857 
5858 /*******************  Bit definition for CAN_TI1R register  *******************/
5859 #define CAN_TI1R_TXRQ_Pos                    (0U)
5860 #define CAN_TI1R_TXRQ_Msk                    (0x1UL << CAN_TI1R_TXRQ_Pos)       /*!< 0x00000001 */
5861 #define CAN_TI1R_TXRQ                        CAN_TI1R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
5862 #define CAN_TI1R_RTR_Pos                     (1U)
5863 #define CAN_TI1R_RTR_Msk                     (0x1UL << CAN_TI1R_RTR_Pos)        /*!< 0x00000002 */
5864 #define CAN_TI1R_RTR                         CAN_TI1R_RTR_Msk                  /*!< Remote Transmission Request */
5865 #define CAN_TI1R_IDE_Pos                     (2U)
5866 #define CAN_TI1R_IDE_Msk                     (0x1UL << CAN_TI1R_IDE_Pos)        /*!< 0x00000004 */
5867 #define CAN_TI1R_IDE                         CAN_TI1R_IDE_Msk                  /*!< Identifier Extension */
5868 #define CAN_TI1R_EXID_Pos                    (3U)
5869 #define CAN_TI1R_EXID_Msk                    (0x3FFFFUL << CAN_TI1R_EXID_Pos)   /*!< 0x001FFFF8 */
5870 #define CAN_TI1R_EXID                        CAN_TI1R_EXID_Msk                 /*!< Extended Identifier */
5871 #define CAN_TI1R_STID_Pos                    (21U)
5872 #define CAN_TI1R_STID_Msk                    (0x7FFUL << CAN_TI1R_STID_Pos)     /*!< 0xFFE00000 */
5873 #define CAN_TI1R_STID                        CAN_TI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
5874 
5875 /*******************  Bit definition for CAN_TDT1R register  ******************/
5876 #define CAN_TDT1R_DLC_Pos                    (0U)
5877 #define CAN_TDT1R_DLC_Msk                    (0xFUL << CAN_TDT1R_DLC_Pos)       /*!< 0x0000000F */
5878 #define CAN_TDT1R_DLC                        CAN_TDT1R_DLC_Msk                 /*!< Data Length Code */
5879 #define CAN_TDT1R_TGT_Pos                    (8U)
5880 #define CAN_TDT1R_TGT_Msk                    (0x1UL << CAN_TDT1R_TGT_Pos)       /*!< 0x00000100 */
5881 #define CAN_TDT1R_TGT                        CAN_TDT1R_TGT_Msk                 /*!< Transmit Global Time */
5882 #define CAN_TDT1R_TIME_Pos                   (16U)
5883 #define CAN_TDT1R_TIME_Msk                   (0xFFFFUL << CAN_TDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
5884 #define CAN_TDT1R_TIME                       CAN_TDT1R_TIME_Msk                /*!< Message Time Stamp */
5885 
5886 /*******************  Bit definition for CAN_TDL1R register  ******************/
5887 #define CAN_TDL1R_DATA0_Pos                  (0U)
5888 #define CAN_TDL1R_DATA0_Msk                  (0xFFUL << CAN_TDL1R_DATA0_Pos)    /*!< 0x000000FF */
5889 #define CAN_TDL1R_DATA0                      CAN_TDL1R_DATA0_Msk               /*!< Data byte 0 */
5890 #define CAN_TDL1R_DATA1_Pos                  (8U)
5891 #define CAN_TDL1R_DATA1_Msk                  (0xFFUL << CAN_TDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
5892 #define CAN_TDL1R_DATA1                      CAN_TDL1R_DATA1_Msk               /*!< Data byte 1 */
5893 #define CAN_TDL1R_DATA2_Pos                  (16U)
5894 #define CAN_TDL1R_DATA2_Msk                  (0xFFUL << CAN_TDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
5895 #define CAN_TDL1R_DATA2                      CAN_TDL1R_DATA2_Msk               /*!< Data byte 2 */
5896 #define CAN_TDL1R_DATA3_Pos                  (24U)
5897 #define CAN_TDL1R_DATA3_Msk                  (0xFFUL << CAN_TDL1R_DATA3_Pos)    /*!< 0xFF000000 */
5898 #define CAN_TDL1R_DATA3                      CAN_TDL1R_DATA3_Msk               /*!< Data byte 3 */
5899 
5900 /*******************  Bit definition for CAN_TDH1R register  ******************/
5901 #define CAN_TDH1R_DATA4_Pos                  (0U)
5902 #define CAN_TDH1R_DATA4_Msk                  (0xFFUL << CAN_TDH1R_DATA4_Pos)    /*!< 0x000000FF */
5903 #define CAN_TDH1R_DATA4                      CAN_TDH1R_DATA4_Msk               /*!< Data byte 4 */
5904 #define CAN_TDH1R_DATA5_Pos                  (8U)
5905 #define CAN_TDH1R_DATA5_Msk                  (0xFFUL << CAN_TDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
5906 #define CAN_TDH1R_DATA5                      CAN_TDH1R_DATA5_Msk               /*!< Data byte 5 */
5907 #define CAN_TDH1R_DATA6_Pos                  (16U)
5908 #define CAN_TDH1R_DATA6_Msk                  (0xFFUL << CAN_TDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
5909 #define CAN_TDH1R_DATA6                      CAN_TDH1R_DATA6_Msk               /*!< Data byte 6 */
5910 #define CAN_TDH1R_DATA7_Pos                  (24U)
5911 #define CAN_TDH1R_DATA7_Msk                  (0xFFUL << CAN_TDH1R_DATA7_Pos)    /*!< 0xFF000000 */
5912 #define CAN_TDH1R_DATA7                      CAN_TDH1R_DATA7_Msk               /*!< Data byte 7 */
5913 
5914 /*******************  Bit definition for CAN_TI2R register  *******************/
5915 #define CAN_TI2R_TXRQ_Pos                    (0U)
5916 #define CAN_TI2R_TXRQ_Msk                    (0x1UL << CAN_TI2R_TXRQ_Pos)       /*!< 0x00000001 */
5917 #define CAN_TI2R_TXRQ                        CAN_TI2R_TXRQ_Msk                 /*!< Transmit Mailbox Request */
5918 #define CAN_TI2R_RTR_Pos                     (1U)
5919 #define CAN_TI2R_RTR_Msk                     (0x1UL << CAN_TI2R_RTR_Pos)        /*!< 0x00000002 */
5920 #define CAN_TI2R_RTR                         CAN_TI2R_RTR_Msk                  /*!< Remote Transmission Request */
5921 #define CAN_TI2R_IDE_Pos                     (2U)
5922 #define CAN_TI2R_IDE_Msk                     (0x1UL << CAN_TI2R_IDE_Pos)        /*!< 0x00000004 */
5923 #define CAN_TI2R_IDE                         CAN_TI2R_IDE_Msk                  /*!< Identifier Extension */
5924 #define CAN_TI2R_EXID_Pos                    (3U)
5925 #define CAN_TI2R_EXID_Msk                    (0x3FFFFUL << CAN_TI2R_EXID_Pos)   /*!< 0x001FFFF8 */
5926 #define CAN_TI2R_EXID                        CAN_TI2R_EXID_Msk                 /*!< Extended identifier */
5927 #define CAN_TI2R_STID_Pos                    (21U)
5928 #define CAN_TI2R_STID_Msk                    (0x7FFUL << CAN_TI2R_STID_Pos)     /*!< 0xFFE00000 */
5929 #define CAN_TI2R_STID                        CAN_TI2R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
5930 
5931 /*******************  Bit definition for CAN_TDT2R register  ******************/
5932 #define CAN_TDT2R_DLC_Pos                    (0U)
5933 #define CAN_TDT2R_DLC_Msk                    (0xFUL << CAN_TDT2R_DLC_Pos)       /*!< 0x0000000F */
5934 #define CAN_TDT2R_DLC                        CAN_TDT2R_DLC_Msk                 /*!< Data Length Code */
5935 #define CAN_TDT2R_TGT_Pos                    (8U)
5936 #define CAN_TDT2R_TGT_Msk                    (0x1UL << CAN_TDT2R_TGT_Pos)       /*!< 0x00000100 */
5937 #define CAN_TDT2R_TGT                        CAN_TDT2R_TGT_Msk                 /*!< Transmit Global Time */
5938 #define CAN_TDT2R_TIME_Pos                   (16U)
5939 #define CAN_TDT2R_TIME_Msk                   (0xFFFFUL << CAN_TDT2R_TIME_Pos)   /*!< 0xFFFF0000 */
5940 #define CAN_TDT2R_TIME                       CAN_TDT2R_TIME_Msk                /*!< Message Time Stamp */
5941 
5942 /*******************  Bit definition for CAN_TDL2R register  ******************/
5943 #define CAN_TDL2R_DATA0_Pos                  (0U)
5944 #define CAN_TDL2R_DATA0_Msk                  (0xFFUL << CAN_TDL2R_DATA0_Pos)    /*!< 0x000000FF */
5945 #define CAN_TDL2R_DATA0                      CAN_TDL2R_DATA0_Msk               /*!< Data byte 0 */
5946 #define CAN_TDL2R_DATA1_Pos                  (8U)
5947 #define CAN_TDL2R_DATA1_Msk                  (0xFFUL << CAN_TDL2R_DATA1_Pos)    /*!< 0x0000FF00 */
5948 #define CAN_TDL2R_DATA1                      CAN_TDL2R_DATA1_Msk               /*!< Data byte 1 */
5949 #define CAN_TDL2R_DATA2_Pos                  (16U)
5950 #define CAN_TDL2R_DATA2_Msk                  (0xFFUL << CAN_TDL2R_DATA2_Pos)    /*!< 0x00FF0000 */
5951 #define CAN_TDL2R_DATA2                      CAN_TDL2R_DATA2_Msk               /*!< Data byte 2 */
5952 #define CAN_TDL2R_DATA3_Pos                  (24U)
5953 #define CAN_TDL2R_DATA3_Msk                  (0xFFUL << CAN_TDL2R_DATA3_Pos)    /*!< 0xFF000000 */
5954 #define CAN_TDL2R_DATA3                      CAN_TDL2R_DATA3_Msk               /*!< Data byte 3 */
5955 
5956 /*******************  Bit definition for CAN_TDH2R register  ******************/
5957 #define CAN_TDH2R_DATA4_Pos                  (0U)
5958 #define CAN_TDH2R_DATA4_Msk                  (0xFFUL << CAN_TDH2R_DATA4_Pos)    /*!< 0x000000FF */
5959 #define CAN_TDH2R_DATA4                      CAN_TDH2R_DATA4_Msk               /*!< Data byte 4 */
5960 #define CAN_TDH2R_DATA5_Pos                  (8U)
5961 #define CAN_TDH2R_DATA5_Msk                  (0xFFUL << CAN_TDH2R_DATA5_Pos)    /*!< 0x0000FF00 */
5962 #define CAN_TDH2R_DATA5                      CAN_TDH2R_DATA5_Msk               /*!< Data byte 5 */
5963 #define CAN_TDH2R_DATA6_Pos                  (16U)
5964 #define CAN_TDH2R_DATA6_Msk                  (0xFFUL << CAN_TDH2R_DATA6_Pos)    /*!< 0x00FF0000 */
5965 #define CAN_TDH2R_DATA6                      CAN_TDH2R_DATA6_Msk               /*!< Data byte 6 */
5966 #define CAN_TDH2R_DATA7_Pos                  (24U)
5967 #define CAN_TDH2R_DATA7_Msk                  (0xFFUL << CAN_TDH2R_DATA7_Pos)    /*!< 0xFF000000 */
5968 #define CAN_TDH2R_DATA7                      CAN_TDH2R_DATA7_Msk               /*!< Data byte 7 */
5969 
5970 /*******************  Bit definition for CAN_RI0R register  *******************/
5971 #define CAN_RI0R_RTR_Pos                     (1U)
5972 #define CAN_RI0R_RTR_Msk                     (0x1UL << CAN_RI0R_RTR_Pos)        /*!< 0x00000002 */
5973 #define CAN_RI0R_RTR                         CAN_RI0R_RTR_Msk                  /*!< Remote Transmission Request */
5974 #define CAN_RI0R_IDE_Pos                     (2U)
5975 #define CAN_RI0R_IDE_Msk                     (0x1UL << CAN_RI0R_IDE_Pos)        /*!< 0x00000004 */
5976 #define CAN_RI0R_IDE                         CAN_RI0R_IDE_Msk                  /*!< Identifier Extension */
5977 #define CAN_RI0R_EXID_Pos                    (3U)
5978 #define CAN_RI0R_EXID_Msk                    (0x3FFFFUL << CAN_RI0R_EXID_Pos)   /*!< 0x001FFFF8 */
5979 #define CAN_RI0R_EXID                        CAN_RI0R_EXID_Msk                 /*!< Extended Identifier */
5980 #define CAN_RI0R_STID_Pos                    (21U)
5981 #define CAN_RI0R_STID_Msk                    (0x7FFUL << CAN_RI0R_STID_Pos)     /*!< 0xFFE00000 */
5982 #define CAN_RI0R_STID                        CAN_RI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
5983 
5984 /*******************  Bit definition for CAN_RDT0R register  ******************/
5985 #define CAN_RDT0R_DLC_Pos                    (0U)
5986 #define CAN_RDT0R_DLC_Msk                    (0xFUL << CAN_RDT0R_DLC_Pos)       /*!< 0x0000000F */
5987 #define CAN_RDT0R_DLC                        CAN_RDT0R_DLC_Msk                 /*!< Data Length Code */
5988 #define CAN_RDT0R_FMI_Pos                    (8U)
5989 #define CAN_RDT0R_FMI_Msk                    (0xFFUL << CAN_RDT0R_FMI_Pos)      /*!< 0x0000FF00 */
5990 #define CAN_RDT0R_FMI                        CAN_RDT0R_FMI_Msk                 /*!< Filter Match Index */
5991 #define CAN_RDT0R_TIME_Pos                   (16U)
5992 #define CAN_RDT0R_TIME_Msk                   (0xFFFFUL << CAN_RDT0R_TIME_Pos)   /*!< 0xFFFF0000 */
5993 #define CAN_RDT0R_TIME                       CAN_RDT0R_TIME_Msk                /*!< Message Time Stamp */
5994 
5995 /*******************  Bit definition for CAN_RDL0R register  ******************/
5996 #define CAN_RDL0R_DATA0_Pos                  (0U)
5997 #define CAN_RDL0R_DATA0_Msk                  (0xFFUL << CAN_RDL0R_DATA0_Pos)    /*!< 0x000000FF */
5998 #define CAN_RDL0R_DATA0                      CAN_RDL0R_DATA0_Msk               /*!< Data byte 0 */
5999 #define CAN_RDL0R_DATA1_Pos                  (8U)
6000 #define CAN_RDL0R_DATA1_Msk                  (0xFFUL << CAN_RDL0R_DATA1_Pos)    /*!< 0x0000FF00 */
6001 #define CAN_RDL0R_DATA1                      CAN_RDL0R_DATA1_Msk               /*!< Data byte 1 */
6002 #define CAN_RDL0R_DATA2_Pos                  (16U)
6003 #define CAN_RDL0R_DATA2_Msk                  (0xFFUL << CAN_RDL0R_DATA2_Pos)    /*!< 0x00FF0000 */
6004 #define CAN_RDL0R_DATA2                      CAN_RDL0R_DATA2_Msk               /*!< Data byte 2 */
6005 #define CAN_RDL0R_DATA3_Pos                  (24U)
6006 #define CAN_RDL0R_DATA3_Msk                  (0xFFUL << CAN_RDL0R_DATA3_Pos)    /*!< 0xFF000000 */
6007 #define CAN_RDL0R_DATA3                      CAN_RDL0R_DATA3_Msk               /*!< Data byte 3 */
6008 
6009 /*******************  Bit definition for CAN_RDH0R register  ******************/
6010 #define CAN_RDH0R_DATA4_Pos                  (0U)
6011 #define CAN_RDH0R_DATA4_Msk                  (0xFFUL << CAN_RDH0R_DATA4_Pos)    /*!< 0x000000FF */
6012 #define CAN_RDH0R_DATA4                      CAN_RDH0R_DATA4_Msk               /*!< Data byte 4 */
6013 #define CAN_RDH0R_DATA5_Pos                  (8U)
6014 #define CAN_RDH0R_DATA5_Msk                  (0xFFUL << CAN_RDH0R_DATA5_Pos)    /*!< 0x0000FF00 */
6015 #define CAN_RDH0R_DATA5                      CAN_RDH0R_DATA5_Msk               /*!< Data byte 5 */
6016 #define CAN_RDH0R_DATA6_Pos                  (16U)
6017 #define CAN_RDH0R_DATA6_Msk                  (0xFFUL << CAN_RDH0R_DATA6_Pos)    /*!< 0x00FF0000 */
6018 #define CAN_RDH0R_DATA6                      CAN_RDH0R_DATA6_Msk               /*!< Data byte 6 */
6019 #define CAN_RDH0R_DATA7_Pos                  (24U)
6020 #define CAN_RDH0R_DATA7_Msk                  (0xFFUL << CAN_RDH0R_DATA7_Pos)    /*!< 0xFF000000 */
6021 #define CAN_RDH0R_DATA7                      CAN_RDH0R_DATA7_Msk               /*!< Data byte 7 */
6022 
6023 /*******************  Bit definition for CAN_RI1R register  *******************/
6024 #define CAN_RI1R_RTR_Pos                     (1U)
6025 #define CAN_RI1R_RTR_Msk                     (0x1UL << CAN_RI1R_RTR_Pos)        /*!< 0x00000002 */
6026 #define CAN_RI1R_RTR                         CAN_RI1R_RTR_Msk                  /*!< Remote Transmission Request */
6027 #define CAN_RI1R_IDE_Pos                     (2U)
6028 #define CAN_RI1R_IDE_Msk                     (0x1UL << CAN_RI1R_IDE_Pos)        /*!< 0x00000004 */
6029 #define CAN_RI1R_IDE                         CAN_RI1R_IDE_Msk                  /*!< Identifier Extension */
6030 #define CAN_RI1R_EXID_Pos                    (3U)
6031 #define CAN_RI1R_EXID_Msk                    (0x3FFFFUL << CAN_RI1R_EXID_Pos)   /*!< 0x001FFFF8 */
6032 #define CAN_RI1R_EXID                        CAN_RI1R_EXID_Msk                 /*!< Extended identifier */
6033 #define CAN_RI1R_STID_Pos                    (21U)
6034 #define CAN_RI1R_STID_Msk                    (0x7FFUL << CAN_RI1R_STID_Pos)     /*!< 0xFFE00000 */
6035 #define CAN_RI1R_STID                        CAN_RI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */
6036 
6037 /*******************  Bit definition for CAN_RDT1R register  ******************/
6038 #define CAN_RDT1R_DLC_Pos                    (0U)
6039 #define CAN_RDT1R_DLC_Msk                    (0xFUL << CAN_RDT1R_DLC_Pos)       /*!< 0x0000000F */
6040 #define CAN_RDT1R_DLC                        CAN_RDT1R_DLC_Msk                 /*!< Data Length Code */
6041 #define CAN_RDT1R_FMI_Pos                    (8U)
6042 #define CAN_RDT1R_FMI_Msk                    (0xFFUL << CAN_RDT1R_FMI_Pos)      /*!< 0x0000FF00 */
6043 #define CAN_RDT1R_FMI                        CAN_RDT1R_FMI_Msk                 /*!< Filter Match Index */
6044 #define CAN_RDT1R_TIME_Pos                   (16U)
6045 #define CAN_RDT1R_TIME_Msk                   (0xFFFFUL << CAN_RDT1R_TIME_Pos)   /*!< 0xFFFF0000 */
6046 #define CAN_RDT1R_TIME                       CAN_RDT1R_TIME_Msk                /*!< Message Time Stamp */
6047 
6048 /*******************  Bit definition for CAN_RDL1R register  ******************/
6049 #define CAN_RDL1R_DATA0_Pos                  (0U)
6050 #define CAN_RDL1R_DATA0_Msk                  (0xFFUL << CAN_RDL1R_DATA0_Pos)    /*!< 0x000000FF */
6051 #define CAN_RDL1R_DATA0                      CAN_RDL1R_DATA0_Msk               /*!< Data byte 0 */
6052 #define CAN_RDL1R_DATA1_Pos                  (8U)
6053 #define CAN_RDL1R_DATA1_Msk                  (0xFFUL << CAN_RDL1R_DATA1_Pos)    /*!< 0x0000FF00 */
6054 #define CAN_RDL1R_DATA1                      CAN_RDL1R_DATA1_Msk               /*!< Data byte 1 */
6055 #define CAN_RDL1R_DATA2_Pos                  (16U)
6056 #define CAN_RDL1R_DATA2_Msk                  (0xFFUL << CAN_RDL1R_DATA2_Pos)    /*!< 0x00FF0000 */
6057 #define CAN_RDL1R_DATA2                      CAN_RDL1R_DATA2_Msk               /*!< Data byte 2 */
6058 #define CAN_RDL1R_DATA3_Pos                  (24U)
6059 #define CAN_RDL1R_DATA3_Msk                  (0xFFUL << CAN_RDL1R_DATA3_Pos)    /*!< 0xFF000000 */
6060 #define CAN_RDL1R_DATA3                      CAN_RDL1R_DATA3_Msk               /*!< Data byte 3 */
6061 
6062 /*******************  Bit definition for CAN_RDH1R register  ******************/
6063 #define CAN_RDH1R_DATA4_Pos                  (0U)
6064 #define CAN_RDH1R_DATA4_Msk                  (0xFFUL << CAN_RDH1R_DATA4_Pos)    /*!< 0x000000FF */
6065 #define CAN_RDH1R_DATA4                      CAN_RDH1R_DATA4_Msk               /*!< Data byte 4 */
6066 #define CAN_RDH1R_DATA5_Pos                  (8U)
6067 #define CAN_RDH1R_DATA5_Msk                  (0xFFUL << CAN_RDH1R_DATA5_Pos)    /*!< 0x0000FF00 */
6068 #define CAN_RDH1R_DATA5                      CAN_RDH1R_DATA5_Msk               /*!< Data byte 5 */
6069 #define CAN_RDH1R_DATA6_Pos                  (16U)
6070 #define CAN_RDH1R_DATA6_Msk                  (0xFFUL << CAN_RDH1R_DATA6_Pos)    /*!< 0x00FF0000 */
6071 #define CAN_RDH1R_DATA6                      CAN_RDH1R_DATA6_Msk               /*!< Data byte 6 */
6072 #define CAN_RDH1R_DATA7_Pos                  (24U)
6073 #define CAN_RDH1R_DATA7_Msk                  (0xFFUL << CAN_RDH1R_DATA7_Pos)    /*!< 0xFF000000 */
6074 #define CAN_RDH1R_DATA7                      CAN_RDH1R_DATA7_Msk               /*!< Data byte 7 */
6075 
6076 /*!< CAN filter registers */
6077 /*******************  Bit definition for CAN_FMR register  ********************/
6078 #define CAN_FMR_FINIT_Pos                    (0U)
6079 #define CAN_FMR_FINIT_Msk                    (0x1UL << CAN_FMR_FINIT_Pos)       /*!< 0x00000001 */
6080 #define CAN_FMR_FINIT                        CAN_FMR_FINIT_Msk                 /*!< Filter Init Mode */
6081 #define CAN_FMR_CAN2SB_Pos                   (8U)
6082 #define CAN_FMR_CAN2SB_Msk                   (0x3FUL << CAN_FMR_CAN2SB_Pos)     /*!< 0x00003F00 */
6083 #define CAN_FMR_CAN2SB                       CAN_FMR_CAN2SB_Msk                /*!< CAN2 start bank */
6084 
6085 /*******************  Bit definition for CAN_FM1R register  *******************/
6086 #define CAN_FM1R_FBM_Pos                     (0U)
6087 #define CAN_FM1R_FBM_Msk                     (0x3FFFUL << CAN_FM1R_FBM_Pos)     /*!< 0x00003FFF */
6088 #define CAN_FM1R_FBM                         CAN_FM1R_FBM_Msk                  /*!< Filter Mode */
6089 #define CAN_FM1R_FBM0_Pos                    (0U)
6090 #define CAN_FM1R_FBM0_Msk                    (0x1UL << CAN_FM1R_FBM0_Pos)       /*!< 0x00000001 */
6091 #define CAN_FM1R_FBM0                        CAN_FM1R_FBM0_Msk                 /*!< Filter Init Mode for filter 0 */
6092 #define CAN_FM1R_FBM1_Pos                    (1U)
6093 #define CAN_FM1R_FBM1_Msk                    (0x1UL << CAN_FM1R_FBM1_Pos)       /*!< 0x00000002 */
6094 #define CAN_FM1R_FBM1                        CAN_FM1R_FBM1_Msk                 /*!< Filter Init Mode for filter 1 */
6095 #define CAN_FM1R_FBM2_Pos                    (2U)
6096 #define CAN_FM1R_FBM2_Msk                    (0x1UL << CAN_FM1R_FBM2_Pos)       /*!< 0x00000004 */
6097 #define CAN_FM1R_FBM2                        CAN_FM1R_FBM2_Msk                 /*!< Filter Init Mode for filter 2 */
6098 #define CAN_FM1R_FBM3_Pos                    (3U)
6099 #define CAN_FM1R_FBM3_Msk                    (0x1UL << CAN_FM1R_FBM3_Pos)       /*!< 0x00000008 */
6100 #define CAN_FM1R_FBM3                        CAN_FM1R_FBM3_Msk                 /*!< Filter Init Mode for filter 3 */
6101 #define CAN_FM1R_FBM4_Pos                    (4U)
6102 #define CAN_FM1R_FBM4_Msk                    (0x1UL << CAN_FM1R_FBM4_Pos)       /*!< 0x00000010 */
6103 #define CAN_FM1R_FBM4                        CAN_FM1R_FBM4_Msk                 /*!< Filter Init Mode for filter 4 */
6104 #define CAN_FM1R_FBM5_Pos                    (5U)
6105 #define CAN_FM1R_FBM5_Msk                    (0x1UL << CAN_FM1R_FBM5_Pos)       /*!< 0x00000020 */
6106 #define CAN_FM1R_FBM5                        CAN_FM1R_FBM5_Msk                 /*!< Filter Init Mode for filter 5 */
6107 #define CAN_FM1R_FBM6_Pos                    (6U)
6108 #define CAN_FM1R_FBM6_Msk                    (0x1UL << CAN_FM1R_FBM6_Pos)       /*!< 0x00000040 */
6109 #define CAN_FM1R_FBM6                        CAN_FM1R_FBM6_Msk                 /*!< Filter Init Mode for filter 6 */
6110 #define CAN_FM1R_FBM7_Pos                    (7U)
6111 #define CAN_FM1R_FBM7_Msk                    (0x1UL << CAN_FM1R_FBM7_Pos)       /*!< 0x00000080 */
6112 #define CAN_FM1R_FBM7                        CAN_FM1R_FBM7_Msk                 /*!< Filter Init Mode for filter 7 */
6113 #define CAN_FM1R_FBM8_Pos                    (8U)
6114 #define CAN_FM1R_FBM8_Msk                    (0x1UL << CAN_FM1R_FBM8_Pos)       /*!< 0x00000100 */
6115 #define CAN_FM1R_FBM8                        CAN_FM1R_FBM8_Msk                 /*!< Filter Init Mode for filter 8 */
6116 #define CAN_FM1R_FBM9_Pos                    (9U)
6117 #define CAN_FM1R_FBM9_Msk                    (0x1UL << CAN_FM1R_FBM9_Pos)       /*!< 0x00000200 */
6118 #define CAN_FM1R_FBM9                        CAN_FM1R_FBM9_Msk                 /*!< Filter Init Mode for filter 9 */
6119 #define CAN_FM1R_FBM10_Pos                   (10U)
6120 #define CAN_FM1R_FBM10_Msk                   (0x1UL << CAN_FM1R_FBM10_Pos)      /*!< 0x00000400 */
6121 #define CAN_FM1R_FBM10                       CAN_FM1R_FBM10_Msk                /*!< Filter Init Mode for filter 10 */
6122 #define CAN_FM1R_FBM11_Pos                   (11U)
6123 #define CAN_FM1R_FBM11_Msk                   (0x1UL << CAN_FM1R_FBM11_Pos)      /*!< 0x00000800 */
6124 #define CAN_FM1R_FBM11                       CAN_FM1R_FBM11_Msk                /*!< Filter Init Mode for filter 11 */
6125 #define CAN_FM1R_FBM12_Pos                   (12U)
6126 #define CAN_FM1R_FBM12_Msk                   (0x1UL << CAN_FM1R_FBM12_Pos)      /*!< 0x00001000 */
6127 #define CAN_FM1R_FBM12                       CAN_FM1R_FBM12_Msk                /*!< Filter Init Mode for filter 12 */
6128 #define CAN_FM1R_FBM13_Pos                   (13U)
6129 #define CAN_FM1R_FBM13_Msk                   (0x1UL << CAN_FM1R_FBM13_Pos)      /*!< 0x00002000 */
6130 #define CAN_FM1R_FBM13                       CAN_FM1R_FBM13_Msk                /*!< Filter Init Mode for filter 13 */
6131 
6132 /*******************  Bit definition for CAN_FS1R register  *******************/
6133 #define CAN_FS1R_FSC_Pos                     (0U)
6134 #define CAN_FS1R_FSC_Msk                     (0x3FFFUL << CAN_FS1R_FSC_Pos)     /*!< 0x00003FFF */
6135 #define CAN_FS1R_FSC                         CAN_FS1R_FSC_Msk                  /*!< Filter Scale Configuration */
6136 #define CAN_FS1R_FSC0_Pos                    (0U)
6137 #define CAN_FS1R_FSC0_Msk                    (0x1UL << CAN_FS1R_FSC0_Pos)       /*!< 0x00000001 */
6138 #define CAN_FS1R_FSC0                        CAN_FS1R_FSC0_Msk                 /*!< Filter Scale Configuration for filter 0 */
6139 #define CAN_FS1R_FSC1_Pos                    (1U)
6140 #define CAN_FS1R_FSC1_Msk                    (0x1UL << CAN_FS1R_FSC1_Pos)       /*!< 0x00000002 */
6141 #define CAN_FS1R_FSC1                        CAN_FS1R_FSC1_Msk                 /*!< Filter Scale Configuration for filter 1 */
6142 #define CAN_FS1R_FSC2_Pos                    (2U)
6143 #define CAN_FS1R_FSC2_Msk                    (0x1UL << CAN_FS1R_FSC2_Pos)       /*!< 0x00000004 */
6144 #define CAN_FS1R_FSC2                        CAN_FS1R_FSC2_Msk                 /*!< Filter Scale Configuration for filter 2 */
6145 #define CAN_FS1R_FSC3_Pos                    (3U)
6146 #define CAN_FS1R_FSC3_Msk                    (0x1UL << CAN_FS1R_FSC3_Pos)       /*!< 0x00000008 */
6147 #define CAN_FS1R_FSC3                        CAN_FS1R_FSC3_Msk                 /*!< Filter Scale Configuration for filter 3 */
6148 #define CAN_FS1R_FSC4_Pos                    (4U)
6149 #define CAN_FS1R_FSC4_Msk                    (0x1UL << CAN_FS1R_FSC4_Pos)       /*!< 0x00000010 */
6150 #define CAN_FS1R_FSC4                        CAN_FS1R_FSC4_Msk                 /*!< Filter Scale Configuration for filter 4 */
6151 #define CAN_FS1R_FSC5_Pos                    (5U)
6152 #define CAN_FS1R_FSC5_Msk                    (0x1UL << CAN_FS1R_FSC5_Pos)       /*!< 0x00000020 */
6153 #define CAN_FS1R_FSC5                        CAN_FS1R_FSC5_Msk                 /*!< Filter Scale Configuration for filter 5 */
6154 #define CAN_FS1R_FSC6_Pos                    (6U)
6155 #define CAN_FS1R_FSC6_Msk                    (0x1UL << CAN_FS1R_FSC6_Pos)       /*!< 0x00000040 */
6156 #define CAN_FS1R_FSC6                        CAN_FS1R_FSC6_Msk                 /*!< Filter Scale Configuration for filter 6 */
6157 #define CAN_FS1R_FSC7_Pos                    (7U)
6158 #define CAN_FS1R_FSC7_Msk                    (0x1UL << CAN_FS1R_FSC7_Pos)       /*!< 0x00000080 */
6159 #define CAN_FS1R_FSC7                        CAN_FS1R_FSC7_Msk                 /*!< Filter Scale Configuration for filter 7 */
6160 #define CAN_FS1R_FSC8_Pos                    (8U)
6161 #define CAN_FS1R_FSC8_Msk                    (0x1UL << CAN_FS1R_FSC8_Pos)       /*!< 0x00000100 */
6162 #define CAN_FS1R_FSC8                        CAN_FS1R_FSC8_Msk                 /*!< Filter Scale Configuration for filter 8 */
6163 #define CAN_FS1R_FSC9_Pos                    (9U)
6164 #define CAN_FS1R_FSC9_Msk                    (0x1UL << CAN_FS1R_FSC9_Pos)       /*!< 0x00000200 */
6165 #define CAN_FS1R_FSC9                        CAN_FS1R_FSC9_Msk                 /*!< Filter Scale Configuration for filter 9 */
6166 #define CAN_FS1R_FSC10_Pos                   (10U)
6167 #define CAN_FS1R_FSC10_Msk                   (0x1UL << CAN_FS1R_FSC10_Pos)      /*!< 0x00000400 */
6168 #define CAN_FS1R_FSC10                       CAN_FS1R_FSC10_Msk                /*!< Filter Scale Configuration for filter 10 */
6169 #define CAN_FS1R_FSC11_Pos                   (11U)
6170 #define CAN_FS1R_FSC11_Msk                   (0x1UL << CAN_FS1R_FSC11_Pos)      /*!< 0x00000800 */
6171 #define CAN_FS1R_FSC11                       CAN_FS1R_FSC11_Msk                /*!< Filter Scale Configuration for filter 11 */
6172 #define CAN_FS1R_FSC12_Pos                   (12U)
6173 #define CAN_FS1R_FSC12_Msk                   (0x1UL << CAN_FS1R_FSC12_Pos)      /*!< 0x00001000 */
6174 #define CAN_FS1R_FSC12                       CAN_FS1R_FSC12_Msk                /*!< Filter Scale Configuration for filter 12 */
6175 #define CAN_FS1R_FSC13_Pos                   (13U)
6176 #define CAN_FS1R_FSC13_Msk                   (0x1UL << CAN_FS1R_FSC13_Pos)      /*!< 0x00002000 */
6177 #define CAN_FS1R_FSC13                       CAN_FS1R_FSC13_Msk                /*!< Filter Scale Configuration for filter 13 */
6178 
6179 /******************  Bit definition for CAN_FFA1R register  *******************/
6180 #define CAN_FFA1R_FFA_Pos                    (0U)
6181 #define CAN_FFA1R_FFA_Msk                    (0x3FFFUL << CAN_FFA1R_FFA_Pos)    /*!< 0x00003FFF */
6182 #define CAN_FFA1R_FFA                        CAN_FFA1R_FFA_Msk                 /*!< Filter FIFO Assignment */
6183 #define CAN_FFA1R_FFA0_Pos                   (0U)
6184 #define CAN_FFA1R_FFA0_Msk                   (0x1UL << CAN_FFA1R_FFA0_Pos)      /*!< 0x00000001 */
6185 #define CAN_FFA1R_FFA0                       CAN_FFA1R_FFA0_Msk                /*!< Filter FIFO Assignment for filter 0 */
6186 #define CAN_FFA1R_FFA1_Pos                   (1U)
6187 #define CAN_FFA1R_FFA1_Msk                   (0x1UL << CAN_FFA1R_FFA1_Pos)      /*!< 0x00000002 */
6188 #define CAN_FFA1R_FFA1                       CAN_FFA1R_FFA1_Msk                /*!< Filter FIFO Assignment for filter 1 */
6189 #define CAN_FFA1R_FFA2_Pos                   (2U)
6190 #define CAN_FFA1R_FFA2_Msk                   (0x1UL << CAN_FFA1R_FFA2_Pos)      /*!< 0x00000004 */
6191 #define CAN_FFA1R_FFA2                       CAN_FFA1R_FFA2_Msk                /*!< Filter FIFO Assignment for filter 2 */
6192 #define CAN_FFA1R_FFA3_Pos                   (3U)
6193 #define CAN_FFA1R_FFA3_Msk                   (0x1UL << CAN_FFA1R_FFA3_Pos)      /*!< 0x00000008 */
6194 #define CAN_FFA1R_FFA3                       CAN_FFA1R_FFA3_Msk                /*!< Filter FIFO Assignment for filter 3 */
6195 #define CAN_FFA1R_FFA4_Pos                   (4U)
6196 #define CAN_FFA1R_FFA4_Msk                   (0x1UL << CAN_FFA1R_FFA4_Pos)      /*!< 0x00000010 */
6197 #define CAN_FFA1R_FFA4                       CAN_FFA1R_FFA4_Msk                /*!< Filter FIFO Assignment for filter 4 */
6198 #define CAN_FFA1R_FFA5_Pos                   (5U)
6199 #define CAN_FFA1R_FFA5_Msk                   (0x1UL << CAN_FFA1R_FFA5_Pos)      /*!< 0x00000020 */
6200 #define CAN_FFA1R_FFA5                       CAN_FFA1R_FFA5_Msk                /*!< Filter FIFO Assignment for filter 5 */
6201 #define CAN_FFA1R_FFA6_Pos                   (6U)
6202 #define CAN_FFA1R_FFA6_Msk                   (0x1UL << CAN_FFA1R_FFA6_Pos)      /*!< 0x00000040 */
6203 #define CAN_FFA1R_FFA6                       CAN_FFA1R_FFA6_Msk                /*!< Filter FIFO Assignment for filter 6 */
6204 #define CAN_FFA1R_FFA7_Pos                   (7U)
6205 #define CAN_FFA1R_FFA7_Msk                   (0x1UL << CAN_FFA1R_FFA7_Pos)      /*!< 0x00000080 */
6206 #define CAN_FFA1R_FFA7                       CAN_FFA1R_FFA7_Msk                /*!< Filter FIFO Assignment for filter 7 */
6207 #define CAN_FFA1R_FFA8_Pos                   (8U)
6208 #define CAN_FFA1R_FFA8_Msk                   (0x1UL << CAN_FFA1R_FFA8_Pos)      /*!< 0x00000100 */
6209 #define CAN_FFA1R_FFA8                       CAN_FFA1R_FFA8_Msk                /*!< Filter FIFO Assignment for filter 8 */
6210 #define CAN_FFA1R_FFA9_Pos                   (9U)
6211 #define CAN_FFA1R_FFA9_Msk                   (0x1UL << CAN_FFA1R_FFA9_Pos)      /*!< 0x00000200 */
6212 #define CAN_FFA1R_FFA9                       CAN_FFA1R_FFA9_Msk                /*!< Filter FIFO Assignment for filter 9 */
6213 #define CAN_FFA1R_FFA10_Pos                  (10U)
6214 #define CAN_FFA1R_FFA10_Msk                  (0x1UL << CAN_FFA1R_FFA10_Pos)     /*!< 0x00000400 */
6215 #define CAN_FFA1R_FFA10                      CAN_FFA1R_FFA10_Msk               /*!< Filter FIFO Assignment for filter 10 */
6216 #define CAN_FFA1R_FFA11_Pos                  (11U)
6217 #define CAN_FFA1R_FFA11_Msk                  (0x1UL << CAN_FFA1R_FFA11_Pos)     /*!< 0x00000800 */
6218 #define CAN_FFA1R_FFA11                      CAN_FFA1R_FFA11_Msk               /*!< Filter FIFO Assignment for filter 11 */
6219 #define CAN_FFA1R_FFA12_Pos                  (12U)
6220 #define CAN_FFA1R_FFA12_Msk                  (0x1UL << CAN_FFA1R_FFA12_Pos)     /*!< 0x00001000 */
6221 #define CAN_FFA1R_FFA12                      CAN_FFA1R_FFA12_Msk               /*!< Filter FIFO Assignment for filter 12 */
6222 #define CAN_FFA1R_FFA13_Pos                  (13U)
6223 #define CAN_FFA1R_FFA13_Msk                  (0x1UL << CAN_FFA1R_FFA13_Pos)     /*!< 0x00002000 */
6224 #define CAN_FFA1R_FFA13                      CAN_FFA1R_FFA13_Msk               /*!< Filter FIFO Assignment for filter 13 */
6225 
6226 /*******************  Bit definition for CAN_FA1R register  *******************/
6227 #define CAN_FA1R_FACT_Pos                    (0U)
6228 #define CAN_FA1R_FACT_Msk                    (0x3FFFUL << CAN_FA1R_FACT_Pos)    /*!< 0x00003FFF */
6229 #define CAN_FA1R_FACT                        CAN_FA1R_FACT_Msk                 /*!< Filter Active */
6230 #define CAN_FA1R_FACT0_Pos                   (0U)
6231 #define CAN_FA1R_FACT0_Msk                   (0x1UL << CAN_FA1R_FACT0_Pos)      /*!< 0x00000001 */
6232 #define CAN_FA1R_FACT0                       CAN_FA1R_FACT0_Msk                /*!< Filter 0 Active */
6233 #define CAN_FA1R_FACT1_Pos                   (1U)
6234 #define CAN_FA1R_FACT1_Msk                   (0x1UL << CAN_FA1R_FACT1_Pos)      /*!< 0x00000002 */
6235 #define CAN_FA1R_FACT1                       CAN_FA1R_FACT1_Msk                /*!< Filter 1 Active */
6236 #define CAN_FA1R_FACT2_Pos                   (2U)
6237 #define CAN_FA1R_FACT2_Msk                   (0x1UL << CAN_FA1R_FACT2_Pos)      /*!< 0x00000004 */
6238 #define CAN_FA1R_FACT2                       CAN_FA1R_FACT2_Msk                /*!< Filter 2 Active */
6239 #define CAN_FA1R_FACT3_Pos                   (3U)
6240 #define CAN_FA1R_FACT3_Msk                   (0x1UL << CAN_FA1R_FACT3_Pos)      /*!< 0x00000008 */
6241 #define CAN_FA1R_FACT3                       CAN_FA1R_FACT3_Msk                /*!< Filter 3 Active */
6242 #define CAN_FA1R_FACT4_Pos                   (4U)
6243 #define CAN_FA1R_FACT4_Msk                   (0x1UL << CAN_FA1R_FACT4_Pos)      /*!< 0x00000010 */
6244 #define CAN_FA1R_FACT4                       CAN_FA1R_FACT4_Msk                /*!< Filter 4 Active */
6245 #define CAN_FA1R_FACT5_Pos                   (5U)
6246 #define CAN_FA1R_FACT5_Msk                   (0x1UL << CAN_FA1R_FACT5_Pos)      /*!< 0x00000020 */
6247 #define CAN_FA1R_FACT5                       CAN_FA1R_FACT5_Msk                /*!< Filter 5 Active */
6248 #define CAN_FA1R_FACT6_Pos                   (6U)
6249 #define CAN_FA1R_FACT6_Msk                   (0x1UL << CAN_FA1R_FACT6_Pos)      /*!< 0x00000040 */
6250 #define CAN_FA1R_FACT6                       CAN_FA1R_FACT6_Msk                /*!< Filter 6 Active */
6251 #define CAN_FA1R_FACT7_Pos                   (7U)
6252 #define CAN_FA1R_FACT7_Msk                   (0x1UL << CAN_FA1R_FACT7_Pos)      /*!< 0x00000080 */
6253 #define CAN_FA1R_FACT7                       CAN_FA1R_FACT7_Msk                /*!< Filter 7 Active */
6254 #define CAN_FA1R_FACT8_Pos                   (8U)
6255 #define CAN_FA1R_FACT8_Msk                   (0x1UL << CAN_FA1R_FACT8_Pos)      /*!< 0x00000100 */
6256 #define CAN_FA1R_FACT8                       CAN_FA1R_FACT8_Msk                /*!< Filter 8 Active */
6257 #define CAN_FA1R_FACT9_Pos                   (9U)
6258 #define CAN_FA1R_FACT9_Msk                   (0x1UL << CAN_FA1R_FACT9_Pos)      /*!< 0x00000200 */
6259 #define CAN_FA1R_FACT9                       CAN_FA1R_FACT9_Msk                /*!< Filter 9 Active */
6260 #define CAN_FA1R_FACT10_Pos                  (10U)
6261 #define CAN_FA1R_FACT10_Msk                  (0x1UL << CAN_FA1R_FACT10_Pos)     /*!< 0x00000400 */
6262 #define CAN_FA1R_FACT10                      CAN_FA1R_FACT10_Msk               /*!< Filter 10 Active */
6263 #define CAN_FA1R_FACT11_Pos                  (11U)
6264 #define CAN_FA1R_FACT11_Msk                  (0x1UL << CAN_FA1R_FACT11_Pos)     /*!< 0x00000800 */
6265 #define CAN_FA1R_FACT11                      CAN_FA1R_FACT11_Msk               /*!< Filter 11 Active */
6266 #define CAN_FA1R_FACT12_Pos                  (12U)
6267 #define CAN_FA1R_FACT12_Msk                  (0x1UL << CAN_FA1R_FACT12_Pos)     /*!< 0x00001000 */
6268 #define CAN_FA1R_FACT12                      CAN_FA1R_FACT12_Msk               /*!< Filter 12 Active */
6269 #define CAN_FA1R_FACT13_Pos                  (13U)
6270 #define CAN_FA1R_FACT13_Msk                  (0x1UL << CAN_FA1R_FACT13_Pos)     /*!< 0x00002000 */
6271 #define CAN_FA1R_FACT13                      CAN_FA1R_FACT13_Msk               /*!< Filter 13 Active */
6272 
6273 /*******************  Bit definition for CAN_F0R1 register  *******************/
6274 #define CAN_F0R1_FB0_Pos                     (0U)
6275 #define CAN_F0R1_FB0_Msk                     (0x1UL << CAN_F0R1_FB0_Pos)        /*!< 0x00000001 */
6276 #define CAN_F0R1_FB0                         CAN_F0R1_FB0_Msk                  /*!< Filter bit 0 */
6277 #define CAN_F0R1_FB1_Pos                     (1U)
6278 #define CAN_F0R1_FB1_Msk                     (0x1UL << CAN_F0R1_FB1_Pos)        /*!< 0x00000002 */
6279 #define CAN_F0R1_FB1                         CAN_F0R1_FB1_Msk                  /*!< Filter bit 1 */
6280 #define CAN_F0R1_FB2_Pos                     (2U)
6281 #define CAN_F0R1_FB2_Msk                     (0x1UL << CAN_F0R1_FB2_Pos)        /*!< 0x00000004 */
6282 #define CAN_F0R1_FB2                         CAN_F0R1_FB2_Msk                  /*!< Filter bit 2 */
6283 #define CAN_F0R1_FB3_Pos                     (3U)
6284 #define CAN_F0R1_FB3_Msk                     (0x1UL << CAN_F0R1_FB3_Pos)        /*!< 0x00000008 */
6285 #define CAN_F0R1_FB3                         CAN_F0R1_FB3_Msk                  /*!< Filter bit 3 */
6286 #define CAN_F0R1_FB4_Pos                     (4U)
6287 #define CAN_F0R1_FB4_Msk                     (0x1UL << CAN_F0R1_FB4_Pos)        /*!< 0x00000010 */
6288 #define CAN_F0R1_FB4                         CAN_F0R1_FB4_Msk                  /*!< Filter bit 4 */
6289 #define CAN_F0R1_FB5_Pos                     (5U)
6290 #define CAN_F0R1_FB5_Msk                     (0x1UL << CAN_F0R1_FB5_Pos)        /*!< 0x00000020 */
6291 #define CAN_F0R1_FB5                         CAN_F0R1_FB5_Msk                  /*!< Filter bit 5 */
6292 #define CAN_F0R1_FB6_Pos                     (6U)
6293 #define CAN_F0R1_FB6_Msk                     (0x1UL << CAN_F0R1_FB6_Pos)        /*!< 0x00000040 */
6294 #define CAN_F0R1_FB6                         CAN_F0R1_FB6_Msk                  /*!< Filter bit 6 */
6295 #define CAN_F0R1_FB7_Pos                     (7U)
6296 #define CAN_F0R1_FB7_Msk                     (0x1UL << CAN_F0R1_FB7_Pos)        /*!< 0x00000080 */
6297 #define CAN_F0R1_FB7                         CAN_F0R1_FB7_Msk                  /*!< Filter bit 7 */
6298 #define CAN_F0R1_FB8_Pos                     (8U)
6299 #define CAN_F0R1_FB8_Msk                     (0x1UL << CAN_F0R1_FB8_Pos)        /*!< 0x00000100 */
6300 #define CAN_F0R1_FB8                         CAN_F0R1_FB8_Msk                  /*!< Filter bit 8 */
6301 #define CAN_F0R1_FB9_Pos                     (9U)
6302 #define CAN_F0R1_FB9_Msk                     (0x1UL << CAN_F0R1_FB9_Pos)        /*!< 0x00000200 */
6303 #define CAN_F0R1_FB9                         CAN_F0R1_FB9_Msk                  /*!< Filter bit 9 */
6304 #define CAN_F0R1_FB10_Pos                    (10U)
6305 #define CAN_F0R1_FB10_Msk                    (0x1UL << CAN_F0R1_FB10_Pos)       /*!< 0x00000400 */
6306 #define CAN_F0R1_FB10                        CAN_F0R1_FB10_Msk                 /*!< Filter bit 10 */
6307 #define CAN_F0R1_FB11_Pos                    (11U)
6308 #define CAN_F0R1_FB11_Msk                    (0x1UL << CAN_F0R1_FB11_Pos)       /*!< 0x00000800 */
6309 #define CAN_F0R1_FB11                        CAN_F0R1_FB11_Msk                 /*!< Filter bit 11 */
6310 #define CAN_F0R1_FB12_Pos                    (12U)
6311 #define CAN_F0R1_FB12_Msk                    (0x1UL << CAN_F0R1_FB12_Pos)       /*!< 0x00001000 */
6312 #define CAN_F0R1_FB12                        CAN_F0R1_FB12_Msk                 /*!< Filter bit 12 */
6313 #define CAN_F0R1_FB13_Pos                    (13U)
6314 #define CAN_F0R1_FB13_Msk                    (0x1UL << CAN_F0R1_FB13_Pos)       /*!< 0x00002000 */
6315 #define CAN_F0R1_FB13                        CAN_F0R1_FB13_Msk                 /*!< Filter bit 13 */
6316 #define CAN_F0R1_FB14_Pos                    (14U)
6317 #define CAN_F0R1_FB14_Msk                    (0x1UL << CAN_F0R1_FB14_Pos)       /*!< 0x00004000 */
6318 #define CAN_F0R1_FB14                        CAN_F0R1_FB14_Msk                 /*!< Filter bit 14 */
6319 #define CAN_F0R1_FB15_Pos                    (15U)
6320 #define CAN_F0R1_FB15_Msk                    (0x1UL << CAN_F0R1_FB15_Pos)       /*!< 0x00008000 */
6321 #define CAN_F0R1_FB15                        CAN_F0R1_FB15_Msk                 /*!< Filter bit 15 */
6322 #define CAN_F0R1_FB16_Pos                    (16U)
6323 #define CAN_F0R1_FB16_Msk                    (0x1UL << CAN_F0R1_FB16_Pos)       /*!< 0x00010000 */
6324 #define CAN_F0R1_FB16                        CAN_F0R1_FB16_Msk                 /*!< Filter bit 16 */
6325 #define CAN_F0R1_FB17_Pos                    (17U)
6326 #define CAN_F0R1_FB17_Msk                    (0x1UL << CAN_F0R1_FB17_Pos)       /*!< 0x00020000 */
6327 #define CAN_F0R1_FB17                        CAN_F0R1_FB17_Msk                 /*!< Filter bit 17 */
6328 #define CAN_F0R1_FB18_Pos                    (18U)
6329 #define CAN_F0R1_FB18_Msk                    (0x1UL << CAN_F0R1_FB18_Pos)       /*!< 0x00040000 */
6330 #define CAN_F0R1_FB18                        CAN_F0R1_FB18_Msk                 /*!< Filter bit 18 */
6331 #define CAN_F0R1_FB19_Pos                    (19U)
6332 #define CAN_F0R1_FB19_Msk                    (0x1UL << CAN_F0R1_FB19_Pos)       /*!< 0x00080000 */
6333 #define CAN_F0R1_FB19                        CAN_F0R1_FB19_Msk                 /*!< Filter bit 19 */
6334 #define CAN_F0R1_FB20_Pos                    (20U)
6335 #define CAN_F0R1_FB20_Msk                    (0x1UL << CAN_F0R1_FB20_Pos)       /*!< 0x00100000 */
6336 #define CAN_F0R1_FB20                        CAN_F0R1_FB20_Msk                 /*!< Filter bit 20 */
6337 #define CAN_F0R1_FB21_Pos                    (21U)
6338 #define CAN_F0R1_FB21_Msk                    (0x1UL << CAN_F0R1_FB21_Pos)       /*!< 0x00200000 */
6339 #define CAN_F0R1_FB21                        CAN_F0R1_FB21_Msk                 /*!< Filter bit 21 */
6340 #define CAN_F0R1_FB22_Pos                    (22U)
6341 #define CAN_F0R1_FB22_Msk                    (0x1UL << CAN_F0R1_FB22_Pos)       /*!< 0x00400000 */
6342 #define CAN_F0R1_FB22                        CAN_F0R1_FB22_Msk                 /*!< Filter bit 22 */
6343 #define CAN_F0R1_FB23_Pos                    (23U)
6344 #define CAN_F0R1_FB23_Msk                    (0x1UL << CAN_F0R1_FB23_Pos)       /*!< 0x00800000 */
6345 #define CAN_F0R1_FB23                        CAN_F0R1_FB23_Msk                 /*!< Filter bit 23 */
6346 #define CAN_F0R1_FB24_Pos                    (24U)
6347 #define CAN_F0R1_FB24_Msk                    (0x1UL << CAN_F0R1_FB24_Pos)       /*!< 0x01000000 */
6348 #define CAN_F0R1_FB24                        CAN_F0R1_FB24_Msk                 /*!< Filter bit 24 */
6349 #define CAN_F0R1_FB25_Pos                    (25U)
6350 #define CAN_F0R1_FB25_Msk                    (0x1UL << CAN_F0R1_FB25_Pos)       /*!< 0x02000000 */
6351 #define CAN_F0R1_FB25                        CAN_F0R1_FB25_Msk                 /*!< Filter bit 25 */
6352 #define CAN_F0R1_FB26_Pos                    (26U)
6353 #define CAN_F0R1_FB26_Msk                    (0x1UL << CAN_F0R1_FB26_Pos)       /*!< 0x04000000 */
6354 #define CAN_F0R1_FB26                        CAN_F0R1_FB26_Msk                 /*!< Filter bit 26 */
6355 #define CAN_F0R1_FB27_Pos                    (27U)
6356 #define CAN_F0R1_FB27_Msk                    (0x1UL << CAN_F0R1_FB27_Pos)       /*!< 0x08000000 */
6357 #define CAN_F0R1_FB27                        CAN_F0R1_FB27_Msk                 /*!< Filter bit 27 */
6358 #define CAN_F0R1_FB28_Pos                    (28U)
6359 #define CAN_F0R1_FB28_Msk                    (0x1UL << CAN_F0R1_FB28_Pos)       /*!< 0x10000000 */
6360 #define CAN_F0R1_FB28                        CAN_F0R1_FB28_Msk                 /*!< Filter bit 28 */
6361 #define CAN_F0R1_FB29_Pos                    (29U)
6362 #define CAN_F0R1_FB29_Msk                    (0x1UL << CAN_F0R1_FB29_Pos)       /*!< 0x20000000 */
6363 #define CAN_F0R1_FB29                        CAN_F0R1_FB29_Msk                 /*!< Filter bit 29 */
6364 #define CAN_F0R1_FB30_Pos                    (30U)
6365 #define CAN_F0R1_FB30_Msk                    (0x1UL << CAN_F0R1_FB30_Pos)       /*!< 0x40000000 */
6366 #define CAN_F0R1_FB30                        CAN_F0R1_FB30_Msk                 /*!< Filter bit 30 */
6367 #define CAN_F0R1_FB31_Pos                    (31U)
6368 #define CAN_F0R1_FB31_Msk                    (0x1UL << CAN_F0R1_FB31_Pos)       /*!< 0x80000000 */
6369 #define CAN_F0R1_FB31                        CAN_F0R1_FB31_Msk                 /*!< Filter bit 31 */
6370 
6371 /*******************  Bit definition for CAN_F1R1 register  *******************/
6372 #define CAN_F1R1_FB0_Pos                     (0U)
6373 #define CAN_F1R1_FB0_Msk                     (0x1UL << CAN_F1R1_FB0_Pos)        /*!< 0x00000001 */
6374 #define CAN_F1R1_FB0                         CAN_F1R1_FB0_Msk                  /*!< Filter bit 0 */
6375 #define CAN_F1R1_FB1_Pos                     (1U)
6376 #define CAN_F1R1_FB1_Msk                     (0x1UL << CAN_F1R1_FB1_Pos)        /*!< 0x00000002 */
6377 #define CAN_F1R1_FB1                         CAN_F1R1_FB1_Msk                  /*!< Filter bit 1 */
6378 #define CAN_F1R1_FB2_Pos                     (2U)
6379 #define CAN_F1R1_FB2_Msk                     (0x1UL << CAN_F1R1_FB2_Pos)        /*!< 0x00000004 */
6380 #define CAN_F1R1_FB2                         CAN_F1R1_FB2_Msk                  /*!< Filter bit 2 */
6381 #define CAN_F1R1_FB3_Pos                     (3U)
6382 #define CAN_F1R1_FB3_Msk                     (0x1UL << CAN_F1R1_FB3_Pos)        /*!< 0x00000008 */
6383 #define CAN_F1R1_FB3                         CAN_F1R1_FB3_Msk                  /*!< Filter bit 3 */
6384 #define CAN_F1R1_FB4_Pos                     (4U)
6385 #define CAN_F1R1_FB4_Msk                     (0x1UL << CAN_F1R1_FB4_Pos)        /*!< 0x00000010 */
6386 #define CAN_F1R1_FB4                         CAN_F1R1_FB4_Msk                  /*!< Filter bit 4 */
6387 #define CAN_F1R1_FB5_Pos                     (5U)
6388 #define CAN_F1R1_FB5_Msk                     (0x1UL << CAN_F1R1_FB5_Pos)        /*!< 0x00000020 */
6389 #define CAN_F1R1_FB5                         CAN_F1R1_FB5_Msk                  /*!< Filter bit 5 */
6390 #define CAN_F1R1_FB6_Pos                     (6U)
6391 #define CAN_F1R1_FB6_Msk                     (0x1UL << CAN_F1R1_FB6_Pos)        /*!< 0x00000040 */
6392 #define CAN_F1R1_FB6                         CAN_F1R1_FB6_Msk                  /*!< Filter bit 6 */
6393 #define CAN_F1R1_FB7_Pos                     (7U)
6394 #define CAN_F1R1_FB7_Msk                     (0x1UL << CAN_F1R1_FB7_Pos)        /*!< 0x00000080 */
6395 #define CAN_F1R1_FB7                         CAN_F1R1_FB7_Msk                  /*!< Filter bit 7 */
6396 #define CAN_F1R1_FB8_Pos                     (8U)
6397 #define CAN_F1R1_FB8_Msk                     (0x1UL << CAN_F1R1_FB8_Pos)        /*!< 0x00000100 */
6398 #define CAN_F1R1_FB8                         CAN_F1R1_FB8_Msk                  /*!< Filter bit 8 */
6399 #define CAN_F1R1_FB9_Pos                     (9U)
6400 #define CAN_F1R1_FB9_Msk                     (0x1UL << CAN_F1R1_FB9_Pos)        /*!< 0x00000200 */
6401 #define CAN_F1R1_FB9                         CAN_F1R1_FB9_Msk                  /*!< Filter bit 9 */
6402 #define CAN_F1R1_FB10_Pos                    (10U)
6403 #define CAN_F1R1_FB10_Msk                    (0x1UL << CAN_F1R1_FB10_Pos)       /*!< 0x00000400 */
6404 #define CAN_F1R1_FB10                        CAN_F1R1_FB10_Msk                 /*!< Filter bit 10 */
6405 #define CAN_F1R1_FB11_Pos                    (11U)
6406 #define CAN_F1R1_FB11_Msk                    (0x1UL << CAN_F1R1_FB11_Pos)       /*!< 0x00000800 */
6407 #define CAN_F1R1_FB11                        CAN_F1R1_FB11_Msk                 /*!< Filter bit 11 */
6408 #define CAN_F1R1_FB12_Pos                    (12U)
6409 #define CAN_F1R1_FB12_Msk                    (0x1UL << CAN_F1R1_FB12_Pos)       /*!< 0x00001000 */
6410 #define CAN_F1R1_FB12                        CAN_F1R1_FB12_Msk                 /*!< Filter bit 12 */
6411 #define CAN_F1R1_FB13_Pos                    (13U)
6412 #define CAN_F1R1_FB13_Msk                    (0x1UL << CAN_F1R1_FB13_Pos)       /*!< 0x00002000 */
6413 #define CAN_F1R1_FB13                        CAN_F1R1_FB13_Msk                 /*!< Filter bit 13 */
6414 #define CAN_F1R1_FB14_Pos                    (14U)
6415 #define CAN_F1R1_FB14_Msk                    (0x1UL << CAN_F1R1_FB14_Pos)       /*!< 0x00004000 */
6416 #define CAN_F1R1_FB14                        CAN_F1R1_FB14_Msk                 /*!< Filter bit 14 */
6417 #define CAN_F1R1_FB15_Pos                    (15U)
6418 #define CAN_F1R1_FB15_Msk                    (0x1UL << CAN_F1R1_FB15_Pos)       /*!< 0x00008000 */
6419 #define CAN_F1R1_FB15                        CAN_F1R1_FB15_Msk                 /*!< Filter bit 15 */
6420 #define CAN_F1R1_FB16_Pos                    (16U)
6421 #define CAN_F1R1_FB16_Msk                    (0x1UL << CAN_F1R1_FB16_Pos)       /*!< 0x00010000 */
6422 #define CAN_F1R1_FB16                        CAN_F1R1_FB16_Msk                 /*!< Filter bit 16 */
6423 #define CAN_F1R1_FB17_Pos                    (17U)
6424 #define CAN_F1R1_FB17_Msk                    (0x1UL << CAN_F1R1_FB17_Pos)       /*!< 0x00020000 */
6425 #define CAN_F1R1_FB17                        CAN_F1R1_FB17_Msk                 /*!< Filter bit 17 */
6426 #define CAN_F1R1_FB18_Pos                    (18U)
6427 #define CAN_F1R1_FB18_Msk                    (0x1UL << CAN_F1R1_FB18_Pos)       /*!< 0x00040000 */
6428 #define CAN_F1R1_FB18                        CAN_F1R1_FB18_Msk                 /*!< Filter bit 18 */
6429 #define CAN_F1R1_FB19_Pos                    (19U)
6430 #define CAN_F1R1_FB19_Msk                    (0x1UL << CAN_F1R1_FB19_Pos)       /*!< 0x00080000 */
6431 #define CAN_F1R1_FB19                        CAN_F1R1_FB19_Msk                 /*!< Filter bit 19 */
6432 #define CAN_F1R1_FB20_Pos                    (20U)
6433 #define CAN_F1R1_FB20_Msk                    (0x1UL << CAN_F1R1_FB20_Pos)       /*!< 0x00100000 */
6434 #define CAN_F1R1_FB20                        CAN_F1R1_FB20_Msk                 /*!< Filter bit 20 */
6435 #define CAN_F1R1_FB21_Pos                    (21U)
6436 #define CAN_F1R1_FB21_Msk                    (0x1UL << CAN_F1R1_FB21_Pos)       /*!< 0x00200000 */
6437 #define CAN_F1R1_FB21                        CAN_F1R1_FB21_Msk                 /*!< Filter bit 21 */
6438 #define CAN_F1R1_FB22_Pos                    (22U)
6439 #define CAN_F1R1_FB22_Msk                    (0x1UL << CAN_F1R1_FB22_Pos)       /*!< 0x00400000 */
6440 #define CAN_F1R1_FB22                        CAN_F1R1_FB22_Msk                 /*!< Filter bit 22 */
6441 #define CAN_F1R1_FB23_Pos                    (23U)
6442 #define CAN_F1R1_FB23_Msk                    (0x1UL << CAN_F1R1_FB23_Pos)       /*!< 0x00800000 */
6443 #define CAN_F1R1_FB23                        CAN_F1R1_FB23_Msk                 /*!< Filter bit 23 */
6444 #define CAN_F1R1_FB24_Pos                    (24U)
6445 #define CAN_F1R1_FB24_Msk                    (0x1UL << CAN_F1R1_FB24_Pos)       /*!< 0x01000000 */
6446 #define CAN_F1R1_FB24                        CAN_F1R1_FB24_Msk                 /*!< Filter bit 24 */
6447 #define CAN_F1R1_FB25_Pos                    (25U)
6448 #define CAN_F1R1_FB25_Msk                    (0x1UL << CAN_F1R1_FB25_Pos)       /*!< 0x02000000 */
6449 #define CAN_F1R1_FB25                        CAN_F1R1_FB25_Msk                 /*!< Filter bit 25 */
6450 #define CAN_F1R1_FB26_Pos                    (26U)
6451 #define CAN_F1R1_FB26_Msk                    (0x1UL << CAN_F1R1_FB26_Pos)       /*!< 0x04000000 */
6452 #define CAN_F1R1_FB26                        CAN_F1R1_FB26_Msk                 /*!< Filter bit 26 */
6453 #define CAN_F1R1_FB27_Pos                    (27U)
6454 #define CAN_F1R1_FB27_Msk                    (0x1UL << CAN_F1R1_FB27_Pos)       /*!< 0x08000000 */
6455 #define CAN_F1R1_FB27                        CAN_F1R1_FB27_Msk                 /*!< Filter bit 27 */
6456 #define CAN_F1R1_FB28_Pos                    (28U)
6457 #define CAN_F1R1_FB28_Msk                    (0x1UL << CAN_F1R1_FB28_Pos)       /*!< 0x10000000 */
6458 #define CAN_F1R1_FB28                        CAN_F1R1_FB28_Msk                 /*!< Filter bit 28 */
6459 #define CAN_F1R1_FB29_Pos                    (29U)
6460 #define CAN_F1R1_FB29_Msk                    (0x1UL << CAN_F1R1_FB29_Pos)       /*!< 0x20000000 */
6461 #define CAN_F1R1_FB29                        CAN_F1R1_FB29_Msk                 /*!< Filter bit 29 */
6462 #define CAN_F1R1_FB30_Pos                    (30U)
6463 #define CAN_F1R1_FB30_Msk                    (0x1UL << CAN_F1R1_FB30_Pos)       /*!< 0x40000000 */
6464 #define CAN_F1R1_FB30                        CAN_F1R1_FB30_Msk                 /*!< Filter bit 30 */
6465 #define CAN_F1R1_FB31_Pos                    (31U)
6466 #define CAN_F1R1_FB31_Msk                    (0x1UL << CAN_F1R1_FB31_Pos)       /*!< 0x80000000 */
6467 #define CAN_F1R1_FB31                        CAN_F1R1_FB31_Msk                 /*!< Filter bit 31 */
6468 
6469 /*******************  Bit definition for CAN_F2R1 register  *******************/
6470 #define CAN_F2R1_FB0_Pos                     (0U)
6471 #define CAN_F2R1_FB0_Msk                     (0x1UL << CAN_F2R1_FB0_Pos)        /*!< 0x00000001 */
6472 #define CAN_F2R1_FB0                         CAN_F2R1_FB0_Msk                  /*!< Filter bit 0 */
6473 #define CAN_F2R1_FB1_Pos                     (1U)
6474 #define CAN_F2R1_FB1_Msk                     (0x1UL << CAN_F2R1_FB1_Pos)        /*!< 0x00000002 */
6475 #define CAN_F2R1_FB1                         CAN_F2R1_FB1_Msk                  /*!< Filter bit 1 */
6476 #define CAN_F2R1_FB2_Pos                     (2U)
6477 #define CAN_F2R1_FB2_Msk                     (0x1UL << CAN_F2R1_FB2_Pos)        /*!< 0x00000004 */
6478 #define CAN_F2R1_FB2                         CAN_F2R1_FB2_Msk                  /*!< Filter bit 2 */
6479 #define CAN_F2R1_FB3_Pos                     (3U)
6480 #define CAN_F2R1_FB3_Msk                     (0x1UL << CAN_F2R1_FB3_Pos)        /*!< 0x00000008 */
6481 #define CAN_F2R1_FB3                         CAN_F2R1_FB3_Msk                  /*!< Filter bit 3 */
6482 #define CAN_F2R1_FB4_Pos                     (4U)
6483 #define CAN_F2R1_FB4_Msk                     (0x1UL << CAN_F2R1_FB4_Pos)        /*!< 0x00000010 */
6484 #define CAN_F2R1_FB4                         CAN_F2R1_FB4_Msk                  /*!< Filter bit 4 */
6485 #define CAN_F2R1_FB5_Pos                     (5U)
6486 #define CAN_F2R1_FB5_Msk                     (0x1UL << CAN_F2R1_FB5_Pos)        /*!< 0x00000020 */
6487 #define CAN_F2R1_FB5                         CAN_F2R1_FB5_Msk                  /*!< Filter bit 5 */
6488 #define CAN_F2R1_FB6_Pos                     (6U)
6489 #define CAN_F2R1_FB6_Msk                     (0x1UL << CAN_F2R1_FB6_Pos)        /*!< 0x00000040 */
6490 #define CAN_F2R1_FB6                         CAN_F2R1_FB6_Msk                  /*!< Filter bit 6 */
6491 #define CAN_F2R1_FB7_Pos                     (7U)
6492 #define CAN_F2R1_FB7_Msk                     (0x1UL << CAN_F2R1_FB7_Pos)        /*!< 0x00000080 */
6493 #define CAN_F2R1_FB7                         CAN_F2R1_FB7_Msk                  /*!< Filter bit 7 */
6494 #define CAN_F2R1_FB8_Pos                     (8U)
6495 #define CAN_F2R1_FB8_Msk                     (0x1UL << CAN_F2R1_FB8_Pos)        /*!< 0x00000100 */
6496 #define CAN_F2R1_FB8                         CAN_F2R1_FB8_Msk                  /*!< Filter bit 8 */
6497 #define CAN_F2R1_FB9_Pos                     (9U)
6498 #define CAN_F2R1_FB9_Msk                     (0x1UL << CAN_F2R1_FB9_Pos)        /*!< 0x00000200 */
6499 #define CAN_F2R1_FB9                         CAN_F2R1_FB9_Msk                  /*!< Filter bit 9 */
6500 #define CAN_F2R1_FB10_Pos                    (10U)
6501 #define CAN_F2R1_FB10_Msk                    (0x1UL << CAN_F2R1_FB10_Pos)       /*!< 0x00000400 */
6502 #define CAN_F2R1_FB10                        CAN_F2R1_FB10_Msk                 /*!< Filter bit 10 */
6503 #define CAN_F2R1_FB11_Pos                    (11U)
6504 #define CAN_F2R1_FB11_Msk                    (0x1UL << CAN_F2R1_FB11_Pos)       /*!< 0x00000800 */
6505 #define CAN_F2R1_FB11                        CAN_F2R1_FB11_Msk                 /*!< Filter bit 11 */
6506 #define CAN_F2R1_FB12_Pos                    (12U)
6507 #define CAN_F2R1_FB12_Msk                    (0x1UL << CAN_F2R1_FB12_Pos)       /*!< 0x00001000 */
6508 #define CAN_F2R1_FB12                        CAN_F2R1_FB12_Msk                 /*!< Filter bit 12 */
6509 #define CAN_F2R1_FB13_Pos                    (13U)
6510 #define CAN_F2R1_FB13_Msk                    (0x1UL << CAN_F2R1_FB13_Pos)       /*!< 0x00002000 */
6511 #define CAN_F2R1_FB13                        CAN_F2R1_FB13_Msk                 /*!< Filter bit 13 */
6512 #define CAN_F2R1_FB14_Pos                    (14U)
6513 #define CAN_F2R1_FB14_Msk                    (0x1UL << CAN_F2R1_FB14_Pos)       /*!< 0x00004000 */
6514 #define CAN_F2R1_FB14                        CAN_F2R1_FB14_Msk                 /*!< Filter bit 14 */
6515 #define CAN_F2R1_FB15_Pos                    (15U)
6516 #define CAN_F2R1_FB15_Msk                    (0x1UL << CAN_F2R1_FB15_Pos)       /*!< 0x00008000 */
6517 #define CAN_F2R1_FB15                        CAN_F2R1_FB15_Msk                 /*!< Filter bit 15 */
6518 #define CAN_F2R1_FB16_Pos                    (16U)
6519 #define CAN_F2R1_FB16_Msk                    (0x1UL << CAN_F2R1_FB16_Pos)       /*!< 0x00010000 */
6520 #define CAN_F2R1_FB16                        CAN_F2R1_FB16_Msk                 /*!< Filter bit 16 */
6521 #define CAN_F2R1_FB17_Pos                    (17U)
6522 #define CAN_F2R1_FB17_Msk                    (0x1UL << CAN_F2R1_FB17_Pos)       /*!< 0x00020000 */
6523 #define CAN_F2R1_FB17                        CAN_F2R1_FB17_Msk                 /*!< Filter bit 17 */
6524 #define CAN_F2R1_FB18_Pos                    (18U)
6525 #define CAN_F2R1_FB18_Msk                    (0x1UL << CAN_F2R1_FB18_Pos)       /*!< 0x00040000 */
6526 #define CAN_F2R1_FB18                        CAN_F2R1_FB18_Msk                 /*!< Filter bit 18 */
6527 #define CAN_F2R1_FB19_Pos                    (19U)
6528 #define CAN_F2R1_FB19_Msk                    (0x1UL << CAN_F2R1_FB19_Pos)       /*!< 0x00080000 */
6529 #define CAN_F2R1_FB19                        CAN_F2R1_FB19_Msk                 /*!< Filter bit 19 */
6530 #define CAN_F2R1_FB20_Pos                    (20U)
6531 #define CAN_F2R1_FB20_Msk                    (0x1UL << CAN_F2R1_FB20_Pos)       /*!< 0x00100000 */
6532 #define CAN_F2R1_FB20                        CAN_F2R1_FB20_Msk                 /*!< Filter bit 20 */
6533 #define CAN_F2R1_FB21_Pos                    (21U)
6534 #define CAN_F2R1_FB21_Msk                    (0x1UL << CAN_F2R1_FB21_Pos)       /*!< 0x00200000 */
6535 #define CAN_F2R1_FB21                        CAN_F2R1_FB21_Msk                 /*!< Filter bit 21 */
6536 #define CAN_F2R1_FB22_Pos                    (22U)
6537 #define CAN_F2R1_FB22_Msk                    (0x1UL << CAN_F2R1_FB22_Pos)       /*!< 0x00400000 */
6538 #define CAN_F2R1_FB22                        CAN_F2R1_FB22_Msk                 /*!< Filter bit 22 */
6539 #define CAN_F2R1_FB23_Pos                    (23U)
6540 #define CAN_F2R1_FB23_Msk                    (0x1UL << CAN_F2R1_FB23_Pos)       /*!< 0x00800000 */
6541 #define CAN_F2R1_FB23                        CAN_F2R1_FB23_Msk                 /*!< Filter bit 23 */
6542 #define CAN_F2R1_FB24_Pos                    (24U)
6543 #define CAN_F2R1_FB24_Msk                    (0x1UL << CAN_F2R1_FB24_Pos)       /*!< 0x01000000 */
6544 #define CAN_F2R1_FB24                        CAN_F2R1_FB24_Msk                 /*!< Filter bit 24 */
6545 #define CAN_F2R1_FB25_Pos                    (25U)
6546 #define CAN_F2R1_FB25_Msk                    (0x1UL << CAN_F2R1_FB25_Pos)       /*!< 0x02000000 */
6547 #define CAN_F2R1_FB25                        CAN_F2R1_FB25_Msk                 /*!< Filter bit 25 */
6548 #define CAN_F2R1_FB26_Pos                    (26U)
6549 #define CAN_F2R1_FB26_Msk                    (0x1UL << CAN_F2R1_FB26_Pos)       /*!< 0x04000000 */
6550 #define CAN_F2R1_FB26                        CAN_F2R1_FB26_Msk                 /*!< Filter bit 26 */
6551 #define CAN_F2R1_FB27_Pos                    (27U)
6552 #define CAN_F2R1_FB27_Msk                    (0x1UL << CAN_F2R1_FB27_Pos)       /*!< 0x08000000 */
6553 #define CAN_F2R1_FB27                        CAN_F2R1_FB27_Msk                 /*!< Filter bit 27 */
6554 #define CAN_F2R1_FB28_Pos                    (28U)
6555 #define CAN_F2R1_FB28_Msk                    (0x1UL << CAN_F2R1_FB28_Pos)       /*!< 0x10000000 */
6556 #define CAN_F2R1_FB28                        CAN_F2R1_FB28_Msk                 /*!< Filter bit 28 */
6557 #define CAN_F2R1_FB29_Pos                    (29U)
6558 #define CAN_F2R1_FB29_Msk                    (0x1UL << CAN_F2R1_FB29_Pos)       /*!< 0x20000000 */
6559 #define CAN_F2R1_FB29                        CAN_F2R1_FB29_Msk                 /*!< Filter bit 29 */
6560 #define CAN_F2R1_FB30_Pos                    (30U)
6561 #define CAN_F2R1_FB30_Msk                    (0x1UL << CAN_F2R1_FB30_Pos)       /*!< 0x40000000 */
6562 #define CAN_F2R1_FB30                        CAN_F2R1_FB30_Msk                 /*!< Filter bit 30 */
6563 #define CAN_F2R1_FB31_Pos                    (31U)
6564 #define CAN_F2R1_FB31_Msk                    (0x1UL << CAN_F2R1_FB31_Pos)       /*!< 0x80000000 */
6565 #define CAN_F2R1_FB31                        CAN_F2R1_FB31_Msk                 /*!< Filter bit 31 */
6566 
6567 /*******************  Bit definition for CAN_F3R1 register  *******************/
6568 #define CAN_F3R1_FB0_Pos                     (0U)
6569 #define CAN_F3R1_FB0_Msk                     (0x1UL << CAN_F3R1_FB0_Pos)        /*!< 0x00000001 */
6570 #define CAN_F3R1_FB0                         CAN_F3R1_FB0_Msk                  /*!< Filter bit 0 */
6571 #define CAN_F3R1_FB1_Pos                     (1U)
6572 #define CAN_F3R1_FB1_Msk                     (0x1UL << CAN_F3R1_FB1_Pos)        /*!< 0x00000002 */
6573 #define CAN_F3R1_FB1                         CAN_F3R1_FB1_Msk                  /*!< Filter bit 1 */
6574 #define CAN_F3R1_FB2_Pos                     (2U)
6575 #define CAN_F3R1_FB2_Msk                     (0x1UL << CAN_F3R1_FB2_Pos)        /*!< 0x00000004 */
6576 #define CAN_F3R1_FB2                         CAN_F3R1_FB2_Msk                  /*!< Filter bit 2 */
6577 #define CAN_F3R1_FB3_Pos                     (3U)
6578 #define CAN_F3R1_FB3_Msk                     (0x1UL << CAN_F3R1_FB3_Pos)        /*!< 0x00000008 */
6579 #define CAN_F3R1_FB3                         CAN_F3R1_FB3_Msk                  /*!< Filter bit 3 */
6580 #define CAN_F3R1_FB4_Pos                     (4U)
6581 #define CAN_F3R1_FB4_Msk                     (0x1UL << CAN_F3R1_FB4_Pos)        /*!< 0x00000010 */
6582 #define CAN_F3R1_FB4                         CAN_F3R1_FB4_Msk                  /*!< Filter bit 4 */
6583 #define CAN_F3R1_FB5_Pos                     (5U)
6584 #define CAN_F3R1_FB5_Msk                     (0x1UL << CAN_F3R1_FB5_Pos)        /*!< 0x00000020 */
6585 #define CAN_F3R1_FB5                         CAN_F3R1_FB5_Msk                  /*!< Filter bit 5 */
6586 #define CAN_F3R1_FB6_Pos                     (6U)
6587 #define CAN_F3R1_FB6_Msk                     (0x1UL << CAN_F3R1_FB6_Pos)        /*!< 0x00000040 */
6588 #define CAN_F3R1_FB6                         CAN_F3R1_FB6_Msk                  /*!< Filter bit 6 */
6589 #define CAN_F3R1_FB7_Pos                     (7U)
6590 #define CAN_F3R1_FB7_Msk                     (0x1UL << CAN_F3R1_FB7_Pos)        /*!< 0x00000080 */
6591 #define CAN_F3R1_FB7                         CAN_F3R1_FB7_Msk                  /*!< Filter bit 7 */
6592 #define CAN_F3R1_FB8_Pos                     (8U)
6593 #define CAN_F3R1_FB8_Msk                     (0x1UL << CAN_F3R1_FB8_Pos)        /*!< 0x00000100 */
6594 #define CAN_F3R1_FB8                         CAN_F3R1_FB8_Msk                  /*!< Filter bit 8 */
6595 #define CAN_F3R1_FB9_Pos                     (9U)
6596 #define CAN_F3R1_FB9_Msk                     (0x1UL << CAN_F3R1_FB9_Pos)        /*!< 0x00000200 */
6597 #define CAN_F3R1_FB9                         CAN_F3R1_FB9_Msk                  /*!< Filter bit 9 */
6598 #define CAN_F3R1_FB10_Pos                    (10U)
6599 #define CAN_F3R1_FB10_Msk                    (0x1UL << CAN_F3R1_FB10_Pos)       /*!< 0x00000400 */
6600 #define CAN_F3R1_FB10                        CAN_F3R1_FB10_Msk                 /*!< Filter bit 10 */
6601 #define CAN_F3R1_FB11_Pos                    (11U)
6602 #define CAN_F3R1_FB11_Msk                    (0x1UL << CAN_F3R1_FB11_Pos)       /*!< 0x00000800 */
6603 #define CAN_F3R1_FB11                        CAN_F3R1_FB11_Msk                 /*!< Filter bit 11 */
6604 #define CAN_F3R1_FB12_Pos                    (12U)
6605 #define CAN_F3R1_FB12_Msk                    (0x1UL << CAN_F3R1_FB12_Pos)       /*!< 0x00001000 */
6606 #define CAN_F3R1_FB12                        CAN_F3R1_FB12_Msk                 /*!< Filter bit 12 */
6607 #define CAN_F3R1_FB13_Pos                    (13U)
6608 #define CAN_F3R1_FB13_Msk                    (0x1UL << CAN_F3R1_FB13_Pos)       /*!< 0x00002000 */
6609 #define CAN_F3R1_FB13                        CAN_F3R1_FB13_Msk                 /*!< Filter bit 13 */
6610 #define CAN_F3R1_FB14_Pos                    (14U)
6611 #define CAN_F3R1_FB14_Msk                    (0x1UL << CAN_F3R1_FB14_Pos)       /*!< 0x00004000 */
6612 #define CAN_F3R1_FB14                        CAN_F3R1_FB14_Msk                 /*!< Filter bit 14 */
6613 #define CAN_F3R1_FB15_Pos                    (15U)
6614 #define CAN_F3R1_FB15_Msk                    (0x1UL << CAN_F3R1_FB15_Pos)       /*!< 0x00008000 */
6615 #define CAN_F3R1_FB15                        CAN_F3R1_FB15_Msk                 /*!< Filter bit 15 */
6616 #define CAN_F3R1_FB16_Pos                    (16U)
6617 #define CAN_F3R1_FB16_Msk                    (0x1UL << CAN_F3R1_FB16_Pos)       /*!< 0x00010000 */
6618 #define CAN_F3R1_FB16                        CAN_F3R1_FB16_Msk                 /*!< Filter bit 16 */
6619 #define CAN_F3R1_FB17_Pos                    (17U)
6620 #define CAN_F3R1_FB17_Msk                    (0x1UL << CAN_F3R1_FB17_Pos)       /*!< 0x00020000 */
6621 #define CAN_F3R1_FB17                        CAN_F3R1_FB17_Msk                 /*!< Filter bit 17 */
6622 #define CAN_F3R1_FB18_Pos                    (18U)
6623 #define CAN_F3R1_FB18_Msk                    (0x1UL << CAN_F3R1_FB18_Pos)       /*!< 0x00040000 */
6624 #define CAN_F3R1_FB18                        CAN_F3R1_FB18_Msk                 /*!< Filter bit 18 */
6625 #define CAN_F3R1_FB19_Pos                    (19U)
6626 #define CAN_F3R1_FB19_Msk                    (0x1UL << CAN_F3R1_FB19_Pos)       /*!< 0x00080000 */
6627 #define CAN_F3R1_FB19                        CAN_F3R1_FB19_Msk                 /*!< Filter bit 19 */
6628 #define CAN_F3R1_FB20_Pos                    (20U)
6629 #define CAN_F3R1_FB20_Msk                    (0x1UL << CAN_F3R1_FB20_Pos)       /*!< 0x00100000 */
6630 #define CAN_F3R1_FB20                        CAN_F3R1_FB20_Msk                 /*!< Filter bit 20 */
6631 #define CAN_F3R1_FB21_Pos                    (21U)
6632 #define CAN_F3R1_FB21_Msk                    (0x1UL << CAN_F3R1_FB21_Pos)       /*!< 0x00200000 */
6633 #define CAN_F3R1_FB21                        CAN_F3R1_FB21_Msk                 /*!< Filter bit 21 */
6634 #define CAN_F3R1_FB22_Pos                    (22U)
6635 #define CAN_F3R1_FB22_Msk                    (0x1UL << CAN_F3R1_FB22_Pos)       /*!< 0x00400000 */
6636 #define CAN_F3R1_FB22                        CAN_F3R1_FB22_Msk                 /*!< Filter bit 22 */
6637 #define CAN_F3R1_FB23_Pos                    (23U)
6638 #define CAN_F3R1_FB23_Msk                    (0x1UL << CAN_F3R1_FB23_Pos)       /*!< 0x00800000 */
6639 #define CAN_F3R1_FB23                        CAN_F3R1_FB23_Msk                 /*!< Filter bit 23 */
6640 #define CAN_F3R1_FB24_Pos                    (24U)
6641 #define CAN_F3R1_FB24_Msk                    (0x1UL << CAN_F3R1_FB24_Pos)       /*!< 0x01000000 */
6642 #define CAN_F3R1_FB24                        CAN_F3R1_FB24_Msk                 /*!< Filter bit 24 */
6643 #define CAN_F3R1_FB25_Pos                    (25U)
6644 #define CAN_F3R1_FB25_Msk                    (0x1UL << CAN_F3R1_FB25_Pos)       /*!< 0x02000000 */
6645 #define CAN_F3R1_FB25                        CAN_F3R1_FB25_Msk                 /*!< Filter bit 25 */
6646 #define CAN_F3R1_FB26_Pos                    (26U)
6647 #define CAN_F3R1_FB26_Msk                    (0x1UL << CAN_F3R1_FB26_Pos)       /*!< 0x04000000 */
6648 #define CAN_F3R1_FB26                        CAN_F3R1_FB26_Msk                 /*!< Filter bit 26 */
6649 #define CAN_F3R1_FB27_Pos                    (27U)
6650 #define CAN_F3R1_FB27_Msk                    (0x1UL << CAN_F3R1_FB27_Pos)       /*!< 0x08000000 */
6651 #define CAN_F3R1_FB27                        CAN_F3R1_FB27_Msk                 /*!< Filter bit 27 */
6652 #define CAN_F3R1_FB28_Pos                    (28U)
6653 #define CAN_F3R1_FB28_Msk                    (0x1UL << CAN_F3R1_FB28_Pos)       /*!< 0x10000000 */
6654 #define CAN_F3R1_FB28                        CAN_F3R1_FB28_Msk                 /*!< Filter bit 28 */
6655 #define CAN_F3R1_FB29_Pos                    (29U)
6656 #define CAN_F3R1_FB29_Msk                    (0x1UL << CAN_F3R1_FB29_Pos)       /*!< 0x20000000 */
6657 #define CAN_F3R1_FB29                        CAN_F3R1_FB29_Msk                 /*!< Filter bit 29 */
6658 #define CAN_F3R1_FB30_Pos                    (30U)
6659 #define CAN_F3R1_FB30_Msk                    (0x1UL << CAN_F3R1_FB30_Pos)       /*!< 0x40000000 */
6660 #define CAN_F3R1_FB30                        CAN_F3R1_FB30_Msk                 /*!< Filter bit 30 */
6661 #define CAN_F3R1_FB31_Pos                    (31U)
6662 #define CAN_F3R1_FB31_Msk                    (0x1UL << CAN_F3R1_FB31_Pos)       /*!< 0x80000000 */
6663 #define CAN_F3R1_FB31                        CAN_F3R1_FB31_Msk                 /*!< Filter bit 31 */
6664 
6665 /*******************  Bit definition for CAN_F4R1 register  *******************/
6666 #define CAN_F4R1_FB0_Pos                     (0U)
6667 #define CAN_F4R1_FB0_Msk                     (0x1UL << CAN_F4R1_FB0_Pos)        /*!< 0x00000001 */
6668 #define CAN_F4R1_FB0                         CAN_F4R1_FB0_Msk                  /*!< Filter bit 0 */
6669 #define CAN_F4R1_FB1_Pos                     (1U)
6670 #define CAN_F4R1_FB1_Msk                     (0x1UL << CAN_F4R1_FB1_Pos)        /*!< 0x00000002 */
6671 #define CAN_F4R1_FB1                         CAN_F4R1_FB1_Msk                  /*!< Filter bit 1 */
6672 #define CAN_F4R1_FB2_Pos                     (2U)
6673 #define CAN_F4R1_FB2_Msk                     (0x1UL << CAN_F4R1_FB2_Pos)        /*!< 0x00000004 */
6674 #define CAN_F4R1_FB2                         CAN_F4R1_FB2_Msk                  /*!< Filter bit 2 */
6675 #define CAN_F4R1_FB3_Pos                     (3U)
6676 #define CAN_F4R1_FB3_Msk                     (0x1UL << CAN_F4R1_FB3_Pos)        /*!< 0x00000008 */
6677 #define CAN_F4R1_FB3                         CAN_F4R1_FB3_Msk                  /*!< Filter bit 3 */
6678 #define CAN_F4R1_FB4_Pos                     (4U)
6679 #define CAN_F4R1_FB4_Msk                     (0x1UL << CAN_F4R1_FB4_Pos)        /*!< 0x00000010 */
6680 #define CAN_F4R1_FB4                         CAN_F4R1_FB4_Msk                  /*!< Filter bit 4 */
6681 #define CAN_F4R1_FB5_Pos                     (5U)
6682 #define CAN_F4R1_FB5_Msk                     (0x1UL << CAN_F4R1_FB5_Pos)        /*!< 0x00000020 */
6683 #define CAN_F4R1_FB5                         CAN_F4R1_FB5_Msk                  /*!< Filter bit 5 */
6684 #define CAN_F4R1_FB6_Pos                     (6U)
6685 #define CAN_F4R1_FB6_Msk                     (0x1UL << CAN_F4R1_FB6_Pos)        /*!< 0x00000040 */
6686 #define CAN_F4R1_FB6                         CAN_F4R1_FB6_Msk                  /*!< Filter bit 6 */
6687 #define CAN_F4R1_FB7_Pos                     (7U)
6688 #define CAN_F4R1_FB7_Msk                     (0x1UL << CAN_F4R1_FB7_Pos)        /*!< 0x00000080 */
6689 #define CAN_F4R1_FB7                         CAN_F4R1_FB7_Msk                  /*!< Filter bit 7 */
6690 #define CAN_F4R1_FB8_Pos                     (8U)
6691 #define CAN_F4R1_FB8_Msk                     (0x1UL << CAN_F4R1_FB8_Pos)        /*!< 0x00000100 */
6692 #define CAN_F4R1_FB8                         CAN_F4R1_FB8_Msk                  /*!< Filter bit 8 */
6693 #define CAN_F4R1_FB9_Pos                     (9U)
6694 #define CAN_F4R1_FB9_Msk                     (0x1UL << CAN_F4R1_FB9_Pos)        /*!< 0x00000200 */
6695 #define CAN_F4R1_FB9                         CAN_F4R1_FB9_Msk                  /*!< Filter bit 9 */
6696 #define CAN_F4R1_FB10_Pos                    (10U)
6697 #define CAN_F4R1_FB10_Msk                    (0x1UL << CAN_F4R1_FB10_Pos)       /*!< 0x00000400 */
6698 #define CAN_F4R1_FB10                        CAN_F4R1_FB10_Msk                 /*!< Filter bit 10 */
6699 #define CAN_F4R1_FB11_Pos                    (11U)
6700 #define CAN_F4R1_FB11_Msk                    (0x1UL << CAN_F4R1_FB11_Pos)       /*!< 0x00000800 */
6701 #define CAN_F4R1_FB11                        CAN_F4R1_FB11_Msk                 /*!< Filter bit 11 */
6702 #define CAN_F4R1_FB12_Pos                    (12U)
6703 #define CAN_F4R1_FB12_Msk                    (0x1UL << CAN_F4R1_FB12_Pos)       /*!< 0x00001000 */
6704 #define CAN_F4R1_FB12                        CAN_F4R1_FB12_Msk                 /*!< Filter bit 12 */
6705 #define CAN_F4R1_FB13_Pos                    (13U)
6706 #define CAN_F4R1_FB13_Msk                    (0x1UL << CAN_F4R1_FB13_Pos)       /*!< 0x00002000 */
6707 #define CAN_F4R1_FB13                        CAN_F4R1_FB13_Msk                 /*!< Filter bit 13 */
6708 #define CAN_F4R1_FB14_Pos                    (14U)
6709 #define CAN_F4R1_FB14_Msk                    (0x1UL << CAN_F4R1_FB14_Pos)       /*!< 0x00004000 */
6710 #define CAN_F4R1_FB14                        CAN_F4R1_FB14_Msk                 /*!< Filter bit 14 */
6711 #define CAN_F4R1_FB15_Pos                    (15U)
6712 #define CAN_F4R1_FB15_Msk                    (0x1UL << CAN_F4R1_FB15_Pos)       /*!< 0x00008000 */
6713 #define CAN_F4R1_FB15                        CAN_F4R1_FB15_Msk                 /*!< Filter bit 15 */
6714 #define CAN_F4R1_FB16_Pos                    (16U)
6715 #define CAN_F4R1_FB16_Msk                    (0x1UL << CAN_F4R1_FB16_Pos)       /*!< 0x00010000 */
6716 #define CAN_F4R1_FB16                        CAN_F4R1_FB16_Msk                 /*!< Filter bit 16 */
6717 #define CAN_F4R1_FB17_Pos                    (17U)
6718 #define CAN_F4R1_FB17_Msk                    (0x1UL << CAN_F4R1_FB17_Pos)       /*!< 0x00020000 */
6719 #define CAN_F4R1_FB17                        CAN_F4R1_FB17_Msk                 /*!< Filter bit 17 */
6720 #define CAN_F4R1_FB18_Pos                    (18U)
6721 #define CAN_F4R1_FB18_Msk                    (0x1UL << CAN_F4R1_FB18_Pos)       /*!< 0x00040000 */
6722 #define CAN_F4R1_FB18                        CAN_F4R1_FB18_Msk                 /*!< Filter bit 18 */
6723 #define CAN_F4R1_FB19_Pos                    (19U)
6724 #define CAN_F4R1_FB19_Msk                    (0x1UL << CAN_F4R1_FB19_Pos)       /*!< 0x00080000 */
6725 #define CAN_F4R1_FB19                        CAN_F4R1_FB19_Msk                 /*!< Filter bit 19 */
6726 #define CAN_F4R1_FB20_Pos                    (20U)
6727 #define CAN_F4R1_FB20_Msk                    (0x1UL << CAN_F4R1_FB20_Pos)       /*!< 0x00100000 */
6728 #define CAN_F4R1_FB20                        CAN_F4R1_FB20_Msk                 /*!< Filter bit 20 */
6729 #define CAN_F4R1_FB21_Pos                    (21U)
6730 #define CAN_F4R1_FB21_Msk                    (0x1UL << CAN_F4R1_FB21_Pos)       /*!< 0x00200000 */
6731 #define CAN_F4R1_FB21                        CAN_F4R1_FB21_Msk                 /*!< Filter bit 21 */
6732 #define CAN_F4R1_FB22_Pos                    (22U)
6733 #define CAN_F4R1_FB22_Msk                    (0x1UL << CAN_F4R1_FB22_Pos)       /*!< 0x00400000 */
6734 #define CAN_F4R1_FB22                        CAN_F4R1_FB22_Msk                 /*!< Filter bit 22 */
6735 #define CAN_F4R1_FB23_Pos                    (23U)
6736 #define CAN_F4R1_FB23_Msk                    (0x1UL << CAN_F4R1_FB23_Pos)       /*!< 0x00800000 */
6737 #define CAN_F4R1_FB23                        CAN_F4R1_FB23_Msk                 /*!< Filter bit 23 */
6738 #define CAN_F4R1_FB24_Pos                    (24U)
6739 #define CAN_F4R1_FB24_Msk                    (0x1UL << CAN_F4R1_FB24_Pos)       /*!< 0x01000000 */
6740 #define CAN_F4R1_FB24                        CAN_F4R1_FB24_Msk                 /*!< Filter bit 24 */
6741 #define CAN_F4R1_FB25_Pos                    (25U)
6742 #define CAN_F4R1_FB25_Msk                    (0x1UL << CAN_F4R1_FB25_Pos)       /*!< 0x02000000 */
6743 #define CAN_F4R1_FB25                        CAN_F4R1_FB25_Msk                 /*!< Filter bit 25 */
6744 #define CAN_F4R1_FB26_Pos                    (26U)
6745 #define CAN_F4R1_FB26_Msk                    (0x1UL << CAN_F4R1_FB26_Pos)       /*!< 0x04000000 */
6746 #define CAN_F4R1_FB26                        CAN_F4R1_FB26_Msk                 /*!< Filter bit 26 */
6747 #define CAN_F4R1_FB27_Pos                    (27U)
6748 #define CAN_F4R1_FB27_Msk                    (0x1UL << CAN_F4R1_FB27_Pos)       /*!< 0x08000000 */
6749 #define CAN_F4R1_FB27                        CAN_F4R1_FB27_Msk                 /*!< Filter bit 27 */
6750 #define CAN_F4R1_FB28_Pos                    (28U)
6751 #define CAN_F4R1_FB28_Msk                    (0x1UL << CAN_F4R1_FB28_Pos)       /*!< 0x10000000 */
6752 #define CAN_F4R1_FB28                        CAN_F4R1_FB28_Msk                 /*!< Filter bit 28 */
6753 #define CAN_F4R1_FB29_Pos                    (29U)
6754 #define CAN_F4R1_FB29_Msk                    (0x1UL << CAN_F4R1_FB29_Pos)       /*!< 0x20000000 */
6755 #define CAN_F4R1_FB29                        CAN_F4R1_FB29_Msk                 /*!< Filter bit 29 */
6756 #define CAN_F4R1_FB30_Pos                    (30U)
6757 #define CAN_F4R1_FB30_Msk                    (0x1UL << CAN_F4R1_FB30_Pos)       /*!< 0x40000000 */
6758 #define CAN_F4R1_FB30                        CAN_F4R1_FB30_Msk                 /*!< Filter bit 30 */
6759 #define CAN_F4R1_FB31_Pos                    (31U)
6760 #define CAN_F4R1_FB31_Msk                    (0x1UL << CAN_F4R1_FB31_Pos)       /*!< 0x80000000 */
6761 #define CAN_F4R1_FB31                        CAN_F4R1_FB31_Msk                 /*!< Filter bit 31 */
6762 
6763 /*******************  Bit definition for CAN_F5R1 register  *******************/
6764 #define CAN_F5R1_FB0_Pos                     (0U)
6765 #define CAN_F5R1_FB0_Msk                     (0x1UL << CAN_F5R1_FB0_Pos)        /*!< 0x00000001 */
6766 #define CAN_F5R1_FB0                         CAN_F5R1_FB0_Msk                  /*!< Filter bit 0 */
6767 #define CAN_F5R1_FB1_Pos                     (1U)
6768 #define CAN_F5R1_FB1_Msk                     (0x1UL << CAN_F5R1_FB1_Pos)        /*!< 0x00000002 */
6769 #define CAN_F5R1_FB1                         CAN_F5R1_FB1_Msk                  /*!< Filter bit 1 */
6770 #define CAN_F5R1_FB2_Pos                     (2U)
6771 #define CAN_F5R1_FB2_Msk                     (0x1UL << CAN_F5R1_FB2_Pos)        /*!< 0x00000004 */
6772 #define CAN_F5R1_FB2                         CAN_F5R1_FB2_Msk                  /*!< Filter bit 2 */
6773 #define CAN_F5R1_FB3_Pos                     (3U)
6774 #define CAN_F5R1_FB3_Msk                     (0x1UL << CAN_F5R1_FB3_Pos)        /*!< 0x00000008 */
6775 #define CAN_F5R1_FB3                         CAN_F5R1_FB3_Msk                  /*!< Filter bit 3 */
6776 #define CAN_F5R1_FB4_Pos                     (4U)
6777 #define CAN_F5R1_FB4_Msk                     (0x1UL << CAN_F5R1_FB4_Pos)        /*!< 0x00000010 */
6778 #define CAN_F5R1_FB4                         CAN_F5R1_FB4_Msk                  /*!< Filter bit 4 */
6779 #define CAN_F5R1_FB5_Pos                     (5U)
6780 #define CAN_F5R1_FB5_Msk                     (0x1UL << CAN_F5R1_FB5_Pos)        /*!< 0x00000020 */
6781 #define CAN_F5R1_FB5                         CAN_F5R1_FB5_Msk                  /*!< Filter bit 5 */
6782 #define CAN_F5R1_FB6_Pos                     (6U)
6783 #define CAN_F5R1_FB6_Msk                     (0x1UL << CAN_F5R1_FB6_Pos)        /*!< 0x00000040 */
6784 #define CAN_F5R1_FB6                         CAN_F5R1_FB6_Msk                  /*!< Filter bit 6 */
6785 #define CAN_F5R1_FB7_Pos                     (7U)
6786 #define CAN_F5R1_FB7_Msk                     (0x1UL << CAN_F5R1_FB7_Pos)        /*!< 0x00000080 */
6787 #define CAN_F5R1_FB7                         CAN_F5R1_FB7_Msk                  /*!< Filter bit 7 */
6788 #define CAN_F5R1_FB8_Pos                     (8U)
6789 #define CAN_F5R1_FB8_Msk                     (0x1UL << CAN_F5R1_FB8_Pos)        /*!< 0x00000100 */
6790 #define CAN_F5R1_FB8                         CAN_F5R1_FB8_Msk                  /*!< Filter bit 8 */
6791 #define CAN_F5R1_FB9_Pos                     (9U)
6792 #define CAN_F5R1_FB9_Msk                     (0x1UL << CAN_F5R1_FB9_Pos)        /*!< 0x00000200 */
6793 #define CAN_F5R1_FB9                         CAN_F5R1_FB9_Msk                  /*!< Filter bit 9 */
6794 #define CAN_F5R1_FB10_Pos                    (10U)
6795 #define CAN_F5R1_FB10_Msk                    (0x1UL << CAN_F5R1_FB10_Pos)       /*!< 0x00000400 */
6796 #define CAN_F5R1_FB10                        CAN_F5R1_FB10_Msk                 /*!< Filter bit 10 */
6797 #define CAN_F5R1_FB11_Pos                    (11U)
6798 #define CAN_F5R1_FB11_Msk                    (0x1UL << CAN_F5R1_FB11_Pos)       /*!< 0x00000800 */
6799 #define CAN_F5R1_FB11                        CAN_F5R1_FB11_Msk                 /*!< Filter bit 11 */
6800 #define CAN_F5R1_FB12_Pos                    (12U)
6801 #define CAN_F5R1_FB12_Msk                    (0x1UL << CAN_F5R1_FB12_Pos)       /*!< 0x00001000 */
6802 #define CAN_F5R1_FB12                        CAN_F5R1_FB12_Msk                 /*!< Filter bit 12 */
6803 #define CAN_F5R1_FB13_Pos                    (13U)
6804 #define CAN_F5R1_FB13_Msk                    (0x1UL << CAN_F5R1_FB13_Pos)       /*!< 0x00002000 */
6805 #define CAN_F5R1_FB13                        CAN_F5R1_FB13_Msk                 /*!< Filter bit 13 */
6806 #define CAN_F5R1_FB14_Pos                    (14U)
6807 #define CAN_F5R1_FB14_Msk                    (0x1UL << CAN_F5R1_FB14_Pos)       /*!< 0x00004000 */
6808 #define CAN_F5R1_FB14                        CAN_F5R1_FB14_Msk                 /*!< Filter bit 14 */
6809 #define CAN_F5R1_FB15_Pos                    (15U)
6810 #define CAN_F5R1_FB15_Msk                    (0x1UL << CAN_F5R1_FB15_Pos)       /*!< 0x00008000 */
6811 #define CAN_F5R1_FB15                        CAN_F5R1_FB15_Msk                 /*!< Filter bit 15 */
6812 #define CAN_F5R1_FB16_Pos                    (16U)
6813 #define CAN_F5R1_FB16_Msk                    (0x1UL << CAN_F5R1_FB16_Pos)       /*!< 0x00010000 */
6814 #define CAN_F5R1_FB16                        CAN_F5R1_FB16_Msk                 /*!< Filter bit 16 */
6815 #define CAN_F5R1_FB17_Pos                    (17U)
6816 #define CAN_F5R1_FB17_Msk                    (0x1UL << CAN_F5R1_FB17_Pos)       /*!< 0x00020000 */
6817 #define CAN_F5R1_FB17                        CAN_F5R1_FB17_Msk                 /*!< Filter bit 17 */
6818 #define CAN_F5R1_FB18_Pos                    (18U)
6819 #define CAN_F5R1_FB18_Msk                    (0x1UL << CAN_F5R1_FB18_Pos)       /*!< 0x00040000 */
6820 #define CAN_F5R1_FB18                        CAN_F5R1_FB18_Msk                 /*!< Filter bit 18 */
6821 #define CAN_F5R1_FB19_Pos                    (19U)
6822 #define CAN_F5R1_FB19_Msk                    (0x1UL << CAN_F5R1_FB19_Pos)       /*!< 0x00080000 */
6823 #define CAN_F5R1_FB19                        CAN_F5R1_FB19_Msk                 /*!< Filter bit 19 */
6824 #define CAN_F5R1_FB20_Pos                    (20U)
6825 #define CAN_F5R1_FB20_Msk                    (0x1UL << CAN_F5R1_FB20_Pos)       /*!< 0x00100000 */
6826 #define CAN_F5R1_FB20                        CAN_F5R1_FB20_Msk                 /*!< Filter bit 20 */
6827 #define CAN_F5R1_FB21_Pos                    (21U)
6828 #define CAN_F5R1_FB21_Msk                    (0x1UL << CAN_F5R1_FB21_Pos)       /*!< 0x00200000 */
6829 #define CAN_F5R1_FB21                        CAN_F5R1_FB21_Msk                 /*!< Filter bit 21 */
6830 #define CAN_F5R1_FB22_Pos                    (22U)
6831 #define CAN_F5R1_FB22_Msk                    (0x1UL << CAN_F5R1_FB22_Pos)       /*!< 0x00400000 */
6832 #define CAN_F5R1_FB22                        CAN_F5R1_FB22_Msk                 /*!< Filter bit 22 */
6833 #define CAN_F5R1_FB23_Pos                    (23U)
6834 #define CAN_F5R1_FB23_Msk                    (0x1UL << CAN_F5R1_FB23_Pos)       /*!< 0x00800000 */
6835 #define CAN_F5R1_FB23                        CAN_F5R1_FB23_Msk                 /*!< Filter bit 23 */
6836 #define CAN_F5R1_FB24_Pos                    (24U)
6837 #define CAN_F5R1_FB24_Msk                    (0x1UL << CAN_F5R1_FB24_Pos)       /*!< 0x01000000 */
6838 #define CAN_F5R1_FB24                        CAN_F5R1_FB24_Msk                 /*!< Filter bit 24 */
6839 #define CAN_F5R1_FB25_Pos                    (25U)
6840 #define CAN_F5R1_FB25_Msk                    (0x1UL << CAN_F5R1_FB25_Pos)       /*!< 0x02000000 */
6841 #define CAN_F5R1_FB25                        CAN_F5R1_FB25_Msk                 /*!< Filter bit 25 */
6842 #define CAN_F5R1_FB26_Pos                    (26U)
6843 #define CAN_F5R1_FB26_Msk                    (0x1UL << CAN_F5R1_FB26_Pos)       /*!< 0x04000000 */
6844 #define CAN_F5R1_FB26                        CAN_F5R1_FB26_Msk                 /*!< Filter bit 26 */
6845 #define CAN_F5R1_FB27_Pos                    (27U)
6846 #define CAN_F5R1_FB27_Msk                    (0x1UL << CAN_F5R1_FB27_Pos)       /*!< 0x08000000 */
6847 #define CAN_F5R1_FB27                        CAN_F5R1_FB27_Msk                 /*!< Filter bit 27 */
6848 #define CAN_F5R1_FB28_Pos                    (28U)
6849 #define CAN_F5R1_FB28_Msk                    (0x1UL << CAN_F5R1_FB28_Pos)       /*!< 0x10000000 */
6850 #define CAN_F5R1_FB28                        CAN_F5R1_FB28_Msk                 /*!< Filter bit 28 */
6851 #define CAN_F5R1_FB29_Pos                    (29U)
6852 #define CAN_F5R1_FB29_Msk                    (0x1UL << CAN_F5R1_FB29_Pos)       /*!< 0x20000000 */
6853 #define CAN_F5R1_FB29                        CAN_F5R1_FB29_Msk                 /*!< Filter bit 29 */
6854 #define CAN_F5R1_FB30_Pos                    (30U)
6855 #define CAN_F5R1_FB30_Msk                    (0x1UL << CAN_F5R1_FB30_Pos)       /*!< 0x40000000 */
6856 #define CAN_F5R1_FB30                        CAN_F5R1_FB30_Msk                 /*!< Filter bit 30 */
6857 #define CAN_F5R1_FB31_Pos                    (31U)
6858 #define CAN_F5R1_FB31_Msk                    (0x1UL << CAN_F5R1_FB31_Pos)       /*!< 0x80000000 */
6859 #define CAN_F5R1_FB31                        CAN_F5R1_FB31_Msk                 /*!< Filter bit 31 */
6860 
6861 /*******************  Bit definition for CAN_F6R1 register  *******************/
6862 #define CAN_F6R1_FB0_Pos                     (0U)
6863 #define CAN_F6R1_FB0_Msk                     (0x1UL << CAN_F6R1_FB0_Pos)        /*!< 0x00000001 */
6864 #define CAN_F6R1_FB0                         CAN_F6R1_FB0_Msk                  /*!< Filter bit 0 */
6865 #define CAN_F6R1_FB1_Pos                     (1U)
6866 #define CAN_F6R1_FB1_Msk                     (0x1UL << CAN_F6R1_FB1_Pos)        /*!< 0x00000002 */
6867 #define CAN_F6R1_FB1                         CAN_F6R1_FB1_Msk                  /*!< Filter bit 1 */
6868 #define CAN_F6R1_FB2_Pos                     (2U)
6869 #define CAN_F6R1_FB2_Msk                     (0x1UL << CAN_F6R1_FB2_Pos)        /*!< 0x00000004 */
6870 #define CAN_F6R1_FB2                         CAN_F6R1_FB2_Msk                  /*!< Filter bit 2 */
6871 #define CAN_F6R1_FB3_Pos                     (3U)
6872 #define CAN_F6R1_FB3_Msk                     (0x1UL << CAN_F6R1_FB3_Pos)        /*!< 0x00000008 */
6873 #define CAN_F6R1_FB3                         CAN_F6R1_FB3_Msk                  /*!< Filter bit 3 */
6874 #define CAN_F6R1_FB4_Pos                     (4U)
6875 #define CAN_F6R1_FB4_Msk                     (0x1UL << CAN_F6R1_FB4_Pos)        /*!< 0x00000010 */
6876 #define CAN_F6R1_FB4                         CAN_F6R1_FB4_Msk                  /*!< Filter bit 4 */
6877 #define CAN_F6R1_FB5_Pos                     (5U)
6878 #define CAN_F6R1_FB5_Msk                     (0x1UL << CAN_F6R1_FB5_Pos)        /*!< 0x00000020 */
6879 #define CAN_F6R1_FB5                         CAN_F6R1_FB5_Msk                  /*!< Filter bit 5 */
6880 #define CAN_F6R1_FB6_Pos                     (6U)
6881 #define CAN_F6R1_FB6_Msk                     (0x1UL << CAN_F6R1_FB6_Pos)        /*!< 0x00000040 */
6882 #define CAN_F6R1_FB6                         CAN_F6R1_FB6_Msk                  /*!< Filter bit 6 */
6883 #define CAN_F6R1_FB7_Pos                     (7U)
6884 #define CAN_F6R1_FB7_Msk                     (0x1UL << CAN_F6R1_FB7_Pos)        /*!< 0x00000080 */
6885 #define CAN_F6R1_FB7                         CAN_F6R1_FB7_Msk                  /*!< Filter bit 7 */
6886 #define CAN_F6R1_FB8_Pos                     (8U)
6887 #define CAN_F6R1_FB8_Msk                     (0x1UL << CAN_F6R1_FB8_Pos)        /*!< 0x00000100 */
6888 #define CAN_F6R1_FB8                         CAN_F6R1_FB8_Msk                  /*!< Filter bit 8 */
6889 #define CAN_F6R1_FB9_Pos                     (9U)
6890 #define CAN_F6R1_FB9_Msk                     (0x1UL << CAN_F6R1_FB9_Pos)        /*!< 0x00000200 */
6891 #define CAN_F6R1_FB9                         CAN_F6R1_FB9_Msk                  /*!< Filter bit 9 */
6892 #define CAN_F6R1_FB10_Pos                    (10U)
6893 #define CAN_F6R1_FB10_Msk                    (0x1UL << CAN_F6R1_FB10_Pos)       /*!< 0x00000400 */
6894 #define CAN_F6R1_FB10                        CAN_F6R1_FB10_Msk                 /*!< Filter bit 10 */
6895 #define CAN_F6R1_FB11_Pos                    (11U)
6896 #define CAN_F6R1_FB11_Msk                    (0x1UL << CAN_F6R1_FB11_Pos)       /*!< 0x00000800 */
6897 #define CAN_F6R1_FB11                        CAN_F6R1_FB11_Msk                 /*!< Filter bit 11 */
6898 #define CAN_F6R1_FB12_Pos                    (12U)
6899 #define CAN_F6R1_FB12_Msk                    (0x1UL << CAN_F6R1_FB12_Pos)       /*!< 0x00001000 */
6900 #define CAN_F6R1_FB12                        CAN_F6R1_FB12_Msk                 /*!< Filter bit 12 */
6901 #define CAN_F6R1_FB13_Pos                    (13U)
6902 #define CAN_F6R1_FB13_Msk                    (0x1UL << CAN_F6R1_FB13_Pos)       /*!< 0x00002000 */
6903 #define CAN_F6R1_FB13                        CAN_F6R1_FB13_Msk                 /*!< Filter bit 13 */
6904 #define CAN_F6R1_FB14_Pos                    (14U)
6905 #define CAN_F6R1_FB14_Msk                    (0x1UL << CAN_F6R1_FB14_Pos)       /*!< 0x00004000 */
6906 #define CAN_F6R1_FB14                        CAN_F6R1_FB14_Msk                 /*!< Filter bit 14 */
6907 #define CAN_F6R1_FB15_Pos                    (15U)
6908 #define CAN_F6R1_FB15_Msk                    (0x1UL << CAN_F6R1_FB15_Pos)       /*!< 0x00008000 */
6909 #define CAN_F6R1_FB15                        CAN_F6R1_FB15_Msk                 /*!< Filter bit 15 */
6910 #define CAN_F6R1_FB16_Pos                    (16U)
6911 #define CAN_F6R1_FB16_Msk                    (0x1UL << CAN_F6R1_FB16_Pos)       /*!< 0x00010000 */
6912 #define CAN_F6R1_FB16                        CAN_F6R1_FB16_Msk                 /*!< Filter bit 16 */
6913 #define CAN_F6R1_FB17_Pos                    (17U)
6914 #define CAN_F6R1_FB17_Msk                    (0x1UL << CAN_F6R1_FB17_Pos)       /*!< 0x00020000 */
6915 #define CAN_F6R1_FB17                        CAN_F6R1_FB17_Msk                 /*!< Filter bit 17 */
6916 #define CAN_F6R1_FB18_Pos                    (18U)
6917 #define CAN_F6R1_FB18_Msk                    (0x1UL << CAN_F6R1_FB18_Pos)       /*!< 0x00040000 */
6918 #define CAN_F6R1_FB18                        CAN_F6R1_FB18_Msk                 /*!< Filter bit 18 */
6919 #define CAN_F6R1_FB19_Pos                    (19U)
6920 #define CAN_F6R1_FB19_Msk                    (0x1UL << CAN_F6R1_FB19_Pos)       /*!< 0x00080000 */
6921 #define CAN_F6R1_FB19                        CAN_F6R1_FB19_Msk                 /*!< Filter bit 19 */
6922 #define CAN_F6R1_FB20_Pos                    (20U)
6923 #define CAN_F6R1_FB20_Msk                    (0x1UL << CAN_F6R1_FB20_Pos)       /*!< 0x00100000 */
6924 #define CAN_F6R1_FB20                        CAN_F6R1_FB20_Msk                 /*!< Filter bit 20 */
6925 #define CAN_F6R1_FB21_Pos                    (21U)
6926 #define CAN_F6R1_FB21_Msk                    (0x1UL << CAN_F6R1_FB21_Pos)       /*!< 0x00200000 */
6927 #define CAN_F6R1_FB21                        CAN_F6R1_FB21_Msk                 /*!< Filter bit 21 */
6928 #define CAN_F6R1_FB22_Pos                    (22U)
6929 #define CAN_F6R1_FB22_Msk                    (0x1UL << CAN_F6R1_FB22_Pos)       /*!< 0x00400000 */
6930 #define CAN_F6R1_FB22                        CAN_F6R1_FB22_Msk                 /*!< Filter bit 22 */
6931 #define CAN_F6R1_FB23_Pos                    (23U)
6932 #define CAN_F6R1_FB23_Msk                    (0x1UL << CAN_F6R1_FB23_Pos)       /*!< 0x00800000 */
6933 #define CAN_F6R1_FB23                        CAN_F6R1_FB23_Msk                 /*!< Filter bit 23 */
6934 #define CAN_F6R1_FB24_Pos                    (24U)
6935 #define CAN_F6R1_FB24_Msk                    (0x1UL << CAN_F6R1_FB24_Pos)       /*!< 0x01000000 */
6936 #define CAN_F6R1_FB24                        CAN_F6R1_FB24_Msk                 /*!< Filter bit 24 */
6937 #define CAN_F6R1_FB25_Pos                    (25U)
6938 #define CAN_F6R1_FB25_Msk                    (0x1UL << CAN_F6R1_FB25_Pos)       /*!< 0x02000000 */
6939 #define CAN_F6R1_FB25                        CAN_F6R1_FB25_Msk                 /*!< Filter bit 25 */
6940 #define CAN_F6R1_FB26_Pos                    (26U)
6941 #define CAN_F6R1_FB26_Msk                    (0x1UL << CAN_F6R1_FB26_Pos)       /*!< 0x04000000 */
6942 #define CAN_F6R1_FB26                        CAN_F6R1_FB26_Msk                 /*!< Filter bit 26 */
6943 #define CAN_F6R1_FB27_Pos                    (27U)
6944 #define CAN_F6R1_FB27_Msk                    (0x1UL << CAN_F6R1_FB27_Pos)       /*!< 0x08000000 */
6945 #define CAN_F6R1_FB27                        CAN_F6R1_FB27_Msk                 /*!< Filter bit 27 */
6946 #define CAN_F6R1_FB28_Pos                    (28U)
6947 #define CAN_F6R1_FB28_Msk                    (0x1UL << CAN_F6R1_FB28_Pos)       /*!< 0x10000000 */
6948 #define CAN_F6R1_FB28                        CAN_F6R1_FB28_Msk                 /*!< Filter bit 28 */
6949 #define CAN_F6R1_FB29_Pos                    (29U)
6950 #define CAN_F6R1_FB29_Msk                    (0x1UL << CAN_F6R1_FB29_Pos)       /*!< 0x20000000 */
6951 #define CAN_F6R1_FB29                        CAN_F6R1_FB29_Msk                 /*!< Filter bit 29 */
6952 #define CAN_F6R1_FB30_Pos                    (30U)
6953 #define CAN_F6R1_FB30_Msk                    (0x1UL << CAN_F6R1_FB30_Pos)       /*!< 0x40000000 */
6954 #define CAN_F6R1_FB30                        CAN_F6R1_FB30_Msk                 /*!< Filter bit 30 */
6955 #define CAN_F6R1_FB31_Pos                    (31U)
6956 #define CAN_F6R1_FB31_Msk                    (0x1UL << CAN_F6R1_FB31_Pos)       /*!< 0x80000000 */
6957 #define CAN_F6R1_FB31                        CAN_F6R1_FB31_Msk                 /*!< Filter bit 31 */
6958 
6959 /*******************  Bit definition for CAN_F7R1 register  *******************/
6960 #define CAN_F7R1_FB0_Pos                     (0U)
6961 #define CAN_F7R1_FB0_Msk                     (0x1UL << CAN_F7R1_FB0_Pos)        /*!< 0x00000001 */
6962 #define CAN_F7R1_FB0                         CAN_F7R1_FB0_Msk                  /*!< Filter bit 0 */
6963 #define CAN_F7R1_FB1_Pos                     (1U)
6964 #define CAN_F7R1_FB1_Msk                     (0x1UL << CAN_F7R1_FB1_Pos)        /*!< 0x00000002 */
6965 #define CAN_F7R1_FB1                         CAN_F7R1_FB1_Msk                  /*!< Filter bit 1 */
6966 #define CAN_F7R1_FB2_Pos                     (2U)
6967 #define CAN_F7R1_FB2_Msk                     (0x1UL << CAN_F7R1_FB2_Pos)        /*!< 0x00000004 */
6968 #define CAN_F7R1_FB2                         CAN_F7R1_FB2_Msk                  /*!< Filter bit 2 */
6969 #define CAN_F7R1_FB3_Pos                     (3U)
6970 #define CAN_F7R1_FB3_Msk                     (0x1UL << CAN_F7R1_FB3_Pos)        /*!< 0x00000008 */
6971 #define CAN_F7R1_FB3                         CAN_F7R1_FB3_Msk                  /*!< Filter bit 3 */
6972 #define CAN_F7R1_FB4_Pos                     (4U)
6973 #define CAN_F7R1_FB4_Msk                     (0x1UL << CAN_F7R1_FB4_Pos)        /*!< 0x00000010 */
6974 #define CAN_F7R1_FB4                         CAN_F7R1_FB4_Msk                  /*!< Filter bit 4 */
6975 #define CAN_F7R1_FB5_Pos                     (5U)
6976 #define CAN_F7R1_FB5_Msk                     (0x1UL << CAN_F7R1_FB5_Pos)        /*!< 0x00000020 */
6977 #define CAN_F7R1_FB5                         CAN_F7R1_FB5_Msk                  /*!< Filter bit 5 */
6978 #define CAN_F7R1_FB6_Pos                     (6U)
6979 #define CAN_F7R1_FB6_Msk                     (0x1UL << CAN_F7R1_FB6_Pos)        /*!< 0x00000040 */
6980 #define CAN_F7R1_FB6                         CAN_F7R1_FB6_Msk                  /*!< Filter bit 6 */
6981 #define CAN_F7R1_FB7_Pos                     (7U)
6982 #define CAN_F7R1_FB7_Msk                     (0x1UL << CAN_F7R1_FB7_Pos)        /*!< 0x00000080 */
6983 #define CAN_F7R1_FB7                         CAN_F7R1_FB7_Msk                  /*!< Filter bit 7 */
6984 #define CAN_F7R1_FB8_Pos                     (8U)
6985 #define CAN_F7R1_FB8_Msk                     (0x1UL << CAN_F7R1_FB8_Pos)        /*!< 0x00000100 */
6986 #define CAN_F7R1_FB8                         CAN_F7R1_FB8_Msk                  /*!< Filter bit 8 */
6987 #define CAN_F7R1_FB9_Pos                     (9U)
6988 #define CAN_F7R1_FB9_Msk                     (0x1UL << CAN_F7R1_FB9_Pos)        /*!< 0x00000200 */
6989 #define CAN_F7R1_FB9                         CAN_F7R1_FB9_Msk                  /*!< Filter bit 9 */
6990 #define CAN_F7R1_FB10_Pos                    (10U)
6991 #define CAN_F7R1_FB10_Msk                    (0x1UL << CAN_F7R1_FB10_Pos)       /*!< 0x00000400 */
6992 #define CAN_F7R1_FB10                        CAN_F7R1_FB10_Msk                 /*!< Filter bit 10 */
6993 #define CAN_F7R1_FB11_Pos                    (11U)
6994 #define CAN_F7R1_FB11_Msk                    (0x1UL << CAN_F7R1_FB11_Pos)       /*!< 0x00000800 */
6995 #define CAN_F7R1_FB11                        CAN_F7R1_FB11_Msk                 /*!< Filter bit 11 */
6996 #define CAN_F7R1_FB12_Pos                    (12U)
6997 #define CAN_F7R1_FB12_Msk                    (0x1UL << CAN_F7R1_FB12_Pos)       /*!< 0x00001000 */
6998 #define CAN_F7R1_FB12                        CAN_F7R1_FB12_Msk                 /*!< Filter bit 12 */
6999 #define CAN_F7R1_FB13_Pos                    (13U)
7000 #define CAN_F7R1_FB13_Msk                    (0x1UL << CAN_F7R1_FB13_Pos)       /*!< 0x00002000 */
7001 #define CAN_F7R1_FB13                        CAN_F7R1_FB13_Msk                 /*!< Filter bit 13 */
7002 #define CAN_F7R1_FB14_Pos                    (14U)
7003 #define CAN_F7R1_FB14_Msk                    (0x1UL << CAN_F7R1_FB14_Pos)       /*!< 0x00004000 */
7004 #define CAN_F7R1_FB14                        CAN_F7R1_FB14_Msk                 /*!< Filter bit 14 */
7005 #define CAN_F7R1_FB15_Pos                    (15U)
7006 #define CAN_F7R1_FB15_Msk                    (0x1UL << CAN_F7R1_FB15_Pos)       /*!< 0x00008000 */
7007 #define CAN_F7R1_FB15                        CAN_F7R1_FB15_Msk                 /*!< Filter bit 15 */
7008 #define CAN_F7R1_FB16_Pos                    (16U)
7009 #define CAN_F7R1_FB16_Msk                    (0x1UL << CAN_F7R1_FB16_Pos)       /*!< 0x00010000 */
7010 #define CAN_F7R1_FB16                        CAN_F7R1_FB16_Msk                 /*!< Filter bit 16 */
7011 #define CAN_F7R1_FB17_Pos                    (17U)
7012 #define CAN_F7R1_FB17_Msk                    (0x1UL << CAN_F7R1_FB17_Pos)       /*!< 0x00020000 */
7013 #define CAN_F7R1_FB17                        CAN_F7R1_FB17_Msk                 /*!< Filter bit 17 */
7014 #define CAN_F7R1_FB18_Pos                    (18U)
7015 #define CAN_F7R1_FB18_Msk                    (0x1UL << CAN_F7R1_FB18_Pos)       /*!< 0x00040000 */
7016 #define CAN_F7R1_FB18                        CAN_F7R1_FB18_Msk                 /*!< Filter bit 18 */
7017 #define CAN_F7R1_FB19_Pos                    (19U)
7018 #define CAN_F7R1_FB19_Msk                    (0x1UL << CAN_F7R1_FB19_Pos)       /*!< 0x00080000 */
7019 #define CAN_F7R1_FB19                        CAN_F7R1_FB19_Msk                 /*!< Filter bit 19 */
7020 #define CAN_F7R1_FB20_Pos                    (20U)
7021 #define CAN_F7R1_FB20_Msk                    (0x1UL << CAN_F7R1_FB20_Pos)       /*!< 0x00100000 */
7022 #define CAN_F7R1_FB20                        CAN_F7R1_FB20_Msk                 /*!< Filter bit 20 */
7023 #define CAN_F7R1_FB21_Pos                    (21U)
7024 #define CAN_F7R1_FB21_Msk                    (0x1UL << CAN_F7R1_FB21_Pos)       /*!< 0x00200000 */
7025 #define CAN_F7R1_FB21                        CAN_F7R1_FB21_Msk                 /*!< Filter bit 21 */
7026 #define CAN_F7R1_FB22_Pos                    (22U)
7027 #define CAN_F7R1_FB22_Msk                    (0x1UL << CAN_F7R1_FB22_Pos)       /*!< 0x00400000 */
7028 #define CAN_F7R1_FB22                        CAN_F7R1_FB22_Msk                 /*!< Filter bit 22 */
7029 #define CAN_F7R1_FB23_Pos                    (23U)
7030 #define CAN_F7R1_FB23_Msk                    (0x1UL << CAN_F7R1_FB23_Pos)       /*!< 0x00800000 */
7031 #define CAN_F7R1_FB23                        CAN_F7R1_FB23_Msk                 /*!< Filter bit 23 */
7032 #define CAN_F7R1_FB24_Pos                    (24U)
7033 #define CAN_F7R1_FB24_Msk                    (0x1UL << CAN_F7R1_FB24_Pos)       /*!< 0x01000000 */
7034 #define CAN_F7R1_FB24                        CAN_F7R1_FB24_Msk                 /*!< Filter bit 24 */
7035 #define CAN_F7R1_FB25_Pos                    (25U)
7036 #define CAN_F7R1_FB25_Msk                    (0x1UL << CAN_F7R1_FB25_Pos)       /*!< 0x02000000 */
7037 #define CAN_F7R1_FB25                        CAN_F7R1_FB25_Msk                 /*!< Filter bit 25 */
7038 #define CAN_F7R1_FB26_Pos                    (26U)
7039 #define CAN_F7R1_FB26_Msk                    (0x1UL << CAN_F7R1_FB26_Pos)       /*!< 0x04000000 */
7040 #define CAN_F7R1_FB26                        CAN_F7R1_FB26_Msk                 /*!< Filter bit 26 */
7041 #define CAN_F7R1_FB27_Pos                    (27U)
7042 #define CAN_F7R1_FB27_Msk                    (0x1UL << CAN_F7R1_FB27_Pos)       /*!< 0x08000000 */
7043 #define CAN_F7R1_FB27                        CAN_F7R1_FB27_Msk                 /*!< Filter bit 27 */
7044 #define CAN_F7R1_FB28_Pos                    (28U)
7045 #define CAN_F7R1_FB28_Msk                    (0x1UL << CAN_F7R1_FB28_Pos)       /*!< 0x10000000 */
7046 #define CAN_F7R1_FB28                        CAN_F7R1_FB28_Msk                 /*!< Filter bit 28 */
7047 #define CAN_F7R1_FB29_Pos                    (29U)
7048 #define CAN_F7R1_FB29_Msk                    (0x1UL << CAN_F7R1_FB29_Pos)       /*!< 0x20000000 */
7049 #define CAN_F7R1_FB29                        CAN_F7R1_FB29_Msk                 /*!< Filter bit 29 */
7050 #define CAN_F7R1_FB30_Pos                    (30U)
7051 #define CAN_F7R1_FB30_Msk                    (0x1UL << CAN_F7R1_FB30_Pos)       /*!< 0x40000000 */
7052 #define CAN_F7R1_FB30                        CAN_F7R1_FB30_Msk                 /*!< Filter bit 30 */
7053 #define CAN_F7R1_FB31_Pos                    (31U)
7054 #define CAN_F7R1_FB31_Msk                    (0x1UL << CAN_F7R1_FB31_Pos)       /*!< 0x80000000 */
7055 #define CAN_F7R1_FB31                        CAN_F7R1_FB31_Msk                 /*!< Filter bit 31 */
7056 
7057 /*******************  Bit definition for CAN_F8R1 register  *******************/
7058 #define CAN_F8R1_FB0_Pos                     (0U)
7059 #define CAN_F8R1_FB0_Msk                     (0x1UL << CAN_F8R1_FB0_Pos)        /*!< 0x00000001 */
7060 #define CAN_F8R1_FB0                         CAN_F8R1_FB0_Msk                  /*!< Filter bit 0 */
7061 #define CAN_F8R1_FB1_Pos                     (1U)
7062 #define CAN_F8R1_FB1_Msk                     (0x1UL << CAN_F8R1_FB1_Pos)        /*!< 0x00000002 */
7063 #define CAN_F8R1_FB1                         CAN_F8R1_FB1_Msk                  /*!< Filter bit 1 */
7064 #define CAN_F8R1_FB2_Pos                     (2U)
7065 #define CAN_F8R1_FB2_Msk                     (0x1UL << CAN_F8R1_FB2_Pos)        /*!< 0x00000004 */
7066 #define CAN_F8R1_FB2                         CAN_F8R1_FB2_Msk                  /*!< Filter bit 2 */
7067 #define CAN_F8R1_FB3_Pos                     (3U)
7068 #define CAN_F8R1_FB3_Msk                     (0x1UL << CAN_F8R1_FB3_Pos)        /*!< 0x00000008 */
7069 #define CAN_F8R1_FB3                         CAN_F8R1_FB3_Msk                  /*!< Filter bit 3 */
7070 #define CAN_F8R1_FB4_Pos                     (4U)
7071 #define CAN_F8R1_FB4_Msk                     (0x1UL << CAN_F8R1_FB4_Pos)        /*!< 0x00000010 */
7072 #define CAN_F8R1_FB4                         CAN_F8R1_FB4_Msk                  /*!< Filter bit 4 */
7073 #define CAN_F8R1_FB5_Pos                     (5U)
7074 #define CAN_F8R1_FB5_Msk                     (0x1UL << CAN_F8R1_FB5_Pos)        /*!< 0x00000020 */
7075 #define CAN_F8R1_FB5                         CAN_F8R1_FB5_Msk                  /*!< Filter bit 5 */
7076 #define CAN_F8R1_FB6_Pos                     (6U)
7077 #define CAN_F8R1_FB6_Msk                     (0x1UL << CAN_F8R1_FB6_Pos)        /*!< 0x00000040 */
7078 #define CAN_F8R1_FB6                         CAN_F8R1_FB6_Msk                  /*!< Filter bit 6 */
7079 #define CAN_F8R1_FB7_Pos                     (7U)
7080 #define CAN_F8R1_FB7_Msk                     (0x1UL << CAN_F8R1_FB7_Pos)        /*!< 0x00000080 */
7081 #define CAN_F8R1_FB7                         CAN_F8R1_FB7_Msk                  /*!< Filter bit 7 */
7082 #define CAN_F8R1_FB8_Pos                     (8U)
7083 #define CAN_F8R1_FB8_Msk                     (0x1UL << CAN_F8R1_FB8_Pos)        /*!< 0x00000100 */
7084 #define CAN_F8R1_FB8                         CAN_F8R1_FB8_Msk                  /*!< Filter bit 8 */
7085 #define CAN_F8R1_FB9_Pos                     (9U)
7086 #define CAN_F8R1_FB9_Msk                     (0x1UL << CAN_F8R1_FB9_Pos)        /*!< 0x00000200 */
7087 #define CAN_F8R1_FB9                         CAN_F8R1_FB9_Msk                  /*!< Filter bit 9 */
7088 #define CAN_F8R1_FB10_Pos                    (10U)
7089 #define CAN_F8R1_FB10_Msk                    (0x1UL << CAN_F8R1_FB10_Pos)       /*!< 0x00000400 */
7090 #define CAN_F8R1_FB10                        CAN_F8R1_FB10_Msk                 /*!< Filter bit 10 */
7091 #define CAN_F8R1_FB11_Pos                    (11U)
7092 #define CAN_F8R1_FB11_Msk                    (0x1UL << CAN_F8R1_FB11_Pos)       /*!< 0x00000800 */
7093 #define CAN_F8R1_FB11                        CAN_F8R1_FB11_Msk                 /*!< Filter bit 11 */
7094 #define CAN_F8R1_FB12_Pos                    (12U)
7095 #define CAN_F8R1_FB12_Msk                    (0x1UL << CAN_F8R1_FB12_Pos)       /*!< 0x00001000 */
7096 #define CAN_F8R1_FB12                        CAN_F8R1_FB12_Msk                 /*!< Filter bit 12 */
7097 #define CAN_F8R1_FB13_Pos                    (13U)
7098 #define CAN_F8R1_FB13_Msk                    (0x1UL << CAN_F8R1_FB13_Pos)       /*!< 0x00002000 */
7099 #define CAN_F8R1_FB13                        CAN_F8R1_FB13_Msk                 /*!< Filter bit 13 */
7100 #define CAN_F8R1_FB14_Pos                    (14U)
7101 #define CAN_F8R1_FB14_Msk                    (0x1UL << CAN_F8R1_FB14_Pos)       /*!< 0x00004000 */
7102 #define CAN_F8R1_FB14                        CAN_F8R1_FB14_Msk                 /*!< Filter bit 14 */
7103 #define CAN_F8R1_FB15_Pos                    (15U)
7104 #define CAN_F8R1_FB15_Msk                    (0x1UL << CAN_F8R1_FB15_Pos)       /*!< 0x00008000 */
7105 #define CAN_F8R1_FB15                        CAN_F8R1_FB15_Msk                 /*!< Filter bit 15 */
7106 #define CAN_F8R1_FB16_Pos                    (16U)
7107 #define CAN_F8R1_FB16_Msk                    (0x1UL << CAN_F8R1_FB16_Pos)       /*!< 0x00010000 */
7108 #define CAN_F8R1_FB16                        CAN_F8R1_FB16_Msk                 /*!< Filter bit 16 */
7109 #define CAN_F8R1_FB17_Pos                    (17U)
7110 #define CAN_F8R1_FB17_Msk                    (0x1UL << CAN_F8R1_FB17_Pos)       /*!< 0x00020000 */
7111 #define CAN_F8R1_FB17                        CAN_F8R1_FB17_Msk                 /*!< Filter bit 17 */
7112 #define CAN_F8R1_FB18_Pos                    (18U)
7113 #define CAN_F8R1_FB18_Msk                    (0x1UL << CAN_F8R1_FB18_Pos)       /*!< 0x00040000 */
7114 #define CAN_F8R1_FB18                        CAN_F8R1_FB18_Msk                 /*!< Filter bit 18 */
7115 #define CAN_F8R1_FB19_Pos                    (19U)
7116 #define CAN_F8R1_FB19_Msk                    (0x1UL << CAN_F8R1_FB19_Pos)       /*!< 0x00080000 */
7117 #define CAN_F8R1_FB19                        CAN_F8R1_FB19_Msk                 /*!< Filter bit 19 */
7118 #define CAN_F8R1_FB20_Pos                    (20U)
7119 #define CAN_F8R1_FB20_Msk                    (0x1UL << CAN_F8R1_FB20_Pos)       /*!< 0x00100000 */
7120 #define CAN_F8R1_FB20                        CAN_F8R1_FB20_Msk                 /*!< Filter bit 20 */
7121 #define CAN_F8R1_FB21_Pos                    (21U)
7122 #define CAN_F8R1_FB21_Msk                    (0x1UL << CAN_F8R1_FB21_Pos)       /*!< 0x00200000 */
7123 #define CAN_F8R1_FB21                        CAN_F8R1_FB21_Msk                 /*!< Filter bit 21 */
7124 #define CAN_F8R1_FB22_Pos                    (22U)
7125 #define CAN_F8R1_FB22_Msk                    (0x1UL << CAN_F8R1_FB22_Pos)       /*!< 0x00400000 */
7126 #define CAN_F8R1_FB22                        CAN_F8R1_FB22_Msk                 /*!< Filter bit 22 */
7127 #define CAN_F8R1_FB23_Pos                    (23U)
7128 #define CAN_F8R1_FB23_Msk                    (0x1UL << CAN_F8R1_FB23_Pos)       /*!< 0x00800000 */
7129 #define CAN_F8R1_FB23                        CAN_F8R1_FB23_Msk                 /*!< Filter bit 23 */
7130 #define CAN_F8R1_FB24_Pos                    (24U)
7131 #define CAN_F8R1_FB24_Msk                    (0x1UL << CAN_F8R1_FB24_Pos)       /*!< 0x01000000 */
7132 #define CAN_F8R1_FB24                        CAN_F8R1_FB24_Msk                 /*!< Filter bit 24 */
7133 #define CAN_F8R1_FB25_Pos                    (25U)
7134 #define CAN_F8R1_FB25_Msk                    (0x1UL << CAN_F8R1_FB25_Pos)       /*!< 0x02000000 */
7135 #define CAN_F8R1_FB25                        CAN_F8R1_FB25_Msk                 /*!< Filter bit 25 */
7136 #define CAN_F8R1_FB26_Pos                    (26U)
7137 #define CAN_F8R1_FB26_Msk                    (0x1UL << CAN_F8R1_FB26_Pos)       /*!< 0x04000000 */
7138 #define CAN_F8R1_FB26                        CAN_F8R1_FB26_Msk                 /*!< Filter bit 26 */
7139 #define CAN_F8R1_FB27_Pos                    (27U)
7140 #define CAN_F8R1_FB27_Msk                    (0x1UL << CAN_F8R1_FB27_Pos)       /*!< 0x08000000 */
7141 #define CAN_F8R1_FB27                        CAN_F8R1_FB27_Msk                 /*!< Filter bit 27 */
7142 #define CAN_F8R1_FB28_Pos                    (28U)
7143 #define CAN_F8R1_FB28_Msk                    (0x1UL << CAN_F8R1_FB28_Pos)       /*!< 0x10000000 */
7144 #define CAN_F8R1_FB28                        CAN_F8R1_FB28_Msk                 /*!< Filter bit 28 */
7145 #define CAN_F8R1_FB29_Pos                    (29U)
7146 #define CAN_F8R1_FB29_Msk                    (0x1UL << CAN_F8R1_FB29_Pos)       /*!< 0x20000000 */
7147 #define CAN_F8R1_FB29                        CAN_F8R1_FB29_Msk                 /*!< Filter bit 29 */
7148 #define CAN_F8R1_FB30_Pos                    (30U)
7149 #define CAN_F8R1_FB30_Msk                    (0x1UL << CAN_F8R1_FB30_Pos)       /*!< 0x40000000 */
7150 #define CAN_F8R1_FB30                        CAN_F8R1_FB30_Msk                 /*!< Filter bit 30 */
7151 #define CAN_F8R1_FB31_Pos                    (31U)
7152 #define CAN_F8R1_FB31_Msk                    (0x1UL << CAN_F8R1_FB31_Pos)       /*!< 0x80000000 */
7153 #define CAN_F8R1_FB31                        CAN_F8R1_FB31_Msk                 /*!< Filter bit 31 */
7154 
7155 /*******************  Bit definition for CAN_F9R1 register  *******************/
7156 #define CAN_F9R1_FB0_Pos                     (0U)
7157 #define CAN_F9R1_FB0_Msk                     (0x1UL << CAN_F9R1_FB0_Pos)        /*!< 0x00000001 */
7158 #define CAN_F9R1_FB0                         CAN_F9R1_FB0_Msk                  /*!< Filter bit 0 */
7159 #define CAN_F9R1_FB1_Pos                     (1U)
7160 #define CAN_F9R1_FB1_Msk                     (0x1UL << CAN_F9R1_FB1_Pos)        /*!< 0x00000002 */
7161 #define CAN_F9R1_FB1                         CAN_F9R1_FB1_Msk                  /*!< Filter bit 1 */
7162 #define CAN_F9R1_FB2_Pos                     (2U)
7163 #define CAN_F9R1_FB2_Msk                     (0x1UL << CAN_F9R1_FB2_Pos)        /*!< 0x00000004 */
7164 #define CAN_F9R1_FB2                         CAN_F9R1_FB2_Msk                  /*!< Filter bit 2 */
7165 #define CAN_F9R1_FB3_Pos                     (3U)
7166 #define CAN_F9R1_FB3_Msk                     (0x1UL << CAN_F9R1_FB3_Pos)        /*!< 0x00000008 */
7167 #define CAN_F9R1_FB3                         CAN_F9R1_FB3_Msk                  /*!< Filter bit 3 */
7168 #define CAN_F9R1_FB4_Pos                     (4U)
7169 #define CAN_F9R1_FB4_Msk                     (0x1UL << CAN_F9R1_FB4_Pos)        /*!< 0x00000010 */
7170 #define CAN_F9R1_FB4                         CAN_F9R1_FB4_Msk                  /*!< Filter bit 4 */
7171 #define CAN_F9R1_FB5_Pos                     (5U)
7172 #define CAN_F9R1_FB5_Msk                     (0x1UL << CAN_F9R1_FB5_Pos)        /*!< 0x00000020 */
7173 #define CAN_F9R1_FB5                         CAN_F9R1_FB5_Msk                  /*!< Filter bit 5 */
7174 #define CAN_F9R1_FB6_Pos                     (6U)
7175 #define CAN_F9R1_FB6_Msk                     (0x1UL << CAN_F9R1_FB6_Pos)        /*!< 0x00000040 */
7176 #define CAN_F9R1_FB6                         CAN_F9R1_FB6_Msk                  /*!< Filter bit 6 */
7177 #define CAN_F9R1_FB7_Pos                     (7U)
7178 #define CAN_F9R1_FB7_Msk                     (0x1UL << CAN_F9R1_FB7_Pos)        /*!< 0x00000080 */
7179 #define CAN_F9R1_FB7                         CAN_F9R1_FB7_Msk                  /*!< Filter bit 7 */
7180 #define CAN_F9R1_FB8_Pos                     (8U)
7181 #define CAN_F9R1_FB8_Msk                     (0x1UL << CAN_F9R1_FB8_Pos)        /*!< 0x00000100 */
7182 #define CAN_F9R1_FB8                         CAN_F9R1_FB8_Msk                  /*!< Filter bit 8 */
7183 #define CAN_F9R1_FB9_Pos                     (9U)
7184 #define CAN_F9R1_FB9_Msk                     (0x1UL << CAN_F9R1_FB9_Pos)        /*!< 0x00000200 */
7185 #define CAN_F9R1_FB9                         CAN_F9R1_FB9_Msk                  /*!< Filter bit 9 */
7186 #define CAN_F9R1_FB10_Pos                    (10U)
7187 #define CAN_F9R1_FB10_Msk                    (0x1UL << CAN_F9R1_FB10_Pos)       /*!< 0x00000400 */
7188 #define CAN_F9R1_FB10                        CAN_F9R1_FB10_Msk                 /*!< Filter bit 10 */
7189 #define CAN_F9R1_FB11_Pos                    (11U)
7190 #define CAN_F9R1_FB11_Msk                    (0x1UL << CAN_F9R1_FB11_Pos)       /*!< 0x00000800 */
7191 #define CAN_F9R1_FB11                        CAN_F9R1_FB11_Msk                 /*!< Filter bit 11 */
7192 #define CAN_F9R1_FB12_Pos                    (12U)
7193 #define CAN_F9R1_FB12_Msk                    (0x1UL << CAN_F9R1_FB12_Pos)       /*!< 0x00001000 */
7194 #define CAN_F9R1_FB12                        CAN_F9R1_FB12_Msk                 /*!< Filter bit 12 */
7195 #define CAN_F9R1_FB13_Pos                    (13U)
7196 #define CAN_F9R1_FB13_Msk                    (0x1UL << CAN_F9R1_FB13_Pos)       /*!< 0x00002000 */
7197 #define CAN_F9R1_FB13                        CAN_F9R1_FB13_Msk                 /*!< Filter bit 13 */
7198 #define CAN_F9R1_FB14_Pos                    (14U)
7199 #define CAN_F9R1_FB14_Msk                    (0x1UL << CAN_F9R1_FB14_Pos)       /*!< 0x00004000 */
7200 #define CAN_F9R1_FB14                        CAN_F9R1_FB14_Msk                 /*!< Filter bit 14 */
7201 #define CAN_F9R1_FB15_Pos                    (15U)
7202 #define CAN_F9R1_FB15_Msk                    (0x1UL << CAN_F9R1_FB15_Pos)       /*!< 0x00008000 */
7203 #define CAN_F9R1_FB15                        CAN_F9R1_FB15_Msk                 /*!< Filter bit 15 */
7204 #define CAN_F9R1_FB16_Pos                    (16U)
7205 #define CAN_F9R1_FB16_Msk                    (0x1UL << CAN_F9R1_FB16_Pos)       /*!< 0x00010000 */
7206 #define CAN_F9R1_FB16                        CAN_F9R1_FB16_Msk                 /*!< Filter bit 16 */
7207 #define CAN_F9R1_FB17_Pos                    (17U)
7208 #define CAN_F9R1_FB17_Msk                    (0x1UL << CAN_F9R1_FB17_Pos)       /*!< 0x00020000 */
7209 #define CAN_F9R1_FB17                        CAN_F9R1_FB17_Msk                 /*!< Filter bit 17 */
7210 #define CAN_F9R1_FB18_Pos                    (18U)
7211 #define CAN_F9R1_FB18_Msk                    (0x1UL << CAN_F9R1_FB18_Pos)       /*!< 0x00040000 */
7212 #define CAN_F9R1_FB18                        CAN_F9R1_FB18_Msk                 /*!< Filter bit 18 */
7213 #define CAN_F9R1_FB19_Pos                    (19U)
7214 #define CAN_F9R1_FB19_Msk                    (0x1UL << CAN_F9R1_FB19_Pos)       /*!< 0x00080000 */
7215 #define CAN_F9R1_FB19                        CAN_F9R1_FB19_Msk                 /*!< Filter bit 19 */
7216 #define CAN_F9R1_FB20_Pos                    (20U)
7217 #define CAN_F9R1_FB20_Msk                    (0x1UL << CAN_F9R1_FB20_Pos)       /*!< 0x00100000 */
7218 #define CAN_F9R1_FB20                        CAN_F9R1_FB20_Msk                 /*!< Filter bit 20 */
7219 #define CAN_F9R1_FB21_Pos                    (21U)
7220 #define CAN_F9R1_FB21_Msk                    (0x1UL << CAN_F9R1_FB21_Pos)       /*!< 0x00200000 */
7221 #define CAN_F9R1_FB21                        CAN_F9R1_FB21_Msk                 /*!< Filter bit 21 */
7222 #define CAN_F9R1_FB22_Pos                    (22U)
7223 #define CAN_F9R1_FB22_Msk                    (0x1UL << CAN_F9R1_FB22_Pos)       /*!< 0x00400000 */
7224 #define CAN_F9R1_FB22                        CAN_F9R1_FB22_Msk                 /*!< Filter bit 22 */
7225 #define CAN_F9R1_FB23_Pos                    (23U)
7226 #define CAN_F9R1_FB23_Msk                    (0x1UL << CAN_F9R1_FB23_Pos)       /*!< 0x00800000 */
7227 #define CAN_F9R1_FB23                        CAN_F9R1_FB23_Msk                 /*!< Filter bit 23 */
7228 #define CAN_F9R1_FB24_Pos                    (24U)
7229 #define CAN_F9R1_FB24_Msk                    (0x1UL << CAN_F9R1_FB24_Pos)       /*!< 0x01000000 */
7230 #define CAN_F9R1_FB24                        CAN_F9R1_FB24_Msk                 /*!< Filter bit 24 */
7231 #define CAN_F9R1_FB25_Pos                    (25U)
7232 #define CAN_F9R1_FB25_Msk                    (0x1UL << CAN_F9R1_FB25_Pos)       /*!< 0x02000000 */
7233 #define CAN_F9R1_FB25                        CAN_F9R1_FB25_Msk                 /*!< Filter bit 25 */
7234 #define CAN_F9R1_FB26_Pos                    (26U)
7235 #define CAN_F9R1_FB26_Msk                    (0x1UL << CAN_F9R1_FB26_Pos)       /*!< 0x04000000 */
7236 #define CAN_F9R1_FB26                        CAN_F9R1_FB26_Msk                 /*!< Filter bit 26 */
7237 #define CAN_F9R1_FB27_Pos                    (27U)
7238 #define CAN_F9R1_FB27_Msk                    (0x1UL << CAN_F9R1_FB27_Pos)       /*!< 0x08000000 */
7239 #define CAN_F9R1_FB27                        CAN_F9R1_FB27_Msk                 /*!< Filter bit 27 */
7240 #define CAN_F9R1_FB28_Pos                    (28U)
7241 #define CAN_F9R1_FB28_Msk                    (0x1UL << CAN_F9R1_FB28_Pos)       /*!< 0x10000000 */
7242 #define CAN_F9R1_FB28                        CAN_F9R1_FB28_Msk                 /*!< Filter bit 28 */
7243 #define CAN_F9R1_FB29_Pos                    (29U)
7244 #define CAN_F9R1_FB29_Msk                    (0x1UL << CAN_F9R1_FB29_Pos)       /*!< 0x20000000 */
7245 #define CAN_F9R1_FB29                        CAN_F9R1_FB29_Msk                 /*!< Filter bit 29 */
7246 #define CAN_F9R1_FB30_Pos                    (30U)
7247 #define CAN_F9R1_FB30_Msk                    (0x1UL << CAN_F9R1_FB30_Pos)       /*!< 0x40000000 */
7248 #define CAN_F9R1_FB30                        CAN_F9R1_FB30_Msk                 /*!< Filter bit 30 */
7249 #define CAN_F9R1_FB31_Pos                    (31U)
7250 #define CAN_F9R1_FB31_Msk                    (0x1UL << CAN_F9R1_FB31_Pos)       /*!< 0x80000000 */
7251 #define CAN_F9R1_FB31                        CAN_F9R1_FB31_Msk                 /*!< Filter bit 31 */
7252 
7253 /*******************  Bit definition for CAN_F10R1 register  ******************/
7254 #define CAN_F10R1_FB0_Pos                    (0U)
7255 #define CAN_F10R1_FB0_Msk                    (0x1UL << CAN_F10R1_FB0_Pos)       /*!< 0x00000001 */
7256 #define CAN_F10R1_FB0                        CAN_F10R1_FB0_Msk                 /*!< Filter bit 0 */
7257 #define CAN_F10R1_FB1_Pos                    (1U)
7258 #define CAN_F10R1_FB1_Msk                    (0x1UL << CAN_F10R1_FB1_Pos)       /*!< 0x00000002 */
7259 #define CAN_F10R1_FB1                        CAN_F10R1_FB1_Msk                 /*!< Filter bit 1 */
7260 #define CAN_F10R1_FB2_Pos                    (2U)
7261 #define CAN_F10R1_FB2_Msk                    (0x1UL << CAN_F10R1_FB2_Pos)       /*!< 0x00000004 */
7262 #define CAN_F10R1_FB2                        CAN_F10R1_FB2_Msk                 /*!< Filter bit 2 */
7263 #define CAN_F10R1_FB3_Pos                    (3U)
7264 #define CAN_F10R1_FB3_Msk                    (0x1UL << CAN_F10R1_FB3_Pos)       /*!< 0x00000008 */
7265 #define CAN_F10R1_FB3                        CAN_F10R1_FB3_Msk                 /*!< Filter bit 3 */
7266 #define CAN_F10R1_FB4_Pos                    (4U)
7267 #define CAN_F10R1_FB4_Msk                    (0x1UL << CAN_F10R1_FB4_Pos)       /*!< 0x00000010 */
7268 #define CAN_F10R1_FB4                        CAN_F10R1_FB4_Msk                 /*!< Filter bit 4 */
7269 #define CAN_F10R1_FB5_Pos                    (5U)
7270 #define CAN_F10R1_FB5_Msk                    (0x1UL << CAN_F10R1_FB5_Pos)       /*!< 0x00000020 */
7271 #define CAN_F10R1_FB5                        CAN_F10R1_FB5_Msk                 /*!< Filter bit 5 */
7272 #define CAN_F10R1_FB6_Pos                    (6U)
7273 #define CAN_F10R1_FB6_Msk                    (0x1UL << CAN_F10R1_FB6_Pos)       /*!< 0x00000040 */
7274 #define CAN_F10R1_FB6                        CAN_F10R1_FB6_Msk                 /*!< Filter bit 6 */
7275 #define CAN_F10R1_FB7_Pos                    (7U)
7276 #define CAN_F10R1_FB7_Msk                    (0x1UL << CAN_F10R1_FB7_Pos)       /*!< 0x00000080 */
7277 #define CAN_F10R1_FB7                        CAN_F10R1_FB7_Msk                 /*!< Filter bit 7 */
7278 #define CAN_F10R1_FB8_Pos                    (8U)
7279 #define CAN_F10R1_FB8_Msk                    (0x1UL << CAN_F10R1_FB8_Pos)       /*!< 0x00000100 */
7280 #define CAN_F10R1_FB8                        CAN_F10R1_FB8_Msk                 /*!< Filter bit 8 */
7281 #define CAN_F10R1_FB9_Pos                    (9U)
7282 #define CAN_F10R1_FB9_Msk                    (0x1UL << CAN_F10R1_FB9_Pos)       /*!< 0x00000200 */
7283 #define CAN_F10R1_FB9                        CAN_F10R1_FB9_Msk                 /*!< Filter bit 9 */
7284 #define CAN_F10R1_FB10_Pos                   (10U)
7285 #define CAN_F10R1_FB10_Msk                   (0x1UL << CAN_F10R1_FB10_Pos)      /*!< 0x00000400 */
7286 #define CAN_F10R1_FB10                       CAN_F10R1_FB10_Msk                /*!< Filter bit 10 */
7287 #define CAN_F10R1_FB11_Pos                   (11U)
7288 #define CAN_F10R1_FB11_Msk                   (0x1UL << CAN_F10R1_FB11_Pos)      /*!< 0x00000800 */
7289 #define CAN_F10R1_FB11                       CAN_F10R1_FB11_Msk                /*!< Filter bit 11 */
7290 #define CAN_F10R1_FB12_Pos                   (12U)
7291 #define CAN_F10R1_FB12_Msk                   (0x1UL << CAN_F10R1_FB12_Pos)      /*!< 0x00001000 */
7292 #define CAN_F10R1_FB12                       CAN_F10R1_FB12_Msk                /*!< Filter bit 12 */
7293 #define CAN_F10R1_FB13_Pos                   (13U)
7294 #define CAN_F10R1_FB13_Msk                   (0x1UL << CAN_F10R1_FB13_Pos)      /*!< 0x00002000 */
7295 #define CAN_F10R1_FB13                       CAN_F10R1_FB13_Msk                /*!< Filter bit 13 */
7296 #define CAN_F10R1_FB14_Pos                   (14U)
7297 #define CAN_F10R1_FB14_Msk                   (0x1UL << CAN_F10R1_FB14_Pos)      /*!< 0x00004000 */
7298 #define CAN_F10R1_FB14                       CAN_F10R1_FB14_Msk                /*!< Filter bit 14 */
7299 #define CAN_F10R1_FB15_Pos                   (15U)
7300 #define CAN_F10R1_FB15_Msk                   (0x1UL << CAN_F10R1_FB15_Pos)      /*!< 0x00008000 */
7301 #define CAN_F10R1_FB15                       CAN_F10R1_FB15_Msk                /*!< Filter bit 15 */
7302 #define CAN_F10R1_FB16_Pos                   (16U)
7303 #define CAN_F10R1_FB16_Msk                   (0x1UL << CAN_F10R1_FB16_Pos)      /*!< 0x00010000 */
7304 #define CAN_F10R1_FB16                       CAN_F10R1_FB16_Msk                /*!< Filter bit 16 */
7305 #define CAN_F10R1_FB17_Pos                   (17U)
7306 #define CAN_F10R1_FB17_Msk                   (0x1UL << CAN_F10R1_FB17_Pos)      /*!< 0x00020000 */
7307 #define CAN_F10R1_FB17                       CAN_F10R1_FB17_Msk                /*!< Filter bit 17 */
7308 #define CAN_F10R1_FB18_Pos                   (18U)
7309 #define CAN_F10R1_FB18_Msk                   (0x1UL << CAN_F10R1_FB18_Pos)      /*!< 0x00040000 */
7310 #define CAN_F10R1_FB18                       CAN_F10R1_FB18_Msk                /*!< Filter bit 18 */
7311 #define CAN_F10R1_FB19_Pos                   (19U)
7312 #define CAN_F10R1_FB19_Msk                   (0x1UL << CAN_F10R1_FB19_Pos)      /*!< 0x00080000 */
7313 #define CAN_F10R1_FB19                       CAN_F10R1_FB19_Msk                /*!< Filter bit 19 */
7314 #define CAN_F10R1_FB20_Pos                   (20U)
7315 #define CAN_F10R1_FB20_Msk                   (0x1UL << CAN_F10R1_FB20_Pos)      /*!< 0x00100000 */
7316 #define CAN_F10R1_FB20                       CAN_F10R1_FB20_Msk                /*!< Filter bit 20 */
7317 #define CAN_F10R1_FB21_Pos                   (21U)
7318 #define CAN_F10R1_FB21_Msk                   (0x1UL << CAN_F10R1_FB21_Pos)      /*!< 0x00200000 */
7319 #define CAN_F10R1_FB21                       CAN_F10R1_FB21_Msk                /*!< Filter bit 21 */
7320 #define CAN_F10R1_FB22_Pos                   (22U)
7321 #define CAN_F10R1_FB22_Msk                   (0x1UL << CAN_F10R1_FB22_Pos)      /*!< 0x00400000 */
7322 #define CAN_F10R1_FB22                       CAN_F10R1_FB22_Msk                /*!< Filter bit 22 */
7323 #define CAN_F10R1_FB23_Pos                   (23U)
7324 #define CAN_F10R1_FB23_Msk                   (0x1UL << CAN_F10R1_FB23_Pos)      /*!< 0x00800000 */
7325 #define CAN_F10R1_FB23                       CAN_F10R1_FB23_Msk                /*!< Filter bit 23 */
7326 #define CAN_F10R1_FB24_Pos                   (24U)
7327 #define CAN_F10R1_FB24_Msk                   (0x1UL << CAN_F10R1_FB24_Pos)      /*!< 0x01000000 */
7328 #define CAN_F10R1_FB24                       CAN_F10R1_FB24_Msk                /*!< Filter bit 24 */
7329 #define CAN_F10R1_FB25_Pos                   (25U)
7330 #define CAN_F10R1_FB25_Msk                   (0x1UL << CAN_F10R1_FB25_Pos)      /*!< 0x02000000 */
7331 #define CAN_F10R1_FB25                       CAN_F10R1_FB25_Msk                /*!< Filter bit 25 */
7332 #define CAN_F10R1_FB26_Pos                   (26U)
7333 #define CAN_F10R1_FB26_Msk                   (0x1UL << CAN_F10R1_FB26_Pos)      /*!< 0x04000000 */
7334 #define CAN_F10R1_FB26                       CAN_F10R1_FB26_Msk                /*!< Filter bit 26 */
7335 #define CAN_F10R1_FB27_Pos                   (27U)
7336 #define CAN_F10R1_FB27_Msk                   (0x1UL << CAN_F10R1_FB27_Pos)      /*!< 0x08000000 */
7337 #define CAN_F10R1_FB27                       CAN_F10R1_FB27_Msk                /*!< Filter bit 27 */
7338 #define CAN_F10R1_FB28_Pos                   (28U)
7339 #define CAN_F10R1_FB28_Msk                   (0x1UL << CAN_F10R1_FB28_Pos)      /*!< 0x10000000 */
7340 #define CAN_F10R1_FB28                       CAN_F10R1_FB28_Msk                /*!< Filter bit 28 */
7341 #define CAN_F10R1_FB29_Pos                   (29U)
7342 #define CAN_F10R1_FB29_Msk                   (0x1UL << CAN_F10R1_FB29_Pos)      /*!< 0x20000000 */
7343 #define CAN_F10R1_FB29                       CAN_F10R1_FB29_Msk                /*!< Filter bit 29 */
7344 #define CAN_F10R1_FB30_Pos                   (30U)
7345 #define CAN_F10R1_FB30_Msk                   (0x1UL << CAN_F10R1_FB30_Pos)      /*!< 0x40000000 */
7346 #define CAN_F10R1_FB30                       CAN_F10R1_FB30_Msk                /*!< Filter bit 30 */
7347 #define CAN_F10R1_FB31_Pos                   (31U)
7348 #define CAN_F10R1_FB31_Msk                   (0x1UL << CAN_F10R1_FB31_Pos)      /*!< 0x80000000 */
7349 #define CAN_F10R1_FB31                       CAN_F10R1_FB31_Msk                /*!< Filter bit 31 */
7350 
7351 /*******************  Bit definition for CAN_F11R1 register  ******************/
7352 #define CAN_F11R1_FB0_Pos                    (0U)
7353 #define CAN_F11R1_FB0_Msk                    (0x1UL << CAN_F11R1_FB0_Pos)       /*!< 0x00000001 */
7354 #define CAN_F11R1_FB0                        CAN_F11R1_FB0_Msk                 /*!< Filter bit 0 */
7355 #define CAN_F11R1_FB1_Pos                    (1U)
7356 #define CAN_F11R1_FB1_Msk                    (0x1UL << CAN_F11R1_FB1_Pos)       /*!< 0x00000002 */
7357 #define CAN_F11R1_FB1                        CAN_F11R1_FB1_Msk                 /*!< Filter bit 1 */
7358 #define CAN_F11R1_FB2_Pos                    (2U)
7359 #define CAN_F11R1_FB2_Msk                    (0x1UL << CAN_F11R1_FB2_Pos)       /*!< 0x00000004 */
7360 #define CAN_F11R1_FB2                        CAN_F11R1_FB2_Msk                 /*!< Filter bit 2 */
7361 #define CAN_F11R1_FB3_Pos                    (3U)
7362 #define CAN_F11R1_FB3_Msk                    (0x1UL << CAN_F11R1_FB3_Pos)       /*!< 0x00000008 */
7363 #define CAN_F11R1_FB3                        CAN_F11R1_FB3_Msk                 /*!< Filter bit 3 */
7364 #define CAN_F11R1_FB4_Pos                    (4U)
7365 #define CAN_F11R1_FB4_Msk                    (0x1UL << CAN_F11R1_FB4_Pos)       /*!< 0x00000010 */
7366 #define CAN_F11R1_FB4                        CAN_F11R1_FB4_Msk                 /*!< Filter bit 4 */
7367 #define CAN_F11R1_FB5_Pos                    (5U)
7368 #define CAN_F11R1_FB5_Msk                    (0x1UL << CAN_F11R1_FB5_Pos)       /*!< 0x00000020 */
7369 #define CAN_F11R1_FB5                        CAN_F11R1_FB5_Msk                 /*!< Filter bit 5 */
7370 #define CAN_F11R1_FB6_Pos                    (6U)
7371 #define CAN_F11R1_FB6_Msk                    (0x1UL << CAN_F11R1_FB6_Pos)       /*!< 0x00000040 */
7372 #define CAN_F11R1_FB6                        CAN_F11R1_FB6_Msk                 /*!< Filter bit 6 */
7373 #define CAN_F11R1_FB7_Pos                    (7U)
7374 #define CAN_F11R1_FB7_Msk                    (0x1UL << CAN_F11R1_FB7_Pos)       /*!< 0x00000080 */
7375 #define CAN_F11R1_FB7                        CAN_F11R1_FB7_Msk                 /*!< Filter bit 7 */
7376 #define CAN_F11R1_FB8_Pos                    (8U)
7377 #define CAN_F11R1_FB8_Msk                    (0x1UL << CAN_F11R1_FB8_Pos)       /*!< 0x00000100 */
7378 #define CAN_F11R1_FB8                        CAN_F11R1_FB8_Msk                 /*!< Filter bit 8 */
7379 #define CAN_F11R1_FB9_Pos                    (9U)
7380 #define CAN_F11R1_FB9_Msk                    (0x1UL << CAN_F11R1_FB9_Pos)       /*!< 0x00000200 */
7381 #define CAN_F11R1_FB9                        CAN_F11R1_FB9_Msk                 /*!< Filter bit 9 */
7382 #define CAN_F11R1_FB10_Pos                   (10U)
7383 #define CAN_F11R1_FB10_Msk                   (0x1UL << CAN_F11R1_FB10_Pos)      /*!< 0x00000400 */
7384 #define CAN_F11R1_FB10                       CAN_F11R1_FB10_Msk                /*!< Filter bit 10 */
7385 #define CAN_F11R1_FB11_Pos                   (11U)
7386 #define CAN_F11R1_FB11_Msk                   (0x1UL << CAN_F11R1_FB11_Pos)      /*!< 0x00000800 */
7387 #define CAN_F11R1_FB11                       CAN_F11R1_FB11_Msk                /*!< Filter bit 11 */
7388 #define CAN_F11R1_FB12_Pos                   (12U)
7389 #define CAN_F11R1_FB12_Msk                   (0x1UL << CAN_F11R1_FB12_Pos)      /*!< 0x00001000 */
7390 #define CAN_F11R1_FB12                       CAN_F11R1_FB12_Msk                /*!< Filter bit 12 */
7391 #define CAN_F11R1_FB13_Pos                   (13U)
7392 #define CAN_F11R1_FB13_Msk                   (0x1UL << CAN_F11R1_FB13_Pos)      /*!< 0x00002000 */
7393 #define CAN_F11R1_FB13                       CAN_F11R1_FB13_Msk                /*!< Filter bit 13 */
7394 #define CAN_F11R1_FB14_Pos                   (14U)
7395 #define CAN_F11R1_FB14_Msk                   (0x1UL << CAN_F11R1_FB14_Pos)      /*!< 0x00004000 */
7396 #define CAN_F11R1_FB14                       CAN_F11R1_FB14_Msk                /*!< Filter bit 14 */
7397 #define CAN_F11R1_FB15_Pos                   (15U)
7398 #define CAN_F11R1_FB15_Msk                   (0x1UL << CAN_F11R1_FB15_Pos)      /*!< 0x00008000 */
7399 #define CAN_F11R1_FB15                       CAN_F11R1_FB15_Msk                /*!< Filter bit 15 */
7400 #define CAN_F11R1_FB16_Pos                   (16U)
7401 #define CAN_F11R1_FB16_Msk                   (0x1UL << CAN_F11R1_FB16_Pos)      /*!< 0x00010000 */
7402 #define CAN_F11R1_FB16                       CAN_F11R1_FB16_Msk                /*!< Filter bit 16 */
7403 #define CAN_F11R1_FB17_Pos                   (17U)
7404 #define CAN_F11R1_FB17_Msk                   (0x1UL << CAN_F11R1_FB17_Pos)      /*!< 0x00020000 */
7405 #define CAN_F11R1_FB17                       CAN_F11R1_FB17_Msk                /*!< Filter bit 17 */
7406 #define CAN_F11R1_FB18_Pos                   (18U)
7407 #define CAN_F11R1_FB18_Msk                   (0x1UL << CAN_F11R1_FB18_Pos)      /*!< 0x00040000 */
7408 #define CAN_F11R1_FB18                       CAN_F11R1_FB18_Msk                /*!< Filter bit 18 */
7409 #define CAN_F11R1_FB19_Pos                   (19U)
7410 #define CAN_F11R1_FB19_Msk                   (0x1UL << CAN_F11R1_FB19_Pos)      /*!< 0x00080000 */
7411 #define CAN_F11R1_FB19                       CAN_F11R1_FB19_Msk                /*!< Filter bit 19 */
7412 #define CAN_F11R1_FB20_Pos                   (20U)
7413 #define CAN_F11R1_FB20_Msk                   (0x1UL << CAN_F11R1_FB20_Pos)      /*!< 0x00100000 */
7414 #define CAN_F11R1_FB20                       CAN_F11R1_FB20_Msk                /*!< Filter bit 20 */
7415 #define CAN_F11R1_FB21_Pos                   (21U)
7416 #define CAN_F11R1_FB21_Msk                   (0x1UL << CAN_F11R1_FB21_Pos)      /*!< 0x00200000 */
7417 #define CAN_F11R1_FB21                       CAN_F11R1_FB21_Msk                /*!< Filter bit 21 */
7418 #define CAN_F11R1_FB22_Pos                   (22U)
7419 #define CAN_F11R1_FB22_Msk                   (0x1UL << CAN_F11R1_FB22_Pos)      /*!< 0x00400000 */
7420 #define CAN_F11R1_FB22                       CAN_F11R1_FB22_Msk                /*!< Filter bit 22 */
7421 #define CAN_F11R1_FB23_Pos                   (23U)
7422 #define CAN_F11R1_FB23_Msk                   (0x1UL << CAN_F11R1_FB23_Pos)      /*!< 0x00800000 */
7423 #define CAN_F11R1_FB23                       CAN_F11R1_FB23_Msk                /*!< Filter bit 23 */
7424 #define CAN_F11R1_FB24_Pos                   (24U)
7425 #define CAN_F11R1_FB24_Msk                   (0x1UL << CAN_F11R1_FB24_Pos)      /*!< 0x01000000 */
7426 #define CAN_F11R1_FB24                       CAN_F11R1_FB24_Msk                /*!< Filter bit 24 */
7427 #define CAN_F11R1_FB25_Pos                   (25U)
7428 #define CAN_F11R1_FB25_Msk                   (0x1UL << CAN_F11R1_FB25_Pos)      /*!< 0x02000000 */
7429 #define CAN_F11R1_FB25                       CAN_F11R1_FB25_Msk                /*!< Filter bit 25 */
7430 #define CAN_F11R1_FB26_Pos                   (26U)
7431 #define CAN_F11R1_FB26_Msk                   (0x1UL << CAN_F11R1_FB26_Pos)      /*!< 0x04000000 */
7432 #define CAN_F11R1_FB26                       CAN_F11R1_FB26_Msk                /*!< Filter bit 26 */
7433 #define CAN_F11R1_FB27_Pos                   (27U)
7434 #define CAN_F11R1_FB27_Msk                   (0x1UL << CAN_F11R1_FB27_Pos)      /*!< 0x08000000 */
7435 #define CAN_F11R1_FB27                       CAN_F11R1_FB27_Msk                /*!< Filter bit 27 */
7436 #define CAN_F11R1_FB28_Pos                   (28U)
7437 #define CAN_F11R1_FB28_Msk                   (0x1UL << CAN_F11R1_FB28_Pos)      /*!< 0x10000000 */
7438 #define CAN_F11R1_FB28                       CAN_F11R1_FB28_Msk                /*!< Filter bit 28 */
7439 #define CAN_F11R1_FB29_Pos                   (29U)
7440 #define CAN_F11R1_FB29_Msk                   (0x1UL << CAN_F11R1_FB29_Pos)      /*!< 0x20000000 */
7441 #define CAN_F11R1_FB29                       CAN_F11R1_FB29_Msk                /*!< Filter bit 29 */
7442 #define CAN_F11R1_FB30_Pos                   (30U)
7443 #define CAN_F11R1_FB30_Msk                   (0x1UL << CAN_F11R1_FB30_Pos)      /*!< 0x40000000 */
7444 #define CAN_F11R1_FB30                       CAN_F11R1_FB30_Msk                /*!< Filter bit 30 */
7445 #define CAN_F11R1_FB31_Pos                   (31U)
7446 #define CAN_F11R1_FB31_Msk                   (0x1UL << CAN_F11R1_FB31_Pos)      /*!< 0x80000000 */
7447 #define CAN_F11R1_FB31                       CAN_F11R1_FB31_Msk                /*!< Filter bit 31 */
7448 
7449 /*******************  Bit definition for CAN_F12R1 register  ******************/
7450 #define CAN_F12R1_FB0_Pos                    (0U)
7451 #define CAN_F12R1_FB0_Msk                    (0x1UL << CAN_F12R1_FB0_Pos)       /*!< 0x00000001 */
7452 #define CAN_F12R1_FB0                        CAN_F12R1_FB0_Msk                 /*!< Filter bit 0 */
7453 #define CAN_F12R1_FB1_Pos                    (1U)
7454 #define CAN_F12R1_FB1_Msk                    (0x1UL << CAN_F12R1_FB1_Pos)       /*!< 0x00000002 */
7455 #define CAN_F12R1_FB1                        CAN_F12R1_FB1_Msk                 /*!< Filter bit 1 */
7456 #define CAN_F12R1_FB2_Pos                    (2U)
7457 #define CAN_F12R1_FB2_Msk                    (0x1UL << CAN_F12R1_FB2_Pos)       /*!< 0x00000004 */
7458 #define CAN_F12R1_FB2                        CAN_F12R1_FB2_Msk                 /*!< Filter bit 2 */
7459 #define CAN_F12R1_FB3_Pos                    (3U)
7460 #define CAN_F12R1_FB3_Msk                    (0x1UL << CAN_F12R1_FB3_Pos)       /*!< 0x00000008 */
7461 #define CAN_F12R1_FB3                        CAN_F12R1_FB3_Msk                 /*!< Filter bit 3 */
7462 #define CAN_F12R1_FB4_Pos                    (4U)
7463 #define CAN_F12R1_FB4_Msk                    (0x1UL << CAN_F12R1_FB4_Pos)       /*!< 0x00000010 */
7464 #define CAN_F12R1_FB4                        CAN_F12R1_FB4_Msk                 /*!< Filter bit 4 */
7465 #define CAN_F12R1_FB5_Pos                    (5U)
7466 #define CAN_F12R1_FB5_Msk                    (0x1UL << CAN_F12R1_FB5_Pos)       /*!< 0x00000020 */
7467 #define CAN_F12R1_FB5                        CAN_F12R1_FB5_Msk                 /*!< Filter bit 5 */
7468 #define CAN_F12R1_FB6_Pos                    (6U)
7469 #define CAN_F12R1_FB6_Msk                    (0x1UL << CAN_F12R1_FB6_Pos)       /*!< 0x00000040 */
7470 #define CAN_F12R1_FB6                        CAN_F12R1_FB6_Msk                 /*!< Filter bit 6 */
7471 #define CAN_F12R1_FB7_Pos                    (7U)
7472 #define CAN_F12R1_FB7_Msk                    (0x1UL << CAN_F12R1_FB7_Pos)       /*!< 0x00000080 */
7473 #define CAN_F12R1_FB7                        CAN_F12R1_FB7_Msk                 /*!< Filter bit 7 */
7474 #define CAN_F12R1_FB8_Pos                    (8U)
7475 #define CAN_F12R1_FB8_Msk                    (0x1UL << CAN_F12R1_FB8_Pos)       /*!< 0x00000100 */
7476 #define CAN_F12R1_FB8                        CAN_F12R1_FB8_Msk                 /*!< Filter bit 8 */
7477 #define CAN_F12R1_FB9_Pos                    (9U)
7478 #define CAN_F12R1_FB9_Msk                    (0x1UL << CAN_F12R1_FB9_Pos)       /*!< 0x00000200 */
7479 #define CAN_F12R1_FB9                        CAN_F12R1_FB9_Msk                 /*!< Filter bit 9 */
7480 #define CAN_F12R1_FB10_Pos                   (10U)
7481 #define CAN_F12R1_FB10_Msk                   (0x1UL << CAN_F12R1_FB10_Pos)      /*!< 0x00000400 */
7482 #define CAN_F12R1_FB10                       CAN_F12R1_FB10_Msk                /*!< Filter bit 10 */
7483 #define CAN_F12R1_FB11_Pos                   (11U)
7484 #define CAN_F12R1_FB11_Msk                   (0x1UL << CAN_F12R1_FB11_Pos)      /*!< 0x00000800 */
7485 #define CAN_F12R1_FB11                       CAN_F12R1_FB11_Msk                /*!< Filter bit 11 */
7486 #define CAN_F12R1_FB12_Pos                   (12U)
7487 #define CAN_F12R1_FB12_Msk                   (0x1UL << CAN_F12R1_FB12_Pos)      /*!< 0x00001000 */
7488 #define CAN_F12R1_FB12                       CAN_F12R1_FB12_Msk                /*!< Filter bit 12 */
7489 #define CAN_F12R1_FB13_Pos                   (13U)
7490 #define CAN_F12R1_FB13_Msk                   (0x1UL << CAN_F12R1_FB13_Pos)      /*!< 0x00002000 */
7491 #define CAN_F12R1_FB13                       CAN_F12R1_FB13_Msk                /*!< Filter bit 13 */
7492 #define CAN_F12R1_FB14_Pos                   (14U)
7493 #define CAN_F12R1_FB14_Msk                   (0x1UL << CAN_F12R1_FB14_Pos)      /*!< 0x00004000 */
7494 #define CAN_F12R1_FB14                       CAN_F12R1_FB14_Msk                /*!< Filter bit 14 */
7495 #define CAN_F12R1_FB15_Pos                   (15U)
7496 #define CAN_F12R1_FB15_Msk                   (0x1UL << CAN_F12R1_FB15_Pos)      /*!< 0x00008000 */
7497 #define CAN_F12R1_FB15                       CAN_F12R1_FB15_Msk                /*!< Filter bit 15 */
7498 #define CAN_F12R1_FB16_Pos                   (16U)
7499 #define CAN_F12R1_FB16_Msk                   (0x1UL << CAN_F12R1_FB16_Pos)      /*!< 0x00010000 */
7500 #define CAN_F12R1_FB16                       CAN_F12R1_FB16_Msk                /*!< Filter bit 16 */
7501 #define CAN_F12R1_FB17_Pos                   (17U)
7502 #define CAN_F12R1_FB17_Msk                   (0x1UL << CAN_F12R1_FB17_Pos)      /*!< 0x00020000 */
7503 #define CAN_F12R1_FB17                       CAN_F12R1_FB17_Msk                /*!< Filter bit 17 */
7504 #define CAN_F12R1_FB18_Pos                   (18U)
7505 #define CAN_F12R1_FB18_Msk                   (0x1UL << CAN_F12R1_FB18_Pos)      /*!< 0x00040000 */
7506 #define CAN_F12R1_FB18                       CAN_F12R1_FB18_Msk                /*!< Filter bit 18 */
7507 #define CAN_F12R1_FB19_Pos                   (19U)
7508 #define CAN_F12R1_FB19_Msk                   (0x1UL << CAN_F12R1_FB19_Pos)      /*!< 0x00080000 */
7509 #define CAN_F12R1_FB19                       CAN_F12R1_FB19_Msk                /*!< Filter bit 19 */
7510 #define CAN_F12R1_FB20_Pos                   (20U)
7511 #define CAN_F12R1_FB20_Msk                   (0x1UL << CAN_F12R1_FB20_Pos)      /*!< 0x00100000 */
7512 #define CAN_F12R1_FB20                       CAN_F12R1_FB20_Msk                /*!< Filter bit 20 */
7513 #define CAN_F12R1_FB21_Pos                   (21U)
7514 #define CAN_F12R1_FB21_Msk                   (0x1UL << CAN_F12R1_FB21_Pos)      /*!< 0x00200000 */
7515 #define CAN_F12R1_FB21                       CAN_F12R1_FB21_Msk                /*!< Filter bit 21 */
7516 #define CAN_F12R1_FB22_Pos                   (22U)
7517 #define CAN_F12R1_FB22_Msk                   (0x1UL << CAN_F12R1_FB22_Pos)      /*!< 0x00400000 */
7518 #define CAN_F12R1_FB22                       CAN_F12R1_FB22_Msk                /*!< Filter bit 22 */
7519 #define CAN_F12R1_FB23_Pos                   (23U)
7520 #define CAN_F12R1_FB23_Msk                   (0x1UL << CAN_F12R1_FB23_Pos)      /*!< 0x00800000 */
7521 #define CAN_F12R1_FB23                       CAN_F12R1_FB23_Msk                /*!< Filter bit 23 */
7522 #define CAN_F12R1_FB24_Pos                   (24U)
7523 #define CAN_F12R1_FB24_Msk                   (0x1UL << CAN_F12R1_FB24_Pos)      /*!< 0x01000000 */
7524 #define CAN_F12R1_FB24                       CAN_F12R1_FB24_Msk                /*!< Filter bit 24 */
7525 #define CAN_F12R1_FB25_Pos                   (25U)
7526 #define CAN_F12R1_FB25_Msk                   (0x1UL << CAN_F12R1_FB25_Pos)      /*!< 0x02000000 */
7527 #define CAN_F12R1_FB25                       CAN_F12R1_FB25_Msk                /*!< Filter bit 25 */
7528 #define CAN_F12R1_FB26_Pos                   (26U)
7529 #define CAN_F12R1_FB26_Msk                   (0x1UL << CAN_F12R1_FB26_Pos)      /*!< 0x04000000 */
7530 #define CAN_F12R1_FB26                       CAN_F12R1_FB26_Msk                /*!< Filter bit 26 */
7531 #define CAN_F12R1_FB27_Pos                   (27U)
7532 #define CAN_F12R1_FB27_Msk                   (0x1UL << CAN_F12R1_FB27_Pos)      /*!< 0x08000000 */
7533 #define CAN_F12R1_FB27                       CAN_F12R1_FB27_Msk                /*!< Filter bit 27 */
7534 #define CAN_F12R1_FB28_Pos                   (28U)
7535 #define CAN_F12R1_FB28_Msk                   (0x1UL << CAN_F12R1_FB28_Pos)      /*!< 0x10000000 */
7536 #define CAN_F12R1_FB28                       CAN_F12R1_FB28_Msk                /*!< Filter bit 28 */
7537 #define CAN_F12R1_FB29_Pos                   (29U)
7538 #define CAN_F12R1_FB29_Msk                   (0x1UL << CAN_F12R1_FB29_Pos)      /*!< 0x20000000 */
7539 #define CAN_F12R1_FB29                       CAN_F12R1_FB29_Msk                /*!< Filter bit 29 */
7540 #define CAN_F12R1_FB30_Pos                   (30U)
7541 #define CAN_F12R1_FB30_Msk                   (0x1UL << CAN_F12R1_FB30_Pos)      /*!< 0x40000000 */
7542 #define CAN_F12R1_FB30                       CAN_F12R1_FB30_Msk                /*!< Filter bit 30 */
7543 #define CAN_F12R1_FB31_Pos                   (31U)
7544 #define CAN_F12R1_FB31_Msk                   (0x1UL << CAN_F12R1_FB31_Pos)      /*!< 0x80000000 */
7545 #define CAN_F12R1_FB31                       CAN_F12R1_FB31_Msk                /*!< Filter bit 31 */
7546 
7547 /*******************  Bit definition for CAN_F13R1 register  ******************/
7548 #define CAN_F13R1_FB0_Pos                    (0U)
7549 #define CAN_F13R1_FB0_Msk                    (0x1UL << CAN_F13R1_FB0_Pos)       /*!< 0x00000001 */
7550 #define CAN_F13R1_FB0                        CAN_F13R1_FB0_Msk                 /*!< Filter bit 0 */
7551 #define CAN_F13R1_FB1_Pos                    (1U)
7552 #define CAN_F13R1_FB1_Msk                    (0x1UL << CAN_F13R1_FB1_Pos)       /*!< 0x00000002 */
7553 #define CAN_F13R1_FB1                        CAN_F13R1_FB1_Msk                 /*!< Filter bit 1 */
7554 #define CAN_F13R1_FB2_Pos                    (2U)
7555 #define CAN_F13R1_FB2_Msk                    (0x1UL << CAN_F13R1_FB2_Pos)       /*!< 0x00000004 */
7556 #define CAN_F13R1_FB2                        CAN_F13R1_FB2_Msk                 /*!< Filter bit 2 */
7557 #define CAN_F13R1_FB3_Pos                    (3U)
7558 #define CAN_F13R1_FB3_Msk                    (0x1UL << CAN_F13R1_FB3_Pos)       /*!< 0x00000008 */
7559 #define CAN_F13R1_FB3                        CAN_F13R1_FB3_Msk                 /*!< Filter bit 3 */
7560 #define CAN_F13R1_FB4_Pos                    (4U)
7561 #define CAN_F13R1_FB4_Msk                    (0x1UL << CAN_F13R1_FB4_Pos)       /*!< 0x00000010 */
7562 #define CAN_F13R1_FB4                        CAN_F13R1_FB4_Msk                 /*!< Filter bit 4 */
7563 #define CAN_F13R1_FB5_Pos                    (5U)
7564 #define CAN_F13R1_FB5_Msk                    (0x1UL << CAN_F13R1_FB5_Pos)       /*!< 0x00000020 */
7565 #define CAN_F13R1_FB5                        CAN_F13R1_FB5_Msk                 /*!< Filter bit 5 */
7566 #define CAN_F13R1_FB6_Pos                    (6U)
7567 #define CAN_F13R1_FB6_Msk                    (0x1UL << CAN_F13R1_FB6_Pos)       /*!< 0x00000040 */
7568 #define CAN_F13R1_FB6                        CAN_F13R1_FB6_Msk                 /*!< Filter bit 6 */
7569 #define CAN_F13R1_FB7_Pos                    (7U)
7570 #define CAN_F13R1_FB7_Msk                    (0x1UL << CAN_F13R1_FB7_Pos)       /*!< 0x00000080 */
7571 #define CAN_F13R1_FB7                        CAN_F13R1_FB7_Msk                 /*!< Filter bit 7 */
7572 #define CAN_F13R1_FB8_Pos                    (8U)
7573 #define CAN_F13R1_FB8_Msk                    (0x1UL << CAN_F13R1_FB8_Pos)       /*!< 0x00000100 */
7574 #define CAN_F13R1_FB8                        CAN_F13R1_FB8_Msk                 /*!< Filter bit 8 */
7575 #define CAN_F13R1_FB9_Pos                    (9U)
7576 #define CAN_F13R1_FB9_Msk                    (0x1UL << CAN_F13R1_FB9_Pos)       /*!< 0x00000200 */
7577 #define CAN_F13R1_FB9                        CAN_F13R1_FB9_Msk                 /*!< Filter bit 9 */
7578 #define CAN_F13R1_FB10_Pos                   (10U)
7579 #define CAN_F13R1_FB10_Msk                   (0x1UL << CAN_F13R1_FB10_Pos)      /*!< 0x00000400 */
7580 #define CAN_F13R1_FB10                       CAN_F13R1_FB10_Msk                /*!< Filter bit 10 */
7581 #define CAN_F13R1_FB11_Pos                   (11U)
7582 #define CAN_F13R1_FB11_Msk                   (0x1UL << CAN_F13R1_FB11_Pos)      /*!< 0x00000800 */
7583 #define CAN_F13R1_FB11                       CAN_F13R1_FB11_Msk                /*!< Filter bit 11 */
7584 #define CAN_F13R1_FB12_Pos                   (12U)
7585 #define CAN_F13R1_FB12_Msk                   (0x1UL << CAN_F13R1_FB12_Pos)      /*!< 0x00001000 */
7586 #define CAN_F13R1_FB12                       CAN_F13R1_FB12_Msk                /*!< Filter bit 12 */
7587 #define CAN_F13R1_FB13_Pos                   (13U)
7588 #define CAN_F13R1_FB13_Msk                   (0x1UL << CAN_F13R1_FB13_Pos)      /*!< 0x00002000 */
7589 #define CAN_F13R1_FB13                       CAN_F13R1_FB13_Msk                /*!< Filter bit 13 */
7590 #define CAN_F13R1_FB14_Pos                   (14U)
7591 #define CAN_F13R1_FB14_Msk                   (0x1UL << CAN_F13R1_FB14_Pos)      /*!< 0x00004000 */
7592 #define CAN_F13R1_FB14                       CAN_F13R1_FB14_Msk                /*!< Filter bit 14 */
7593 #define CAN_F13R1_FB15_Pos                   (15U)
7594 #define CAN_F13R1_FB15_Msk                   (0x1UL << CAN_F13R1_FB15_Pos)      /*!< 0x00008000 */
7595 #define CAN_F13R1_FB15                       CAN_F13R1_FB15_Msk                /*!< Filter bit 15 */
7596 #define CAN_F13R1_FB16_Pos                   (16U)
7597 #define CAN_F13R1_FB16_Msk                   (0x1UL << CAN_F13R1_FB16_Pos)      /*!< 0x00010000 */
7598 #define CAN_F13R1_FB16                       CAN_F13R1_FB16_Msk                /*!< Filter bit 16 */
7599 #define CAN_F13R1_FB17_Pos                   (17U)
7600 #define CAN_F13R1_FB17_Msk                   (0x1UL << CAN_F13R1_FB17_Pos)      /*!< 0x00020000 */
7601 #define CAN_F13R1_FB17                       CAN_F13R1_FB17_Msk                /*!< Filter bit 17 */
7602 #define CAN_F13R1_FB18_Pos                   (18U)
7603 #define CAN_F13R1_FB18_Msk                   (0x1UL << CAN_F13R1_FB18_Pos)      /*!< 0x00040000 */
7604 #define CAN_F13R1_FB18                       CAN_F13R1_FB18_Msk                /*!< Filter bit 18 */
7605 #define CAN_F13R1_FB19_Pos                   (19U)
7606 #define CAN_F13R1_FB19_Msk                   (0x1UL << CAN_F13R1_FB19_Pos)      /*!< 0x00080000 */
7607 #define CAN_F13R1_FB19                       CAN_F13R1_FB19_Msk                /*!< Filter bit 19 */
7608 #define CAN_F13R1_FB20_Pos                   (20U)
7609 #define CAN_F13R1_FB20_Msk                   (0x1UL << CAN_F13R1_FB20_Pos)      /*!< 0x00100000 */
7610 #define CAN_F13R1_FB20                       CAN_F13R1_FB20_Msk                /*!< Filter bit 20 */
7611 #define CAN_F13R1_FB21_Pos                   (21U)
7612 #define CAN_F13R1_FB21_Msk                   (0x1UL << CAN_F13R1_FB21_Pos)      /*!< 0x00200000 */
7613 #define CAN_F13R1_FB21                       CAN_F13R1_FB21_Msk                /*!< Filter bit 21 */
7614 #define CAN_F13R1_FB22_Pos                   (22U)
7615 #define CAN_F13R1_FB22_Msk                   (0x1UL << CAN_F13R1_FB22_Pos)      /*!< 0x00400000 */
7616 #define CAN_F13R1_FB22                       CAN_F13R1_FB22_Msk                /*!< Filter bit 22 */
7617 #define CAN_F13R1_FB23_Pos                   (23U)
7618 #define CAN_F13R1_FB23_Msk                   (0x1UL << CAN_F13R1_FB23_Pos)      /*!< 0x00800000 */
7619 #define CAN_F13R1_FB23                       CAN_F13R1_FB23_Msk                /*!< Filter bit 23 */
7620 #define CAN_F13R1_FB24_Pos                   (24U)
7621 #define CAN_F13R1_FB24_Msk                   (0x1UL << CAN_F13R1_FB24_Pos)      /*!< 0x01000000 */
7622 #define CAN_F13R1_FB24                       CAN_F13R1_FB24_Msk                /*!< Filter bit 24 */
7623 #define CAN_F13R1_FB25_Pos                   (25U)
7624 #define CAN_F13R1_FB25_Msk                   (0x1UL << CAN_F13R1_FB25_Pos)      /*!< 0x02000000 */
7625 #define CAN_F13R1_FB25                       CAN_F13R1_FB25_Msk                /*!< Filter bit 25 */
7626 #define CAN_F13R1_FB26_Pos                   (26U)
7627 #define CAN_F13R1_FB26_Msk                   (0x1UL << CAN_F13R1_FB26_Pos)      /*!< 0x04000000 */
7628 #define CAN_F13R1_FB26                       CAN_F13R1_FB26_Msk                /*!< Filter bit 26 */
7629 #define CAN_F13R1_FB27_Pos                   (27U)
7630 #define CAN_F13R1_FB27_Msk                   (0x1UL << CAN_F13R1_FB27_Pos)      /*!< 0x08000000 */
7631 #define CAN_F13R1_FB27                       CAN_F13R1_FB27_Msk                /*!< Filter bit 27 */
7632 #define CAN_F13R1_FB28_Pos                   (28U)
7633 #define CAN_F13R1_FB28_Msk                   (0x1UL << CAN_F13R1_FB28_Pos)      /*!< 0x10000000 */
7634 #define CAN_F13R1_FB28                       CAN_F13R1_FB28_Msk                /*!< Filter bit 28 */
7635 #define CAN_F13R1_FB29_Pos                   (29U)
7636 #define CAN_F13R1_FB29_Msk                   (0x1UL << CAN_F13R1_FB29_Pos)      /*!< 0x20000000 */
7637 #define CAN_F13R1_FB29                       CAN_F13R1_FB29_Msk                /*!< Filter bit 29 */
7638 #define CAN_F13R1_FB30_Pos                   (30U)
7639 #define CAN_F13R1_FB30_Msk                   (0x1UL << CAN_F13R1_FB30_Pos)      /*!< 0x40000000 */
7640 #define CAN_F13R1_FB30                       CAN_F13R1_FB30_Msk                /*!< Filter bit 30 */
7641 #define CAN_F13R1_FB31_Pos                   (31U)
7642 #define CAN_F13R1_FB31_Msk                   (0x1UL << CAN_F13R1_FB31_Pos)      /*!< 0x80000000 */
7643 #define CAN_F13R1_FB31                       CAN_F13R1_FB31_Msk                /*!< Filter bit 31 */
7644 
7645 /*******************  Bit definition for CAN_F0R2 register  *******************/
7646 #define CAN_F0R2_FB0_Pos                     (0U)
7647 #define CAN_F0R2_FB0_Msk                     (0x1UL << CAN_F0R2_FB0_Pos)        /*!< 0x00000001 */
7648 #define CAN_F0R2_FB0                         CAN_F0R2_FB0_Msk                  /*!< Filter bit 0 */
7649 #define CAN_F0R2_FB1_Pos                     (1U)
7650 #define CAN_F0R2_FB1_Msk                     (0x1UL << CAN_F0R2_FB1_Pos)        /*!< 0x00000002 */
7651 #define CAN_F0R2_FB1                         CAN_F0R2_FB1_Msk                  /*!< Filter bit 1 */
7652 #define CAN_F0R2_FB2_Pos                     (2U)
7653 #define CAN_F0R2_FB2_Msk                     (0x1UL << CAN_F0R2_FB2_Pos)        /*!< 0x00000004 */
7654 #define CAN_F0R2_FB2                         CAN_F0R2_FB2_Msk                  /*!< Filter bit 2 */
7655 #define CAN_F0R2_FB3_Pos                     (3U)
7656 #define CAN_F0R2_FB3_Msk                     (0x1UL << CAN_F0R2_FB3_Pos)        /*!< 0x00000008 */
7657 #define CAN_F0R2_FB3                         CAN_F0R2_FB3_Msk                  /*!< Filter bit 3 */
7658 #define CAN_F0R2_FB4_Pos                     (4U)
7659 #define CAN_F0R2_FB4_Msk                     (0x1UL << CAN_F0R2_FB4_Pos)        /*!< 0x00000010 */
7660 #define CAN_F0R2_FB4                         CAN_F0R2_FB4_Msk                  /*!< Filter bit 4 */
7661 #define CAN_F0R2_FB5_Pos                     (5U)
7662 #define CAN_F0R2_FB5_Msk                     (0x1UL << CAN_F0R2_FB5_Pos)        /*!< 0x00000020 */
7663 #define CAN_F0R2_FB5                         CAN_F0R2_FB5_Msk                  /*!< Filter bit 5 */
7664 #define CAN_F0R2_FB6_Pos                     (6U)
7665 #define CAN_F0R2_FB6_Msk                     (0x1UL << CAN_F0R2_FB6_Pos)        /*!< 0x00000040 */
7666 #define CAN_F0R2_FB6                         CAN_F0R2_FB6_Msk                  /*!< Filter bit 6 */
7667 #define CAN_F0R2_FB7_Pos                     (7U)
7668 #define CAN_F0R2_FB7_Msk                     (0x1UL << CAN_F0R2_FB7_Pos)        /*!< 0x00000080 */
7669 #define CAN_F0R2_FB7                         CAN_F0R2_FB7_Msk                  /*!< Filter bit 7 */
7670 #define CAN_F0R2_FB8_Pos                     (8U)
7671 #define CAN_F0R2_FB8_Msk                     (0x1UL << CAN_F0R2_FB8_Pos)        /*!< 0x00000100 */
7672 #define CAN_F0R2_FB8                         CAN_F0R2_FB8_Msk                  /*!< Filter bit 8 */
7673 #define CAN_F0R2_FB9_Pos                     (9U)
7674 #define CAN_F0R2_FB9_Msk                     (0x1UL << CAN_F0R2_FB9_Pos)        /*!< 0x00000200 */
7675 #define CAN_F0R2_FB9                         CAN_F0R2_FB9_Msk                  /*!< Filter bit 9 */
7676 #define CAN_F0R2_FB10_Pos                    (10U)
7677 #define CAN_F0R2_FB10_Msk                    (0x1UL << CAN_F0R2_FB10_Pos)       /*!< 0x00000400 */
7678 #define CAN_F0R2_FB10                        CAN_F0R2_FB10_Msk                 /*!< Filter bit 10 */
7679 #define CAN_F0R2_FB11_Pos                    (11U)
7680 #define CAN_F0R2_FB11_Msk                    (0x1UL << CAN_F0R2_FB11_Pos)       /*!< 0x00000800 */
7681 #define CAN_F0R2_FB11                        CAN_F0R2_FB11_Msk                 /*!< Filter bit 11 */
7682 #define CAN_F0R2_FB12_Pos                    (12U)
7683 #define CAN_F0R2_FB12_Msk                    (0x1UL << CAN_F0R2_FB12_Pos)       /*!< 0x00001000 */
7684 #define CAN_F0R2_FB12                        CAN_F0R2_FB12_Msk                 /*!< Filter bit 12 */
7685 #define CAN_F0R2_FB13_Pos                    (13U)
7686 #define CAN_F0R2_FB13_Msk                    (0x1UL << CAN_F0R2_FB13_Pos)       /*!< 0x00002000 */
7687 #define CAN_F0R2_FB13                        CAN_F0R2_FB13_Msk                 /*!< Filter bit 13 */
7688 #define CAN_F0R2_FB14_Pos                    (14U)
7689 #define CAN_F0R2_FB14_Msk                    (0x1UL << CAN_F0R2_FB14_Pos)       /*!< 0x00004000 */
7690 #define CAN_F0R2_FB14                        CAN_F0R2_FB14_Msk                 /*!< Filter bit 14 */
7691 #define CAN_F0R2_FB15_Pos                    (15U)
7692 #define CAN_F0R2_FB15_Msk                    (0x1UL << CAN_F0R2_FB15_Pos)       /*!< 0x00008000 */
7693 #define CAN_F0R2_FB15                        CAN_F0R2_FB15_Msk                 /*!< Filter bit 15 */
7694 #define CAN_F0R2_FB16_Pos                    (16U)
7695 #define CAN_F0R2_FB16_Msk                    (0x1UL << CAN_F0R2_FB16_Pos)       /*!< 0x00010000 */
7696 #define CAN_F0R2_FB16                        CAN_F0R2_FB16_Msk                 /*!< Filter bit 16 */
7697 #define CAN_F0R2_FB17_Pos                    (17U)
7698 #define CAN_F0R2_FB17_Msk                    (0x1UL << CAN_F0R2_FB17_Pos)       /*!< 0x00020000 */
7699 #define CAN_F0R2_FB17                        CAN_F0R2_FB17_Msk                 /*!< Filter bit 17 */
7700 #define CAN_F0R2_FB18_Pos                    (18U)
7701 #define CAN_F0R2_FB18_Msk                    (0x1UL << CAN_F0R2_FB18_Pos)       /*!< 0x00040000 */
7702 #define CAN_F0R2_FB18                        CAN_F0R2_FB18_Msk                 /*!< Filter bit 18 */
7703 #define CAN_F0R2_FB19_Pos                    (19U)
7704 #define CAN_F0R2_FB19_Msk                    (0x1UL << CAN_F0R2_FB19_Pos)       /*!< 0x00080000 */
7705 #define CAN_F0R2_FB19                        CAN_F0R2_FB19_Msk                 /*!< Filter bit 19 */
7706 #define CAN_F0R2_FB20_Pos                    (20U)
7707 #define CAN_F0R2_FB20_Msk                    (0x1UL << CAN_F0R2_FB20_Pos)       /*!< 0x00100000 */
7708 #define CAN_F0R2_FB20                        CAN_F0R2_FB20_Msk                 /*!< Filter bit 20 */
7709 #define CAN_F0R2_FB21_Pos                    (21U)
7710 #define CAN_F0R2_FB21_Msk                    (0x1UL << CAN_F0R2_FB21_Pos)       /*!< 0x00200000 */
7711 #define CAN_F0R2_FB21                        CAN_F0R2_FB21_Msk                 /*!< Filter bit 21 */
7712 #define CAN_F0R2_FB22_Pos                    (22U)
7713 #define CAN_F0R2_FB22_Msk                    (0x1UL << CAN_F0R2_FB22_Pos)       /*!< 0x00400000 */
7714 #define CAN_F0R2_FB22                        CAN_F0R2_FB22_Msk                 /*!< Filter bit 22 */
7715 #define CAN_F0R2_FB23_Pos                    (23U)
7716 #define CAN_F0R2_FB23_Msk                    (0x1UL << CAN_F0R2_FB23_Pos)       /*!< 0x00800000 */
7717 #define CAN_F0R2_FB23                        CAN_F0R2_FB23_Msk                 /*!< Filter bit 23 */
7718 #define CAN_F0R2_FB24_Pos                    (24U)
7719 #define CAN_F0R2_FB24_Msk                    (0x1UL << CAN_F0R2_FB24_Pos)       /*!< 0x01000000 */
7720 #define CAN_F0R2_FB24                        CAN_F0R2_FB24_Msk                 /*!< Filter bit 24 */
7721 #define CAN_F0R2_FB25_Pos                    (25U)
7722 #define CAN_F0R2_FB25_Msk                    (0x1UL << CAN_F0R2_FB25_Pos)       /*!< 0x02000000 */
7723 #define CAN_F0R2_FB25                        CAN_F0R2_FB25_Msk                 /*!< Filter bit 25 */
7724 #define CAN_F0R2_FB26_Pos                    (26U)
7725 #define CAN_F0R2_FB26_Msk                    (0x1UL << CAN_F0R2_FB26_Pos)       /*!< 0x04000000 */
7726 #define CAN_F0R2_FB26                        CAN_F0R2_FB26_Msk                 /*!< Filter bit 26 */
7727 #define CAN_F0R2_FB27_Pos                    (27U)
7728 #define CAN_F0R2_FB27_Msk                    (0x1UL << CAN_F0R2_FB27_Pos)       /*!< 0x08000000 */
7729 #define CAN_F0R2_FB27                        CAN_F0R2_FB27_Msk                 /*!< Filter bit 27 */
7730 #define CAN_F0R2_FB28_Pos                    (28U)
7731 #define CAN_F0R2_FB28_Msk                    (0x1UL << CAN_F0R2_FB28_Pos)       /*!< 0x10000000 */
7732 #define CAN_F0R2_FB28                        CAN_F0R2_FB28_Msk                 /*!< Filter bit 28 */
7733 #define CAN_F0R2_FB29_Pos                    (29U)
7734 #define CAN_F0R2_FB29_Msk                    (0x1UL << CAN_F0R2_FB29_Pos)       /*!< 0x20000000 */
7735 #define CAN_F0R2_FB29                        CAN_F0R2_FB29_Msk                 /*!< Filter bit 29 */
7736 #define CAN_F0R2_FB30_Pos                    (30U)
7737 #define CAN_F0R2_FB30_Msk                    (0x1UL << CAN_F0R2_FB30_Pos)       /*!< 0x40000000 */
7738 #define CAN_F0R2_FB30                        CAN_F0R2_FB30_Msk                 /*!< Filter bit 30 */
7739 #define CAN_F0R2_FB31_Pos                    (31U)
7740 #define CAN_F0R2_FB31_Msk                    (0x1UL << CAN_F0R2_FB31_Pos)       /*!< 0x80000000 */
7741 #define CAN_F0R2_FB31                        CAN_F0R2_FB31_Msk                 /*!< Filter bit 31 */
7742 
7743 /*******************  Bit definition for CAN_F1R2 register  *******************/
7744 #define CAN_F1R2_FB0_Pos                     (0U)
7745 #define CAN_F1R2_FB0_Msk                     (0x1UL << CAN_F1R2_FB0_Pos)        /*!< 0x00000001 */
7746 #define CAN_F1R2_FB0                         CAN_F1R2_FB0_Msk                  /*!< Filter bit 0 */
7747 #define CAN_F1R2_FB1_Pos                     (1U)
7748 #define CAN_F1R2_FB1_Msk                     (0x1UL << CAN_F1R2_FB1_Pos)        /*!< 0x00000002 */
7749 #define CAN_F1R2_FB1                         CAN_F1R2_FB1_Msk                  /*!< Filter bit 1 */
7750 #define CAN_F1R2_FB2_Pos                     (2U)
7751 #define CAN_F1R2_FB2_Msk                     (0x1UL << CAN_F1R2_FB2_Pos)        /*!< 0x00000004 */
7752 #define CAN_F1R2_FB2                         CAN_F1R2_FB2_Msk                  /*!< Filter bit 2 */
7753 #define CAN_F1R2_FB3_Pos                     (3U)
7754 #define CAN_F1R2_FB3_Msk                     (0x1UL << CAN_F1R2_FB3_Pos)        /*!< 0x00000008 */
7755 #define CAN_F1R2_FB3                         CAN_F1R2_FB3_Msk                  /*!< Filter bit 3 */
7756 #define CAN_F1R2_FB4_Pos                     (4U)
7757 #define CAN_F1R2_FB4_Msk                     (0x1UL << CAN_F1R2_FB4_Pos)        /*!< 0x00000010 */
7758 #define CAN_F1R2_FB4                         CAN_F1R2_FB4_Msk                  /*!< Filter bit 4 */
7759 #define CAN_F1R2_FB5_Pos                     (5U)
7760 #define CAN_F1R2_FB5_Msk                     (0x1UL << CAN_F1R2_FB5_Pos)        /*!< 0x00000020 */
7761 #define CAN_F1R2_FB5                         CAN_F1R2_FB5_Msk                  /*!< Filter bit 5 */
7762 #define CAN_F1R2_FB6_Pos                     (6U)
7763 #define CAN_F1R2_FB6_Msk                     (0x1UL << CAN_F1R2_FB6_Pos)        /*!< 0x00000040 */
7764 #define CAN_F1R2_FB6                         CAN_F1R2_FB6_Msk                  /*!< Filter bit 6 */
7765 #define CAN_F1R2_FB7_Pos                     (7U)
7766 #define CAN_F1R2_FB7_Msk                     (0x1UL << CAN_F1R2_FB7_Pos)        /*!< 0x00000080 */
7767 #define CAN_F1R2_FB7                         CAN_F1R2_FB7_Msk                  /*!< Filter bit 7 */
7768 #define CAN_F1R2_FB8_Pos                     (8U)
7769 #define CAN_F1R2_FB8_Msk                     (0x1UL << CAN_F1R2_FB8_Pos)        /*!< 0x00000100 */
7770 #define CAN_F1R2_FB8                         CAN_F1R2_FB8_Msk                  /*!< Filter bit 8 */
7771 #define CAN_F1R2_FB9_Pos                     (9U)
7772 #define CAN_F1R2_FB9_Msk                     (0x1UL << CAN_F1R2_FB9_Pos)        /*!< 0x00000200 */
7773 #define CAN_F1R2_FB9                         CAN_F1R2_FB9_Msk                  /*!< Filter bit 9 */
7774 #define CAN_F1R2_FB10_Pos                    (10U)
7775 #define CAN_F1R2_FB10_Msk                    (0x1UL << CAN_F1R2_FB10_Pos)       /*!< 0x00000400 */
7776 #define CAN_F1R2_FB10                        CAN_F1R2_FB10_Msk                 /*!< Filter bit 10 */
7777 #define CAN_F1R2_FB11_Pos                    (11U)
7778 #define CAN_F1R2_FB11_Msk                    (0x1UL << CAN_F1R2_FB11_Pos)       /*!< 0x00000800 */
7779 #define CAN_F1R2_FB11                        CAN_F1R2_FB11_Msk                 /*!< Filter bit 11 */
7780 #define CAN_F1R2_FB12_Pos                    (12U)
7781 #define CAN_F1R2_FB12_Msk                    (0x1UL << CAN_F1R2_FB12_Pos)       /*!< 0x00001000 */
7782 #define CAN_F1R2_FB12                        CAN_F1R2_FB12_Msk                 /*!< Filter bit 12 */
7783 #define CAN_F1R2_FB13_Pos                    (13U)
7784 #define CAN_F1R2_FB13_Msk                    (0x1UL << CAN_F1R2_FB13_Pos)       /*!< 0x00002000 */
7785 #define CAN_F1R2_FB13                        CAN_F1R2_FB13_Msk                 /*!< Filter bit 13 */
7786 #define CAN_F1R2_FB14_Pos                    (14U)
7787 #define CAN_F1R2_FB14_Msk                    (0x1UL << CAN_F1R2_FB14_Pos)       /*!< 0x00004000 */
7788 #define CAN_F1R2_FB14                        CAN_F1R2_FB14_Msk                 /*!< Filter bit 14 */
7789 #define CAN_F1R2_FB15_Pos                    (15U)
7790 #define CAN_F1R2_FB15_Msk                    (0x1UL << CAN_F1R2_FB15_Pos)       /*!< 0x00008000 */
7791 #define CAN_F1R2_FB15                        CAN_F1R2_FB15_Msk                 /*!< Filter bit 15 */
7792 #define CAN_F1R2_FB16_Pos                    (16U)
7793 #define CAN_F1R2_FB16_Msk                    (0x1UL << CAN_F1R2_FB16_Pos)       /*!< 0x00010000 */
7794 #define CAN_F1R2_FB16                        CAN_F1R2_FB16_Msk                 /*!< Filter bit 16 */
7795 #define CAN_F1R2_FB17_Pos                    (17U)
7796 #define CAN_F1R2_FB17_Msk                    (0x1UL << CAN_F1R2_FB17_Pos)       /*!< 0x00020000 */
7797 #define CAN_F1R2_FB17                        CAN_F1R2_FB17_Msk                 /*!< Filter bit 17 */
7798 #define CAN_F1R2_FB18_Pos                    (18U)
7799 #define CAN_F1R2_FB18_Msk                    (0x1UL << CAN_F1R2_FB18_Pos)       /*!< 0x00040000 */
7800 #define CAN_F1R2_FB18                        CAN_F1R2_FB18_Msk                 /*!< Filter bit 18 */
7801 #define CAN_F1R2_FB19_Pos                    (19U)
7802 #define CAN_F1R2_FB19_Msk                    (0x1UL << CAN_F1R2_FB19_Pos)       /*!< 0x00080000 */
7803 #define CAN_F1R2_FB19                        CAN_F1R2_FB19_Msk                 /*!< Filter bit 19 */
7804 #define CAN_F1R2_FB20_Pos                    (20U)
7805 #define CAN_F1R2_FB20_Msk                    (0x1UL << CAN_F1R2_FB20_Pos)       /*!< 0x00100000 */
7806 #define CAN_F1R2_FB20                        CAN_F1R2_FB20_Msk                 /*!< Filter bit 20 */
7807 #define CAN_F1R2_FB21_Pos                    (21U)
7808 #define CAN_F1R2_FB21_Msk                    (0x1UL << CAN_F1R2_FB21_Pos)       /*!< 0x00200000 */
7809 #define CAN_F1R2_FB21                        CAN_F1R2_FB21_Msk                 /*!< Filter bit 21 */
7810 #define CAN_F1R2_FB22_Pos                    (22U)
7811 #define CAN_F1R2_FB22_Msk                    (0x1UL << CAN_F1R2_FB22_Pos)       /*!< 0x00400000 */
7812 #define CAN_F1R2_FB22                        CAN_F1R2_FB22_Msk                 /*!< Filter bit 22 */
7813 #define CAN_F1R2_FB23_Pos                    (23U)
7814 #define CAN_F1R2_FB23_Msk                    (0x1UL << CAN_F1R2_FB23_Pos)       /*!< 0x00800000 */
7815 #define CAN_F1R2_FB23                        CAN_F1R2_FB23_Msk                 /*!< Filter bit 23 */
7816 #define CAN_F1R2_FB24_Pos                    (24U)
7817 #define CAN_F1R2_FB24_Msk                    (0x1UL << CAN_F1R2_FB24_Pos)       /*!< 0x01000000 */
7818 #define CAN_F1R2_FB24                        CAN_F1R2_FB24_Msk                 /*!< Filter bit 24 */
7819 #define CAN_F1R2_FB25_Pos                    (25U)
7820 #define CAN_F1R2_FB25_Msk                    (0x1UL << CAN_F1R2_FB25_Pos)       /*!< 0x02000000 */
7821 #define CAN_F1R2_FB25                        CAN_F1R2_FB25_Msk                 /*!< Filter bit 25 */
7822 #define CAN_F1R2_FB26_Pos                    (26U)
7823 #define CAN_F1R2_FB26_Msk                    (0x1UL << CAN_F1R2_FB26_Pos)       /*!< 0x04000000 */
7824 #define CAN_F1R2_FB26                        CAN_F1R2_FB26_Msk                 /*!< Filter bit 26 */
7825 #define CAN_F1R2_FB27_Pos                    (27U)
7826 #define CAN_F1R2_FB27_Msk                    (0x1UL << CAN_F1R2_FB27_Pos)       /*!< 0x08000000 */
7827 #define CAN_F1R2_FB27                        CAN_F1R2_FB27_Msk                 /*!< Filter bit 27 */
7828 #define CAN_F1R2_FB28_Pos                    (28U)
7829 #define CAN_F1R2_FB28_Msk                    (0x1UL << CAN_F1R2_FB28_Pos)       /*!< 0x10000000 */
7830 #define CAN_F1R2_FB28                        CAN_F1R2_FB28_Msk                 /*!< Filter bit 28 */
7831 #define CAN_F1R2_FB29_Pos                    (29U)
7832 #define CAN_F1R2_FB29_Msk                    (0x1UL << CAN_F1R2_FB29_Pos)       /*!< 0x20000000 */
7833 #define CAN_F1R2_FB29                        CAN_F1R2_FB29_Msk                 /*!< Filter bit 29 */
7834 #define CAN_F1R2_FB30_Pos                    (30U)
7835 #define CAN_F1R2_FB30_Msk                    (0x1UL << CAN_F1R2_FB30_Pos)       /*!< 0x40000000 */
7836 #define CAN_F1R2_FB30                        CAN_F1R2_FB30_Msk                 /*!< Filter bit 30 */
7837 #define CAN_F1R2_FB31_Pos                    (31U)
7838 #define CAN_F1R2_FB31_Msk                    (0x1UL << CAN_F1R2_FB31_Pos)       /*!< 0x80000000 */
7839 #define CAN_F1R2_FB31                        CAN_F1R2_FB31_Msk                 /*!< Filter bit 31 */
7840 
7841 /*******************  Bit definition for CAN_F2R2 register  *******************/
7842 #define CAN_F2R2_FB0_Pos                     (0U)
7843 #define CAN_F2R2_FB0_Msk                     (0x1UL << CAN_F2R2_FB0_Pos)        /*!< 0x00000001 */
7844 #define CAN_F2R2_FB0                         CAN_F2R2_FB0_Msk                  /*!< Filter bit 0 */
7845 #define CAN_F2R2_FB1_Pos                     (1U)
7846 #define CAN_F2R2_FB1_Msk                     (0x1UL << CAN_F2R2_FB1_Pos)        /*!< 0x00000002 */
7847 #define CAN_F2R2_FB1                         CAN_F2R2_FB1_Msk                  /*!< Filter bit 1 */
7848 #define CAN_F2R2_FB2_Pos                     (2U)
7849 #define CAN_F2R2_FB2_Msk                     (0x1UL << CAN_F2R2_FB2_Pos)        /*!< 0x00000004 */
7850 #define CAN_F2R2_FB2                         CAN_F2R2_FB2_Msk                  /*!< Filter bit 2 */
7851 #define CAN_F2R2_FB3_Pos                     (3U)
7852 #define CAN_F2R2_FB3_Msk                     (0x1UL << CAN_F2R2_FB3_Pos)        /*!< 0x00000008 */
7853 #define CAN_F2R2_FB3                         CAN_F2R2_FB3_Msk                  /*!< Filter bit 3 */
7854 #define CAN_F2R2_FB4_Pos                     (4U)
7855 #define CAN_F2R2_FB4_Msk                     (0x1UL << CAN_F2R2_FB4_Pos)        /*!< 0x00000010 */
7856 #define CAN_F2R2_FB4                         CAN_F2R2_FB4_Msk                  /*!< Filter bit 4 */
7857 #define CAN_F2R2_FB5_Pos                     (5U)
7858 #define CAN_F2R2_FB5_Msk                     (0x1UL << CAN_F2R2_FB5_Pos)        /*!< 0x00000020 */
7859 #define CAN_F2R2_FB5                         CAN_F2R2_FB5_Msk                  /*!< Filter bit 5 */
7860 #define CAN_F2R2_FB6_Pos                     (6U)
7861 #define CAN_F2R2_FB6_Msk                     (0x1UL << CAN_F2R2_FB6_Pos)        /*!< 0x00000040 */
7862 #define CAN_F2R2_FB6                         CAN_F2R2_FB6_Msk                  /*!< Filter bit 6 */
7863 #define CAN_F2R2_FB7_Pos                     (7U)
7864 #define CAN_F2R2_FB7_Msk                     (0x1UL << CAN_F2R2_FB7_Pos)        /*!< 0x00000080 */
7865 #define CAN_F2R2_FB7                         CAN_F2R2_FB7_Msk                  /*!< Filter bit 7 */
7866 #define CAN_F2R2_FB8_Pos                     (8U)
7867 #define CAN_F2R2_FB8_Msk                     (0x1UL << CAN_F2R2_FB8_Pos)        /*!< 0x00000100 */
7868 #define CAN_F2R2_FB8                         CAN_F2R2_FB8_Msk                  /*!< Filter bit 8 */
7869 #define CAN_F2R2_FB9_Pos                     (9U)
7870 #define CAN_F2R2_FB9_Msk                     (0x1UL << CAN_F2R2_FB9_Pos)        /*!< 0x00000200 */
7871 #define CAN_F2R2_FB9                         CAN_F2R2_FB9_Msk                  /*!< Filter bit 9 */
7872 #define CAN_F2R2_FB10_Pos                    (10U)
7873 #define CAN_F2R2_FB10_Msk                    (0x1UL << CAN_F2R2_FB10_Pos)       /*!< 0x00000400 */
7874 #define CAN_F2R2_FB10                        CAN_F2R2_FB10_Msk                 /*!< Filter bit 10 */
7875 #define CAN_F2R2_FB11_Pos                    (11U)
7876 #define CAN_F2R2_FB11_Msk                    (0x1UL << CAN_F2R2_FB11_Pos)       /*!< 0x00000800 */
7877 #define CAN_F2R2_FB11                        CAN_F2R2_FB11_Msk                 /*!< Filter bit 11 */
7878 #define CAN_F2R2_FB12_Pos                    (12U)
7879 #define CAN_F2R2_FB12_Msk                    (0x1UL << CAN_F2R2_FB12_Pos)       /*!< 0x00001000 */
7880 #define CAN_F2R2_FB12                        CAN_F2R2_FB12_Msk                 /*!< Filter bit 12 */
7881 #define CAN_F2R2_FB13_Pos                    (13U)
7882 #define CAN_F2R2_FB13_Msk                    (0x1UL << CAN_F2R2_FB13_Pos)       /*!< 0x00002000 */
7883 #define CAN_F2R2_FB13                        CAN_F2R2_FB13_Msk                 /*!< Filter bit 13 */
7884 #define CAN_F2R2_FB14_Pos                    (14U)
7885 #define CAN_F2R2_FB14_Msk                    (0x1UL << CAN_F2R2_FB14_Pos)       /*!< 0x00004000 */
7886 #define CAN_F2R2_FB14                        CAN_F2R2_FB14_Msk                 /*!< Filter bit 14 */
7887 #define CAN_F2R2_FB15_Pos                    (15U)
7888 #define CAN_F2R2_FB15_Msk                    (0x1UL << CAN_F2R2_FB15_Pos)       /*!< 0x00008000 */
7889 #define CAN_F2R2_FB15                        CAN_F2R2_FB15_Msk                 /*!< Filter bit 15 */
7890 #define CAN_F2R2_FB16_Pos                    (16U)
7891 #define CAN_F2R2_FB16_Msk                    (0x1UL << CAN_F2R2_FB16_Pos)       /*!< 0x00010000 */
7892 #define CAN_F2R2_FB16                        CAN_F2R2_FB16_Msk                 /*!< Filter bit 16 */
7893 #define CAN_F2R2_FB17_Pos                    (17U)
7894 #define CAN_F2R2_FB17_Msk                    (0x1UL << CAN_F2R2_FB17_Pos)       /*!< 0x00020000 */
7895 #define CAN_F2R2_FB17                        CAN_F2R2_FB17_Msk                 /*!< Filter bit 17 */
7896 #define CAN_F2R2_FB18_Pos                    (18U)
7897 #define CAN_F2R2_FB18_Msk                    (0x1UL << CAN_F2R2_FB18_Pos)       /*!< 0x00040000 */
7898 #define CAN_F2R2_FB18                        CAN_F2R2_FB18_Msk                 /*!< Filter bit 18 */
7899 #define CAN_F2R2_FB19_Pos                    (19U)
7900 #define CAN_F2R2_FB19_Msk                    (0x1UL << CAN_F2R2_FB19_Pos)       /*!< 0x00080000 */
7901 #define CAN_F2R2_FB19                        CAN_F2R2_FB19_Msk                 /*!< Filter bit 19 */
7902 #define CAN_F2R2_FB20_Pos                    (20U)
7903 #define CAN_F2R2_FB20_Msk                    (0x1UL << CAN_F2R2_FB20_Pos)       /*!< 0x00100000 */
7904 #define CAN_F2R2_FB20                        CAN_F2R2_FB20_Msk                 /*!< Filter bit 20 */
7905 #define CAN_F2R2_FB21_Pos                    (21U)
7906 #define CAN_F2R2_FB21_Msk                    (0x1UL << CAN_F2R2_FB21_Pos)       /*!< 0x00200000 */
7907 #define CAN_F2R2_FB21                        CAN_F2R2_FB21_Msk                 /*!< Filter bit 21 */
7908 #define CAN_F2R2_FB22_Pos                    (22U)
7909 #define CAN_F2R2_FB22_Msk                    (0x1UL << CAN_F2R2_FB22_Pos)       /*!< 0x00400000 */
7910 #define CAN_F2R2_FB22                        CAN_F2R2_FB22_Msk                 /*!< Filter bit 22 */
7911 #define CAN_F2R2_FB23_Pos                    (23U)
7912 #define CAN_F2R2_FB23_Msk                    (0x1UL << CAN_F2R2_FB23_Pos)       /*!< 0x00800000 */
7913 #define CAN_F2R2_FB23                        CAN_F2R2_FB23_Msk                 /*!< Filter bit 23 */
7914 #define CAN_F2R2_FB24_Pos                    (24U)
7915 #define CAN_F2R2_FB24_Msk                    (0x1UL << CAN_F2R2_FB24_Pos)       /*!< 0x01000000 */
7916 #define CAN_F2R2_FB24                        CAN_F2R2_FB24_Msk                 /*!< Filter bit 24 */
7917 #define CAN_F2R2_FB25_Pos                    (25U)
7918 #define CAN_F2R2_FB25_Msk                    (0x1UL << CAN_F2R2_FB25_Pos)       /*!< 0x02000000 */
7919 #define CAN_F2R2_FB25                        CAN_F2R2_FB25_Msk                 /*!< Filter bit 25 */
7920 #define CAN_F2R2_FB26_Pos                    (26U)
7921 #define CAN_F2R2_FB26_Msk                    (0x1UL << CAN_F2R2_FB26_Pos)       /*!< 0x04000000 */
7922 #define CAN_F2R2_FB26                        CAN_F2R2_FB26_Msk                 /*!< Filter bit 26 */
7923 #define CAN_F2R2_FB27_Pos                    (27U)
7924 #define CAN_F2R2_FB27_Msk                    (0x1UL << CAN_F2R2_FB27_Pos)       /*!< 0x08000000 */
7925 #define CAN_F2R2_FB27                        CAN_F2R2_FB27_Msk                 /*!< Filter bit 27 */
7926 #define CAN_F2R2_FB28_Pos                    (28U)
7927 #define CAN_F2R2_FB28_Msk                    (0x1UL << CAN_F2R2_FB28_Pos)       /*!< 0x10000000 */
7928 #define CAN_F2R2_FB28                        CAN_F2R2_FB28_Msk                 /*!< Filter bit 28 */
7929 #define CAN_F2R2_FB29_Pos                    (29U)
7930 #define CAN_F2R2_FB29_Msk                    (0x1UL << CAN_F2R2_FB29_Pos)       /*!< 0x20000000 */
7931 #define CAN_F2R2_FB29                        CAN_F2R2_FB29_Msk                 /*!< Filter bit 29 */
7932 #define CAN_F2R2_FB30_Pos                    (30U)
7933 #define CAN_F2R2_FB30_Msk                    (0x1UL << CAN_F2R2_FB30_Pos)       /*!< 0x40000000 */
7934 #define CAN_F2R2_FB30                        CAN_F2R2_FB30_Msk                 /*!< Filter bit 30 */
7935 #define CAN_F2R2_FB31_Pos                    (31U)
7936 #define CAN_F2R2_FB31_Msk                    (0x1UL << CAN_F2R2_FB31_Pos)       /*!< 0x80000000 */
7937 #define CAN_F2R2_FB31                        CAN_F2R2_FB31_Msk                 /*!< Filter bit 31 */
7938 
7939 /*******************  Bit definition for CAN_F3R2 register  *******************/
7940 #define CAN_F3R2_FB0_Pos                     (0U)
7941 #define CAN_F3R2_FB0_Msk                     (0x1UL << CAN_F3R2_FB0_Pos)        /*!< 0x00000001 */
7942 #define CAN_F3R2_FB0                         CAN_F3R2_FB0_Msk                  /*!< Filter bit 0 */
7943 #define CAN_F3R2_FB1_Pos                     (1U)
7944 #define CAN_F3R2_FB1_Msk                     (0x1UL << CAN_F3R2_FB1_Pos)        /*!< 0x00000002 */
7945 #define CAN_F3R2_FB1                         CAN_F3R2_FB1_Msk                  /*!< Filter bit 1 */
7946 #define CAN_F3R2_FB2_Pos                     (2U)
7947 #define CAN_F3R2_FB2_Msk                     (0x1UL << CAN_F3R2_FB2_Pos)        /*!< 0x00000004 */
7948 #define CAN_F3R2_FB2                         CAN_F3R2_FB2_Msk                  /*!< Filter bit 2 */
7949 #define CAN_F3R2_FB3_Pos                     (3U)
7950 #define CAN_F3R2_FB3_Msk                     (0x1UL << CAN_F3R2_FB3_Pos)        /*!< 0x00000008 */
7951 #define CAN_F3R2_FB3                         CAN_F3R2_FB3_Msk                  /*!< Filter bit 3 */
7952 #define CAN_F3R2_FB4_Pos                     (4U)
7953 #define CAN_F3R2_FB4_Msk                     (0x1UL << CAN_F3R2_FB4_Pos)        /*!< 0x00000010 */
7954 #define CAN_F3R2_FB4                         CAN_F3R2_FB4_Msk                  /*!< Filter bit 4 */
7955 #define CAN_F3R2_FB5_Pos                     (5U)
7956 #define CAN_F3R2_FB5_Msk                     (0x1UL << CAN_F3R2_FB5_Pos)        /*!< 0x00000020 */
7957 #define CAN_F3R2_FB5                         CAN_F3R2_FB5_Msk                  /*!< Filter bit 5 */
7958 #define CAN_F3R2_FB6_Pos                     (6U)
7959 #define CAN_F3R2_FB6_Msk                     (0x1UL << CAN_F3R2_FB6_Pos)        /*!< 0x00000040 */
7960 #define CAN_F3R2_FB6                         CAN_F3R2_FB6_Msk                  /*!< Filter bit 6 */
7961 #define CAN_F3R2_FB7_Pos                     (7U)
7962 #define CAN_F3R2_FB7_Msk                     (0x1UL << CAN_F3R2_FB7_Pos)        /*!< 0x00000080 */
7963 #define CAN_F3R2_FB7                         CAN_F3R2_FB7_Msk                  /*!< Filter bit 7 */
7964 #define CAN_F3R2_FB8_Pos                     (8U)
7965 #define CAN_F3R2_FB8_Msk                     (0x1UL << CAN_F3R2_FB8_Pos)        /*!< 0x00000100 */
7966 #define CAN_F3R2_FB8                         CAN_F3R2_FB8_Msk                  /*!< Filter bit 8 */
7967 #define CAN_F3R2_FB9_Pos                     (9U)
7968 #define CAN_F3R2_FB9_Msk                     (0x1UL << CAN_F3R2_FB9_Pos)        /*!< 0x00000200 */
7969 #define CAN_F3R2_FB9                         CAN_F3R2_FB9_Msk                  /*!< Filter bit 9 */
7970 #define CAN_F3R2_FB10_Pos                    (10U)
7971 #define CAN_F3R2_FB10_Msk                    (0x1UL << CAN_F3R2_FB10_Pos)       /*!< 0x00000400 */
7972 #define CAN_F3R2_FB10                        CAN_F3R2_FB10_Msk                 /*!< Filter bit 10 */
7973 #define CAN_F3R2_FB11_Pos                    (11U)
7974 #define CAN_F3R2_FB11_Msk                    (0x1UL << CAN_F3R2_FB11_Pos)       /*!< 0x00000800 */
7975 #define CAN_F3R2_FB11                        CAN_F3R2_FB11_Msk                 /*!< Filter bit 11 */
7976 #define CAN_F3R2_FB12_Pos                    (12U)
7977 #define CAN_F3R2_FB12_Msk                    (0x1UL << CAN_F3R2_FB12_Pos)       /*!< 0x00001000 */
7978 #define CAN_F3R2_FB12                        CAN_F3R2_FB12_Msk                 /*!< Filter bit 12 */
7979 #define CAN_F3R2_FB13_Pos                    (13U)
7980 #define CAN_F3R2_FB13_Msk                    (0x1UL << CAN_F3R2_FB13_Pos)       /*!< 0x00002000 */
7981 #define CAN_F3R2_FB13                        CAN_F3R2_FB13_Msk                 /*!< Filter bit 13 */
7982 #define CAN_F3R2_FB14_Pos                    (14U)
7983 #define CAN_F3R2_FB14_Msk                    (0x1UL << CAN_F3R2_FB14_Pos)       /*!< 0x00004000 */
7984 #define CAN_F3R2_FB14                        CAN_F3R2_FB14_Msk                 /*!< Filter bit 14 */
7985 #define CAN_F3R2_FB15_Pos                    (15U)
7986 #define CAN_F3R2_FB15_Msk                    (0x1UL << CAN_F3R2_FB15_Pos)       /*!< 0x00008000 */
7987 #define CAN_F3R2_FB15                        CAN_F3R2_FB15_Msk                 /*!< Filter bit 15 */
7988 #define CAN_F3R2_FB16_Pos                    (16U)
7989 #define CAN_F3R2_FB16_Msk                    (0x1UL << CAN_F3R2_FB16_Pos)       /*!< 0x00010000 */
7990 #define CAN_F3R2_FB16                        CAN_F3R2_FB16_Msk                 /*!< Filter bit 16 */
7991 #define CAN_F3R2_FB17_Pos                    (17U)
7992 #define CAN_F3R2_FB17_Msk                    (0x1UL << CAN_F3R2_FB17_Pos)       /*!< 0x00020000 */
7993 #define CAN_F3R2_FB17                        CAN_F3R2_FB17_Msk                 /*!< Filter bit 17 */
7994 #define CAN_F3R2_FB18_Pos                    (18U)
7995 #define CAN_F3R2_FB18_Msk                    (0x1UL << CAN_F3R2_FB18_Pos)       /*!< 0x00040000 */
7996 #define CAN_F3R2_FB18                        CAN_F3R2_FB18_Msk                 /*!< Filter bit 18 */
7997 #define CAN_F3R2_FB19_Pos                    (19U)
7998 #define CAN_F3R2_FB19_Msk                    (0x1UL << CAN_F3R2_FB19_Pos)       /*!< 0x00080000 */
7999 #define CAN_F3R2_FB19                        CAN_F3R2_FB19_Msk                 /*!< Filter bit 19 */
8000 #define CAN_F3R2_FB20_Pos                    (20U)
8001 #define CAN_F3R2_FB20_Msk                    (0x1UL << CAN_F3R2_FB20_Pos)       /*!< 0x00100000 */
8002 #define CAN_F3R2_FB20                        CAN_F3R2_FB20_Msk                 /*!< Filter bit 20 */
8003 #define CAN_F3R2_FB21_Pos                    (21U)
8004 #define CAN_F3R2_FB21_Msk                    (0x1UL << CAN_F3R2_FB21_Pos)       /*!< 0x00200000 */
8005 #define CAN_F3R2_FB21                        CAN_F3R2_FB21_Msk                 /*!< Filter bit 21 */
8006 #define CAN_F3R2_FB22_Pos                    (22U)
8007 #define CAN_F3R2_FB22_Msk                    (0x1UL << CAN_F3R2_FB22_Pos)       /*!< 0x00400000 */
8008 #define CAN_F3R2_FB22                        CAN_F3R2_FB22_Msk                 /*!< Filter bit 22 */
8009 #define CAN_F3R2_FB23_Pos                    (23U)
8010 #define CAN_F3R2_FB23_Msk                    (0x1UL << CAN_F3R2_FB23_Pos)       /*!< 0x00800000 */
8011 #define CAN_F3R2_FB23                        CAN_F3R2_FB23_Msk                 /*!< Filter bit 23 */
8012 #define CAN_F3R2_FB24_Pos                    (24U)
8013 #define CAN_F3R2_FB24_Msk                    (0x1UL << CAN_F3R2_FB24_Pos)       /*!< 0x01000000 */
8014 #define CAN_F3R2_FB24                        CAN_F3R2_FB24_Msk                 /*!< Filter bit 24 */
8015 #define CAN_F3R2_FB25_Pos                    (25U)
8016 #define CAN_F3R2_FB25_Msk                    (0x1UL << CAN_F3R2_FB25_Pos)       /*!< 0x02000000 */
8017 #define CAN_F3R2_FB25                        CAN_F3R2_FB25_Msk                 /*!< Filter bit 25 */
8018 #define CAN_F3R2_FB26_Pos                    (26U)
8019 #define CAN_F3R2_FB26_Msk                    (0x1UL << CAN_F3R2_FB26_Pos)       /*!< 0x04000000 */
8020 #define CAN_F3R2_FB26                        CAN_F3R2_FB26_Msk                 /*!< Filter bit 26 */
8021 #define CAN_F3R2_FB27_Pos                    (27U)
8022 #define CAN_F3R2_FB27_Msk                    (0x1UL << CAN_F3R2_FB27_Pos)       /*!< 0x08000000 */
8023 #define CAN_F3R2_FB27                        CAN_F3R2_FB27_Msk                 /*!< Filter bit 27 */
8024 #define CAN_F3R2_FB28_Pos                    (28U)
8025 #define CAN_F3R2_FB28_Msk                    (0x1UL << CAN_F3R2_FB28_Pos)       /*!< 0x10000000 */
8026 #define CAN_F3R2_FB28                        CAN_F3R2_FB28_Msk                 /*!< Filter bit 28 */
8027 #define CAN_F3R2_FB29_Pos                    (29U)
8028 #define CAN_F3R2_FB29_Msk                    (0x1UL << CAN_F3R2_FB29_Pos)       /*!< 0x20000000 */
8029 #define CAN_F3R2_FB29                        CAN_F3R2_FB29_Msk                 /*!< Filter bit 29 */
8030 #define CAN_F3R2_FB30_Pos                    (30U)
8031 #define CAN_F3R2_FB30_Msk                    (0x1UL << CAN_F3R2_FB30_Pos)       /*!< 0x40000000 */
8032 #define CAN_F3R2_FB30                        CAN_F3R2_FB30_Msk                 /*!< Filter bit 30 */
8033 #define CAN_F3R2_FB31_Pos                    (31U)
8034 #define CAN_F3R2_FB31_Msk                    (0x1UL << CAN_F3R2_FB31_Pos)       /*!< 0x80000000 */
8035 #define CAN_F3R2_FB31                        CAN_F3R2_FB31_Msk                 /*!< Filter bit 31 */
8036 
8037 /*******************  Bit definition for CAN_F4R2 register  *******************/
8038 #define CAN_F4R2_FB0_Pos                     (0U)
8039 #define CAN_F4R2_FB0_Msk                     (0x1UL << CAN_F4R2_FB0_Pos)        /*!< 0x00000001 */
8040 #define CAN_F4R2_FB0                         CAN_F4R2_FB0_Msk                  /*!< Filter bit 0 */
8041 #define CAN_F4R2_FB1_Pos                     (1U)
8042 #define CAN_F4R2_FB1_Msk                     (0x1UL << CAN_F4R2_FB1_Pos)        /*!< 0x00000002 */
8043 #define CAN_F4R2_FB1                         CAN_F4R2_FB1_Msk                  /*!< Filter bit 1 */
8044 #define CAN_F4R2_FB2_Pos                     (2U)
8045 #define CAN_F4R2_FB2_Msk                     (0x1UL << CAN_F4R2_FB2_Pos)        /*!< 0x00000004 */
8046 #define CAN_F4R2_FB2                         CAN_F4R2_FB2_Msk                  /*!< Filter bit 2 */
8047 #define CAN_F4R2_FB3_Pos                     (3U)
8048 #define CAN_F4R2_FB3_Msk                     (0x1UL << CAN_F4R2_FB3_Pos)        /*!< 0x00000008 */
8049 #define CAN_F4R2_FB3                         CAN_F4R2_FB3_Msk                  /*!< Filter bit 3 */
8050 #define CAN_F4R2_FB4_Pos                     (4U)
8051 #define CAN_F4R2_FB4_Msk                     (0x1UL << CAN_F4R2_FB4_Pos)        /*!< 0x00000010 */
8052 #define CAN_F4R2_FB4                         CAN_F4R2_FB4_Msk                  /*!< Filter bit 4 */
8053 #define CAN_F4R2_FB5_Pos                     (5U)
8054 #define CAN_F4R2_FB5_Msk                     (0x1UL << CAN_F4R2_FB5_Pos)        /*!< 0x00000020 */
8055 #define CAN_F4R2_FB5                         CAN_F4R2_FB5_Msk                  /*!< Filter bit 5 */
8056 #define CAN_F4R2_FB6_Pos                     (6U)
8057 #define CAN_F4R2_FB6_Msk                     (0x1UL << CAN_F4R2_FB6_Pos)        /*!< 0x00000040 */
8058 #define CAN_F4R2_FB6                         CAN_F4R2_FB6_Msk                  /*!< Filter bit 6 */
8059 #define CAN_F4R2_FB7_Pos                     (7U)
8060 #define CAN_F4R2_FB7_Msk                     (0x1UL << CAN_F4R2_FB7_Pos)        /*!< 0x00000080 */
8061 #define CAN_F4R2_FB7                         CAN_F4R2_FB7_Msk                  /*!< Filter bit 7 */
8062 #define CAN_F4R2_FB8_Pos                     (8U)
8063 #define CAN_F4R2_FB8_Msk                     (0x1UL << CAN_F4R2_FB8_Pos)        /*!< 0x00000100 */
8064 #define CAN_F4R2_FB8                         CAN_F4R2_FB8_Msk                  /*!< Filter bit 8 */
8065 #define CAN_F4R2_FB9_Pos                     (9U)
8066 #define CAN_F4R2_FB9_Msk                     (0x1UL << CAN_F4R2_FB9_Pos)        /*!< 0x00000200 */
8067 #define CAN_F4R2_FB9                         CAN_F4R2_FB9_Msk                  /*!< Filter bit 9 */
8068 #define CAN_F4R2_FB10_Pos                    (10U)
8069 #define CAN_F4R2_FB10_Msk                    (0x1UL << CAN_F4R2_FB10_Pos)       /*!< 0x00000400 */
8070 #define CAN_F4R2_FB10                        CAN_F4R2_FB10_Msk                 /*!< Filter bit 10 */
8071 #define CAN_F4R2_FB11_Pos                    (11U)
8072 #define CAN_F4R2_FB11_Msk                    (0x1UL << CAN_F4R2_FB11_Pos)       /*!< 0x00000800 */
8073 #define CAN_F4R2_FB11                        CAN_F4R2_FB11_Msk                 /*!< Filter bit 11 */
8074 #define CAN_F4R2_FB12_Pos                    (12U)
8075 #define CAN_F4R2_FB12_Msk                    (0x1UL << CAN_F4R2_FB12_Pos)       /*!< 0x00001000 */
8076 #define CAN_F4R2_FB12                        CAN_F4R2_FB12_Msk                 /*!< Filter bit 12 */
8077 #define CAN_F4R2_FB13_Pos                    (13U)
8078 #define CAN_F4R2_FB13_Msk                    (0x1UL << CAN_F4R2_FB13_Pos)       /*!< 0x00002000 */
8079 #define CAN_F4R2_FB13                        CAN_F4R2_FB13_Msk                 /*!< Filter bit 13 */
8080 #define CAN_F4R2_FB14_Pos                    (14U)
8081 #define CAN_F4R2_FB14_Msk                    (0x1UL << CAN_F4R2_FB14_Pos)       /*!< 0x00004000 */
8082 #define CAN_F4R2_FB14                        CAN_F4R2_FB14_Msk                 /*!< Filter bit 14 */
8083 #define CAN_F4R2_FB15_Pos                    (15U)
8084 #define CAN_F4R2_FB15_Msk                    (0x1UL << CAN_F4R2_FB15_Pos)       /*!< 0x00008000 */
8085 #define CAN_F4R2_FB15                        CAN_F4R2_FB15_Msk                 /*!< Filter bit 15 */
8086 #define CAN_F4R2_FB16_Pos                    (16U)
8087 #define CAN_F4R2_FB16_Msk                    (0x1UL << CAN_F4R2_FB16_Pos)       /*!< 0x00010000 */
8088 #define CAN_F4R2_FB16                        CAN_F4R2_FB16_Msk                 /*!< Filter bit 16 */
8089 #define CAN_F4R2_FB17_Pos                    (17U)
8090 #define CAN_F4R2_FB17_Msk                    (0x1UL << CAN_F4R2_FB17_Pos)       /*!< 0x00020000 */
8091 #define CAN_F4R2_FB17                        CAN_F4R2_FB17_Msk                 /*!< Filter bit 17 */
8092 #define CAN_F4R2_FB18_Pos                    (18U)
8093 #define CAN_F4R2_FB18_Msk                    (0x1UL << CAN_F4R2_FB18_Pos)       /*!< 0x00040000 */
8094 #define CAN_F4R2_FB18                        CAN_F4R2_FB18_Msk                 /*!< Filter bit 18 */
8095 #define CAN_F4R2_FB19_Pos                    (19U)
8096 #define CAN_F4R2_FB19_Msk                    (0x1UL << CAN_F4R2_FB19_Pos)       /*!< 0x00080000 */
8097 #define CAN_F4R2_FB19                        CAN_F4R2_FB19_Msk                 /*!< Filter bit 19 */
8098 #define CAN_F4R2_FB20_Pos                    (20U)
8099 #define CAN_F4R2_FB20_Msk                    (0x1UL << CAN_F4R2_FB20_Pos)       /*!< 0x00100000 */
8100 #define CAN_F4R2_FB20                        CAN_F4R2_FB20_Msk                 /*!< Filter bit 20 */
8101 #define CAN_F4R2_FB21_Pos                    (21U)
8102 #define CAN_F4R2_FB21_Msk                    (0x1UL << CAN_F4R2_FB21_Pos)       /*!< 0x00200000 */
8103 #define CAN_F4R2_FB21                        CAN_F4R2_FB21_Msk                 /*!< Filter bit 21 */
8104 #define CAN_F4R2_FB22_Pos                    (22U)
8105 #define CAN_F4R2_FB22_Msk                    (0x1UL << CAN_F4R2_FB22_Pos)       /*!< 0x00400000 */
8106 #define CAN_F4R2_FB22                        CAN_F4R2_FB22_Msk                 /*!< Filter bit 22 */
8107 #define CAN_F4R2_FB23_Pos                    (23U)
8108 #define CAN_F4R2_FB23_Msk                    (0x1UL << CAN_F4R2_FB23_Pos)       /*!< 0x00800000 */
8109 #define CAN_F4R2_FB23                        CAN_F4R2_FB23_Msk                 /*!< Filter bit 23 */
8110 #define CAN_F4R2_FB24_Pos                    (24U)
8111 #define CAN_F4R2_FB24_Msk                    (0x1UL << CAN_F4R2_FB24_Pos)       /*!< 0x01000000 */
8112 #define CAN_F4R2_FB24                        CAN_F4R2_FB24_Msk                 /*!< Filter bit 24 */
8113 #define CAN_F4R2_FB25_Pos                    (25U)
8114 #define CAN_F4R2_FB25_Msk                    (0x1UL << CAN_F4R2_FB25_Pos)       /*!< 0x02000000 */
8115 #define CAN_F4R2_FB25                        CAN_F4R2_FB25_Msk                 /*!< Filter bit 25 */
8116 #define CAN_F4R2_FB26_Pos                    (26U)
8117 #define CAN_F4R2_FB26_Msk                    (0x1UL << CAN_F4R2_FB26_Pos)       /*!< 0x04000000 */
8118 #define CAN_F4R2_FB26                        CAN_F4R2_FB26_Msk                 /*!< Filter bit 26 */
8119 #define CAN_F4R2_FB27_Pos                    (27U)
8120 #define CAN_F4R2_FB27_Msk                    (0x1UL << CAN_F4R2_FB27_Pos)       /*!< 0x08000000 */
8121 #define CAN_F4R2_FB27                        CAN_F4R2_FB27_Msk                 /*!< Filter bit 27 */
8122 #define CAN_F4R2_FB28_Pos                    (28U)
8123 #define CAN_F4R2_FB28_Msk                    (0x1UL << CAN_F4R2_FB28_Pos)       /*!< 0x10000000 */
8124 #define CAN_F4R2_FB28                        CAN_F4R2_FB28_Msk                 /*!< Filter bit 28 */
8125 #define CAN_F4R2_FB29_Pos                    (29U)
8126 #define CAN_F4R2_FB29_Msk                    (0x1UL << CAN_F4R2_FB29_Pos)       /*!< 0x20000000 */
8127 #define CAN_F4R2_FB29                        CAN_F4R2_FB29_Msk                 /*!< Filter bit 29 */
8128 #define CAN_F4R2_FB30_Pos                    (30U)
8129 #define CAN_F4R2_FB30_Msk                    (0x1UL << CAN_F4R2_FB30_Pos)       /*!< 0x40000000 */
8130 #define CAN_F4R2_FB30                        CAN_F4R2_FB30_Msk                 /*!< Filter bit 30 */
8131 #define CAN_F4R2_FB31_Pos                    (31U)
8132 #define CAN_F4R2_FB31_Msk                    (0x1UL << CAN_F4R2_FB31_Pos)       /*!< 0x80000000 */
8133 #define CAN_F4R2_FB31                        CAN_F4R2_FB31_Msk                 /*!< Filter bit 31 */
8134 
8135 /*******************  Bit definition for CAN_F5R2 register  *******************/
8136 #define CAN_F5R2_FB0_Pos                     (0U)
8137 #define CAN_F5R2_FB0_Msk                     (0x1UL << CAN_F5R2_FB0_Pos)        /*!< 0x00000001 */
8138 #define CAN_F5R2_FB0                         CAN_F5R2_FB0_Msk                  /*!< Filter bit 0 */
8139 #define CAN_F5R2_FB1_Pos                     (1U)
8140 #define CAN_F5R2_FB1_Msk                     (0x1UL << CAN_F5R2_FB1_Pos)        /*!< 0x00000002 */
8141 #define CAN_F5R2_FB1                         CAN_F5R2_FB1_Msk                  /*!< Filter bit 1 */
8142 #define CAN_F5R2_FB2_Pos                     (2U)
8143 #define CAN_F5R2_FB2_Msk                     (0x1UL << CAN_F5R2_FB2_Pos)        /*!< 0x00000004 */
8144 #define CAN_F5R2_FB2                         CAN_F5R2_FB2_Msk                  /*!< Filter bit 2 */
8145 #define CAN_F5R2_FB3_Pos                     (3U)
8146 #define CAN_F5R2_FB3_Msk                     (0x1UL << CAN_F5R2_FB3_Pos)        /*!< 0x00000008 */
8147 #define CAN_F5R2_FB3                         CAN_F5R2_FB3_Msk                  /*!< Filter bit 3 */
8148 #define CAN_F5R2_FB4_Pos                     (4U)
8149 #define CAN_F5R2_FB4_Msk                     (0x1UL << CAN_F5R2_FB4_Pos)        /*!< 0x00000010 */
8150 #define CAN_F5R2_FB4                         CAN_F5R2_FB4_Msk                  /*!< Filter bit 4 */
8151 #define CAN_F5R2_FB5_Pos                     (5U)
8152 #define CAN_F5R2_FB5_Msk                     (0x1UL << CAN_F5R2_FB5_Pos)        /*!< 0x00000020 */
8153 #define CAN_F5R2_FB5                         CAN_F5R2_FB5_Msk                  /*!< Filter bit 5 */
8154 #define CAN_F5R2_FB6_Pos                     (6U)
8155 #define CAN_F5R2_FB6_Msk                     (0x1UL << CAN_F5R2_FB6_Pos)        /*!< 0x00000040 */
8156 #define CAN_F5R2_FB6                         CAN_F5R2_FB6_Msk                  /*!< Filter bit 6 */
8157 #define CAN_F5R2_FB7_Pos                     (7U)
8158 #define CAN_F5R2_FB7_Msk                     (0x1UL << CAN_F5R2_FB7_Pos)        /*!< 0x00000080 */
8159 #define CAN_F5R2_FB7                         CAN_F5R2_FB7_Msk                  /*!< Filter bit 7 */
8160 #define CAN_F5R2_FB8_Pos                     (8U)
8161 #define CAN_F5R2_FB8_Msk                     (0x1UL << CAN_F5R2_FB8_Pos)        /*!< 0x00000100 */
8162 #define CAN_F5R2_FB8                         CAN_F5R2_FB8_Msk                  /*!< Filter bit 8 */
8163 #define CAN_F5R2_FB9_Pos                     (9U)
8164 #define CAN_F5R2_FB9_Msk                     (0x1UL << CAN_F5R2_FB9_Pos)        /*!< 0x00000200 */
8165 #define CAN_F5R2_FB9                         CAN_F5R2_FB9_Msk                  /*!< Filter bit 9 */
8166 #define CAN_F5R2_FB10_Pos                    (10U)
8167 #define CAN_F5R2_FB10_Msk                    (0x1UL << CAN_F5R2_FB10_Pos)       /*!< 0x00000400 */
8168 #define CAN_F5R2_FB10                        CAN_F5R2_FB10_Msk                 /*!< Filter bit 10 */
8169 #define CAN_F5R2_FB11_Pos                    (11U)
8170 #define CAN_F5R2_FB11_Msk                    (0x1UL << CAN_F5R2_FB11_Pos)       /*!< 0x00000800 */
8171 #define CAN_F5R2_FB11                        CAN_F5R2_FB11_Msk                 /*!< Filter bit 11 */
8172 #define CAN_F5R2_FB12_Pos                    (12U)
8173 #define CAN_F5R2_FB12_Msk                    (0x1UL << CAN_F5R2_FB12_Pos)       /*!< 0x00001000 */
8174 #define CAN_F5R2_FB12                        CAN_F5R2_FB12_Msk                 /*!< Filter bit 12 */
8175 #define CAN_F5R2_FB13_Pos                    (13U)
8176 #define CAN_F5R2_FB13_Msk                    (0x1UL << CAN_F5R2_FB13_Pos)       /*!< 0x00002000 */
8177 #define CAN_F5R2_FB13                        CAN_F5R2_FB13_Msk                 /*!< Filter bit 13 */
8178 #define CAN_F5R2_FB14_Pos                    (14U)
8179 #define CAN_F5R2_FB14_Msk                    (0x1UL << CAN_F5R2_FB14_Pos)       /*!< 0x00004000 */
8180 #define CAN_F5R2_FB14                        CAN_F5R2_FB14_Msk                 /*!< Filter bit 14 */
8181 #define CAN_F5R2_FB15_Pos                    (15U)
8182 #define CAN_F5R2_FB15_Msk                    (0x1UL << CAN_F5R2_FB15_Pos)       /*!< 0x00008000 */
8183 #define CAN_F5R2_FB15                        CAN_F5R2_FB15_Msk                 /*!< Filter bit 15 */
8184 #define CAN_F5R2_FB16_Pos                    (16U)
8185 #define CAN_F5R2_FB16_Msk                    (0x1UL << CAN_F5R2_FB16_Pos)       /*!< 0x00010000 */
8186 #define CAN_F5R2_FB16                        CAN_F5R2_FB16_Msk                 /*!< Filter bit 16 */
8187 #define CAN_F5R2_FB17_Pos                    (17U)
8188 #define CAN_F5R2_FB17_Msk                    (0x1UL << CAN_F5R2_FB17_Pos)       /*!< 0x00020000 */
8189 #define CAN_F5R2_FB17                        CAN_F5R2_FB17_Msk                 /*!< Filter bit 17 */
8190 #define CAN_F5R2_FB18_Pos                    (18U)
8191 #define CAN_F5R2_FB18_Msk                    (0x1UL << CAN_F5R2_FB18_Pos)       /*!< 0x00040000 */
8192 #define CAN_F5R2_FB18                        CAN_F5R2_FB18_Msk                 /*!< Filter bit 18 */
8193 #define CAN_F5R2_FB19_Pos                    (19U)
8194 #define CAN_F5R2_FB19_Msk                    (0x1UL << CAN_F5R2_FB19_Pos)       /*!< 0x00080000 */
8195 #define CAN_F5R2_FB19                        CAN_F5R2_FB19_Msk                 /*!< Filter bit 19 */
8196 #define CAN_F5R2_FB20_Pos                    (20U)
8197 #define CAN_F5R2_FB20_Msk                    (0x1UL << CAN_F5R2_FB20_Pos)       /*!< 0x00100000 */
8198 #define CAN_F5R2_FB20                        CAN_F5R2_FB20_Msk                 /*!< Filter bit 20 */
8199 #define CAN_F5R2_FB21_Pos                    (21U)
8200 #define CAN_F5R2_FB21_Msk                    (0x1UL << CAN_F5R2_FB21_Pos)       /*!< 0x00200000 */
8201 #define CAN_F5R2_FB21                        CAN_F5R2_FB21_Msk                 /*!< Filter bit 21 */
8202 #define CAN_F5R2_FB22_Pos                    (22U)
8203 #define CAN_F5R2_FB22_Msk                    (0x1UL << CAN_F5R2_FB22_Pos)       /*!< 0x00400000 */
8204 #define CAN_F5R2_FB22                        CAN_F5R2_FB22_Msk                 /*!< Filter bit 22 */
8205 #define CAN_F5R2_FB23_Pos                    (23U)
8206 #define CAN_F5R2_FB23_Msk                    (0x1UL << CAN_F5R2_FB23_Pos)       /*!< 0x00800000 */
8207 #define CAN_F5R2_FB23                        CAN_F5R2_FB23_Msk                 /*!< Filter bit 23 */
8208 #define CAN_F5R2_FB24_Pos                    (24U)
8209 #define CAN_F5R2_FB24_Msk                    (0x1UL << CAN_F5R2_FB24_Pos)       /*!< 0x01000000 */
8210 #define CAN_F5R2_FB24                        CAN_F5R2_FB24_Msk                 /*!< Filter bit 24 */
8211 #define CAN_F5R2_FB25_Pos                    (25U)
8212 #define CAN_F5R2_FB25_Msk                    (0x1UL << CAN_F5R2_FB25_Pos)       /*!< 0x02000000 */
8213 #define CAN_F5R2_FB25                        CAN_F5R2_FB25_Msk                 /*!< Filter bit 25 */
8214 #define CAN_F5R2_FB26_Pos                    (26U)
8215 #define CAN_F5R2_FB26_Msk                    (0x1UL << CAN_F5R2_FB26_Pos)       /*!< 0x04000000 */
8216 #define CAN_F5R2_FB26                        CAN_F5R2_FB26_Msk                 /*!< Filter bit 26 */
8217 #define CAN_F5R2_FB27_Pos                    (27U)
8218 #define CAN_F5R2_FB27_Msk                    (0x1UL << CAN_F5R2_FB27_Pos)       /*!< 0x08000000 */
8219 #define CAN_F5R2_FB27                        CAN_F5R2_FB27_Msk                 /*!< Filter bit 27 */
8220 #define CAN_F5R2_FB28_Pos                    (28U)
8221 #define CAN_F5R2_FB28_Msk                    (0x1UL << CAN_F5R2_FB28_Pos)       /*!< 0x10000000 */
8222 #define CAN_F5R2_FB28                        CAN_F5R2_FB28_Msk                 /*!< Filter bit 28 */
8223 #define CAN_F5R2_FB29_Pos                    (29U)
8224 #define CAN_F5R2_FB29_Msk                    (0x1UL << CAN_F5R2_FB29_Pos)       /*!< 0x20000000 */
8225 #define CAN_F5R2_FB29                        CAN_F5R2_FB29_Msk                 /*!< Filter bit 29 */
8226 #define CAN_F5R2_FB30_Pos                    (30U)
8227 #define CAN_F5R2_FB30_Msk                    (0x1UL << CAN_F5R2_FB30_Pos)       /*!< 0x40000000 */
8228 #define CAN_F5R2_FB30                        CAN_F5R2_FB30_Msk                 /*!< Filter bit 30 */
8229 #define CAN_F5R2_FB31_Pos                    (31U)
8230 #define CAN_F5R2_FB31_Msk                    (0x1UL << CAN_F5R2_FB31_Pos)       /*!< 0x80000000 */
8231 #define CAN_F5R2_FB31                        CAN_F5R2_FB31_Msk                 /*!< Filter bit 31 */
8232 
8233 /*******************  Bit definition for CAN_F6R2 register  *******************/
8234 #define CAN_F6R2_FB0_Pos                     (0U)
8235 #define CAN_F6R2_FB0_Msk                     (0x1UL << CAN_F6R2_FB0_Pos)        /*!< 0x00000001 */
8236 #define CAN_F6R2_FB0                         CAN_F6R2_FB0_Msk                  /*!< Filter bit 0 */
8237 #define CAN_F6R2_FB1_Pos                     (1U)
8238 #define CAN_F6R2_FB1_Msk                     (0x1UL << CAN_F6R2_FB1_Pos)        /*!< 0x00000002 */
8239 #define CAN_F6R2_FB1                         CAN_F6R2_FB1_Msk                  /*!< Filter bit 1 */
8240 #define CAN_F6R2_FB2_Pos                     (2U)
8241 #define CAN_F6R2_FB2_Msk                     (0x1UL << CAN_F6R2_FB2_Pos)        /*!< 0x00000004 */
8242 #define CAN_F6R2_FB2                         CAN_F6R2_FB2_Msk                  /*!< Filter bit 2 */
8243 #define CAN_F6R2_FB3_Pos                     (3U)
8244 #define CAN_F6R2_FB3_Msk                     (0x1UL << CAN_F6R2_FB3_Pos)        /*!< 0x00000008 */
8245 #define CAN_F6R2_FB3                         CAN_F6R2_FB3_Msk                  /*!< Filter bit 3 */
8246 #define CAN_F6R2_FB4_Pos                     (4U)
8247 #define CAN_F6R2_FB4_Msk                     (0x1UL << CAN_F6R2_FB4_Pos)        /*!< 0x00000010 */
8248 #define CAN_F6R2_FB4                         CAN_F6R2_FB4_Msk                  /*!< Filter bit 4 */
8249 #define CAN_F6R2_FB5_Pos                     (5U)
8250 #define CAN_F6R2_FB5_Msk                     (0x1UL << CAN_F6R2_FB5_Pos)        /*!< 0x00000020 */
8251 #define CAN_F6R2_FB5                         CAN_F6R2_FB5_Msk                  /*!< Filter bit 5 */
8252 #define CAN_F6R2_FB6_Pos                     (6U)
8253 #define CAN_F6R2_FB6_Msk                     (0x1UL << CAN_F6R2_FB6_Pos)        /*!< 0x00000040 */
8254 #define CAN_F6R2_FB6                         CAN_F6R2_FB6_Msk                  /*!< Filter bit 6 */
8255 #define CAN_F6R2_FB7_Pos                     (7U)
8256 #define CAN_F6R2_FB7_Msk                     (0x1UL << CAN_F6R2_FB7_Pos)        /*!< 0x00000080 */
8257 #define CAN_F6R2_FB7                         CAN_F6R2_FB7_Msk                  /*!< Filter bit 7 */
8258 #define CAN_F6R2_FB8_Pos                     (8U)
8259 #define CAN_F6R2_FB8_Msk                     (0x1UL << CAN_F6R2_FB8_Pos)        /*!< 0x00000100 */
8260 #define CAN_F6R2_FB8                         CAN_F6R2_FB8_Msk                  /*!< Filter bit 8 */
8261 #define CAN_F6R2_FB9_Pos                     (9U)
8262 #define CAN_F6R2_FB9_Msk                     (0x1UL << CAN_F6R2_FB9_Pos)        /*!< 0x00000200 */
8263 #define CAN_F6R2_FB9                         CAN_F6R2_FB9_Msk                  /*!< Filter bit 9 */
8264 #define CAN_F6R2_FB10_Pos                    (10U)
8265 #define CAN_F6R2_FB10_Msk                    (0x1UL << CAN_F6R2_FB10_Pos)       /*!< 0x00000400 */
8266 #define CAN_F6R2_FB10                        CAN_F6R2_FB10_Msk                 /*!< Filter bit 10 */
8267 #define CAN_F6R2_FB11_Pos                    (11U)
8268 #define CAN_F6R2_FB11_Msk                    (0x1UL << CAN_F6R2_FB11_Pos)       /*!< 0x00000800 */
8269 #define CAN_F6R2_FB11                        CAN_F6R2_FB11_Msk                 /*!< Filter bit 11 */
8270 #define CAN_F6R2_FB12_Pos                    (12U)
8271 #define CAN_F6R2_FB12_Msk                    (0x1UL << CAN_F6R2_FB12_Pos)       /*!< 0x00001000 */
8272 #define CAN_F6R2_FB12                        CAN_F6R2_FB12_Msk                 /*!< Filter bit 12 */
8273 #define CAN_F6R2_FB13_Pos                    (13U)
8274 #define CAN_F6R2_FB13_Msk                    (0x1UL << CAN_F6R2_FB13_Pos)       /*!< 0x00002000 */
8275 #define CAN_F6R2_FB13                        CAN_F6R2_FB13_Msk                 /*!< Filter bit 13 */
8276 #define CAN_F6R2_FB14_Pos                    (14U)
8277 #define CAN_F6R2_FB14_Msk                    (0x1UL << CAN_F6R2_FB14_Pos)       /*!< 0x00004000 */
8278 #define CAN_F6R2_FB14                        CAN_F6R2_FB14_Msk                 /*!< Filter bit 14 */
8279 #define CAN_F6R2_FB15_Pos                    (15U)
8280 #define CAN_F6R2_FB15_Msk                    (0x1UL << CAN_F6R2_FB15_Pos)       /*!< 0x00008000 */
8281 #define CAN_F6R2_FB15                        CAN_F6R2_FB15_Msk                 /*!< Filter bit 15 */
8282 #define CAN_F6R2_FB16_Pos                    (16U)
8283 #define CAN_F6R2_FB16_Msk                    (0x1UL << CAN_F6R2_FB16_Pos)       /*!< 0x00010000 */
8284 #define CAN_F6R2_FB16                        CAN_F6R2_FB16_Msk                 /*!< Filter bit 16 */
8285 #define CAN_F6R2_FB17_Pos                    (17U)
8286 #define CAN_F6R2_FB17_Msk                    (0x1UL << CAN_F6R2_FB17_Pos)       /*!< 0x00020000 */
8287 #define CAN_F6R2_FB17                        CAN_F6R2_FB17_Msk                 /*!< Filter bit 17 */
8288 #define CAN_F6R2_FB18_Pos                    (18U)
8289 #define CAN_F6R2_FB18_Msk                    (0x1UL << CAN_F6R2_FB18_Pos)       /*!< 0x00040000 */
8290 #define CAN_F6R2_FB18                        CAN_F6R2_FB18_Msk                 /*!< Filter bit 18 */
8291 #define CAN_F6R2_FB19_Pos                    (19U)
8292 #define CAN_F6R2_FB19_Msk                    (0x1UL << CAN_F6R2_FB19_Pos)       /*!< 0x00080000 */
8293 #define CAN_F6R2_FB19                        CAN_F6R2_FB19_Msk                 /*!< Filter bit 19 */
8294 #define CAN_F6R2_FB20_Pos                    (20U)
8295 #define CAN_F6R2_FB20_Msk                    (0x1UL << CAN_F6R2_FB20_Pos)       /*!< 0x00100000 */
8296 #define CAN_F6R2_FB20                        CAN_F6R2_FB20_Msk                 /*!< Filter bit 20 */
8297 #define CAN_F6R2_FB21_Pos                    (21U)
8298 #define CAN_F6R2_FB21_Msk                    (0x1UL << CAN_F6R2_FB21_Pos)       /*!< 0x00200000 */
8299 #define CAN_F6R2_FB21                        CAN_F6R2_FB21_Msk                 /*!< Filter bit 21 */
8300 #define CAN_F6R2_FB22_Pos                    (22U)
8301 #define CAN_F6R2_FB22_Msk                    (0x1UL << CAN_F6R2_FB22_Pos)       /*!< 0x00400000 */
8302 #define CAN_F6R2_FB22                        CAN_F6R2_FB22_Msk                 /*!< Filter bit 22 */
8303 #define CAN_F6R2_FB23_Pos                    (23U)
8304 #define CAN_F6R2_FB23_Msk                    (0x1UL << CAN_F6R2_FB23_Pos)       /*!< 0x00800000 */
8305 #define CAN_F6R2_FB23                        CAN_F6R2_FB23_Msk                 /*!< Filter bit 23 */
8306 #define CAN_F6R2_FB24_Pos                    (24U)
8307 #define CAN_F6R2_FB24_Msk                    (0x1UL << CAN_F6R2_FB24_Pos)       /*!< 0x01000000 */
8308 #define CAN_F6R2_FB24                        CAN_F6R2_FB24_Msk                 /*!< Filter bit 24 */
8309 #define CAN_F6R2_FB25_Pos                    (25U)
8310 #define CAN_F6R2_FB25_Msk                    (0x1UL << CAN_F6R2_FB25_Pos)       /*!< 0x02000000 */
8311 #define CAN_F6R2_FB25                        CAN_F6R2_FB25_Msk                 /*!< Filter bit 25 */
8312 #define CAN_F6R2_FB26_Pos                    (26U)
8313 #define CAN_F6R2_FB26_Msk                    (0x1UL << CAN_F6R2_FB26_Pos)       /*!< 0x04000000 */
8314 #define CAN_F6R2_FB26                        CAN_F6R2_FB26_Msk                 /*!< Filter bit 26 */
8315 #define CAN_F6R2_FB27_Pos                    (27U)
8316 #define CAN_F6R2_FB27_Msk                    (0x1UL << CAN_F6R2_FB27_Pos)       /*!< 0x08000000 */
8317 #define CAN_F6R2_FB27                        CAN_F6R2_FB27_Msk                 /*!< Filter bit 27 */
8318 #define CAN_F6R2_FB28_Pos                    (28U)
8319 #define CAN_F6R2_FB28_Msk                    (0x1UL << CAN_F6R2_FB28_Pos)       /*!< 0x10000000 */
8320 #define CAN_F6R2_FB28                        CAN_F6R2_FB28_Msk                 /*!< Filter bit 28 */
8321 #define CAN_F6R2_FB29_Pos                    (29U)
8322 #define CAN_F6R2_FB29_Msk                    (0x1UL << CAN_F6R2_FB29_Pos)       /*!< 0x20000000 */
8323 #define CAN_F6R2_FB29                        CAN_F6R2_FB29_Msk                 /*!< Filter bit 29 */
8324 #define CAN_F6R2_FB30_Pos                    (30U)
8325 #define CAN_F6R2_FB30_Msk                    (0x1UL << CAN_F6R2_FB30_Pos)       /*!< 0x40000000 */
8326 #define CAN_F6R2_FB30                        CAN_F6R2_FB30_Msk                 /*!< Filter bit 30 */
8327 #define CAN_F6R2_FB31_Pos                    (31U)
8328 #define CAN_F6R2_FB31_Msk                    (0x1UL << CAN_F6R2_FB31_Pos)       /*!< 0x80000000 */
8329 #define CAN_F6R2_FB31                        CAN_F6R2_FB31_Msk                 /*!< Filter bit 31 */
8330 
8331 /*******************  Bit definition for CAN_F7R2 register  *******************/
8332 #define CAN_F7R2_FB0_Pos                     (0U)
8333 #define CAN_F7R2_FB0_Msk                     (0x1UL << CAN_F7R2_FB0_Pos)        /*!< 0x00000001 */
8334 #define CAN_F7R2_FB0                         CAN_F7R2_FB0_Msk                  /*!< Filter bit 0 */
8335 #define CAN_F7R2_FB1_Pos                     (1U)
8336 #define CAN_F7R2_FB1_Msk                     (0x1UL << CAN_F7R2_FB1_Pos)        /*!< 0x00000002 */
8337 #define CAN_F7R2_FB1                         CAN_F7R2_FB1_Msk                  /*!< Filter bit 1 */
8338 #define CAN_F7R2_FB2_Pos                     (2U)
8339 #define CAN_F7R2_FB2_Msk                     (0x1UL << CAN_F7R2_FB2_Pos)        /*!< 0x00000004 */
8340 #define CAN_F7R2_FB2                         CAN_F7R2_FB2_Msk                  /*!< Filter bit 2 */
8341 #define CAN_F7R2_FB3_Pos                     (3U)
8342 #define CAN_F7R2_FB3_Msk                     (0x1UL << CAN_F7R2_FB3_Pos)        /*!< 0x00000008 */
8343 #define CAN_F7R2_FB3                         CAN_F7R2_FB3_Msk                  /*!< Filter bit 3 */
8344 #define CAN_F7R2_FB4_Pos                     (4U)
8345 #define CAN_F7R2_FB4_Msk                     (0x1UL << CAN_F7R2_FB4_Pos)        /*!< 0x00000010 */
8346 #define CAN_F7R2_FB4                         CAN_F7R2_FB4_Msk                  /*!< Filter bit 4 */
8347 #define CAN_F7R2_FB5_Pos                     (5U)
8348 #define CAN_F7R2_FB5_Msk                     (0x1UL << CAN_F7R2_FB5_Pos)        /*!< 0x00000020 */
8349 #define CAN_F7R2_FB5                         CAN_F7R2_FB5_Msk                  /*!< Filter bit 5 */
8350 #define CAN_F7R2_FB6_Pos                     (6U)
8351 #define CAN_F7R2_FB6_Msk                     (0x1UL << CAN_F7R2_FB6_Pos)        /*!< 0x00000040 */
8352 #define CAN_F7R2_FB6                         CAN_F7R2_FB6_Msk                  /*!< Filter bit 6 */
8353 #define CAN_F7R2_FB7_Pos                     (7U)
8354 #define CAN_F7R2_FB7_Msk                     (0x1UL << CAN_F7R2_FB7_Pos)        /*!< 0x00000080 */
8355 #define CAN_F7R2_FB7                         CAN_F7R2_FB7_Msk                  /*!< Filter bit 7 */
8356 #define CAN_F7R2_FB8_Pos                     (8U)
8357 #define CAN_F7R2_FB8_Msk                     (0x1UL << CAN_F7R2_FB8_Pos)        /*!< 0x00000100 */
8358 #define CAN_F7R2_FB8                         CAN_F7R2_FB8_Msk                  /*!< Filter bit 8 */
8359 #define CAN_F7R2_FB9_Pos                     (9U)
8360 #define CAN_F7R2_FB9_Msk                     (0x1UL << CAN_F7R2_FB9_Pos)        /*!< 0x00000200 */
8361 #define CAN_F7R2_FB9                         CAN_F7R2_FB9_Msk                  /*!< Filter bit 9 */
8362 #define CAN_F7R2_FB10_Pos                    (10U)
8363 #define CAN_F7R2_FB10_Msk                    (0x1UL << CAN_F7R2_FB10_Pos)       /*!< 0x00000400 */
8364 #define CAN_F7R2_FB10                        CAN_F7R2_FB10_Msk                 /*!< Filter bit 10 */
8365 #define CAN_F7R2_FB11_Pos                    (11U)
8366 #define CAN_F7R2_FB11_Msk                    (0x1UL << CAN_F7R2_FB11_Pos)       /*!< 0x00000800 */
8367 #define CAN_F7R2_FB11                        CAN_F7R2_FB11_Msk                 /*!< Filter bit 11 */
8368 #define CAN_F7R2_FB12_Pos                    (12U)
8369 #define CAN_F7R2_FB12_Msk                    (0x1UL << CAN_F7R2_FB12_Pos)       /*!< 0x00001000 */
8370 #define CAN_F7R2_FB12                        CAN_F7R2_FB12_Msk                 /*!< Filter bit 12 */
8371 #define CAN_F7R2_FB13_Pos                    (13U)
8372 #define CAN_F7R2_FB13_Msk                    (0x1UL << CAN_F7R2_FB13_Pos)       /*!< 0x00002000 */
8373 #define CAN_F7R2_FB13                        CAN_F7R2_FB13_Msk                 /*!< Filter bit 13 */
8374 #define CAN_F7R2_FB14_Pos                    (14U)
8375 #define CAN_F7R2_FB14_Msk                    (0x1UL << CAN_F7R2_FB14_Pos)       /*!< 0x00004000 */
8376 #define CAN_F7R2_FB14                        CAN_F7R2_FB14_Msk                 /*!< Filter bit 14 */
8377 #define CAN_F7R2_FB15_Pos                    (15U)
8378 #define CAN_F7R2_FB15_Msk                    (0x1UL << CAN_F7R2_FB15_Pos)       /*!< 0x00008000 */
8379 #define CAN_F7R2_FB15                        CAN_F7R2_FB15_Msk                 /*!< Filter bit 15 */
8380 #define CAN_F7R2_FB16_Pos                    (16U)
8381 #define CAN_F7R2_FB16_Msk                    (0x1UL << CAN_F7R2_FB16_Pos)       /*!< 0x00010000 */
8382 #define CAN_F7R2_FB16                        CAN_F7R2_FB16_Msk                 /*!< Filter bit 16 */
8383 #define CAN_F7R2_FB17_Pos                    (17U)
8384 #define CAN_F7R2_FB17_Msk                    (0x1UL << CAN_F7R2_FB17_Pos)       /*!< 0x00020000 */
8385 #define CAN_F7R2_FB17                        CAN_F7R2_FB17_Msk                 /*!< Filter bit 17 */
8386 #define CAN_F7R2_FB18_Pos                    (18U)
8387 #define CAN_F7R2_FB18_Msk                    (0x1UL << CAN_F7R2_FB18_Pos)       /*!< 0x00040000 */
8388 #define CAN_F7R2_FB18                        CAN_F7R2_FB18_Msk                 /*!< Filter bit 18 */
8389 #define CAN_F7R2_FB19_Pos                    (19U)
8390 #define CAN_F7R2_FB19_Msk                    (0x1UL << CAN_F7R2_FB19_Pos)       /*!< 0x00080000 */
8391 #define CAN_F7R2_FB19                        CAN_F7R2_FB19_Msk                 /*!< Filter bit 19 */
8392 #define CAN_F7R2_FB20_Pos                    (20U)
8393 #define CAN_F7R2_FB20_Msk                    (0x1UL << CAN_F7R2_FB20_Pos)       /*!< 0x00100000 */
8394 #define CAN_F7R2_FB20                        CAN_F7R2_FB20_Msk                 /*!< Filter bit 20 */
8395 #define CAN_F7R2_FB21_Pos                    (21U)
8396 #define CAN_F7R2_FB21_Msk                    (0x1UL << CAN_F7R2_FB21_Pos)       /*!< 0x00200000 */
8397 #define CAN_F7R2_FB21                        CAN_F7R2_FB21_Msk                 /*!< Filter bit 21 */
8398 #define CAN_F7R2_FB22_Pos                    (22U)
8399 #define CAN_F7R2_FB22_Msk                    (0x1UL << CAN_F7R2_FB22_Pos)       /*!< 0x00400000 */
8400 #define CAN_F7R2_FB22                        CAN_F7R2_FB22_Msk                 /*!< Filter bit 22 */
8401 #define CAN_F7R2_FB23_Pos                    (23U)
8402 #define CAN_F7R2_FB23_Msk                    (0x1UL << CAN_F7R2_FB23_Pos)       /*!< 0x00800000 */
8403 #define CAN_F7R2_FB23                        CAN_F7R2_FB23_Msk                 /*!< Filter bit 23 */
8404 #define CAN_F7R2_FB24_Pos                    (24U)
8405 #define CAN_F7R2_FB24_Msk                    (0x1UL << CAN_F7R2_FB24_Pos)       /*!< 0x01000000 */
8406 #define CAN_F7R2_FB24                        CAN_F7R2_FB24_Msk                 /*!< Filter bit 24 */
8407 #define CAN_F7R2_FB25_Pos                    (25U)
8408 #define CAN_F7R2_FB25_Msk                    (0x1UL << CAN_F7R2_FB25_Pos)       /*!< 0x02000000 */
8409 #define CAN_F7R2_FB25                        CAN_F7R2_FB25_Msk                 /*!< Filter bit 25 */
8410 #define CAN_F7R2_FB26_Pos                    (26U)
8411 #define CAN_F7R2_FB26_Msk                    (0x1UL << CAN_F7R2_FB26_Pos)       /*!< 0x04000000 */
8412 #define CAN_F7R2_FB26                        CAN_F7R2_FB26_Msk                 /*!< Filter bit 26 */
8413 #define CAN_F7R2_FB27_Pos                    (27U)
8414 #define CAN_F7R2_FB27_Msk                    (0x1UL << CAN_F7R2_FB27_Pos)       /*!< 0x08000000 */
8415 #define CAN_F7R2_FB27                        CAN_F7R2_FB27_Msk                 /*!< Filter bit 27 */
8416 #define CAN_F7R2_FB28_Pos                    (28U)
8417 #define CAN_F7R2_FB28_Msk                    (0x1UL << CAN_F7R2_FB28_Pos)       /*!< 0x10000000 */
8418 #define CAN_F7R2_FB28                        CAN_F7R2_FB28_Msk                 /*!< Filter bit 28 */
8419 #define CAN_F7R2_FB29_Pos                    (29U)
8420 #define CAN_F7R2_FB29_Msk                    (0x1UL << CAN_F7R2_FB29_Pos)       /*!< 0x20000000 */
8421 #define CAN_F7R2_FB29                        CAN_F7R2_FB29_Msk                 /*!< Filter bit 29 */
8422 #define CAN_F7R2_FB30_Pos                    (30U)
8423 #define CAN_F7R2_FB30_Msk                    (0x1UL << CAN_F7R2_FB30_Pos)       /*!< 0x40000000 */
8424 #define CAN_F7R2_FB30                        CAN_F7R2_FB30_Msk                 /*!< Filter bit 30 */
8425 #define CAN_F7R2_FB31_Pos                    (31U)
8426 #define CAN_F7R2_FB31_Msk                    (0x1UL << CAN_F7R2_FB31_Pos)       /*!< 0x80000000 */
8427 #define CAN_F7R2_FB31                        CAN_F7R2_FB31_Msk                 /*!< Filter bit 31 */
8428 
8429 /*******************  Bit definition for CAN_F8R2 register  *******************/
8430 #define CAN_F8R2_FB0_Pos                     (0U)
8431 #define CAN_F8R2_FB0_Msk                     (0x1UL << CAN_F8R2_FB0_Pos)        /*!< 0x00000001 */
8432 #define CAN_F8R2_FB0                         CAN_F8R2_FB0_Msk                  /*!< Filter bit 0 */
8433 #define CAN_F8R2_FB1_Pos                     (1U)
8434 #define CAN_F8R2_FB1_Msk                     (0x1UL << CAN_F8R2_FB1_Pos)        /*!< 0x00000002 */
8435 #define CAN_F8R2_FB1                         CAN_F8R2_FB1_Msk                  /*!< Filter bit 1 */
8436 #define CAN_F8R2_FB2_Pos                     (2U)
8437 #define CAN_F8R2_FB2_Msk                     (0x1UL << CAN_F8R2_FB2_Pos)        /*!< 0x00000004 */
8438 #define CAN_F8R2_FB2                         CAN_F8R2_FB2_Msk                  /*!< Filter bit 2 */
8439 #define CAN_F8R2_FB3_Pos                     (3U)
8440 #define CAN_F8R2_FB3_Msk                     (0x1UL << CAN_F8R2_FB3_Pos)        /*!< 0x00000008 */
8441 #define CAN_F8R2_FB3                         CAN_F8R2_FB3_Msk                  /*!< Filter bit 3 */
8442 #define CAN_F8R2_FB4_Pos                     (4U)
8443 #define CAN_F8R2_FB4_Msk                     (0x1UL << CAN_F8R2_FB4_Pos)        /*!< 0x00000010 */
8444 #define CAN_F8R2_FB4                         CAN_F8R2_FB4_Msk                  /*!< Filter bit 4 */
8445 #define CAN_F8R2_FB5_Pos                     (5U)
8446 #define CAN_F8R2_FB5_Msk                     (0x1UL << CAN_F8R2_FB5_Pos)        /*!< 0x00000020 */
8447 #define CAN_F8R2_FB5                         CAN_F8R2_FB5_Msk                  /*!< Filter bit 5 */
8448 #define CAN_F8R2_FB6_Pos                     (6U)
8449 #define CAN_F8R2_FB6_Msk                     (0x1UL << CAN_F8R2_FB6_Pos)        /*!< 0x00000040 */
8450 #define CAN_F8R2_FB6                         CAN_F8R2_FB6_Msk                  /*!< Filter bit 6 */
8451 #define CAN_F8R2_FB7_Pos                     (7U)
8452 #define CAN_F8R2_FB7_Msk                     (0x1UL << CAN_F8R2_FB7_Pos)        /*!< 0x00000080 */
8453 #define CAN_F8R2_FB7                         CAN_F8R2_FB7_Msk                  /*!< Filter bit 7 */
8454 #define CAN_F8R2_FB8_Pos                     (8U)
8455 #define CAN_F8R2_FB8_Msk                     (0x1UL << CAN_F8R2_FB8_Pos)        /*!< 0x00000100 */
8456 #define CAN_F8R2_FB8                         CAN_F8R2_FB8_Msk                  /*!< Filter bit 8 */
8457 #define CAN_F8R2_FB9_Pos                     (9U)
8458 #define CAN_F8R2_FB9_Msk                     (0x1UL << CAN_F8R2_FB9_Pos)        /*!< 0x00000200 */
8459 #define CAN_F8R2_FB9                         CAN_F8R2_FB9_Msk                  /*!< Filter bit 9 */
8460 #define CAN_F8R2_FB10_Pos                    (10U)
8461 #define CAN_F8R2_FB10_Msk                    (0x1UL << CAN_F8R2_FB10_Pos)       /*!< 0x00000400 */
8462 #define CAN_F8R2_FB10                        CAN_F8R2_FB10_Msk                 /*!< Filter bit 10 */
8463 #define CAN_F8R2_FB11_Pos                    (11U)
8464 #define CAN_F8R2_FB11_Msk                    (0x1UL << CAN_F8R2_FB11_Pos)       /*!< 0x00000800 */
8465 #define CAN_F8R2_FB11                        CAN_F8R2_FB11_Msk                 /*!< Filter bit 11 */
8466 #define CAN_F8R2_FB12_Pos                    (12U)
8467 #define CAN_F8R2_FB12_Msk                    (0x1UL << CAN_F8R2_FB12_Pos)       /*!< 0x00001000 */
8468 #define CAN_F8R2_FB12                        CAN_F8R2_FB12_Msk                 /*!< Filter bit 12 */
8469 #define CAN_F8R2_FB13_Pos                    (13U)
8470 #define CAN_F8R2_FB13_Msk                    (0x1UL << CAN_F8R2_FB13_Pos)       /*!< 0x00002000 */
8471 #define CAN_F8R2_FB13                        CAN_F8R2_FB13_Msk                 /*!< Filter bit 13 */
8472 #define CAN_F8R2_FB14_Pos                    (14U)
8473 #define CAN_F8R2_FB14_Msk                    (0x1UL << CAN_F8R2_FB14_Pos)       /*!< 0x00004000 */
8474 #define CAN_F8R2_FB14                        CAN_F8R2_FB14_Msk                 /*!< Filter bit 14 */
8475 #define CAN_F8R2_FB15_Pos                    (15U)
8476 #define CAN_F8R2_FB15_Msk                    (0x1UL << CAN_F8R2_FB15_Pos)       /*!< 0x00008000 */
8477 #define CAN_F8R2_FB15                        CAN_F8R2_FB15_Msk                 /*!< Filter bit 15 */
8478 #define CAN_F8R2_FB16_Pos                    (16U)
8479 #define CAN_F8R2_FB16_Msk                    (0x1UL << CAN_F8R2_FB16_Pos)       /*!< 0x00010000 */
8480 #define CAN_F8R2_FB16                        CAN_F8R2_FB16_Msk                 /*!< Filter bit 16 */
8481 #define CAN_F8R2_FB17_Pos                    (17U)
8482 #define CAN_F8R2_FB17_Msk                    (0x1UL << CAN_F8R2_FB17_Pos)       /*!< 0x00020000 */
8483 #define CAN_F8R2_FB17                        CAN_F8R2_FB17_Msk                 /*!< Filter bit 17 */
8484 #define CAN_F8R2_FB18_Pos                    (18U)
8485 #define CAN_F8R2_FB18_Msk                    (0x1UL << CAN_F8R2_FB18_Pos)       /*!< 0x00040000 */
8486 #define CAN_F8R2_FB18                        CAN_F8R2_FB18_Msk                 /*!< Filter bit 18 */
8487 #define CAN_F8R2_FB19_Pos                    (19U)
8488 #define CAN_F8R2_FB19_Msk                    (0x1UL << CAN_F8R2_FB19_Pos)       /*!< 0x00080000 */
8489 #define CAN_F8R2_FB19                        CAN_F8R2_FB19_Msk                 /*!< Filter bit 19 */
8490 #define CAN_F8R2_FB20_Pos                    (20U)
8491 #define CAN_F8R2_FB20_Msk                    (0x1UL << CAN_F8R2_FB20_Pos)       /*!< 0x00100000 */
8492 #define CAN_F8R2_FB20                        CAN_F8R2_FB20_Msk                 /*!< Filter bit 20 */
8493 #define CAN_F8R2_FB21_Pos                    (21U)
8494 #define CAN_F8R2_FB21_Msk                    (0x1UL << CAN_F8R2_FB21_Pos)       /*!< 0x00200000 */
8495 #define CAN_F8R2_FB21                        CAN_F8R2_FB21_Msk                 /*!< Filter bit 21 */
8496 #define CAN_F8R2_FB22_Pos                    (22U)
8497 #define CAN_F8R2_FB22_Msk                    (0x1UL << CAN_F8R2_FB22_Pos)       /*!< 0x00400000 */
8498 #define CAN_F8R2_FB22                        CAN_F8R2_FB22_Msk                 /*!< Filter bit 22 */
8499 #define CAN_F8R2_FB23_Pos                    (23U)
8500 #define CAN_F8R2_FB23_Msk                    (0x1UL << CAN_F8R2_FB23_Pos)       /*!< 0x00800000 */
8501 #define CAN_F8R2_FB23                        CAN_F8R2_FB23_Msk                 /*!< Filter bit 23 */
8502 #define CAN_F8R2_FB24_Pos                    (24U)
8503 #define CAN_F8R2_FB24_Msk                    (0x1UL << CAN_F8R2_FB24_Pos)       /*!< 0x01000000 */
8504 #define CAN_F8R2_FB24                        CAN_F8R2_FB24_Msk                 /*!< Filter bit 24 */
8505 #define CAN_F8R2_FB25_Pos                    (25U)
8506 #define CAN_F8R2_FB25_Msk                    (0x1UL << CAN_F8R2_FB25_Pos)       /*!< 0x02000000 */
8507 #define CAN_F8R2_FB25                        CAN_F8R2_FB25_Msk                 /*!< Filter bit 25 */
8508 #define CAN_F8R2_FB26_Pos                    (26U)
8509 #define CAN_F8R2_FB26_Msk                    (0x1UL << CAN_F8R2_FB26_Pos)       /*!< 0x04000000 */
8510 #define CAN_F8R2_FB26                        CAN_F8R2_FB26_Msk                 /*!< Filter bit 26 */
8511 #define CAN_F8R2_FB27_Pos                    (27U)
8512 #define CAN_F8R2_FB27_Msk                    (0x1UL << CAN_F8R2_FB27_Pos)       /*!< 0x08000000 */
8513 #define CAN_F8R2_FB27                        CAN_F8R2_FB27_Msk                 /*!< Filter bit 27 */
8514 #define CAN_F8R2_FB28_Pos                    (28U)
8515 #define CAN_F8R2_FB28_Msk                    (0x1UL << CAN_F8R2_FB28_Pos)       /*!< 0x10000000 */
8516 #define CAN_F8R2_FB28                        CAN_F8R2_FB28_Msk                 /*!< Filter bit 28 */
8517 #define CAN_F8R2_FB29_Pos                    (29U)
8518 #define CAN_F8R2_FB29_Msk                    (0x1UL << CAN_F8R2_FB29_Pos)       /*!< 0x20000000 */
8519 #define CAN_F8R2_FB29                        CAN_F8R2_FB29_Msk                 /*!< Filter bit 29 */
8520 #define CAN_F8R2_FB30_Pos                    (30U)
8521 #define CAN_F8R2_FB30_Msk                    (0x1UL << CAN_F8R2_FB30_Pos)       /*!< 0x40000000 */
8522 #define CAN_F8R2_FB30                        CAN_F8R2_FB30_Msk                 /*!< Filter bit 30 */
8523 #define CAN_F8R2_FB31_Pos                    (31U)
8524 #define CAN_F8R2_FB31_Msk                    (0x1UL << CAN_F8R2_FB31_Pos)       /*!< 0x80000000 */
8525 #define CAN_F8R2_FB31                        CAN_F8R2_FB31_Msk                 /*!< Filter bit 31 */
8526 
8527 /*******************  Bit definition for CAN_F9R2 register  *******************/
8528 #define CAN_F9R2_FB0_Pos                     (0U)
8529 #define CAN_F9R2_FB0_Msk                     (0x1UL << CAN_F9R2_FB0_Pos)        /*!< 0x00000001 */
8530 #define CAN_F9R2_FB0                         CAN_F9R2_FB0_Msk                  /*!< Filter bit 0 */
8531 #define CAN_F9R2_FB1_Pos                     (1U)
8532 #define CAN_F9R2_FB1_Msk                     (0x1UL << CAN_F9R2_FB1_Pos)        /*!< 0x00000002 */
8533 #define CAN_F9R2_FB1                         CAN_F9R2_FB1_Msk                  /*!< Filter bit 1 */
8534 #define CAN_F9R2_FB2_Pos                     (2U)
8535 #define CAN_F9R2_FB2_Msk                     (0x1UL << CAN_F9R2_FB2_Pos)        /*!< 0x00000004 */
8536 #define CAN_F9R2_FB2                         CAN_F9R2_FB2_Msk                  /*!< Filter bit 2 */
8537 #define CAN_F9R2_FB3_Pos                     (3U)
8538 #define CAN_F9R2_FB3_Msk                     (0x1UL << CAN_F9R2_FB3_Pos)        /*!< 0x00000008 */
8539 #define CAN_F9R2_FB3                         CAN_F9R2_FB3_Msk                  /*!< Filter bit 3 */
8540 #define CAN_F9R2_FB4_Pos                     (4U)
8541 #define CAN_F9R2_FB4_Msk                     (0x1UL << CAN_F9R2_FB4_Pos)        /*!< 0x00000010 */
8542 #define CAN_F9R2_FB4                         CAN_F9R2_FB4_Msk                  /*!< Filter bit 4 */
8543 #define CAN_F9R2_FB5_Pos                     (5U)
8544 #define CAN_F9R2_FB5_Msk                     (0x1UL << CAN_F9R2_FB5_Pos)        /*!< 0x00000020 */
8545 #define CAN_F9R2_FB5                         CAN_F9R2_FB5_Msk                  /*!< Filter bit 5 */
8546 #define CAN_F9R2_FB6_Pos                     (6U)
8547 #define CAN_F9R2_FB6_Msk                     (0x1UL << CAN_F9R2_FB6_Pos)        /*!< 0x00000040 */
8548 #define CAN_F9R2_FB6                         CAN_F9R2_FB6_Msk                  /*!< Filter bit 6 */
8549 #define CAN_F9R2_FB7_Pos                     (7U)
8550 #define CAN_F9R2_FB7_Msk                     (0x1UL << CAN_F9R2_FB7_Pos)        /*!< 0x00000080 */
8551 #define CAN_F9R2_FB7                         CAN_F9R2_FB7_Msk                  /*!< Filter bit 7 */
8552 #define CAN_F9R2_FB8_Pos                     (8U)
8553 #define CAN_F9R2_FB8_Msk                     (0x1UL << CAN_F9R2_FB8_Pos)        /*!< 0x00000100 */
8554 #define CAN_F9R2_FB8                         CAN_F9R2_FB8_Msk                  /*!< Filter bit 8 */
8555 #define CAN_F9R2_FB9_Pos                     (9U)
8556 #define CAN_F9R2_FB9_Msk                     (0x1UL << CAN_F9R2_FB9_Pos)        /*!< 0x00000200 */
8557 #define CAN_F9R2_FB9                         CAN_F9R2_FB9_Msk                  /*!< Filter bit 9 */
8558 #define CAN_F9R2_FB10_Pos                    (10U)
8559 #define CAN_F9R2_FB10_Msk                    (0x1UL << CAN_F9R2_FB10_Pos)       /*!< 0x00000400 */
8560 #define CAN_F9R2_FB10                        CAN_F9R2_FB10_Msk                 /*!< Filter bit 10 */
8561 #define CAN_F9R2_FB11_Pos                    (11U)
8562 #define CAN_F9R2_FB11_Msk                    (0x1UL << CAN_F9R2_FB11_Pos)       /*!< 0x00000800 */
8563 #define CAN_F9R2_FB11                        CAN_F9R2_FB11_Msk                 /*!< Filter bit 11 */
8564 #define CAN_F9R2_FB12_Pos                    (12U)
8565 #define CAN_F9R2_FB12_Msk                    (0x1UL << CAN_F9R2_FB12_Pos)       /*!< 0x00001000 */
8566 #define CAN_F9R2_FB12                        CAN_F9R2_FB12_Msk                 /*!< Filter bit 12 */
8567 #define CAN_F9R2_FB13_Pos                    (13U)
8568 #define CAN_F9R2_FB13_Msk                    (0x1UL << CAN_F9R2_FB13_Pos)       /*!< 0x00002000 */
8569 #define CAN_F9R2_FB13                        CAN_F9R2_FB13_Msk                 /*!< Filter bit 13 */
8570 #define CAN_F9R2_FB14_Pos                    (14U)
8571 #define CAN_F9R2_FB14_Msk                    (0x1UL << CAN_F9R2_FB14_Pos)       /*!< 0x00004000 */
8572 #define CAN_F9R2_FB14                        CAN_F9R2_FB14_Msk                 /*!< Filter bit 14 */
8573 #define CAN_F9R2_FB15_Pos                    (15U)
8574 #define CAN_F9R2_FB15_Msk                    (0x1UL << CAN_F9R2_FB15_Pos)       /*!< 0x00008000 */
8575 #define CAN_F9R2_FB15                        CAN_F9R2_FB15_Msk                 /*!< Filter bit 15 */
8576 #define CAN_F9R2_FB16_Pos                    (16U)
8577 #define CAN_F9R2_FB16_Msk                    (0x1UL << CAN_F9R2_FB16_Pos)       /*!< 0x00010000 */
8578 #define CAN_F9R2_FB16                        CAN_F9R2_FB16_Msk                 /*!< Filter bit 16 */
8579 #define CAN_F9R2_FB17_Pos                    (17U)
8580 #define CAN_F9R2_FB17_Msk                    (0x1UL << CAN_F9R2_FB17_Pos)       /*!< 0x00020000 */
8581 #define CAN_F9R2_FB17                        CAN_F9R2_FB17_Msk                 /*!< Filter bit 17 */
8582 #define CAN_F9R2_FB18_Pos                    (18U)
8583 #define CAN_F9R2_FB18_Msk                    (0x1UL << CAN_F9R2_FB18_Pos)       /*!< 0x00040000 */
8584 #define CAN_F9R2_FB18                        CAN_F9R2_FB18_Msk                 /*!< Filter bit 18 */
8585 #define CAN_F9R2_FB19_Pos                    (19U)
8586 #define CAN_F9R2_FB19_Msk                    (0x1UL << CAN_F9R2_FB19_Pos)       /*!< 0x00080000 */
8587 #define CAN_F9R2_FB19                        CAN_F9R2_FB19_Msk                 /*!< Filter bit 19 */
8588 #define CAN_F9R2_FB20_Pos                    (20U)
8589 #define CAN_F9R2_FB20_Msk                    (0x1UL << CAN_F9R2_FB20_Pos)       /*!< 0x00100000 */
8590 #define CAN_F9R2_FB20                        CAN_F9R2_FB20_Msk                 /*!< Filter bit 20 */
8591 #define CAN_F9R2_FB21_Pos                    (21U)
8592 #define CAN_F9R2_FB21_Msk                    (0x1UL << CAN_F9R2_FB21_Pos)       /*!< 0x00200000 */
8593 #define CAN_F9R2_FB21                        CAN_F9R2_FB21_Msk                 /*!< Filter bit 21 */
8594 #define CAN_F9R2_FB22_Pos                    (22U)
8595 #define CAN_F9R2_FB22_Msk                    (0x1UL << CAN_F9R2_FB22_Pos)       /*!< 0x00400000 */
8596 #define CAN_F9R2_FB22                        CAN_F9R2_FB22_Msk                 /*!< Filter bit 22 */
8597 #define CAN_F9R2_FB23_Pos                    (23U)
8598 #define CAN_F9R2_FB23_Msk                    (0x1UL << CAN_F9R2_FB23_Pos)       /*!< 0x00800000 */
8599 #define CAN_F9R2_FB23                        CAN_F9R2_FB23_Msk                 /*!< Filter bit 23 */
8600 #define CAN_F9R2_FB24_Pos                    (24U)
8601 #define CAN_F9R2_FB24_Msk                    (0x1UL << CAN_F9R2_FB24_Pos)       /*!< 0x01000000 */
8602 #define CAN_F9R2_FB24                        CAN_F9R2_FB24_Msk                 /*!< Filter bit 24 */
8603 #define CAN_F9R2_FB25_Pos                    (25U)
8604 #define CAN_F9R2_FB25_Msk                    (0x1UL << CAN_F9R2_FB25_Pos)       /*!< 0x02000000 */
8605 #define CAN_F9R2_FB25                        CAN_F9R2_FB25_Msk                 /*!< Filter bit 25 */
8606 #define CAN_F9R2_FB26_Pos                    (26U)
8607 #define CAN_F9R2_FB26_Msk                    (0x1UL << CAN_F9R2_FB26_Pos)       /*!< 0x04000000 */
8608 #define CAN_F9R2_FB26                        CAN_F9R2_FB26_Msk                 /*!< Filter bit 26 */
8609 #define CAN_F9R2_FB27_Pos                    (27U)
8610 #define CAN_F9R2_FB27_Msk                    (0x1UL << CAN_F9R2_FB27_Pos)       /*!< 0x08000000 */
8611 #define CAN_F9R2_FB27                        CAN_F9R2_FB27_Msk                 /*!< Filter bit 27 */
8612 #define CAN_F9R2_FB28_Pos                    (28U)
8613 #define CAN_F9R2_FB28_Msk                    (0x1UL << CAN_F9R2_FB28_Pos)       /*!< 0x10000000 */
8614 #define CAN_F9R2_FB28                        CAN_F9R2_FB28_Msk                 /*!< Filter bit 28 */
8615 #define CAN_F9R2_FB29_Pos                    (29U)
8616 #define CAN_F9R2_FB29_Msk                    (0x1UL << CAN_F9R2_FB29_Pos)       /*!< 0x20000000 */
8617 #define CAN_F9R2_FB29                        CAN_F9R2_FB29_Msk                 /*!< Filter bit 29 */
8618 #define CAN_F9R2_FB30_Pos                    (30U)
8619 #define CAN_F9R2_FB30_Msk                    (0x1UL << CAN_F9R2_FB30_Pos)       /*!< 0x40000000 */
8620 #define CAN_F9R2_FB30                        CAN_F9R2_FB30_Msk                 /*!< Filter bit 30 */
8621 #define CAN_F9R2_FB31_Pos                    (31U)
8622 #define CAN_F9R2_FB31_Msk                    (0x1UL << CAN_F9R2_FB31_Pos)       /*!< 0x80000000 */
8623 #define CAN_F9R2_FB31                        CAN_F9R2_FB31_Msk                 /*!< Filter bit 31 */
8624 
8625 /*******************  Bit definition for CAN_F10R2 register  ******************/
8626 #define CAN_F10R2_FB0_Pos                    (0U)
8627 #define CAN_F10R2_FB0_Msk                    (0x1UL << CAN_F10R2_FB0_Pos)       /*!< 0x00000001 */
8628 #define CAN_F10R2_FB0                        CAN_F10R2_FB0_Msk                 /*!< Filter bit 0 */
8629 #define CAN_F10R2_FB1_Pos                    (1U)
8630 #define CAN_F10R2_FB1_Msk                    (0x1UL << CAN_F10R2_FB1_Pos)       /*!< 0x00000002 */
8631 #define CAN_F10R2_FB1                        CAN_F10R2_FB1_Msk                 /*!< Filter bit 1 */
8632 #define CAN_F10R2_FB2_Pos                    (2U)
8633 #define CAN_F10R2_FB2_Msk                    (0x1UL << CAN_F10R2_FB2_Pos)       /*!< 0x00000004 */
8634 #define CAN_F10R2_FB2                        CAN_F10R2_FB2_Msk                 /*!< Filter bit 2 */
8635 #define CAN_F10R2_FB3_Pos                    (3U)
8636 #define CAN_F10R2_FB3_Msk                    (0x1UL << CAN_F10R2_FB3_Pos)       /*!< 0x00000008 */
8637 #define CAN_F10R2_FB3                        CAN_F10R2_FB3_Msk                 /*!< Filter bit 3 */
8638 #define CAN_F10R2_FB4_Pos                    (4U)
8639 #define CAN_F10R2_FB4_Msk                    (0x1UL << CAN_F10R2_FB4_Pos)       /*!< 0x00000010 */
8640 #define CAN_F10R2_FB4                        CAN_F10R2_FB4_Msk                 /*!< Filter bit 4 */
8641 #define CAN_F10R2_FB5_Pos                    (5U)
8642 #define CAN_F10R2_FB5_Msk                    (0x1UL << CAN_F10R2_FB5_Pos)       /*!< 0x00000020 */
8643 #define CAN_F10R2_FB5                        CAN_F10R2_FB5_Msk                 /*!< Filter bit 5 */
8644 #define CAN_F10R2_FB6_Pos                    (6U)
8645 #define CAN_F10R2_FB6_Msk                    (0x1UL << CAN_F10R2_FB6_Pos)       /*!< 0x00000040 */
8646 #define CAN_F10R2_FB6                        CAN_F10R2_FB6_Msk                 /*!< Filter bit 6 */
8647 #define CAN_F10R2_FB7_Pos                    (7U)
8648 #define CAN_F10R2_FB7_Msk                    (0x1UL << CAN_F10R2_FB7_Pos)       /*!< 0x00000080 */
8649 #define CAN_F10R2_FB7                        CAN_F10R2_FB7_Msk                 /*!< Filter bit 7 */
8650 #define CAN_F10R2_FB8_Pos                    (8U)
8651 #define CAN_F10R2_FB8_Msk                    (0x1UL << CAN_F10R2_FB8_Pos)       /*!< 0x00000100 */
8652 #define CAN_F10R2_FB8                        CAN_F10R2_FB8_Msk                 /*!< Filter bit 8 */
8653 #define CAN_F10R2_FB9_Pos                    (9U)
8654 #define CAN_F10R2_FB9_Msk                    (0x1UL << CAN_F10R2_FB9_Pos)       /*!< 0x00000200 */
8655 #define CAN_F10R2_FB9                        CAN_F10R2_FB9_Msk                 /*!< Filter bit 9 */
8656 #define CAN_F10R2_FB10_Pos                   (10U)
8657 #define CAN_F10R2_FB10_Msk                   (0x1UL << CAN_F10R2_FB10_Pos)      /*!< 0x00000400 */
8658 #define CAN_F10R2_FB10                       CAN_F10R2_FB10_Msk                /*!< Filter bit 10 */
8659 #define CAN_F10R2_FB11_Pos                   (11U)
8660 #define CAN_F10R2_FB11_Msk                   (0x1UL << CAN_F10R2_FB11_Pos)      /*!< 0x00000800 */
8661 #define CAN_F10R2_FB11                       CAN_F10R2_FB11_Msk                /*!< Filter bit 11 */
8662 #define CAN_F10R2_FB12_Pos                   (12U)
8663 #define CAN_F10R2_FB12_Msk                   (0x1UL << CAN_F10R2_FB12_Pos)      /*!< 0x00001000 */
8664 #define CAN_F10R2_FB12                       CAN_F10R2_FB12_Msk                /*!< Filter bit 12 */
8665 #define CAN_F10R2_FB13_Pos                   (13U)
8666 #define CAN_F10R2_FB13_Msk                   (0x1UL << CAN_F10R2_FB13_Pos)      /*!< 0x00002000 */
8667 #define CAN_F10R2_FB13                       CAN_F10R2_FB13_Msk                /*!< Filter bit 13 */
8668 #define CAN_F10R2_FB14_Pos                   (14U)
8669 #define CAN_F10R2_FB14_Msk                   (0x1UL << CAN_F10R2_FB14_Pos)      /*!< 0x00004000 */
8670 #define CAN_F10R2_FB14                       CAN_F10R2_FB14_Msk                /*!< Filter bit 14 */
8671 #define CAN_F10R2_FB15_Pos                   (15U)
8672 #define CAN_F10R2_FB15_Msk                   (0x1UL << CAN_F10R2_FB15_Pos)      /*!< 0x00008000 */
8673 #define CAN_F10R2_FB15                       CAN_F10R2_FB15_Msk                /*!< Filter bit 15 */
8674 #define CAN_F10R2_FB16_Pos                   (16U)
8675 #define CAN_F10R2_FB16_Msk                   (0x1UL << CAN_F10R2_FB16_Pos)      /*!< 0x00010000 */
8676 #define CAN_F10R2_FB16                       CAN_F10R2_FB16_Msk                /*!< Filter bit 16 */
8677 #define CAN_F10R2_FB17_Pos                   (17U)
8678 #define CAN_F10R2_FB17_Msk                   (0x1UL << CAN_F10R2_FB17_Pos)      /*!< 0x00020000 */
8679 #define CAN_F10R2_FB17                       CAN_F10R2_FB17_Msk                /*!< Filter bit 17 */
8680 #define CAN_F10R2_FB18_Pos                   (18U)
8681 #define CAN_F10R2_FB18_Msk                   (0x1UL << CAN_F10R2_FB18_Pos)      /*!< 0x00040000 */
8682 #define CAN_F10R2_FB18                       CAN_F10R2_FB18_Msk                /*!< Filter bit 18 */
8683 #define CAN_F10R2_FB19_Pos                   (19U)
8684 #define CAN_F10R2_FB19_Msk                   (0x1UL << CAN_F10R2_FB19_Pos)      /*!< 0x00080000 */
8685 #define CAN_F10R2_FB19                       CAN_F10R2_FB19_Msk                /*!< Filter bit 19 */
8686 #define CAN_F10R2_FB20_Pos                   (20U)
8687 #define CAN_F10R2_FB20_Msk                   (0x1UL << CAN_F10R2_FB20_Pos)      /*!< 0x00100000 */
8688 #define CAN_F10R2_FB20                       CAN_F10R2_FB20_Msk                /*!< Filter bit 20 */
8689 #define CAN_F10R2_FB21_Pos                   (21U)
8690 #define CAN_F10R2_FB21_Msk                   (0x1UL << CAN_F10R2_FB21_Pos)      /*!< 0x00200000 */
8691 #define CAN_F10R2_FB21                       CAN_F10R2_FB21_Msk                /*!< Filter bit 21 */
8692 #define CAN_F10R2_FB22_Pos                   (22U)
8693 #define CAN_F10R2_FB22_Msk                   (0x1UL << CAN_F10R2_FB22_Pos)      /*!< 0x00400000 */
8694 #define CAN_F10R2_FB22                       CAN_F10R2_FB22_Msk                /*!< Filter bit 22 */
8695 #define CAN_F10R2_FB23_Pos                   (23U)
8696 #define CAN_F10R2_FB23_Msk                   (0x1UL << CAN_F10R2_FB23_Pos)      /*!< 0x00800000 */
8697 #define CAN_F10R2_FB23                       CAN_F10R2_FB23_Msk                /*!< Filter bit 23 */
8698 #define CAN_F10R2_FB24_Pos                   (24U)
8699 #define CAN_F10R2_FB24_Msk                   (0x1UL << CAN_F10R2_FB24_Pos)      /*!< 0x01000000 */
8700 #define CAN_F10R2_FB24                       CAN_F10R2_FB24_Msk                /*!< Filter bit 24 */
8701 #define CAN_F10R2_FB25_Pos                   (25U)
8702 #define CAN_F10R2_FB25_Msk                   (0x1UL << CAN_F10R2_FB25_Pos)      /*!< 0x02000000 */
8703 #define CAN_F10R2_FB25                       CAN_F10R2_FB25_Msk                /*!< Filter bit 25 */
8704 #define CAN_F10R2_FB26_Pos                   (26U)
8705 #define CAN_F10R2_FB26_Msk                   (0x1UL << CAN_F10R2_FB26_Pos)      /*!< 0x04000000 */
8706 #define CAN_F10R2_FB26                       CAN_F10R2_FB26_Msk                /*!< Filter bit 26 */
8707 #define CAN_F10R2_FB27_Pos                   (27U)
8708 #define CAN_F10R2_FB27_Msk                   (0x1UL << CAN_F10R2_FB27_Pos)      /*!< 0x08000000 */
8709 #define CAN_F10R2_FB27                       CAN_F10R2_FB27_Msk                /*!< Filter bit 27 */
8710 #define CAN_F10R2_FB28_Pos                   (28U)
8711 #define CAN_F10R2_FB28_Msk                   (0x1UL << CAN_F10R2_FB28_Pos)      /*!< 0x10000000 */
8712 #define CAN_F10R2_FB28                       CAN_F10R2_FB28_Msk                /*!< Filter bit 28 */
8713 #define CAN_F10R2_FB29_Pos                   (29U)
8714 #define CAN_F10R2_FB29_Msk                   (0x1UL << CAN_F10R2_FB29_Pos)      /*!< 0x20000000 */
8715 #define CAN_F10R2_FB29                       CAN_F10R2_FB29_Msk                /*!< Filter bit 29 */
8716 #define CAN_F10R2_FB30_Pos                   (30U)
8717 #define CAN_F10R2_FB30_Msk                   (0x1UL << CAN_F10R2_FB30_Pos)      /*!< 0x40000000 */
8718 #define CAN_F10R2_FB30                       CAN_F10R2_FB30_Msk                /*!< Filter bit 30 */
8719 #define CAN_F10R2_FB31_Pos                   (31U)
8720 #define CAN_F10R2_FB31_Msk                   (0x1UL << CAN_F10R2_FB31_Pos)      /*!< 0x80000000 */
8721 #define CAN_F10R2_FB31                       CAN_F10R2_FB31_Msk                /*!< Filter bit 31 */
8722 
8723 /*******************  Bit definition for CAN_F11R2 register  ******************/
8724 #define CAN_F11R2_FB0_Pos                    (0U)
8725 #define CAN_F11R2_FB0_Msk                    (0x1UL << CAN_F11R2_FB0_Pos)       /*!< 0x00000001 */
8726 #define CAN_F11R2_FB0                        CAN_F11R2_FB0_Msk                 /*!< Filter bit 0 */
8727 #define CAN_F11R2_FB1_Pos                    (1U)
8728 #define CAN_F11R2_FB1_Msk                    (0x1UL << CAN_F11R2_FB1_Pos)       /*!< 0x00000002 */
8729 #define CAN_F11R2_FB1                        CAN_F11R2_FB1_Msk                 /*!< Filter bit 1 */
8730 #define CAN_F11R2_FB2_Pos                    (2U)
8731 #define CAN_F11R2_FB2_Msk                    (0x1UL << CAN_F11R2_FB2_Pos)       /*!< 0x00000004 */
8732 #define CAN_F11R2_FB2                        CAN_F11R2_FB2_Msk                 /*!< Filter bit 2 */
8733 #define CAN_F11R2_FB3_Pos                    (3U)
8734 #define CAN_F11R2_FB3_Msk                    (0x1UL << CAN_F11R2_FB3_Pos)       /*!< 0x00000008 */
8735 #define CAN_F11R2_FB3                        CAN_F11R2_FB3_Msk                 /*!< Filter bit 3 */
8736 #define CAN_F11R2_FB4_Pos                    (4U)
8737 #define CAN_F11R2_FB4_Msk                    (0x1UL << CAN_F11R2_FB4_Pos)       /*!< 0x00000010 */
8738 #define CAN_F11R2_FB4                        CAN_F11R2_FB4_Msk                 /*!< Filter bit 4 */
8739 #define CAN_F11R2_FB5_Pos                    (5U)
8740 #define CAN_F11R2_FB5_Msk                    (0x1UL << CAN_F11R2_FB5_Pos)       /*!< 0x00000020 */
8741 #define CAN_F11R2_FB5                        CAN_F11R2_FB5_Msk                 /*!< Filter bit 5 */
8742 #define CAN_F11R2_FB6_Pos                    (6U)
8743 #define CAN_F11R2_FB6_Msk                    (0x1UL << CAN_F11R2_FB6_Pos)       /*!< 0x00000040 */
8744 #define CAN_F11R2_FB6                        CAN_F11R2_FB6_Msk                 /*!< Filter bit 6 */
8745 #define CAN_F11R2_FB7_Pos                    (7U)
8746 #define CAN_F11R2_FB7_Msk                    (0x1UL << CAN_F11R2_FB7_Pos)       /*!< 0x00000080 */
8747 #define CAN_F11R2_FB7                        CAN_F11R2_FB7_Msk                 /*!< Filter bit 7 */
8748 #define CAN_F11R2_FB8_Pos                    (8U)
8749 #define CAN_F11R2_FB8_Msk                    (0x1UL << CAN_F11R2_FB8_Pos)       /*!< 0x00000100 */
8750 #define CAN_F11R2_FB8                        CAN_F11R2_FB8_Msk                 /*!< Filter bit 8 */
8751 #define CAN_F11R2_FB9_Pos                    (9U)
8752 #define CAN_F11R2_FB9_Msk                    (0x1UL << CAN_F11R2_FB9_Pos)       /*!< 0x00000200 */
8753 #define CAN_F11R2_FB9                        CAN_F11R2_FB9_Msk                 /*!< Filter bit 9 */
8754 #define CAN_F11R2_FB10_Pos                   (10U)
8755 #define CAN_F11R2_FB10_Msk                   (0x1UL << CAN_F11R2_FB10_Pos)      /*!< 0x00000400 */
8756 #define CAN_F11R2_FB10                       CAN_F11R2_FB10_Msk                /*!< Filter bit 10 */
8757 #define CAN_F11R2_FB11_Pos                   (11U)
8758 #define CAN_F11R2_FB11_Msk                   (0x1UL << CAN_F11R2_FB11_Pos)      /*!< 0x00000800 */
8759 #define CAN_F11R2_FB11                       CAN_F11R2_FB11_Msk                /*!< Filter bit 11 */
8760 #define CAN_F11R2_FB12_Pos                   (12U)
8761 #define CAN_F11R2_FB12_Msk                   (0x1UL << CAN_F11R2_FB12_Pos)      /*!< 0x00001000 */
8762 #define CAN_F11R2_FB12                       CAN_F11R2_FB12_Msk                /*!< Filter bit 12 */
8763 #define CAN_F11R2_FB13_Pos                   (13U)
8764 #define CAN_F11R2_FB13_Msk                   (0x1UL << CAN_F11R2_FB13_Pos)      /*!< 0x00002000 */
8765 #define CAN_F11R2_FB13                       CAN_F11R2_FB13_Msk                /*!< Filter bit 13 */
8766 #define CAN_F11R2_FB14_Pos                   (14U)
8767 #define CAN_F11R2_FB14_Msk                   (0x1UL << CAN_F11R2_FB14_Pos)      /*!< 0x00004000 */
8768 #define CAN_F11R2_FB14                       CAN_F11R2_FB14_Msk                /*!< Filter bit 14 */
8769 #define CAN_F11R2_FB15_Pos                   (15U)
8770 #define CAN_F11R2_FB15_Msk                   (0x1UL << CAN_F11R2_FB15_Pos)      /*!< 0x00008000 */
8771 #define CAN_F11R2_FB15                       CAN_F11R2_FB15_Msk                /*!< Filter bit 15 */
8772 #define CAN_F11R2_FB16_Pos                   (16U)
8773 #define CAN_F11R2_FB16_Msk                   (0x1UL << CAN_F11R2_FB16_Pos)      /*!< 0x00010000 */
8774 #define CAN_F11R2_FB16                       CAN_F11R2_FB16_Msk                /*!< Filter bit 16 */
8775 #define CAN_F11R2_FB17_Pos                   (17U)
8776 #define CAN_F11R2_FB17_Msk                   (0x1UL << CAN_F11R2_FB17_Pos)      /*!< 0x00020000 */
8777 #define CAN_F11R2_FB17                       CAN_F11R2_FB17_Msk                /*!< Filter bit 17 */
8778 #define CAN_F11R2_FB18_Pos                   (18U)
8779 #define CAN_F11R2_FB18_Msk                   (0x1UL << CAN_F11R2_FB18_Pos)      /*!< 0x00040000 */
8780 #define CAN_F11R2_FB18                       CAN_F11R2_FB18_Msk                /*!< Filter bit 18 */
8781 #define CAN_F11R2_FB19_Pos                   (19U)
8782 #define CAN_F11R2_FB19_Msk                   (0x1UL << CAN_F11R2_FB19_Pos)      /*!< 0x00080000 */
8783 #define CAN_F11R2_FB19                       CAN_F11R2_FB19_Msk                /*!< Filter bit 19 */
8784 #define CAN_F11R2_FB20_Pos                   (20U)
8785 #define CAN_F11R2_FB20_Msk                   (0x1UL << CAN_F11R2_FB20_Pos)      /*!< 0x00100000 */
8786 #define CAN_F11R2_FB20                       CAN_F11R2_FB20_Msk                /*!< Filter bit 20 */
8787 #define CAN_F11R2_FB21_Pos                   (21U)
8788 #define CAN_F11R2_FB21_Msk                   (0x1UL << CAN_F11R2_FB21_Pos)      /*!< 0x00200000 */
8789 #define CAN_F11R2_FB21                       CAN_F11R2_FB21_Msk                /*!< Filter bit 21 */
8790 #define CAN_F11R2_FB22_Pos                   (22U)
8791 #define CAN_F11R2_FB22_Msk                   (0x1UL << CAN_F11R2_FB22_Pos)      /*!< 0x00400000 */
8792 #define CAN_F11R2_FB22                       CAN_F11R2_FB22_Msk                /*!< Filter bit 22 */
8793 #define CAN_F11R2_FB23_Pos                   (23U)
8794 #define CAN_F11R2_FB23_Msk                   (0x1UL << CAN_F11R2_FB23_Pos)      /*!< 0x00800000 */
8795 #define CAN_F11R2_FB23                       CAN_F11R2_FB23_Msk                /*!< Filter bit 23 */
8796 #define CAN_F11R2_FB24_Pos                   (24U)
8797 #define CAN_F11R2_FB24_Msk                   (0x1UL << CAN_F11R2_FB24_Pos)      /*!< 0x01000000 */
8798 #define CAN_F11R2_FB24                       CAN_F11R2_FB24_Msk                /*!< Filter bit 24 */
8799 #define CAN_F11R2_FB25_Pos                   (25U)
8800 #define CAN_F11R2_FB25_Msk                   (0x1UL << CAN_F11R2_FB25_Pos)      /*!< 0x02000000 */
8801 #define CAN_F11R2_FB25                       CAN_F11R2_FB25_Msk                /*!< Filter bit 25 */
8802 #define CAN_F11R2_FB26_Pos                   (26U)
8803 #define CAN_F11R2_FB26_Msk                   (0x1UL << CAN_F11R2_FB26_Pos)      /*!< 0x04000000 */
8804 #define CAN_F11R2_FB26                       CAN_F11R2_FB26_Msk                /*!< Filter bit 26 */
8805 #define CAN_F11R2_FB27_Pos                   (27U)
8806 #define CAN_F11R2_FB27_Msk                   (0x1UL << CAN_F11R2_FB27_Pos)      /*!< 0x08000000 */
8807 #define CAN_F11R2_FB27                       CAN_F11R2_FB27_Msk                /*!< Filter bit 27 */
8808 #define CAN_F11R2_FB28_Pos                   (28U)
8809 #define CAN_F11R2_FB28_Msk                   (0x1UL << CAN_F11R2_FB28_Pos)      /*!< 0x10000000 */
8810 #define CAN_F11R2_FB28                       CAN_F11R2_FB28_Msk                /*!< Filter bit 28 */
8811 #define CAN_F11R2_FB29_Pos                   (29U)
8812 #define CAN_F11R2_FB29_Msk                   (0x1UL << CAN_F11R2_FB29_Pos)      /*!< 0x20000000 */
8813 #define CAN_F11R2_FB29                       CAN_F11R2_FB29_Msk                /*!< Filter bit 29 */
8814 #define CAN_F11R2_FB30_Pos                   (30U)
8815 #define CAN_F11R2_FB30_Msk                   (0x1UL << CAN_F11R2_FB30_Pos)      /*!< 0x40000000 */
8816 #define CAN_F11R2_FB30                       CAN_F11R2_FB30_Msk                /*!< Filter bit 30 */
8817 #define CAN_F11R2_FB31_Pos                   (31U)
8818 #define CAN_F11R2_FB31_Msk                   (0x1UL << CAN_F11R2_FB31_Pos)      /*!< 0x80000000 */
8819 #define CAN_F11R2_FB31                       CAN_F11R2_FB31_Msk                /*!< Filter bit 31 */
8820 
8821 /*******************  Bit definition for CAN_F12R2 register  ******************/
8822 #define CAN_F12R2_FB0_Pos                    (0U)
8823 #define CAN_F12R2_FB0_Msk                    (0x1UL << CAN_F12R2_FB0_Pos)       /*!< 0x00000001 */
8824 #define CAN_F12R2_FB0                        CAN_F12R2_FB0_Msk                 /*!< Filter bit 0 */
8825 #define CAN_F12R2_FB1_Pos                    (1U)
8826 #define CAN_F12R2_FB1_Msk                    (0x1UL << CAN_F12R2_FB1_Pos)       /*!< 0x00000002 */
8827 #define CAN_F12R2_FB1                        CAN_F12R2_FB1_Msk                 /*!< Filter bit 1 */
8828 #define CAN_F12R2_FB2_Pos                    (2U)
8829 #define CAN_F12R2_FB2_Msk                    (0x1UL << CAN_F12R2_FB2_Pos)       /*!< 0x00000004 */
8830 #define CAN_F12R2_FB2                        CAN_F12R2_FB2_Msk                 /*!< Filter bit 2 */
8831 #define CAN_F12R2_FB3_Pos                    (3U)
8832 #define CAN_F12R2_FB3_Msk                    (0x1UL << CAN_F12R2_FB3_Pos)       /*!< 0x00000008 */
8833 #define CAN_F12R2_FB3                        CAN_F12R2_FB3_Msk                 /*!< Filter bit 3 */
8834 #define CAN_F12R2_FB4_Pos                    (4U)
8835 #define CAN_F12R2_FB4_Msk                    (0x1UL << CAN_F12R2_FB4_Pos)       /*!< 0x00000010 */
8836 #define CAN_F12R2_FB4                        CAN_F12R2_FB4_Msk                 /*!< Filter bit 4 */
8837 #define CAN_F12R2_FB5_Pos                    (5U)
8838 #define CAN_F12R2_FB5_Msk                    (0x1UL << CAN_F12R2_FB5_Pos)       /*!< 0x00000020 */
8839 #define CAN_F12R2_FB5                        CAN_F12R2_FB5_Msk                 /*!< Filter bit 5 */
8840 #define CAN_F12R2_FB6_Pos                    (6U)
8841 #define CAN_F12R2_FB6_Msk                    (0x1UL << CAN_F12R2_FB6_Pos)       /*!< 0x00000040 */
8842 #define CAN_F12R2_FB6                        CAN_F12R2_FB6_Msk                 /*!< Filter bit 6 */
8843 #define CAN_F12R2_FB7_Pos                    (7U)
8844 #define CAN_F12R2_FB7_Msk                    (0x1UL << CAN_F12R2_FB7_Pos)       /*!< 0x00000080 */
8845 #define CAN_F12R2_FB7                        CAN_F12R2_FB7_Msk                 /*!< Filter bit 7 */
8846 #define CAN_F12R2_FB8_Pos                    (8U)
8847 #define CAN_F12R2_FB8_Msk                    (0x1UL << CAN_F12R2_FB8_Pos)       /*!< 0x00000100 */
8848 #define CAN_F12R2_FB8                        CAN_F12R2_FB8_Msk                 /*!< Filter bit 8 */
8849 #define CAN_F12R2_FB9_Pos                    (9U)
8850 #define CAN_F12R2_FB9_Msk                    (0x1UL << CAN_F12R2_FB9_Pos)       /*!< 0x00000200 */
8851 #define CAN_F12R2_FB9                        CAN_F12R2_FB9_Msk                 /*!< Filter bit 9 */
8852 #define CAN_F12R2_FB10_Pos                   (10U)
8853 #define CAN_F12R2_FB10_Msk                   (0x1UL << CAN_F12R2_FB10_Pos)      /*!< 0x00000400 */
8854 #define CAN_F12R2_FB10                       CAN_F12R2_FB10_Msk                /*!< Filter bit 10 */
8855 #define CAN_F12R2_FB11_Pos                   (11U)
8856 #define CAN_F12R2_FB11_Msk                   (0x1UL << CAN_F12R2_FB11_Pos)      /*!< 0x00000800 */
8857 #define CAN_F12R2_FB11                       CAN_F12R2_FB11_Msk                /*!< Filter bit 11 */
8858 #define CAN_F12R2_FB12_Pos                   (12U)
8859 #define CAN_F12R2_FB12_Msk                   (0x1UL << CAN_F12R2_FB12_Pos)      /*!< 0x00001000 */
8860 #define CAN_F12R2_FB12                       CAN_F12R2_FB12_Msk                /*!< Filter bit 12 */
8861 #define CAN_F12R2_FB13_Pos                   (13U)
8862 #define CAN_F12R2_FB13_Msk                   (0x1UL << CAN_F12R2_FB13_Pos)      /*!< 0x00002000 */
8863 #define CAN_F12R2_FB13                       CAN_F12R2_FB13_Msk                /*!< Filter bit 13 */
8864 #define CAN_F12R2_FB14_Pos                   (14U)
8865 #define CAN_F12R2_FB14_Msk                   (0x1UL << CAN_F12R2_FB14_Pos)      /*!< 0x00004000 */
8866 #define CAN_F12R2_FB14                       CAN_F12R2_FB14_Msk                /*!< Filter bit 14 */
8867 #define CAN_F12R2_FB15_Pos                   (15U)
8868 #define CAN_F12R2_FB15_Msk                   (0x1UL << CAN_F12R2_FB15_Pos)      /*!< 0x00008000 */
8869 #define CAN_F12R2_FB15                       CAN_F12R2_FB15_Msk                /*!< Filter bit 15 */
8870 #define CAN_F12R2_FB16_Pos                   (16U)
8871 #define CAN_F12R2_FB16_Msk                   (0x1UL << CAN_F12R2_FB16_Pos)      /*!< 0x00010000 */
8872 #define CAN_F12R2_FB16                       CAN_F12R2_FB16_Msk                /*!< Filter bit 16 */
8873 #define CAN_F12R2_FB17_Pos                   (17U)
8874 #define CAN_F12R2_FB17_Msk                   (0x1UL << CAN_F12R2_FB17_Pos)      /*!< 0x00020000 */
8875 #define CAN_F12R2_FB17                       CAN_F12R2_FB17_Msk                /*!< Filter bit 17 */
8876 #define CAN_F12R2_FB18_Pos                   (18U)
8877 #define CAN_F12R2_FB18_Msk                   (0x1UL << CAN_F12R2_FB18_Pos)      /*!< 0x00040000 */
8878 #define CAN_F12R2_FB18                       CAN_F12R2_FB18_Msk                /*!< Filter bit 18 */
8879 #define CAN_F12R2_FB19_Pos                   (19U)
8880 #define CAN_F12R2_FB19_Msk                   (0x1UL << CAN_F12R2_FB19_Pos)      /*!< 0x00080000 */
8881 #define CAN_F12R2_FB19                       CAN_F12R2_FB19_Msk                /*!< Filter bit 19 */
8882 #define CAN_F12R2_FB20_Pos                   (20U)
8883 #define CAN_F12R2_FB20_Msk                   (0x1UL << CAN_F12R2_FB20_Pos)      /*!< 0x00100000 */
8884 #define CAN_F12R2_FB20                       CAN_F12R2_FB20_Msk                /*!< Filter bit 20 */
8885 #define CAN_F12R2_FB21_Pos                   (21U)
8886 #define CAN_F12R2_FB21_Msk                   (0x1UL << CAN_F12R2_FB21_Pos)      /*!< 0x00200000 */
8887 #define CAN_F12R2_FB21                       CAN_F12R2_FB21_Msk                /*!< Filter bit 21 */
8888 #define CAN_F12R2_FB22_Pos                   (22U)
8889 #define CAN_F12R2_FB22_Msk                   (0x1UL << CAN_F12R2_FB22_Pos)      /*!< 0x00400000 */
8890 #define CAN_F12R2_FB22                       CAN_F12R2_FB22_Msk                /*!< Filter bit 22 */
8891 #define CAN_F12R2_FB23_Pos                   (23U)
8892 #define CAN_F12R2_FB23_Msk                   (0x1UL << CAN_F12R2_FB23_Pos)      /*!< 0x00800000 */
8893 #define CAN_F12R2_FB23                       CAN_F12R2_FB23_Msk                /*!< Filter bit 23 */
8894 #define CAN_F12R2_FB24_Pos                   (24U)
8895 #define CAN_F12R2_FB24_Msk                   (0x1UL << CAN_F12R2_FB24_Pos)      /*!< 0x01000000 */
8896 #define CAN_F12R2_FB24                       CAN_F12R2_FB24_Msk                /*!< Filter bit 24 */
8897 #define CAN_F12R2_FB25_Pos                   (25U)
8898 #define CAN_F12R2_FB25_Msk                   (0x1UL << CAN_F12R2_FB25_Pos)      /*!< 0x02000000 */
8899 #define CAN_F12R2_FB25                       CAN_F12R2_FB25_Msk                /*!< Filter bit 25 */
8900 #define CAN_F12R2_FB26_Pos                   (26U)
8901 #define CAN_F12R2_FB26_Msk                   (0x1UL << CAN_F12R2_FB26_Pos)      /*!< 0x04000000 */
8902 #define CAN_F12R2_FB26                       CAN_F12R2_FB26_Msk                /*!< Filter bit 26 */
8903 #define CAN_F12R2_FB27_Pos                   (27U)
8904 #define CAN_F12R2_FB27_Msk                   (0x1UL << CAN_F12R2_FB27_Pos)      /*!< 0x08000000 */
8905 #define CAN_F12R2_FB27                       CAN_F12R2_FB27_Msk                /*!< Filter bit 27 */
8906 #define CAN_F12R2_FB28_Pos                   (28U)
8907 #define CAN_F12R2_FB28_Msk                   (0x1UL << CAN_F12R2_FB28_Pos)      /*!< 0x10000000 */
8908 #define CAN_F12R2_FB28                       CAN_F12R2_FB28_Msk                /*!< Filter bit 28 */
8909 #define CAN_F12R2_FB29_Pos                   (29U)
8910 #define CAN_F12R2_FB29_Msk                   (0x1UL << CAN_F12R2_FB29_Pos)      /*!< 0x20000000 */
8911 #define CAN_F12R2_FB29                       CAN_F12R2_FB29_Msk                /*!< Filter bit 29 */
8912 #define CAN_F12R2_FB30_Pos                   (30U)
8913 #define CAN_F12R2_FB30_Msk                   (0x1UL << CAN_F12R2_FB30_Pos)      /*!< 0x40000000 */
8914 #define CAN_F12R2_FB30                       CAN_F12R2_FB30_Msk                /*!< Filter bit 30 */
8915 #define CAN_F12R2_FB31_Pos                   (31U)
8916 #define CAN_F12R2_FB31_Msk                   (0x1UL << CAN_F12R2_FB31_Pos)      /*!< 0x80000000 */
8917 #define CAN_F12R2_FB31                       CAN_F12R2_FB31_Msk                /*!< Filter bit 31 */
8918 
8919 /*******************  Bit definition for CAN_F13R2 register  ******************/
8920 #define CAN_F13R2_FB0_Pos                    (0U)
8921 #define CAN_F13R2_FB0_Msk                    (0x1UL << CAN_F13R2_FB0_Pos)       /*!< 0x00000001 */
8922 #define CAN_F13R2_FB0                        CAN_F13R2_FB0_Msk                 /*!< Filter bit 0 */
8923 #define CAN_F13R2_FB1_Pos                    (1U)
8924 #define CAN_F13R2_FB1_Msk                    (0x1UL << CAN_F13R2_FB1_Pos)       /*!< 0x00000002 */
8925 #define CAN_F13R2_FB1                        CAN_F13R2_FB1_Msk                 /*!< Filter bit 1 */
8926 #define CAN_F13R2_FB2_Pos                    (2U)
8927 #define CAN_F13R2_FB2_Msk                    (0x1UL << CAN_F13R2_FB2_Pos)       /*!< 0x00000004 */
8928 #define CAN_F13R2_FB2                        CAN_F13R2_FB2_Msk                 /*!< Filter bit 2 */
8929 #define CAN_F13R2_FB3_Pos                    (3U)
8930 #define CAN_F13R2_FB3_Msk                    (0x1UL << CAN_F13R2_FB3_Pos)       /*!< 0x00000008 */
8931 #define CAN_F13R2_FB3                        CAN_F13R2_FB3_Msk                 /*!< Filter bit 3 */
8932 #define CAN_F13R2_FB4_Pos                    (4U)
8933 #define CAN_F13R2_FB4_Msk                    (0x1UL << CAN_F13R2_FB4_Pos)       /*!< 0x00000010 */
8934 #define CAN_F13R2_FB4                        CAN_F13R2_FB4_Msk                 /*!< Filter bit 4 */
8935 #define CAN_F13R2_FB5_Pos                    (5U)
8936 #define CAN_F13R2_FB5_Msk                    (0x1UL << CAN_F13R2_FB5_Pos)       /*!< 0x00000020 */
8937 #define CAN_F13R2_FB5                        CAN_F13R2_FB5_Msk                 /*!< Filter bit 5 */
8938 #define CAN_F13R2_FB6_Pos                    (6U)
8939 #define CAN_F13R2_FB6_Msk                    (0x1UL << CAN_F13R2_FB6_Pos)       /*!< 0x00000040 */
8940 #define CAN_F13R2_FB6                        CAN_F13R2_FB6_Msk                 /*!< Filter bit 6 */
8941 #define CAN_F13R2_FB7_Pos                    (7U)
8942 #define CAN_F13R2_FB7_Msk                    (0x1UL << CAN_F13R2_FB7_Pos)       /*!< 0x00000080 */
8943 #define CAN_F13R2_FB7                        CAN_F13R2_FB7_Msk                 /*!< Filter bit 7 */
8944 #define CAN_F13R2_FB8_Pos                    (8U)
8945 #define CAN_F13R2_FB8_Msk                    (0x1UL << CAN_F13R2_FB8_Pos)       /*!< 0x00000100 */
8946 #define CAN_F13R2_FB8                        CAN_F13R2_FB8_Msk                 /*!< Filter bit 8 */
8947 #define CAN_F13R2_FB9_Pos                    (9U)
8948 #define CAN_F13R2_FB9_Msk                    (0x1UL << CAN_F13R2_FB9_Pos)       /*!< 0x00000200 */
8949 #define CAN_F13R2_FB9                        CAN_F13R2_FB9_Msk                 /*!< Filter bit 9 */
8950 #define CAN_F13R2_FB10_Pos                   (10U)
8951 #define CAN_F13R2_FB10_Msk                   (0x1UL << CAN_F13R2_FB10_Pos)      /*!< 0x00000400 */
8952 #define CAN_F13R2_FB10                       CAN_F13R2_FB10_Msk                /*!< Filter bit 10 */
8953 #define CAN_F13R2_FB11_Pos                   (11U)
8954 #define CAN_F13R2_FB11_Msk                   (0x1UL << CAN_F13R2_FB11_Pos)      /*!< 0x00000800 */
8955 #define CAN_F13R2_FB11                       CAN_F13R2_FB11_Msk                /*!< Filter bit 11 */
8956 #define CAN_F13R2_FB12_Pos                   (12U)
8957 #define CAN_F13R2_FB12_Msk                   (0x1UL << CAN_F13R2_FB12_Pos)      /*!< 0x00001000 */
8958 #define CAN_F13R2_FB12                       CAN_F13R2_FB12_Msk                /*!< Filter bit 12 */
8959 #define CAN_F13R2_FB13_Pos                   (13U)
8960 #define CAN_F13R2_FB13_Msk                   (0x1UL << CAN_F13R2_FB13_Pos)      /*!< 0x00002000 */
8961 #define CAN_F13R2_FB13                       CAN_F13R2_FB13_Msk                /*!< Filter bit 13 */
8962 #define CAN_F13R2_FB14_Pos                   (14U)
8963 #define CAN_F13R2_FB14_Msk                   (0x1UL << CAN_F13R2_FB14_Pos)      /*!< 0x00004000 */
8964 #define CAN_F13R2_FB14                       CAN_F13R2_FB14_Msk                /*!< Filter bit 14 */
8965 #define CAN_F13R2_FB15_Pos                   (15U)
8966 #define CAN_F13R2_FB15_Msk                   (0x1UL << CAN_F13R2_FB15_Pos)      /*!< 0x00008000 */
8967 #define CAN_F13R2_FB15                       CAN_F13R2_FB15_Msk                /*!< Filter bit 15 */
8968 #define CAN_F13R2_FB16_Pos                   (16U)
8969 #define CAN_F13R2_FB16_Msk                   (0x1UL << CAN_F13R2_FB16_Pos)      /*!< 0x00010000 */
8970 #define CAN_F13R2_FB16                       CAN_F13R2_FB16_Msk                /*!< Filter bit 16 */
8971 #define CAN_F13R2_FB17_Pos                   (17U)
8972 #define CAN_F13R2_FB17_Msk                   (0x1UL << CAN_F13R2_FB17_Pos)      /*!< 0x00020000 */
8973 #define CAN_F13R2_FB17                       CAN_F13R2_FB17_Msk                /*!< Filter bit 17 */
8974 #define CAN_F13R2_FB18_Pos                   (18U)
8975 #define CAN_F13R2_FB18_Msk                   (0x1UL << CAN_F13R2_FB18_Pos)      /*!< 0x00040000 */
8976 #define CAN_F13R2_FB18                       CAN_F13R2_FB18_Msk                /*!< Filter bit 18 */
8977 #define CAN_F13R2_FB19_Pos                   (19U)
8978 #define CAN_F13R2_FB19_Msk                   (0x1UL << CAN_F13R2_FB19_Pos)      /*!< 0x00080000 */
8979 #define CAN_F13R2_FB19                       CAN_F13R2_FB19_Msk                /*!< Filter bit 19 */
8980 #define CAN_F13R2_FB20_Pos                   (20U)
8981 #define CAN_F13R2_FB20_Msk                   (0x1UL << CAN_F13R2_FB20_Pos)      /*!< 0x00100000 */
8982 #define CAN_F13R2_FB20                       CAN_F13R2_FB20_Msk                /*!< Filter bit 20 */
8983 #define CAN_F13R2_FB21_Pos                   (21U)
8984 #define CAN_F13R2_FB21_Msk                   (0x1UL << CAN_F13R2_FB21_Pos)      /*!< 0x00200000 */
8985 #define CAN_F13R2_FB21                       CAN_F13R2_FB21_Msk                /*!< Filter bit 21 */
8986 #define CAN_F13R2_FB22_Pos                   (22U)
8987 #define CAN_F13R2_FB22_Msk                   (0x1UL << CAN_F13R2_FB22_Pos)      /*!< 0x00400000 */
8988 #define CAN_F13R2_FB22                       CAN_F13R2_FB22_Msk                /*!< Filter bit 22 */
8989 #define CAN_F13R2_FB23_Pos                   (23U)
8990 #define CAN_F13R2_FB23_Msk                   (0x1UL << CAN_F13R2_FB23_Pos)      /*!< 0x00800000 */
8991 #define CAN_F13R2_FB23                       CAN_F13R2_FB23_Msk                /*!< Filter bit 23 */
8992 #define CAN_F13R2_FB24_Pos                   (24U)
8993 #define CAN_F13R2_FB24_Msk                   (0x1UL << CAN_F13R2_FB24_Pos)      /*!< 0x01000000 */
8994 #define CAN_F13R2_FB24                       CAN_F13R2_FB24_Msk                /*!< Filter bit 24 */
8995 #define CAN_F13R2_FB25_Pos                   (25U)
8996 #define CAN_F13R2_FB25_Msk                   (0x1UL << CAN_F13R2_FB25_Pos)      /*!< 0x02000000 */
8997 #define CAN_F13R2_FB25                       CAN_F13R2_FB25_Msk                /*!< Filter bit 25 */
8998 #define CAN_F13R2_FB26_Pos                   (26U)
8999 #define CAN_F13R2_FB26_Msk                   (0x1UL << CAN_F13R2_FB26_Pos)      /*!< 0x04000000 */
9000 #define CAN_F13R2_FB26                       CAN_F13R2_FB26_Msk                /*!< Filter bit 26 */
9001 #define CAN_F13R2_FB27_Pos                   (27U)
9002 #define CAN_F13R2_FB27_Msk                   (0x1UL << CAN_F13R2_FB27_Pos)      /*!< 0x08000000 */
9003 #define CAN_F13R2_FB27                       CAN_F13R2_FB27_Msk                /*!< Filter bit 27 */
9004 #define CAN_F13R2_FB28_Pos                   (28U)
9005 #define CAN_F13R2_FB28_Msk                   (0x1UL << CAN_F13R2_FB28_Pos)      /*!< 0x10000000 */
9006 #define CAN_F13R2_FB28                       CAN_F13R2_FB28_Msk                /*!< Filter bit 28 */
9007 #define CAN_F13R2_FB29_Pos                   (29U)
9008 #define CAN_F13R2_FB29_Msk                   (0x1UL << CAN_F13R2_FB29_Pos)      /*!< 0x20000000 */
9009 #define CAN_F13R2_FB29                       CAN_F13R2_FB29_Msk                /*!< Filter bit 29 */
9010 #define CAN_F13R2_FB30_Pos                   (30U)
9011 #define CAN_F13R2_FB30_Msk                   (0x1UL << CAN_F13R2_FB30_Pos)      /*!< 0x40000000 */
9012 #define CAN_F13R2_FB30                       CAN_F13R2_FB30_Msk                /*!< Filter bit 30 */
9013 #define CAN_F13R2_FB31_Pos                   (31U)
9014 #define CAN_F13R2_FB31_Msk                   (0x1UL << CAN_F13R2_FB31_Pos)      /*!< 0x80000000 */
9015 #define CAN_F13R2_FB31                       CAN_F13R2_FB31_Msk                /*!< Filter bit 31 */
9016 
9017 /******************************************************************************/
9018 /*                                                                            */
9019 /*                        Serial Peripheral Interface                         */
9020 /*                                                                            */
9021 /******************************************************************************/
9022 
9023 /*******************  Bit definition for SPI_CR1 register  ********************/
9024 #define SPI_CR1_CPHA_Pos                    (0U)
9025 #define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
9026 #define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
9027 #define SPI_CR1_CPOL_Pos                    (1U)
9028 #define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
9029 #define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
9030 #define SPI_CR1_MSTR_Pos                    (2U)
9031 #define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
9032 #define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
9033 
9034 #define SPI_CR1_BR_Pos                      (3U)
9035 #define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
9036 #define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
9037 #define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
9038 #define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
9039 #define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
9040 
9041 #define SPI_CR1_SPE_Pos                     (6U)
9042 #define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
9043 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
9044 #define SPI_CR1_LSBFIRST_Pos                (7U)
9045 #define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
9046 #define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
9047 #define SPI_CR1_SSI_Pos                     (8U)
9048 #define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
9049 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
9050 #define SPI_CR1_SSM_Pos                     (9U)
9051 #define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
9052 #define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
9053 #define SPI_CR1_RXONLY_Pos                  (10U)
9054 #define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
9055 #define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
9056 #define SPI_CR1_DFF_Pos                     (11U)
9057 #define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
9058 #define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
9059 #define SPI_CR1_CRCNEXT_Pos                 (12U)
9060 #define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
9061 #define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
9062 #define SPI_CR1_CRCEN_Pos                   (13U)
9063 #define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
9064 #define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
9065 #define SPI_CR1_BIDIOE_Pos                  (14U)
9066 #define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
9067 #define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
9068 #define SPI_CR1_BIDIMODE_Pos                (15U)
9069 #define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
9070 #define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
9071 
9072 /*******************  Bit definition for SPI_CR2 register  ********************/
9073 #define SPI_CR2_RXDMAEN_Pos                 (0U)
9074 #define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
9075 #define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
9076 #define SPI_CR2_TXDMAEN_Pos                 (1U)
9077 #define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
9078 #define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
9079 #define SPI_CR2_SSOE_Pos                    (2U)
9080 #define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
9081 #define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
9082 #define SPI_CR2_ERRIE_Pos                   (5U)
9083 #define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
9084 #define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
9085 #define SPI_CR2_RXNEIE_Pos                  (6U)
9086 #define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
9087 #define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
9088 #define SPI_CR2_TXEIE_Pos                   (7U)
9089 #define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
9090 #define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
9091 
9092 /********************  Bit definition for SPI_SR register  ********************/
9093 #define SPI_SR_RXNE_Pos                     (0U)
9094 #define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
9095 #define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
9096 #define SPI_SR_TXE_Pos                      (1U)
9097 #define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
9098 #define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
9099 #define SPI_SR_CHSIDE_Pos                   (2U)
9100 #define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
9101 #define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
9102 #define SPI_SR_UDR_Pos                      (3U)
9103 #define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
9104 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
9105 #define SPI_SR_CRCERR_Pos                   (4U)
9106 #define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
9107 #define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
9108 #define SPI_SR_MODF_Pos                     (5U)
9109 #define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
9110 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
9111 #define SPI_SR_OVR_Pos                      (6U)
9112 #define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
9113 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
9114 #define SPI_SR_BSY_Pos                      (7U)
9115 #define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
9116 #define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
9117 
9118 /********************  Bit definition for SPI_DR register  ********************/
9119 #define SPI_DR_DR_Pos                       (0U)
9120 #define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
9121 #define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
9122 
9123 /*******************  Bit definition for SPI_CRCPR register  ******************/
9124 #define SPI_CRCPR_CRCPOLY_Pos               (0U)
9125 #define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
9126 #define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
9127 
9128 /******************  Bit definition for SPI_RXCRCR register  ******************/
9129 #define SPI_RXCRCR_RXCRC_Pos                (0U)
9130 #define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
9131 #define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
9132 
9133 /******************  Bit definition for SPI_TXCRCR register  ******************/
9134 #define SPI_TXCRCR_TXCRC_Pos                (0U)
9135 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
9136 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
9137 
9138 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)
9139 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
9140 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */
9141 
9142 /******************************************************************************/
9143 /*                                                                            */
9144 /*                      Inter-integrated Circuit Interface                    */
9145 /*                                                                            */
9146 /******************************************************************************/
9147 
9148 /*******************  Bit definition for I2C_CR1 register  ********************/
9149 #define I2C_CR1_PE_Pos                      (0U)
9150 #define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
9151 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
9152 #define I2C_CR1_SMBUS_Pos                   (1U)
9153 #define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
9154 #define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
9155 #define I2C_CR1_SMBTYPE_Pos                 (3U)
9156 #define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
9157 #define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
9158 #define I2C_CR1_ENARP_Pos                   (4U)
9159 #define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
9160 #define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
9161 #define I2C_CR1_ENPEC_Pos                   (5U)
9162 #define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
9163 #define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
9164 #define I2C_CR1_ENGC_Pos                    (6U)
9165 #define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
9166 #define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
9167 #define I2C_CR1_NOSTRETCH_Pos               (7U)
9168 #define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
9169 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
9170 #define I2C_CR1_START_Pos                   (8U)
9171 #define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */
9172 #define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
9173 #define I2C_CR1_STOP_Pos                    (9U)
9174 #define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
9175 #define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
9176 #define I2C_CR1_ACK_Pos                     (10U)
9177 #define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
9178 #define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
9179 #define I2C_CR1_POS_Pos                     (11U)
9180 #define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
9181 #define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
9182 #define I2C_CR1_PEC_Pos                     (12U)
9183 #define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
9184 #define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
9185 #define I2C_CR1_ALERT_Pos                   (13U)
9186 #define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
9187 #define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
9188 #define I2C_CR1_SWRST_Pos                   (15U)
9189 #define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
9190 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
9191 
9192 /*******************  Bit definition for I2C_CR2 register  ********************/
9193 #define I2C_CR2_FREQ_Pos                    (0U)
9194 #define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
9195 #define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
9196 #define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
9197 #define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
9198 #define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
9199 #define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
9200 #define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
9201 #define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
9202 
9203 #define I2C_CR2_ITERREN_Pos                 (8U)
9204 #define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
9205 #define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
9206 #define I2C_CR2_ITEVTEN_Pos                 (9U)
9207 #define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
9208 #define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
9209 #define I2C_CR2_ITBUFEN_Pos                 (10U)
9210 #define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
9211 #define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
9212 #define I2C_CR2_DMAEN_Pos                   (11U)
9213 #define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
9214 #define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
9215 #define I2C_CR2_LAST_Pos                    (12U)
9216 #define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
9217 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
9218 
9219 /*******************  Bit definition for I2C_OAR1 register  *******************/
9220 #define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */
9221 #define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */
9222 
9223 #define I2C_OAR1_ADD0_Pos                   (0U)
9224 #define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
9225 #define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
9226 #define I2C_OAR1_ADD1_Pos                   (1U)
9227 #define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
9228 #define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
9229 #define I2C_OAR1_ADD2_Pos                   (2U)
9230 #define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
9231 #define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
9232 #define I2C_OAR1_ADD3_Pos                   (3U)
9233 #define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
9234 #define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
9235 #define I2C_OAR1_ADD4_Pos                   (4U)
9236 #define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
9237 #define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
9238 #define I2C_OAR1_ADD5_Pos                   (5U)
9239 #define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
9240 #define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
9241 #define I2C_OAR1_ADD6_Pos                   (6U)
9242 #define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
9243 #define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
9244 #define I2C_OAR1_ADD7_Pos                   (7U)
9245 #define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
9246 #define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
9247 #define I2C_OAR1_ADD8_Pos                   (8U)
9248 #define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
9249 #define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
9250 #define I2C_OAR1_ADD9_Pos                   (9U)
9251 #define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
9252 #define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
9253 
9254 #define I2C_OAR1_ADDMODE_Pos                (15U)
9255 #define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
9256 #define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
9257 
9258 /*******************  Bit definition for I2C_OAR2 register  *******************/
9259 #define I2C_OAR2_ENDUAL_Pos                 (0U)
9260 #define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
9261 #define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
9262 #define I2C_OAR2_ADD2_Pos                   (1U)
9263 #define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
9264 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
9265 
9266 /********************  Bit definition for I2C_DR register  ********************/
9267 #define I2C_DR_DR_Pos             (0U)
9268 #define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
9269 #define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */
9270 
9271 /*******************  Bit definition for I2C_SR1 register  ********************/
9272 #define I2C_SR1_SB_Pos                      (0U)
9273 #define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
9274 #define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
9275 #define I2C_SR1_ADDR_Pos                    (1U)
9276 #define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
9277 #define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
9278 #define I2C_SR1_BTF_Pos                     (2U)
9279 #define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
9280 #define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
9281 #define I2C_SR1_ADD10_Pos                   (3U)
9282 #define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
9283 #define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
9284 #define I2C_SR1_STOPF_Pos                   (4U)
9285 #define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
9286 #define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
9287 #define I2C_SR1_RXNE_Pos                    (6U)
9288 #define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
9289 #define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
9290 #define I2C_SR1_TXE_Pos                     (7U)
9291 #define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
9292 #define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
9293 #define I2C_SR1_BERR_Pos                    (8U)
9294 #define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
9295 #define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
9296 #define I2C_SR1_ARLO_Pos                    (9U)
9297 #define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
9298 #define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
9299 #define I2C_SR1_AF_Pos                      (10U)
9300 #define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
9301 #define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
9302 #define I2C_SR1_OVR_Pos                     (11U)
9303 #define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
9304 #define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
9305 #define I2C_SR1_PECERR_Pos                  (12U)
9306 #define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
9307 #define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
9308 #define I2C_SR1_TIMEOUT_Pos                 (14U)
9309 #define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
9310 #define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
9311 #define I2C_SR1_SMBALERT_Pos                (15U)
9312 #define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
9313 #define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
9314 
9315 /*******************  Bit definition for I2C_SR2 register  ********************/
9316 #define I2C_SR2_MSL_Pos                     (0U)
9317 #define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
9318 #define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
9319 #define I2C_SR2_BUSY_Pos                    (1U)
9320 #define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
9321 #define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
9322 #define I2C_SR2_TRA_Pos                     (2U)
9323 #define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
9324 #define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
9325 #define I2C_SR2_GENCALL_Pos                 (4U)
9326 #define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
9327 #define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
9328 #define I2C_SR2_SMBDEFAULT_Pos              (5U)
9329 #define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
9330 #define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
9331 #define I2C_SR2_SMBHOST_Pos                 (6U)
9332 #define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
9333 #define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
9334 #define I2C_SR2_DUALF_Pos                   (7U)
9335 #define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
9336 #define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
9337 #define I2C_SR2_PEC_Pos                     (8U)
9338 #define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
9339 #define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
9340 
9341 /*******************  Bit definition for I2C_CCR register  ********************/
9342 #define I2C_CCR_CCR_Pos                     (0U)
9343 #define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
9344 #define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
9345 #define I2C_CCR_DUTY_Pos                    (14U)
9346 #define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
9347 #define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
9348 #define I2C_CCR_FS_Pos                      (15U)
9349 #define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
9350 #define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
9351 
9352 /******************  Bit definition for I2C_TRISE register  *******************/
9353 #define I2C_TRISE_TRISE_Pos                 (0U)
9354 #define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
9355 #define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
9356 
9357 /******************************************************************************/
9358 /*                                                                            */
9359 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
9360 /*                                                                            */
9361 /******************************************************************************/
9362 
9363 /*******************  Bit definition for USART_SR register  *******************/
9364 #define USART_SR_PE_Pos                     (0U)
9365 #define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */
9366 #define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
9367 #define USART_SR_FE_Pos                     (1U)
9368 #define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */
9369 #define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
9370 #define USART_SR_NE_Pos                     (2U)
9371 #define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */
9372 #define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
9373 #define USART_SR_ORE_Pos                    (3U)
9374 #define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */
9375 #define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
9376 #define USART_SR_IDLE_Pos                   (4U)
9377 #define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
9378 #define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
9379 #define USART_SR_RXNE_Pos                   (5U)
9380 #define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
9381 #define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
9382 #define USART_SR_TC_Pos                     (6U)
9383 #define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */
9384 #define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
9385 #define USART_SR_TXE_Pos                    (7U)
9386 #define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */
9387 #define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
9388 #define USART_SR_LBD_Pos                    (8U)
9389 #define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */
9390 #define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
9391 #define USART_SR_CTS_Pos                    (9U)
9392 #define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */
9393 #define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
9394 
9395 /*******************  Bit definition for USART_DR register  *******************/
9396 #define USART_DR_DR_Pos                     (0U)
9397 #define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */
9398 #define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
9399 
9400 /******************  Bit definition for USART_BRR register  *******************/
9401 #define USART_BRR_DIV_Fraction_Pos          (0U)
9402 #define USART_BRR_DIV_Fraction_Msk          (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
9403 #define USART_BRR_DIV_Fraction              USART_BRR_DIV_Fraction_Msk         /*!< Fraction of USARTDIV */
9404 #define USART_BRR_DIV_Mantissa_Pos          (4U)
9405 #define USART_BRR_DIV_Mantissa_Msk          (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
9406 #define USART_BRR_DIV_Mantissa              USART_BRR_DIV_Mantissa_Msk         /*!< Mantissa of USARTDIV */
9407 
9408 /******************  Bit definition for USART_CR1 register  *******************/
9409 #define USART_CR1_SBK_Pos                   (0U)
9410 #define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
9411 #define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
9412 #define USART_CR1_RWU_Pos                   (1U)
9413 #define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
9414 #define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
9415 #define USART_CR1_RE_Pos                    (2U)
9416 #define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */
9417 #define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
9418 #define USART_CR1_TE_Pos                    (3U)
9419 #define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */
9420 #define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
9421 #define USART_CR1_IDLEIE_Pos                (4U)
9422 #define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
9423 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
9424 #define USART_CR1_RXNEIE_Pos                (5U)
9425 #define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
9426 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
9427 #define USART_CR1_TCIE_Pos                  (6U)
9428 #define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
9429 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
9430 #define USART_CR1_TXEIE_Pos                 (7U)
9431 #define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
9432 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
9433 #define USART_CR1_PEIE_Pos                  (8U)
9434 #define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
9435 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
9436 #define USART_CR1_PS_Pos                    (9U)
9437 #define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */
9438 #define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
9439 #define USART_CR1_PCE_Pos                   (10U)
9440 #define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
9441 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
9442 #define USART_CR1_WAKE_Pos                  (11U)
9443 #define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
9444 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
9445 #define USART_CR1_M_Pos                     (12U)
9446 #define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */
9447 #define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
9448 #define USART_CR1_UE_Pos                    (13U)
9449 #define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */
9450 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
9451 
9452 /******************  Bit definition for USART_CR2 register  *******************/
9453 #define USART_CR2_ADD_Pos                   (0U)
9454 #define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
9455 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
9456 #define USART_CR2_LBDL_Pos                  (5U)
9457 #define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
9458 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
9459 #define USART_CR2_LBDIE_Pos                 (6U)
9460 #define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
9461 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
9462 #define USART_CR2_LBCL_Pos                  (8U)
9463 #define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
9464 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
9465 #define USART_CR2_CPHA_Pos                  (9U)
9466 #define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
9467 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
9468 #define USART_CR2_CPOL_Pos                  (10U)
9469 #define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
9470 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
9471 #define USART_CR2_CLKEN_Pos                 (11U)
9472 #define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
9473 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
9474 
9475 #define USART_CR2_STOP_Pos                  (12U)
9476 #define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
9477 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
9478 #define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
9479 #define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
9480 
9481 #define USART_CR2_LINEN_Pos                 (14U)
9482 #define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
9483 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
9484 
9485 /******************  Bit definition for USART_CR3 register  *******************/
9486 #define USART_CR3_EIE_Pos                   (0U)
9487 #define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
9488 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
9489 #define USART_CR3_IREN_Pos                  (1U)
9490 #define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
9491 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
9492 #define USART_CR3_IRLP_Pos                  (2U)
9493 #define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
9494 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
9495 #define USART_CR3_HDSEL_Pos                 (3U)
9496 #define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
9497 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
9498 #define USART_CR3_NACK_Pos                  (4U)
9499 #define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
9500 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
9501 #define USART_CR3_SCEN_Pos                  (5U)
9502 #define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
9503 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
9504 #define USART_CR3_DMAR_Pos                  (6U)
9505 #define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
9506 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
9507 #define USART_CR3_DMAT_Pos                  (7U)
9508 #define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
9509 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
9510 #define USART_CR3_RTSE_Pos                  (8U)
9511 #define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
9512 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
9513 #define USART_CR3_CTSE_Pos                  (9U)
9514 #define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
9515 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
9516 #define USART_CR3_CTSIE_Pos                 (10U)
9517 #define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
9518 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
9519 
9520 /******************  Bit definition for USART_GTPR register  ******************/
9521 #define USART_GTPR_PSC_Pos                  (0U)
9522 #define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
9523 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
9524 #define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
9525 #define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
9526 #define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
9527 #define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
9528 #define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
9529 #define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
9530 #define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
9531 #define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
9532 
9533 #define USART_GTPR_GT_Pos                   (8U)
9534 #define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
9535 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
9536 
9537 /******************************************************************************/
9538 /*                                                                            */
9539 /*                                 Debug MCU                                  */
9540 /*                                                                            */
9541 /******************************************************************************/
9542 
9543 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
9544 #define DBGMCU_IDCODE_DEV_ID_Pos            (0U)
9545 #define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
9546 #define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           /*!< Device Identifier */
9547 
9548 #define DBGMCU_IDCODE_REV_ID_Pos            (16U)
9549 #define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
9550 #define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           /*!< REV_ID[15:0] bits (Revision Identifier) */
9551 #define DBGMCU_IDCODE_REV_ID_0              (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
9552 #define DBGMCU_IDCODE_REV_ID_1              (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
9553 #define DBGMCU_IDCODE_REV_ID_2              (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
9554 #define DBGMCU_IDCODE_REV_ID_3              (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
9555 #define DBGMCU_IDCODE_REV_ID_4              (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
9556 #define DBGMCU_IDCODE_REV_ID_5              (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
9557 #define DBGMCU_IDCODE_REV_ID_6              (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
9558 #define DBGMCU_IDCODE_REV_ID_7              (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
9559 #define DBGMCU_IDCODE_REV_ID_8              (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
9560 #define DBGMCU_IDCODE_REV_ID_9              (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
9561 #define DBGMCU_IDCODE_REV_ID_10             (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
9562 #define DBGMCU_IDCODE_REV_ID_11             (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
9563 #define DBGMCU_IDCODE_REV_ID_12             (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
9564 #define DBGMCU_IDCODE_REV_ID_13             (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
9565 #define DBGMCU_IDCODE_REV_ID_14             (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
9566 #define DBGMCU_IDCODE_REV_ID_15             (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
9567 
9568 /******************  Bit definition for DBGMCU_CR register  *******************/
9569 #define DBGMCU_CR_DBG_SLEEP_Pos             (0U)
9570 #define DBGMCU_CR_DBG_SLEEP_Msk             (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
9571 #define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            /*!< Debug Sleep Mode */
9572 #define DBGMCU_CR_DBG_STOP_Pos              (1U)
9573 #define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
9574 #define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             /*!< Debug Stop Mode */
9575 #define DBGMCU_CR_DBG_STANDBY_Pos           (2U)
9576 #define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
9577 #define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          /*!< Debug Standby mode */
9578 #define DBGMCU_CR_TRACE_IOEN_Pos            (5U)
9579 #define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
9580 #define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           /*!< Trace Pin Assignment Control */
9581 
9582 #define DBGMCU_CR_TRACE_MODE_Pos            (6U)
9583 #define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
9584 #define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
9585 #define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
9586 #define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
9587 
9588 #define DBGMCU_CR_DBG_IWDG_STOP_Pos         (8U)
9589 #define DBGMCU_CR_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
9590 #define DBGMCU_CR_DBG_IWDG_STOP             DBGMCU_CR_DBG_IWDG_STOP_Msk        /*!< Debug Independent Watchdog stopped when Core is halted */
9591 #define DBGMCU_CR_DBG_WWDG_STOP_Pos         (9U)
9592 #define DBGMCU_CR_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
9593 #define DBGMCU_CR_DBG_WWDG_STOP             DBGMCU_CR_DBG_WWDG_STOP_Msk        /*!< Debug Window Watchdog stopped when Core is halted */
9594 #define DBGMCU_CR_DBG_TIM1_STOP_Pos         (10U)
9595 #define DBGMCU_CR_DBG_TIM1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
9596 #define DBGMCU_CR_DBG_TIM1_STOP             DBGMCU_CR_DBG_TIM1_STOP_Msk        /*!< TIM1 counter stopped when core is halted */
9597 #define DBGMCU_CR_DBG_TIM2_STOP_Pos         (11U)
9598 #define DBGMCU_CR_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
9599 #define DBGMCU_CR_DBG_TIM2_STOP             DBGMCU_CR_DBG_TIM2_STOP_Msk        /*!< TIM2 counter stopped when core is halted */
9600 #define DBGMCU_CR_DBG_TIM3_STOP_Pos         (12U)
9601 #define DBGMCU_CR_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
9602 #define DBGMCU_CR_DBG_TIM3_STOP             DBGMCU_CR_DBG_TIM3_STOP_Msk        /*!< TIM3 counter stopped when core is halted */
9603 #define DBGMCU_CR_DBG_CAN1_STOP_Pos         (14U)
9604 #define DBGMCU_CR_DBG_CAN1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
9605 #define DBGMCU_CR_DBG_CAN1_STOP             DBGMCU_CR_DBG_CAN1_STOP_Msk        /*!< Debug CAN1 stopped when Core is halted */
9606 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
9607 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
9608 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
9609 
9610 /******************************************************************************/
9611 /*                                                                            */
9612 /*                      FLASH and Option Bytes Registers                      */
9613 /*                                                                            */
9614 /******************************************************************************/
9615 /*******************  Bit definition for FLASH_ACR register  ******************/
9616 #define FLASH_ACR_LATENCY_Pos               (0U)
9617 #define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */
9618 #define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< LATENCY[2:0] bits (Latency) */
9619 #define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */
9620 #define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */
9621 #define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */
9622 
9623 #define FLASH_ACR_HLFCYA_Pos                (3U)
9624 #define FLASH_ACR_HLFCYA_Msk                (0x1UL << FLASH_ACR_HLFCYA_Pos)     /*!< 0x00000008 */
9625 #define FLASH_ACR_HLFCYA                    FLASH_ACR_HLFCYA_Msk               /*!< Flash Half Cycle Access Enable */
9626 #define FLASH_ACR_PRFTBE_Pos                (4U)
9627 #define FLASH_ACR_PRFTBE_Msk                (0x1UL << FLASH_ACR_PRFTBE_Pos)     /*!< 0x00000010 */
9628 #define FLASH_ACR_PRFTBE                    FLASH_ACR_PRFTBE_Msk               /*!< Prefetch Buffer Enable */
9629 #define FLASH_ACR_PRFTBS_Pos                (5U)
9630 #define FLASH_ACR_PRFTBS_Msk                (0x1UL << FLASH_ACR_PRFTBS_Pos)     /*!< 0x00000020 */
9631 #define FLASH_ACR_PRFTBS                    FLASH_ACR_PRFTBS_Msk               /*!< Prefetch Buffer Status */
9632 
9633 /******************  Bit definition for FLASH_KEYR register  ******************/
9634 #define FLASH_KEYR_FKEYR_Pos                (0U)
9635 #define FLASH_KEYR_FKEYR_Msk                (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
9636 #define FLASH_KEYR_FKEYR                    FLASH_KEYR_FKEYR_Msk               /*!< FPEC Key */
9637 
9638 #define RDP_KEY_Pos                         (0U)
9639 #define RDP_KEY_Msk                         (0xA5UL << RDP_KEY_Pos)             /*!< 0x000000A5 */
9640 #define RDP_KEY                             RDP_KEY_Msk                        /*!< RDP Key */
9641 #define FLASH_KEY1_Pos                      (0U)
9642 #define FLASH_KEY1_Msk                      (0x45670123UL << FLASH_KEY1_Pos)    /*!< 0x45670123 */
9643 #define FLASH_KEY1                          FLASH_KEY1_Msk                     /*!< FPEC Key1 */
9644 #define FLASH_KEY2_Pos                      (0U)
9645 #define FLASH_KEY2_Msk                      (0xCDEF89ABUL << FLASH_KEY2_Pos)    /*!< 0xCDEF89AB */
9646 #define FLASH_KEY2                          FLASH_KEY2_Msk                     /*!< FPEC Key2 */
9647 
9648 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
9649 #define FLASH_OPTKEYR_OPTKEYR_Pos           (0U)
9650 #define FLASH_OPTKEYR_OPTKEYR_Msk           (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
9651 #define FLASH_OPTKEYR_OPTKEYR               FLASH_OPTKEYR_OPTKEYR_Msk          /*!< Option Byte Key */
9652 
9653 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
9654 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
9655 
9656 /******************  Bit definition for FLASH_SR register  ********************/
9657 #define FLASH_SR_BSY_Pos                    (0U)
9658 #define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)         /*!< 0x00000001 */
9659 #define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Busy */
9660 #define FLASH_SR_PGERR_Pos                  (2U)
9661 #define FLASH_SR_PGERR_Msk                  (0x1UL << FLASH_SR_PGERR_Pos)       /*!< 0x00000004 */
9662 #define FLASH_SR_PGERR                      FLASH_SR_PGERR_Msk                 /*!< Programming Error */
9663 #define FLASH_SR_WRPRTERR_Pos               (4U)
9664 #define FLASH_SR_WRPRTERR_Msk               (0x1UL << FLASH_SR_WRPRTERR_Pos)    /*!< 0x00000010 */
9665 #define FLASH_SR_WRPRTERR                   FLASH_SR_WRPRTERR_Msk              /*!< Write Protection Error */
9666 #define FLASH_SR_EOP_Pos                    (5U)
9667 #define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)         /*!< 0x00000020 */
9668 #define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of operation */
9669 
9670 /*******************  Bit definition for FLASH_CR register  *******************/
9671 #define FLASH_CR_PG_Pos                     (0U)
9672 #define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)          /*!< 0x00000001 */
9673 #define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Programming */
9674 #define FLASH_CR_PER_Pos                    (1U)
9675 #define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)         /*!< 0x00000002 */
9676 #define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page Erase */
9677 #define FLASH_CR_MER_Pos                    (2U)
9678 #define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)         /*!< 0x00000004 */
9679 #define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass Erase */
9680 #define FLASH_CR_OPTPG_Pos                  (4U)
9681 #define FLASH_CR_OPTPG_Msk                  (0x1UL << FLASH_CR_OPTPG_Pos)       /*!< 0x00000010 */
9682 #define FLASH_CR_OPTPG                      FLASH_CR_OPTPG_Msk                 /*!< Option Byte Programming */
9683 #define FLASH_CR_OPTER_Pos                  (5U)
9684 #define FLASH_CR_OPTER_Msk                  (0x1UL << FLASH_CR_OPTER_Pos)       /*!< 0x00000020 */
9685 #define FLASH_CR_OPTER                      FLASH_CR_OPTER_Msk                 /*!< Option Byte Erase */
9686 #define FLASH_CR_STRT_Pos                   (6U)
9687 #define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)        /*!< 0x00000040 */
9688 #define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start */
9689 #define FLASH_CR_LOCK_Pos                   (7U)
9690 #define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)        /*!< 0x00000080 */
9691 #define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Lock */
9692 #define FLASH_CR_OPTWRE_Pos                 (9U)
9693 #define FLASH_CR_OPTWRE_Msk                 (0x1UL << FLASH_CR_OPTWRE_Pos)      /*!< 0x00000200 */
9694 #define FLASH_CR_OPTWRE                     FLASH_CR_OPTWRE_Msk                /*!< Option Bytes Write Enable */
9695 #define FLASH_CR_ERRIE_Pos                  (10U)
9696 #define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)       /*!< 0x00000400 */
9697 #define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error Interrupt Enable */
9698 #define FLASH_CR_EOPIE_Pos                  (12U)
9699 #define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)       /*!< 0x00001000 */
9700 #define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable */
9701 
9702 /*******************  Bit definition for FLASH_AR register  *******************/
9703 #define FLASH_AR_FAR_Pos                    (0U)
9704 #define FLASH_AR_FAR_Msk                    (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)  /*!< 0xFFFFFFFF */
9705 #define FLASH_AR_FAR                        FLASH_AR_FAR_Msk                   /*!< Flash Address */
9706 
9707 /******************  Bit definition for FLASH_OBR register  *******************/
9708 #define FLASH_OBR_OPTERR_Pos                (0U)
9709 #define FLASH_OBR_OPTERR_Msk                (0x1UL << FLASH_OBR_OPTERR_Pos)     /*!< 0x00000001 */
9710 #define FLASH_OBR_OPTERR                    FLASH_OBR_OPTERR_Msk               /*!< Option Byte Error */
9711 #define FLASH_OBR_RDPRT_Pos                 (1U)
9712 #define FLASH_OBR_RDPRT_Msk                 (0x1UL << FLASH_OBR_RDPRT_Pos)      /*!< 0x00000002 */
9713 #define FLASH_OBR_RDPRT                     FLASH_OBR_RDPRT_Msk                /*!< Read protection */
9714 
9715 #define FLASH_OBR_IWDG_SW_Pos               (2U)
9716 #define FLASH_OBR_IWDG_SW_Msk               (0x1UL << FLASH_OBR_IWDG_SW_Pos)    /*!< 0x00000004 */
9717 #define FLASH_OBR_IWDG_SW                   FLASH_OBR_IWDG_SW_Msk              /*!< IWDG SW */
9718 #define FLASH_OBR_nRST_STOP_Pos             (3U)
9719 #define FLASH_OBR_nRST_STOP_Msk             (0x1UL << FLASH_OBR_nRST_STOP_Pos)  /*!< 0x00000008 */
9720 #define FLASH_OBR_nRST_STOP                 FLASH_OBR_nRST_STOP_Msk            /*!< nRST_STOP */
9721 #define FLASH_OBR_nRST_STDBY_Pos            (4U)
9722 #define FLASH_OBR_nRST_STDBY_Msk            (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
9723 #define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */
9724 #define FLASH_OBR_USER_Pos                  (2U)
9725 #define FLASH_OBR_USER_Msk                  (0x7UL << FLASH_OBR_USER_Pos)       /*!< 0x0000001C */
9726 #define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */
9727 #define FLASH_OBR_DATA0_Pos                 (10U)
9728 #define FLASH_OBR_DATA0_Msk                 (0xFFUL << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */
9729 #define FLASH_OBR_DATA0                     FLASH_OBR_DATA0_Msk                /*!< Data0 */
9730 #define FLASH_OBR_DATA1_Pos                 (18U)
9731 #define FLASH_OBR_DATA1_Msk                 (0xFFUL << FLASH_OBR_DATA1_Pos)     /*!< 0x03FC0000 */
9732 #define FLASH_OBR_DATA1                     FLASH_OBR_DATA1_Msk                /*!< Data1 */
9733 
9734 /******************  Bit definition for FLASH_WRPR register  ******************/
9735 #define FLASH_WRPR_WRP_Pos                  (0U)
9736 #define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
9737 #define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */
9738 
9739 /*----------------------------------------------------------------------------*/
9740 
9741 /******************  Bit definition for FLASH_RDP register  *******************/
9742 #define FLASH_RDP_RDP_Pos                   (0U)
9743 #define FLASH_RDP_RDP_Msk                   (0xFFUL << FLASH_RDP_RDP_Pos)       /*!< 0x000000FF */
9744 #define FLASH_RDP_RDP                       FLASH_RDP_RDP_Msk                  /*!< Read protection option byte */
9745 #define FLASH_RDP_nRDP_Pos                  (8U)
9746 #define FLASH_RDP_nRDP_Msk                  (0xFFUL << FLASH_RDP_nRDP_Pos)      /*!< 0x0000FF00 */
9747 #define FLASH_RDP_nRDP                      FLASH_RDP_nRDP_Msk                 /*!< Read protection complemented option byte */
9748 
9749 /******************  Bit definition for FLASH_USER register  ******************/
9750 #define FLASH_USER_USER_Pos                 (16U)
9751 #define FLASH_USER_USER_Msk                 (0xFFUL << FLASH_USER_USER_Pos)     /*!< 0x00FF0000 */
9752 #define FLASH_USER_USER                     FLASH_USER_USER_Msk                /*!< User option byte */
9753 #define FLASH_USER_nUSER_Pos                (24U)
9754 #define FLASH_USER_nUSER_Msk                (0xFFUL << FLASH_USER_nUSER_Pos)    /*!< 0xFF000000 */
9755 #define FLASH_USER_nUSER                    FLASH_USER_nUSER_Msk               /*!< User complemented option byte */
9756 
9757 /******************  Bit definition for FLASH_Data0 register  *****************/
9758 #define FLASH_DATA0_DATA0_Pos               (0U)
9759 #define FLASH_DATA0_DATA0_Msk               (0xFFUL << FLASH_DATA0_DATA0_Pos)   /*!< 0x000000FF */
9760 #define FLASH_DATA0_DATA0                   FLASH_DATA0_DATA0_Msk              /*!< User data storage option byte */
9761 #define FLASH_DATA0_nDATA0_Pos              (8U)
9762 #define FLASH_DATA0_nDATA0_Msk              (0xFFUL << FLASH_DATA0_nDATA0_Pos)  /*!< 0x0000FF00 */
9763 #define FLASH_DATA0_nDATA0                  FLASH_DATA0_nDATA0_Msk             /*!< User data storage complemented option byte */
9764 
9765 /******************  Bit definition for FLASH_Data1 register  *****************/
9766 #define FLASH_DATA1_DATA1_Pos               (16U)
9767 #define FLASH_DATA1_DATA1_Msk               (0xFFUL << FLASH_DATA1_DATA1_Pos)   /*!< 0x00FF0000 */
9768 #define FLASH_DATA1_DATA1                   FLASH_DATA1_DATA1_Msk              /*!< User data storage option byte */
9769 #define FLASH_DATA1_nDATA1_Pos              (24U)
9770 #define FLASH_DATA1_nDATA1_Msk              (0xFFUL << FLASH_DATA1_nDATA1_Pos)  /*!< 0xFF000000 */
9771 #define FLASH_DATA1_nDATA1                  FLASH_DATA1_nDATA1_Msk             /*!< User data storage complemented option byte */
9772 
9773 /******************  Bit definition for FLASH_WRP0 register  ******************/
9774 #define FLASH_WRP0_WRP0_Pos                 (0U)
9775 #define FLASH_WRP0_WRP0_Msk                 (0xFFUL << FLASH_WRP0_WRP0_Pos)     /*!< 0x000000FF */
9776 #define FLASH_WRP0_WRP0                     FLASH_WRP0_WRP0_Msk                /*!< Flash memory write protection option bytes */
9777 #define FLASH_WRP0_nWRP0_Pos                (8U)
9778 #define FLASH_WRP0_nWRP0_Msk                (0xFFUL << FLASH_WRP0_nWRP0_Pos)    /*!< 0x0000FF00 */
9779 #define FLASH_WRP0_nWRP0                    FLASH_WRP0_nWRP0_Msk               /*!< Flash memory write protection complemented option bytes */
9780 
9781 
9782 
9783 /**
9784   * @}
9785 */
9786 
9787 /**
9788   * @}
9789 */
9790 
9791 /** @addtogroup Exported_macro
9792   * @{
9793   */
9794 
9795 /****************************** ADC Instances *********************************/
9796 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
9797                                        ((INSTANCE) == ADC2))
9798 
9799 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
9800 
9801 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9802 
9803 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9804 
9805 /****************************** CAN Instances *********************************/
9806 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
9807 
9808 /****************************** CRC Instances *********************************/
9809 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9810 
9811 /****************************** DAC Instances *********************************/
9812 
9813 /****************************** DMA Instances *********************************/
9814 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9815                                        ((INSTANCE) == DMA1_Channel2) || \
9816                                        ((INSTANCE) == DMA1_Channel3) || \
9817                                        ((INSTANCE) == DMA1_Channel4) || \
9818                                        ((INSTANCE) == DMA1_Channel5) || \
9819                                        ((INSTANCE) == DMA1_Channel6) || \
9820                                        ((INSTANCE) == DMA1_Channel7))
9821 
9822 /******************************* GPIO Instances *******************************/
9823 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9824                                         ((INSTANCE) == GPIOB) || \
9825                                         ((INSTANCE) == GPIOC) || \
9826                                         ((INSTANCE) == GPIOD))
9827 
9828 /**************************** GPIO Alternate Function Instances ***************/
9829 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9830 
9831 /**************************** GPIO Lock Instances *****************************/
9832 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9833 
9834 /******************************** I2C Instances *******************************/
9835 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
9836 
9837 /******************************* SMBUS Instances ******************************/
9838 #define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
9839 
9840 /****************************** IWDG Instances ********************************/
9841 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
9842 
9843 /******************************** SPI Instances *******************************/
9844 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
9845 
9846 /****************************** START TIM Instances ***************************/
9847 /****************************** TIM Instances *********************************/
9848 #define IS_TIM_INSTANCE(INSTANCE)\
9849   (((INSTANCE) == TIM1)    || \
9850    ((INSTANCE) == TIM2)    || \
9851    ((INSTANCE) == TIM3))
9852 
9853 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9854 
9855 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
9856   (((INSTANCE) == TIM1)    || \
9857    ((INSTANCE) == TIM2)    || \
9858    ((INSTANCE) == TIM3))
9859 
9860 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
9861   (((INSTANCE) == TIM1)    || \
9862    ((INSTANCE) == TIM2)    || \
9863    ((INSTANCE) == TIM3))
9864 
9865 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
9866   (((INSTANCE) == TIM1)    || \
9867    ((INSTANCE) == TIM2)    || \
9868    ((INSTANCE) == TIM3))
9869 
9870 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
9871   (((INSTANCE) == TIM1)    || \
9872    ((INSTANCE) == TIM2)    || \
9873    ((INSTANCE) == TIM3))
9874 
9875 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
9876   (((INSTANCE) == TIM1)    || \
9877    ((INSTANCE) == TIM2)    || \
9878    ((INSTANCE) == TIM3))
9879 
9880 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
9881   (((INSTANCE) == TIM1)    || \
9882    ((INSTANCE) == TIM2)    || \
9883    ((INSTANCE) == TIM3))
9884 
9885 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
9886   (((INSTANCE) == TIM1)    || \
9887    ((INSTANCE) == TIM2)    || \
9888    ((INSTANCE) == TIM3))
9889 
9890 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
9891   (((INSTANCE) == TIM1)    || \
9892    ((INSTANCE) == TIM2)    || \
9893    ((INSTANCE) == TIM3))
9894 
9895 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
9896   (((INSTANCE) == TIM1)    || \
9897    ((INSTANCE) == TIM2)    || \
9898    ((INSTANCE) == TIM3))
9899 
9900 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
9901   (((INSTANCE) == TIM1)    || \
9902    ((INSTANCE) == TIM2)    || \
9903    ((INSTANCE) == TIM3))
9904 
9905 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
9906   (((INSTANCE) == TIM1)    || \
9907    ((INSTANCE) == TIM2)    || \
9908    ((INSTANCE) == TIM3))
9909 
9910 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
9911   (((INSTANCE) == TIM1)    || \
9912    ((INSTANCE) == TIM2)    || \
9913    ((INSTANCE) == TIM3))
9914 
9915 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
9916   (((INSTANCE) == TIM1)    || \
9917    ((INSTANCE) == TIM2)    || \
9918    ((INSTANCE) == TIM3))
9919 
9920 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
9921   (((INSTANCE) == TIM1)    || \
9922    ((INSTANCE) == TIM2)    || \
9923    ((INSTANCE) == TIM3))
9924 
9925 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
9926   ((INSTANCE) == TIM1)
9927 
9928 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9929    ((((INSTANCE) == TIM1) &&                  \
9930      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9931       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9932       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9933       ((CHANNEL) == TIM_CHANNEL_4)))           \
9934     ||                                         \
9935     (((INSTANCE) == TIM2) &&                   \
9936      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9937       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9938       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9939       ((CHANNEL) == TIM_CHANNEL_4)))           \
9940     ||                                         \
9941     (((INSTANCE) == TIM3) &&                   \
9942      (((CHANNEL) == TIM_CHANNEL_1) ||          \
9943       ((CHANNEL) == TIM_CHANNEL_2) ||          \
9944       ((CHANNEL) == TIM_CHANNEL_3) ||          \
9945       ((CHANNEL) == TIM_CHANNEL_4))))
9946 
9947 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9948     (((INSTANCE) == TIM1) &&                    \
9949      (((CHANNEL) == TIM_CHANNEL_1) ||           \
9950       ((CHANNEL) == TIM_CHANNEL_2) ||           \
9951       ((CHANNEL) == TIM_CHANNEL_3)))
9952 
9953 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
9954   (((INSTANCE) == TIM1)    || \
9955    ((INSTANCE) == TIM2)    || \
9956    ((INSTANCE) == TIM3))
9957 
9958 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
9959   ((INSTANCE) == TIM1)
9960 
9961 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
9962   (((INSTANCE) == TIM1)    || \
9963    ((INSTANCE) == TIM2)    || \
9964    ((INSTANCE) == TIM3))
9965 
9966 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
9967   (((INSTANCE) == TIM1)    || \
9968    ((INSTANCE) == TIM2)    || \
9969    ((INSTANCE) == TIM3))
9970 
9971 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
9972   (((INSTANCE) == TIM1)    || \
9973    ((INSTANCE) == TIM2)    || \
9974    ((INSTANCE) == TIM3))
9975 
9976 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
9977   ((INSTANCE) == TIM1)
9978 
9979 #define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \
9980                                         ((INSTANCE) == TIM2)    || \
9981                                         ((INSTANCE) == TIM3))
9982 
9983 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
9984                                                          ((INSTANCE) == TIM2)    || \
9985                                                          ((INSTANCE) == TIM3))
9986 
9987 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U
9988 
9989 /****************************** END TIM Instances *****************************/
9990 
9991 
9992 /******************** USART Instances : Synchronous mode **********************/
9993 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9994                                      ((INSTANCE) == USART2))
9995 
9996 /******************** UART Instances : Asynchronous mode **********************/
9997 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9998                                     ((INSTANCE) == USART2) )
9999 
10000 /******************** UART Instances : Half-Duplex mode **********************/
10001 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10002                                                ((INSTANCE) == USART2) )
10003 
10004 /******************** UART Instances : LIN mode **********************/
10005 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10006                                         ((INSTANCE) == USART2) )
10007 
10008 /****************** UART Instances : Hardware Flow control ********************/
10009 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10010                                            ((INSTANCE) == USART2) )
10011 
10012 /********************* UART Instances : Smard card mode ***********************/
10013 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10014                                          ((INSTANCE) == USART2) )
10015 
10016 /*********************** UART Instances : IRDA mode ***************************/
10017 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10018                                     ((INSTANCE) == USART2) )
10019 
10020 /***************** UART Instances : Multi-Processor mode **********************/
10021 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10022                                                    ((INSTANCE) == USART2) )
10023 
10024 /***************** UART Instances : DMA mode available **********************/
10025 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10026                                         ((INSTANCE) == USART2))
10027 
10028 /****************************** RTC Instances *********************************/
10029 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
10030 
10031 /**************************** WWDG Instances *****************************/
10032 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
10033 
10034 /****************************** USB Instances ********************************/
10035 #define IS_PCD_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == USB)
10036 
10037 
10038 
10039 #define RCC_HSE_MIN         4000000U
10040 #define RCC_HSE_MAX        16000000U
10041 
10042 #define RCC_MAX_FREQUENCY  72000000U
10043 
10044 /**
10045   * @}
10046   */
10047 /******************************************************************************/
10048 /*  For a painless codes migration between the STM32F1xx device product       */
10049 /*  lines, the aliases defined below are put in place to overcome the         */
10050 /*  differences in the interrupt handlers and IRQn definitions.               */
10051 /*  No need to update developed interrupt code when moving across             */
10052 /*  product lines within the same STM32F1 Family                              */
10053 /******************************************************************************/
10054 
10055 /* Aliases for __IRQn */
10056 #define ADC1_IRQn               ADC1_2_IRQn
10057 #define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn
10058 #define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn
10059 #define TIM9_IRQn               TIM1_BRK_IRQn
10060 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
10061 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
10062 #define TIM11_IRQn              TIM1_TRG_COM_IRQn
10063 #define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn
10064 #define TIM10_IRQn              TIM1_UP_IRQn
10065 #define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn
10066 #define CEC_IRQn                USBWakeUp_IRQn
10067 #define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn
10068 #define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn
10069 #define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn
10070 #define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn
10071 #define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn
10072 
10073 
10074 /* Aliases for __IRQHandler */
10075 #define ADC1_IRQHandler               ADC1_2_IRQHandler
10076 #define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler
10077 #define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler
10078 #define TIM9_IRQHandler               TIM1_BRK_IRQHandler
10079 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
10080 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
10081 #define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler
10082 #define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler
10083 #define TIM10_IRQHandler              TIM1_UP_IRQHandler
10084 #define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler
10085 #define CEC_IRQHandler                USBWakeUp_IRQHandler
10086 #define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler
10087 #define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler
10088 #define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler
10089 #define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler
10090 #define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler
10091 
10092 
10093 /**
10094   * @}
10095   */
10096 
10097 /**
10098   * @}
10099   */
10100 
10101 
10102 #ifdef __cplusplus
10103   }
10104 #endif /* __cplusplus */
10105 
10106 #endif /* __STM32F103x6_H */
10107 
10108 
10109 
10110