1 /** 2 ****************************************************************************** 3 * @file stm32f100xb.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for STM32F1xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * Copyright (c) 2017-2021 STMicroelectronics. 18 * All rights reserved. 19 * 20 * This software is licensed under terms that can be found in the LICENSE file 21 * in the root directory of this software component. 22 * If no LICENSE file comes with this software, it is provided AS-IS. 23 * 24 ****************************************************************************** 25 */ 26 27 28 /** @addtogroup CMSIS 29 * @{ 30 */ 31 32 /** @addtogroup stm32f100xb 33 * @{ 34 */ 35 36 #ifndef __STM32F100xB_H 37 #define __STM32F100xB_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /** @addtogroup Configuration_section_for_CMSIS 44 * @{ 45 */ 46 /** 47 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 48 */ 49 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ 50 #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ 51 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ 52 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 53 54 /** 55 * @} 56 */ 57 58 /** @addtogroup Peripheral_interrupt_number_definition 59 * @{ 60 */ 61 62 /** 63 * @brief STM32F10x Interrupt Number Definition, according to the selected device 64 * in @ref Library_configuration_section 65 */ 66 67 /*!< Interrupt Number Definition */ 68 typedef enum 69 { 70 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 71 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 72 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 73 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 74 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 75 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 76 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 77 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 78 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 79 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 80 81 /****** STM32 specific Interrupt Numbers *********************************************************/ 82 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 83 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 84 TAMPER_IRQn = 2, /*!< Tamper Interrupt */ 85 RTC_IRQn = 3, /*!< RTC global Interrupt */ 86 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 87 RCC_IRQn = 5, /*!< RCC global Interrupt */ 88 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 89 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 90 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 91 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 92 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 93 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 94 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 95 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 96 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 97 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 98 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 99 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 100 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ 101 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 102 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ 103 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ 104 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ 105 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 106 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 107 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 108 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 109 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 110 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 111 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 112 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 113 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 114 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 115 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 116 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 117 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 118 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 119 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 120 CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ 121 TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ 122 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ 123 } IRQn_Type; 124 125 /** 126 * @} 127 */ 128 129 #include "core_cm3.h" 130 #include "system_stm32f1xx.h" 131 #include <stdint.h> 132 133 /** @addtogroup Peripheral_registers_structures 134 * @{ 135 */ 136 137 /** 138 * @brief Analog to Digital Converter 139 */ 140 141 typedef struct 142 { 143 __IO uint32_t SR; 144 __IO uint32_t CR1; 145 __IO uint32_t CR2; 146 __IO uint32_t SMPR1; 147 __IO uint32_t SMPR2; 148 __IO uint32_t JOFR1; 149 __IO uint32_t JOFR2; 150 __IO uint32_t JOFR3; 151 __IO uint32_t JOFR4; 152 __IO uint32_t HTR; 153 __IO uint32_t LTR; 154 __IO uint32_t SQR1; 155 __IO uint32_t SQR2; 156 __IO uint32_t SQR3; 157 __IO uint32_t JSQR; 158 __IO uint32_t JDR1; 159 __IO uint32_t JDR2; 160 __IO uint32_t JDR3; 161 __IO uint32_t JDR4; 162 __IO uint32_t DR; 163 } ADC_TypeDef; 164 165 typedef struct 166 { 167 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ 168 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ 169 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ 170 uint32_t RESERVED[16]; 171 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ 172 } ADC_Common_TypeDef; 173 174 /** 175 * @brief Backup Registers 176 */ 177 178 typedef struct 179 { 180 uint32_t RESERVED0; 181 __IO uint32_t DR1; 182 __IO uint32_t DR2; 183 __IO uint32_t DR3; 184 __IO uint32_t DR4; 185 __IO uint32_t DR5; 186 __IO uint32_t DR6; 187 __IO uint32_t DR7; 188 __IO uint32_t DR8; 189 __IO uint32_t DR9; 190 __IO uint32_t DR10; 191 __IO uint32_t RTCCR; 192 __IO uint32_t CR; 193 __IO uint32_t CSR; 194 } BKP_TypeDef; 195 196 197 /** 198 * @brief Consumer Electronics Control (CEC) 199 */ 200 typedef struct 201 { 202 __IO uint32_t CFGR; 203 __IO uint32_t OAR; 204 __IO uint32_t PRES; 205 __IO uint32_t ESR; 206 __IO uint32_t CSR; 207 __IO uint32_t TXD; 208 __IO uint32_t RXD; 209 } CEC_TypeDef; 210 211 /** 212 * @brief CRC calculation unit 213 */ 214 215 typedef struct 216 { 217 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 218 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 219 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ 220 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ 221 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 222 } CRC_TypeDef; 223 224 /** 225 * @brief Digital to Analog Converter 226 */ 227 228 typedef struct 229 { 230 __IO uint32_t CR; 231 __IO uint32_t SWTRIGR; 232 __IO uint32_t DHR12R1; 233 __IO uint32_t DHR12L1; 234 __IO uint32_t DHR8R1; 235 __IO uint32_t DHR12R2; 236 __IO uint32_t DHR12L2; 237 __IO uint32_t DHR8R2; 238 __IO uint32_t DHR12RD; 239 __IO uint32_t DHR12LD; 240 __IO uint32_t DHR8RD; 241 __IO uint32_t DOR1; 242 __IO uint32_t DOR2; 243 __IO uint32_t SR; 244 } DAC_TypeDef; 245 246 /** 247 * @brief Debug MCU 248 */ 249 250 typedef struct 251 { 252 __IO uint32_t IDCODE; 253 __IO uint32_t CR; 254 }DBGMCU_TypeDef; 255 256 /** 257 * @brief DMA Controller 258 */ 259 260 typedef struct 261 { 262 __IO uint32_t CCR; 263 __IO uint32_t CNDTR; 264 __IO uint32_t CPAR; 265 __IO uint32_t CMAR; 266 } DMA_Channel_TypeDef; 267 268 typedef struct 269 { 270 __IO uint32_t ISR; 271 __IO uint32_t IFCR; 272 } DMA_TypeDef; 273 274 275 276 /** 277 * @brief External Interrupt/Event Controller 278 */ 279 280 typedef struct 281 { 282 __IO uint32_t IMR; 283 __IO uint32_t EMR; 284 __IO uint32_t RTSR; 285 __IO uint32_t FTSR; 286 __IO uint32_t SWIER; 287 __IO uint32_t PR; 288 } EXTI_TypeDef; 289 290 /** 291 * @brief FLASH Registers 292 */ 293 294 typedef struct 295 { 296 __IO uint32_t ACR; 297 __IO uint32_t KEYR; 298 __IO uint32_t OPTKEYR; 299 __IO uint32_t SR; 300 __IO uint32_t CR; 301 __IO uint32_t AR; 302 __IO uint32_t RESERVED; 303 __IO uint32_t OBR; 304 __IO uint32_t WRPR; 305 } FLASH_TypeDef; 306 307 /** 308 * @brief Option Bytes Registers 309 */ 310 311 typedef struct 312 { 313 __IO uint16_t RDP; 314 __IO uint16_t USER; 315 __IO uint16_t Data0; 316 __IO uint16_t Data1; 317 __IO uint16_t WRP0; 318 __IO uint16_t WRP1; 319 __IO uint16_t WRP2; 320 __IO uint16_t WRP3; 321 } OB_TypeDef; 322 323 /** 324 * @brief General Purpose I/O 325 */ 326 327 typedef struct 328 { 329 __IO uint32_t CRL; 330 __IO uint32_t CRH; 331 __IO uint32_t IDR; 332 __IO uint32_t ODR; 333 __IO uint32_t BSRR; 334 __IO uint32_t BRR; 335 __IO uint32_t LCKR; 336 } GPIO_TypeDef; 337 338 /** 339 * @brief Alternate Function I/O 340 */ 341 342 typedef struct 343 { 344 __IO uint32_t EVCR; 345 __IO uint32_t MAPR; 346 __IO uint32_t EXTICR[4]; 347 uint32_t RESERVED0; 348 __IO uint32_t MAPR2; 349 } AFIO_TypeDef; 350 /** 351 * @brief Inter Integrated Circuit Interface 352 */ 353 354 typedef struct 355 { 356 __IO uint32_t CR1; 357 __IO uint32_t CR2; 358 __IO uint32_t OAR1; 359 __IO uint32_t OAR2; 360 __IO uint32_t DR; 361 __IO uint32_t SR1; 362 __IO uint32_t SR2; 363 __IO uint32_t CCR; 364 __IO uint32_t TRISE; 365 } I2C_TypeDef; 366 367 /** 368 * @brief Independent WATCHDOG 369 */ 370 371 typedef struct 372 { 373 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ 374 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ 375 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ 376 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ 377 } IWDG_TypeDef; 378 379 /** 380 * @brief Power Control 381 */ 382 383 typedef struct 384 { 385 __IO uint32_t CR; 386 __IO uint32_t CSR; 387 } PWR_TypeDef; 388 389 /** 390 * @brief Reset and Clock Control 391 */ 392 393 typedef struct 394 { 395 __IO uint32_t CR; 396 __IO uint32_t CFGR; 397 __IO uint32_t CIR; 398 __IO uint32_t APB2RSTR; 399 __IO uint32_t APB1RSTR; 400 __IO uint32_t AHBENR; 401 __IO uint32_t APB2ENR; 402 __IO uint32_t APB1ENR; 403 __IO uint32_t BDCR; 404 __IO uint32_t CSR; 405 406 407 uint32_t RESERVED0; 408 __IO uint32_t CFGR2; 409 } RCC_TypeDef; 410 411 /** 412 * @brief Real-Time Clock 413 */ 414 415 typedef struct 416 { 417 __IO uint32_t CRH; 418 __IO uint32_t CRL; 419 __IO uint32_t PRLH; 420 __IO uint32_t PRLL; 421 __IO uint32_t DIVH; 422 __IO uint32_t DIVL; 423 __IO uint32_t CNTH; 424 __IO uint32_t CNTL; 425 __IO uint32_t ALRH; 426 __IO uint32_t ALRL; 427 } RTC_TypeDef; 428 429 /** 430 * @brief Serial Peripheral Interface 431 */ 432 433 typedef struct 434 { 435 __IO uint32_t CR1; 436 __IO uint32_t CR2; 437 __IO uint32_t SR; 438 __IO uint32_t DR; 439 __IO uint32_t CRCPR; 440 __IO uint32_t RXCRCR; 441 __IO uint32_t TXCRCR; 442 } SPI_TypeDef; 443 444 /** 445 * @brief TIM Timers 446 */ 447 typedef struct 448 { 449 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 450 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 451 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 452 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 453 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 454 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 455 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 456 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 457 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 458 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 459 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 460 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 461 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 462 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 463 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 464 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 465 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 466 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 467 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 468 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 469 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 470 }TIM_TypeDef; 471 472 473 /** 474 * @brief Universal Synchronous Asynchronous Receiver Transmitter 475 */ 476 477 typedef struct 478 { 479 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ 480 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ 481 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ 482 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ 483 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ 484 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ 485 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 486 } USART_TypeDef; 487 488 489 490 /** 491 * @brief Window WATCHDOG 492 */ 493 494 typedef struct 495 { 496 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 497 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 498 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 499 } WWDG_TypeDef; 500 501 /** 502 * @} 503 */ 504 505 /** @addtogroup Peripheral_memory_map 506 * @{ 507 */ 508 509 510 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ 511 #define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */ 512 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ 513 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ 514 515 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ 516 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ 517 518 519 /*!< Peripheral memory map */ 520 #define APB1PERIPH_BASE PERIPH_BASE 521 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) 522 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) 523 524 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) 525 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) 526 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) 527 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) 528 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) 529 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) 530 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) 531 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) 532 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) 533 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) 534 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) 535 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) 536 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) 537 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) 538 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) 539 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) 540 #define CEC_BASE (APB1PERIPH_BASE + 0x00007800UL) 541 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) 542 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) 543 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) 544 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) 545 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) 546 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) 547 #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) 548 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) 549 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) 550 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) 551 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) 552 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000UL) 553 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400UL) 554 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800UL) 555 556 557 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) 558 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) 559 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) 560 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) 561 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) 562 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) 563 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) 564 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) 565 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) 566 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) 567 568 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ 569 #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ 570 #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ 571 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ 572 573 574 575 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ 576 577 578 579 /** 580 * @} 581 */ 582 583 /** @addtogroup Peripheral_declaration 584 * @{ 585 */ 586 587 #define TIM2 ((TIM_TypeDef *)TIM2_BASE) 588 #define TIM3 ((TIM_TypeDef *)TIM3_BASE) 589 #define TIM4 ((TIM_TypeDef *)TIM4_BASE) 590 #define TIM6 ((TIM_TypeDef *)TIM6_BASE) 591 #define TIM7 ((TIM_TypeDef *)TIM7_BASE) 592 #define RTC ((RTC_TypeDef *)RTC_BASE) 593 #define WWDG ((WWDG_TypeDef *)WWDG_BASE) 594 #define IWDG ((IWDG_TypeDef *)IWDG_BASE) 595 #define SPI2 ((SPI_TypeDef *)SPI2_BASE) 596 #define USART2 ((USART_TypeDef *)USART2_BASE) 597 #define USART3 ((USART_TypeDef *)USART3_BASE) 598 #define I2C1 ((I2C_TypeDef *)I2C1_BASE) 599 #define I2C2 ((I2C_TypeDef *)I2C2_BASE) 600 #define BKP ((BKP_TypeDef *)BKP_BASE) 601 #define PWR ((PWR_TypeDef *)PWR_BASE) 602 #define DAC1 ((DAC_TypeDef *)DAC_BASE) 603 #define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ 604 #define CEC ((CEC_TypeDef *)CEC_BASE) 605 #define AFIO ((AFIO_TypeDef *)AFIO_BASE) 606 #define EXTI ((EXTI_TypeDef *)EXTI_BASE) 607 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) 608 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) 609 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) 610 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) 611 #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) 612 #define ADC1 ((ADC_TypeDef *)ADC1_BASE) 613 #define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) 614 #define TIM1 ((TIM_TypeDef *)TIM1_BASE) 615 #define SPI1 ((SPI_TypeDef *)SPI1_BASE) 616 #define USART1 ((USART_TypeDef *)USART1_BASE) 617 #define TIM15 ((TIM_TypeDef *)TIM15_BASE) 618 #define TIM16 ((TIM_TypeDef *)TIM16_BASE) 619 #define TIM17 ((TIM_TypeDef *)TIM17_BASE) 620 #define DMA1 ((DMA_TypeDef *)DMA1_BASE) 621 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) 622 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) 623 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) 624 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) 625 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) 626 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) 627 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) 628 #define RCC ((RCC_TypeDef *)RCC_BASE) 629 #define CRC ((CRC_TypeDef *)CRC_BASE) 630 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) 631 #define OB ((OB_TypeDef *)OB_BASE) 632 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) 633 634 635 /** 636 * @} 637 */ 638 639 /** @addtogroup Exported_constants 640 * @{ 641 */ 642 643 /** @addtogroup Hardware_Constant_Definition 644 * @{ 645 */ 646 #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ 647 /** 648 * @} 649 */ 650 651 /** @addtogroup Peripheral_Registers_Bits_Definition 652 * @{ 653 */ 654 655 /******************************************************************************/ 656 /* Peripheral Registers_Bits_Definition */ 657 /******************************************************************************/ 658 659 /******************************************************************************/ 660 /* */ 661 /* CRC calculation unit (CRC) */ 662 /* */ 663 /******************************************************************************/ 664 665 /******************* Bit definition for CRC_DR register *********************/ 666 #define CRC_DR_DR_Pos (0U) 667 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 668 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 669 670 /******************* Bit definition for CRC_IDR register ********************/ 671 #define CRC_IDR_IDR_Pos (0U) 672 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 673 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 674 675 /******************** Bit definition for CRC_CR register ********************/ 676 #define CRC_CR_RESET_Pos (0U) 677 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 678 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 679 680 /******************************************************************************/ 681 /* */ 682 /* Power Control */ 683 /* */ 684 /******************************************************************************/ 685 686 /******************** Bit definition for PWR_CR register ********************/ 687 #define PWR_CR_LPDS_Pos (0U) 688 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 689 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ 690 #define PWR_CR_PDDS_Pos (1U) 691 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 692 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 693 #define PWR_CR_CWUF_Pos (2U) 694 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 695 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 696 #define PWR_CR_CSBF_Pos (3U) 697 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 698 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 699 #define PWR_CR_PVDE_Pos (4U) 700 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 701 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 702 703 #define PWR_CR_PLS_Pos (5U) 704 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 705 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 706 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 707 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 708 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 709 710 /*!< PVD level configuration */ 711 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ 712 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ 713 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ 714 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ 715 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ 716 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ 717 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ 718 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ 719 720 /* Legacy defines */ 721 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 722 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 723 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 724 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 725 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 726 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 727 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 728 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 729 730 #define PWR_CR_DBP_Pos (8U) 731 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 732 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 733 734 735 /******************* Bit definition for PWR_CSR register ********************/ 736 #define PWR_CSR_WUF_Pos (0U) 737 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 738 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 739 #define PWR_CSR_SBF_Pos (1U) 740 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 741 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 742 #define PWR_CSR_PVDO_Pos (2U) 743 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 744 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 745 #define PWR_CSR_EWUP_Pos (8U) 746 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ 747 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ 748 749 /******************************************************************************/ 750 /* */ 751 /* Backup registers */ 752 /* */ 753 /******************************************************************************/ 754 755 /******************* Bit definition for BKP_DR1 register ********************/ 756 #define BKP_DR1_D_Pos (0U) 757 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ 758 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ 759 760 /******************* Bit definition for BKP_DR2 register ********************/ 761 #define BKP_DR2_D_Pos (0U) 762 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ 763 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ 764 765 /******************* Bit definition for BKP_DR3 register ********************/ 766 #define BKP_DR3_D_Pos (0U) 767 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ 768 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ 769 770 /******************* Bit definition for BKP_DR4 register ********************/ 771 #define BKP_DR4_D_Pos (0U) 772 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ 773 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ 774 775 /******************* Bit definition for BKP_DR5 register ********************/ 776 #define BKP_DR5_D_Pos (0U) 777 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ 778 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ 779 780 /******************* Bit definition for BKP_DR6 register ********************/ 781 #define BKP_DR6_D_Pos (0U) 782 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ 783 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ 784 785 /******************* Bit definition for BKP_DR7 register ********************/ 786 #define BKP_DR7_D_Pos (0U) 787 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ 788 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ 789 790 /******************* Bit definition for BKP_DR8 register ********************/ 791 #define BKP_DR8_D_Pos (0U) 792 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ 793 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ 794 795 /******************* Bit definition for BKP_DR9 register ********************/ 796 #define BKP_DR9_D_Pos (0U) 797 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ 798 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ 799 800 /******************* Bit definition for BKP_DR10 register *******************/ 801 #define BKP_DR10_D_Pos (0U) 802 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ 803 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ 804 805 #define RTC_BKP_NUMBER 10 806 807 /****************** Bit definition for BKP_RTCCR register *******************/ 808 #define BKP_RTCCR_CAL_Pos (0U) 809 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ 810 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ 811 #define BKP_RTCCR_CCO_Pos (7U) 812 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ 813 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ 814 #define BKP_RTCCR_ASOE_Pos (8U) 815 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ 816 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ 817 #define BKP_RTCCR_ASOS_Pos (9U) 818 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ 819 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ 820 821 /******************** Bit definition for BKP_CR register ********************/ 822 #define BKP_CR_TPE_Pos (0U) 823 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ 824 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ 825 #define BKP_CR_TPAL_Pos (1U) 826 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ 827 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ 828 829 /******************* Bit definition for BKP_CSR register ********************/ 830 #define BKP_CSR_CTE_Pos (0U) 831 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ 832 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ 833 #define BKP_CSR_CTI_Pos (1U) 834 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ 835 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ 836 #define BKP_CSR_TPIE_Pos (2U) 837 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ 838 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ 839 #define BKP_CSR_TEF_Pos (8U) 840 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ 841 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ 842 #define BKP_CSR_TIF_Pos (9U) 843 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ 844 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ 845 846 /******************************************************************************/ 847 /* */ 848 /* Reset and Clock Control */ 849 /* */ 850 /******************************************************************************/ 851 852 /******************** Bit definition for RCC_CR register ********************/ 853 #define RCC_CR_HSION_Pos (0U) 854 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 855 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 856 #define RCC_CR_HSIRDY_Pos (1U) 857 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 858 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 859 #define RCC_CR_HSITRIM_Pos (3U) 860 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 861 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 862 #define RCC_CR_HSICAL_Pos (8U) 863 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 864 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 865 #define RCC_CR_HSEON_Pos (16U) 866 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 867 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 868 #define RCC_CR_HSERDY_Pos (17U) 869 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 870 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 871 #define RCC_CR_HSEBYP_Pos (18U) 872 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 873 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 874 #define RCC_CR_CSSON_Pos (19U) 875 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 876 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 877 #define RCC_CR_PLLON_Pos (24U) 878 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 879 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 880 #define RCC_CR_PLLRDY_Pos (25U) 881 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 882 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 883 884 885 /******************* Bit definition for RCC_CFGR register *******************/ 886 /*!< SW configuration */ 887 #define RCC_CFGR_SW_Pos (0U) 888 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 889 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 890 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 891 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 892 893 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ 894 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ 895 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ 896 897 /*!< SWS configuration */ 898 #define RCC_CFGR_SWS_Pos (2U) 899 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 900 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 901 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 902 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 903 904 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ 905 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ 906 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ 907 908 /*!< HPRE configuration */ 909 #define RCC_CFGR_HPRE_Pos (4U) 910 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 911 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 912 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 913 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 914 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 915 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 916 917 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ 918 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ 919 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ 920 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ 921 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ 922 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ 923 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ 924 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ 925 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ 926 927 /*!< PPRE1 configuration */ 928 #define RCC_CFGR_PPRE1_Pos (8U) 929 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 930 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 931 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 932 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 933 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 934 935 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ 936 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ 937 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ 938 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ 939 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ 940 941 /*!< PPRE2 configuration */ 942 #define RCC_CFGR_PPRE2_Pos (11U) 943 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 944 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 945 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 946 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 947 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 948 949 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ 950 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ 951 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ 952 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ 953 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ 954 955 /*!< ADCPPRE configuration */ 956 #define RCC_CFGR_ADCPRE_Pos (14U) 957 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ 958 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ 959 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 960 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ 961 962 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ 963 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ 964 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ 965 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ 966 967 #define RCC_CFGR_PLLSRC_Pos (16U) 968 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 969 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 970 971 #define RCC_CFGR_PLLXTPRE_Pos (17U) 972 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 973 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 974 975 /*!< PLLMUL configuration */ 976 #define RCC_CFGR_PLLMULL_Pos (18U) 977 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ 978 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 979 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ 980 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ 981 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ 982 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ 983 984 #define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ 985 #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ 986 987 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ 988 #define RCC_CFGR_PLLMULL3_Pos (18U) 989 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ 990 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ 991 #define RCC_CFGR_PLLMULL4_Pos (19U) 992 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ 993 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ 994 #define RCC_CFGR_PLLMULL5_Pos (18U) 995 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ 996 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ 997 #define RCC_CFGR_PLLMULL6_Pos (20U) 998 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ 999 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ 1000 #define RCC_CFGR_PLLMULL7_Pos (18U) 1001 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ 1002 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ 1003 #define RCC_CFGR_PLLMULL8_Pos (19U) 1004 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ 1005 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ 1006 #define RCC_CFGR_PLLMULL9_Pos (18U) 1007 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ 1008 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ 1009 #define RCC_CFGR_PLLMULL10_Pos (21U) 1010 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ 1011 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ 1012 #define RCC_CFGR_PLLMULL11_Pos (18U) 1013 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ 1014 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ 1015 #define RCC_CFGR_PLLMULL12_Pos (19U) 1016 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ 1017 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ 1018 #define RCC_CFGR_PLLMULL13_Pos (18U) 1019 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ 1020 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ 1021 #define RCC_CFGR_PLLMULL14_Pos (20U) 1022 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ 1023 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ 1024 #define RCC_CFGR_PLLMULL15_Pos (18U) 1025 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ 1026 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ 1027 #define RCC_CFGR_PLLMULL16_Pos (19U) 1028 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ 1029 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ 1030 1031 /*!< MCO configuration */ 1032 #define RCC_CFGR_MCO_Pos (24U) 1033 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 1034 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 1035 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 1036 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 1037 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 1038 1039 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ 1040 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ 1041 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ 1042 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ 1043 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ 1044 1045 /* Reference defines */ 1046 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 1047 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 1048 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 1049 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 1050 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 1051 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 1052 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 1053 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 1054 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 1055 1056 /*!<****************** Bit definition for RCC_CIR register ********************/ 1057 #define RCC_CIR_LSIRDYF_Pos (0U) 1058 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 1059 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 1060 #define RCC_CIR_LSERDYF_Pos (1U) 1061 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 1062 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 1063 #define RCC_CIR_HSIRDYF_Pos (2U) 1064 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 1065 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 1066 #define RCC_CIR_HSERDYF_Pos (3U) 1067 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 1068 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 1069 #define RCC_CIR_PLLRDYF_Pos (4U) 1070 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 1071 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 1072 #define RCC_CIR_CSSF_Pos (7U) 1073 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 1074 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 1075 #define RCC_CIR_LSIRDYIE_Pos (8U) 1076 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 1077 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 1078 #define RCC_CIR_LSERDYIE_Pos (9U) 1079 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 1080 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 1081 #define RCC_CIR_HSIRDYIE_Pos (10U) 1082 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 1083 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 1084 #define RCC_CIR_HSERDYIE_Pos (11U) 1085 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 1086 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 1087 #define RCC_CIR_PLLRDYIE_Pos (12U) 1088 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 1089 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 1090 #define RCC_CIR_LSIRDYC_Pos (16U) 1091 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 1092 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 1093 #define RCC_CIR_LSERDYC_Pos (17U) 1094 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 1095 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 1096 #define RCC_CIR_HSIRDYC_Pos (18U) 1097 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 1098 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 1099 #define RCC_CIR_HSERDYC_Pos (19U) 1100 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 1101 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 1102 #define RCC_CIR_PLLRDYC_Pos (20U) 1103 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 1104 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 1105 #define RCC_CIR_CSSC_Pos (23U) 1106 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 1107 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 1108 1109 1110 /***************** Bit definition for RCC_APB2RSTR register *****************/ 1111 #define RCC_APB2RSTR_AFIORST_Pos (0U) 1112 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ 1113 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ 1114 #define RCC_APB2RSTR_IOPARST_Pos (2U) 1115 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ 1116 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ 1117 #define RCC_APB2RSTR_IOPBRST_Pos (3U) 1118 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ 1119 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ 1120 #define RCC_APB2RSTR_IOPCRST_Pos (4U) 1121 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ 1122 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ 1123 #define RCC_APB2RSTR_IOPDRST_Pos (5U) 1124 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ 1125 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ 1126 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 1127 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 1128 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ 1129 1130 1131 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 1132 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 1133 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ 1134 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 1135 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 1136 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ 1137 #define RCC_APB2RSTR_USART1RST_Pos (14U) 1138 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 1139 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 1140 1141 #define RCC_APB2RSTR_TIM15RST_Pos (16U) 1142 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */ 1143 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 Timer reset */ 1144 #define RCC_APB2RSTR_TIM16RST_Pos (17U) 1145 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ 1146 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 Timer reset */ 1147 #define RCC_APB2RSTR_TIM17RST_Pos (18U) 1148 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ 1149 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 Timer reset */ 1150 1151 #define RCC_APB2RSTR_IOPERST_Pos (6U) 1152 #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ 1153 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ 1154 1155 1156 1157 1158 /***************** Bit definition for RCC_APB1RSTR register *****************/ 1159 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 1160 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 1161 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 1162 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 1163 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 1164 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 1165 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 1166 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 1167 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 1168 #define RCC_APB1RSTR_USART2RST_Pos (17U) 1169 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 1170 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 1171 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 1172 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 1173 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 1174 1175 1176 #define RCC_APB1RSTR_BKPRST_Pos (27U) 1177 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ 1178 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ 1179 #define RCC_APB1RSTR_PWRRST_Pos (28U) 1180 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 1181 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 1182 1183 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 1184 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 1185 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 1186 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 1187 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 1188 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 1189 #define RCC_APB1RSTR_USART3RST_Pos (18U) 1190 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 1191 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 1192 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 1193 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 1194 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 1195 1196 1197 1198 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 1199 #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 1200 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ 1201 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 1202 #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 1203 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ 1204 #define RCC_APB1RSTR_CECRST_Pos (30U) 1205 #define RCC_APB1RSTR_CECRST_Msk (0x1UL << RCC_APB1RSTR_CECRST_Pos) /*!< 0x40000000 */ 1206 #define RCC_APB1RSTR_CECRST RCC_APB1RSTR_CECRST_Msk /*!< CEC interface reset */ 1207 1208 1209 1210 #define RCC_APB1RSTR_DACRST_Pos (29U) 1211 #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ 1212 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ 1213 1214 /****************** Bit definition for RCC_AHBENR register ******************/ 1215 #define RCC_AHBENR_DMA1EN_Pos (0U) 1216 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 1217 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 1218 #define RCC_AHBENR_SRAMEN_Pos (2U) 1219 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 1220 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 1221 #define RCC_AHBENR_FLITFEN_Pos (4U) 1222 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 1223 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 1224 #define RCC_AHBENR_CRCEN_Pos (6U) 1225 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 1226 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 1227 1228 1229 1230 1231 /****************** Bit definition for RCC_APB2ENR register *****************/ 1232 #define RCC_APB2ENR_AFIOEN_Pos (0U) 1233 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ 1234 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ 1235 #define RCC_APB2ENR_IOPAEN_Pos (2U) 1236 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ 1237 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ 1238 #define RCC_APB2ENR_IOPBEN_Pos (3U) 1239 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ 1240 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ 1241 #define RCC_APB2ENR_IOPCEN_Pos (4U) 1242 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ 1243 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ 1244 #define RCC_APB2ENR_IOPDEN_Pos (5U) 1245 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ 1246 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ 1247 #define RCC_APB2ENR_ADC1EN_Pos (9U) 1248 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 1249 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ 1250 1251 1252 #define RCC_APB2ENR_TIM1EN_Pos (11U) 1253 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 1254 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ 1255 #define RCC_APB2ENR_SPI1EN_Pos (12U) 1256 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 1257 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ 1258 #define RCC_APB2ENR_USART1EN_Pos (14U) 1259 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 1260 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 1261 1262 #define RCC_APB2ENR_TIM15EN_Pos (16U) 1263 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */ 1264 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 Timer clock enable */ 1265 #define RCC_APB2ENR_TIM16EN_Pos (17U) 1266 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ 1267 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 Timer clock enable */ 1268 #define RCC_APB2ENR_TIM17EN_Pos (18U) 1269 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ 1270 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 Timer clock enable */ 1271 1272 #define RCC_APB2ENR_IOPEEN_Pos (6U) 1273 #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ 1274 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ 1275 1276 1277 1278 1279 /***************** Bit definition for RCC_APB1ENR register ******************/ 1280 #define RCC_APB1ENR_TIM2EN_Pos (0U) 1281 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 1282 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 1283 #define RCC_APB1ENR_TIM3EN_Pos (1U) 1284 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 1285 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 1286 #define RCC_APB1ENR_WWDGEN_Pos (11U) 1287 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 1288 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 1289 #define RCC_APB1ENR_USART2EN_Pos (17U) 1290 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 1291 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 1292 #define RCC_APB1ENR_I2C1EN_Pos (21U) 1293 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 1294 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 1295 1296 1297 #define RCC_APB1ENR_BKPEN_Pos (27U) 1298 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ 1299 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ 1300 #define RCC_APB1ENR_PWREN_Pos (28U) 1301 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 1302 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 1303 1304 #define RCC_APB1ENR_TIM4EN_Pos (2U) 1305 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 1306 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 1307 #define RCC_APB1ENR_SPI2EN_Pos (14U) 1308 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 1309 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 1310 #define RCC_APB1ENR_USART3EN_Pos (18U) 1311 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 1312 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 1313 #define RCC_APB1ENR_I2C2EN_Pos (22U) 1314 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 1315 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 1316 1317 1318 1319 #define RCC_APB1ENR_TIM6EN_Pos (4U) 1320 #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 1321 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 1322 #define RCC_APB1ENR_TIM7EN_Pos (5U) 1323 #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 1324 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 1325 #define RCC_APB1ENR_CECEN_Pos (30U) 1326 #define RCC_APB1ENR_CECEN_Msk (0x1UL << RCC_APB1ENR_CECEN_Pos) /*!< 0x40000000 */ 1327 #define RCC_APB1ENR_CECEN RCC_APB1ENR_CECEN_Msk /*!< CEC interface clock enable */ 1328 1329 1330 1331 #define RCC_APB1ENR_DACEN_Pos (29U) 1332 #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ 1333 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ 1334 1335 /******************* Bit definition for RCC_BDCR register *******************/ 1336 #define RCC_BDCR_LSEON_Pos (0U) 1337 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 1338 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 1339 #define RCC_BDCR_LSERDY_Pos (1U) 1340 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 1341 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 1342 #define RCC_BDCR_LSEBYP_Pos (2U) 1343 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 1344 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 1345 1346 #define RCC_BDCR_RTCSEL_Pos (8U) 1347 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 1348 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 1349 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 1350 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 1351 1352 /*!< RTC configuration */ 1353 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ 1354 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ 1355 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ 1356 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ 1357 1358 #define RCC_BDCR_RTCEN_Pos (15U) 1359 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 1360 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 1361 #define RCC_BDCR_BDRST_Pos (16U) 1362 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 1363 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 1364 1365 /******************* Bit definition for RCC_CSR register ********************/ 1366 #define RCC_CSR_LSION_Pos (0U) 1367 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 1368 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 1369 #define RCC_CSR_LSIRDY_Pos (1U) 1370 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 1371 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 1372 #define RCC_CSR_RMVF_Pos (24U) 1373 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 1374 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 1375 #define RCC_CSR_PINRSTF_Pos (26U) 1376 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 1377 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 1378 #define RCC_CSR_PORRSTF_Pos (27U) 1379 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 1380 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 1381 #define RCC_CSR_SFTRSTF_Pos (28U) 1382 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 1383 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 1384 #define RCC_CSR_IWDGRSTF_Pos (29U) 1385 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 1386 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 1387 #define RCC_CSR_WWDGRSTF_Pos (30U) 1388 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 1389 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 1390 #define RCC_CSR_LPWRRSTF_Pos (31U) 1391 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 1392 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 1393 1394 1395 /******************* Bit definition for RCC_CFGR2 register ******************/ 1396 /*!< PREDIV1 configuration */ 1397 #define RCC_CFGR2_PREDIV1_Pos (0U) 1398 #define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ 1399 #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ 1400 #define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ 1401 #define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ 1402 #define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ 1403 #define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ 1404 1405 #define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ 1406 #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) 1407 #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ 1408 #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ 1409 #define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) 1410 #define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ 1411 #define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ 1412 #define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) 1413 #define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ 1414 #define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ 1415 #define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) 1416 #define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ 1417 #define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ 1418 #define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) 1419 #define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ 1420 #define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ 1421 #define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) 1422 #define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ 1423 #define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ 1424 #define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) 1425 #define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ 1426 #define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ 1427 #define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) 1428 #define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ 1429 #define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ 1430 #define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) 1431 #define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ 1432 #define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ 1433 #define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) 1434 #define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ 1435 #define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ 1436 #define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) 1437 #define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ 1438 #define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ 1439 #define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) 1440 #define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ 1441 #define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ 1442 #define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) 1443 #define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ 1444 #define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ 1445 #define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) 1446 #define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ 1447 #define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ 1448 #define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) 1449 #define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ 1450 #define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ 1451 1452 /******************************************************************************/ 1453 /* */ 1454 /* General Purpose and Alternate Function I/O */ 1455 /* */ 1456 /******************************************************************************/ 1457 1458 /******************* Bit definition for GPIO_CRL register *******************/ 1459 #define GPIO_CRL_MODE_Pos (0U) 1460 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ 1461 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ 1462 1463 #define GPIO_CRL_MODE0_Pos (0U) 1464 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ 1465 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ 1466 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ 1467 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ 1468 1469 #define GPIO_CRL_MODE1_Pos (4U) 1470 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ 1471 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ 1472 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ 1473 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ 1474 1475 #define GPIO_CRL_MODE2_Pos (8U) 1476 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ 1477 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ 1478 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ 1479 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ 1480 1481 #define GPIO_CRL_MODE3_Pos (12U) 1482 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ 1483 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ 1484 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ 1485 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ 1486 1487 #define GPIO_CRL_MODE4_Pos (16U) 1488 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ 1489 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ 1490 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ 1491 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ 1492 1493 #define GPIO_CRL_MODE5_Pos (20U) 1494 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ 1495 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ 1496 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ 1497 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ 1498 1499 #define GPIO_CRL_MODE6_Pos (24U) 1500 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ 1501 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ 1502 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ 1503 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ 1504 1505 #define GPIO_CRL_MODE7_Pos (28U) 1506 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ 1507 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ 1508 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ 1509 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ 1510 1511 #define GPIO_CRL_CNF_Pos (2U) 1512 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ 1513 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ 1514 1515 #define GPIO_CRL_CNF0_Pos (2U) 1516 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ 1517 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ 1518 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ 1519 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ 1520 1521 #define GPIO_CRL_CNF1_Pos (6U) 1522 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ 1523 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ 1524 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ 1525 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ 1526 1527 #define GPIO_CRL_CNF2_Pos (10U) 1528 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ 1529 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ 1530 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ 1531 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ 1532 1533 #define GPIO_CRL_CNF3_Pos (14U) 1534 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ 1535 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ 1536 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ 1537 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ 1538 1539 #define GPIO_CRL_CNF4_Pos (18U) 1540 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ 1541 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ 1542 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ 1543 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ 1544 1545 #define GPIO_CRL_CNF5_Pos (22U) 1546 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ 1547 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ 1548 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ 1549 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ 1550 1551 #define GPIO_CRL_CNF6_Pos (26U) 1552 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ 1553 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ 1554 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ 1555 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ 1556 1557 #define GPIO_CRL_CNF7_Pos (30U) 1558 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ 1559 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ 1560 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ 1561 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ 1562 1563 /******************* Bit definition for GPIO_CRH register *******************/ 1564 #define GPIO_CRH_MODE_Pos (0U) 1565 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ 1566 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ 1567 1568 #define GPIO_CRH_MODE8_Pos (0U) 1569 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ 1570 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ 1571 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ 1572 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ 1573 1574 #define GPIO_CRH_MODE9_Pos (4U) 1575 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ 1576 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ 1577 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ 1578 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ 1579 1580 #define GPIO_CRH_MODE10_Pos (8U) 1581 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ 1582 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ 1583 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ 1584 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ 1585 1586 #define GPIO_CRH_MODE11_Pos (12U) 1587 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ 1588 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ 1589 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ 1590 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ 1591 1592 #define GPIO_CRH_MODE12_Pos (16U) 1593 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ 1594 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ 1595 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ 1596 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ 1597 1598 #define GPIO_CRH_MODE13_Pos (20U) 1599 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ 1600 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ 1601 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ 1602 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ 1603 1604 #define GPIO_CRH_MODE14_Pos (24U) 1605 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ 1606 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ 1607 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ 1608 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ 1609 1610 #define GPIO_CRH_MODE15_Pos (28U) 1611 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ 1612 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ 1613 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ 1614 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ 1615 1616 #define GPIO_CRH_CNF_Pos (2U) 1617 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ 1618 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ 1619 1620 #define GPIO_CRH_CNF8_Pos (2U) 1621 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ 1622 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ 1623 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ 1624 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ 1625 1626 #define GPIO_CRH_CNF9_Pos (6U) 1627 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ 1628 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ 1629 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ 1630 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ 1631 1632 #define GPIO_CRH_CNF10_Pos (10U) 1633 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ 1634 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ 1635 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ 1636 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ 1637 1638 #define GPIO_CRH_CNF11_Pos (14U) 1639 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ 1640 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ 1641 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ 1642 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ 1643 1644 #define GPIO_CRH_CNF12_Pos (18U) 1645 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ 1646 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ 1647 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ 1648 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ 1649 1650 #define GPIO_CRH_CNF13_Pos (22U) 1651 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ 1652 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ 1653 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ 1654 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ 1655 1656 #define GPIO_CRH_CNF14_Pos (26U) 1657 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ 1658 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ 1659 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ 1660 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ 1661 1662 #define GPIO_CRH_CNF15_Pos (30U) 1663 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ 1664 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ 1665 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ 1666 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ 1667 1668 /*!<****************** Bit definition for GPIO_IDR register *******************/ 1669 #define GPIO_IDR_IDR0_Pos (0U) 1670 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ 1671 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ 1672 #define GPIO_IDR_IDR1_Pos (1U) 1673 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ 1674 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ 1675 #define GPIO_IDR_IDR2_Pos (2U) 1676 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ 1677 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ 1678 #define GPIO_IDR_IDR3_Pos (3U) 1679 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ 1680 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ 1681 #define GPIO_IDR_IDR4_Pos (4U) 1682 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ 1683 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ 1684 #define GPIO_IDR_IDR5_Pos (5U) 1685 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ 1686 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ 1687 #define GPIO_IDR_IDR6_Pos (6U) 1688 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ 1689 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ 1690 #define GPIO_IDR_IDR7_Pos (7U) 1691 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ 1692 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ 1693 #define GPIO_IDR_IDR8_Pos (8U) 1694 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ 1695 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ 1696 #define GPIO_IDR_IDR9_Pos (9U) 1697 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ 1698 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ 1699 #define GPIO_IDR_IDR10_Pos (10U) 1700 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ 1701 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ 1702 #define GPIO_IDR_IDR11_Pos (11U) 1703 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ 1704 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ 1705 #define GPIO_IDR_IDR12_Pos (12U) 1706 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ 1707 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ 1708 #define GPIO_IDR_IDR13_Pos (13U) 1709 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ 1710 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ 1711 #define GPIO_IDR_IDR14_Pos (14U) 1712 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ 1713 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ 1714 #define GPIO_IDR_IDR15_Pos (15U) 1715 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ 1716 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ 1717 1718 /******************* Bit definition for GPIO_ODR register *******************/ 1719 #define GPIO_ODR_ODR0_Pos (0U) 1720 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ 1721 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ 1722 #define GPIO_ODR_ODR1_Pos (1U) 1723 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ 1724 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ 1725 #define GPIO_ODR_ODR2_Pos (2U) 1726 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ 1727 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ 1728 #define GPIO_ODR_ODR3_Pos (3U) 1729 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ 1730 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ 1731 #define GPIO_ODR_ODR4_Pos (4U) 1732 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ 1733 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ 1734 #define GPIO_ODR_ODR5_Pos (5U) 1735 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ 1736 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ 1737 #define GPIO_ODR_ODR6_Pos (6U) 1738 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ 1739 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ 1740 #define GPIO_ODR_ODR7_Pos (7U) 1741 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ 1742 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ 1743 #define GPIO_ODR_ODR8_Pos (8U) 1744 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ 1745 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ 1746 #define GPIO_ODR_ODR9_Pos (9U) 1747 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ 1748 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ 1749 #define GPIO_ODR_ODR10_Pos (10U) 1750 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ 1751 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ 1752 #define GPIO_ODR_ODR11_Pos (11U) 1753 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ 1754 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ 1755 #define GPIO_ODR_ODR12_Pos (12U) 1756 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ 1757 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ 1758 #define GPIO_ODR_ODR13_Pos (13U) 1759 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ 1760 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ 1761 #define GPIO_ODR_ODR14_Pos (14U) 1762 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ 1763 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ 1764 #define GPIO_ODR_ODR15_Pos (15U) 1765 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ 1766 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ 1767 1768 /****************** Bit definition for GPIO_BSRR register *******************/ 1769 #define GPIO_BSRR_BS0_Pos (0U) 1770 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 1771 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ 1772 #define GPIO_BSRR_BS1_Pos (1U) 1773 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 1774 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ 1775 #define GPIO_BSRR_BS2_Pos (2U) 1776 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 1777 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ 1778 #define GPIO_BSRR_BS3_Pos (3U) 1779 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 1780 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ 1781 #define GPIO_BSRR_BS4_Pos (4U) 1782 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 1783 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ 1784 #define GPIO_BSRR_BS5_Pos (5U) 1785 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 1786 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ 1787 #define GPIO_BSRR_BS6_Pos (6U) 1788 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 1789 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ 1790 #define GPIO_BSRR_BS7_Pos (7U) 1791 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 1792 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ 1793 #define GPIO_BSRR_BS8_Pos (8U) 1794 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 1795 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ 1796 #define GPIO_BSRR_BS9_Pos (9U) 1797 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 1798 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ 1799 #define GPIO_BSRR_BS10_Pos (10U) 1800 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 1801 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ 1802 #define GPIO_BSRR_BS11_Pos (11U) 1803 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 1804 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ 1805 #define GPIO_BSRR_BS12_Pos (12U) 1806 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 1807 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ 1808 #define GPIO_BSRR_BS13_Pos (13U) 1809 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 1810 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ 1811 #define GPIO_BSRR_BS14_Pos (14U) 1812 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 1813 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ 1814 #define GPIO_BSRR_BS15_Pos (15U) 1815 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 1816 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ 1817 1818 #define GPIO_BSRR_BR0_Pos (16U) 1819 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 1820 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ 1821 #define GPIO_BSRR_BR1_Pos (17U) 1822 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 1823 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ 1824 #define GPIO_BSRR_BR2_Pos (18U) 1825 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 1826 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ 1827 #define GPIO_BSRR_BR3_Pos (19U) 1828 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 1829 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ 1830 #define GPIO_BSRR_BR4_Pos (20U) 1831 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 1832 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ 1833 #define GPIO_BSRR_BR5_Pos (21U) 1834 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 1835 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ 1836 #define GPIO_BSRR_BR6_Pos (22U) 1837 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 1838 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ 1839 #define GPIO_BSRR_BR7_Pos (23U) 1840 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 1841 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ 1842 #define GPIO_BSRR_BR8_Pos (24U) 1843 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 1844 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ 1845 #define GPIO_BSRR_BR9_Pos (25U) 1846 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 1847 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ 1848 #define GPIO_BSRR_BR10_Pos (26U) 1849 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 1850 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ 1851 #define GPIO_BSRR_BR11_Pos (27U) 1852 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 1853 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ 1854 #define GPIO_BSRR_BR12_Pos (28U) 1855 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 1856 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ 1857 #define GPIO_BSRR_BR13_Pos (29U) 1858 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 1859 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ 1860 #define GPIO_BSRR_BR14_Pos (30U) 1861 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 1862 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ 1863 #define GPIO_BSRR_BR15_Pos (31U) 1864 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 1865 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ 1866 1867 /******************* Bit definition for GPIO_BRR register *******************/ 1868 #define GPIO_BRR_BR0_Pos (0U) 1869 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 1870 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ 1871 #define GPIO_BRR_BR1_Pos (1U) 1872 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 1873 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ 1874 #define GPIO_BRR_BR2_Pos (2U) 1875 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 1876 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ 1877 #define GPIO_BRR_BR3_Pos (3U) 1878 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 1879 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ 1880 #define GPIO_BRR_BR4_Pos (4U) 1881 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 1882 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ 1883 #define GPIO_BRR_BR5_Pos (5U) 1884 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 1885 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ 1886 #define GPIO_BRR_BR6_Pos (6U) 1887 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 1888 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ 1889 #define GPIO_BRR_BR7_Pos (7U) 1890 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 1891 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ 1892 #define GPIO_BRR_BR8_Pos (8U) 1893 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 1894 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ 1895 #define GPIO_BRR_BR9_Pos (9U) 1896 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 1897 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ 1898 #define GPIO_BRR_BR10_Pos (10U) 1899 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 1900 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ 1901 #define GPIO_BRR_BR11_Pos (11U) 1902 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 1903 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ 1904 #define GPIO_BRR_BR12_Pos (12U) 1905 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 1906 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ 1907 #define GPIO_BRR_BR13_Pos (13U) 1908 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 1909 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ 1910 #define GPIO_BRR_BR14_Pos (14U) 1911 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 1912 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ 1913 #define GPIO_BRR_BR15_Pos (15U) 1914 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 1915 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ 1916 1917 /****************** Bit definition for GPIO_LCKR register *******************/ 1918 #define GPIO_LCKR_LCK0_Pos (0U) 1919 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 1920 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ 1921 #define GPIO_LCKR_LCK1_Pos (1U) 1922 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 1923 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ 1924 #define GPIO_LCKR_LCK2_Pos (2U) 1925 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 1926 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ 1927 #define GPIO_LCKR_LCK3_Pos (3U) 1928 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 1929 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ 1930 #define GPIO_LCKR_LCK4_Pos (4U) 1931 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 1932 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ 1933 #define GPIO_LCKR_LCK5_Pos (5U) 1934 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 1935 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ 1936 #define GPIO_LCKR_LCK6_Pos (6U) 1937 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 1938 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ 1939 #define GPIO_LCKR_LCK7_Pos (7U) 1940 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 1941 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ 1942 #define GPIO_LCKR_LCK8_Pos (8U) 1943 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 1944 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ 1945 #define GPIO_LCKR_LCK9_Pos (9U) 1946 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 1947 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ 1948 #define GPIO_LCKR_LCK10_Pos (10U) 1949 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 1950 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ 1951 #define GPIO_LCKR_LCK11_Pos (11U) 1952 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 1953 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ 1954 #define GPIO_LCKR_LCK12_Pos (12U) 1955 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 1956 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ 1957 #define GPIO_LCKR_LCK13_Pos (13U) 1958 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 1959 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ 1960 #define GPIO_LCKR_LCK14_Pos (14U) 1961 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 1962 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ 1963 #define GPIO_LCKR_LCK15_Pos (15U) 1964 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 1965 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ 1966 #define GPIO_LCKR_LCKK_Pos (16U) 1967 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 1968 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ 1969 1970 /*----------------------------------------------------------------------------*/ 1971 1972 /****************** Bit definition for AFIO_EVCR register *******************/ 1973 #define AFIO_EVCR_PIN_Pos (0U) 1974 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ 1975 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ 1976 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ 1977 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ 1978 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ 1979 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ 1980 1981 /*!< PIN configuration */ 1982 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ 1983 #define AFIO_EVCR_PIN_PX1_Pos (0U) 1984 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ 1985 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ 1986 #define AFIO_EVCR_PIN_PX2_Pos (1U) 1987 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ 1988 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ 1989 #define AFIO_EVCR_PIN_PX3_Pos (0U) 1990 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ 1991 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ 1992 #define AFIO_EVCR_PIN_PX4_Pos (2U) 1993 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ 1994 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ 1995 #define AFIO_EVCR_PIN_PX5_Pos (0U) 1996 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ 1997 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ 1998 #define AFIO_EVCR_PIN_PX6_Pos (1U) 1999 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ 2000 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ 2001 #define AFIO_EVCR_PIN_PX7_Pos (0U) 2002 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ 2003 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ 2004 #define AFIO_EVCR_PIN_PX8_Pos (3U) 2005 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ 2006 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ 2007 #define AFIO_EVCR_PIN_PX9_Pos (0U) 2008 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ 2009 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ 2010 #define AFIO_EVCR_PIN_PX10_Pos (1U) 2011 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ 2012 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ 2013 #define AFIO_EVCR_PIN_PX11_Pos (0U) 2014 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ 2015 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ 2016 #define AFIO_EVCR_PIN_PX12_Pos (2U) 2017 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ 2018 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ 2019 #define AFIO_EVCR_PIN_PX13_Pos (0U) 2020 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ 2021 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ 2022 #define AFIO_EVCR_PIN_PX14_Pos (1U) 2023 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ 2024 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ 2025 #define AFIO_EVCR_PIN_PX15_Pos (0U) 2026 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ 2027 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ 2028 2029 #define AFIO_EVCR_PORT_Pos (4U) 2030 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ 2031 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ 2032 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ 2033 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ 2034 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ 2035 2036 /*!< PORT configuration */ 2037 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ 2038 #define AFIO_EVCR_PORT_PB_Pos (4U) 2039 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ 2040 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ 2041 #define AFIO_EVCR_PORT_PC_Pos (5U) 2042 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ 2043 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ 2044 #define AFIO_EVCR_PORT_PD_Pos (4U) 2045 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ 2046 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ 2047 #define AFIO_EVCR_PORT_PE_Pos (6U) 2048 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ 2049 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ 2050 2051 #define AFIO_EVCR_EVOE_Pos (7U) 2052 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ 2053 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ 2054 2055 /****************** Bit definition for AFIO_MAPR register *******************/ 2056 #define AFIO_MAPR_SPI1_REMAP_Pos (0U) 2057 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ 2058 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ 2059 #define AFIO_MAPR_I2C1_REMAP_Pos (1U) 2060 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ 2061 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ 2062 #define AFIO_MAPR_USART1_REMAP_Pos (2U) 2063 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ 2064 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ 2065 #define AFIO_MAPR_USART2_REMAP_Pos (3U) 2066 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ 2067 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ 2068 2069 #define AFIO_MAPR_USART3_REMAP_Pos (4U) 2070 #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ 2071 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ 2072 #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ 2073 #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ 2074 2075 /* USART3_REMAP configuration */ 2076 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ 2077 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) 2078 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ 2079 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ 2080 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) 2081 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ 2082 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ 2083 2084 #define AFIO_MAPR_TIM1_REMAP_Pos (6U) 2085 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ 2086 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ 2087 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ 2088 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ 2089 2090 /*!< TIM1_REMAP configuration */ 2091 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ 2092 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) 2093 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ 2094 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ 2095 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) 2096 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ 2097 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ 2098 2099 #define AFIO_MAPR_TIM2_REMAP_Pos (8U) 2100 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ 2101 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ 2102 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ 2103 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ 2104 2105 /*!< TIM2_REMAP configuration */ 2106 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ 2107 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) 2108 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ 2109 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ 2110 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) 2111 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ 2112 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ 2113 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) 2114 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ 2115 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ 2116 2117 #define AFIO_MAPR_TIM3_REMAP_Pos (10U) 2118 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ 2119 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ 2120 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ 2121 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ 2122 2123 /*!< TIM3_REMAP configuration */ 2124 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ 2125 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) 2126 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ 2127 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ 2128 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) 2129 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ 2130 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ 2131 2132 #define AFIO_MAPR_TIM4_REMAP_Pos (12U) 2133 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ 2134 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ 2135 2136 2137 #define AFIO_MAPR_PD01_REMAP_Pos (15U) 2138 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ 2139 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ 2140 2141 /*!< SWJ_CFG configuration */ 2142 #define AFIO_MAPR_SWJ_CFG_Pos (24U) 2143 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ 2144 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ 2145 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ 2146 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ 2147 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ 2148 2149 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ 2150 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) 2151 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ 2152 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ 2153 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) 2154 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ 2155 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ 2156 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) 2157 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ 2158 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ 2159 2160 2161 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 2162 #define AFIO_EXTICR1_EXTI0_Pos (0U) 2163 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 2164 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 2165 #define AFIO_EXTICR1_EXTI1_Pos (4U) 2166 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 2167 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 2168 #define AFIO_EXTICR1_EXTI2_Pos (8U) 2169 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 2170 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 2171 #define AFIO_EXTICR1_EXTI3_Pos (12U) 2172 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 2173 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 2174 2175 /*!< EXTI0 configuration */ 2176 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ 2177 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) 2178 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ 2179 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ 2180 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) 2181 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ 2182 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ 2183 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) 2184 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ 2185 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ 2186 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) 2187 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ 2188 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ 2189 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) 2190 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ 2191 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ 2192 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) 2193 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ 2194 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ 2195 2196 /*!< EXTI1 configuration */ 2197 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ 2198 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) 2199 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ 2200 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ 2201 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) 2202 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ 2203 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ 2204 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) 2205 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ 2206 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ 2207 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) 2208 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ 2209 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ 2210 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) 2211 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ 2212 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ 2213 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) 2214 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ 2215 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ 2216 2217 /*!< EXTI2 configuration */ 2218 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ 2219 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) 2220 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ 2221 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ 2222 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) 2223 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ 2224 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ 2225 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) 2226 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ 2227 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ 2228 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) 2229 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ 2230 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ 2231 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) 2232 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ 2233 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ 2234 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) 2235 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ 2236 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ 2237 2238 /*!< EXTI3 configuration */ 2239 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ 2240 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) 2241 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ 2242 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ 2243 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) 2244 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ 2245 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ 2246 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) 2247 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ 2248 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ 2249 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) 2250 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ 2251 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ 2252 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) 2253 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ 2254 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ 2255 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) 2256 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ 2257 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ 2258 2259 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 2260 #define AFIO_EXTICR2_EXTI4_Pos (0U) 2261 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 2262 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 2263 #define AFIO_EXTICR2_EXTI5_Pos (4U) 2264 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 2265 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 2266 #define AFIO_EXTICR2_EXTI6_Pos (8U) 2267 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 2268 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 2269 #define AFIO_EXTICR2_EXTI7_Pos (12U) 2270 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 2271 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 2272 2273 /*!< EXTI4 configuration */ 2274 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ 2275 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) 2276 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ 2277 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ 2278 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) 2279 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ 2280 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ 2281 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) 2282 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ 2283 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ 2284 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) 2285 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ 2286 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ 2287 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) 2288 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ 2289 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ 2290 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) 2291 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ 2292 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ 2293 2294 /* EXTI5 configuration */ 2295 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ 2296 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) 2297 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ 2298 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ 2299 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) 2300 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ 2301 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ 2302 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) 2303 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ 2304 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ 2305 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) 2306 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ 2307 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ 2308 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) 2309 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ 2310 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ 2311 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) 2312 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ 2313 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ 2314 2315 /*!< EXTI6 configuration */ 2316 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ 2317 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) 2318 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ 2319 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ 2320 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) 2321 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ 2322 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ 2323 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) 2324 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ 2325 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ 2326 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) 2327 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ 2328 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ 2329 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) 2330 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ 2331 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ 2332 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) 2333 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ 2334 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ 2335 2336 /*!< EXTI7 configuration */ 2337 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ 2338 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) 2339 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ 2340 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ 2341 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) 2342 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ 2343 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ 2344 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) 2345 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ 2346 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ 2347 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) 2348 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ 2349 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ 2350 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) 2351 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ 2352 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ 2353 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) 2354 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ 2355 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ 2356 2357 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 2358 #define AFIO_EXTICR3_EXTI8_Pos (0U) 2359 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 2360 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 2361 #define AFIO_EXTICR3_EXTI9_Pos (4U) 2362 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 2363 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 2364 #define AFIO_EXTICR3_EXTI10_Pos (8U) 2365 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 2366 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 2367 #define AFIO_EXTICR3_EXTI11_Pos (12U) 2368 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 2369 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 2370 2371 /*!< EXTI8 configuration */ 2372 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ 2373 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) 2374 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ 2375 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ 2376 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) 2377 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ 2378 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ 2379 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) 2380 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ 2381 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ 2382 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) 2383 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ 2384 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ 2385 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) 2386 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ 2387 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ 2388 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) 2389 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ 2390 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ 2391 2392 /*!< EXTI9 configuration */ 2393 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ 2394 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) 2395 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ 2396 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ 2397 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) 2398 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ 2399 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ 2400 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) 2401 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ 2402 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ 2403 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) 2404 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ 2405 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ 2406 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) 2407 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ 2408 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ 2409 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) 2410 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ 2411 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ 2412 2413 /*!< EXTI10 configuration */ 2414 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ 2415 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) 2416 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ 2417 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ 2418 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) 2419 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ 2420 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ 2421 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) 2422 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ 2423 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ 2424 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) 2425 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ 2426 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ 2427 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) 2428 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ 2429 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ 2430 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) 2431 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ 2432 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ 2433 2434 /*!< EXTI11 configuration */ 2435 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ 2436 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) 2437 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ 2438 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ 2439 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) 2440 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ 2441 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ 2442 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) 2443 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ 2444 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ 2445 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) 2446 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ 2447 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ 2448 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) 2449 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ 2450 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ 2451 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) 2452 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ 2453 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ 2454 2455 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 2456 #define AFIO_EXTICR4_EXTI12_Pos (0U) 2457 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 2458 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 2459 #define AFIO_EXTICR4_EXTI13_Pos (4U) 2460 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 2461 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 2462 #define AFIO_EXTICR4_EXTI14_Pos (8U) 2463 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 2464 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 2465 #define AFIO_EXTICR4_EXTI15_Pos (12U) 2466 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 2467 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 2468 2469 /* EXTI12 configuration */ 2470 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ 2471 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) 2472 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ 2473 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ 2474 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) 2475 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ 2476 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ 2477 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) 2478 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ 2479 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ 2480 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) 2481 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ 2482 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ 2483 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) 2484 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ 2485 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ 2486 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) 2487 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ 2488 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ 2489 2490 /* EXTI13 configuration */ 2491 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ 2492 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) 2493 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ 2494 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ 2495 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) 2496 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ 2497 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ 2498 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) 2499 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ 2500 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ 2501 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) 2502 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ 2503 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ 2504 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) 2505 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ 2506 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ 2507 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) 2508 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ 2509 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ 2510 2511 /*!< EXTI14 configuration */ 2512 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ 2513 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) 2514 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ 2515 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ 2516 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) 2517 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ 2518 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ 2519 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) 2520 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ 2521 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ 2522 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) 2523 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ 2524 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ 2525 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) 2526 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ 2527 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ 2528 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) 2529 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ 2530 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ 2531 2532 /*!< EXTI15 configuration */ 2533 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ 2534 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) 2535 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ 2536 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ 2537 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) 2538 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ 2539 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ 2540 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) 2541 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ 2542 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ 2543 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) 2544 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ 2545 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ 2546 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) 2547 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ 2548 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ 2549 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) 2550 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ 2551 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ 2552 2553 /****************** Bit definition for AFIO_MAPR2 register ******************/ 2554 #define AFIO_MAPR2_TIM15_REMAP_Pos (0U) 2555 #define AFIO_MAPR2_TIM15_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM15_REMAP_Pos) /*!< 0x00000001 */ 2556 #define AFIO_MAPR2_TIM15_REMAP AFIO_MAPR2_TIM15_REMAP_Msk /*!< TIM15 remapping */ 2557 #define AFIO_MAPR2_TIM16_REMAP_Pos (1U) 2558 #define AFIO_MAPR2_TIM16_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM16_REMAP_Pos) /*!< 0x00000002 */ 2559 #define AFIO_MAPR2_TIM16_REMAP AFIO_MAPR2_TIM16_REMAP_Msk /*!< TIM16 remapping */ 2560 #define AFIO_MAPR2_TIM17_REMAP_Pos (2U) 2561 #define AFIO_MAPR2_TIM17_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM17_REMAP_Pos) /*!< 0x00000004 */ 2562 #define AFIO_MAPR2_TIM17_REMAP AFIO_MAPR2_TIM17_REMAP_Msk /*!< TIM17 remapping */ 2563 #define AFIO_MAPR2_CEC_REMAP_Pos (3U) 2564 #define AFIO_MAPR2_CEC_REMAP_Msk (0x1UL << AFIO_MAPR2_CEC_REMAP_Pos) /*!< 0x00000008 */ 2565 #define AFIO_MAPR2_CEC_REMAP AFIO_MAPR2_CEC_REMAP_Msk /*!< CEC remapping */ 2566 #define AFIO_MAPR2_TIM1_DMA_REMAP_Pos (4U) 2567 #define AFIO_MAPR2_TIM1_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM1_DMA_REMAP_Pos) /*!< 0x00000010 */ 2568 #define AFIO_MAPR2_TIM1_DMA_REMAP AFIO_MAPR2_TIM1_DMA_REMAP_Msk /*!< TIM1_DMA remapping */ 2569 2570 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos (11U) 2571 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk (0x1UL << AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Pos) /*!< 0x00000800 */ 2572 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */ 2573 2574 2575 /******************************************************************************/ 2576 /* */ 2577 /* External Interrupt/Event Controller */ 2578 /* */ 2579 /******************************************************************************/ 2580 2581 /******************* Bit definition for EXTI_IMR register *******************/ 2582 #define EXTI_IMR_MR0_Pos (0U) 2583 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 2584 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 2585 #define EXTI_IMR_MR1_Pos (1U) 2586 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 2587 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 2588 #define EXTI_IMR_MR2_Pos (2U) 2589 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 2590 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 2591 #define EXTI_IMR_MR3_Pos (3U) 2592 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 2593 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 2594 #define EXTI_IMR_MR4_Pos (4U) 2595 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 2596 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 2597 #define EXTI_IMR_MR5_Pos (5U) 2598 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 2599 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 2600 #define EXTI_IMR_MR6_Pos (6U) 2601 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 2602 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 2603 #define EXTI_IMR_MR7_Pos (7U) 2604 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 2605 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 2606 #define EXTI_IMR_MR8_Pos (8U) 2607 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 2608 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 2609 #define EXTI_IMR_MR9_Pos (9U) 2610 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 2611 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 2612 #define EXTI_IMR_MR10_Pos (10U) 2613 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 2614 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 2615 #define EXTI_IMR_MR11_Pos (11U) 2616 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 2617 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 2618 #define EXTI_IMR_MR12_Pos (12U) 2619 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 2620 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 2621 #define EXTI_IMR_MR13_Pos (13U) 2622 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 2623 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 2624 #define EXTI_IMR_MR14_Pos (14U) 2625 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 2626 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 2627 #define EXTI_IMR_MR15_Pos (15U) 2628 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 2629 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 2630 #define EXTI_IMR_MR16_Pos (16U) 2631 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 2632 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 2633 #define EXTI_IMR_MR17_Pos (17U) 2634 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 2635 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 2636 2637 /* References Defines */ 2638 #define EXTI_IMR_IM0 EXTI_IMR_MR0 2639 #define EXTI_IMR_IM1 EXTI_IMR_MR1 2640 #define EXTI_IMR_IM2 EXTI_IMR_MR2 2641 #define EXTI_IMR_IM3 EXTI_IMR_MR3 2642 #define EXTI_IMR_IM4 EXTI_IMR_MR4 2643 #define EXTI_IMR_IM5 EXTI_IMR_MR5 2644 #define EXTI_IMR_IM6 EXTI_IMR_MR6 2645 #define EXTI_IMR_IM7 EXTI_IMR_MR7 2646 #define EXTI_IMR_IM8 EXTI_IMR_MR8 2647 #define EXTI_IMR_IM9 EXTI_IMR_MR9 2648 #define EXTI_IMR_IM10 EXTI_IMR_MR10 2649 #define EXTI_IMR_IM11 EXTI_IMR_MR11 2650 #define EXTI_IMR_IM12 EXTI_IMR_MR12 2651 #define EXTI_IMR_IM13 EXTI_IMR_MR13 2652 #define EXTI_IMR_IM14 EXTI_IMR_MR14 2653 #define EXTI_IMR_IM15 EXTI_IMR_MR15 2654 #define EXTI_IMR_IM16 EXTI_IMR_MR16 2655 #define EXTI_IMR_IM17 EXTI_IMR_MR17 2656 #define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */ 2657 2658 /******************* Bit definition for EXTI_EMR register *******************/ 2659 #define EXTI_EMR_MR0_Pos (0U) 2660 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 2661 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 2662 #define EXTI_EMR_MR1_Pos (1U) 2663 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 2664 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 2665 #define EXTI_EMR_MR2_Pos (2U) 2666 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 2667 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 2668 #define EXTI_EMR_MR3_Pos (3U) 2669 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 2670 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 2671 #define EXTI_EMR_MR4_Pos (4U) 2672 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 2673 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 2674 #define EXTI_EMR_MR5_Pos (5U) 2675 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 2676 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 2677 #define EXTI_EMR_MR6_Pos (6U) 2678 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 2679 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 2680 #define EXTI_EMR_MR7_Pos (7U) 2681 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 2682 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 2683 #define EXTI_EMR_MR8_Pos (8U) 2684 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 2685 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 2686 #define EXTI_EMR_MR9_Pos (9U) 2687 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 2688 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 2689 #define EXTI_EMR_MR10_Pos (10U) 2690 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 2691 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 2692 #define EXTI_EMR_MR11_Pos (11U) 2693 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 2694 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 2695 #define EXTI_EMR_MR12_Pos (12U) 2696 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 2697 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 2698 #define EXTI_EMR_MR13_Pos (13U) 2699 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 2700 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 2701 #define EXTI_EMR_MR14_Pos (14U) 2702 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 2703 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 2704 #define EXTI_EMR_MR15_Pos (15U) 2705 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 2706 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 2707 #define EXTI_EMR_MR16_Pos (16U) 2708 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 2709 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 2710 #define EXTI_EMR_MR17_Pos (17U) 2711 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 2712 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 2713 2714 /* References Defines */ 2715 #define EXTI_EMR_EM0 EXTI_EMR_MR0 2716 #define EXTI_EMR_EM1 EXTI_EMR_MR1 2717 #define EXTI_EMR_EM2 EXTI_EMR_MR2 2718 #define EXTI_EMR_EM3 EXTI_EMR_MR3 2719 #define EXTI_EMR_EM4 EXTI_EMR_MR4 2720 #define EXTI_EMR_EM5 EXTI_EMR_MR5 2721 #define EXTI_EMR_EM6 EXTI_EMR_MR6 2722 #define EXTI_EMR_EM7 EXTI_EMR_MR7 2723 #define EXTI_EMR_EM8 EXTI_EMR_MR8 2724 #define EXTI_EMR_EM9 EXTI_EMR_MR9 2725 #define EXTI_EMR_EM10 EXTI_EMR_MR10 2726 #define EXTI_EMR_EM11 EXTI_EMR_MR11 2727 #define EXTI_EMR_EM12 EXTI_EMR_MR12 2728 #define EXTI_EMR_EM13 EXTI_EMR_MR13 2729 #define EXTI_EMR_EM14 EXTI_EMR_MR14 2730 #define EXTI_EMR_EM15 EXTI_EMR_MR15 2731 #define EXTI_EMR_EM16 EXTI_EMR_MR16 2732 #define EXTI_EMR_EM17 EXTI_EMR_MR17 2733 2734 /****************** Bit definition for EXTI_RTSR register *******************/ 2735 #define EXTI_RTSR_TR0_Pos (0U) 2736 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 2737 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 2738 #define EXTI_RTSR_TR1_Pos (1U) 2739 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 2740 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 2741 #define EXTI_RTSR_TR2_Pos (2U) 2742 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 2743 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 2744 #define EXTI_RTSR_TR3_Pos (3U) 2745 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 2746 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 2747 #define EXTI_RTSR_TR4_Pos (4U) 2748 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 2749 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 2750 #define EXTI_RTSR_TR5_Pos (5U) 2751 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 2752 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 2753 #define EXTI_RTSR_TR6_Pos (6U) 2754 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 2755 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 2756 #define EXTI_RTSR_TR7_Pos (7U) 2757 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 2758 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 2759 #define EXTI_RTSR_TR8_Pos (8U) 2760 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 2761 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 2762 #define EXTI_RTSR_TR9_Pos (9U) 2763 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 2764 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 2765 #define EXTI_RTSR_TR10_Pos (10U) 2766 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 2767 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 2768 #define EXTI_RTSR_TR11_Pos (11U) 2769 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 2770 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 2771 #define EXTI_RTSR_TR12_Pos (12U) 2772 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 2773 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 2774 #define EXTI_RTSR_TR13_Pos (13U) 2775 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 2776 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 2777 #define EXTI_RTSR_TR14_Pos (14U) 2778 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 2779 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 2780 #define EXTI_RTSR_TR15_Pos (15U) 2781 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 2782 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 2783 #define EXTI_RTSR_TR16_Pos (16U) 2784 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 2785 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 2786 #define EXTI_RTSR_TR17_Pos (17U) 2787 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 2788 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 2789 2790 /* References Defines */ 2791 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 2792 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 2793 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 2794 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 2795 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 2796 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 2797 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 2798 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 2799 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 2800 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 2801 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 2802 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 2803 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 2804 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 2805 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 2806 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 2807 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 2808 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 2809 2810 /****************** Bit definition for EXTI_FTSR register *******************/ 2811 #define EXTI_FTSR_TR0_Pos (0U) 2812 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 2813 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 2814 #define EXTI_FTSR_TR1_Pos (1U) 2815 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 2816 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 2817 #define EXTI_FTSR_TR2_Pos (2U) 2818 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 2819 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 2820 #define EXTI_FTSR_TR3_Pos (3U) 2821 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 2822 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 2823 #define EXTI_FTSR_TR4_Pos (4U) 2824 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 2825 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 2826 #define EXTI_FTSR_TR5_Pos (5U) 2827 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 2828 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 2829 #define EXTI_FTSR_TR6_Pos (6U) 2830 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 2831 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 2832 #define EXTI_FTSR_TR7_Pos (7U) 2833 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 2834 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 2835 #define EXTI_FTSR_TR8_Pos (8U) 2836 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 2837 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 2838 #define EXTI_FTSR_TR9_Pos (9U) 2839 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 2840 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 2841 #define EXTI_FTSR_TR10_Pos (10U) 2842 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 2843 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 2844 #define EXTI_FTSR_TR11_Pos (11U) 2845 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 2846 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 2847 #define EXTI_FTSR_TR12_Pos (12U) 2848 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 2849 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 2850 #define EXTI_FTSR_TR13_Pos (13U) 2851 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 2852 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 2853 #define EXTI_FTSR_TR14_Pos (14U) 2854 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 2855 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 2856 #define EXTI_FTSR_TR15_Pos (15U) 2857 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 2858 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 2859 #define EXTI_FTSR_TR16_Pos (16U) 2860 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 2861 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 2862 #define EXTI_FTSR_TR17_Pos (17U) 2863 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 2864 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 2865 2866 /* References Defines */ 2867 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 2868 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 2869 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 2870 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 2871 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 2872 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 2873 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 2874 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 2875 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 2876 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 2877 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 2878 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 2879 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 2880 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 2881 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 2882 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 2883 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 2884 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 2885 2886 /****************** Bit definition for EXTI_SWIER register ******************/ 2887 #define EXTI_SWIER_SWIER0_Pos (0U) 2888 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 2889 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 2890 #define EXTI_SWIER_SWIER1_Pos (1U) 2891 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 2892 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 2893 #define EXTI_SWIER_SWIER2_Pos (2U) 2894 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 2895 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 2896 #define EXTI_SWIER_SWIER3_Pos (3U) 2897 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 2898 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 2899 #define EXTI_SWIER_SWIER4_Pos (4U) 2900 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 2901 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 2902 #define EXTI_SWIER_SWIER5_Pos (5U) 2903 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 2904 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 2905 #define EXTI_SWIER_SWIER6_Pos (6U) 2906 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 2907 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 2908 #define EXTI_SWIER_SWIER7_Pos (7U) 2909 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 2910 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 2911 #define EXTI_SWIER_SWIER8_Pos (8U) 2912 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 2913 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 2914 #define EXTI_SWIER_SWIER9_Pos (9U) 2915 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 2916 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 2917 #define EXTI_SWIER_SWIER10_Pos (10U) 2918 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 2919 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 2920 #define EXTI_SWIER_SWIER11_Pos (11U) 2921 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 2922 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 2923 #define EXTI_SWIER_SWIER12_Pos (12U) 2924 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 2925 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 2926 #define EXTI_SWIER_SWIER13_Pos (13U) 2927 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 2928 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 2929 #define EXTI_SWIER_SWIER14_Pos (14U) 2930 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 2931 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 2932 #define EXTI_SWIER_SWIER15_Pos (15U) 2933 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 2934 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 2935 #define EXTI_SWIER_SWIER16_Pos (16U) 2936 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 2937 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 2938 #define EXTI_SWIER_SWIER17_Pos (17U) 2939 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 2940 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 2941 2942 /* References Defines */ 2943 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 2944 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 2945 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 2946 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 2947 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 2948 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 2949 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 2950 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 2951 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 2952 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 2953 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 2954 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 2955 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 2956 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 2957 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 2958 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 2959 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 2960 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 2961 2962 /******************* Bit definition for EXTI_PR register ********************/ 2963 #define EXTI_PR_PR0_Pos (0U) 2964 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 2965 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 2966 #define EXTI_PR_PR1_Pos (1U) 2967 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 2968 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 2969 #define EXTI_PR_PR2_Pos (2U) 2970 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 2971 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 2972 #define EXTI_PR_PR3_Pos (3U) 2973 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 2974 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 2975 #define EXTI_PR_PR4_Pos (4U) 2976 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 2977 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 2978 #define EXTI_PR_PR5_Pos (5U) 2979 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 2980 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 2981 #define EXTI_PR_PR6_Pos (6U) 2982 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 2983 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 2984 #define EXTI_PR_PR7_Pos (7U) 2985 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 2986 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 2987 #define EXTI_PR_PR8_Pos (8U) 2988 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 2989 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 2990 #define EXTI_PR_PR9_Pos (9U) 2991 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 2992 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 2993 #define EXTI_PR_PR10_Pos (10U) 2994 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 2995 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 2996 #define EXTI_PR_PR11_Pos (11U) 2997 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 2998 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 2999 #define EXTI_PR_PR12_Pos (12U) 3000 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 3001 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 3002 #define EXTI_PR_PR13_Pos (13U) 3003 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 3004 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 3005 #define EXTI_PR_PR14_Pos (14U) 3006 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 3007 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 3008 #define EXTI_PR_PR15_Pos (15U) 3009 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 3010 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 3011 #define EXTI_PR_PR16_Pos (16U) 3012 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 3013 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 3014 #define EXTI_PR_PR17_Pos (17U) 3015 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 3016 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 3017 3018 /* References Defines */ 3019 #define EXTI_PR_PIF0 EXTI_PR_PR0 3020 #define EXTI_PR_PIF1 EXTI_PR_PR1 3021 #define EXTI_PR_PIF2 EXTI_PR_PR2 3022 #define EXTI_PR_PIF3 EXTI_PR_PR3 3023 #define EXTI_PR_PIF4 EXTI_PR_PR4 3024 #define EXTI_PR_PIF5 EXTI_PR_PR5 3025 #define EXTI_PR_PIF6 EXTI_PR_PR6 3026 #define EXTI_PR_PIF7 EXTI_PR_PR7 3027 #define EXTI_PR_PIF8 EXTI_PR_PR8 3028 #define EXTI_PR_PIF9 EXTI_PR_PR9 3029 #define EXTI_PR_PIF10 EXTI_PR_PR10 3030 #define EXTI_PR_PIF11 EXTI_PR_PR11 3031 #define EXTI_PR_PIF12 EXTI_PR_PR12 3032 #define EXTI_PR_PIF13 EXTI_PR_PR13 3033 #define EXTI_PR_PIF14 EXTI_PR_PR14 3034 #define EXTI_PR_PIF15 EXTI_PR_PR15 3035 #define EXTI_PR_PIF16 EXTI_PR_PR16 3036 #define EXTI_PR_PIF17 EXTI_PR_PR17 3037 3038 /******************************************************************************/ 3039 /* */ 3040 /* DMA Controller */ 3041 /* */ 3042 /******************************************************************************/ 3043 3044 /******************* Bit definition for DMA_ISR register ********************/ 3045 #define DMA_ISR_GIF1_Pos (0U) 3046 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 3047 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 3048 #define DMA_ISR_TCIF1_Pos (1U) 3049 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 3050 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 3051 #define DMA_ISR_HTIF1_Pos (2U) 3052 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 3053 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 3054 #define DMA_ISR_TEIF1_Pos (3U) 3055 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 3056 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 3057 #define DMA_ISR_GIF2_Pos (4U) 3058 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 3059 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 3060 #define DMA_ISR_TCIF2_Pos (5U) 3061 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 3062 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 3063 #define DMA_ISR_HTIF2_Pos (6U) 3064 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 3065 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 3066 #define DMA_ISR_TEIF2_Pos (7U) 3067 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 3068 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 3069 #define DMA_ISR_GIF3_Pos (8U) 3070 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 3071 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 3072 #define DMA_ISR_TCIF3_Pos (9U) 3073 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 3074 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 3075 #define DMA_ISR_HTIF3_Pos (10U) 3076 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 3077 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 3078 #define DMA_ISR_TEIF3_Pos (11U) 3079 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 3080 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 3081 #define DMA_ISR_GIF4_Pos (12U) 3082 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 3083 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 3084 #define DMA_ISR_TCIF4_Pos (13U) 3085 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 3086 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 3087 #define DMA_ISR_HTIF4_Pos (14U) 3088 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 3089 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 3090 #define DMA_ISR_TEIF4_Pos (15U) 3091 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 3092 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 3093 #define DMA_ISR_GIF5_Pos (16U) 3094 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 3095 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 3096 #define DMA_ISR_TCIF5_Pos (17U) 3097 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 3098 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 3099 #define DMA_ISR_HTIF5_Pos (18U) 3100 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 3101 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 3102 #define DMA_ISR_TEIF5_Pos (19U) 3103 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 3104 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 3105 #define DMA_ISR_GIF6_Pos (20U) 3106 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 3107 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 3108 #define DMA_ISR_TCIF6_Pos (21U) 3109 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 3110 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 3111 #define DMA_ISR_HTIF6_Pos (22U) 3112 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 3113 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 3114 #define DMA_ISR_TEIF6_Pos (23U) 3115 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 3116 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 3117 #define DMA_ISR_GIF7_Pos (24U) 3118 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 3119 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 3120 #define DMA_ISR_TCIF7_Pos (25U) 3121 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 3122 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 3123 #define DMA_ISR_HTIF7_Pos (26U) 3124 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 3125 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 3126 #define DMA_ISR_TEIF7_Pos (27U) 3127 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 3128 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 3129 3130 /******************* Bit definition for DMA_IFCR register *******************/ 3131 #define DMA_IFCR_CGIF1_Pos (0U) 3132 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 3133 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 3134 #define DMA_IFCR_CTCIF1_Pos (1U) 3135 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 3136 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 3137 #define DMA_IFCR_CHTIF1_Pos (2U) 3138 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 3139 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 3140 #define DMA_IFCR_CTEIF1_Pos (3U) 3141 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 3142 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 3143 #define DMA_IFCR_CGIF2_Pos (4U) 3144 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 3145 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 3146 #define DMA_IFCR_CTCIF2_Pos (5U) 3147 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 3148 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 3149 #define DMA_IFCR_CHTIF2_Pos (6U) 3150 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 3151 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 3152 #define DMA_IFCR_CTEIF2_Pos (7U) 3153 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 3154 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 3155 #define DMA_IFCR_CGIF3_Pos (8U) 3156 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 3157 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 3158 #define DMA_IFCR_CTCIF3_Pos (9U) 3159 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 3160 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 3161 #define DMA_IFCR_CHTIF3_Pos (10U) 3162 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 3163 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 3164 #define DMA_IFCR_CTEIF3_Pos (11U) 3165 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 3166 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 3167 #define DMA_IFCR_CGIF4_Pos (12U) 3168 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 3169 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 3170 #define DMA_IFCR_CTCIF4_Pos (13U) 3171 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 3172 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 3173 #define DMA_IFCR_CHTIF4_Pos (14U) 3174 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 3175 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 3176 #define DMA_IFCR_CTEIF4_Pos (15U) 3177 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 3178 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 3179 #define DMA_IFCR_CGIF5_Pos (16U) 3180 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 3181 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 3182 #define DMA_IFCR_CTCIF5_Pos (17U) 3183 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 3184 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 3185 #define DMA_IFCR_CHTIF5_Pos (18U) 3186 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 3187 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 3188 #define DMA_IFCR_CTEIF5_Pos (19U) 3189 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 3190 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 3191 #define DMA_IFCR_CGIF6_Pos (20U) 3192 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 3193 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 3194 #define DMA_IFCR_CTCIF6_Pos (21U) 3195 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 3196 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 3197 #define DMA_IFCR_CHTIF6_Pos (22U) 3198 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 3199 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 3200 #define DMA_IFCR_CTEIF6_Pos (23U) 3201 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 3202 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 3203 #define DMA_IFCR_CGIF7_Pos (24U) 3204 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 3205 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 3206 #define DMA_IFCR_CTCIF7_Pos (25U) 3207 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 3208 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 3209 #define DMA_IFCR_CHTIF7_Pos (26U) 3210 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 3211 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 3212 #define DMA_IFCR_CTEIF7_Pos (27U) 3213 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 3214 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 3215 3216 /******************* Bit definition for DMA_CCR register *******************/ 3217 #define DMA_CCR_EN_Pos (0U) 3218 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 3219 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 3220 #define DMA_CCR_TCIE_Pos (1U) 3221 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 3222 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 3223 #define DMA_CCR_HTIE_Pos (2U) 3224 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 3225 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 3226 #define DMA_CCR_TEIE_Pos (3U) 3227 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 3228 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 3229 #define DMA_CCR_DIR_Pos (4U) 3230 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 3231 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 3232 #define DMA_CCR_CIRC_Pos (5U) 3233 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 3234 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 3235 #define DMA_CCR_PINC_Pos (6U) 3236 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 3237 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 3238 #define DMA_CCR_MINC_Pos (7U) 3239 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 3240 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 3241 3242 #define DMA_CCR_PSIZE_Pos (8U) 3243 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 3244 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 3245 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 3246 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 3247 3248 #define DMA_CCR_MSIZE_Pos (10U) 3249 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 3250 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 3251 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 3252 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 3253 3254 #define DMA_CCR_PL_Pos (12U) 3255 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 3256 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 3257 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 3258 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 3259 3260 #define DMA_CCR_MEM2MEM_Pos (14U) 3261 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 3262 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 3263 3264 /****************** Bit definition for DMA_CNDTR register ******************/ 3265 #define DMA_CNDTR_NDT_Pos (0U) 3266 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 3267 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 3268 3269 /****************** Bit definition for DMA_CPAR register *******************/ 3270 #define DMA_CPAR_PA_Pos (0U) 3271 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 3272 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 3273 3274 /****************** Bit definition for DMA_CMAR register *******************/ 3275 #define DMA_CMAR_MA_Pos (0U) 3276 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 3277 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 3278 3279 /******************************************************************************/ 3280 /* */ 3281 /* Analog to Digital Converter (ADC) */ 3282 /* */ 3283 /******************************************************************************/ 3284 3285 /* 3286 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) 3287 */ 3288 /* Note: No specific macro feature on this device */ 3289 3290 /******************** Bit definition for ADC_SR register ********************/ 3291 #define ADC_SR_AWD_Pos (0U) 3292 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 3293 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 3294 #define ADC_SR_EOS_Pos (1U) 3295 #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ 3296 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 3297 #define ADC_SR_JEOS_Pos (2U) 3298 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 3299 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 3300 #define ADC_SR_JSTRT_Pos (3U) 3301 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 3302 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 3303 #define ADC_SR_STRT_Pos (4U) 3304 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 3305 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 3306 3307 /* Legacy defines */ 3308 #define ADC_SR_EOC (ADC_SR_EOS) 3309 #define ADC_SR_JEOC (ADC_SR_JEOS) 3310 3311 /******************* Bit definition for ADC_CR1 register ********************/ 3312 #define ADC_CR1_AWDCH_Pos (0U) 3313 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 3314 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 3315 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 3316 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 3317 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 3318 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 3319 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 3320 3321 #define ADC_CR1_EOSIE_Pos (5U) 3322 #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ 3323 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 3324 #define ADC_CR1_AWDIE_Pos (6U) 3325 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 3326 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 3327 #define ADC_CR1_JEOSIE_Pos (7U) 3328 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 3329 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 3330 #define ADC_CR1_SCAN_Pos (8U) 3331 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 3332 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 3333 #define ADC_CR1_AWDSGL_Pos (9U) 3334 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 3335 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 3336 #define ADC_CR1_JAUTO_Pos (10U) 3337 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 3338 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 3339 #define ADC_CR1_DISCEN_Pos (11U) 3340 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 3341 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 3342 #define ADC_CR1_JDISCEN_Pos (12U) 3343 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 3344 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 3345 3346 #define ADC_CR1_DISCNUM_Pos (13U) 3347 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 3348 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 3349 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 3350 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 3351 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 3352 3353 #define ADC_CR1_JAWDEN_Pos (22U) 3354 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 3355 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 3356 #define ADC_CR1_AWDEN_Pos (23U) 3357 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 3358 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 3359 3360 /* Legacy defines */ 3361 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) 3362 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 3363 3364 /******************* Bit definition for ADC_CR2 register ********************/ 3365 #define ADC_CR2_ADON_Pos (0U) 3366 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 3367 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 3368 #define ADC_CR2_CONT_Pos (1U) 3369 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 3370 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 3371 #define ADC_CR2_CAL_Pos (2U) 3372 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ 3373 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ 3374 #define ADC_CR2_RSTCAL_Pos (3U) 3375 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ 3376 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ 3377 #define ADC_CR2_DMA_Pos (8U) 3378 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 3379 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 3380 #define ADC_CR2_ALIGN_Pos (11U) 3381 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 3382 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */ 3383 3384 #define ADC_CR2_JEXTSEL_Pos (12U) 3385 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ 3386 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 3387 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ 3388 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ 3389 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ 3390 3391 #define ADC_CR2_JEXTTRIG_Pos (15U) 3392 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ 3393 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ 3394 3395 #define ADC_CR2_EXTSEL_Pos (17U) 3396 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ 3397 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 3398 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ 3399 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ 3400 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ 3401 3402 #define ADC_CR2_EXTTRIG_Pos (20U) 3403 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ 3404 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ 3405 #define ADC_CR2_JSWSTART_Pos (21U) 3406 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ 3407 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 3408 #define ADC_CR2_SWSTART_Pos (22U) 3409 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ 3410 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 3411 #define ADC_CR2_TSVREFE_Pos (23U) 3412 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ 3413 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 3414 3415 /****************** Bit definition for ADC_SMPR1 register *******************/ 3416 #define ADC_SMPR1_SMP10_Pos (0U) 3417 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ 3418 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 3419 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ 3420 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ 3421 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ 3422 3423 #define ADC_SMPR1_SMP11_Pos (3U) 3424 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ 3425 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 3426 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ 3427 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ 3428 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ 3429 3430 #define ADC_SMPR1_SMP12_Pos (6U) 3431 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ 3432 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 3433 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ 3434 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ 3435 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ 3436 3437 #define ADC_SMPR1_SMP13_Pos (9U) 3438 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ 3439 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 3440 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ 3441 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ 3442 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ 3443 3444 #define ADC_SMPR1_SMP14_Pos (12U) 3445 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ 3446 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 3447 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ 3448 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ 3449 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ 3450 3451 #define ADC_SMPR1_SMP15_Pos (15U) 3452 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ 3453 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 3454 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ 3455 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ 3456 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ 3457 3458 #define ADC_SMPR1_SMP16_Pos (18U) 3459 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ 3460 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 3461 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ 3462 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ 3463 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ 3464 3465 #define ADC_SMPR1_SMP17_Pos (21U) 3466 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ 3467 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 3468 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ 3469 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ 3470 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ 3471 3472 /****************** Bit definition for ADC_SMPR2 register *******************/ 3473 #define ADC_SMPR2_SMP0_Pos (0U) 3474 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ 3475 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 3476 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ 3477 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ 3478 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ 3479 3480 #define ADC_SMPR2_SMP1_Pos (3U) 3481 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ 3482 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 3483 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ 3484 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ 3485 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ 3486 3487 #define ADC_SMPR2_SMP2_Pos (6U) 3488 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ 3489 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 3490 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ 3491 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ 3492 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ 3493 3494 #define ADC_SMPR2_SMP3_Pos (9U) 3495 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ 3496 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 3497 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ 3498 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ 3499 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ 3500 3501 #define ADC_SMPR2_SMP4_Pos (12U) 3502 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ 3503 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 3504 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ 3505 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ 3506 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ 3507 3508 #define ADC_SMPR2_SMP5_Pos (15U) 3509 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ 3510 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 3511 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ 3512 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ 3513 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ 3514 3515 #define ADC_SMPR2_SMP6_Pos (18U) 3516 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ 3517 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 3518 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ 3519 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ 3520 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ 3521 3522 #define ADC_SMPR2_SMP7_Pos (21U) 3523 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ 3524 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 3525 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ 3526 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ 3527 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ 3528 3529 #define ADC_SMPR2_SMP8_Pos (24U) 3530 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ 3531 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 3532 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ 3533 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ 3534 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ 3535 3536 #define ADC_SMPR2_SMP9_Pos (27U) 3537 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ 3538 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 3539 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ 3540 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ 3541 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ 3542 3543 /****************** Bit definition for ADC_JOFR1 register *******************/ 3544 #define ADC_JOFR1_JOFFSET1_Pos (0U) 3545 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 3546 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 3547 3548 /****************** Bit definition for ADC_JOFR2 register *******************/ 3549 #define ADC_JOFR2_JOFFSET2_Pos (0U) 3550 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 3551 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 3552 3553 /****************** Bit definition for ADC_JOFR3 register *******************/ 3554 #define ADC_JOFR3_JOFFSET3_Pos (0U) 3555 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 3556 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 3557 3558 /****************** Bit definition for ADC_JOFR4 register *******************/ 3559 #define ADC_JOFR4_JOFFSET4_Pos (0U) 3560 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 3561 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 3562 3563 /******************* Bit definition for ADC_HTR register ********************/ 3564 #define ADC_HTR_HT_Pos (0U) 3565 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 3566 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 3567 3568 /******************* Bit definition for ADC_LTR register ********************/ 3569 #define ADC_LTR_LT_Pos (0U) 3570 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 3571 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 3572 3573 /******************* Bit definition for ADC_SQR1 register *******************/ 3574 #define ADC_SQR1_SQ13_Pos (0U) 3575 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ 3576 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 3577 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ 3578 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ 3579 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ 3580 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ 3581 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ 3582 3583 #define ADC_SQR1_SQ14_Pos (5U) 3584 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ 3585 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 3586 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ 3587 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ 3588 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ 3589 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ 3590 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ 3591 3592 #define ADC_SQR1_SQ15_Pos (10U) 3593 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ 3594 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 3595 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ 3596 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ 3597 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ 3598 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ 3599 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ 3600 3601 #define ADC_SQR1_SQ16_Pos (15U) 3602 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ 3603 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 3604 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ 3605 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ 3606 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ 3607 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ 3608 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ 3609 3610 #define ADC_SQR1_L_Pos (20U) 3611 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ 3612 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 3613 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 3614 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 3615 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 3616 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 3617 3618 /******************* Bit definition for ADC_SQR2 register *******************/ 3619 #define ADC_SQR2_SQ7_Pos (0U) 3620 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ 3621 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 3622 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ 3623 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ 3624 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ 3625 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ 3626 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ 3627 3628 #define ADC_SQR2_SQ8_Pos (5U) 3629 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ 3630 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 3631 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ 3632 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ 3633 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ 3634 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ 3635 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ 3636 3637 #define ADC_SQR2_SQ9_Pos (10U) 3638 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ 3639 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 3640 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ 3641 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ 3642 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ 3643 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ 3644 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ 3645 3646 #define ADC_SQR2_SQ10_Pos (15U) 3647 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ 3648 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 3649 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ 3650 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ 3651 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ 3652 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ 3653 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ 3654 3655 #define ADC_SQR2_SQ11_Pos (20U) 3656 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ 3657 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ 3658 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ 3659 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ 3660 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ 3661 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ 3662 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ 3663 3664 #define ADC_SQR2_SQ12_Pos (25U) 3665 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ 3666 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 3667 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ 3668 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ 3669 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ 3670 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ 3671 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ 3672 3673 /******************* Bit definition for ADC_SQR3 register *******************/ 3674 #define ADC_SQR3_SQ1_Pos (0U) 3675 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ 3676 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 3677 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ 3678 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ 3679 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ 3680 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ 3681 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ 3682 3683 #define ADC_SQR3_SQ2_Pos (5U) 3684 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ 3685 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 3686 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ 3687 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ 3688 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ 3689 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ 3690 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ 3691 3692 #define ADC_SQR3_SQ3_Pos (10U) 3693 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ 3694 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 3695 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ 3696 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ 3697 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ 3698 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ 3699 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ 3700 3701 #define ADC_SQR3_SQ4_Pos (15U) 3702 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ 3703 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 3704 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ 3705 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ 3706 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ 3707 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ 3708 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ 3709 3710 #define ADC_SQR3_SQ5_Pos (20U) 3711 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ 3712 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 3713 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ 3714 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ 3715 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ 3716 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ 3717 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ 3718 3719 #define ADC_SQR3_SQ6_Pos (25U) 3720 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ 3721 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 3722 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ 3723 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ 3724 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ 3725 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ 3726 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ 3727 3728 /******************* Bit definition for ADC_JSQR register *******************/ 3729 #define ADC_JSQR_JSQ1_Pos (0U) 3730 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 3731 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 3732 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 3733 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 3734 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 3735 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 3736 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 3737 3738 #define ADC_JSQR_JSQ2_Pos (5U) 3739 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 3740 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 3741 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 3742 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 3743 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 3744 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 3745 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 3746 3747 #define ADC_JSQR_JSQ3_Pos (10U) 3748 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 3749 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 3750 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 3751 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 3752 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 3753 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 3754 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 3755 3756 #define ADC_JSQR_JSQ4_Pos (15U) 3757 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 3758 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 3759 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 3760 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 3761 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 3762 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 3763 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 3764 3765 #define ADC_JSQR_JL_Pos (20U) 3766 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 3767 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 3768 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 3769 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 3770 3771 /******************* Bit definition for ADC_JDR1 register *******************/ 3772 #define ADC_JDR1_JDATA_Pos (0U) 3773 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 3774 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 3775 3776 /******************* Bit definition for ADC_JDR2 register *******************/ 3777 #define ADC_JDR2_JDATA_Pos (0U) 3778 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 3779 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 3780 3781 /******************* Bit definition for ADC_JDR3 register *******************/ 3782 #define ADC_JDR3_JDATA_Pos (0U) 3783 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 3784 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 3785 3786 /******************* Bit definition for ADC_JDR4 register *******************/ 3787 #define ADC_JDR4_JDATA_Pos (0U) 3788 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 3789 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 3790 3791 /******************** Bit definition for ADC_DR register ********************/ 3792 #define ADC_DR_DATA_Pos (0U) 3793 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 3794 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 3795 /******************************************************************************/ 3796 /* */ 3797 /* Digital to Analog Converter */ 3798 /* */ 3799 /******************************************************************************/ 3800 3801 /******************** Bit definition for DAC_CR register ********************/ 3802 #define DAC_CR_EN1_Pos (0U) 3803 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ 3804 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ 3805 #define DAC_CR_BOFF1_Pos (1U) 3806 #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ 3807 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ 3808 #define DAC_CR_TEN1_Pos (2U) 3809 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ 3810 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ 3811 3812 #define DAC_CR_TSEL1_Pos (3U) 3813 #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ 3814 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 3815 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ 3816 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ 3817 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ 3818 3819 #define DAC_CR_WAVE1_Pos (6U) 3820 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ 3821 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ 3822 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ 3823 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ 3824 3825 #define DAC_CR_MAMP1_Pos (8U) 3826 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ 3827 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ 3828 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ 3829 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ 3830 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ 3831 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ 3832 3833 #define DAC_CR_DMAEN1_Pos (12U) 3834 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ 3835 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ 3836 #define DAC_CR_EN2_Pos (16U) 3837 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ 3838 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ 3839 #define DAC_CR_BOFF2_Pos (17U) 3840 #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ 3841 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ 3842 #define DAC_CR_TEN2_Pos (18U) 3843 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ 3844 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ 3845 3846 #define DAC_CR_TSEL2_Pos (19U) 3847 #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ 3848 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ 3849 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ 3850 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ 3851 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ 3852 3853 #define DAC_CR_WAVE2_Pos (22U) 3854 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ 3855 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 3856 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ 3857 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ 3858 3859 #define DAC_CR_MAMP2_Pos (24U) 3860 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ 3861 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 3862 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ 3863 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ 3864 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ 3865 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ 3866 3867 #define DAC_CR_DMAEN2_Pos (28U) 3868 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ 3869 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ 3870 3871 #define DAC_CR_DMAUDRIE1_Pos (13U) 3872 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ 3873 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< DAC channel1 DMA underrun interrupt enable */ 3874 #define DAC_CR_DMAUDRIE2_Pos (29U) 3875 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ 3876 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< DAC channel2 DMA underrun interrupt enable */ 3877 3878 /***************** Bit definition for DAC_SWTRIGR register ******************/ 3879 #define DAC_SWTRIGR_SWTRIG1_Pos (0U) 3880 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ 3881 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ 3882 #define DAC_SWTRIGR_SWTRIG2_Pos (1U) 3883 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ 3884 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ 3885 3886 /***************** Bit definition for DAC_DHR12R1 register ******************/ 3887 #define DAC_DHR12R1_DACC1DHR_Pos (0U) 3888 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ 3889 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 3890 3891 /***************** Bit definition for DAC_DHR12L1 register ******************/ 3892 #define DAC_DHR12L1_DACC1DHR_Pos (4U) 3893 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 3894 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 3895 3896 /****************** Bit definition for DAC_DHR8R1 register ******************/ 3897 #define DAC_DHR8R1_DACC1DHR_Pos (0U) 3898 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ 3899 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 3900 3901 /***************** Bit definition for DAC_DHR12R2 register ******************/ 3902 #define DAC_DHR12R2_DACC2DHR_Pos (0U) 3903 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ 3904 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 3905 3906 /***************** Bit definition for DAC_DHR12L2 register ******************/ 3907 #define DAC_DHR12L2_DACC2DHR_Pos (4U) 3908 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ 3909 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 3910 3911 /****************** Bit definition for DAC_DHR8R2 register ******************/ 3912 #define DAC_DHR8R2_DACC2DHR_Pos (0U) 3913 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ 3914 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 3915 3916 /***************** Bit definition for DAC_DHR12RD register ******************/ 3917 #define DAC_DHR12RD_DACC1DHR_Pos (0U) 3918 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ 3919 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ 3920 #define DAC_DHR12RD_DACC2DHR_Pos (16U) 3921 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ 3922 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ 3923 3924 /***************** Bit definition for DAC_DHR12LD register ******************/ 3925 #define DAC_DHR12LD_DACC1DHR_Pos (4U) 3926 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ 3927 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ 3928 #define DAC_DHR12LD_DACC2DHR_Pos (20U) 3929 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ 3930 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ 3931 3932 /****************** Bit definition for DAC_DHR8RD register ******************/ 3933 #define DAC_DHR8RD_DACC1DHR_Pos (0U) 3934 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ 3935 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ 3936 #define DAC_DHR8RD_DACC2DHR_Pos (8U) 3937 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ 3938 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ 3939 3940 /******************* Bit definition for DAC_DOR1 register *******************/ 3941 #define DAC_DOR1_DACC1DOR_Pos (0U) 3942 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ 3943 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ 3944 3945 /******************* Bit definition for DAC_DOR2 register *******************/ 3946 #define DAC_DOR2_DACC2DOR_Pos (0U) 3947 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ 3948 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ 3949 3950 /******************** Bit definition for DAC_SR register ********************/ 3951 #define DAC_SR_DMAUDR1_Pos (13U) 3952 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ 3953 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< DAC channel1 DMA underrun flag */ 3954 #define DAC_SR_DMAUDR2_Pos (29U) 3955 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ 3956 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< DAC channel2 DMA underrun flag */ 3957 3958 /******************************************************************************/ 3959 /* */ 3960 /* CEC */ 3961 /* */ 3962 /******************************************************************************/ 3963 /******************** Bit definition for CEC_CFGR register ******************/ 3964 #define CEC_CFGR_PE_Pos (0U) 3965 #define CEC_CFGR_PE_Msk (0x1UL << CEC_CFGR_PE_Pos) /*!< 0x00000001 */ 3966 #define CEC_CFGR_PE CEC_CFGR_PE_Msk /*!< Peripheral Enable */ 3967 #define CEC_CFGR_IE_Pos (1U) 3968 #define CEC_CFGR_IE_Msk (0x1UL << CEC_CFGR_IE_Pos) /*!< 0x00000002 */ 3969 #define CEC_CFGR_IE CEC_CFGR_IE_Msk /*!< Interrupt Enable */ 3970 #define CEC_CFGR_BTEM_Pos (2U) 3971 #define CEC_CFGR_BTEM_Msk (0x1UL << CEC_CFGR_BTEM_Pos) /*!< 0x00000004 */ 3972 #define CEC_CFGR_BTEM CEC_CFGR_BTEM_Msk /*!< Bit Timing Error Mode */ 3973 #define CEC_CFGR_BPEM_Pos (3U) 3974 #define CEC_CFGR_BPEM_Msk (0x1UL << CEC_CFGR_BPEM_Pos) /*!< 0x00000008 */ 3975 #define CEC_CFGR_BPEM CEC_CFGR_BPEM_Msk /*!< Bit Period Error Mode */ 3976 3977 /******************** Bit definition for CEC_OAR register ******************/ 3978 #define CEC_OAR_OA_Pos (0U) 3979 #define CEC_OAR_OA_Msk (0xFUL << CEC_OAR_OA_Pos) /*!< 0x0000000F */ 3980 #define CEC_OAR_OA CEC_OAR_OA_Msk /*!< OA[3:0]: Own Address */ 3981 #define CEC_OAR_OA_0 (0x1UL << CEC_OAR_OA_Pos) /*!< 0x00000001 */ 3982 #define CEC_OAR_OA_1 (0x2UL << CEC_OAR_OA_Pos) /*!< 0x00000002 */ 3983 #define CEC_OAR_OA_2 (0x4UL << CEC_OAR_OA_Pos) /*!< 0x00000004 */ 3984 #define CEC_OAR_OA_3 (0x8UL << CEC_OAR_OA_Pos) /*!< 0x00000008 */ 3985 3986 /******************** Bit definition for CEC_PRES register ******************/ 3987 #define CEC_PRES_PRES_Pos (0U) 3988 #define CEC_PRES_PRES_Msk (0x3FFFUL << CEC_PRES_PRES_Pos) /*!< 0x00003FFF */ 3989 #define CEC_PRES_PRES CEC_PRES_PRES_Msk /*!< Prescaler Counter Value */ 3990 3991 /******************** Bit definition for CEC_ESR register ******************/ 3992 #define CEC_ESR_BTE_Pos (0U) 3993 #define CEC_ESR_BTE_Msk (0x1UL << CEC_ESR_BTE_Pos) /*!< 0x00000001 */ 3994 #define CEC_ESR_BTE CEC_ESR_BTE_Msk /*!< Bit Timing Error */ 3995 #define CEC_ESR_BPE_Pos (1U) 3996 #define CEC_ESR_BPE_Msk (0x1UL << CEC_ESR_BPE_Pos) /*!< 0x00000002 */ 3997 #define CEC_ESR_BPE CEC_ESR_BPE_Msk /*!< Bit Period Error */ 3998 #define CEC_ESR_RBTFE_Pos (2U) 3999 #define CEC_ESR_RBTFE_Msk (0x1UL << CEC_ESR_RBTFE_Pos) /*!< 0x00000004 */ 4000 #define CEC_ESR_RBTFE CEC_ESR_RBTFE_Msk /*!< Rx Block Transfer Finished Error */ 4001 #define CEC_ESR_SBE_Pos (3U) 4002 #define CEC_ESR_SBE_Msk (0x1UL << CEC_ESR_SBE_Pos) /*!< 0x00000008 */ 4003 #define CEC_ESR_SBE CEC_ESR_SBE_Msk /*!< Start Bit Error */ 4004 #define CEC_ESR_ACKE_Pos (4U) 4005 #define CEC_ESR_ACKE_Msk (0x1UL << CEC_ESR_ACKE_Pos) /*!< 0x00000010 */ 4006 #define CEC_ESR_ACKE CEC_ESR_ACKE_Msk /*!< Block Acknowledge Error */ 4007 #define CEC_ESR_LINE_Pos (5U) 4008 #define CEC_ESR_LINE_Msk (0x1UL << CEC_ESR_LINE_Pos) /*!< 0x00000020 */ 4009 #define CEC_ESR_LINE CEC_ESR_LINE_Msk /*!< Line Error */ 4010 #define CEC_ESR_TBTFE_Pos (6U) 4011 #define CEC_ESR_TBTFE_Msk (0x1UL << CEC_ESR_TBTFE_Pos) /*!< 0x00000040 */ 4012 #define CEC_ESR_TBTFE CEC_ESR_TBTFE_Msk /*!< Tx Block Transfer Finished Error */ 4013 4014 /******************** Bit definition for CEC_CSR register ******************/ 4015 #define CEC_CSR_TSOM_Pos (0U) 4016 #define CEC_CSR_TSOM_Msk (0x1UL << CEC_CSR_TSOM_Pos) /*!< 0x00000001 */ 4017 #define CEC_CSR_TSOM CEC_CSR_TSOM_Msk /*!< Tx Start Of Message */ 4018 #define CEC_CSR_TEOM_Pos (1U) 4019 #define CEC_CSR_TEOM_Msk (0x1UL << CEC_CSR_TEOM_Pos) /*!< 0x00000002 */ 4020 #define CEC_CSR_TEOM CEC_CSR_TEOM_Msk /*!< Tx End Of Message */ 4021 #define CEC_CSR_TERR_Pos (2U) 4022 #define CEC_CSR_TERR_Msk (0x1UL << CEC_CSR_TERR_Pos) /*!< 0x00000004 */ 4023 #define CEC_CSR_TERR CEC_CSR_TERR_Msk /*!< Tx Error */ 4024 #define CEC_CSR_TBTRF_Pos (3U) 4025 #define CEC_CSR_TBTRF_Msk (0x1UL << CEC_CSR_TBTRF_Pos) /*!< 0x00000008 */ 4026 #define CEC_CSR_TBTRF CEC_CSR_TBTRF_Msk /*!< Tx Byte Transfer Request or Block Transfer Finished */ 4027 #define CEC_CSR_RSOM_Pos (4U) 4028 #define CEC_CSR_RSOM_Msk (0x1UL << CEC_CSR_RSOM_Pos) /*!< 0x00000010 */ 4029 #define CEC_CSR_RSOM CEC_CSR_RSOM_Msk /*!< Rx Start Of Message */ 4030 #define CEC_CSR_REOM_Pos (5U) 4031 #define CEC_CSR_REOM_Msk (0x1UL << CEC_CSR_REOM_Pos) /*!< 0x00000020 */ 4032 #define CEC_CSR_REOM CEC_CSR_REOM_Msk /*!< Rx End Of Message */ 4033 #define CEC_CSR_RERR_Pos (6U) 4034 #define CEC_CSR_RERR_Msk (0x1UL << CEC_CSR_RERR_Pos) /*!< 0x00000040 */ 4035 #define CEC_CSR_RERR CEC_CSR_RERR_Msk /*!< Rx Error */ 4036 #define CEC_CSR_RBTF_Pos (7U) 4037 #define CEC_CSR_RBTF_Msk (0x1UL << CEC_CSR_RBTF_Pos) /*!< 0x00000080 */ 4038 #define CEC_CSR_RBTF CEC_CSR_RBTF_Msk /*!< Rx Block Transfer Finished */ 4039 4040 /******************** Bit definition for CEC_TXD register ******************/ 4041 #define CEC_TXD_TXD_Pos (0U) 4042 #define CEC_TXD_TXD_Msk (0xFFUL << CEC_TXD_TXD_Pos) /*!< 0x000000FF */ 4043 #define CEC_TXD_TXD CEC_TXD_TXD_Msk /*!< Tx Data register */ 4044 4045 /******************** Bit definition for CEC_RXD register ******************/ 4046 #define CEC_RXD_RXD_Pos (0U) 4047 #define CEC_RXD_RXD_Msk (0xFFUL << CEC_RXD_RXD_Pos) /*!< 0x000000FF */ 4048 #define CEC_RXD_RXD CEC_RXD_RXD_Msk /*!< Rx Data register */ 4049 4050 /*****************************************************************************/ 4051 /* */ 4052 /* Timers (TIM) */ 4053 /* */ 4054 /*****************************************************************************/ 4055 /******************* Bit definition for TIM_CR1 register *******************/ 4056 #define TIM_CR1_CEN_Pos (0U) 4057 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 4058 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 4059 #define TIM_CR1_UDIS_Pos (1U) 4060 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 4061 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 4062 #define TIM_CR1_URS_Pos (2U) 4063 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 4064 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 4065 #define TIM_CR1_OPM_Pos (3U) 4066 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 4067 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 4068 #define TIM_CR1_DIR_Pos (4U) 4069 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 4070 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 4071 4072 #define TIM_CR1_CMS_Pos (5U) 4073 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 4074 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4075 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 4076 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 4077 4078 #define TIM_CR1_ARPE_Pos (7U) 4079 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 4080 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 4081 4082 #define TIM_CR1_CKD_Pos (8U) 4083 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 4084 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 4085 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 4086 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 4087 4088 /******************* Bit definition for TIM_CR2 register *******************/ 4089 #define TIM_CR2_CCPC_Pos (0U) 4090 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 4091 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 4092 #define TIM_CR2_CCUS_Pos (2U) 4093 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 4094 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 4095 #define TIM_CR2_CCDS_Pos (3U) 4096 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 4097 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 4098 4099 #define TIM_CR2_MMS_Pos (4U) 4100 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 4101 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 4102 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 4103 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 4104 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 4105 4106 #define TIM_CR2_TI1S_Pos (7U) 4107 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 4108 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 4109 #define TIM_CR2_OIS1_Pos (8U) 4110 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 4111 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 4112 #define TIM_CR2_OIS1N_Pos (9U) 4113 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 4114 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 4115 #define TIM_CR2_OIS2_Pos (10U) 4116 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 4117 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 4118 #define TIM_CR2_OIS2N_Pos (11U) 4119 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 4120 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 4121 #define TIM_CR2_OIS3_Pos (12U) 4122 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 4123 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 4124 #define TIM_CR2_OIS3N_Pos (13U) 4125 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 4126 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 4127 #define TIM_CR2_OIS4_Pos (14U) 4128 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 4129 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 4130 4131 /******************* Bit definition for TIM_SMCR register ******************/ 4132 #define TIM_SMCR_SMS_Pos (0U) 4133 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 4134 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 4135 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 4136 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 4137 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 4138 4139 #define TIM_SMCR_TS_Pos (4U) 4140 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 4141 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 4142 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 4143 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 4144 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 4145 4146 #define TIM_SMCR_MSM_Pos (7U) 4147 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 4148 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 4149 4150 #define TIM_SMCR_ETF_Pos (8U) 4151 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 4152 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 4153 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 4154 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 4155 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 4156 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 4157 4158 #define TIM_SMCR_ETPS_Pos (12U) 4159 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 4160 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 4161 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 4162 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 4163 4164 #define TIM_SMCR_ECE_Pos (14U) 4165 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 4166 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 4167 #define TIM_SMCR_ETP_Pos (15U) 4168 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 4169 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 4170 4171 /******************* Bit definition for TIM_DIER register ******************/ 4172 #define TIM_DIER_UIE_Pos (0U) 4173 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 4174 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 4175 #define TIM_DIER_CC1IE_Pos (1U) 4176 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 4177 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 4178 #define TIM_DIER_CC2IE_Pos (2U) 4179 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 4180 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 4181 #define TIM_DIER_CC3IE_Pos (3U) 4182 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 4183 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 4184 #define TIM_DIER_CC4IE_Pos (4U) 4185 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 4186 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 4187 #define TIM_DIER_COMIE_Pos (5U) 4188 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 4189 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 4190 #define TIM_DIER_TIE_Pos (6U) 4191 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 4192 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 4193 #define TIM_DIER_BIE_Pos (7U) 4194 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 4195 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 4196 #define TIM_DIER_UDE_Pos (8U) 4197 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 4198 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 4199 #define TIM_DIER_CC1DE_Pos (9U) 4200 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 4201 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 4202 #define TIM_DIER_CC2DE_Pos (10U) 4203 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 4204 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 4205 #define TIM_DIER_CC3DE_Pos (11U) 4206 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 4207 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 4208 #define TIM_DIER_CC4DE_Pos (12U) 4209 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 4210 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 4211 #define TIM_DIER_COMDE_Pos (13U) 4212 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 4213 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 4214 #define TIM_DIER_TDE_Pos (14U) 4215 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 4216 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 4217 4218 /******************** Bit definition for TIM_SR register *******************/ 4219 #define TIM_SR_UIF_Pos (0U) 4220 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 4221 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 4222 #define TIM_SR_CC1IF_Pos (1U) 4223 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 4224 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 4225 #define TIM_SR_CC2IF_Pos (2U) 4226 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 4227 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 4228 #define TIM_SR_CC3IF_Pos (3U) 4229 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 4230 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 4231 #define TIM_SR_CC4IF_Pos (4U) 4232 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 4233 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 4234 #define TIM_SR_COMIF_Pos (5U) 4235 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 4236 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 4237 #define TIM_SR_TIF_Pos (6U) 4238 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 4239 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 4240 #define TIM_SR_BIF_Pos (7U) 4241 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 4242 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 4243 #define TIM_SR_CC1OF_Pos (9U) 4244 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 4245 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 4246 #define TIM_SR_CC2OF_Pos (10U) 4247 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 4248 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 4249 #define TIM_SR_CC3OF_Pos (11U) 4250 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 4251 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 4252 #define TIM_SR_CC4OF_Pos (12U) 4253 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 4254 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 4255 4256 /******************* Bit definition for TIM_EGR register *******************/ 4257 #define TIM_EGR_UG_Pos (0U) 4258 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 4259 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 4260 #define TIM_EGR_CC1G_Pos (1U) 4261 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 4262 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 4263 #define TIM_EGR_CC2G_Pos (2U) 4264 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 4265 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 4266 #define TIM_EGR_CC3G_Pos (3U) 4267 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 4268 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 4269 #define TIM_EGR_CC4G_Pos (4U) 4270 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 4271 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 4272 #define TIM_EGR_COMG_Pos (5U) 4273 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 4274 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 4275 #define TIM_EGR_TG_Pos (6U) 4276 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 4277 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 4278 #define TIM_EGR_BG_Pos (7U) 4279 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 4280 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 4281 4282 /****************** Bit definition for TIM_CCMR1 register ******************/ 4283 #define TIM_CCMR1_CC1S_Pos (0U) 4284 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 4285 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 4286 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 4287 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 4288 4289 #define TIM_CCMR1_OC1FE_Pos (2U) 4290 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 4291 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 4292 #define TIM_CCMR1_OC1PE_Pos (3U) 4293 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 4294 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 4295 4296 #define TIM_CCMR1_OC1M_Pos (4U) 4297 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 4298 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 4299 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 4300 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 4301 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 4302 4303 #define TIM_CCMR1_OC1CE_Pos (7U) 4304 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 4305 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 4306 4307 #define TIM_CCMR1_CC2S_Pos (8U) 4308 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 4309 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 4310 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 4311 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 4312 4313 #define TIM_CCMR1_OC2FE_Pos (10U) 4314 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 4315 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 4316 #define TIM_CCMR1_OC2PE_Pos (11U) 4317 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 4318 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 4319 4320 #define TIM_CCMR1_OC2M_Pos (12U) 4321 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 4322 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 4323 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 4324 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 4325 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 4326 4327 #define TIM_CCMR1_OC2CE_Pos (15U) 4328 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 4329 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 4330 4331 /*---------------------------------------------------------------------------*/ 4332 4333 #define TIM_CCMR1_IC1PSC_Pos (2U) 4334 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 4335 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 4336 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 4337 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 4338 4339 #define TIM_CCMR1_IC1F_Pos (4U) 4340 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 4341 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 4342 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 4343 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 4344 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 4345 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 4346 4347 #define TIM_CCMR1_IC2PSC_Pos (10U) 4348 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 4349 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 4350 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 4351 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 4352 4353 #define TIM_CCMR1_IC2F_Pos (12U) 4354 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 4355 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 4356 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 4357 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 4358 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 4359 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 4360 4361 /****************** Bit definition for TIM_CCMR2 register ******************/ 4362 #define TIM_CCMR2_CC3S_Pos (0U) 4363 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 4364 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 4365 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 4366 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 4367 4368 #define TIM_CCMR2_OC3FE_Pos (2U) 4369 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 4370 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 4371 #define TIM_CCMR2_OC3PE_Pos (3U) 4372 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 4373 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 4374 4375 #define TIM_CCMR2_OC3M_Pos (4U) 4376 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 4377 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 4378 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 4379 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 4380 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 4381 4382 #define TIM_CCMR2_OC3CE_Pos (7U) 4383 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 4384 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 4385 4386 #define TIM_CCMR2_CC4S_Pos (8U) 4387 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 4388 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 4389 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 4390 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 4391 4392 #define TIM_CCMR2_OC4FE_Pos (10U) 4393 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 4394 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 4395 #define TIM_CCMR2_OC4PE_Pos (11U) 4396 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 4397 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 4398 4399 #define TIM_CCMR2_OC4M_Pos (12U) 4400 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 4401 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 4402 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 4403 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 4404 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 4405 4406 #define TIM_CCMR2_OC4CE_Pos (15U) 4407 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 4408 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 4409 4410 /*---------------------------------------------------------------------------*/ 4411 4412 #define TIM_CCMR2_IC3PSC_Pos (2U) 4413 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 4414 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 4415 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 4416 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 4417 4418 #define TIM_CCMR2_IC3F_Pos (4U) 4419 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 4420 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 4421 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 4422 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 4423 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 4424 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 4425 4426 #define TIM_CCMR2_IC4PSC_Pos (10U) 4427 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 4428 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 4429 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 4430 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 4431 4432 #define TIM_CCMR2_IC4F_Pos (12U) 4433 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 4434 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 4435 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 4436 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 4437 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 4438 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 4439 4440 /******************* Bit definition for TIM_CCER register ******************/ 4441 #define TIM_CCER_CC1E_Pos (0U) 4442 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 4443 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 4444 #define TIM_CCER_CC1P_Pos (1U) 4445 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 4446 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 4447 #define TIM_CCER_CC1NE_Pos (2U) 4448 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 4449 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 4450 #define TIM_CCER_CC1NP_Pos (3U) 4451 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 4452 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 4453 #define TIM_CCER_CC2E_Pos (4U) 4454 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 4455 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 4456 #define TIM_CCER_CC2P_Pos (5U) 4457 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 4458 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 4459 #define TIM_CCER_CC2NE_Pos (6U) 4460 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 4461 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 4462 #define TIM_CCER_CC2NP_Pos (7U) 4463 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 4464 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 4465 #define TIM_CCER_CC3E_Pos (8U) 4466 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 4467 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 4468 #define TIM_CCER_CC3P_Pos (9U) 4469 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 4470 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 4471 #define TIM_CCER_CC3NE_Pos (10U) 4472 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 4473 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 4474 #define TIM_CCER_CC3NP_Pos (11U) 4475 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 4476 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 4477 #define TIM_CCER_CC4E_Pos (12U) 4478 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 4479 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 4480 #define TIM_CCER_CC4P_Pos (13U) 4481 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 4482 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 4483 4484 /******************* Bit definition for TIM_CNT register *******************/ 4485 #define TIM_CNT_CNT_Pos (0U) 4486 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 4487 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 4488 4489 /******************* Bit definition for TIM_PSC register *******************/ 4490 #define TIM_PSC_PSC_Pos (0U) 4491 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 4492 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 4493 4494 /******************* Bit definition for TIM_ARR register *******************/ 4495 #define TIM_ARR_ARR_Pos (0U) 4496 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 4497 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 4498 4499 /******************* Bit definition for TIM_RCR register *******************/ 4500 #define TIM_RCR_REP_Pos (0U) 4501 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 4502 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 4503 4504 /******************* Bit definition for TIM_CCR1 register ******************/ 4505 #define TIM_CCR1_CCR1_Pos (0U) 4506 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 4507 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 4508 4509 /******************* Bit definition for TIM_CCR2 register ******************/ 4510 #define TIM_CCR2_CCR2_Pos (0U) 4511 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 4512 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 4513 4514 /******************* Bit definition for TIM_CCR3 register ******************/ 4515 #define TIM_CCR3_CCR3_Pos (0U) 4516 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 4517 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 4518 4519 /******************* Bit definition for TIM_CCR4 register ******************/ 4520 #define TIM_CCR4_CCR4_Pos (0U) 4521 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 4522 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 4523 4524 /******************* Bit definition for TIM_BDTR register ******************/ 4525 #define TIM_BDTR_DTG_Pos (0U) 4526 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 4527 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 4528 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 4529 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 4530 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 4531 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 4532 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 4533 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 4534 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 4535 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 4536 4537 #define TIM_BDTR_LOCK_Pos (8U) 4538 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 4539 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 4540 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 4541 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 4542 4543 #define TIM_BDTR_OSSI_Pos (10U) 4544 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 4545 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 4546 #define TIM_BDTR_OSSR_Pos (11U) 4547 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 4548 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 4549 #define TIM_BDTR_BKE_Pos (12U) 4550 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 4551 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 4552 #define TIM_BDTR_BKP_Pos (13U) 4553 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 4554 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 4555 #define TIM_BDTR_AOE_Pos (14U) 4556 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 4557 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 4558 #define TIM_BDTR_MOE_Pos (15U) 4559 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 4560 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 4561 4562 /******************* Bit definition for TIM_DCR register *******************/ 4563 #define TIM_DCR_DBA_Pos (0U) 4564 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 4565 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 4566 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 4567 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 4568 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 4569 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 4570 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 4571 4572 #define TIM_DCR_DBL_Pos (8U) 4573 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 4574 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 4575 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 4576 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 4577 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 4578 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 4579 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 4580 4581 /******************* Bit definition for TIM_DMAR register ******************/ 4582 #define TIM_DMAR_DMAB_Pos (0U) 4583 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 4584 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 4585 4586 /******************************************************************************/ 4587 /* */ 4588 /* Real-Time Clock */ 4589 /* */ 4590 /******************************************************************************/ 4591 4592 /******************* Bit definition for RTC_CRH register ********************/ 4593 #define RTC_CRH_SECIE_Pos (0U) 4594 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ 4595 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ 4596 #define RTC_CRH_ALRIE_Pos (1U) 4597 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ 4598 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ 4599 #define RTC_CRH_OWIE_Pos (2U) 4600 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ 4601 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ 4602 4603 /******************* Bit definition for RTC_CRL register ********************/ 4604 #define RTC_CRL_SECF_Pos (0U) 4605 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ 4606 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ 4607 #define RTC_CRL_ALRF_Pos (1U) 4608 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ 4609 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ 4610 #define RTC_CRL_OWF_Pos (2U) 4611 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ 4612 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ 4613 #define RTC_CRL_RSF_Pos (3U) 4614 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ 4615 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ 4616 #define RTC_CRL_CNF_Pos (4U) 4617 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ 4618 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ 4619 #define RTC_CRL_RTOFF_Pos (5U) 4620 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ 4621 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ 4622 4623 /******************* Bit definition for RTC_PRLH register *******************/ 4624 #define RTC_PRLH_PRL_Pos (0U) 4625 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ 4626 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ 4627 4628 /******************* Bit definition for RTC_PRLL register *******************/ 4629 #define RTC_PRLL_PRL_Pos (0U) 4630 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ 4631 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ 4632 4633 /******************* Bit definition for RTC_DIVH register *******************/ 4634 #define RTC_DIVH_RTC_DIV_Pos (0U) 4635 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ 4636 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ 4637 4638 /******************* Bit definition for RTC_DIVL register *******************/ 4639 #define RTC_DIVL_RTC_DIV_Pos (0U) 4640 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ 4641 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ 4642 4643 /******************* Bit definition for RTC_CNTH register *******************/ 4644 #define RTC_CNTH_RTC_CNT_Pos (0U) 4645 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4646 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ 4647 4648 /******************* Bit definition for RTC_CNTL register *******************/ 4649 #define RTC_CNTL_RTC_CNT_Pos (0U) 4650 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ 4651 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ 4652 4653 /******************* Bit definition for RTC_ALRH register *******************/ 4654 #define RTC_ALRH_RTC_ALR_Pos (0U) 4655 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ 4656 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ 4657 4658 /******************* Bit definition for RTC_ALRL register *******************/ 4659 #define RTC_ALRL_RTC_ALR_Pos (0U) 4660 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ 4661 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ 4662 4663 /******************************************************************************/ 4664 /* */ 4665 /* Independent WATCHDOG (IWDG) */ 4666 /* */ 4667 /******************************************************************************/ 4668 4669 /******************* Bit definition for IWDG_KR register ********************/ 4670 #define IWDG_KR_KEY_Pos (0U) 4671 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 4672 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 4673 4674 /******************* Bit definition for IWDG_PR register ********************/ 4675 #define IWDG_PR_PR_Pos (0U) 4676 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 4677 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 4678 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 4679 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 4680 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 4681 4682 /******************* Bit definition for IWDG_RLR register *******************/ 4683 #define IWDG_RLR_RL_Pos (0U) 4684 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 4685 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 4686 4687 /******************* Bit definition for IWDG_SR register ********************/ 4688 #define IWDG_SR_PVU_Pos (0U) 4689 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 4690 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 4691 #define IWDG_SR_RVU_Pos (1U) 4692 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 4693 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 4694 4695 /******************************************************************************/ 4696 /* */ 4697 /* Window WATCHDOG (WWDG) */ 4698 /* */ 4699 /******************************************************************************/ 4700 4701 /******************* Bit definition for WWDG_CR register ********************/ 4702 #define WWDG_CR_T_Pos (0U) 4703 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ 4704 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 4705 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ 4706 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ 4707 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ 4708 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ 4709 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ 4710 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ 4711 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ 4712 4713 /* Legacy defines */ 4714 #define WWDG_CR_T0 WWDG_CR_T_0 4715 #define WWDG_CR_T1 WWDG_CR_T_1 4716 #define WWDG_CR_T2 WWDG_CR_T_2 4717 #define WWDG_CR_T3 WWDG_CR_T_3 4718 #define WWDG_CR_T4 WWDG_CR_T_4 4719 #define WWDG_CR_T5 WWDG_CR_T_5 4720 #define WWDG_CR_T6 WWDG_CR_T_6 4721 4722 #define WWDG_CR_WDGA_Pos (7U) 4723 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 4724 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 4725 4726 /******************* Bit definition for WWDG_CFR register *******************/ 4727 #define WWDG_CFR_W_Pos (0U) 4728 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 4729 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 4730 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 4731 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 4732 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 4733 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 4734 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 4735 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 4736 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 4737 4738 /* Legacy defines */ 4739 #define WWDG_CFR_W0 WWDG_CFR_W_0 4740 #define WWDG_CFR_W1 WWDG_CFR_W_1 4741 #define WWDG_CFR_W2 WWDG_CFR_W_2 4742 #define WWDG_CFR_W3 WWDG_CFR_W_3 4743 #define WWDG_CFR_W4 WWDG_CFR_W_4 4744 #define WWDG_CFR_W5 WWDG_CFR_W_5 4745 #define WWDG_CFR_W6 WWDG_CFR_W_6 4746 4747 #define WWDG_CFR_WDGTB_Pos (7U) 4748 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 4749 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 4750 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 4751 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 4752 4753 /* Legacy defines */ 4754 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 4755 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 4756 4757 #define WWDG_CFR_EWI_Pos (9U) 4758 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 4759 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 4760 4761 /******************* Bit definition for WWDG_SR register ********************/ 4762 #define WWDG_SR_EWIF_Pos (0U) 4763 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 4764 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 4765 4766 4767 4768 /******************************************************************************/ 4769 /* */ 4770 /* Serial Peripheral Interface */ 4771 /* */ 4772 /******************************************************************************/ 4773 4774 /******************* Bit definition for SPI_CR1 register ********************/ 4775 #define SPI_CR1_CPHA_Pos (0U) 4776 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4777 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4778 #define SPI_CR1_CPOL_Pos (1U) 4779 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4780 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4781 #define SPI_CR1_MSTR_Pos (2U) 4782 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4783 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4784 4785 #define SPI_CR1_BR_Pos (3U) 4786 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4787 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4788 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4789 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4790 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4791 4792 #define SPI_CR1_SPE_Pos (6U) 4793 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4794 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4795 #define SPI_CR1_LSBFIRST_Pos (7U) 4796 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4797 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4798 #define SPI_CR1_SSI_Pos (8U) 4799 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4800 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4801 #define SPI_CR1_SSM_Pos (9U) 4802 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4803 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4804 #define SPI_CR1_RXONLY_Pos (10U) 4805 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4806 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4807 #define SPI_CR1_DFF_Pos (11U) 4808 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 4809 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 4810 #define SPI_CR1_CRCNEXT_Pos (12U) 4811 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4812 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4813 #define SPI_CR1_CRCEN_Pos (13U) 4814 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4815 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4816 #define SPI_CR1_BIDIOE_Pos (14U) 4817 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4818 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4819 #define SPI_CR1_BIDIMODE_Pos (15U) 4820 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4821 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4822 4823 /******************* Bit definition for SPI_CR2 register ********************/ 4824 #define SPI_CR2_RXDMAEN_Pos (0U) 4825 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4826 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4827 #define SPI_CR2_TXDMAEN_Pos (1U) 4828 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4829 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4830 #define SPI_CR2_SSOE_Pos (2U) 4831 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4832 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4833 #define SPI_CR2_ERRIE_Pos (5U) 4834 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4835 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4836 #define SPI_CR2_RXNEIE_Pos (6U) 4837 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4838 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4839 #define SPI_CR2_TXEIE_Pos (7U) 4840 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4841 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4842 4843 /******************** Bit definition for SPI_SR register ********************/ 4844 #define SPI_SR_RXNE_Pos (0U) 4845 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4846 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4847 #define SPI_SR_TXE_Pos (1U) 4848 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4849 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 4850 #define SPI_SR_CHSIDE_Pos (2U) 4851 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 4852 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 4853 #define SPI_SR_UDR_Pos (3U) 4854 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 4855 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 4856 #define SPI_SR_CRCERR_Pos (4U) 4857 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 4858 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 4859 #define SPI_SR_MODF_Pos (5U) 4860 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 4861 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 4862 #define SPI_SR_OVR_Pos (6U) 4863 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 4864 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 4865 #define SPI_SR_BSY_Pos (7U) 4866 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 4867 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 4868 4869 /******************** Bit definition for SPI_DR register ********************/ 4870 #define SPI_DR_DR_Pos (0U) 4871 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 4872 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 4873 4874 /******************* Bit definition for SPI_CRCPR register ******************/ 4875 #define SPI_CRCPR_CRCPOLY_Pos (0U) 4876 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 4877 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 4878 4879 /****************** Bit definition for SPI_RXCRCR register ******************/ 4880 #define SPI_RXCRCR_RXCRC_Pos (0U) 4881 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 4882 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 4883 4884 /****************** Bit definition for SPI_TXCRCR register ******************/ 4885 #define SPI_TXCRCR_TXCRC_Pos (0U) 4886 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 4887 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 4888 4889 4890 /******************************************************************************/ 4891 /* */ 4892 /* Inter-integrated Circuit Interface */ 4893 /* */ 4894 /******************************************************************************/ 4895 4896 /******************* Bit definition for I2C_CR1 register ********************/ 4897 #define I2C_CR1_PE_Pos (0U) 4898 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 4899 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 4900 #define I2C_CR1_SMBUS_Pos (1U) 4901 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 4902 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 4903 #define I2C_CR1_SMBTYPE_Pos (3U) 4904 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 4905 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 4906 #define I2C_CR1_ENARP_Pos (4U) 4907 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 4908 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 4909 #define I2C_CR1_ENPEC_Pos (5U) 4910 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 4911 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 4912 #define I2C_CR1_ENGC_Pos (6U) 4913 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 4914 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 4915 #define I2C_CR1_NOSTRETCH_Pos (7U) 4916 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 4917 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 4918 #define I2C_CR1_START_Pos (8U) 4919 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ 4920 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 4921 #define I2C_CR1_STOP_Pos (9U) 4922 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 4923 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 4924 #define I2C_CR1_ACK_Pos (10U) 4925 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 4926 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 4927 #define I2C_CR1_POS_Pos (11U) 4928 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 4929 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 4930 #define I2C_CR1_PEC_Pos (12U) 4931 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 4932 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 4933 #define I2C_CR1_ALERT_Pos (13U) 4934 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 4935 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 4936 #define I2C_CR1_SWRST_Pos (15U) 4937 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 4938 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 4939 4940 /******************* Bit definition for I2C_CR2 register ********************/ 4941 #define I2C_CR2_FREQ_Pos (0U) 4942 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 4943 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 4944 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 4945 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 4946 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 4947 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 4948 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 4949 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 4950 4951 #define I2C_CR2_ITERREN_Pos (8U) 4952 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 4953 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 4954 #define I2C_CR2_ITEVTEN_Pos (9U) 4955 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 4956 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 4957 #define I2C_CR2_ITBUFEN_Pos (10U) 4958 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 4959 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 4960 #define I2C_CR2_DMAEN_Pos (11U) 4961 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 4962 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 4963 #define I2C_CR2_LAST_Pos (12U) 4964 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 4965 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 4966 4967 /******************* Bit definition for I2C_OAR1 register *******************/ 4968 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ 4969 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ 4970 4971 #define I2C_OAR1_ADD0_Pos (0U) 4972 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 4973 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 4974 #define I2C_OAR1_ADD1_Pos (1U) 4975 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 4976 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 4977 #define I2C_OAR1_ADD2_Pos (2U) 4978 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 4979 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 4980 #define I2C_OAR1_ADD3_Pos (3U) 4981 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 4982 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 4983 #define I2C_OAR1_ADD4_Pos (4U) 4984 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 4985 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 4986 #define I2C_OAR1_ADD5_Pos (5U) 4987 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 4988 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 4989 #define I2C_OAR1_ADD6_Pos (6U) 4990 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 4991 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 4992 #define I2C_OAR1_ADD7_Pos (7U) 4993 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 4994 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 4995 #define I2C_OAR1_ADD8_Pos (8U) 4996 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 4997 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 4998 #define I2C_OAR1_ADD9_Pos (9U) 4999 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 5000 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 5001 5002 #define I2C_OAR1_ADDMODE_Pos (15U) 5003 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 5004 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 5005 5006 /******************* Bit definition for I2C_OAR2 register *******************/ 5007 #define I2C_OAR2_ENDUAL_Pos (0U) 5008 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 5009 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 5010 #define I2C_OAR2_ADD2_Pos (1U) 5011 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 5012 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 5013 5014 /******************** Bit definition for I2C_DR register ********************/ 5015 #define I2C_DR_DR_Pos (0U) 5016 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ 5017 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ 5018 5019 /******************* Bit definition for I2C_SR1 register ********************/ 5020 #define I2C_SR1_SB_Pos (0U) 5021 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 5022 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 5023 #define I2C_SR1_ADDR_Pos (1U) 5024 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 5025 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 5026 #define I2C_SR1_BTF_Pos (2U) 5027 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 5028 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 5029 #define I2C_SR1_ADD10_Pos (3U) 5030 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 5031 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 5032 #define I2C_SR1_STOPF_Pos (4U) 5033 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 5034 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 5035 #define I2C_SR1_RXNE_Pos (6U) 5036 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 5037 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 5038 #define I2C_SR1_TXE_Pos (7U) 5039 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 5040 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 5041 #define I2C_SR1_BERR_Pos (8U) 5042 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 5043 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 5044 #define I2C_SR1_ARLO_Pos (9U) 5045 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 5046 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 5047 #define I2C_SR1_AF_Pos (10U) 5048 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 5049 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 5050 #define I2C_SR1_OVR_Pos (11U) 5051 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 5052 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 5053 #define I2C_SR1_PECERR_Pos (12U) 5054 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 5055 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 5056 #define I2C_SR1_TIMEOUT_Pos (14U) 5057 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 5058 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 5059 #define I2C_SR1_SMBALERT_Pos (15U) 5060 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 5061 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 5062 5063 /******************* Bit definition for I2C_SR2 register ********************/ 5064 #define I2C_SR2_MSL_Pos (0U) 5065 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 5066 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 5067 #define I2C_SR2_BUSY_Pos (1U) 5068 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 5069 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 5070 #define I2C_SR2_TRA_Pos (2U) 5071 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 5072 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 5073 #define I2C_SR2_GENCALL_Pos (4U) 5074 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 5075 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 5076 #define I2C_SR2_SMBDEFAULT_Pos (5U) 5077 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 5078 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 5079 #define I2C_SR2_SMBHOST_Pos (6U) 5080 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 5081 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 5082 #define I2C_SR2_DUALF_Pos (7U) 5083 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 5084 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 5085 #define I2C_SR2_PEC_Pos (8U) 5086 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 5087 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 5088 5089 /******************* Bit definition for I2C_CCR register ********************/ 5090 #define I2C_CCR_CCR_Pos (0U) 5091 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 5092 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 5093 #define I2C_CCR_DUTY_Pos (14U) 5094 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 5095 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 5096 #define I2C_CCR_FS_Pos (15U) 5097 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 5098 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 5099 5100 /****************** Bit definition for I2C_TRISE register *******************/ 5101 #define I2C_TRISE_TRISE_Pos (0U) 5102 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 5103 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 5104 5105 /******************************************************************************/ 5106 /* */ 5107 /* Universal Synchronous Asynchronous Receiver Transmitter */ 5108 /* */ 5109 /******************************************************************************/ 5110 5111 /******************* Bit definition for USART_SR register *******************/ 5112 #define USART_SR_PE_Pos (0U) 5113 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ 5114 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 5115 #define USART_SR_FE_Pos (1U) 5116 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ 5117 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 5118 #define USART_SR_NE_Pos (2U) 5119 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ 5120 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 5121 #define USART_SR_ORE_Pos (3U) 5122 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ 5123 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 5124 #define USART_SR_IDLE_Pos (4U) 5125 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 5126 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 5127 #define USART_SR_RXNE_Pos (5U) 5128 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 5129 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 5130 #define USART_SR_TC_Pos (6U) 5131 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ 5132 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 5133 #define USART_SR_TXE_Pos (7U) 5134 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ 5135 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 5136 #define USART_SR_LBD_Pos (8U) 5137 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ 5138 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 5139 #define USART_SR_CTS_Pos (9U) 5140 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ 5141 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 5142 5143 /******************* Bit definition for USART_DR register *******************/ 5144 #define USART_DR_DR_Pos (0U) 5145 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ 5146 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 5147 5148 /****************** Bit definition for USART_BRR register *******************/ 5149 #define USART_BRR_DIV_Fraction_Pos (0U) 5150 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 5151 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ 5152 #define USART_BRR_DIV_Mantissa_Pos (4U) 5153 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 5154 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ 5155 5156 /****************** Bit definition for USART_CR1 register *******************/ 5157 #define USART_CR1_SBK_Pos (0U) 5158 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 5159 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 5160 #define USART_CR1_RWU_Pos (1U) 5161 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 5162 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 5163 #define USART_CR1_RE_Pos (2U) 5164 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5165 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5166 #define USART_CR1_TE_Pos (3U) 5167 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5168 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5169 #define USART_CR1_IDLEIE_Pos (4U) 5170 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5171 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5172 #define USART_CR1_RXNEIE_Pos (5U) 5173 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5174 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5175 #define USART_CR1_TCIE_Pos (6U) 5176 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5177 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5178 #define USART_CR1_TXEIE_Pos (7U) 5179 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5180 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 5181 #define USART_CR1_PEIE_Pos (8U) 5182 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5183 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5184 #define USART_CR1_PS_Pos (9U) 5185 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5186 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5187 #define USART_CR1_PCE_Pos (10U) 5188 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5189 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5190 #define USART_CR1_WAKE_Pos (11U) 5191 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5192 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 5193 #define USART_CR1_M_Pos (12U) 5194 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ 5195 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 5196 #define USART_CR1_UE_Pos (13U) 5197 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ 5198 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5199 #define USART_CR1_OVER8_Pos (15U) 5200 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5201 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< USART Oversmapling 8-bits */ 5202 5203 /****************** Bit definition for USART_CR2 register *******************/ 5204 #define USART_CR2_ADD_Pos (0U) 5205 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 5206 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 5207 #define USART_CR2_LBDL_Pos (5U) 5208 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 5209 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 5210 #define USART_CR2_LBDIE_Pos (6U) 5211 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 5212 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 5213 #define USART_CR2_LBCL_Pos (8U) 5214 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5215 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5216 #define USART_CR2_CPHA_Pos (9U) 5217 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5218 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5219 #define USART_CR2_CPOL_Pos (10U) 5220 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5221 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5222 #define USART_CR2_CLKEN_Pos (11U) 5223 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5224 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5225 5226 #define USART_CR2_STOP_Pos (12U) 5227 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5228 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5229 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5230 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5231 5232 #define USART_CR2_LINEN_Pos (14U) 5233 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 5234 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 5235 5236 /****************** Bit definition for USART_CR3 register *******************/ 5237 #define USART_CR3_EIE_Pos (0U) 5238 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 5239 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 5240 #define USART_CR3_IREN_Pos (1U) 5241 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 5242 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 5243 #define USART_CR3_IRLP_Pos (2U) 5244 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 5245 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 5246 #define USART_CR3_HDSEL_Pos (3U) 5247 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 5248 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 5249 #define USART_CR3_NACK_Pos (4U) 5250 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 5251 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 5252 #define USART_CR3_SCEN_Pos (5U) 5253 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 5254 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 5255 #define USART_CR3_DMAR_Pos (6U) 5256 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 5257 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 5258 #define USART_CR3_DMAT_Pos (7U) 5259 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 5260 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 5261 #define USART_CR3_RTSE_Pos (8U) 5262 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 5263 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 5264 #define USART_CR3_CTSE_Pos (9U) 5265 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 5266 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 5267 #define USART_CR3_CTSIE_Pos (10U) 5268 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 5269 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 5270 #define USART_CR3_ONEBIT_Pos (11U) 5271 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 5272 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One Bit method */ 5273 5274 /****************** Bit definition for USART_GTPR register ******************/ 5275 #define USART_GTPR_PSC_Pos (0U) 5276 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 5277 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 5278 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 5279 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 5280 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 5281 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 5282 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 5283 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 5284 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 5285 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 5286 5287 #define USART_GTPR_GT_Pos (8U) 5288 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 5289 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 5290 5291 /******************************************************************************/ 5292 /* */ 5293 /* Debug MCU */ 5294 /* */ 5295 /******************************************************************************/ 5296 5297 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 5298 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 5299 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 5300 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 5301 5302 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 5303 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 5304 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 5305 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 5306 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 5307 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 5308 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 5309 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 5310 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 5311 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 5312 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 5313 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 5314 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 5315 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 5316 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 5317 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 5318 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 5319 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 5320 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 5321 5322 /****************** Bit definition for DBGMCU_CR register *******************/ 5323 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 5324 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 5325 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 5326 #define DBGMCU_CR_DBG_STOP_Pos (1U) 5327 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 5328 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 5329 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 5330 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 5331 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 5332 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 5333 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 5334 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 5335 5336 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 5337 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 5338 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 5339 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 5340 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 5341 5342 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) 5343 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ 5344 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 5345 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) 5346 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ 5347 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 5348 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) 5349 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ 5350 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 5351 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) 5352 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ 5353 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 5354 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) 5355 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ 5356 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 5357 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) 5358 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ 5359 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 5360 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) 5361 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ 5362 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 5363 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) 5364 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ 5365 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 5366 #define DBGMCU_CR_DBG_TIM15_STOP_Pos (22U) 5367 #define DBGMCU_CR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM15_STOP_Pos) /*!< 0x00400000 */ 5368 #define DBGMCU_CR_DBG_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP_Msk /*!< Debug TIM15 stopped when Core is halted */ 5369 #define DBGMCU_CR_DBG_TIM16_STOP_Pos (23U) 5370 #define DBGMCU_CR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM16_STOP_Pos) /*!< 0x00800000 */ 5371 #define DBGMCU_CR_DBG_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP_Msk /*!< Debug TIM16 stopped when Core is halted */ 5372 #define DBGMCU_CR_DBG_TIM17_STOP_Pos (24U) 5373 #define DBGMCU_CR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM17_STOP_Pos) /*!< 0x01000000 */ 5374 #define DBGMCU_CR_DBG_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP_Msk /*!< Debug TIM17 stopped when Core is halted */ 5375 5376 /******************************************************************************/ 5377 /* */ 5378 /* FLASH and Option Bytes Registers */ 5379 /* */ 5380 /******************************************************************************/ 5381 /******************* Bit definition for FLASH_ACR register ******************/ 5382 #define FLASH_ACR_HLFCYA_Pos (3U) 5383 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 5384 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 5385 5386 /****************** Bit definition for FLASH_KEYR register ******************/ 5387 #define FLASH_KEYR_FKEYR_Pos (0U) 5388 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 5389 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 5390 5391 #define RDP_KEY_Pos (0U) 5392 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ 5393 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 5394 #define FLASH_KEY1_Pos (0U) 5395 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ 5396 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 5397 #define FLASH_KEY2_Pos (0U) 5398 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 5399 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 5400 5401 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 5402 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 5403 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 5404 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 5405 5406 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 5407 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 5408 5409 /****************** Bit definition for FLASH_SR register ********************/ 5410 #define FLASH_SR_BSY_Pos (0U) 5411 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 5412 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 5413 #define FLASH_SR_PGERR_Pos (2U) 5414 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 5415 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 5416 #define FLASH_SR_WRPRTERR_Pos (4U) 5417 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 5418 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 5419 #define FLASH_SR_EOP_Pos (5U) 5420 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 5421 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 5422 5423 /******************* Bit definition for FLASH_CR register *******************/ 5424 #define FLASH_CR_PG_Pos (0U) 5425 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 5426 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 5427 #define FLASH_CR_PER_Pos (1U) 5428 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 5429 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 5430 #define FLASH_CR_MER_Pos (2U) 5431 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 5432 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 5433 #define FLASH_CR_OPTPG_Pos (4U) 5434 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 5435 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 5436 #define FLASH_CR_OPTER_Pos (5U) 5437 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 5438 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 5439 #define FLASH_CR_STRT_Pos (6U) 5440 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 5441 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 5442 #define FLASH_CR_LOCK_Pos (7U) 5443 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 5444 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 5445 #define FLASH_CR_OPTWRE_Pos (9U) 5446 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 5447 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 5448 #define FLASH_CR_ERRIE_Pos (10U) 5449 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 5450 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 5451 #define FLASH_CR_EOPIE_Pos (12U) 5452 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 5453 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 5454 5455 /******************* Bit definition for FLASH_AR register *******************/ 5456 #define FLASH_AR_FAR_Pos (0U) 5457 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 5458 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 5459 5460 /****************** Bit definition for FLASH_OBR register *******************/ 5461 #define FLASH_OBR_OPTERR_Pos (0U) 5462 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 5463 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 5464 #define FLASH_OBR_RDPRT_Pos (1U) 5465 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 5466 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 5467 5468 #define FLASH_OBR_IWDG_SW_Pos (2U) 5469 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ 5470 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 5471 #define FLASH_OBR_nRST_STOP_Pos (3U) 5472 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ 5473 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 5474 #define FLASH_OBR_nRST_STDBY_Pos (4U) 5475 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ 5476 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 5477 #define FLASH_OBR_USER_Pos (2U) 5478 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ 5479 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 5480 #define FLASH_OBR_DATA0_Pos (10U) 5481 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ 5482 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 5483 #define FLASH_OBR_DATA1_Pos (18U) 5484 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ 5485 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 5486 5487 /****************** Bit definition for FLASH_WRPR register ******************/ 5488 #define FLASH_WRPR_WRP_Pos (0U) 5489 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 5490 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 5491 5492 /*----------------------------------------------------------------------------*/ 5493 5494 /****************** Bit definition for FLASH_RDP register *******************/ 5495 #define FLASH_RDP_RDP_Pos (0U) 5496 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ 5497 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ 5498 #define FLASH_RDP_nRDP_Pos (8U) 5499 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 5500 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 5501 5502 /****************** Bit definition for FLASH_USER register ******************/ 5503 #define FLASH_USER_USER_Pos (16U) 5504 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ 5505 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ 5506 #define FLASH_USER_nUSER_Pos (24U) 5507 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ 5508 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ 5509 5510 /****************** Bit definition for FLASH_Data0 register *****************/ 5511 #define FLASH_DATA0_DATA0_Pos (0U) 5512 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ 5513 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ 5514 #define FLASH_DATA0_nDATA0_Pos (8U) 5515 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ 5516 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ 5517 5518 /****************** Bit definition for FLASH_Data1 register *****************/ 5519 #define FLASH_DATA1_DATA1_Pos (16U) 5520 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ 5521 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ 5522 #define FLASH_DATA1_nDATA1_Pos (24U) 5523 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ 5524 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ 5525 5526 /****************** Bit definition for FLASH_WRP0 register ******************/ 5527 #define FLASH_WRP0_WRP0_Pos (0U) 5528 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ 5529 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 5530 #define FLASH_WRP0_nWRP0_Pos (8U) 5531 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 5532 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 5533 5534 /****************** Bit definition for FLASH_WRP1 register ******************/ 5535 #define FLASH_WRP1_WRP1_Pos (16U) 5536 #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 5537 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 5538 #define FLASH_WRP1_nWRP1_Pos (24U) 5539 #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 5540 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 5541 5542 /****************** Bit definition for FLASH_WRP2 register ******************/ 5543 #define FLASH_WRP2_WRP2_Pos (0U) 5544 #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ 5545 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ 5546 #define FLASH_WRP2_nWRP2_Pos (8U) 5547 #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ 5548 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ 5549 5550 /****************** Bit definition for FLASH_WRP3 register ******************/ 5551 #define FLASH_WRP3_WRP3_Pos (16U) 5552 #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ 5553 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ 5554 #define FLASH_WRP3_nWRP3_Pos (24U) 5555 #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ 5556 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ 5557 5558 5559 5560 /** 5561 * @} 5562 */ 5563 5564 /** 5565 * @} 5566 */ 5567 5568 /** @addtogroup Exported_macro 5569 * @{ 5570 */ 5571 5572 /****************************** ADC Instances *********************************/ 5573 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) 5574 5575 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 5576 5577 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 5578 5579 /****************************** CEC Instances *********************************/ 5580 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC) 5581 5582 /****************************** CRC Instances *********************************/ 5583 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 5584 5585 /****************************** DAC Instances *********************************/ 5586 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) 5587 5588 /****************************** DMA Instances *********************************/ 5589 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 5590 ((INSTANCE) == DMA1_Channel2) || \ 5591 ((INSTANCE) == DMA1_Channel3) || \ 5592 ((INSTANCE) == DMA1_Channel4) || \ 5593 ((INSTANCE) == DMA1_Channel5) || \ 5594 ((INSTANCE) == DMA1_Channel6) || \ 5595 ((INSTANCE) == DMA1_Channel7)) 5596 5597 /******************************* GPIO Instances *******************************/ 5598 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 5599 ((INSTANCE) == GPIOB) || \ 5600 ((INSTANCE) == GPIOC) || \ 5601 ((INSTANCE) == GPIOD) || \ 5602 ((INSTANCE) == GPIOE)) 5603 5604 /**************************** GPIO Alternate Function Instances ***************/ 5605 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 5606 5607 /**************************** GPIO Lock Instances *****************************/ 5608 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 5609 5610 /******************************** I2C Instances *******************************/ 5611 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 5612 ((INSTANCE) == I2C2)) 5613 5614 /******************************* SMBUS Instances ******************************/ 5615 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE 5616 5617 /****************************** IWDG Instances ********************************/ 5618 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 5619 5620 /******************************** SPI Instances *******************************/ 5621 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 5622 ((INSTANCE) == SPI2)) 5623 5624 /****************************** START TIM Instances ***************************/ 5625 /****************************** TIM Instances *********************************/ 5626 #define IS_TIM_INSTANCE(INSTANCE)\ 5627 (((INSTANCE) == TIM1) || \ 5628 ((INSTANCE) == TIM2) || \ 5629 ((INSTANCE) == TIM3) || \ 5630 ((INSTANCE) == TIM4) || \ 5631 ((INSTANCE) == TIM6) || \ 5632 ((INSTANCE) == TIM7) || \ 5633 ((INSTANCE) == TIM15) || \ 5634 ((INSTANCE) == TIM16) || \ 5635 ((INSTANCE) == TIM17)) 5636 5637 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) 5638 5639 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 5640 (((INSTANCE) == TIM1) || \ 5641 ((INSTANCE) == TIM2) || \ 5642 ((INSTANCE) == TIM3) || \ 5643 ((INSTANCE) == TIM4) || \ 5644 ((INSTANCE) == TIM15) || \ 5645 ((INSTANCE) == TIM16) || \ 5646 ((INSTANCE) == TIM17)) 5647 5648 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 5649 (((INSTANCE) == TIM1) || \ 5650 ((INSTANCE) == TIM2) || \ 5651 ((INSTANCE) == TIM3) || \ 5652 ((INSTANCE) == TIM4) || \ 5653 ((INSTANCE) == TIM15)) 5654 5655 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 5656 (((INSTANCE) == TIM1) || \ 5657 ((INSTANCE) == TIM2) || \ 5658 ((INSTANCE) == TIM3) || \ 5659 ((INSTANCE) == TIM4)) 5660 5661 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 5662 (((INSTANCE) == TIM1) || \ 5663 ((INSTANCE) == TIM2) || \ 5664 ((INSTANCE) == TIM3) || \ 5665 ((INSTANCE) == TIM4)) 5666 5667 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 5668 (((INSTANCE) == TIM1) || \ 5669 ((INSTANCE) == TIM2) || \ 5670 ((INSTANCE) == TIM3) || \ 5671 ((INSTANCE) == TIM4)) 5672 5673 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 5674 (((INSTANCE) == TIM1) || \ 5675 ((INSTANCE) == TIM2) || \ 5676 ((INSTANCE) == TIM3) || \ 5677 ((INSTANCE) == TIM4)) 5678 5679 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 5680 (((INSTANCE) == TIM1) || \ 5681 ((INSTANCE) == TIM2) || \ 5682 ((INSTANCE) == TIM3) || \ 5683 ((INSTANCE) == TIM4) || \ 5684 ((INSTANCE) == TIM15)) 5685 5686 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 5687 (((INSTANCE) == TIM1) || \ 5688 ((INSTANCE) == TIM2) || \ 5689 ((INSTANCE) == TIM3) || \ 5690 ((INSTANCE) == TIM4) || \ 5691 ((INSTANCE) == TIM15)) 5692 5693 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 5694 (((INSTANCE) == TIM1) || \ 5695 ((INSTANCE) == TIM2) || \ 5696 ((INSTANCE) == TIM3) || \ 5697 ((INSTANCE) == TIM4)) 5698 5699 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 5700 (((INSTANCE) == TIM1) || \ 5701 ((INSTANCE) == TIM2) || \ 5702 ((INSTANCE) == TIM3) || \ 5703 ((INSTANCE) == TIM4)) 5704 5705 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 5706 (((INSTANCE) == TIM1) || \ 5707 ((INSTANCE) == TIM2) || \ 5708 ((INSTANCE) == TIM3) || \ 5709 ((INSTANCE) == TIM4)) 5710 5711 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 5712 (((INSTANCE) == TIM1) || \ 5713 ((INSTANCE) == TIM2) || \ 5714 ((INSTANCE) == TIM3) || \ 5715 ((INSTANCE) == TIM4) || \ 5716 ((INSTANCE) == TIM6) || \ 5717 ((INSTANCE) == TIM7) || \ 5718 ((INSTANCE) == TIM15)) 5719 5720 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 5721 (((INSTANCE) == TIM1) || \ 5722 ((INSTANCE) == TIM2) || \ 5723 ((INSTANCE) == TIM3) || \ 5724 ((INSTANCE) == TIM4) || \ 5725 ((INSTANCE) == TIM15)) 5726 5727 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 5728 (((INSTANCE) == TIM1) || \ 5729 ((INSTANCE) == TIM2) || \ 5730 ((INSTANCE) == TIM3) || \ 5731 ((INSTANCE) == TIM4) || \ 5732 ((INSTANCE) == TIM15) || \ 5733 ((INSTANCE) == TIM16) || \ 5734 ((INSTANCE) == TIM17)) 5735 5736 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 5737 (((INSTANCE) == TIM1) || \ 5738 ((INSTANCE) == TIM15) || \ 5739 ((INSTANCE) == TIM16) || \ 5740 ((INSTANCE) == TIM17)) 5741 5742 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 5743 ((((INSTANCE) == TIM1) && \ 5744 (((CHANNEL) == TIM_CHANNEL_1) || \ 5745 ((CHANNEL) == TIM_CHANNEL_2) || \ 5746 ((CHANNEL) == TIM_CHANNEL_3) || \ 5747 ((CHANNEL) == TIM_CHANNEL_4))) \ 5748 || \ 5749 (((INSTANCE) == TIM2) && \ 5750 (((CHANNEL) == TIM_CHANNEL_1) || \ 5751 ((CHANNEL) == TIM_CHANNEL_2) || \ 5752 ((CHANNEL) == TIM_CHANNEL_3) || \ 5753 ((CHANNEL) == TIM_CHANNEL_4))) \ 5754 || \ 5755 (((INSTANCE) == TIM3) && \ 5756 (((CHANNEL) == TIM_CHANNEL_1) || \ 5757 ((CHANNEL) == TIM_CHANNEL_2) || \ 5758 ((CHANNEL) == TIM_CHANNEL_3) || \ 5759 ((CHANNEL) == TIM_CHANNEL_4))) \ 5760 || \ 5761 (((INSTANCE) == TIM4) && \ 5762 (((CHANNEL) == TIM_CHANNEL_1) || \ 5763 ((CHANNEL) == TIM_CHANNEL_2) || \ 5764 ((CHANNEL) == TIM_CHANNEL_3) || \ 5765 ((CHANNEL) == TIM_CHANNEL_4))) \ 5766 || \ 5767 (((INSTANCE) == TIM15) && \ 5768 (((CHANNEL) == TIM_CHANNEL_1) || \ 5769 ((CHANNEL) == TIM_CHANNEL_2))) \ 5770 || \ 5771 (((INSTANCE) == TIM16) && \ 5772 (((CHANNEL) == TIM_CHANNEL_1))) \ 5773 || \ 5774 (((INSTANCE) == TIM17) && \ 5775 (((CHANNEL) == TIM_CHANNEL_1)))) 5776 5777 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 5778 ((((INSTANCE) == TIM1) && \ 5779 (((CHANNEL) == TIM_CHANNEL_1) || \ 5780 ((CHANNEL) == TIM_CHANNEL_2) || \ 5781 ((CHANNEL) == TIM_CHANNEL_3))) \ 5782 || \ 5783 (((INSTANCE) == TIM15) && \ 5784 ((CHANNEL) == TIM_CHANNEL_1)) \ 5785 || \ 5786 (((INSTANCE) == TIM16) && \ 5787 ((CHANNEL) == TIM_CHANNEL_1)) \ 5788 || \ 5789 (((INSTANCE) == TIM17) && \ 5790 ((CHANNEL) == TIM_CHANNEL_1))) 5791 5792 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 5793 (((INSTANCE) == TIM1) || \ 5794 ((INSTANCE) == TIM2) || \ 5795 ((INSTANCE) == TIM3) || \ 5796 ((INSTANCE) == TIM4)) 5797 5798 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 5799 (((INSTANCE) == TIM1) || \ 5800 ((INSTANCE) == TIM15) || \ 5801 ((INSTANCE) == TIM16) || \ 5802 ((INSTANCE) == TIM17)) 5803 5804 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 5805 (((INSTANCE) == TIM1) || \ 5806 ((INSTANCE) == TIM2) || \ 5807 ((INSTANCE) == TIM3) || \ 5808 ((INSTANCE) == TIM4) || \ 5809 ((INSTANCE) == TIM15) || \ 5810 ((INSTANCE) == TIM16) || \ 5811 ((INSTANCE) == TIM17)) 5812 5813 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 5814 (((INSTANCE) == TIM1) || \ 5815 ((INSTANCE) == TIM2) || \ 5816 ((INSTANCE) == TIM3) || \ 5817 ((INSTANCE) == TIM4) || \ 5818 ((INSTANCE) == TIM6) || \ 5819 ((INSTANCE) == TIM7) || \ 5820 ((INSTANCE) == TIM15) || \ 5821 ((INSTANCE) == TIM16) || \ 5822 ((INSTANCE) == TIM17)) 5823 5824 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 5825 (((INSTANCE) == TIM1) || \ 5826 ((INSTANCE) == TIM2) || \ 5827 ((INSTANCE) == TIM3) || \ 5828 ((INSTANCE) == TIM4) || \ 5829 ((INSTANCE) == TIM15) || \ 5830 ((INSTANCE) == TIM16) || \ 5831 ((INSTANCE) == TIM17)) 5832 5833 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 5834 (((INSTANCE) == TIM1) || \ 5835 ((INSTANCE) == TIM15) || \ 5836 ((INSTANCE) == TIM16) || \ 5837 ((INSTANCE) == TIM17)) 5838 5839 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 5840 ((INSTANCE) == TIM2) || \ 5841 ((INSTANCE) == TIM3) || \ 5842 ((INSTANCE) == TIM4)) 5843 5844 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ 5845 ((INSTANCE) == TIM2) || \ 5846 ((INSTANCE) == TIM3) || \ 5847 ((INSTANCE) == TIM4)) 5848 5849 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U 5850 5851 /****************************** END TIM Instances *****************************/ 5852 5853 5854 /******************** USART Instances : Synchronous mode **********************/ 5855 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5856 ((INSTANCE) == USART2) || \ 5857 ((INSTANCE) == USART3)) 5858 5859 /******************** UART Instances : Asynchronous mode **********************/ 5860 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5861 ((INSTANCE) == USART2) || \ 5862 ((INSTANCE) == USART3)) 5863 5864 /******************** UART Instances : Half-Duplex mode **********************/ 5865 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5866 ((INSTANCE) == USART2) || \ 5867 ((INSTANCE) == USART3)) 5868 5869 /******************** UART Instances : LIN mode **********************/ 5870 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5871 ((INSTANCE) == USART2) || \ 5872 ((INSTANCE) == USART3)) 5873 5874 /****************** UART Instances : Hardware Flow control ********************/ 5875 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5876 ((INSTANCE) == USART2) || \ 5877 ((INSTANCE) == USART3)) 5878 5879 /********************* UART Instances : Smard card mode ***********************/ 5880 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5881 ((INSTANCE) == USART2) || \ 5882 ((INSTANCE) == USART3)) 5883 5884 /*********************** UART Instances : IRDA mode ***************************/ 5885 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5886 ((INSTANCE) == USART2) || \ 5887 ((INSTANCE) == USART3)) 5888 5889 /***************** UART Instances : Multi-Processor mode **********************/ 5890 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5891 ((INSTANCE) == USART2) || \ 5892 ((INSTANCE) == USART3)) 5893 5894 /***************** UART Instances : DMA mode available **********************/ 5895 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 5896 ((INSTANCE) == USART2) || \ 5897 ((INSTANCE) == USART3)) 5898 5899 /****************************** RTC Instances *********************************/ 5900 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 5901 5902 /**************************** WWDG Instances *****************************/ 5903 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 5904 5905 5906 5907 5908 #define RCC_HSE_MIN 4000000U 5909 #define RCC_HSE_MAX 26000000U 5910 5911 #define RCC_MAX_FREQUENCY 24000000U 5912 5913 /** 5914 * @} 5915 */ 5916 /******************************************************************************/ 5917 /* For a painless codes migration between the STM32F1xx device product */ 5918 /* lines, the aliases defined below are put in place to overcome the */ 5919 /* differences in the interrupt handlers and IRQn definitions. */ 5920 /* No need to update developed interrupt code when moving across */ 5921 /* product lines within the same STM32F1 Family */ 5922 /******************************************************************************/ 5923 5924 /* Aliases for __IRQn */ 5925 #define ADC1_2_IRQn ADC1_IRQn 5926 #define USBWakeUp_IRQn CEC_IRQn 5927 #define OTG_FS_WKUP_IRQn CEC_IRQn 5928 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_TIM15_IRQn 5929 #define TIM9_IRQn TIM1_BRK_TIM15_IRQn 5930 #define TIM1_BRK_IRQn TIM1_BRK_TIM15_IRQn 5931 #define TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn 5932 #define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM17_IRQn 5933 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_TIM17_IRQn 5934 #define TIM1_UP_IRQn TIM1_UP_TIM16_IRQn 5935 #define TIM10_IRQn TIM1_UP_TIM16_IRQn 5936 #define TIM1_UP_TIM10_IRQn TIM1_UP_TIM16_IRQn 5937 #define TIM6_IRQn TIM6_DAC_IRQn 5938 5939 5940 /* Aliases for __IRQHandler */ 5941 #define ADC1_2_IRQHandler ADC1_IRQHandler 5942 #define USBWakeUp_IRQHandler CEC_IRQHandler 5943 #define OTG_FS_WKUP_IRQHandler CEC_IRQHandler 5944 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler 5945 #define TIM9_IRQHandler TIM1_BRK_TIM15_IRQHandler 5946 #define TIM1_BRK_IRQHandler TIM1_BRK_TIM15_IRQHandler 5947 #define TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 5948 #define TIM1_TRG_COM_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 5949 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler 5950 #define TIM1_UP_IRQHandler TIM1_UP_TIM16_IRQHandler 5951 #define TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler 5952 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_TIM16_IRQHandler 5953 #define TIM6_IRQHandler TIM6_DAC_IRQHandler 5954 5955 5956 /** 5957 * @} 5958 */ 5959 5960 /** 5961 * @} 5962 */ 5963 5964 5965 #ifdef __cplusplus 5966 } 5967 #endif /* __cplusplus */ 5968 5969 #endif /* __STM32F100xB_H */ 5970 5971 5972 5973
