1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_HSEM_H
21 #define STM32WLxx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_COREID COREID Defines
53 * @{
54 */
55 #define LL_HSEM_COREID_NONE 0U
56 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
57 #if defined(DUAL_CORE)
58 #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
59 #endif /* DUAL_CORE */
60 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT
61 /**
62 * @}
63 */
64
65
66 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
67 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
68 * @{
69 */
70
71 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
72 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
73 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
74 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
75 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
76 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
77 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
78 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
79 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
80 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
81 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
82 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
83 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
84 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
85 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
86 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
87 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
88 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
89 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
90 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
91 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
92 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
93 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
94 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
95 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
96 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
97 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
98 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
99 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
100 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
101 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
102 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
103 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
104 /**
105 * @}
106 */
107
108 /**
109 * @}
110 */
111
112 /* Exported macro ------------------------------------------------------------*/
113 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
114 * @{
115 */
116
117 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
118 * @{
119 */
120
121 /**
122 * @brief Write a value in HSEM register
123 * @param __INSTANCE__ HSEM Instance
124 * @param __REG__ Register to be written
125 * @param __VALUE__ Value to be written in the register
126 * @retval None
127 */
128 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
129
130 /**
131 * @brief Read a value in HSEM register
132 * @param __INSTANCE__ HSEM Instance
133 * @param __REG__ Register to be read
134 * @retval Register value
135 */
136 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
137 /**
138 * @}
139 */
140
141 /**
142 * @}
143 */
144
145 /* Exported functions --------------------------------------------------------*/
146 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
147 * @{
148 */
149
150 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
151 * @{
152 */
153
154
155 /**
156 * @brief Return 1 if the semaphore is locked, else return 0.
157 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
158 * @param HSEMx HSEM Instance.
159 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
160 * @retval State of bit (1 or 0).
161 */
LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef * HSEMx,uint32_t Semaphore)162 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
163 {
164 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
165 }
166
167 /**
168 * @brief Get core id.
169 * @rmtoll R COREID LL_HSEM_GetCoreId
170 * @param HSEMx HSEM Instance.
171 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
172 * @retval Returned value can be one of the following values:
173 * @arg @ref LL_HSEM_COREID_NONE
174 * @arg @ref LL_HSEM_COREID_CPU1
175 * @arg @ref LL_HSEM_COREID_CPU2
176 */
LL_HSEM_GetCoreId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)177 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
178 {
179 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
180 }
181
182 /**
183 * @brief Get process id.
184 * @rmtoll R PROCID LL_HSEM_GetProcessId
185 * @param HSEMx HSEM Instance.
186 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
187 * @retval Process number. Value between Min_Data=0 and Max_Data=255
188 */
LL_HSEM_GetProcessId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)189 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
190 {
191 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
192 }
193
194 /**
195 * @brief Get the lock by writing in R register.
196 * @note The R register has to be read to determined if the lock is taken.
197 * @rmtoll R LOCK LL_HSEM_SetLock
198 * @rmtoll R COREID LL_HSEM_SetLock
199 * @rmtoll R PROCID LL_HSEM_SetLock
200 * @param HSEMx HSEM Instance.
201 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
202 * @param process Process id. Value between Min_Data=0 and Max_Data=255
203 * @retval None
204 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)205 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
206 {
207 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
208 }
209
210 /**
211 * @brief Get the lock with 2-step lock.
212 * @rmtoll R LOCK LL_HSEM_2StepLock
213 * @rmtoll R COREID LL_HSEM_2StepLock
214 * @rmtoll R PROCID LL_HSEM_2StepLock
215 * @param HSEMx HSEM Instance.
216 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
217 * @param process Process id. Value between Min_Data=0 and Max_Data=255
218 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
219 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)220 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
221 {
222 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
223 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
224 }
225
226 /**
227 * @brief Get the lock with 1-step lock.
228 * @rmtoll RLR LOCK LL_HSEM_1StepLock
229 * @rmtoll RLR COREID LL_HSEM_1StepLock
230 * @rmtoll RLR PROCID LL_HSEM_1StepLock
231 * @param HSEMx HSEM Instance.
232 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
233 * @retval 1 lock fail, 0 lock successful or already locked by same core
234 */
LL_HSEM_1StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore)235 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
236 {
237 return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
238 }
239
240 /**
241 * @brief Release the lock of the semaphore.
242 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
243 * @rmtoll R LOCK LL_HSEM_ReleaseLock
244 * @param HSEMx HSEM Instance.
245 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
246 * @param process Process number. Value between Min_Data=0 and Max_Data=255
247 * @retval None
248 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)249 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
250 {
251 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
252 }
253
254 /**
255 * @brief Get the lock status of the semaphore.
256 * @rmtoll R LOCK LL_HSEM_GetStatus
257 * @param HSEMx HSEM Instance.
258 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
259 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(HSEM_TypeDef * HSEMx,uint32_t Semaphore)260 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
261 {
262 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
263 }
264
265 /**
266 * @brief Set the key.
267 * @rmtoll KEYR KEY LL_HSEM_SetKey
268 * @param HSEMx HSEM Instance.
269 * @param key Key value.
270 * @retval None
271 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)272 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
273 {
274 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
275 }
276
277 /**
278 * @brief Get the key.
279 * @rmtoll KEYR KEY LL_HSEM_GetKey
280 * @param HSEMx HSEM Instance.
281 * @retval key to unlock all semaphore from the same core
282 */
LL_HSEM_GetKey(HSEM_TypeDef * HSEMx)283 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
284 {
285 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
286 }
287
288 /**
289 * @brief Release all semaphore with the same core id.
290 * @rmtoll CR KEY LL_HSEM_ResetAllLock
291 * @rmtoll CR SEC LL_HSEM_ResetAllLock
292 * @rmtoll CR PRIV LL_HSEM_ResetAllLock
293 * @param HSEMx HSEM Instance.
294 * @param key Key value.
295 * @param core This parameter can be one of the following values:
296 * @arg @ref LL_HSEM_COREID_CPU1
297 * @arg @ref LL_HSEM_COREID_CPU2
298 * @retval None
299 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core)300 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
301 {
302 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
303 }
304
305 /**
306 * @}
307 */
308
309 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
310 * @{
311 */
312
313 /**
314 * @brief Enable interrupt.
315 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER
316 * @param HSEMx HSEM Instance.
317 * @param SemaphoreMask This parameter can be a combination of the following values:
318 * @arg @ref LL_HSEM_SEMAPHORE_0
319 * @arg @ref LL_HSEM_SEMAPHORE_1
320 * @arg @ref LL_HSEM_SEMAPHORE_2
321 * @arg @ref LL_HSEM_SEMAPHORE_3
322 * @arg @ref LL_HSEM_SEMAPHORE_4
323 * @arg @ref LL_HSEM_SEMAPHORE_5
324 * @arg @ref LL_HSEM_SEMAPHORE_6
325 * @arg @ref LL_HSEM_SEMAPHORE_7
326 * @arg @ref LL_HSEM_SEMAPHORE_8
327 * @arg @ref LL_HSEM_SEMAPHORE_9
328 * @arg @ref LL_HSEM_SEMAPHORE_10
329 * @arg @ref LL_HSEM_SEMAPHORE_11
330 * @arg @ref LL_HSEM_SEMAPHORE_12
331 * @arg @ref LL_HSEM_SEMAPHORE_13
332 * @arg @ref LL_HSEM_SEMAPHORE_14
333 * @arg @ref LL_HSEM_SEMAPHORE_15
334 * @arg @ref LL_HSEM_SEMAPHORE_16
335 * @arg @ref LL_HSEM_SEMAPHORE_17
336 * @arg @ref LL_HSEM_SEMAPHORE_18
337 * @arg @ref LL_HSEM_SEMAPHORE_19
338 * @arg @ref LL_HSEM_SEMAPHORE_20
339 * @arg @ref LL_HSEM_SEMAPHORE_21
340 * @arg @ref LL_HSEM_SEMAPHORE_22
341 * @arg @ref LL_HSEM_SEMAPHORE_23
342 * @arg @ref LL_HSEM_SEMAPHORE_24
343 * @arg @ref LL_HSEM_SEMAPHORE_25
344 * @arg @ref LL_HSEM_SEMAPHORE_26
345 * @arg @ref LL_HSEM_SEMAPHORE_27
346 * @arg @ref LL_HSEM_SEMAPHORE_28
347 * @arg @ref LL_HSEM_SEMAPHORE_29
348 * @arg @ref LL_HSEM_SEMAPHORE_30
349 * @arg @ref LL_HSEM_SEMAPHORE_31
350 * @arg @ref LL_HSEM_SEMAPHORE_ALL
351 * @retval None
352 */
LL_HSEM_EnableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)353 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
354 {
355 SET_BIT(HSEMx->C1IER, SemaphoreMask);
356 }
357
358 /**
359 * @brief Disable interrupt.
360 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER
361 * @param HSEMx HSEM Instance.
362 * @param SemaphoreMask This parameter can be a combination of the following values:
363 * @arg @ref LL_HSEM_SEMAPHORE_0
364 * @arg @ref LL_HSEM_SEMAPHORE_1
365 * @arg @ref LL_HSEM_SEMAPHORE_2
366 * @arg @ref LL_HSEM_SEMAPHORE_3
367 * @arg @ref LL_HSEM_SEMAPHORE_4
368 * @arg @ref LL_HSEM_SEMAPHORE_5
369 * @arg @ref LL_HSEM_SEMAPHORE_6
370 * @arg @ref LL_HSEM_SEMAPHORE_7
371 * @arg @ref LL_HSEM_SEMAPHORE_8
372 * @arg @ref LL_HSEM_SEMAPHORE_9
373 * @arg @ref LL_HSEM_SEMAPHORE_10
374 * @arg @ref LL_HSEM_SEMAPHORE_11
375 * @arg @ref LL_HSEM_SEMAPHORE_12
376 * @arg @ref LL_HSEM_SEMAPHORE_13
377 * @arg @ref LL_HSEM_SEMAPHORE_14
378 * @arg @ref LL_HSEM_SEMAPHORE_15
379 * @arg @ref LL_HSEM_SEMAPHORE_16
380 * @arg @ref LL_HSEM_SEMAPHORE_17
381 * @arg @ref LL_HSEM_SEMAPHORE_18
382 * @arg @ref LL_HSEM_SEMAPHORE_19
383 * @arg @ref LL_HSEM_SEMAPHORE_20
384 * @arg @ref LL_HSEM_SEMAPHORE_21
385 * @arg @ref LL_HSEM_SEMAPHORE_22
386 * @arg @ref LL_HSEM_SEMAPHORE_23
387 * @arg @ref LL_HSEM_SEMAPHORE_24
388 * @arg @ref LL_HSEM_SEMAPHORE_25
389 * @arg @ref LL_HSEM_SEMAPHORE_26
390 * @arg @ref LL_HSEM_SEMAPHORE_27
391 * @arg @ref LL_HSEM_SEMAPHORE_28
392 * @arg @ref LL_HSEM_SEMAPHORE_29
393 * @arg @ref LL_HSEM_SEMAPHORE_30
394 * @arg @ref LL_HSEM_SEMAPHORE_31
395 * @arg @ref LL_HSEM_SEMAPHORE_ALL
396 * @retval None
397 */
LL_HSEM_DisableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)398 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
399 {
400 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
401 }
402
403 /**
404 * @brief Check if interrupt is enabled.
405 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
406 * @param HSEMx HSEM Instance.
407 * @param SemaphoreMask This parameter can be a combination of the following values:
408 * @arg @ref LL_HSEM_SEMAPHORE_0
409 * @arg @ref LL_HSEM_SEMAPHORE_1
410 * @arg @ref LL_HSEM_SEMAPHORE_2
411 * @arg @ref LL_HSEM_SEMAPHORE_3
412 * @arg @ref LL_HSEM_SEMAPHORE_4
413 * @arg @ref LL_HSEM_SEMAPHORE_5
414 * @arg @ref LL_HSEM_SEMAPHORE_6
415 * @arg @ref LL_HSEM_SEMAPHORE_7
416 * @arg @ref LL_HSEM_SEMAPHORE_8
417 * @arg @ref LL_HSEM_SEMAPHORE_9
418 * @arg @ref LL_HSEM_SEMAPHORE_10
419 * @arg @ref LL_HSEM_SEMAPHORE_11
420 * @arg @ref LL_HSEM_SEMAPHORE_12
421 * @arg @ref LL_HSEM_SEMAPHORE_13
422 * @arg @ref LL_HSEM_SEMAPHORE_14
423 * @arg @ref LL_HSEM_SEMAPHORE_15
424 * @arg @ref LL_HSEM_SEMAPHORE_16
425 * @arg @ref LL_HSEM_SEMAPHORE_17
426 * @arg @ref LL_HSEM_SEMAPHORE_18
427 * @arg @ref LL_HSEM_SEMAPHORE_19
428 * @arg @ref LL_HSEM_SEMAPHORE_20
429 * @arg @ref LL_HSEM_SEMAPHORE_21
430 * @arg @ref LL_HSEM_SEMAPHORE_22
431 * @arg @ref LL_HSEM_SEMAPHORE_23
432 * @arg @ref LL_HSEM_SEMAPHORE_24
433 * @arg @ref LL_HSEM_SEMAPHORE_25
434 * @arg @ref LL_HSEM_SEMAPHORE_26
435 * @arg @ref LL_HSEM_SEMAPHORE_27
436 * @arg @ref LL_HSEM_SEMAPHORE_28
437 * @arg @ref LL_HSEM_SEMAPHORE_29
438 * @arg @ref LL_HSEM_SEMAPHORE_30
439 * @arg @ref LL_HSEM_SEMAPHORE_31
440 * @arg @ref LL_HSEM_SEMAPHORE_ALL
441 * @retval State of bit (1 or 0).
442 */
LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)443 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
444 {
445 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
446 }
447
448 #if defined(DUAL_CORE)
449 /**
450 * @brief Enable interrupt.
451 * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER
452 * @param HSEMx HSEM Instance.
453 * @param SemaphoreMask This parameter can be a combination of the following values:
454 * @arg @ref LL_HSEM_SEMAPHORE_0
455 * @arg @ref LL_HSEM_SEMAPHORE_1
456 * @arg @ref LL_HSEM_SEMAPHORE_2
457 * @arg @ref LL_HSEM_SEMAPHORE_3
458 * @arg @ref LL_HSEM_SEMAPHORE_4
459 * @arg @ref LL_HSEM_SEMAPHORE_5
460 * @arg @ref LL_HSEM_SEMAPHORE_6
461 * @arg @ref LL_HSEM_SEMAPHORE_7
462 * @arg @ref LL_HSEM_SEMAPHORE_8
463 * @arg @ref LL_HSEM_SEMAPHORE_9
464 * @arg @ref LL_HSEM_SEMAPHORE_10
465 * @arg @ref LL_HSEM_SEMAPHORE_11
466 * @arg @ref LL_HSEM_SEMAPHORE_12
467 * @arg @ref LL_HSEM_SEMAPHORE_13
468 * @arg @ref LL_HSEM_SEMAPHORE_14
469 * @arg @ref LL_HSEM_SEMAPHORE_15
470 * @arg @ref LL_HSEM_SEMAPHORE_16
471 * @arg @ref LL_HSEM_SEMAPHORE_17
472 * @arg @ref LL_HSEM_SEMAPHORE_18
473 * @arg @ref LL_HSEM_SEMAPHORE_19
474 * @arg @ref LL_HSEM_SEMAPHORE_20
475 * @arg @ref LL_HSEM_SEMAPHORE_21
476 * @arg @ref LL_HSEM_SEMAPHORE_22
477 * @arg @ref LL_HSEM_SEMAPHORE_23
478 * @arg @ref LL_HSEM_SEMAPHORE_24
479 * @arg @ref LL_HSEM_SEMAPHORE_25
480 * @arg @ref LL_HSEM_SEMAPHORE_26
481 * @arg @ref LL_HSEM_SEMAPHORE_27
482 * @arg @ref LL_HSEM_SEMAPHORE_28
483 * @arg @ref LL_HSEM_SEMAPHORE_29
484 * @arg @ref LL_HSEM_SEMAPHORE_30
485 * @arg @ref LL_HSEM_SEMAPHORE_31
486 * @arg @ref LL_HSEM_SEMAPHORE_ALL
487 * @retval None
488 */
LL_HSEM_EnableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)489 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
490 {
491 SET_BIT(HSEMx->C2IER, SemaphoreMask);
492 }
493
494 /**
495 * @brief Disable interrupt.
496 * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER
497 * @param HSEMx HSEM Instance.
498 * @param SemaphoreMask This parameter can be a combination of the following values:
499 * @arg @ref LL_HSEM_SEMAPHORE_0
500 * @arg @ref LL_HSEM_SEMAPHORE_1
501 * @arg @ref LL_HSEM_SEMAPHORE_2
502 * @arg @ref LL_HSEM_SEMAPHORE_3
503 * @arg @ref LL_HSEM_SEMAPHORE_4
504 * @arg @ref LL_HSEM_SEMAPHORE_5
505 * @arg @ref LL_HSEM_SEMAPHORE_6
506 * @arg @ref LL_HSEM_SEMAPHORE_7
507 * @arg @ref LL_HSEM_SEMAPHORE_8
508 * @arg @ref LL_HSEM_SEMAPHORE_9
509 * @arg @ref LL_HSEM_SEMAPHORE_10
510 * @arg @ref LL_HSEM_SEMAPHORE_11
511 * @arg @ref LL_HSEM_SEMAPHORE_12
512 * @arg @ref LL_HSEM_SEMAPHORE_13
513 * @arg @ref LL_HSEM_SEMAPHORE_14
514 * @arg @ref LL_HSEM_SEMAPHORE_15
515 * @arg @ref LL_HSEM_SEMAPHORE_16
516 * @arg @ref LL_HSEM_SEMAPHORE_17
517 * @arg @ref LL_HSEM_SEMAPHORE_18
518 * @arg @ref LL_HSEM_SEMAPHORE_19
519 * @arg @ref LL_HSEM_SEMAPHORE_20
520 * @arg @ref LL_HSEM_SEMAPHORE_21
521 * @arg @ref LL_HSEM_SEMAPHORE_22
522 * @arg @ref LL_HSEM_SEMAPHORE_23
523 * @arg @ref LL_HSEM_SEMAPHORE_24
524 * @arg @ref LL_HSEM_SEMAPHORE_25
525 * @arg @ref LL_HSEM_SEMAPHORE_26
526 * @arg @ref LL_HSEM_SEMAPHORE_27
527 * @arg @ref LL_HSEM_SEMAPHORE_28
528 * @arg @ref LL_HSEM_SEMAPHORE_29
529 * @arg @ref LL_HSEM_SEMAPHORE_30
530 * @arg @ref LL_HSEM_SEMAPHORE_31
531 * @arg @ref LL_HSEM_SEMAPHORE_ALL
532 * @retval None
533 */
LL_HSEM_DisableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)534 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
535 {
536 CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
537 }
538
539 /**
540 * @brief Check if interrupt is enabled.
541 * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER
542 * @param HSEMx HSEM Instance.
543 * @param SemaphoreMask This parameter can be a combination of the following values:
544 * @arg @ref LL_HSEM_SEMAPHORE_0
545 * @arg @ref LL_HSEM_SEMAPHORE_1
546 * @arg @ref LL_HSEM_SEMAPHORE_2
547 * @arg @ref LL_HSEM_SEMAPHORE_3
548 * @arg @ref LL_HSEM_SEMAPHORE_4
549 * @arg @ref LL_HSEM_SEMAPHORE_5
550 * @arg @ref LL_HSEM_SEMAPHORE_6
551 * @arg @ref LL_HSEM_SEMAPHORE_7
552 * @arg @ref LL_HSEM_SEMAPHORE_8
553 * @arg @ref LL_HSEM_SEMAPHORE_9
554 * @arg @ref LL_HSEM_SEMAPHORE_10
555 * @arg @ref LL_HSEM_SEMAPHORE_11
556 * @arg @ref LL_HSEM_SEMAPHORE_12
557 * @arg @ref LL_HSEM_SEMAPHORE_13
558 * @arg @ref LL_HSEM_SEMAPHORE_14
559 * @arg @ref LL_HSEM_SEMAPHORE_15
560 * @arg @ref LL_HSEM_SEMAPHORE_16
561 * @arg @ref LL_HSEM_SEMAPHORE_17
562 * @arg @ref LL_HSEM_SEMAPHORE_18
563 * @arg @ref LL_HSEM_SEMAPHORE_19
564 * @arg @ref LL_HSEM_SEMAPHORE_20
565 * @arg @ref LL_HSEM_SEMAPHORE_21
566 * @arg @ref LL_HSEM_SEMAPHORE_22
567 * @arg @ref LL_HSEM_SEMAPHORE_23
568 * @arg @ref LL_HSEM_SEMAPHORE_24
569 * @arg @ref LL_HSEM_SEMAPHORE_25
570 * @arg @ref LL_HSEM_SEMAPHORE_26
571 * @arg @ref LL_HSEM_SEMAPHORE_27
572 * @arg @ref LL_HSEM_SEMAPHORE_28
573 * @arg @ref LL_HSEM_SEMAPHORE_29
574 * @arg @ref LL_HSEM_SEMAPHORE_30
575 * @arg @ref LL_HSEM_SEMAPHORE_31
576 * @arg @ref LL_HSEM_SEMAPHORE_ALL
577 * @retval State of bit (1 or 0).
578 */
LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)579 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
580 {
581 return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
582 }
583 #endif /* DUAL_CORE */
584
585 /**
586 * @}
587 */
588
589 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
590 * @{
591 */
592
593 /**
594 * @brief Clear interrupt status.
595 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
596 * @param HSEMx HSEM Instance.
597 * @param SemaphoreMask This parameter can be a combination of the following values:
598 * @arg @ref LL_HSEM_SEMAPHORE_0
599 * @arg @ref LL_HSEM_SEMAPHORE_1
600 * @arg @ref LL_HSEM_SEMAPHORE_2
601 * @arg @ref LL_HSEM_SEMAPHORE_3
602 * @arg @ref LL_HSEM_SEMAPHORE_4
603 * @arg @ref LL_HSEM_SEMAPHORE_5
604 * @arg @ref LL_HSEM_SEMAPHORE_6
605 * @arg @ref LL_HSEM_SEMAPHORE_7
606 * @arg @ref LL_HSEM_SEMAPHORE_8
607 * @arg @ref LL_HSEM_SEMAPHORE_9
608 * @arg @ref LL_HSEM_SEMAPHORE_10
609 * @arg @ref LL_HSEM_SEMAPHORE_11
610 * @arg @ref LL_HSEM_SEMAPHORE_12
611 * @arg @ref LL_HSEM_SEMAPHORE_13
612 * @arg @ref LL_HSEM_SEMAPHORE_14
613 * @arg @ref LL_HSEM_SEMAPHORE_15
614 * @arg @ref LL_HSEM_SEMAPHORE_16
615 * @arg @ref LL_HSEM_SEMAPHORE_17
616 * @arg @ref LL_HSEM_SEMAPHORE_18
617 * @arg @ref LL_HSEM_SEMAPHORE_19
618 * @arg @ref LL_HSEM_SEMAPHORE_20
619 * @arg @ref LL_HSEM_SEMAPHORE_21
620 * @arg @ref LL_HSEM_SEMAPHORE_22
621 * @arg @ref LL_HSEM_SEMAPHORE_23
622 * @arg @ref LL_HSEM_SEMAPHORE_24
623 * @arg @ref LL_HSEM_SEMAPHORE_25
624 * @arg @ref LL_HSEM_SEMAPHORE_26
625 * @arg @ref LL_HSEM_SEMAPHORE_27
626 * @arg @ref LL_HSEM_SEMAPHORE_28
627 * @arg @ref LL_HSEM_SEMAPHORE_29
628 * @arg @ref LL_HSEM_SEMAPHORE_30
629 * @arg @ref LL_HSEM_SEMAPHORE_31
630 * @arg @ref LL_HSEM_SEMAPHORE_ALL
631 * @retval None
632 */
LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)633 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
634 {
635 WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
636 }
637
638 /**
639 * @brief Get interrupt status from ISR register.
640 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
641 * @param HSEMx HSEM Instance.
642 * @param SemaphoreMask This parameter can be a combination of the following values:
643 * @arg @ref LL_HSEM_SEMAPHORE_0
644 * @arg @ref LL_HSEM_SEMAPHORE_1
645 * @arg @ref LL_HSEM_SEMAPHORE_2
646 * @arg @ref LL_HSEM_SEMAPHORE_3
647 * @arg @ref LL_HSEM_SEMAPHORE_4
648 * @arg @ref LL_HSEM_SEMAPHORE_5
649 * @arg @ref LL_HSEM_SEMAPHORE_6
650 * @arg @ref LL_HSEM_SEMAPHORE_7
651 * @arg @ref LL_HSEM_SEMAPHORE_8
652 * @arg @ref LL_HSEM_SEMAPHORE_9
653 * @arg @ref LL_HSEM_SEMAPHORE_10
654 * @arg @ref LL_HSEM_SEMAPHORE_11
655 * @arg @ref LL_HSEM_SEMAPHORE_12
656 * @arg @ref LL_HSEM_SEMAPHORE_13
657 * @arg @ref LL_HSEM_SEMAPHORE_14
658 * @arg @ref LL_HSEM_SEMAPHORE_15
659 * @arg @ref LL_HSEM_SEMAPHORE_16
660 * @arg @ref LL_HSEM_SEMAPHORE_17
661 * @arg @ref LL_HSEM_SEMAPHORE_18
662 * @arg @ref LL_HSEM_SEMAPHORE_19
663 * @arg @ref LL_HSEM_SEMAPHORE_20
664 * @arg @ref LL_HSEM_SEMAPHORE_21
665 * @arg @ref LL_HSEM_SEMAPHORE_22
666 * @arg @ref LL_HSEM_SEMAPHORE_23
667 * @arg @ref LL_HSEM_SEMAPHORE_24
668 * @arg @ref LL_HSEM_SEMAPHORE_25
669 * @arg @ref LL_HSEM_SEMAPHORE_26
670 * @arg @ref LL_HSEM_SEMAPHORE_27
671 * @arg @ref LL_HSEM_SEMAPHORE_28
672 * @arg @ref LL_HSEM_SEMAPHORE_29
673 * @arg @ref LL_HSEM_SEMAPHORE_30
674 * @arg @ref LL_HSEM_SEMAPHORE_31
675 * @arg @ref LL_HSEM_SEMAPHORE_ALL
676 * @retval State of bit (1 or 0).
677 */
LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)678 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
679 {
680 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
681 }
682
683 /**
684 * @brief Get interrupt status from MISR register.
685 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
686 * @param HSEMx HSEM Instance.
687 * @param SemaphoreMask This parameter can be a combination of the following values:
688 * @arg @ref LL_HSEM_SEMAPHORE_0
689 * @arg @ref LL_HSEM_SEMAPHORE_1
690 * @arg @ref LL_HSEM_SEMAPHORE_2
691 * @arg @ref LL_HSEM_SEMAPHORE_3
692 * @arg @ref LL_HSEM_SEMAPHORE_4
693 * @arg @ref LL_HSEM_SEMAPHORE_5
694 * @arg @ref LL_HSEM_SEMAPHORE_6
695 * @arg @ref LL_HSEM_SEMAPHORE_7
696 * @arg @ref LL_HSEM_SEMAPHORE_8
697 * @arg @ref LL_HSEM_SEMAPHORE_9
698 * @arg @ref LL_HSEM_SEMAPHORE_10
699 * @arg @ref LL_HSEM_SEMAPHORE_11
700 * @arg @ref LL_HSEM_SEMAPHORE_12
701 * @arg @ref LL_HSEM_SEMAPHORE_13
702 * @arg @ref LL_HSEM_SEMAPHORE_14
703 * @arg @ref LL_HSEM_SEMAPHORE_15
704 * @arg @ref LL_HSEM_SEMAPHORE_16
705 * @arg @ref LL_HSEM_SEMAPHORE_17
706 * @arg @ref LL_HSEM_SEMAPHORE_18
707 * @arg @ref LL_HSEM_SEMAPHORE_19
708 * @arg @ref LL_HSEM_SEMAPHORE_20
709 * @arg @ref LL_HSEM_SEMAPHORE_21
710 * @arg @ref LL_HSEM_SEMAPHORE_22
711 * @arg @ref LL_HSEM_SEMAPHORE_23
712 * @arg @ref LL_HSEM_SEMAPHORE_24
713 * @arg @ref LL_HSEM_SEMAPHORE_25
714 * @arg @ref LL_HSEM_SEMAPHORE_26
715 * @arg @ref LL_HSEM_SEMAPHORE_27
716 * @arg @ref LL_HSEM_SEMAPHORE_28
717 * @arg @ref LL_HSEM_SEMAPHORE_29
718 * @arg @ref LL_HSEM_SEMAPHORE_30
719 * @arg @ref LL_HSEM_SEMAPHORE_31
720 * @arg @ref LL_HSEM_SEMAPHORE_ALL
721 * @retval State of bit (1 or 0).
722 */
LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)723 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
724 {
725 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
726 }
727
728 #if defined(DUAL_CORE)
729 /**
730 * @brief Clear interrupt status.
731 * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR
732 * @param HSEMx HSEM Instance.
733 * @param SemaphoreMask This parameter can be a combination of the following values:
734 * @arg @ref LL_HSEM_SEMAPHORE_0
735 * @arg @ref LL_HSEM_SEMAPHORE_1
736 * @arg @ref LL_HSEM_SEMAPHORE_2
737 * @arg @ref LL_HSEM_SEMAPHORE_3
738 * @arg @ref LL_HSEM_SEMAPHORE_4
739 * @arg @ref LL_HSEM_SEMAPHORE_5
740 * @arg @ref LL_HSEM_SEMAPHORE_6
741 * @arg @ref LL_HSEM_SEMAPHORE_7
742 * @arg @ref LL_HSEM_SEMAPHORE_8
743 * @arg @ref LL_HSEM_SEMAPHORE_9
744 * @arg @ref LL_HSEM_SEMAPHORE_10
745 * @arg @ref LL_HSEM_SEMAPHORE_11
746 * @arg @ref LL_HSEM_SEMAPHORE_12
747 * @arg @ref LL_HSEM_SEMAPHORE_13
748 * @arg @ref LL_HSEM_SEMAPHORE_14
749 * @arg @ref LL_HSEM_SEMAPHORE_15
750 * @arg @ref LL_HSEM_SEMAPHORE_16
751 * @arg @ref LL_HSEM_SEMAPHORE_17
752 * @arg @ref LL_HSEM_SEMAPHORE_18
753 * @arg @ref LL_HSEM_SEMAPHORE_19
754 * @arg @ref LL_HSEM_SEMAPHORE_20
755 * @arg @ref LL_HSEM_SEMAPHORE_21
756 * @arg @ref LL_HSEM_SEMAPHORE_22
757 * @arg @ref LL_HSEM_SEMAPHORE_23
758 * @arg @ref LL_HSEM_SEMAPHORE_24
759 * @arg @ref LL_HSEM_SEMAPHORE_25
760 * @arg @ref LL_HSEM_SEMAPHORE_26
761 * @arg @ref LL_HSEM_SEMAPHORE_27
762 * @arg @ref LL_HSEM_SEMAPHORE_28
763 * @arg @ref LL_HSEM_SEMAPHORE_29
764 * @arg @ref LL_HSEM_SEMAPHORE_30
765 * @arg @ref LL_HSEM_SEMAPHORE_31
766 * @arg @ref LL_HSEM_SEMAPHORE_ALL
767 * @retval None
768 */
LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)769 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
770 {
771 WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
772 }
773
774 /**
775 * @brief Get interrupt status from ISR register.
776 * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR
777 * @param HSEMx HSEM Instance.
778 * @param SemaphoreMask This parameter can be a combination of the following values:
779 * @arg @ref LL_HSEM_SEMAPHORE_0
780 * @arg @ref LL_HSEM_SEMAPHORE_1
781 * @arg @ref LL_HSEM_SEMAPHORE_2
782 * @arg @ref LL_HSEM_SEMAPHORE_3
783 * @arg @ref LL_HSEM_SEMAPHORE_4
784 * @arg @ref LL_HSEM_SEMAPHORE_5
785 * @arg @ref LL_HSEM_SEMAPHORE_6
786 * @arg @ref LL_HSEM_SEMAPHORE_7
787 * @arg @ref LL_HSEM_SEMAPHORE_8
788 * @arg @ref LL_HSEM_SEMAPHORE_9
789 * @arg @ref LL_HSEM_SEMAPHORE_10
790 * @arg @ref LL_HSEM_SEMAPHORE_11
791 * @arg @ref LL_HSEM_SEMAPHORE_12
792 * @arg @ref LL_HSEM_SEMAPHORE_13
793 * @arg @ref LL_HSEM_SEMAPHORE_14
794 * @arg @ref LL_HSEM_SEMAPHORE_15
795 * @arg @ref LL_HSEM_SEMAPHORE_16
796 * @arg @ref LL_HSEM_SEMAPHORE_17
797 * @arg @ref LL_HSEM_SEMAPHORE_18
798 * @arg @ref LL_HSEM_SEMAPHORE_19
799 * @arg @ref LL_HSEM_SEMAPHORE_20
800 * @arg @ref LL_HSEM_SEMAPHORE_21
801 * @arg @ref LL_HSEM_SEMAPHORE_22
802 * @arg @ref LL_HSEM_SEMAPHORE_23
803 * @arg @ref LL_HSEM_SEMAPHORE_24
804 * @arg @ref LL_HSEM_SEMAPHORE_25
805 * @arg @ref LL_HSEM_SEMAPHORE_26
806 * @arg @ref LL_HSEM_SEMAPHORE_27
807 * @arg @ref LL_HSEM_SEMAPHORE_28
808 * @arg @ref LL_HSEM_SEMAPHORE_29
809 * @arg @ref LL_HSEM_SEMAPHORE_30
810 * @arg @ref LL_HSEM_SEMAPHORE_31
811 * @arg @ref LL_HSEM_SEMAPHORE_ALL
812 * @retval State of bit (1 or 0).
813 */
LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)814 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
815 {
816 return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
817 }
818
819 /**
820 * @brief Get interrupt status from MISR register.
821 * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR
822 * @param HSEMx HSEM Instance.
823 * @param SemaphoreMask This parameter can be a combination of the following values:
824 * @arg @ref LL_HSEM_SEMAPHORE_0
825 * @arg @ref LL_HSEM_SEMAPHORE_1
826 * @arg @ref LL_HSEM_SEMAPHORE_2
827 * @arg @ref LL_HSEM_SEMAPHORE_3
828 * @arg @ref LL_HSEM_SEMAPHORE_4
829 * @arg @ref LL_HSEM_SEMAPHORE_5
830 * @arg @ref LL_HSEM_SEMAPHORE_6
831 * @arg @ref LL_HSEM_SEMAPHORE_7
832 * @arg @ref LL_HSEM_SEMAPHORE_8
833 * @arg @ref LL_HSEM_SEMAPHORE_9
834 * @arg @ref LL_HSEM_SEMAPHORE_10
835 * @arg @ref LL_HSEM_SEMAPHORE_11
836 * @arg @ref LL_HSEM_SEMAPHORE_12
837 * @arg @ref LL_HSEM_SEMAPHORE_13
838 * @arg @ref LL_HSEM_SEMAPHORE_14
839 * @arg @ref LL_HSEM_SEMAPHORE_15
840 * @arg @ref LL_HSEM_SEMAPHORE_16
841 * @arg @ref LL_HSEM_SEMAPHORE_17
842 * @arg @ref LL_HSEM_SEMAPHORE_18
843 * @arg @ref LL_HSEM_SEMAPHORE_19
844 * @arg @ref LL_HSEM_SEMAPHORE_20
845 * @arg @ref LL_HSEM_SEMAPHORE_21
846 * @arg @ref LL_HSEM_SEMAPHORE_22
847 * @arg @ref LL_HSEM_SEMAPHORE_23
848 * @arg @ref LL_HSEM_SEMAPHORE_24
849 * @arg @ref LL_HSEM_SEMAPHORE_25
850 * @arg @ref LL_HSEM_SEMAPHORE_26
851 * @arg @ref LL_HSEM_SEMAPHORE_27
852 * @arg @ref LL_HSEM_SEMAPHORE_28
853 * @arg @ref LL_HSEM_SEMAPHORE_29
854 * @arg @ref LL_HSEM_SEMAPHORE_30
855 * @arg @ref LL_HSEM_SEMAPHORE_31
856 * @arg @ref LL_HSEM_SEMAPHORE_ALL
857 * @retval State of bit (1 or 0).
858 */
LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)859 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
860 {
861 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
862 }
863 #endif /* DUAL_CORE */
864 /**
865 * @}
866 */
867
868 /**
869 * @}
870 */
871
872 /**
873 * @}
874 */
875
876 #endif /* defined(HSEM) */
877
878 /**
879 * @}
880 */
881
882 #ifdef __cplusplus
883 }
884 #endif
885
886 #endif /* __STM32WLxx_LL_HSEM_H */
887
