1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_DMA_H
21 #define STM32WLxx_LL_DMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29 #include "stm32wlxx_ll_dmamux.h"
30
31 /** @addtogroup STM32WLxx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMA1) || defined (DMA2)
36
37 /** @defgroup DMA_LL DMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
44 * @{
45 */
46 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
47 static const uint8_t CHANNEL_OFFSET_TAB[] =
48 {
49 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
50 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE),
56 };
57 /**
58 * @}
59 */
60
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
65 * @{
66 */
67 /**
68 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
69 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
70 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
71 * @param __DMA_INSTANCE__ DMAx
72 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0).
73 */
74 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
75 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7)
76 /**
77 * @}
78 */
79 /* Exported types ------------------------------------------------------------*/
80 #if defined(USE_FULL_LL_DRIVER)
81 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
82 * @{
83 */
84 typedef struct
85 {
86 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
87 or as Source base address in case of memory to memory transfer direction.
88
89 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
90
91 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
92 or as Destination base address in case of memory to memory transfer direction.
93
94 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
95
96 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
97 from memory to memory or from peripheral to memory.
98 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
99
100 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
101
102 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
103 This parameter can be a value of @ref DMA_LL_EC_MODE
104 @note: The circular buffer mode cannot be used if the memory to memory
105 data transfer direction is configured on the selected Channel
106
107 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
108
109 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref DMA_LL_EC_PERIPH
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
114
115 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
116 is incremented or not.
117 This parameter can be a value of @ref DMA_LL_EC_MEMORY
118
119 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
120
121 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
126
127 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
128 in case of memory to memory transfer direction.
129 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
130
131 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
132
133 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
134 The data unit is equal to the source buffer configuration set in PeripheralSize
135 or MemorySize parameters depending in the transfer direction.
136 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
137
138 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
139
140 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
141 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
142
143 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
144
145 uint32_t Priority; /*!< Specifies the channel priority level.
146 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
147
148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
149
150 } LL_DMA_InitTypeDef;
151 /**
152 * @}
153 */
154 #endif /*USE_FULL_LL_DRIVER*/
155
156 /* Exported constants --------------------------------------------------------*/
157 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
158 * @{
159 */
160 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
161 * @brief Flags defines which can be used with LL_DMA_WriteReg function
162 * @{
163 */
164 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
165 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
166 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
167 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
168 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
169 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
170 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
171 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
172 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
173 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
174 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
175 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
176 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
177 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
178 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
179 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
180 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
181 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
182 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
183 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
184 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
185 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
186 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
187 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
188 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
189 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
190 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
191 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
192 /**
193 * @}
194 */
195
196 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
197 * @brief Flags defines which can be used with LL_DMA_ReadReg function
198 * @{
199 */
200 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
201 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
202 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
203 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
204 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
205 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
206 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
207 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
208 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
209 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
210 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
211 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
212 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
213 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
214 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
215 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
216 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
217 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
218 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
219 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
220 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
221 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
222 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
223 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
224 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
225 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
226 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
227 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
228 /**
229 * @}
230 */
231
232 /** @defgroup DMA_LL_EC_IT IT Defines
233 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
234 * @{
235 */
236 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
237 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
238 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
239 /**
240 * @}
241 */
242
243 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
244 * @{
245 */
246 #define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
247 #define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
248 #define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
249 #define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
250 #define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
251 #define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
252 #define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
253 #if defined(USE_FULL_LL_DRIVER)
254 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
255 #endif /*USE_FULL_LL_DRIVER*/
256 /**
257 * @}
258 */
259
260 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
261 * @{
262 */
263 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
264 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
265 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
266 /**
267 * @}
268 */
269
270 /** @defgroup DMA_LL_EC_MODE Transfer mode
271 * @{
272 */
273 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
274 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
275 /**
276 * @}
277 */
278
279 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
280 * @{
281 */
282 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
283 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
284 /**
285 * @}
286 */
287
288 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
289 * @{
290 */
291 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
292 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
293 /**
294 * @}
295 */
296
297 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
298 * @{
299 */
300 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
301 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
302 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
303 /**
304 * @}
305 */
306
307 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
308 * @{
309 */
310 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
311 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
312 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
313 /**
314 * @}
315 */
316
317 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
318 * @{
319 */
320 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
321 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
322 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
323 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
324 /**
325 * @}
326 */
327
328 #if defined(DMA_CCR_SECM)
329 /** @defgroup DMA_LL_CHANNEL_SEC_MODE CHANNEL SECURITY MODE
330 * @{
331 */
332 #define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< Disable secure DMA channel */
333 #define LL_DMA_CHANNEL_SEC DMA_CCR_SECM /*!< Enable secure DMA channel */
334 /**
335 * @}
336 */
337
338 #if defined (CORE_CM0PLUS)
339 /** @defgroup DMA_LL_SOURCE_TRANSFER_SEC_MODE TRANSFER SECURITY SOURCE MODE
340 * @{
341 */
342 #define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< Disable secure DMA transfer from the source */
343 #define LL_DMA_CHANNEL_SRC_SEC DMA_CCR_SSEC /*!< Enable secure DMA transfer from the source */
344 /**
345 * @}
346 */
347
348 /** @defgroup DMA_LL_DEST_TRANSFER_SEC_MODE TRANSFER SECURITY DESTINATION MODE
349 * @{
350 */
351 #define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< Disable secure DMA transfer to the destination */
352 #define LL_DMA_CHANNEL_DEST_SEC DMA_CCR_DSEC /*!< Enable secure DMA transfer to the destination */
353 /**
354 * @}
355 */
356 #endif /* CORE_CM0PLUS */
357
358 #endif /* DMA_CCR_SECM */
359 #if defined(DMA_CCR_PRIV)
360 /** @defgroup DMA_LL_SEC_PRIVILEGE_MODE PRIVILEGE MODE
361 * @{
362 */
363 #define LL_DMA_CHANNEL_NPRIV 0x00000000U /*!< Disable privilege */
364 #define LL_DMA_CHANNEL_PRIV DMA_CCR_PRIV /*!< Enable privilege */
365 /**
366 * @}
367 */
368
369 #endif /* DMA_CCR_PRIV */
370 /**
371 * @}
372 */
373
374 /* Exported macro ------------------------------------------------------------*/
375 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
376 * @{
377 */
378
379 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
380 * @{
381 */
382 /**
383 * @brief Write a value in DMA register
384 * @param __INSTANCE__ DMA Instance
385 * @param __REG__ Register to be written
386 * @param __VALUE__ Value to be written in the register
387 * @retval None
388 */
389 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
390
391 /**
392 * @brief Read a value in DMA register
393 * @param __INSTANCE__ DMA Instance
394 * @param __REG__ Register to be read
395 * @retval Register value
396 */
397 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
398 /**
399 * @}
400 */
401
402 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
403 * @{
404 */
405 /**
406 * @brief Convert DMAx_Channely into DMAx
407 * @param __CHANNEL_INSTANCE__ DMAx_Channely
408 * @retval DMAx
409 */
410 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
411 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
412
413 /**
414 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
415 * @param __CHANNEL_INSTANCE__ DMAx_Channely
416 * @retval LL_DMA_CHANNEL_y
417 */
418 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
419 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
431 LL_DMA_CHANNEL_7)
432
433 /**
434 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
435 * @param __DMA_INSTANCE__ DMAx
436 * @param __CHANNEL__ LL_DMA_CHANNEL_y
437 * @retval DMAx_Channely
438 */
439 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
440 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
449 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
450 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
451 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
452 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
453 DMA2_Channel7)
454
455 /**
456 * @}
457 */
458
459 /**
460 * @}
461 */
462
463 /* Exported functions --------------------------------------------------------*/
464 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
465 * @{
466 */
467
468 /** @defgroup DMA_LL_EF_Configuration Configuration
469 * @{
470 */
471 /**
472 * @brief Enable DMA channel.
473 * @rmtoll CCR EN LL_DMA_EnableChannel
474 * @param DMAx DMAx Instance
475 * @param Channel This parameter can be one of the following values:
476 * @arg @ref LL_DMA_CHANNEL_1
477 * @arg @ref LL_DMA_CHANNEL_2
478 * @arg @ref LL_DMA_CHANNEL_3
479 * @arg @ref LL_DMA_CHANNEL_4
480 * @arg @ref LL_DMA_CHANNEL_5
481 * @arg @ref LL_DMA_CHANNEL_6
482 * @arg @ref LL_DMA_CHANNEL_7
483 * @retval None
484 */
LL_DMA_EnableChannel(DMA_TypeDef * DMAx,uint32_t Channel)485 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
486 {
487 uint32_t dma_base_addr = (uint32_t)DMAx;
488 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
489 }
490
491 /**
492 * @brief Disable DMA channel.
493 * @rmtoll CCR EN LL_DMA_DisableChannel
494 * @param DMAx DMAx Instance
495 * @param Channel This parameter can be one of the following values:
496 * @arg @ref LL_DMA_CHANNEL_1
497 * @arg @ref LL_DMA_CHANNEL_2
498 * @arg @ref LL_DMA_CHANNEL_3
499 * @arg @ref LL_DMA_CHANNEL_4
500 * @arg @ref LL_DMA_CHANNEL_5
501 * @arg @ref LL_DMA_CHANNEL_6
502 * @arg @ref LL_DMA_CHANNEL_7
503 * @retval None
504 */
LL_DMA_DisableChannel(DMA_TypeDef * DMAx,uint32_t Channel)505 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
506 {
507 uint32_t dma_base_addr = (uint32_t)DMAx;
508 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN);
509 }
510
511 /**
512 * @brief Check if DMA channel is enabled or disabled.
513 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
514 * @param DMAx DMAx Instance
515 * @param Channel This parameter can be one of the following values:
516 * @arg @ref LL_DMA_CHANNEL_1
517 * @arg @ref LL_DMA_CHANNEL_2
518 * @arg @ref LL_DMA_CHANNEL_3
519 * @arg @ref LL_DMA_CHANNEL_4
520 * @arg @ref LL_DMA_CHANNEL_5
521 * @arg @ref LL_DMA_CHANNEL_6
522 * @arg @ref LL_DMA_CHANNEL_7
523 * @retval State of bit (1 or 0).
524 */
LL_DMA_IsEnabledChannel(DMA_TypeDef * DMAx,uint32_t Channel)525 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
526 {
527 uint32_t dma_base_addr = (uint32_t)DMAx;
528 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
529 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
530 }
531
532 #if defined(DMA_CCR_SECM)
533 #if defined (CORE_CM0PLUS)
534 /**
535 * @brief Configure all secure parameters link to DMA transfer.
536 * @rmtoll CCR SECM LL_DMA_ConfigChannelSecure\n
537 * CCR SSEC LL_DMA_ConfigChannelSecure\n
538 * CCR DSEC LL_DMA_ConfigChannelSecure\n
539 * @param DMAx DMAx Instance
540 * @param Channel This parameter can be one of the following values:
541 * @arg @ref LL_DMA_CHANNEL_1
542 * @arg @ref LL_DMA_CHANNEL_2
543 * @arg @ref LL_DMA_CHANNEL_3
544 * @arg @ref LL_DMA_CHANNEL_4
545 * @arg @ref LL_DMA_CHANNEL_5
546 * @arg @ref LL_DMA_CHANNEL_6
547 * @arg @ref LL_DMA_CHANNEL_7
548 * @param Configuration This parameter must be a combination of all the following values:
549 * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC
550 * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC
551 * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC
552 * @retval None
553 */
LL_DMA_ConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)554 __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
555 {
556 uint32_t dma_base_addr = (uint32_t)DMAx;
557 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel])))->CCR,
558 DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC,
559 Configuration);
560 }
561
562 /**
563 * @brief Get the configuration of a secure channel.
564 * @rmtoll CCR SECM LL_DMA_GetConfigChannelSecure\n
565 * CCR SSEC LL_DMA_GetConfigChannelSecure\n
566 * CCR DSEC LL_DMA_GetConfigChannelSecure\n
567 * @param DMAx DMAx Instance
568 * @param Channel This parameter can be one of the following values:
569 * @arg @ref LL_DMA_CHANNEL_1
570 * @arg @ref LL_DMA_CHANNEL_2
571 * @arg @ref LL_DMA_CHANNEL_3
572 * @arg @ref LL_DMA_CHANNEL_4
573 * @arg @ref LL_DMA_CHANNEL_5
574 * @arg @ref LL_DMA_CHANNEL_6
575 * @arg @ref LL_DMA_CHANNEL_7
576 * @retval Configuration This parameter must be a combination of all the following values:
577 * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC
578 * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC
579 * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC
580 */
LL_DMA_GetConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)581 __STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
582 {
583 uint32_t dma_base_addr = (uint32_t)DMAx;
584 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
585 DMA_CCR_SECM | DMA_CCR_SSEC | DMA_CCR_DSEC));
586 }
587 #else
588 /**
589 * @brief Get the configuration of a secure channel.
590 * @rmtoll CCR SECM LL_DMA_GetConfigChannelSecure\n
591 * @param DMAx DMAx Instance
592 * @param Channel This parameter can be one of the following values:
593 * @arg @ref LL_DMA_CHANNEL_1
594 * @arg @ref LL_DMA_CHANNEL_2
595 * @arg @ref LL_DMA_CHANNEL_3
596 * @arg @ref LL_DMA_CHANNEL_4
597 * @arg @ref LL_DMA_CHANNEL_5
598 * @arg @ref LL_DMA_CHANNEL_6
599 * @arg @ref LL_DMA_CHANNEL_7
600 * @retval Configuration This parameter must be a combination of all the following values:
601 * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC
602 */
LL_DMA_GetConfigChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)603 __STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
604 {
605 uint32_t dma_base_addr = (uint32_t)DMAx;
606 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
607 DMA_CCR_SECM));
608 }
609 #endif /* CORE_CM0PLUS */
610
611 #endif /* DMA_CCR_SECM */
612 /**
613 * @brief Configure all parameters link to DMA transfer.
614 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
615 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
616 * CCR CIRC LL_DMA_ConfigTransfer\n
617 * CCR PINC LL_DMA_ConfigTransfer\n
618 * CCR MINC LL_DMA_ConfigTransfer\n
619 * CCR PSIZE LL_DMA_ConfigTransfer\n
620 * CCR MSIZE LL_DMA_ConfigTransfer\n
621 * CCR PL LL_DMA_ConfigTransfer
622 * @param DMAx DMAx Instance
623 * @param Channel This parameter can be one of the following values:
624 * @arg @ref LL_DMA_CHANNEL_1
625 * @arg @ref LL_DMA_CHANNEL_2
626 * @arg @ref LL_DMA_CHANNEL_3
627 * @arg @ref LL_DMA_CHANNEL_4
628 * @arg @ref LL_DMA_CHANNEL_5
629 * @arg @ref LL_DMA_CHANNEL_6
630 * @arg @ref LL_DMA_CHANNEL_7
631 * @param Configuration This parameter must be a combination of all the following values:
632 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
633 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
634 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
635 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
636 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
637 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
638 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
639 * @retval None
640 */
LL_DMA_ConfigTransfer(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Configuration)641 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
642 {
643 uint32_t dma_base_addr = (uint32_t)DMAx;
644 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
645 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
646 Configuration);
647 }
648
649 /**
650 * @brief Set Data transfer direction (read from peripheral or from memory).
651 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
652 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
653 * @param DMAx DMAx Instance
654 * @param Channel This parameter can be one of the following values:
655 * @arg @ref LL_DMA_CHANNEL_1
656 * @arg @ref LL_DMA_CHANNEL_2
657 * @arg @ref LL_DMA_CHANNEL_3
658 * @arg @ref LL_DMA_CHANNEL_4
659 * @arg @ref LL_DMA_CHANNEL_5
660 * @arg @ref LL_DMA_CHANNEL_6
661 * @arg @ref LL_DMA_CHANNEL_7
662 * @param Direction This parameter can be one of the following values:
663 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
664 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
665 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
666 * @retval None
667 */
LL_DMA_SetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Direction)668 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
669 {
670 uint32_t dma_base_addr = (uint32_t)DMAx;
671 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
672 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
673 }
674
675 /**
676 * @brief Get Data transfer direction (read from peripheral or from memory).
677 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
678 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
679 * @param DMAx DMAx Instance
680 * @param Channel This parameter can be one of the following values:
681 * @arg @ref LL_DMA_CHANNEL_1
682 * @arg @ref LL_DMA_CHANNEL_2
683 * @arg @ref LL_DMA_CHANNEL_3
684 * @arg @ref LL_DMA_CHANNEL_4
685 * @arg @ref LL_DMA_CHANNEL_5
686 * @arg @ref LL_DMA_CHANNEL_6
687 * @arg @ref LL_DMA_CHANNEL_7
688 * @retval Returned value can be one of the following values:
689 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
690 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
691 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
692 */
LL_DMA_GetDataTransferDirection(DMA_TypeDef * DMAx,uint32_t Channel)693 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
694 {
695 uint32_t dma_base_addr = (uint32_t)DMAx;
696 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
697 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
698 }
699
700 /**
701 * @brief Set DMA mode circular or normal.
702 * @note The circular buffer mode cannot be used if the memory-to-memory
703 * data transfer is configured on the selected Channel.
704 * @rmtoll CCR CIRC LL_DMA_SetMode
705 * @param DMAx DMAx Instance
706 * @param Channel This parameter can be one of the following values:
707 * @arg @ref LL_DMA_CHANNEL_1
708 * @arg @ref LL_DMA_CHANNEL_2
709 * @arg @ref LL_DMA_CHANNEL_3
710 * @arg @ref LL_DMA_CHANNEL_4
711 * @arg @ref LL_DMA_CHANNEL_5
712 * @arg @ref LL_DMA_CHANNEL_6
713 * @arg @ref LL_DMA_CHANNEL_7
714 * @param Mode This parameter can be one of the following values:
715 * @arg @ref LL_DMA_MODE_NORMAL
716 * @arg @ref LL_DMA_MODE_CIRCULAR
717 * @retval None
718 */
LL_DMA_SetMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Mode)719 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
720 {
721 uint32_t dma_base_addr = (uint32_t)DMAx;
722 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC,
723 Mode);
724 }
725
726 /**
727 * @brief Get DMA mode circular or normal.
728 * @rmtoll CCR CIRC LL_DMA_GetMode
729 * @param DMAx DMAx Instance
730 * @param Channel This parameter can be one of the following values:
731 * @arg @ref LL_DMA_CHANNEL_1
732 * @arg @ref LL_DMA_CHANNEL_2
733 * @arg @ref LL_DMA_CHANNEL_3
734 * @arg @ref LL_DMA_CHANNEL_4
735 * @arg @ref LL_DMA_CHANNEL_5
736 * @arg @ref LL_DMA_CHANNEL_6
737 * @arg @ref LL_DMA_CHANNEL_7
738 * @retval Returned value can be one of the following values:
739 * @arg @ref LL_DMA_MODE_NORMAL
740 * @arg @ref LL_DMA_MODE_CIRCULAR
741 */
LL_DMA_GetMode(DMA_TypeDef * DMAx,uint32_t Channel)742 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
743 {
744 uint32_t dma_base_addr = (uint32_t)DMAx;
745 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
746 DMA_CCR_CIRC));
747 }
748
749 /**
750 * @brief Set Peripheral increment mode.
751 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
752 * @param DMAx DMAx Instance
753 * @param Channel This parameter can be one of the following values:
754 * @arg @ref LL_DMA_CHANNEL_1
755 * @arg @ref LL_DMA_CHANNEL_2
756 * @arg @ref LL_DMA_CHANNEL_3
757 * @arg @ref LL_DMA_CHANNEL_4
758 * @arg @ref LL_DMA_CHANNEL_5
759 * @arg @ref LL_DMA_CHANNEL_6
760 * @arg @ref LL_DMA_CHANNEL_7
761 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
762 * @arg @ref LL_DMA_PERIPH_INCREMENT
763 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
764 * @retval None
765 */
LL_DMA_SetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcIncMode)766 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
767 {
768 uint32_t dma_base_addr = (uint32_t)DMAx;
769 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC,
770 PeriphOrM2MSrcIncMode);
771 }
772
773 /**
774 * @brief Get Peripheral increment mode.
775 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
776 * @param DMAx DMAx Instance
777 * @param Channel This parameter can be one of the following values:
778 * @arg @ref LL_DMA_CHANNEL_1
779 * @arg @ref LL_DMA_CHANNEL_2
780 * @arg @ref LL_DMA_CHANNEL_3
781 * @arg @ref LL_DMA_CHANNEL_4
782 * @arg @ref LL_DMA_CHANNEL_5
783 * @arg @ref LL_DMA_CHANNEL_6
784 * @arg @ref LL_DMA_CHANNEL_7
785 * @retval Returned value can be one of the following values:
786 * @arg @ref LL_DMA_PERIPH_INCREMENT
787 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
788 */
LL_DMA_GetPeriphIncMode(DMA_TypeDef * DMAx,uint32_t Channel)789 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
790 {
791 uint32_t dma_base_addr = (uint32_t)DMAx;
792 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
793 DMA_CCR_PINC));
794 }
795
796 /**
797 * @brief Set Memory increment mode.
798 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
799 * @param DMAx DMAx Instance
800 * @param Channel This parameter can be one of the following values:
801 * @arg @ref LL_DMA_CHANNEL_1
802 * @arg @ref LL_DMA_CHANNEL_2
803 * @arg @ref LL_DMA_CHANNEL_3
804 * @arg @ref LL_DMA_CHANNEL_4
805 * @arg @ref LL_DMA_CHANNEL_5
806 * @arg @ref LL_DMA_CHANNEL_6
807 * @arg @ref LL_DMA_CHANNEL_7
808 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
809 * @arg @ref LL_DMA_MEMORY_INCREMENT
810 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
811 * @retval None
812 */
LL_DMA_SetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstIncMode)813 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
814 {
815 uint32_t dma_base_addr = (uint32_t)DMAx;
816 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC,
817 MemoryOrM2MDstIncMode);
818 }
819
820 /**
821 * @brief Get Memory increment mode.
822 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
823 * @param DMAx DMAx Instance
824 * @param Channel This parameter can be one of the following values:
825 * @arg @ref LL_DMA_CHANNEL_1
826 * @arg @ref LL_DMA_CHANNEL_2
827 * @arg @ref LL_DMA_CHANNEL_3
828 * @arg @ref LL_DMA_CHANNEL_4
829 * @arg @ref LL_DMA_CHANNEL_5
830 * @arg @ref LL_DMA_CHANNEL_6
831 * @arg @ref LL_DMA_CHANNEL_7
832 * @retval Returned value can be one of the following values:
833 * @arg @ref LL_DMA_MEMORY_INCREMENT
834 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
835 */
LL_DMA_GetMemoryIncMode(DMA_TypeDef * DMAx,uint32_t Channel)836 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
837 {
838 uint32_t dma_base_addr = (uint32_t)DMAx;
839 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
840 DMA_CCR_MINC));
841 }
842
843 /**
844 * @brief Set Peripheral size.
845 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
846 * @param DMAx DMAx Instance
847 * @param Channel This parameter can be one of the following values:
848 * @arg @ref LL_DMA_CHANNEL_1
849 * @arg @ref LL_DMA_CHANNEL_2
850 * @arg @ref LL_DMA_CHANNEL_3
851 * @arg @ref LL_DMA_CHANNEL_4
852 * @arg @ref LL_DMA_CHANNEL_5
853 * @arg @ref LL_DMA_CHANNEL_6
854 * @arg @ref LL_DMA_CHANNEL_7
855 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
856 * @arg @ref LL_DMA_PDATAALIGN_BYTE
857 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
858 * @arg @ref LL_DMA_PDATAALIGN_WORD
859 * @retval None
860 */
LL_DMA_SetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphOrM2MSrcDataSize)861 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
862 {
863 uint32_t dma_base_addr = (uint32_t)DMAx;
864 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE,
865 PeriphOrM2MSrcDataSize);
866 }
867
868 /**
869 * @brief Get Peripheral size.
870 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
871 * @param DMAx DMAx Instance
872 * @param Channel This parameter can be one of the following values:
873 * @arg @ref LL_DMA_CHANNEL_1
874 * @arg @ref LL_DMA_CHANNEL_2
875 * @arg @ref LL_DMA_CHANNEL_3
876 * @arg @ref LL_DMA_CHANNEL_4
877 * @arg @ref LL_DMA_CHANNEL_5
878 * @arg @ref LL_DMA_CHANNEL_6
879 * @arg @ref LL_DMA_CHANNEL_7
880 * @retval Returned value can be one of the following values:
881 * @arg @ref LL_DMA_PDATAALIGN_BYTE
882 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
883 * @arg @ref LL_DMA_PDATAALIGN_WORD
884 */
LL_DMA_GetPeriphSize(DMA_TypeDef * DMAx,uint32_t Channel)885 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
886 {
887 uint32_t dma_base_addr = (uint32_t)DMAx;
888 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
889 DMA_CCR_PSIZE));
890 }
891
892 /**
893 * @brief Set Memory size.
894 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
895 * @param DMAx DMAx Instance
896 * @param Channel This parameter can be one of the following values:
897 * @arg @ref LL_DMA_CHANNEL_1
898 * @arg @ref LL_DMA_CHANNEL_2
899 * @arg @ref LL_DMA_CHANNEL_3
900 * @arg @ref LL_DMA_CHANNEL_4
901 * @arg @ref LL_DMA_CHANNEL_5
902 * @arg @ref LL_DMA_CHANNEL_6
903 * @arg @ref LL_DMA_CHANNEL_7
904 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
905 * @arg @ref LL_DMA_MDATAALIGN_BYTE
906 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
907 * @arg @ref LL_DMA_MDATAALIGN_WORD
908 * @retval None
909 */
LL_DMA_SetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryOrM2MDstDataSize)910 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
911 {
912 uint32_t dma_base_addr = (uint32_t)DMAx;
913 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE,
914 MemoryOrM2MDstDataSize);
915 }
916
917 /**
918 * @brief Get Memory size.
919 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
920 * @param DMAx DMAx Instance
921 * @param Channel This parameter can be one of the following values:
922 * @arg @ref LL_DMA_CHANNEL_1
923 * @arg @ref LL_DMA_CHANNEL_2
924 * @arg @ref LL_DMA_CHANNEL_3
925 * @arg @ref LL_DMA_CHANNEL_4
926 * @arg @ref LL_DMA_CHANNEL_5
927 * @arg @ref LL_DMA_CHANNEL_6
928 * @arg @ref LL_DMA_CHANNEL_7
929 * @retval Returned value can be one of the following values:
930 * @arg @ref LL_DMA_MDATAALIGN_BYTE
931 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
932 * @arg @ref LL_DMA_MDATAALIGN_WORD
933 */
LL_DMA_GetMemorySize(DMA_TypeDef * DMAx,uint32_t Channel)934 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
935 {
936 uint32_t dma_base_addr = (uint32_t)DMAx;
937 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
938 DMA_CCR_MSIZE));
939 }
940
941 /**
942 * @brief Set Channel priority level.
943 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
944 * @param DMAx DMAx Instance
945 * @param Channel This parameter can be one of the following values:
946 * @arg @ref LL_DMA_CHANNEL_1
947 * @arg @ref LL_DMA_CHANNEL_2
948 * @arg @ref LL_DMA_CHANNEL_3
949 * @arg @ref LL_DMA_CHANNEL_4
950 * @arg @ref LL_DMA_CHANNEL_5
951 * @arg @ref LL_DMA_CHANNEL_6
952 * @arg @ref LL_DMA_CHANNEL_7
953 * @param Priority This parameter can be one of the following values:
954 * @arg @ref LL_DMA_PRIORITY_LOW
955 * @arg @ref LL_DMA_PRIORITY_MEDIUM
956 * @arg @ref LL_DMA_PRIORITY_HIGH
957 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
958 * @retval None
959 */
LL_DMA_SetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Priority)960 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
961 {
962 uint32_t dma_base_addr = (uint32_t)DMAx;
963 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL,
964 Priority);
965 }
966
967 /**
968 * @brief Get Channel priority level.
969 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
970 * @param DMAx DMAx Instance
971 * @param Channel This parameter can be one of the following values:
972 * @arg @ref LL_DMA_CHANNEL_1
973 * @arg @ref LL_DMA_CHANNEL_2
974 * @arg @ref LL_DMA_CHANNEL_3
975 * @arg @ref LL_DMA_CHANNEL_4
976 * @arg @ref LL_DMA_CHANNEL_5
977 * @arg @ref LL_DMA_CHANNEL_6
978 * @arg @ref LL_DMA_CHANNEL_7
979 * @retval Returned value can be one of the following values:
980 * @arg @ref LL_DMA_PRIORITY_LOW
981 * @arg @ref LL_DMA_PRIORITY_MEDIUM
982 * @arg @ref LL_DMA_PRIORITY_HIGH
983 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
984 */
LL_DMA_GetChannelPriorityLevel(DMA_TypeDef * DMAx,uint32_t Channel)985 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
986 {
987 uint32_t dma_base_addr = (uint32_t)DMAx;
988 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
989 DMA_CCR_PL));
990 }
991
992 #if defined(DMA_CCR_SECM)
993 #if defined (CORE_CM0PLUS)
994 /**
995 * @brief Enable the DMA Channel secure attribute.
996 * @rmtoll CCR SECM LL_DMA_EnableChannelSecure\n
997 * @param DMAx DMAx Instance
998 * @param Channel This parameter can be one of the following values:
999 * @arg @ref LL_DMA_CHANNEL_1
1000 * @arg @ref LL_DMA_CHANNEL_2
1001 * @arg @ref LL_DMA_CHANNEL_3
1002 * @arg @ref LL_DMA_CHANNEL_4
1003 * @arg @ref LL_DMA_CHANNEL_5
1004 * @arg @ref LL_DMA_CHANNEL_6
1005 * @arg @ref LL_DMA_CHANNEL_7
1006 * @retval None
1007 */
LL_DMA_EnableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1008 __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1009 {
1010 uint32_t dma_base_addr = (uint32_t)DMAx;
1011 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM);
1012 }
1013
1014 /**
1015 * @brief Disable the DMA channel secure attribute.
1016 * @rmtoll CCR SECM LL_DMA_DisableChannelSecure\n
1017 * @param DMAx DMAx Instance
1018 * @param Channel This parameter can be one of the following values:
1019 * @arg @ref LL_DMA_CHANNEL_1
1020 * @arg @ref LL_DMA_CHANNEL_2
1021 * @arg @ref LL_DMA_CHANNEL_3
1022 * @arg @ref LL_DMA_CHANNEL_4
1023 * @arg @ref LL_DMA_CHANNEL_5
1024 * @arg @ref LL_DMA_CHANNEL_6
1025 * @arg @ref LL_DMA_CHANNEL_7
1026 * @retval None
1027 */
LL_DMA_DisableChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1028 __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1029 {
1030 uint32_t dma_base_addr = (uint32_t)DMAx;
1031 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM);
1032 }
1033 #endif /* CORE_CM0PLUS */
1034
1035 /**
1036 * @brief Check if DMA channel is secure or not.
1037 * @rmtoll CCR SECM LL_DMA_IsEnabledChannelSecure\n
1038 * @param DMAx DMAx Instance
1039 * @param Channel This parameter can be one of the following values:
1040 * @arg @ref LL_DMA_CHANNEL_1
1041 * @arg @ref LL_DMA_CHANNEL_2
1042 * @arg @ref LL_DMA_CHANNEL_3
1043 * @arg @ref LL_DMA_CHANNEL_4
1044 * @arg @ref LL_DMA_CHANNEL_5
1045 * @arg @ref LL_DMA_CHANNEL_6
1046 * @arg @ref LL_DMA_CHANNEL_7
1047 * @retval State of bit (1 or 0).
1048 */
LL_DMA_IsEnabledChannelSecure(DMA_TypeDef * DMAx,uint32_t Channel)1049 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1050 {
1051 uint32_t dma_base_addr = (uint32_t)DMAx;
1052 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1053 DMA_CCR_SECM) == (DMA_CCR_SECM)) ? 1UL : 0UL);
1054 }
1055
1056 #if defined (CORE_CM0PLUS)
1057 /**
1058 * @brief Enable the secure attribute on DMA channel source.
1059 * @rmtoll CCR SSEC LL_DMA_EnableChannelSrcSecure\n
1060 * @param DMAx DMAx Instance
1061 * @param Channel This parameter can be one of the following values:
1062 * @arg @ref LL_DMA_CHANNEL_1
1063 * @arg @ref LL_DMA_CHANNEL_2
1064 * @arg @ref LL_DMA_CHANNEL_3
1065 * @arg @ref LL_DMA_CHANNEL_4
1066 * @arg @ref LL_DMA_CHANNEL_5
1067 * @arg @ref LL_DMA_CHANNEL_6
1068 * @arg @ref LL_DMA_CHANNEL_7
1069 * @retval None
1070 */
LL_DMA_EnableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1071 __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1072 {
1073 uint32_t dma_base_addr = (uint32_t)DMAx;
1074 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC);
1075 }
1076
1077 /**
1078 * @brief Disable the secure attribute on DMA channel source.
1079 * @rmtoll CCR SSEC LL_DMA_DisableChannelSrcSecure\n
1080 * @param DMAx DMAx Instance
1081 * @param Channel This parameter can be one of the following values:
1082 * @arg @ref LL_DMA_CHANNEL_1
1083 * @arg @ref LL_DMA_CHANNEL_2
1084 * @arg @ref LL_DMA_CHANNEL_3
1085 * @arg @ref LL_DMA_CHANNEL_4
1086 * @arg @ref LL_DMA_CHANNEL_5
1087 * @arg @ref LL_DMA_CHANNEL_6
1088 * @arg @ref LL_DMA_CHANNEL_7
1089 * @retval None
1090 */
LL_DMA_DisableChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1091 __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1092 {
1093 uint32_t dma_base_addr = (uint32_t)DMAx;
1094 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC);
1095 }
1096
1097 /**
1098 * @brief Check if DMA channel source attribute is secure or not.
1099 * @rmtoll CCR SSEC LL_DMA_IsEnabledChannelSrcSecure\n
1100 * @param DMAx DMAx Instance
1101 * @param Channel This parameter can be one of the following values:
1102 * @arg @ref LL_DMA_CHANNEL_1
1103 * @arg @ref LL_DMA_CHANNEL_2
1104 * @arg @ref LL_DMA_CHANNEL_3
1105 * @arg @ref LL_DMA_CHANNEL_4
1106 * @arg @ref LL_DMA_CHANNEL_5
1107 * @arg @ref LL_DMA_CHANNEL_6
1108 * @arg @ref LL_DMA_CHANNEL_7
1109 * @retval State of bit (1 or 0).
1110 */
LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef * DMAx,uint32_t Channel)1111 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1112 {
1113 uint32_t dma_base_addr = (uint32_t)DMAx;
1114 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1115 DMA_CCR_SSEC) == (DMA_CCR_SSEC)) ? 1UL : 0UL);
1116 }
1117
1118 /**
1119 * @brief Enable the secure attribute on DMA channel destination
1120 * @rmtoll CCR DSEC LL_DMA_EnableChannelDestSecure\n
1121 * @param DMAx DMAx Instance
1122 * @param Channel This parameter can be one of the following values:
1123 * @arg @ref LL_DMA_CHANNEL_1
1124 * @arg @ref LL_DMA_CHANNEL_2
1125 * @arg @ref LL_DMA_CHANNEL_3
1126 * @arg @ref LL_DMA_CHANNEL_4
1127 * @arg @ref LL_DMA_CHANNEL_5
1128 * @arg @ref LL_DMA_CHANNEL_6
1129 * @arg @ref LL_DMA_CHANNEL_7
1130 * @retval None
1131 */
LL_DMA_EnableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1132 __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1133 {
1134 uint32_t dma_base_addr = (uint32_t)DMAx;
1135 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC);
1136 }
1137
1138 /**
1139 * @brief Disable the secure attribute on DMA channel destination.
1140 * @rmtoll CCR DSEC LL_DMA_DisableChannelDestSecure\n
1141 * @param DMAx DMAx Instance
1142 * @param Channel This parameter can be one of the following values:
1143 * @arg @ref LL_DMA_CHANNEL_1
1144 * @arg @ref LL_DMA_CHANNEL_2
1145 * @arg @ref LL_DMA_CHANNEL_3
1146 * @arg @ref LL_DMA_CHANNEL_4
1147 * @arg @ref LL_DMA_CHANNEL_5
1148 * @arg @ref LL_DMA_CHANNEL_6
1149 * @arg @ref LL_DMA_CHANNEL_7
1150 * @retval None
1151 */
LL_DMA_DisableChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1152 __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1153 {
1154 uint32_t dma_base_addr = (uint32_t)DMAx;
1155 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC);
1156 }
1157
1158 /**
1159 * @brief Check if DMA channel destination attribute is secure or not.
1160 * @rmtoll CCR DSEC LL_DMA_IsEnabledChannelDestSecure\n
1161 * @param DMAx DMAx Instance
1162 * @param Channel This parameter can be one of the following values:
1163 * @arg @ref LL_DMA_CHANNEL_1
1164 * @arg @ref LL_DMA_CHANNEL_2
1165 * @arg @ref LL_DMA_CHANNEL_3
1166 * @arg @ref LL_DMA_CHANNEL_4
1167 * @arg @ref LL_DMA_CHANNEL_5
1168 * @arg @ref LL_DMA_CHANNEL_6
1169 * @arg @ref LL_DMA_CHANNEL_7
1170 * @retval State of bit (1 or 0).
1171 */
LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef * DMAx,uint32_t Channel)1172 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel)
1173 {
1174 uint32_t dma_base_addr = (uint32_t)DMAx;
1175 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1176 DMA_CCR_DSEC) == (DMA_CCR_DSEC)) ? 1UL : 0UL);
1177 }
1178 #endif /* CORE_CM0PLUS */
1179 #endif /* DMA_CCR_SECM */
1180 #if defined(DMA_CCR_PRIV)
1181
1182 /**
1183 * @brief Enable the privilege attribute on DMA channel.
1184 * @rmtoll CCR PRIV LL_DMA_EnableChannelPrivilege\n
1185 * @param DMAx DMAx Instance
1186 * @param Channel This parameter can be one of the following values:
1187 * @arg @ref LL_DMA_CHANNEL_1
1188 * @arg @ref LL_DMA_CHANNEL_2
1189 * @arg @ref LL_DMA_CHANNEL_3
1190 * @arg @ref LL_DMA_CHANNEL_4
1191 * @arg @ref LL_DMA_CHANNEL_5
1192 * @arg @ref LL_DMA_CHANNEL_6
1193 * @arg @ref LL_DMA_CHANNEL_7
1194 * @retval None
1195 */
LL_DMA_EnableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1196 __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1197 {
1198 uint32_t dma_base_addr = (uint32_t)DMAx;
1199 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV);
1200 }
1201
1202 /**
1203 * @brief Disable the privilege attribute on DMA channel.
1204 * @rmtoll CCR PRIV LL_DMA_DisableChannelPrivilege\n
1205 * @param DMAx DMAx Instance
1206 * @param Channel This parameter can be one of the following values:
1207 * @arg @ref LL_DMA_CHANNEL_1
1208 * @arg @ref LL_DMA_CHANNEL_2
1209 * @arg @ref LL_DMA_CHANNEL_3
1210 * @arg @ref LL_DMA_CHANNEL_4
1211 * @arg @ref LL_DMA_CHANNEL_5
1212 * @arg @ref LL_DMA_CHANNEL_6
1213 * @arg @ref LL_DMA_CHANNEL_7
1214 * @retval None
1215 */
LL_DMA_DisableChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1216 __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1217 {
1218 uint32_t dma_base_addr = (uint32_t)DMAx;
1219 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV);
1220 }
1221
1222 /**
1223 * @brief Check if DMA channel attribute is privilege or not.
1224 * @rmtoll CCR PRIV LL_DMA_IsEnabledChannelPrivilege\n
1225 * @param DMAx DMAx Instance
1226 * @param Channel This parameter can be one of the following values:
1227 * @arg @ref LL_DMA_CHANNEL_1
1228 * @arg @ref LL_DMA_CHANNEL_2
1229 * @arg @ref LL_DMA_CHANNEL_3
1230 * @arg @ref LL_DMA_CHANNEL_4
1231 * @arg @ref LL_DMA_CHANNEL_5
1232 * @arg @ref LL_DMA_CHANNEL_6
1233 * @arg @ref LL_DMA_CHANNEL_7
1234 * @retval State of bit (1 or 0).
1235 */
LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef * DMAx,uint32_t Channel)1236 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel)
1237 {
1238 uint32_t dma_base_addr = (uint32_t)DMAx;
1239 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
1240 DMA_CCR_PRIV) == (DMA_CCR_PRIV)) ? 1UL : 0UL);
1241 }
1242
1243 #endif /* DMA_CCR_PRIV */
1244 /**
1245 * @brief Set Number of data to transfer.
1246 * @note This action has no effect if
1247 * channel is enabled.
1248 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
1249 * @param DMAx DMAx Instance
1250 * @param Channel This parameter can be one of the following values:
1251 * @arg @ref LL_DMA_CHANNEL_1
1252 * @arg @ref LL_DMA_CHANNEL_2
1253 * @arg @ref LL_DMA_CHANNEL_3
1254 * @arg @ref LL_DMA_CHANNEL_4
1255 * @arg @ref LL_DMA_CHANNEL_5
1256 * @arg @ref LL_DMA_CHANNEL_6
1257 * @arg @ref LL_DMA_CHANNEL_7
1258 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
1259 * @retval None
1260 */
LL_DMA_SetDataLength(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t NbData)1261 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
1262 {
1263 uint32_t dma_base_addr = (uint32_t)DMAx;
1264 MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1265 DMA_CNDTR_NDT, NbData);
1266 }
1267
1268 /**
1269 * @brief Get Number of data to transfer.
1270 * @note Once the channel is enabled, the return value indicate the
1271 * remaining bytes to be transmitted.
1272 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1273 * @param DMAx DMAx Instance
1274 * @param Channel This parameter can be one of the following values:
1275 * @arg @ref LL_DMA_CHANNEL_1
1276 * @arg @ref LL_DMA_CHANNEL_2
1277 * @arg @ref LL_DMA_CHANNEL_3
1278 * @arg @ref LL_DMA_CHANNEL_4
1279 * @arg @ref LL_DMA_CHANNEL_5
1280 * @arg @ref LL_DMA_CHANNEL_6
1281 * @arg @ref LL_DMA_CHANNEL_7
1282 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1283 */
LL_DMA_GetDataLength(DMA_TypeDef * DMAx,uint32_t Channel)1284 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1285 {
1286 uint32_t dma_base_addr = (uint32_t)DMAx;
1287 return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR,
1288 DMA_CNDTR_NDT));
1289 }
1290
1291 /**
1292 * @brief Configure the Source and Destination addresses.
1293 * @note This API must not be called when the DMA channel is enabled.
1294 * @note Each peripheral using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
1295 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1296 * CMAR MA LL_DMA_ConfigAddresses
1297 * @param DMAx DMAx Instance
1298 * @param Channel This parameter can be one of the following values:
1299 * @arg @ref LL_DMA_CHANNEL_1
1300 * @arg @ref LL_DMA_CHANNEL_2
1301 * @arg @ref LL_DMA_CHANNEL_3
1302 * @arg @ref LL_DMA_CHANNEL_4
1303 * @arg @ref LL_DMA_CHANNEL_5
1304 * @arg @ref LL_DMA_CHANNEL_6
1305 * @arg @ref LL_DMA_CHANNEL_7
1306 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1307 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1308 * @param Direction This parameter can be one of the following values:
1309 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1310 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1311 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1312 * @retval None
1313 */
LL_DMA_ConfigAddresses(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t SrcAddress,uint32_t DstAddress,uint32_t Direction)1314 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1315 uint32_t DstAddress, uint32_t Direction)
1316 {
1317 uint32_t dma_base_addr = (uint32_t)DMAx;
1318 /* Direction Memory to Periph */
1319 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1320 {
1321 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, SrcAddress);
1322 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1323 }
1324 /* Direction Periph to Memory and Memory to Memory */
1325 else
1326 {
1327 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1328 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, DstAddress);
1329 }
1330 }
1331
1332 /**
1333 * @brief Set the Memory address.
1334 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1335 * @note This API must not be called when the DMA channel is enabled.
1336 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1337 * @param DMAx DMAx Instance
1338 * @param Channel This parameter can be one of the following values:
1339 * @arg @ref LL_DMA_CHANNEL_1
1340 * @arg @ref LL_DMA_CHANNEL_2
1341 * @arg @ref LL_DMA_CHANNEL_3
1342 * @arg @ref LL_DMA_CHANNEL_4
1343 * @arg @ref LL_DMA_CHANNEL_5
1344 * @arg @ref LL_DMA_CHANNEL_6
1345 * @arg @ref LL_DMA_CHANNEL_7
1346 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1347 * @retval None
1348 */
LL_DMA_SetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1349 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1350 {
1351 uint32_t dma_base_addr = (uint32_t)DMAx;
1352 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1353 }
1354
1355 /**
1356 * @brief Set the Peripheral address.
1357 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1358 * @note This API must not be called when the DMA channel is enabled.
1359 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1360 * @param DMAx DMAx Instance
1361 * @param Channel This parameter can be one of the following values:
1362 * @arg @ref LL_DMA_CHANNEL_1
1363 * @arg @ref LL_DMA_CHANNEL_2
1364 * @arg @ref LL_DMA_CHANNEL_3
1365 * @arg @ref LL_DMA_CHANNEL_4
1366 * @arg @ref LL_DMA_CHANNEL_5
1367 * @arg @ref LL_DMA_CHANNEL_6
1368 * @arg @ref LL_DMA_CHANNEL_7
1369 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1370 * @retval None
1371 */
LL_DMA_SetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t PeriphAddress)1372 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1373 {
1374 uint32_t dma_base_addr = (uint32_t)DMAx;
1375 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1376 }
1377
1378 /**
1379 * @brief Get Memory address.
1380 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1381 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1382 * @param DMAx DMAx Instance
1383 * @param Channel This parameter can be one of the following values:
1384 * @arg @ref LL_DMA_CHANNEL_1
1385 * @arg @ref LL_DMA_CHANNEL_2
1386 * @arg @ref LL_DMA_CHANNEL_3
1387 * @arg @ref LL_DMA_CHANNEL_4
1388 * @arg @ref LL_DMA_CHANNEL_5
1389 * @arg @ref LL_DMA_CHANNEL_6
1390 * @arg @ref LL_DMA_CHANNEL_7
1391 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1392 */
LL_DMA_GetMemoryAddress(DMA_TypeDef * DMAx,uint32_t Channel)1393 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1394 {
1395 uint32_t dma_base_addr = (uint32_t)DMAx;
1396 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1397 }
1398
1399 /**
1400 * @brief Get Peripheral address.
1401 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1402 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1403 * @param DMAx DMAx Instance
1404 * @param Channel This parameter can be one of the following values:
1405 * @arg @ref LL_DMA_CHANNEL_1
1406 * @arg @ref LL_DMA_CHANNEL_2
1407 * @arg @ref LL_DMA_CHANNEL_3
1408 * @arg @ref LL_DMA_CHANNEL_4
1409 * @arg @ref LL_DMA_CHANNEL_5
1410 * @arg @ref LL_DMA_CHANNEL_6
1411 * @arg @ref LL_DMA_CHANNEL_7
1412 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1413 */
LL_DMA_GetPeriphAddress(DMA_TypeDef * DMAx,uint32_t Channel)1414 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1415 {
1416 uint32_t dma_base_addr = (uint32_t)DMAx;
1417 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1418 }
1419
1420 /**
1421 * @brief Set the Memory to Memory Source address.
1422 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1423 * @note This API must not be called when the DMA channel is enabled.
1424 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1425 * @param DMAx DMAx Instance
1426 * @param Channel This parameter can be one of the following values:
1427 * @arg @ref LL_DMA_CHANNEL_1
1428 * @arg @ref LL_DMA_CHANNEL_2
1429 * @arg @ref LL_DMA_CHANNEL_3
1430 * @arg @ref LL_DMA_CHANNEL_4
1431 * @arg @ref LL_DMA_CHANNEL_5
1432 * @arg @ref LL_DMA_CHANNEL_6
1433 * @arg @ref LL_DMA_CHANNEL_7
1434 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1435 * @retval None
1436 */
LL_DMA_SetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1437 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1438 {
1439 uint32_t dma_base_addr = (uint32_t)DMAx;
1440 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1441 }
1442
1443 /**
1444 * @brief Set the Memory to Memory Destination address.
1445 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1446 * @note This API must not be called when the DMA channel is enabled.
1447 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1448 * @param DMAx DMAx Instance
1449 * @param Channel This parameter can be one of the following values:
1450 * @arg @ref LL_DMA_CHANNEL_1
1451 * @arg @ref LL_DMA_CHANNEL_2
1452 * @arg @ref LL_DMA_CHANNEL_3
1453 * @arg @ref LL_DMA_CHANNEL_4
1454 * @arg @ref LL_DMA_CHANNEL_5
1455 * @arg @ref LL_DMA_CHANNEL_6
1456 * @arg @ref LL_DMA_CHANNEL_7
1457 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1458 * @retval None
1459 */
LL_DMA_SetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t MemoryAddress)1460 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1461 {
1462 uint32_t dma_base_addr = (uint32_t)DMAx;
1463 WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress);
1464 }
1465
1466 /**
1467 * @brief Get the Memory to Memory Source address.
1468 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1469 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1470 * @param DMAx DMAx Instance
1471 * @param Channel This parameter can be one of the following values:
1472 * @arg @ref LL_DMA_CHANNEL_1
1473 * @arg @ref LL_DMA_CHANNEL_2
1474 * @arg @ref LL_DMA_CHANNEL_3
1475 * @arg @ref LL_DMA_CHANNEL_4
1476 * @arg @ref LL_DMA_CHANNEL_5
1477 * @arg @ref LL_DMA_CHANNEL_6
1478 * @arg @ref LL_DMA_CHANNEL_7
1479 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1480 */
LL_DMA_GetM2MSrcAddress(DMA_TypeDef * DMAx,uint32_t Channel)1481 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1482 {
1483 uint32_t dma_base_addr = (uint32_t)DMAx;
1484 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR));
1485 }
1486
1487 /**
1488 * @brief Get the Memory to Memory Destination address.
1489 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1490 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1491 * @param DMAx DMAx Instance
1492 * @param Channel This parameter can be one of the following values:
1493 * @arg @ref LL_DMA_CHANNEL_1
1494 * @arg @ref LL_DMA_CHANNEL_2
1495 * @arg @ref LL_DMA_CHANNEL_3
1496 * @arg @ref LL_DMA_CHANNEL_4
1497 * @arg @ref LL_DMA_CHANNEL_5
1498 * @arg @ref LL_DMA_CHANNEL_6
1499 * @arg @ref LL_DMA_CHANNEL_7
1500 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1501 */
LL_DMA_GetM2MDstAddress(DMA_TypeDef * DMAx,uint32_t Channel)1502 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1503 {
1504 uint32_t dma_base_addr = (uint32_t)DMAx;
1505 return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR));
1506 }
1507
1508 /**
1509 * @brief Set DMA request for DMA Channels on DMAMUX Channel x.
1510 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1511 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1512 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1513 * @param DMAx DMAx Instance
1514 * @param Channel This parameter can be one of the following values:
1515 * @arg @ref LL_DMA_CHANNEL_1
1516 * @arg @ref LL_DMA_CHANNEL_2
1517 * @arg @ref LL_DMA_CHANNEL_3
1518 * @arg @ref LL_DMA_CHANNEL_4
1519 * @arg @ref LL_DMA_CHANNEL_5
1520 * @arg @ref LL_DMA_CHANNEL_6
1521 * @arg @ref LL_DMA_CHANNEL_7
1522 * @param Request This parameter can be one of the following values:
1523 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1524 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1525 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1526 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1527 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1528 * @arg @ref LL_DMAMUX_REQ_ADC
1529 * @arg @ref LL_DMAMUX_REQ_DAC_OUT1
1530 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1531 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1532 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1533 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1534 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1535 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1536 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1537 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1538 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1539 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1540 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1541 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1542 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1543 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1544 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1545 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1546 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1547 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1548 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1549 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1550 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1551 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1552 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1553 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1554 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1555 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1556 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1557 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1558 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1559 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1560 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1561 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1562 * @arg @ref LL_DMAMUX_REQ_AES_IN
1563 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1564 * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX
1565 * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX
1566 * @retval None
1567 */
LL_DMA_SetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel,uint32_t Request)1568 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
1569 {
1570 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1571 MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1572 }
1573
1574 /**
1575 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1576 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
1577 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7.
1578 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1579 * @param DMAx DMAx Instance
1580 * @param Channel This parameter can be one of the following values:
1581 * @arg @ref LL_DMA_CHANNEL_1
1582 * @arg @ref LL_DMA_CHANNEL_2
1583 * @arg @ref LL_DMA_CHANNEL_3
1584 * @arg @ref LL_DMA_CHANNEL_4
1585 * @arg @ref LL_DMA_CHANNEL_5
1586 * @arg @ref LL_DMA_CHANNEL_6
1587 * @arg @ref LL_DMA_CHANNEL_7
1588 * @retval Returned value can be one of the following values:
1589 * @arg @ref LL_DMAMUX_REQ_MEM2MEM
1590 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1591 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1592 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1593 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1594 * @arg @ref LL_DMAMUX_REQ_ADC
1595 * @arg @ref LL_DMAMUX_REQ_DAC_OUT1
1596 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1597 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1598 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1599 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1600 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1601 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1602 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1603 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1604 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1605 * @arg @ref LL_DMAMUX_REQ_I2C3_TX
1606 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1607 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1608 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1609 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1610 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1611 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1612 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1613 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1614 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1615 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1616 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1617 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1618 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1619 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1620 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1621 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1622 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1623 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1624 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1625 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1626 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1627 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1628 * @arg @ref LL_DMAMUX_REQ_AES_IN
1629 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1630 * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX
1631 * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX
1632 */
LL_DMA_GetPeriphRequest(DMA_TypeDef * DMAx,uint32_t Channel)1633 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1634 {
1635 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U);
1636 return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1637 }
1638
1639 /**
1640 * @}
1641 */
1642
1643 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1644 * @{
1645 */
1646
1647 /**
1648 * @brief Get Channel 1 global interrupt flag.
1649 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1650 * @param DMAx DMAx Instance
1651 * @retval State of bit (1 or 0).
1652 */
LL_DMA_IsActiveFlag_GI1(DMA_TypeDef * DMAx)1653 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1654 {
1655 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1656 }
1657
1658 /**
1659 * @brief Get Channel 2 global interrupt flag.
1660 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1661 * @param DMAx DMAx Instance
1662 * @retval State of bit (1 or 0).
1663 */
LL_DMA_IsActiveFlag_GI2(DMA_TypeDef * DMAx)1664 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1665 {
1666 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1667 }
1668
1669 /**
1670 * @brief Get Channel 3 global interrupt flag.
1671 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1672 * @param DMAx DMAx Instance
1673 * @retval State of bit (1 or 0).
1674 */
LL_DMA_IsActiveFlag_GI3(DMA_TypeDef * DMAx)1675 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1676 {
1677 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1678 }
1679
1680 /**
1681 * @brief Get Channel 4 global interrupt flag.
1682 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1683 * @param DMAx DMAx Instance
1684 * @retval State of bit (1 or 0).
1685 */
LL_DMA_IsActiveFlag_GI4(DMA_TypeDef * DMAx)1686 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1687 {
1688 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1689 }
1690
1691 /**
1692 * @brief Get Channel 5 global interrupt flag.
1693 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1694 * @param DMAx DMAx Instance
1695 * @retval State of bit (1 or 0).
1696 */
LL_DMA_IsActiveFlag_GI5(DMA_TypeDef * DMAx)1697 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1698 {
1699 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1700 }
1701
1702 /**
1703 * @brief Get Channel 6 global interrupt flag.
1704 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1705 * @param DMAx DMAx Instance
1706 * @retval State of bit (1 or 0).
1707 */
LL_DMA_IsActiveFlag_GI6(DMA_TypeDef * DMAx)1708 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1709 {
1710 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1711 }
1712
1713 /**
1714 * @brief Get Channel 7 global interrupt flag.
1715 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1716 * @param DMAx DMAx Instance
1717 * @retval State of bit (1 or 0).
1718 */
LL_DMA_IsActiveFlag_GI7(DMA_TypeDef * DMAx)1719 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1720 {
1721 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1722 }
1723
1724 /**
1725 * @brief Get Channel 1 transfer complete flag.
1726 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1727 * @param DMAx DMAx Instance
1728 * @retval State of bit (1 or 0).
1729 */
LL_DMA_IsActiveFlag_TC1(DMA_TypeDef * DMAx)1730 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1731 {
1732 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1733 }
1734
1735 /**
1736 * @brief Get Channel 2 transfer complete flag.
1737 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1738 * @param DMAx DMAx Instance
1739 * @retval State of bit (1 or 0).
1740 */
LL_DMA_IsActiveFlag_TC2(DMA_TypeDef * DMAx)1741 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1742 {
1743 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1744 }
1745
1746 /**
1747 * @brief Get Channel 3 transfer complete flag.
1748 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1749 * @param DMAx DMAx Instance
1750 * @retval State of bit (1 or 0).
1751 */
LL_DMA_IsActiveFlag_TC3(DMA_TypeDef * DMAx)1752 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1753 {
1754 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1755 }
1756
1757 /**
1758 * @brief Get Channel 4 transfer complete flag.
1759 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1760 * @param DMAx DMAx Instance
1761 * @retval State of bit (1 or 0).
1762 */
LL_DMA_IsActiveFlag_TC4(DMA_TypeDef * DMAx)1763 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1764 {
1765 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1766 }
1767
1768 /**
1769 * @brief Get Channel 5 transfer complete flag.
1770 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1771 * @param DMAx DMAx Instance
1772 * @retval State of bit (1 or 0).
1773 */
LL_DMA_IsActiveFlag_TC5(DMA_TypeDef * DMAx)1774 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1775 {
1776 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1777 }
1778
1779 /**
1780 * @brief Get Channel 6 transfer complete flag.
1781 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1782 * @param DMAx DMAx Instance
1783 * @retval State of bit (1 or 0).
1784 */
LL_DMA_IsActiveFlag_TC6(DMA_TypeDef * DMAx)1785 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1786 {
1787 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1788 }
1789
1790 /**
1791 * @brief Get Channel 7 transfer complete flag.
1792 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1793 * @param DMAx DMAx Instance
1794 * @retval State of bit (1 or 0).
1795 */
LL_DMA_IsActiveFlag_TC7(DMA_TypeDef * DMAx)1796 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1797 {
1798 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1799 }
1800
1801 /**
1802 * @brief Get Channel 1 half transfer flag.
1803 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1804 * @param DMAx DMAx Instance
1805 * @retval State of bit (1 or 0).
1806 */
LL_DMA_IsActiveFlag_HT1(DMA_TypeDef * DMAx)1807 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1808 {
1809 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1810 }
1811
1812 /**
1813 * @brief Get Channel 2 half transfer flag.
1814 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1815 * @param DMAx DMAx Instance
1816 * @retval State of bit (1 or 0).
1817 */
LL_DMA_IsActiveFlag_HT2(DMA_TypeDef * DMAx)1818 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1819 {
1820 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1821 }
1822
1823 /**
1824 * @brief Get Channel 3 half transfer flag.
1825 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1826 * @param DMAx DMAx Instance
1827 * @retval State of bit (1 or 0).
1828 */
LL_DMA_IsActiveFlag_HT3(DMA_TypeDef * DMAx)1829 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1830 {
1831 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1832 }
1833
1834 /**
1835 * @brief Get Channel 4 half transfer flag.
1836 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1837 * @param DMAx DMAx Instance
1838 * @retval State of bit (1 or 0).
1839 */
LL_DMA_IsActiveFlag_HT4(DMA_TypeDef * DMAx)1840 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1841 {
1842 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1843 }
1844
1845 /**
1846 * @brief Get Channel 5 half transfer flag.
1847 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1848 * @param DMAx DMAx Instance
1849 * @retval State of bit (1 or 0).
1850 */
LL_DMA_IsActiveFlag_HT5(DMA_TypeDef * DMAx)1851 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1852 {
1853 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1854 }
1855
1856 /**
1857 * @brief Get Channel 6 half transfer flag.
1858 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1859 * @param DMAx DMAx Instance
1860 * @retval State of bit (1 or 0).
1861 */
LL_DMA_IsActiveFlag_HT6(DMA_TypeDef * DMAx)1862 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1863 {
1864 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1865 }
1866
1867 /**
1868 * @brief Get Channel 7 half transfer flag.
1869 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1870 * @param DMAx DMAx Instance
1871 * @retval State of bit (1 or 0).
1872 */
LL_DMA_IsActiveFlag_HT7(DMA_TypeDef * DMAx)1873 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1874 {
1875 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1876 }
1877
1878 /**
1879 * @brief Get Channel 1 transfer error flag.
1880 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1881 * @param DMAx DMAx Instance
1882 * @retval State of bit (1 or 0).
1883 */
LL_DMA_IsActiveFlag_TE1(DMA_TypeDef * DMAx)1884 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1885 {
1886 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @brief Get Channel 2 transfer error flag.
1891 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1892 * @param DMAx DMAx Instance
1893 * @retval State of bit (1 or 0).
1894 */
LL_DMA_IsActiveFlag_TE2(DMA_TypeDef * DMAx)1895 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1896 {
1897 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1898 }
1899
1900 /**
1901 * @brief Get Channel 3 transfer error flag.
1902 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1903 * @param DMAx DMAx Instance
1904 * @retval State of bit (1 or 0).
1905 */
LL_DMA_IsActiveFlag_TE3(DMA_TypeDef * DMAx)1906 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1907 {
1908 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1909 }
1910
1911 /**
1912 * @brief Get Channel 4 transfer error flag.
1913 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1914 * @param DMAx DMAx Instance
1915 * @retval State of bit (1 or 0).
1916 */
LL_DMA_IsActiveFlag_TE4(DMA_TypeDef * DMAx)1917 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1918 {
1919 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1920 }
1921
1922 /**
1923 * @brief Get Channel 5 transfer error flag.
1924 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1925 * @param DMAx DMAx Instance
1926 * @retval State of bit (1 or 0).
1927 */
LL_DMA_IsActiveFlag_TE5(DMA_TypeDef * DMAx)1928 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1929 {
1930 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1931 }
1932
1933 /**
1934 * @brief Get Channel 6 transfer error flag.
1935 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1936 * @param DMAx DMAx Instance
1937 * @retval State of bit (1 or 0).
1938 */
LL_DMA_IsActiveFlag_TE6(DMA_TypeDef * DMAx)1939 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1940 {
1941 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1942 }
1943
1944 /**
1945 * @brief Get Channel 7 transfer error flag.
1946 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1947 * @param DMAx DMAx Instance
1948 * @retval State of bit (1 or 0).
1949 */
LL_DMA_IsActiveFlag_TE7(DMA_TypeDef * DMAx)1950 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1951 {
1952 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1953 }
1954
1955 /**
1956 * @brief Clear Channel 1 global interrupt flag.
1957 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1958 * @param DMAx DMAx Instance
1959 * @retval None
1960 */
LL_DMA_ClearFlag_GI1(DMA_TypeDef * DMAx)1961 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1962 {
1963 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1964 }
1965
1966 /**
1967 * @brief Clear Channel 2 global interrupt flag.
1968 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1969 * @param DMAx DMAx Instance
1970 * @retval None
1971 */
LL_DMA_ClearFlag_GI2(DMA_TypeDef * DMAx)1972 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1973 {
1974 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1975 }
1976
1977 /**
1978 * @brief Clear Channel 3 global interrupt flag.
1979 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1980 * @param DMAx DMAx Instance
1981 * @retval None
1982 */
LL_DMA_ClearFlag_GI3(DMA_TypeDef * DMAx)1983 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1984 {
1985 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1986 }
1987
1988 /**
1989 * @brief Clear Channel 4 global interrupt flag.
1990 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1991 * @param DMAx DMAx Instance
1992 * @retval None
1993 */
LL_DMA_ClearFlag_GI4(DMA_TypeDef * DMAx)1994 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1995 {
1996 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1997 }
1998
1999 /**
2000 * @brief Clear Channel 5 global interrupt flag.
2001 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
2002 * @param DMAx DMAx Instance
2003 * @retval None
2004 */
LL_DMA_ClearFlag_GI5(DMA_TypeDef * DMAx)2005 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
2006 {
2007 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
2008 }
2009
2010 /**
2011 * @brief Clear Channel 6 global interrupt flag.
2012 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
2013 * @param DMAx DMAx Instance
2014 * @retval None
2015 */
LL_DMA_ClearFlag_GI6(DMA_TypeDef * DMAx)2016 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
2017 {
2018 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
2019 }
2020
2021 /**
2022 * @brief Clear Channel 7 global interrupt flag.
2023 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
2024 * @param DMAx DMAx Instance
2025 * @retval None
2026 */
LL_DMA_ClearFlag_GI7(DMA_TypeDef * DMAx)2027 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
2028 {
2029 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
2030 }
2031
2032 /**
2033 * @brief Clear Channel 1 transfer complete flag.
2034 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
2035 * @param DMAx DMAx Instance
2036 * @retval None
2037 */
LL_DMA_ClearFlag_TC1(DMA_TypeDef * DMAx)2038 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2039 {
2040 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
2041 }
2042
2043 /**
2044 * @brief Clear Channel 2 transfer complete flag.
2045 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
2046 * @param DMAx DMAx Instance
2047 * @retval None
2048 */
LL_DMA_ClearFlag_TC2(DMA_TypeDef * DMAx)2049 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2050 {
2051 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
2052 }
2053
2054 /**
2055 * @brief Clear Channel 3 transfer complete flag.
2056 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
2057 * @param DMAx DMAx Instance
2058 * @retval None
2059 */
LL_DMA_ClearFlag_TC3(DMA_TypeDef * DMAx)2060 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2061 {
2062 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
2063 }
2064
2065 /**
2066 * @brief Clear Channel 4 transfer complete flag.
2067 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
2068 * @param DMAx DMAx Instance
2069 * @retval None
2070 */
LL_DMA_ClearFlag_TC4(DMA_TypeDef * DMAx)2071 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2072 {
2073 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
2074 }
2075
2076 /**
2077 * @brief Clear Channel 5 transfer complete flag.
2078 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
2079 * @param DMAx DMAx Instance
2080 * @retval None
2081 */
LL_DMA_ClearFlag_TC5(DMA_TypeDef * DMAx)2082 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2083 {
2084 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
2085 }
2086
2087 /**
2088 * @brief Clear Channel 6 transfer complete flag.
2089 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2090 * @param DMAx DMAx Instance
2091 * @retval None
2092 */
LL_DMA_ClearFlag_TC6(DMA_TypeDef * DMAx)2093 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2094 {
2095 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2096 }
2097
2098 /**
2099 * @brief Clear Channel 7 transfer complete flag.
2100 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2101 * @param DMAx DMAx Instance
2102 * @retval None
2103 */
LL_DMA_ClearFlag_TC7(DMA_TypeDef * DMAx)2104 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2105 {
2106 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2107 }
2108
2109 /**
2110 * @brief Clear Channel 1 half transfer flag.
2111 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2112 * @param DMAx DMAx Instance
2113 * @retval None
2114 */
LL_DMA_ClearFlag_HT1(DMA_TypeDef * DMAx)2115 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2116 {
2117 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2118 }
2119
2120 /**
2121 * @brief Clear Channel 2 half transfer flag.
2122 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2123 * @param DMAx DMAx Instance
2124 * @retval None
2125 */
LL_DMA_ClearFlag_HT2(DMA_TypeDef * DMAx)2126 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2127 {
2128 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2129 }
2130
2131 /**
2132 * @brief Clear Channel 3 half transfer flag.
2133 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2134 * @param DMAx DMAx Instance
2135 * @retval None
2136 */
LL_DMA_ClearFlag_HT3(DMA_TypeDef * DMAx)2137 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2138 {
2139 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2140 }
2141
2142 /**
2143 * @brief Clear Channel 4 half transfer flag.
2144 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2145 * @param DMAx DMAx Instance
2146 * @retval None
2147 */
LL_DMA_ClearFlag_HT4(DMA_TypeDef * DMAx)2148 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2149 {
2150 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2151 }
2152
2153 /**
2154 * @brief Clear Channel 5 half transfer flag.
2155 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2156 * @param DMAx DMAx Instance
2157 * @retval None
2158 */
LL_DMA_ClearFlag_HT5(DMA_TypeDef * DMAx)2159 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2160 {
2161 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2162 }
2163
2164 /**
2165 * @brief Clear Channel 6 half transfer flag.
2166 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2167 * @param DMAx DMAx Instance
2168 * @retval None
2169 */
LL_DMA_ClearFlag_HT6(DMA_TypeDef * DMAx)2170 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2171 {
2172 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2173 }
2174
2175 /**
2176 * @brief Clear Channel 7 half transfer flag.
2177 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2178 * @param DMAx DMAx Instance
2179 * @retval None
2180 */
LL_DMA_ClearFlag_HT7(DMA_TypeDef * DMAx)2181 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2182 {
2183 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2184 }
2185
2186 /**
2187 * @brief Clear Channel 1 transfer error flag.
2188 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2189 * @param DMAx DMAx Instance
2190 * @retval None
2191 */
LL_DMA_ClearFlag_TE1(DMA_TypeDef * DMAx)2192 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2193 {
2194 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2195 }
2196
2197 /**
2198 * @brief Clear Channel 2 transfer error flag.
2199 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2200 * @param DMAx DMAx Instance
2201 * @retval None
2202 */
LL_DMA_ClearFlag_TE2(DMA_TypeDef * DMAx)2203 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2204 {
2205 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2206 }
2207
2208 /**
2209 * @brief Clear Channel 3 transfer error flag.
2210 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2211 * @param DMAx DMAx Instance
2212 * @retval None
2213 */
LL_DMA_ClearFlag_TE3(DMA_TypeDef * DMAx)2214 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2215 {
2216 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2217 }
2218
2219 /**
2220 * @brief Clear Channel 4 transfer error flag.
2221 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2222 * @param DMAx DMAx Instance
2223 * @retval None
2224 */
LL_DMA_ClearFlag_TE4(DMA_TypeDef * DMAx)2225 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2226 {
2227 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2228 }
2229
2230 /**
2231 * @brief Clear Channel 5 transfer error flag.
2232 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2233 * @param DMAx DMAx Instance
2234 * @retval None
2235 */
LL_DMA_ClearFlag_TE5(DMA_TypeDef * DMAx)2236 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2237 {
2238 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2239 }
2240
2241 /**
2242 * @brief Clear Channel 6 transfer error flag.
2243 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2244 * @param DMAx DMAx Instance
2245 * @retval None
2246 */
LL_DMA_ClearFlag_TE6(DMA_TypeDef * DMAx)2247 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2248 {
2249 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2250 }
2251
2252 /**
2253 * @brief Clear Channel 7 transfer error flag.
2254 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2255 * @param DMAx DMAx Instance
2256 * @retval None
2257 */
LL_DMA_ClearFlag_TE7(DMA_TypeDef * DMAx)2258 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2259 {
2260 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2261 }
2262
2263 /**
2264 * @}
2265 */
2266
2267 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2268 * @{
2269 */
2270 /**
2271 * @brief Enable Transfer complete interrupt.
2272 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2273 * @param DMAx DMAx Instance
2274 * @param Channel This parameter can be one of the following values:
2275 * @arg @ref LL_DMA_CHANNEL_1
2276 * @arg @ref LL_DMA_CHANNEL_2
2277 * @arg @ref LL_DMA_CHANNEL_3
2278 * @arg @ref LL_DMA_CHANNEL_4
2279 * @arg @ref LL_DMA_CHANNEL_5
2280 * @arg @ref LL_DMA_CHANNEL_6
2281 * @arg @ref LL_DMA_CHANNEL_7
2282 * @retval None
2283 */
LL_DMA_EnableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2284 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2285 {
2286 uint32_t dma_base_addr = (uint32_t)DMAx;
2287 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2288 }
2289
2290 /**
2291 * @brief Enable Half transfer interrupt.
2292 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2293 * @param DMAx DMAx Instance
2294 * @param Channel This parameter can be one of the following values:
2295 * @arg @ref LL_DMA_CHANNEL_1
2296 * @arg @ref LL_DMA_CHANNEL_2
2297 * @arg @ref LL_DMA_CHANNEL_3
2298 * @arg @ref LL_DMA_CHANNEL_4
2299 * @arg @ref LL_DMA_CHANNEL_5
2300 * @arg @ref LL_DMA_CHANNEL_6
2301 * @arg @ref LL_DMA_CHANNEL_7
2302 * @retval None
2303 */
LL_DMA_EnableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2304 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2305 {
2306 uint32_t dma_base_addr = (uint32_t)DMAx;
2307 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2308 }
2309
2310 /**
2311 * @brief Enable Transfer error interrupt.
2312 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2313 * @param DMAx DMAx Instance
2314 * @param Channel This parameter can be one of the following values:
2315 * @arg @ref LL_DMA_CHANNEL_1
2316 * @arg @ref LL_DMA_CHANNEL_2
2317 * @arg @ref LL_DMA_CHANNEL_3
2318 * @arg @ref LL_DMA_CHANNEL_4
2319 * @arg @ref LL_DMA_CHANNEL_5
2320 * @arg @ref LL_DMA_CHANNEL_6
2321 * @arg @ref LL_DMA_CHANNEL_7
2322 * @retval None
2323 */
LL_DMA_EnableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2324 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2325 {
2326 uint32_t dma_base_addr = (uint32_t)DMAx;
2327 SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2328 }
2329
2330 /**
2331 * @brief Disable Transfer complete interrupt.
2332 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2333 * @param DMAx DMAx Instance
2334 * @param Channel This parameter can be one of the following values:
2335 * @arg @ref LL_DMA_CHANNEL_1
2336 * @arg @ref LL_DMA_CHANNEL_2
2337 * @arg @ref LL_DMA_CHANNEL_3
2338 * @arg @ref LL_DMA_CHANNEL_4
2339 * @arg @ref LL_DMA_CHANNEL_5
2340 * @arg @ref LL_DMA_CHANNEL_6
2341 * @arg @ref LL_DMA_CHANNEL_7
2342 * @retval None
2343 */
LL_DMA_DisableIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2344 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2345 {
2346 uint32_t dma_base_addr = (uint32_t)DMAx;
2347 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE);
2348 }
2349
2350 /**
2351 * @brief Disable Half transfer interrupt.
2352 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2353 * @param DMAx DMAx Instance
2354 * @param Channel This parameter can be one of the following values:
2355 * @arg @ref LL_DMA_CHANNEL_1
2356 * @arg @ref LL_DMA_CHANNEL_2
2357 * @arg @ref LL_DMA_CHANNEL_3
2358 * @arg @ref LL_DMA_CHANNEL_4
2359 * @arg @ref LL_DMA_CHANNEL_5
2360 * @arg @ref LL_DMA_CHANNEL_6
2361 * @arg @ref LL_DMA_CHANNEL_7
2362 * @retval None
2363 */
LL_DMA_DisableIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2364 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2365 {
2366 uint32_t dma_base_addr = (uint32_t)DMAx;
2367 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE);
2368 }
2369
2370 /**
2371 * @brief Disable Transfer error interrupt.
2372 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2373 * @param DMAx DMAx Instance
2374 * @param Channel This parameter can be one of the following values:
2375 * @arg @ref LL_DMA_CHANNEL_1
2376 * @arg @ref LL_DMA_CHANNEL_2
2377 * @arg @ref LL_DMA_CHANNEL_3
2378 * @arg @ref LL_DMA_CHANNEL_4
2379 * @arg @ref LL_DMA_CHANNEL_5
2380 * @arg @ref LL_DMA_CHANNEL_6
2381 * @arg @ref LL_DMA_CHANNEL_7
2382 * @retval None
2383 */
LL_DMA_DisableIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2384 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2385 {
2386 uint32_t dma_base_addr = (uint32_t)DMAx;
2387 CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE);
2388 }
2389
2390 /**
2391 * @brief Check if Transfer complete Interrupt is enabled.
2392 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2393 * @param DMAx DMAx Instance
2394 * @param Channel This parameter can be one of the following values:
2395 * @arg @ref LL_DMA_CHANNEL_1
2396 * @arg @ref LL_DMA_CHANNEL_2
2397 * @arg @ref LL_DMA_CHANNEL_3
2398 * @arg @ref LL_DMA_CHANNEL_4
2399 * @arg @ref LL_DMA_CHANNEL_5
2400 * @arg @ref LL_DMA_CHANNEL_6
2401 * @arg @ref LL_DMA_CHANNEL_7
2402 * @retval State of bit (1 or 0).
2403 */
LL_DMA_IsEnabledIT_TC(DMA_TypeDef * DMAx,uint32_t Channel)2404 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2405 {
2406 uint32_t dma_base_addr = (uint32_t)DMAx;
2407 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2408 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2409 }
2410
2411 /**
2412 * @brief Check if Half transfer Interrupt is enabled.
2413 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2414 * @param DMAx DMAx Instance
2415 * @param Channel This parameter can be one of the following values:
2416 * @arg @ref LL_DMA_CHANNEL_1
2417 * @arg @ref LL_DMA_CHANNEL_2
2418 * @arg @ref LL_DMA_CHANNEL_3
2419 * @arg @ref LL_DMA_CHANNEL_4
2420 * @arg @ref LL_DMA_CHANNEL_5
2421 * @arg @ref LL_DMA_CHANNEL_6
2422 * @arg @ref LL_DMA_CHANNEL_7
2423 * @retval State of bit (1 or 0).
2424 */
LL_DMA_IsEnabledIT_HT(DMA_TypeDef * DMAx,uint32_t Channel)2425 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2426 {
2427 uint32_t dma_base_addr = (uint32_t)DMAx;
2428 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2429 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2430 }
2431
2432 /**
2433 * @brief Check if Transfer error Interrupt is enabled.
2434 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2435 * @param DMAx DMAx Instance
2436 * @param Channel This parameter can be one of the following values:
2437 * @arg @ref LL_DMA_CHANNEL_1
2438 * @arg @ref LL_DMA_CHANNEL_2
2439 * @arg @ref LL_DMA_CHANNEL_3
2440 * @arg @ref LL_DMA_CHANNEL_4
2441 * @arg @ref LL_DMA_CHANNEL_5
2442 * @arg @ref LL_DMA_CHANNEL_6
2443 * @arg @ref LL_DMA_CHANNEL_7
2444 * @retval State of bit (1 or 0).
2445 */
LL_DMA_IsEnabledIT_TE(DMA_TypeDef * DMAx,uint32_t Channel)2446 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2447 {
2448 uint32_t dma_base_addr = (uint32_t)DMAx;
2449 return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR,
2450 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2451 }
2452
2453 /**
2454 * @}
2455 */
2456
2457 #if defined(USE_FULL_LL_DRIVER)
2458 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2459 * @{
2460 */
2461 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2462 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2463 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2464
2465 /**
2466 * @}
2467 */
2468 #endif /* USE_FULL_LL_DRIVER */
2469
2470 /**
2471 * @}
2472 */
2473
2474 /**
2475 * @}
2476 */
2477
2478 #endif /* DMA1 || DMA2 */
2479
2480 /**
2481 * @}
2482 */
2483
2484 #ifdef __cplusplus
2485 }
2486 #endif
2487
2488 #endif /* STM32WLxx_LL_DMA_H */
2489
