1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef STM32WBxx_LL_UTILS_H
34 #define STM32WBxx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32wbxx.h"
42
43 /** @addtogroup STM32WBxx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @brief Package data register base address
74 */
75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 /* Exported types ------------------------------------------------------------*/
89 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
90 * @{
91 */
92 /**
93 * @brief UTILS PLL structure definition
94 */
95 typedef struct
96 {
97 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV.
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102
103 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
104 This parameter must be a number between Min_Data = 6 and Max_Data = 127.
105
106 This feature can be modified afterwards using unitary function
107 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
108
109 uint32_t PLLR; /*!< Division for the main system clock.
110 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV.
111
112 This feature can be modified afterwards using unitary function
113 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
114 } LL_UTILS_PLLInitTypeDef;
115
116 /**
117 * @brief UTILS System, AHB and APB buses clock configuration structure definition
118 */
119 typedef struct
120 {
121 uint32_t CPU1CLKDivider; /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK).
122 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV.
123
124 This feature can be modified afterwards using unitary function
125 @ref LL_RCC_SetAHBPrescaler(). */
126
127 uint32_t CPU2CLKDivider; /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK).
128 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV.
129
130 This feature can be modified afterwards using unitary function
131 @ref LL_C2_RCC_SetAHBPrescaler(). */
132
133 uint32_t AHB4CLKDivider; /*!< The AHBS clock (HCLK4) divider. This clock is derived from the system clock (SYSCLK).
134 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV.
135
136 This feature can be modified afterwards using unitary function
137 @ref LL_RCC_SetAHB4Prescaler(). */
138
139 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1).
140 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV.
141
142 This feature can be modified afterwards using unitary function
143 @ref LL_RCC_SetAPB1Prescaler(). */
144
145 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1).
146 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV.
147
148 This feature can be modified afterwards using unitary function
149 @ref LL_RCC_SetAPB2Prescaler(). */
150
151 } LL_UTILS_ClkInitTypeDef;
152
153 /**
154 * @}
155 */
156
157 /* Exported constants --------------------------------------------------------*/
158 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
159 * @{
160 */
161
162 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
163 * @{
164 */
165 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
166 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
167 /**
168 * @}
169 */
170
171 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
172 * @{
173 */
174 #define LL_UTILS_PACKAGETYPE_CSP100 0x00000011U /*!< CSP100/BGA129 package type */
175 #define LL_UTILS_PACKAGETYPE_QFN68 0x00000013U /*!< QFN68 package type */
176 #define LL_UTILS_PACKAGETYPE_QFN48 0x0000000AU /*!< QFN48 package type */
177
178 /**
179 * @}
180 */
181
182 /**
183 * @}
184 */
185
186 /* Exported macro ------------------------------------------------------------*/
187
188 /* Exported functions --------------------------------------------------------*/
189 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
190 * @{
191 */
192
193 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
194 * @{
195 */
196 /**
197 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
198 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
199 */
LL_GetUID_Word0(void)200 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
201 {
202 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
203 }
204
205 /**
206 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
207 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
208 */
LL_GetUID_Word1(void)209 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
210 {
211 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
212 }
213
214 /**
215 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
216 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
217 */
LL_GetUID_Word2(void)218 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
219 {
220 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
221 }
222
223 /**
224 * @brief Get Flash memory size
225 * @note This bitfield indicates the size of the device Flash memory expressed in
226 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
227 * @retval FLASH_SIZE[15:0]: Flash memory size
228 */
LL_GetFlashSize(void)229 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
230 {
231 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
232 }
233
234 /**
235 * @brief Get Package type
236 * @retval Returned value can be one of the following values:
237 * @arg @ref LL_UTILS_PACKAGETYPE_CSP100
238 * @arg @ref LL_UTILS_PACKAGETYPE_QFN68
239 * @arg @ref LL_UTILS_PACKAGETYPE_QFN48
240 *
241 */
LL_GetPackageType(void)242 __STATIC_INLINE uint32_t LL_GetPackageType(void)
243 {
244 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
245 }
246
247 /**
248 * @}
249 */
250
251 /** @defgroup UTILS_LL_EF_DELAY DELAY
252 * @{
253 */
254 /**
255 * @brief This function configures the Cortex-M SysTick source of the time base.
256 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
257 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
258 * configuration by calling this function, for a delay use rather osDelay RTOS service.
259 * @param Ticks Number of ticks
260 * @retval None
261 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)262 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
263 {
264 /* Configure the SysTick to have interrupt in 1ms time base */
265 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
266 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
267 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
268 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
269 }
270
271 void LL_Init1msTick(uint32_t HCLKFrequency);
272
273 void LL_mDelay(uint32_t Delay);
274
275 /**
276 * @}
277 */
278
279 /** @defgroup UTILS_EF_SYSTEM SYSTEM
280 * @{
281 */
282
283 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
284 ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency);
285 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
286 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
287 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
288 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
289 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEBypass,
290 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
291
292 /**
293 * @}
294 */
295
296 /**
297 * @}
298 */
299
300 /**
301 * @}
302 */
303
304 /**
305 * @}
306 */
307
308 #ifdef __cplusplus
309 }
310 #endif
311
312 #endif /* STM32WBxx_LL_UTILS_H */
313
