1 /**
2 ******************************************************************************
3 * @file stm32wbxx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WBxx_LL_HSEM_H
21 #define STM32WBxx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wbxx.h"
29
30 /** @addtogroup STM32WBxx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_COREID COREID Defines
53 * @{
54 */
55 #define LL_HSEM_COREID_NONE 0U
56 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
57 #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
58 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT
59 /**
60 * @}
61 */
62
63
64 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
65 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
66 * @{
67 */
68
69 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
70 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
71 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
72 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
73 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
74 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
75 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
76 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
77 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
78 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
79 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
80 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
81 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
82 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
83 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
84 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
85 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
86 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
87 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
88 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
89 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
90 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
91 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
92 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
93 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
94 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
95 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
96 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
97 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
98 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
99 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
100 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
101 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
102 /**
103 * @}
104 */
105
106 /**
107 * @}
108 */
109
110 /* Exported macro ------------------------------------------------------------*/
111 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
112 * @{
113 */
114
115 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
116 * @{
117 */
118
119 /**
120 * @brief Write a value in HSEM register
121 * @param __INSTANCE__ HSEM Instance
122 * @param __REG__ Register to be written
123 * @param __VALUE__ Value to be written in the register
124 * @retval None
125 */
126 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
127
128 /**
129 * @brief Read a value in HSEM register
130 * @param __INSTANCE__ HSEM Instance
131 * @param __REG__ Register to be read
132 * @retval Register value
133 */
134 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
135 /**
136 * @}
137 */
138
139 /**
140 * @}
141 */
142
143 /* Exported functions --------------------------------------------------------*/
144 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
145 * @{
146 */
147
148 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
149 * @{
150 */
151
152
153 /**
154 * @brief Return 1 if the semaphore is locked, else return 0.
155 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
156 * @param HSEMx HSEM Instance.
157 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
158 * @retval State of bit (1 or 0).
159 */
LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef * HSEMx,uint32_t Semaphore)160 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
161 {
162 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
163 }
164
165 /**
166 * @brief Get core id.
167 * @rmtoll R COREID LL_HSEM_GetCoreId
168 * @param HSEMx HSEM Instance.
169 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
170 * @retval Returned value can be one of the following values:
171 * @arg @ref LL_HSEM_COREID_NONE
172 * @arg @ref LL_HSEM_COREID_CPU1
173 * @arg @ref LL_HSEM_COREID_CPU2
174 */
LL_HSEM_GetCoreId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)175 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
176 {
177 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
178 }
179
180 /**
181 * @brief Get process id.
182 * @rmtoll R PROCID LL_HSEM_GetProcessId
183 * @param HSEMx HSEM Instance.
184 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
185 * @retval Process number. Value between Min_Data=0 and Max_Data=255
186 */
LL_HSEM_GetProcessId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)187 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
188 {
189 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
190 }
191
192 /**
193 * @brief Get the lock by writing in R register.
194 * @note The R register has to be read to determined if the lock is taken.
195 * @rmtoll R LOCK LL_HSEM_SetLock
196 * @rmtoll R COREID LL_HSEM_SetLock
197 * @rmtoll R PROCID LL_HSEM_SetLock
198 * @param HSEMx HSEM Instance.
199 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
200 * @param process Process id. Value between Min_Data=0 and Max_Data=255
201 * @retval None
202 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)203 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
204 {
205 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
206 }
207
208 /**
209 * @brief Get the lock with 2-step lock.
210 * @rmtoll R LOCK LL_HSEM_2StepLock
211 * @rmtoll R COREID LL_HSEM_2StepLock
212 * @rmtoll R PROCID LL_HSEM_2StepLock
213 * @param HSEMx HSEM Instance.
214 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
215 * @param process Process id. Value between Min_Data=0 and Max_Data=255
216 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
217 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)218 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
219 {
220 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
221 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
222 }
223
224 /**
225 * @brief Get the lock with 1-step lock.
226 * @rmtoll RLR LOCK LL_HSEM_1StepLock
227 * @rmtoll RLR COREID LL_HSEM_1StepLock
228 * @rmtoll RLR PROCID LL_HSEM_1StepLock
229 * @param HSEMx HSEM Instance.
230 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
231 * @retval 1 lock fail, 0 lock successful or already locked by same core
232 */
LL_HSEM_1StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore)233 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
234 {
235 return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
236 }
237
238 /**
239 * @brief Release the lock of the semaphore.
240 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
241 * @rmtoll R LOCK LL_HSEM_ReleaseLock
242 * @param HSEMx HSEM Instance.
243 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
244 * @param process Process number. Value between Min_Data=0 and Max_Data=255
245 * @retval None
246 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)247 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
248 {
249 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
250 }
251
252 /**
253 * @brief Get the lock status of the semaphore.
254 * @rmtoll R LOCK LL_HSEM_GetStatus
255 * @param HSEMx HSEM Instance.
256 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
257 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(HSEM_TypeDef * HSEMx,uint32_t Semaphore)258 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
259 {
260 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
261 }
262
263 /**
264 * @brief Set the key.
265 * @rmtoll KEYR KEY LL_HSEM_SetKey
266 * @param HSEMx HSEM Instance.
267 * @param key Key value.
268 * @retval None
269 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)270 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
271 {
272 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
273 }
274
275 /**
276 * @brief Get the key.
277 * @rmtoll KEYR KEY LL_HSEM_GetKey
278 * @param HSEMx HSEM Instance.
279 * @retval key to unlock all semaphore from the same core
280 */
LL_HSEM_GetKey(HSEM_TypeDef * HSEMx)281 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
282 {
283 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
284 }
285
286 /**
287 * @brief Release all semaphore with the same core id.
288 * @rmtoll CR KEY LL_HSEM_ResetAllLock
289 * @rmtoll CR SEC LL_HSEM_ResetAllLock
290 * @rmtoll CR PRIV LL_HSEM_ResetAllLock
291 * @param HSEMx HSEM Instance.
292 * @param key Key value.
293 * @param core This parameter can be one of the following values:
294 * @arg @ref LL_HSEM_COREID_CPU1
295 * @arg @ref LL_HSEM_COREID_CPU2
296 * @retval None
297 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core)298 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
299 {
300 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
301 }
302
303 /**
304 * @}
305 */
306
307 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
308 * @{
309 */
310
311 /**
312 * @brief Enable interrupt.
313 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER
314 * @param HSEMx HSEM Instance.
315 * @param SemaphoreMask This parameter can be a combination of the following values:
316 * @arg @ref LL_HSEM_SEMAPHORE_0
317 * @arg @ref LL_HSEM_SEMAPHORE_1
318 * @arg @ref LL_HSEM_SEMAPHORE_2
319 * @arg @ref LL_HSEM_SEMAPHORE_3
320 * @arg @ref LL_HSEM_SEMAPHORE_4
321 * @arg @ref LL_HSEM_SEMAPHORE_5
322 * @arg @ref LL_HSEM_SEMAPHORE_6
323 * @arg @ref LL_HSEM_SEMAPHORE_7
324 * @arg @ref LL_HSEM_SEMAPHORE_8
325 * @arg @ref LL_HSEM_SEMAPHORE_9
326 * @arg @ref LL_HSEM_SEMAPHORE_10
327 * @arg @ref LL_HSEM_SEMAPHORE_11
328 * @arg @ref LL_HSEM_SEMAPHORE_12
329 * @arg @ref LL_HSEM_SEMAPHORE_13
330 * @arg @ref LL_HSEM_SEMAPHORE_14
331 * @arg @ref LL_HSEM_SEMAPHORE_15
332 * @arg @ref LL_HSEM_SEMAPHORE_16
333 * @arg @ref LL_HSEM_SEMAPHORE_17
334 * @arg @ref LL_HSEM_SEMAPHORE_18
335 * @arg @ref LL_HSEM_SEMAPHORE_19
336 * @arg @ref LL_HSEM_SEMAPHORE_20
337 * @arg @ref LL_HSEM_SEMAPHORE_21
338 * @arg @ref LL_HSEM_SEMAPHORE_22
339 * @arg @ref LL_HSEM_SEMAPHORE_23
340 * @arg @ref LL_HSEM_SEMAPHORE_24
341 * @arg @ref LL_HSEM_SEMAPHORE_25
342 * @arg @ref LL_HSEM_SEMAPHORE_26
343 * @arg @ref LL_HSEM_SEMAPHORE_27
344 * @arg @ref LL_HSEM_SEMAPHORE_28
345 * @arg @ref LL_HSEM_SEMAPHORE_29
346 * @arg @ref LL_HSEM_SEMAPHORE_30
347 * @arg @ref LL_HSEM_SEMAPHORE_31
348 * @arg @ref LL_HSEM_SEMAPHORE_ALL
349 * @retval None
350 */
LL_HSEM_EnableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)351 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
352 {
353 SET_BIT(HSEMx->C1IER, SemaphoreMask);
354 }
355
356 /**
357 * @brief Disable interrupt.
358 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER
359 * @param HSEMx HSEM Instance.
360 * @param SemaphoreMask This parameter can be a combination of the following values:
361 * @arg @ref LL_HSEM_SEMAPHORE_0
362 * @arg @ref LL_HSEM_SEMAPHORE_1
363 * @arg @ref LL_HSEM_SEMAPHORE_2
364 * @arg @ref LL_HSEM_SEMAPHORE_3
365 * @arg @ref LL_HSEM_SEMAPHORE_4
366 * @arg @ref LL_HSEM_SEMAPHORE_5
367 * @arg @ref LL_HSEM_SEMAPHORE_6
368 * @arg @ref LL_HSEM_SEMAPHORE_7
369 * @arg @ref LL_HSEM_SEMAPHORE_8
370 * @arg @ref LL_HSEM_SEMAPHORE_9
371 * @arg @ref LL_HSEM_SEMAPHORE_10
372 * @arg @ref LL_HSEM_SEMAPHORE_11
373 * @arg @ref LL_HSEM_SEMAPHORE_12
374 * @arg @ref LL_HSEM_SEMAPHORE_13
375 * @arg @ref LL_HSEM_SEMAPHORE_14
376 * @arg @ref LL_HSEM_SEMAPHORE_15
377 * @arg @ref LL_HSEM_SEMAPHORE_16
378 * @arg @ref LL_HSEM_SEMAPHORE_17
379 * @arg @ref LL_HSEM_SEMAPHORE_18
380 * @arg @ref LL_HSEM_SEMAPHORE_19
381 * @arg @ref LL_HSEM_SEMAPHORE_20
382 * @arg @ref LL_HSEM_SEMAPHORE_21
383 * @arg @ref LL_HSEM_SEMAPHORE_22
384 * @arg @ref LL_HSEM_SEMAPHORE_23
385 * @arg @ref LL_HSEM_SEMAPHORE_24
386 * @arg @ref LL_HSEM_SEMAPHORE_25
387 * @arg @ref LL_HSEM_SEMAPHORE_26
388 * @arg @ref LL_HSEM_SEMAPHORE_27
389 * @arg @ref LL_HSEM_SEMAPHORE_28
390 * @arg @ref LL_HSEM_SEMAPHORE_29
391 * @arg @ref LL_HSEM_SEMAPHORE_30
392 * @arg @ref LL_HSEM_SEMAPHORE_31
393 * @arg @ref LL_HSEM_SEMAPHORE_ALL
394 * @retval None
395 */
LL_HSEM_DisableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)396 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
397 {
398 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
399 }
400
401 /**
402 * @brief Check if interrupt is enabled.
403 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
404 * @param HSEMx HSEM Instance.
405 * @param SemaphoreMask This parameter can be a combination of the following values:
406 * @arg @ref LL_HSEM_SEMAPHORE_0
407 * @arg @ref LL_HSEM_SEMAPHORE_1
408 * @arg @ref LL_HSEM_SEMAPHORE_2
409 * @arg @ref LL_HSEM_SEMAPHORE_3
410 * @arg @ref LL_HSEM_SEMAPHORE_4
411 * @arg @ref LL_HSEM_SEMAPHORE_5
412 * @arg @ref LL_HSEM_SEMAPHORE_6
413 * @arg @ref LL_HSEM_SEMAPHORE_7
414 * @arg @ref LL_HSEM_SEMAPHORE_8
415 * @arg @ref LL_HSEM_SEMAPHORE_9
416 * @arg @ref LL_HSEM_SEMAPHORE_10
417 * @arg @ref LL_HSEM_SEMAPHORE_11
418 * @arg @ref LL_HSEM_SEMAPHORE_12
419 * @arg @ref LL_HSEM_SEMAPHORE_13
420 * @arg @ref LL_HSEM_SEMAPHORE_14
421 * @arg @ref LL_HSEM_SEMAPHORE_15
422 * @arg @ref LL_HSEM_SEMAPHORE_16
423 * @arg @ref LL_HSEM_SEMAPHORE_17
424 * @arg @ref LL_HSEM_SEMAPHORE_18
425 * @arg @ref LL_HSEM_SEMAPHORE_19
426 * @arg @ref LL_HSEM_SEMAPHORE_20
427 * @arg @ref LL_HSEM_SEMAPHORE_21
428 * @arg @ref LL_HSEM_SEMAPHORE_22
429 * @arg @ref LL_HSEM_SEMAPHORE_23
430 * @arg @ref LL_HSEM_SEMAPHORE_24
431 * @arg @ref LL_HSEM_SEMAPHORE_25
432 * @arg @ref LL_HSEM_SEMAPHORE_26
433 * @arg @ref LL_HSEM_SEMAPHORE_27
434 * @arg @ref LL_HSEM_SEMAPHORE_28
435 * @arg @ref LL_HSEM_SEMAPHORE_29
436 * @arg @ref LL_HSEM_SEMAPHORE_30
437 * @arg @ref LL_HSEM_SEMAPHORE_31
438 * @arg @ref LL_HSEM_SEMAPHORE_ALL
439 * @retval State of bit (1 or 0).
440 */
LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)441 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
442 {
443 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
444 }
445
446 /**
447 * @brief Enable interrupt.
448 * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER
449 * @param HSEMx HSEM Instance.
450 * @param SemaphoreMask This parameter can be a combination of the following values:
451 * @arg @ref LL_HSEM_SEMAPHORE_0
452 * @arg @ref LL_HSEM_SEMAPHORE_1
453 * @arg @ref LL_HSEM_SEMAPHORE_2
454 * @arg @ref LL_HSEM_SEMAPHORE_3
455 * @arg @ref LL_HSEM_SEMAPHORE_4
456 * @arg @ref LL_HSEM_SEMAPHORE_5
457 * @arg @ref LL_HSEM_SEMAPHORE_6
458 * @arg @ref LL_HSEM_SEMAPHORE_7
459 * @arg @ref LL_HSEM_SEMAPHORE_8
460 * @arg @ref LL_HSEM_SEMAPHORE_9
461 * @arg @ref LL_HSEM_SEMAPHORE_10
462 * @arg @ref LL_HSEM_SEMAPHORE_11
463 * @arg @ref LL_HSEM_SEMAPHORE_12
464 * @arg @ref LL_HSEM_SEMAPHORE_13
465 * @arg @ref LL_HSEM_SEMAPHORE_14
466 * @arg @ref LL_HSEM_SEMAPHORE_15
467 * @arg @ref LL_HSEM_SEMAPHORE_16
468 * @arg @ref LL_HSEM_SEMAPHORE_17
469 * @arg @ref LL_HSEM_SEMAPHORE_18
470 * @arg @ref LL_HSEM_SEMAPHORE_19
471 * @arg @ref LL_HSEM_SEMAPHORE_20
472 * @arg @ref LL_HSEM_SEMAPHORE_21
473 * @arg @ref LL_HSEM_SEMAPHORE_22
474 * @arg @ref LL_HSEM_SEMAPHORE_23
475 * @arg @ref LL_HSEM_SEMAPHORE_24
476 * @arg @ref LL_HSEM_SEMAPHORE_25
477 * @arg @ref LL_HSEM_SEMAPHORE_26
478 * @arg @ref LL_HSEM_SEMAPHORE_27
479 * @arg @ref LL_HSEM_SEMAPHORE_28
480 * @arg @ref LL_HSEM_SEMAPHORE_29
481 * @arg @ref LL_HSEM_SEMAPHORE_30
482 * @arg @ref LL_HSEM_SEMAPHORE_31
483 * @arg @ref LL_HSEM_SEMAPHORE_ALL
484 * @retval None
485 */
LL_HSEM_EnableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)486 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
487 {
488 SET_BIT(HSEMx->C2IER, SemaphoreMask);
489 }
490
491 /**
492 * @brief Disable interrupt.
493 * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER
494 * @param HSEMx HSEM Instance.
495 * @param SemaphoreMask This parameter can be a combination of the following values:
496 * @arg @ref LL_HSEM_SEMAPHORE_0
497 * @arg @ref LL_HSEM_SEMAPHORE_1
498 * @arg @ref LL_HSEM_SEMAPHORE_2
499 * @arg @ref LL_HSEM_SEMAPHORE_3
500 * @arg @ref LL_HSEM_SEMAPHORE_4
501 * @arg @ref LL_HSEM_SEMAPHORE_5
502 * @arg @ref LL_HSEM_SEMAPHORE_6
503 * @arg @ref LL_HSEM_SEMAPHORE_7
504 * @arg @ref LL_HSEM_SEMAPHORE_8
505 * @arg @ref LL_HSEM_SEMAPHORE_9
506 * @arg @ref LL_HSEM_SEMAPHORE_10
507 * @arg @ref LL_HSEM_SEMAPHORE_11
508 * @arg @ref LL_HSEM_SEMAPHORE_12
509 * @arg @ref LL_HSEM_SEMAPHORE_13
510 * @arg @ref LL_HSEM_SEMAPHORE_14
511 * @arg @ref LL_HSEM_SEMAPHORE_15
512 * @arg @ref LL_HSEM_SEMAPHORE_16
513 * @arg @ref LL_HSEM_SEMAPHORE_17
514 * @arg @ref LL_HSEM_SEMAPHORE_18
515 * @arg @ref LL_HSEM_SEMAPHORE_19
516 * @arg @ref LL_HSEM_SEMAPHORE_20
517 * @arg @ref LL_HSEM_SEMAPHORE_21
518 * @arg @ref LL_HSEM_SEMAPHORE_22
519 * @arg @ref LL_HSEM_SEMAPHORE_23
520 * @arg @ref LL_HSEM_SEMAPHORE_24
521 * @arg @ref LL_HSEM_SEMAPHORE_25
522 * @arg @ref LL_HSEM_SEMAPHORE_26
523 * @arg @ref LL_HSEM_SEMAPHORE_27
524 * @arg @ref LL_HSEM_SEMAPHORE_28
525 * @arg @ref LL_HSEM_SEMAPHORE_29
526 * @arg @ref LL_HSEM_SEMAPHORE_30
527 * @arg @ref LL_HSEM_SEMAPHORE_31
528 * @arg @ref LL_HSEM_SEMAPHORE_ALL
529 * @retval None
530 */
LL_HSEM_DisableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)531 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
532 {
533 CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
534 }
535
536 /**
537 * @brief Check if interrupt is enabled.
538 * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER
539 * @param HSEMx HSEM Instance.
540 * @param SemaphoreMask This parameter can be a combination of the following values:
541 * @arg @ref LL_HSEM_SEMAPHORE_0
542 * @arg @ref LL_HSEM_SEMAPHORE_1
543 * @arg @ref LL_HSEM_SEMAPHORE_2
544 * @arg @ref LL_HSEM_SEMAPHORE_3
545 * @arg @ref LL_HSEM_SEMAPHORE_4
546 * @arg @ref LL_HSEM_SEMAPHORE_5
547 * @arg @ref LL_HSEM_SEMAPHORE_6
548 * @arg @ref LL_HSEM_SEMAPHORE_7
549 * @arg @ref LL_HSEM_SEMAPHORE_8
550 * @arg @ref LL_HSEM_SEMAPHORE_9
551 * @arg @ref LL_HSEM_SEMAPHORE_10
552 * @arg @ref LL_HSEM_SEMAPHORE_11
553 * @arg @ref LL_HSEM_SEMAPHORE_12
554 * @arg @ref LL_HSEM_SEMAPHORE_13
555 * @arg @ref LL_HSEM_SEMAPHORE_14
556 * @arg @ref LL_HSEM_SEMAPHORE_15
557 * @arg @ref LL_HSEM_SEMAPHORE_16
558 * @arg @ref LL_HSEM_SEMAPHORE_17
559 * @arg @ref LL_HSEM_SEMAPHORE_18
560 * @arg @ref LL_HSEM_SEMAPHORE_19
561 * @arg @ref LL_HSEM_SEMAPHORE_20
562 * @arg @ref LL_HSEM_SEMAPHORE_21
563 * @arg @ref LL_HSEM_SEMAPHORE_22
564 * @arg @ref LL_HSEM_SEMAPHORE_23
565 * @arg @ref LL_HSEM_SEMAPHORE_24
566 * @arg @ref LL_HSEM_SEMAPHORE_25
567 * @arg @ref LL_HSEM_SEMAPHORE_26
568 * @arg @ref LL_HSEM_SEMAPHORE_27
569 * @arg @ref LL_HSEM_SEMAPHORE_28
570 * @arg @ref LL_HSEM_SEMAPHORE_29
571 * @arg @ref LL_HSEM_SEMAPHORE_30
572 * @arg @ref LL_HSEM_SEMAPHORE_31
573 * @arg @ref LL_HSEM_SEMAPHORE_ALL
574 * @retval State of bit (1 or 0).
575 */
LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)576 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
577 {
578 return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
579 }
580
581 /**
582 * @}
583 */
584
585 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
586 * @{
587 */
588
589 /**
590 * @brief Clear interrupt status.
591 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
592 * @param HSEMx HSEM Instance.
593 * @param SemaphoreMask This parameter can be a combination of the following values:
594 * @arg @ref LL_HSEM_SEMAPHORE_0
595 * @arg @ref LL_HSEM_SEMAPHORE_1
596 * @arg @ref LL_HSEM_SEMAPHORE_2
597 * @arg @ref LL_HSEM_SEMAPHORE_3
598 * @arg @ref LL_HSEM_SEMAPHORE_4
599 * @arg @ref LL_HSEM_SEMAPHORE_5
600 * @arg @ref LL_HSEM_SEMAPHORE_6
601 * @arg @ref LL_HSEM_SEMAPHORE_7
602 * @arg @ref LL_HSEM_SEMAPHORE_8
603 * @arg @ref LL_HSEM_SEMAPHORE_9
604 * @arg @ref LL_HSEM_SEMAPHORE_10
605 * @arg @ref LL_HSEM_SEMAPHORE_11
606 * @arg @ref LL_HSEM_SEMAPHORE_12
607 * @arg @ref LL_HSEM_SEMAPHORE_13
608 * @arg @ref LL_HSEM_SEMAPHORE_14
609 * @arg @ref LL_HSEM_SEMAPHORE_15
610 * @arg @ref LL_HSEM_SEMAPHORE_16
611 * @arg @ref LL_HSEM_SEMAPHORE_17
612 * @arg @ref LL_HSEM_SEMAPHORE_18
613 * @arg @ref LL_HSEM_SEMAPHORE_19
614 * @arg @ref LL_HSEM_SEMAPHORE_20
615 * @arg @ref LL_HSEM_SEMAPHORE_21
616 * @arg @ref LL_HSEM_SEMAPHORE_22
617 * @arg @ref LL_HSEM_SEMAPHORE_23
618 * @arg @ref LL_HSEM_SEMAPHORE_24
619 * @arg @ref LL_HSEM_SEMAPHORE_25
620 * @arg @ref LL_HSEM_SEMAPHORE_26
621 * @arg @ref LL_HSEM_SEMAPHORE_27
622 * @arg @ref LL_HSEM_SEMAPHORE_28
623 * @arg @ref LL_HSEM_SEMAPHORE_29
624 * @arg @ref LL_HSEM_SEMAPHORE_30
625 * @arg @ref LL_HSEM_SEMAPHORE_31
626 * @arg @ref LL_HSEM_SEMAPHORE_ALL
627 * @retval None
628 */
LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)629 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
630 {
631 WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
632 }
633
634 /**
635 * @brief Get interrupt status from ISR register.
636 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
637 * @param HSEMx HSEM Instance.
638 * @param SemaphoreMask This parameter can be a combination of the following values:
639 * @arg @ref LL_HSEM_SEMAPHORE_0
640 * @arg @ref LL_HSEM_SEMAPHORE_1
641 * @arg @ref LL_HSEM_SEMAPHORE_2
642 * @arg @ref LL_HSEM_SEMAPHORE_3
643 * @arg @ref LL_HSEM_SEMAPHORE_4
644 * @arg @ref LL_HSEM_SEMAPHORE_5
645 * @arg @ref LL_HSEM_SEMAPHORE_6
646 * @arg @ref LL_HSEM_SEMAPHORE_7
647 * @arg @ref LL_HSEM_SEMAPHORE_8
648 * @arg @ref LL_HSEM_SEMAPHORE_9
649 * @arg @ref LL_HSEM_SEMAPHORE_10
650 * @arg @ref LL_HSEM_SEMAPHORE_11
651 * @arg @ref LL_HSEM_SEMAPHORE_12
652 * @arg @ref LL_HSEM_SEMAPHORE_13
653 * @arg @ref LL_HSEM_SEMAPHORE_14
654 * @arg @ref LL_HSEM_SEMAPHORE_15
655 * @arg @ref LL_HSEM_SEMAPHORE_16
656 * @arg @ref LL_HSEM_SEMAPHORE_17
657 * @arg @ref LL_HSEM_SEMAPHORE_18
658 * @arg @ref LL_HSEM_SEMAPHORE_19
659 * @arg @ref LL_HSEM_SEMAPHORE_20
660 * @arg @ref LL_HSEM_SEMAPHORE_21
661 * @arg @ref LL_HSEM_SEMAPHORE_22
662 * @arg @ref LL_HSEM_SEMAPHORE_23
663 * @arg @ref LL_HSEM_SEMAPHORE_24
664 * @arg @ref LL_HSEM_SEMAPHORE_25
665 * @arg @ref LL_HSEM_SEMAPHORE_26
666 * @arg @ref LL_HSEM_SEMAPHORE_27
667 * @arg @ref LL_HSEM_SEMAPHORE_28
668 * @arg @ref LL_HSEM_SEMAPHORE_29
669 * @arg @ref LL_HSEM_SEMAPHORE_30
670 * @arg @ref LL_HSEM_SEMAPHORE_31
671 * @arg @ref LL_HSEM_SEMAPHORE_ALL
672 * @retval State of bit (1 or 0).
673 */
LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)674 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
675 {
676 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
677 }
678
679 /**
680 * @brief Get interrupt status from MISR register.
681 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
682 * @param HSEMx HSEM Instance.
683 * @param SemaphoreMask This parameter can be a combination of the following values:
684 * @arg @ref LL_HSEM_SEMAPHORE_0
685 * @arg @ref LL_HSEM_SEMAPHORE_1
686 * @arg @ref LL_HSEM_SEMAPHORE_2
687 * @arg @ref LL_HSEM_SEMAPHORE_3
688 * @arg @ref LL_HSEM_SEMAPHORE_4
689 * @arg @ref LL_HSEM_SEMAPHORE_5
690 * @arg @ref LL_HSEM_SEMAPHORE_6
691 * @arg @ref LL_HSEM_SEMAPHORE_7
692 * @arg @ref LL_HSEM_SEMAPHORE_8
693 * @arg @ref LL_HSEM_SEMAPHORE_9
694 * @arg @ref LL_HSEM_SEMAPHORE_10
695 * @arg @ref LL_HSEM_SEMAPHORE_11
696 * @arg @ref LL_HSEM_SEMAPHORE_12
697 * @arg @ref LL_HSEM_SEMAPHORE_13
698 * @arg @ref LL_HSEM_SEMAPHORE_14
699 * @arg @ref LL_HSEM_SEMAPHORE_15
700 * @arg @ref LL_HSEM_SEMAPHORE_16
701 * @arg @ref LL_HSEM_SEMAPHORE_17
702 * @arg @ref LL_HSEM_SEMAPHORE_18
703 * @arg @ref LL_HSEM_SEMAPHORE_19
704 * @arg @ref LL_HSEM_SEMAPHORE_20
705 * @arg @ref LL_HSEM_SEMAPHORE_21
706 * @arg @ref LL_HSEM_SEMAPHORE_22
707 * @arg @ref LL_HSEM_SEMAPHORE_23
708 * @arg @ref LL_HSEM_SEMAPHORE_24
709 * @arg @ref LL_HSEM_SEMAPHORE_25
710 * @arg @ref LL_HSEM_SEMAPHORE_26
711 * @arg @ref LL_HSEM_SEMAPHORE_27
712 * @arg @ref LL_HSEM_SEMAPHORE_28
713 * @arg @ref LL_HSEM_SEMAPHORE_29
714 * @arg @ref LL_HSEM_SEMAPHORE_30
715 * @arg @ref LL_HSEM_SEMAPHORE_31
716 * @arg @ref LL_HSEM_SEMAPHORE_ALL
717 * @retval State of bit (1 or 0).
718 */
LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)719 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
720 {
721 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
722 }
723
724 /**
725 * @brief Clear interrupt status.
726 * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR
727 * @param HSEMx HSEM Instance.
728 * @param SemaphoreMask This parameter can be a combination of the following values:
729 * @arg @ref LL_HSEM_SEMAPHORE_0
730 * @arg @ref LL_HSEM_SEMAPHORE_1
731 * @arg @ref LL_HSEM_SEMAPHORE_2
732 * @arg @ref LL_HSEM_SEMAPHORE_3
733 * @arg @ref LL_HSEM_SEMAPHORE_4
734 * @arg @ref LL_HSEM_SEMAPHORE_5
735 * @arg @ref LL_HSEM_SEMAPHORE_6
736 * @arg @ref LL_HSEM_SEMAPHORE_7
737 * @arg @ref LL_HSEM_SEMAPHORE_8
738 * @arg @ref LL_HSEM_SEMAPHORE_9
739 * @arg @ref LL_HSEM_SEMAPHORE_10
740 * @arg @ref LL_HSEM_SEMAPHORE_11
741 * @arg @ref LL_HSEM_SEMAPHORE_12
742 * @arg @ref LL_HSEM_SEMAPHORE_13
743 * @arg @ref LL_HSEM_SEMAPHORE_14
744 * @arg @ref LL_HSEM_SEMAPHORE_15
745 * @arg @ref LL_HSEM_SEMAPHORE_16
746 * @arg @ref LL_HSEM_SEMAPHORE_17
747 * @arg @ref LL_HSEM_SEMAPHORE_18
748 * @arg @ref LL_HSEM_SEMAPHORE_19
749 * @arg @ref LL_HSEM_SEMAPHORE_20
750 * @arg @ref LL_HSEM_SEMAPHORE_21
751 * @arg @ref LL_HSEM_SEMAPHORE_22
752 * @arg @ref LL_HSEM_SEMAPHORE_23
753 * @arg @ref LL_HSEM_SEMAPHORE_24
754 * @arg @ref LL_HSEM_SEMAPHORE_25
755 * @arg @ref LL_HSEM_SEMAPHORE_26
756 * @arg @ref LL_HSEM_SEMAPHORE_27
757 * @arg @ref LL_HSEM_SEMAPHORE_28
758 * @arg @ref LL_HSEM_SEMAPHORE_29
759 * @arg @ref LL_HSEM_SEMAPHORE_30
760 * @arg @ref LL_HSEM_SEMAPHORE_31
761 * @arg @ref LL_HSEM_SEMAPHORE_ALL
762 * @retval None
763 */
LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)764 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
765 {
766 WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
767 }
768
769 /**
770 * @brief Get interrupt status from ISR register.
771 * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR
772 * @param HSEMx HSEM Instance.
773 * @param SemaphoreMask This parameter can be a combination of the following values:
774 * @arg @ref LL_HSEM_SEMAPHORE_0
775 * @arg @ref LL_HSEM_SEMAPHORE_1
776 * @arg @ref LL_HSEM_SEMAPHORE_2
777 * @arg @ref LL_HSEM_SEMAPHORE_3
778 * @arg @ref LL_HSEM_SEMAPHORE_4
779 * @arg @ref LL_HSEM_SEMAPHORE_5
780 * @arg @ref LL_HSEM_SEMAPHORE_6
781 * @arg @ref LL_HSEM_SEMAPHORE_7
782 * @arg @ref LL_HSEM_SEMAPHORE_8
783 * @arg @ref LL_HSEM_SEMAPHORE_9
784 * @arg @ref LL_HSEM_SEMAPHORE_10
785 * @arg @ref LL_HSEM_SEMAPHORE_11
786 * @arg @ref LL_HSEM_SEMAPHORE_12
787 * @arg @ref LL_HSEM_SEMAPHORE_13
788 * @arg @ref LL_HSEM_SEMAPHORE_14
789 * @arg @ref LL_HSEM_SEMAPHORE_15
790 * @arg @ref LL_HSEM_SEMAPHORE_16
791 * @arg @ref LL_HSEM_SEMAPHORE_17
792 * @arg @ref LL_HSEM_SEMAPHORE_18
793 * @arg @ref LL_HSEM_SEMAPHORE_19
794 * @arg @ref LL_HSEM_SEMAPHORE_20
795 * @arg @ref LL_HSEM_SEMAPHORE_21
796 * @arg @ref LL_HSEM_SEMAPHORE_22
797 * @arg @ref LL_HSEM_SEMAPHORE_23
798 * @arg @ref LL_HSEM_SEMAPHORE_24
799 * @arg @ref LL_HSEM_SEMAPHORE_25
800 * @arg @ref LL_HSEM_SEMAPHORE_26
801 * @arg @ref LL_HSEM_SEMAPHORE_27
802 * @arg @ref LL_HSEM_SEMAPHORE_28
803 * @arg @ref LL_HSEM_SEMAPHORE_29
804 * @arg @ref LL_HSEM_SEMAPHORE_30
805 * @arg @ref LL_HSEM_SEMAPHORE_31
806 * @arg @ref LL_HSEM_SEMAPHORE_ALL
807 * @retval State of bit (1 or 0).
808 */
LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)809 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
810 {
811 return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
812 }
813
814 /**
815 * @brief Get interrupt status from MISR register.
816 * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR
817 * @param HSEMx HSEM Instance.
818 * @param SemaphoreMask This parameter can be a combination of the following values:
819 * @arg @ref LL_HSEM_SEMAPHORE_0
820 * @arg @ref LL_HSEM_SEMAPHORE_1
821 * @arg @ref LL_HSEM_SEMAPHORE_2
822 * @arg @ref LL_HSEM_SEMAPHORE_3
823 * @arg @ref LL_HSEM_SEMAPHORE_4
824 * @arg @ref LL_HSEM_SEMAPHORE_5
825 * @arg @ref LL_HSEM_SEMAPHORE_6
826 * @arg @ref LL_HSEM_SEMAPHORE_7
827 * @arg @ref LL_HSEM_SEMAPHORE_8
828 * @arg @ref LL_HSEM_SEMAPHORE_9
829 * @arg @ref LL_HSEM_SEMAPHORE_10
830 * @arg @ref LL_HSEM_SEMAPHORE_11
831 * @arg @ref LL_HSEM_SEMAPHORE_12
832 * @arg @ref LL_HSEM_SEMAPHORE_13
833 * @arg @ref LL_HSEM_SEMAPHORE_14
834 * @arg @ref LL_HSEM_SEMAPHORE_15
835 * @arg @ref LL_HSEM_SEMAPHORE_16
836 * @arg @ref LL_HSEM_SEMAPHORE_17
837 * @arg @ref LL_HSEM_SEMAPHORE_18
838 * @arg @ref LL_HSEM_SEMAPHORE_19
839 * @arg @ref LL_HSEM_SEMAPHORE_20
840 * @arg @ref LL_HSEM_SEMAPHORE_21
841 * @arg @ref LL_HSEM_SEMAPHORE_22
842 * @arg @ref LL_HSEM_SEMAPHORE_23
843 * @arg @ref LL_HSEM_SEMAPHORE_24
844 * @arg @ref LL_HSEM_SEMAPHORE_25
845 * @arg @ref LL_HSEM_SEMAPHORE_26
846 * @arg @ref LL_HSEM_SEMAPHORE_27
847 * @arg @ref LL_HSEM_SEMAPHORE_28
848 * @arg @ref LL_HSEM_SEMAPHORE_29
849 * @arg @ref LL_HSEM_SEMAPHORE_30
850 * @arg @ref LL_HSEM_SEMAPHORE_31
851 * @arg @ref LL_HSEM_SEMAPHORE_ALL
852 * @retval State of bit (1 or 0).
853 */
LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)854 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
855 {
856 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
857 }
858 /**
859 * @}
860 */
861
862 /**
863 * @}
864 */
865
866 /**
867 * @}
868 */
869
870 #endif /* defined(HSEM) */
871
872 /**
873 * @}
874 */
875
876 #ifdef __cplusplus
877 }
878 #endif
879
880 #endif /* __STM32WBxx_LL_HSEM_H */
881
