1 /** 2 ****************************************************************************** 3 * @file stm32u5xx.h 4 * @author MCD Application Team 5 * @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File. 6 * 7 * The file is the unique include file that the application programmer 8 * is using in the C source code, usually in main.c. This file contains: 9 * - Configuration section that allows to select: 10 * - The STM32U5xx device used in the target application 11 * - To use or not the peripheral's drivers in application code(i.e. 12 * code will be based on direct access to peripheral's registers 13 * rather than drivers API), this option is controlled by 14 * "#define USE_HAL_DRIVER" 15 * 16 ****************************************************************************** 17 * @attention 18 * 19 * Copyright (c) 2021 STMicroelectronics. 20 * All rights reserved. 21 * 22 * This software is licensed under terms that can be found in the LICENSE file 23 * in the root directory of this software component. 24 * If no LICENSE file comes with this software, it is provided AS-IS. 25 * 26 ****************************************************************************** 27 */ 28 29 /** @addtogroup CMSIS 30 * @{ 31 */ 32 33 /** @addtogroup stm32u5xx 34 * @{ 35 */ 36 37 #ifndef STM32U5xx_H 38 #define STM32U5xx_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif /* __cplusplus */ 43 44 /** @addtogroup Library_configuration_section 45 * @{ 46 */ 47 48 /** 49 * @brief STM32 Family 50 */ 51 #if !defined (STM32U5) 52 #define STM32U5 53 #endif /* STM32U5 */ 54 55 /* Uncomment the line below according to the target STM32U5 device used in your 56 application 57 */ 58 59 #if !defined (STM32U575xx) && !defined (STM32U585xx) \ 60 && !defined (STM32U595xx) && !defined (STM32U599xx) \ 61 && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \ 62 && !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \ 63 && !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \ 64 && !defined (STM32U535xx) && !defined (STM32U545xx) \ 65 /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ 66 /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ 67 /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ 68 /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ 69 /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ 70 /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ 71 /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ 72 /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ 73 /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ 74 /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ 75 /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ 76 /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ 77 #endif 78 79 /* Tip: To avoid modifying this file each time you need to switch between these 80 devices, you can define the device in your toolchain compiler preprocessor. 81 */ 82 #if !defined (USE_HAL_DRIVER) 83 /** 84 * @brief Comment the line below if you will not use the peripherals drivers. 85 In this case, these drivers will not be included and the application code will 86 be based on direct access to peripherals registers 87 */ 88 /*#define USE_HAL_DRIVER */ 89 #endif /* USE_HAL_DRIVER */ 90 91 /** 92 * @brief CMSIS Device version number 1.3.1 93 */ 94 #define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ 95 #define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ 96 #define __STM32U5_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ 97 #define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ 98 #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ 99 |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ 100 |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\ 101 |(__STM32U5_CMSIS_VERSION_RC)) 102 103 /** 104 * @} 105 */ 106 107 /** @addtogroup Device_Included 108 * @{ 109 */ 110 111 #if defined(STM32U575xx) 112 #include "stm32u575xx.h" 113 #elif defined(STM32U585xx) 114 #include "stm32u585xx.h" 115 #elif defined(STM32U595xx) 116 #include "stm32u595xx.h" 117 #elif defined(STM32U599xx) 118 #include "stm32u599xx.h" 119 #elif defined(STM32U5A5xx) 120 #include "stm32u5a5xx.h" 121 #elif defined(STM32U5A9xx) 122 #include "stm32u5a9xx.h" 123 #elif defined(STM32U5F9xx) 124 #include "stm32u5f9xx.h" 125 #elif defined(STM32U5G9xx) 126 #include "stm32u5g9xx.h" 127 #elif defined(STM32U5F7xx) 128 #include "stm32u5f7xx.h" 129 #elif defined(STM32U5G7xx) 130 #include "stm32u5g7xx.h" 131 #elif defined(STM32U535xx) 132 #include "stm32u535xx.h" 133 #elif defined(STM32U545xx) 134 #include "stm32u545xx.h" 135 #else 136 #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" 137 #endif 138 139 /** 140 * @} 141 */ 142 143 /** @addtogroup Exported_types 144 * @{ 145 */ 146 typedef enum 147 { 148 RESET = 0, 149 SET = !RESET 150 } FlagStatus, ITStatus; 151 152 typedef enum 153 { 154 DISABLE = 0, 155 ENABLE = !DISABLE 156 } FunctionalState; 157 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 158 159 typedef enum 160 { 161 SUCCESS = 0, 162 ERROR = !SUCCESS 163 } ErrorStatus; 164 165 /** 166 * @} 167 */ 168 169 170 /** @addtogroup Exported_macros 171 * @{ 172 */ 173 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 174 175 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 176 177 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 178 179 #define CLEAR_REG(REG) ((REG) = (0x0)) 180 181 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 182 183 #define READ_REG(REG) ((REG)) 184 185 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 186 187 /* Use of CMSIS compiler intrinsics for register exclusive access */ 188 /* Atomic 32-bit register access macro to set one or several bits */ 189 #define ATOMIC_SET_BIT(REG, BIT) \ 190 do { \ 191 uint32_t val; \ 192 do { \ 193 val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ 194 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 195 } while(0) 196 197 /* Atomic 32-bit register access macro to clear one or several bits */ 198 #define ATOMIC_CLEAR_BIT(REG, BIT) \ 199 do { \ 200 uint32_t val; \ 201 do { \ 202 val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ 203 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 204 } while(0) 205 206 /* Atomic 32-bit register access macro to clear and set one or several bits */ 207 #define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ 208 do { \ 209 uint32_t val; \ 210 do { \ 211 val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 212 } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ 213 } while(0) 214 215 /* Atomic 16-bit register access macro to set one or several bits */ 216 #define ATOMIC_SETH_BIT(REG, BIT) \ 217 do { \ 218 uint16_t val; \ 219 do { \ 220 val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ 221 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 222 } while(0) 223 224 /* Atomic 16-bit register access macro to clear one or several bits */ 225 #define ATOMIC_CLEARH_BIT(REG, BIT) \ 226 do { \ 227 uint16_t val; \ 228 do { \ 229 val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ 230 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 231 } while(0) 232 233 /* Atomic 16-bit register access macro to clear and set one or several bits */ 234 #define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ 235 do { \ 236 uint16_t val; \ 237 do { \ 238 val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ 239 } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ 240 } while(0) 241 242 #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 243 244 245 /** 246 * @} 247 */ 248 249 #if defined (USE_HAL_DRIVER) 250 #include "stm32u5xx_hal.h" 251 #endif /* USE_HAL_DRIVER */ 252 253 #ifdef __cplusplus 254 } 255 #endif /* __cplusplus */ 256 257 #endif /* STM32U5xx_H */ 258 /** 259 * @} 260 */ 261 262 /** 263 * @} 264 */ 265 266 267 268 269
