1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extended peripheral:
8 * + Extended Peripheral Control functions
9 * + Extended Clock management functions
10 * + Extended Clock Recovery System Control functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 */
24
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32u5xx_hal.h"
27
28 /** @addtogroup STM32U5xx_HAL_Driver
29 * @{
30 */
31
32 /** @defgroup RCCEx RCCEx
33 * @brief RCC Extended HAL module driver
34 * @{
35 */
36
37 #ifdef HAL_RCC_MODULE_ENABLED
38
39 /* Private typedef -----------------------------------------------------------*/
40 /* Private defines -----------------------------------------------------------*/
41 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
42 * @{
43 */
44 #define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
45 #define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
46 #define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
47
48 /* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
49 #if defined (STM32U585xx) || defined (STM32U575xx)
50 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */
51 #else
52 #define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */
53 #endif /* STM32U585xx || STM32U575xx */
54
55 /* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */
56 #define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */
57
58 /**
59 * @}
60 */
61
62 /* Private macros ------------------------------------------------------------*/
63 /** @addtogroup RCCEx_Private_Macros
64 * @{
65 */
66
67 #define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
68
69 #define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U))
70
71 #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
72 ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
73
74 #define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \
75 ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL))
76
77 #define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
78 (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
79
80 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
81 (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
82 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
83 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \
84 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE))
85
86 #if defined(USART2)
87 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
88 (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
89 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
90 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \
91 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE))
92 #endif /* USART2 */
93
94 #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
95 (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
96 ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
97 ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \
98 ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE))
99
100 #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
101 (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
102 ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
103 ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \
104 ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE))
105
106 #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
107 (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
108 ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
109 ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \
110 ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE))
111
112 #if defined(USART6)
113 #define IS_RCC_USART6CLKSOURCE(__SOURCE__) \
114 (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \
115 ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \
116 ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \
117 ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE))
118 #endif /* USART6 */
119
120 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
121 (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \
122 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
123 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \
124 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
125 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK))
126
127 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
128 (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
129 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
130 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \
131 ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK))
132
133 #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
134 (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
135 ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
136 ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \
137 ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK))
138
139 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
140 (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \
141 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \
142 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \
143 ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK))
144
145 #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
146 (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
147 ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
148 ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \
149 ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK))
150
151 #if defined(I2C5)
152 #define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \
153 (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \
154 ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \
155 ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \
156 ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK))
157 #endif /* I2C5 */
158
159 #if defined(I2C6)
160 #define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \
161 (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \
162 ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \
163 ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \
164 ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK))
165 #endif /* I2C6 */
166
167 #define IS_RCC_SAI1CLK(__SOURCE__) \
168 (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \
169 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \
170 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \
171 ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \
172 ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
173
174 #if defined(SAI2)
175 #define IS_RCC_SAI2CLK(__SOURCE__) \
176 (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \
177 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \
178 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \
179 ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \
180 ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI))
181 #endif /* SAI2 */
182
183 #define IS_RCC_LPTIM1CLK(__SOURCE__) \
184 (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \
185 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
186 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
187 ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
188
189 #define IS_RCC_LPTIM2CLK(__SOURCE__) \
190 (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
191 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \
192 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
193 ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
194
195 #define IS_RCC_LPTIM34CLK(__SOURCE__) \
196 (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \
197 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \
198 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \
199 ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE))
200
201 #define IS_RCC_FDCAN1CLK(__SOURCE__) \
202 (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \
203 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \
204 ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2))
205
206 #define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \
207 (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \
208 ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1))
209
210 #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
211 (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
212 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \
213 ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI))
214
215 #if defined(SAES)
216 #define IS_RCC_SAESCLKSOURCE(__SOURCE__) \
217 (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \
218 ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2))
219 #endif /* SAES */
220
221 #define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \
222 (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \
223 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \
224 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \
225 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \
226 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \
227 ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK))
228
229 #define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \
230 (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \
231 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \
232 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \
233 ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \
234 ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK))
235
236 #define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \
237 (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \
238 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \
239 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \
240 ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \
241 ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK))
242
243 #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \
244 (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \
245 ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \
246 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\
247 ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2))
248
249 #if defined(HSPI1)
250 #define IS_RCC_HSPICLKSOURCE(__SOURCE__) \
251 (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \
252 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \
253 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \
254 ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3))
255 #endif /* HSPI1 */
256
257 #define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\
258 (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \
259 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \
260 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \
261 ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK))
262
263 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
264 (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \
265 ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \
266 ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \
267 ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK))
268
269 #define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \
270 (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \
271 ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \
272 ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \
273 ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK))
274
275 #define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \
276 (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \
277 ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \
278 ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \
279 ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK))
280
281 #define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \
282 (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \
283 ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI))
284
285 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
286 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
287 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
288 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
289
290 #if defined(LTDC)
291
292 #define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \
293 (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \
294 ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2))
295
296 #endif /* LTDC */
297
298 #if defined(DSI)
299
300 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \
301 (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \
302 ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY))
303
304 #endif /* DSI */
305
306 #if defined(USB_OTG_HS)
307
308 #define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \
309 (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \
310 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \
311 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \
312 ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2))
313
314 #endif /* USB_OTG_HS */
315
316 #if defined(CRS)
317
318 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
319 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
320 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
321
322 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
323 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
324 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
325 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
326
327 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
328 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
329
330 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
331
332 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
333
334 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
335
336 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
337 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
338
339 #endif /* CRS */
340
341 /**
342 * @}
343 */
344
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347 /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
348 * @{
349 */
350 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource);
351 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2);
352 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3);
353 /**
354 * @}
355 */
356
357 /* Exported functions --------------------------------------------------------*/
358
359 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
360 * @{
361 */
362
363 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
364 * @brief Extended Peripheral Control functions
365 *
366 @verbatim
367 ===============================================================================
368 ##### Extended Peripheral Control functions #####
369 ===============================================================================
370 [..]
371 This subsection provides a set of functions allowing to control the RCC Clocks
372 frequencies.
373 [..]
374 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
375 select the RTC clock source; in this case the Backup domain will be reset in
376 order to modify the RTC Clock source, as consequence RTC registers (including
377 the backup registers) are set to their reset values.
378
379 @endverbatim
380 * @{
381 */
382 /**
383 * @brief Initialize the RCC extended peripherals clocks according to the specified
384 * parameters in the RCC_PeriphCLKInitTypeDef.
385 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
386 * contains a field PeriphClockSelection which can be a combination of the following values:
387 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
388 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
389 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
390 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
391 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
392 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
393 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
394 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
395 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
396 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
397 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
398 * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock
399 * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock
400 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
401 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
402 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
403 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
404 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
405 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
406 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
407 * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
408 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
409 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
410 * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
411 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock
412 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
413 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
414 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
415 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
416 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
417 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
418 * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock
419 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock
420 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
421 * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
422 *
423 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
424 * the RTC clock source: in this case the access to Backup domain is enabled.
425 *
426 * @retval HAL status
427 *
428 * (*) value not defined in all devices.
429 */
HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef * pPeriphClkInit)430 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
431 {
432 uint32_t tmpregister;
433 uint32_t tickstart;
434 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
435 HAL_StatusTypeDef status = HAL_OK; /* Final status */
436
437 /* Check the parameters */
438 assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection));
439
440 /*-------------------------- USART1 clock source configuration -------------------*/
441 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
442 {
443 /* Check the parameters */
444 assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection));
445
446 /* Configure the USART1 clock source */
447 __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection);
448 }
449
450 #if defined(USART2)
451 /*-------------------------- USART2 clock source configuration -------------------*/
452 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
453 {
454 /* Check the parameters */
455 assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection));
456
457 /* Configure the USART2 clock source */
458 __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection);
459 }
460 #endif /* USART2 */
461
462 /*-------------------------- USART3 clock source configuration -------------------*/
463 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
464 {
465 /* Check the parameters */
466 assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection));
467
468 /* Configure the USART3 clock source */
469 __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection);
470 }
471
472 /*-------------------------- UART4 clock source configuration --------------------*/
473 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
474 {
475 /* Check the parameters */
476 assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection));
477
478 /* Configure the UART4 clock source */
479 __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection);
480 }
481
482 /*-------------------------- UART5 clock source configuration --------------------*/
483 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
484 {
485 /* Check the parameters */
486 assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection));
487
488 /* Configure the UART5 clock source */
489 __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection);
490 }
491 #if defined(USART6)
492 /*-------------------------- USART6 clock source configuration -------------------*/
493 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6)
494 {
495 /* Check the parameters */
496 assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection));
497
498 /* Configure the USART6 clock source */
499 __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection);
500 }
501 #endif /* USART6 */
502
503 /*-------------------------- LPUART1 clock source configuration ------------------*/
504 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
505 {
506 /* Check the parameters */
507 assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection));
508
509 /* Configure the LPUART1 clock source */
510 __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection);
511 }
512
513 /*-------------------------- I2C1 clock source configuration ---------------------*/
514 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
515 {
516 /* Check the parameters */
517 assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection));
518
519 /* Configure the I2C1 clock source */
520 __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection);
521 }
522
523 /*-------------------------- I2C2 clock source configuration ---------------------*/
524 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
525 {
526 /* Check the parameters */
527 assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection));
528
529 /* Configure the I2C2 clock source */
530 __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection);
531 }
532
533 /*-------------------------- I2C3 clock source configuration ---------------------*/
534 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
535 {
536 /* Check the parameters */
537 assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection));
538
539 /* Configure the I2C3 clock source */
540 __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection);
541 }
542
543 /*-------------------------- I2C4 clock source configuration ---------------------*/
544 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
545 {
546 /* Check the parameters */
547 assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection));
548
549 /* Configure the I2C4 clock source */
550 __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection);
551 }
552
553 #if defined(I2C5)
554 /*-------------------------- I2C5 clock source configuration ---------------------*/
555 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5)
556 {
557 /* Check the parameters */
558 assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection));
559
560 /* Configure the I2C5 clock source */
561 __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection);
562 }
563 #endif /* I2C5 */
564
565 #if defined(I2C6)
566 /*-------------------------- I2C6 clock source configuration ---------------------*/
567 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6)
568 {
569 /* Check the parameters */
570 assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection));
571
572 /* Configure the I2C6 clock source */
573 __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection);
574 }
575 #endif /* I2C6 */
576
577 /*-------------------------- LPTIM1 clock source configuration -------------------*/
578 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
579 {
580 assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection));
581 __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection);
582 }
583
584 /*-------------------------- LPTIM2 clock source configuration -------------------*/
585 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
586 {
587 assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection));
588 __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection);
589 }
590
591 /*-------------------------- LPTIM34 clock source configuration -------------------*/
592 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34))
593 {
594 assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection));
595 __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection);
596 }
597
598 /*-------------------------- SAI1 clock source configuration ---------------------*/
599 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
600 {
601 /* Check the parameters */
602 assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection));
603
604 switch (pPeriphClkInit->Sai1ClockSelection)
605 {
606 case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/
607 /* Enable SAI Clock output generated from System PLL */
608 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
609 /* SAI1 clock source config set later after clock selection check */
610 break;
611
612 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
613 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
614 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
615 /* SAI1 clock source config set later after clock selection check */
616 break;
617
618 case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/
619 /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */
620 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
621 /* SAI1 clock source config set later after clock selection check */
622 break;
623
624 case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/
625 /* SAI1 clock source configuration done later after clock selection check */
626 break;
627
628 case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/
629 /* SAI1 clock source config set later after clock selection check */
630 break;
631
632 default:
633 ret = HAL_ERROR;
634 break;
635 }
636
637 if (ret == HAL_OK)
638 {
639 /* Set the source of SAI1 clock*/
640 __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection);
641 }
642 else
643 {
644 /* set overall return value */
645 status = ret;
646 }
647 }
648
649 #if defined(SAI2)
650 /*-------------------------- SAI2 clock source configuration ---------------------*/
651 if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
652 {
653 /* Check the parameters */
654 assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection));
655
656 switch (pPeriphClkInit->Sai2ClockSelection)
657 {
658 case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/
659 /* Enable SAI Clock output generated from System PLL */
660 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
661 /* SAI2 clock source config set later after clock selection check */
662 break;
663
664 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
665 /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
666 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
667 /* SAI2 clock source config set later after clock selection check */
668 break;
669
670 case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/
671 /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
672 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
673 /* SAI2 clock source config set later after clock selection check */
674 break;
675
676 case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/
677 /* SAI2 clock source configuration done later after clock selection check */
678 break;
679 case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/
680 /* SAI2 clock source config set later after clock selection check */
681 break;
682
683 default:
684 ret = HAL_ERROR;
685 break;
686 }
687
688 if (ret == HAL_OK)
689 {
690 /* Set the source of SAI2 clock*/
691 __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection);
692 }
693 else
694 {
695 /* set overall return value */
696 status = ret;
697 }
698 }
699 #endif /* SAI2 */
700
701 /*-------------------------- ADCDAC clock source configuration ----------------------*/
702 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC)
703 {
704 /* Check the parameters */
705 assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection));
706
707 switch (pPeriphClkInit->AdcDacClockSelection)
708 {
709 case RCC_ADCDACCLKSOURCE_PLL2:
710 /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */
711 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
712 break;
713
714 case RCC_ADCDACCLKSOURCE_SYSCLK:
715 case RCC_ADCDACCLKSOURCE_HCLK:
716 case RCC_ADCDACCLKSOURCE_HSE:
717 case RCC_ADCDACCLKSOURCE_HSI:
718 case RCC_ADCDACCLKSOURCE_MSIK:
719 break;
720 default:
721 ret = HAL_ERROR;
722 break;
723 }
724
725 if (ret == HAL_OK)
726 {
727 /* Configure the ADC1 interface clock source */
728 __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection);
729 }
730 else
731 {
732 /* set overall return value */
733 status = ret;
734 }
735 }
736
737 /*-------------------------- MDF1 clock source configuration -------------------*/
738 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1)
739 {
740 /* Check the parameters */
741 assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection));
742
743 switch (pPeriphClkInit->Mdf1ClockSelection)
744 {
745 case RCC_MDF1CLKSOURCE_PLL1:
746 /* Enable PLL1 Clock output generated from System PLL */
747 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
748 break;
749 case RCC_MDF1CLKSOURCE_PLL3:
750 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
751 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
752 break;
753 case RCC_MDF1CLKSOURCE_HCLK:
754 break;
755 case RCC_MDF1CLKSOURCE_PIN:
756 break;
757 case RCC_MDF1CLKSOURCE_MSIK:
758 break;
759 default:
760 ret = HAL_ERROR;
761 break;
762 }
763 if (ret == HAL_OK)
764 {
765 /* Configure the MDF1 interface clock source */
766 __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection);
767 }
768 else
769 {
770 /* set overall return value */
771 status = ret;
772 }
773 }
774
775 /*-------------------------- ADF1 clock source configuration -------------------*/
776 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1)
777 {
778 /* Check the parameters */
779 assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection));
780 switch (pPeriphClkInit->Adf1ClockSelection)
781 {
782 case RCC_ADF1CLKSOURCE_PLL1:
783 /* Enable PLL1 Clock output generated from System PLL */
784 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
785 break;
786 case RCC_ADF1CLKSOURCE_PLL3:
787 /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */
788 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
789 break;
790 case RCC_ADF1CLKSOURCE_HCLK:
791 break;
792 case RCC_ADF1CLKSOURCE_PIN:
793 break;
794 case RCC_ADF1CLKSOURCE_MSIK:
795 break;
796 default:
797 ret = HAL_ERROR;
798 break;
799 }
800 if (ret == HAL_OK)
801 {
802 /* Configure the ADF1 interface clock source */
803 __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection);
804 }
805 else
806 {
807 /* set overall return value */
808 status = ret;
809 }
810 }
811
812 /*-------------------------- RTC clock source configuration ----------------------*/
813 if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
814 {
815 FlagStatus pwrclkchanged = RESET;
816 /* Check for RTC Parameters used to output RTCCLK */
817 assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection));
818 /* Enable Power Clock */
819 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
820 {
821 __HAL_RCC_PWR_CLK_ENABLE();
822 pwrclkchanged = SET;
823 }
824 /* Enable write access to Backup domain */
825 SET_BIT(PWR->DBPR, PWR_DBPR_DBP);
826
827 /* Wait for Backup domain Write protection disable */
828 tickstart = HAL_GetTick();
829
830 while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
831 {
832 if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
833 {
834 ret = HAL_TIMEOUT;
835 break;
836 }
837 }
838
839 if (ret == HAL_OK)
840 {
841 /* Reset the Backup domain only if the RTC Clock source selection is modified from default */
842 tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
843
844 if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection))
845 {
846 /* Store the content of BDCR register before the reset of Backup Domain */
847 tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
848 /* RTC Clock selection can be changed only if the Backup Domain is reset */
849 __HAL_RCC_BACKUPRESET_FORCE();
850 __HAL_RCC_BACKUPRESET_RELEASE();
851 /* Restore the Content of BDCR register */
852 RCC->BDCR = tmpregister;
853 }
854
855 /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
856 if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
857 {
858 /* Get Start Tick*/
859 tickstart = HAL_GetTick();
860
861 /* Wait till LSE is ready */
862 while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
863 {
864 if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
865 {
866 ret = HAL_TIMEOUT;
867 break;
868 }
869 }
870 }
871
872 if (ret == HAL_OK)
873 {
874 /* Apply new RTC clock source selection */
875 __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection);
876 }
877 else
878 {
879 /* set overall return value */
880 status = ret;
881 }
882 }
883 else
884 {
885 /* set overall return value */
886 status = ret;
887 }
888
889 /* Restore clock configuration if changed */
890 if (pwrclkchanged == SET)
891 {
892 __HAL_RCC_PWR_CLK_DISABLE();
893 }
894 }
895
896 /*-------------------------------------- ICLK Configuration -----------------------------------*/
897 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK)
898 {
899 /* Check the parameters */
900 assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection));
901
902 switch (pPeriphClkInit->IclkClockSelection)
903 {
904 case RCC_ICLK_CLKSOURCE_PLL2:
905 /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */
906 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
907 break;
908 case RCC_ICLK_CLKSOURCE_PLL1:
909 /* Enable ICLK Clock output generated from System PLL */
910 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
911 break;
912 case RCC_ICLK_CLKSOURCE_HSI48:
913 break;
914 case RCC_ICLK_CLKSOURCE_MSIK:
915 break;
916 default:
917 ret = HAL_ERROR;
918 break;
919 }
920 if (ret == HAL_OK)
921 {
922 /* Configure the CLK48 source */
923 __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection);
924 }
925 else
926 {
927 /* set overall return value */
928 status = ret;
929 }
930 }
931
932 /*------------------------------ RNG Configuration -------------------------*/
933 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
934 {
935
936 /* Check the parameters */
937 assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection));
938
939 switch (pPeriphClkInit->RngClockSelection)
940 {
941 case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/
942 /* RNG clock source configuration done later after clock selection check */
943 break;
944 case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/
945 /* RNG clock source configuration done later after clock selection check */
946 break;
947 case RCC_RNGCLKSOURCE_HSI48:
948 /* HSI48 oscillator is used as source of RNG clock */
949 /* RNG clock source configuration done later after clock selection check */
950 break;
951 default:
952 ret = HAL_ERROR;
953 break;
954 }
955 if (ret == HAL_OK)
956 {
957 /* Set the source of RNG clock*/
958 __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection);
959 }
960 else
961 {
962 /* set overall return value */
963 status = ret;
964 }
965 }
966
967 #if defined(SAES)
968 /*-------------------------- SAES clock source configuration ----------------*/
969 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES)
970 {
971 /* Check the parameters */
972 assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection));
973
974 /* Configure the SAES clock source */
975 __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection);
976 }
977 #endif /* SAES */
978
979 /*-------------------------- SDMMC1/2 clock source configuration -------------------*/
980 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC))
981 {
982 /* Check the parameters */
983 assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection));
984
985 if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1)
986 {
987 /* Enable PLL1 P CLK output */
988 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
989 }
990
991 /* Configure the SDMMC1/2 clock source */
992 __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection);
993 }
994
995 /*-------------------------- SPI1 clock source configuration ----------------*/
996 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1)
997 {
998 /* Check the parameters */
999 assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection));
1000
1001 /* Configure the SPI1 clock source */
1002 __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection);
1003 }
1004
1005 /*-------------------------- SPI2 clock source configuration ----------------*/
1006 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2)
1007 {
1008 /* Check the parameters */
1009 assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection));
1010
1011 /* Configure the SPI2 clock source */
1012 __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection);
1013 }
1014
1015 /*-------------------------- SPI3 clock source configuration ----------------*/
1016 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3)
1017 {
1018 /* Check the parameters */
1019 assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection));
1020
1021 /* Configure the SPI3 clock source */
1022 __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection);
1023 }
1024
1025 /*-------------------------- OctoSPIx clock source configuration ----------------*/
1026 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
1027 {
1028 /* Check the parameters */
1029 assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection));
1030
1031 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1)
1032 {
1033 /* Enable PLL1 Q CLK output */
1034 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1035 }
1036 if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2)
1037 {
1038 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
1039 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1040 }
1041 if (ret == HAL_OK)
1042 {
1043 /* Configure the OctoSPI clock source */
1044 __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection);
1045 }
1046 else
1047 {
1048 /* set overall return value */
1049 status = ret;
1050 }
1051 }
1052
1053 #if defined(HSPI1)
1054 /*-------------------------- HSPIx kernel clock source configuration ----------------*/
1055 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI)
1056 {
1057
1058 /* Check the parameters */
1059 assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection));
1060
1061 switch (pPeriphClkInit->HspiClockSelection)
1062 {
1063 case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/
1064 /* HSPI kernel clock source config set later after clock selection check */
1065 break;
1066
1067 case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/
1068 /* Enable 48M2 Clock output generated from System PLL . */
1069 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1070 /* HSPI kernel clock source config set later after clock selection check */
1071 break;
1072
1073 case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/
1074 /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */
1075 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1076 /* HSPI kernel clock source config set later after clock selection check */
1077 break;
1078
1079 case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/
1080 /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */
1081 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1082 /* HSPI kernel clock source config set later after clock selection check */
1083 break;
1084
1085 default:
1086 ret = HAL_ERROR;
1087 break;
1088 }
1089
1090 if (ret == HAL_OK)
1091 {
1092 /* Set the source of HSPI kernel clock*/
1093 __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection);
1094 }
1095 else
1096 {
1097 /* set overall return value */
1098 status = ret;
1099 }
1100 }
1101 #endif /* defined(HSPI1) */
1102
1103 /*-------------------------- FDCAN1 kernel clock source configuration -------------*/
1104 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1))
1105 {
1106 assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection));
1107
1108 switch (pPeriphClkInit->Fdcan1ClockSelection)
1109 {
1110 case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/
1111 /* FDCAN1 kernel clock source config set later after clock selection check */
1112 break;
1113 case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/
1114 /* Enable 48M2 Clock output generated from System PLL */
1115 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
1116 /* FDCAN1 kernel clock source config set later after clock selection check */
1117 break;
1118 case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/
1119 /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1120 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1121 /* FDCAN1 kernel clock source config set later after clock selection check */
1122 break;
1123 default:
1124 ret = HAL_ERROR;
1125 break;
1126 }
1127 if (ret == HAL_OK)
1128 {
1129 /* Set the source of FDCAN1 kernel clock*/
1130 __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection);
1131 }
1132 else
1133 {
1134 /* set overall return value */
1135 status = ret;
1136 }
1137 }
1138
1139 /*-------------------------- DAC1 clock source configuration ----------------*/
1140 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1)
1141 {
1142
1143 /* Check the parameters */
1144 assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection));
1145
1146 /* Configure the DAC1 clock source */
1147 __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection);
1148 }
1149
1150 #if defined(LTDC)
1151
1152 /*-------------------------- LTDC clock source configuration ----------------*/
1153 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
1154 {
1155
1156 /* Check the parameters */
1157 assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection));
1158
1159 switch (pPeriphClkInit->LtdcClockSelection)
1160 {
1161 case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/
1162 /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */
1163 ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2));
1164 /* LTDC clock source config set later after clock selection check */
1165 break;
1166
1167 case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/
1168 /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1169 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1170 /* LTDC clock source config set later after clock selection check */
1171 break;
1172
1173 default:
1174 ret = HAL_ERROR;
1175 break;
1176 }
1177
1178 if (ret == HAL_OK)
1179 {
1180 /* Set the source of LTDC clock*/
1181 __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection);
1182 }
1183 else
1184 {
1185 /* set overall return value */
1186 status = ret;
1187 }
1188 }
1189
1190 #endif /* defined(LTDC) */
1191
1192 #if defined(DSI)
1193
1194 /*-------------------------- DSI clock source configuration ----------------*/
1195 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
1196 {
1197
1198 /* Check the parameters */
1199 assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection));
1200
1201 if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3)
1202 {
1203 /* PLL3 is used as clock source for DSI clock*/
1204 /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */
1205 ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));
1206 }
1207
1208 if (ret == HAL_OK)
1209 {
1210 /* Set the source of DSI clock*/
1211 __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection);
1212 }
1213 else
1214 {
1215 /* set overall return value */
1216 status = ret;
1217 }
1218 }
1219
1220 #endif /* defined(DSI) */
1221
1222 #if defined(USB_OTG_HS)
1223
1224 /*-------------------------- USB PHY clock source configuration ----------------*/
1225 if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY)
1226 {
1227
1228 /* Check the parameters */
1229 assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection));
1230
1231 switch (pPeriphClkInit->UsbPhyClockSelection)
1232 {
1233 case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/
1234 case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/
1235 /* USB-PHY clock source config set later after clock selection check */
1236 break;
1237
1238 case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */
1239 case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */
1240 /* Enable P Clock output generated from System PLL . */
1241 __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
1242 /* USB-PHY clock source config set later after clock selection check */
1243 break;
1244
1245 default:
1246 ret = HAL_ERROR;
1247 break;
1248 }
1249
1250 if (ret == HAL_OK)
1251 {
1252 /* Set the source of USBPHY clock*/
1253 __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection);
1254 }
1255 else
1256 {
1257 /* set overall return value */
1258 status = ret;
1259 }
1260 }
1261
1262 #endif /* defined(USB_OTG_HS) */
1263
1264 return status;
1265 }
1266
1267
1268
1269 /**
1270 * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
1271 * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
1272 * returns the configuration information for the Extended Peripherals
1273 * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2,
1274 * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1).
1275 * @retval None
1276 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * pPeriphClkInit)1277 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit)
1278 {
1279 /* Set all possible values for the extended clock type parameter------------*/
1280 #if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx))
1281 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1282 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
1283 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1284 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
1285 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1286 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
1287 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
1288 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
1289 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
1290 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
1291 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \
1292 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY;
1293 #elif (defined(STM32U595xx) || defined(STM32U5A5xx))
1294 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1295 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \
1296 RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1297 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \
1298 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1299 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \
1300 RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \
1301 RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \
1302 RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \
1303 RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \
1304 RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY;
1305 #elif (defined(STM32U585xx) || defined(STM32U575xx))
1306 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1307 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \
1308 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \
1309 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1310 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \
1311 RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \
1312 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \
1313 RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \
1314 RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \
1315 RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
1316
1317 #else
1318 pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \
1319 RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \
1320 RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \
1321 RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \
1322 RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \
1323 RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \
1324 RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \
1325 RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \
1326 RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1;
1327 #endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */
1328
1329 #if defined(SAES)
1330 pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES;
1331 #endif /* SAES */
1332
1333 /* Get the PLL2 Clock configuration -----------------------------------------------*/
1334 pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos);
1335 pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1336 pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U;
1337 pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U;
1338 pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U;
1339 pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U;
1340 pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos);
1341 pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1342 RCC_PLL2FRACR_PLL2FRACN_Pos);
1343
1344 /* Get the PLL3 Clock configuration -----------------------------------------------*/
1345 pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos);
1346 pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1347 pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U;
1348 pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U;
1349 pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U;
1350 pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U;
1351 pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos);
1352 pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1353 RCC_PLL3FRACR_PLL3FRACN_Pos);
1354
1355 /* Get the USART1 clock source ---------------------------------------------*/
1356 pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1357
1358 #if defined(USART2)
1359 /* Get the USART2 clock source ---------------------------------------------*/
1360 pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
1361 #endif /* USART2 */
1362
1363 /* Get the USART3 clock source ---------------------------------------------*/
1364 pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
1365
1366 /* Get the UART4 clock source ----------------------------------------------*/
1367 pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
1368
1369 /* Get the UART5 clock source ----------------------------------------------*/
1370 pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
1371
1372 /* Get the LPUART1 clock source --------------------------------------------*/
1373 pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
1374
1375 #if defined(USART6)
1376 /* Get the UART6 clock source ---------------------------------------------*/
1377 pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
1378 #endif /* defined(USART6) */
1379
1380 /* Get the I2C1 clock source -----------------------------------------------*/
1381 pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
1382
1383 /* Get the I2C2 clock source -----------------------------------------------*/
1384 pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
1385
1386 /* Get the I2C3 clock source -----------------------------------------------*/
1387 pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
1388
1389 /* Get the I2C4 clock source -----------------------------------------------*/
1390 pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE();
1391
1392 #if defined(I2C5)
1393 /* Get the clock source ---------------------------------------------*/
1394 pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE();
1395 #endif /* defined(I2C5) */
1396
1397 #if defined(I2C6)
1398 /* Get the clock source ---------------------------------------------*/
1399 pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE();
1400 #endif /* defined(I2C6) */
1401
1402 /* Get the LPTIM1 clock source ---------------------------------------------*/
1403 pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1404
1405 /* Get the LPTIM2 clock source ---------------------------------------------*/
1406 pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
1407
1408 /* Get the LPTIM34 clock source --------------------------------------------*/
1409 pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE();
1410
1411 /* Get the FDCAN1 clock source ---------------------------------------------*/
1412 pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE();
1413
1414 /* Get the MDF1 clock source -----------------------------------------------*/
1415 pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE();
1416
1417 /* Get the ADF1 clock source -----------------------------------------------*/
1418 pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE();
1419
1420 #if defined(SAES)
1421 /* Get the SAES clock source -----------------------------------------------*/
1422 pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE();
1423 #endif /* SAES */
1424
1425 /* Get the SAI1 clock source -----------------------------------------------*/
1426 pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1427
1428 #if defined(SAI2)
1429 /* Get the SAI2 clock source -----------------------------------------------*/
1430 pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1431 #endif /* SAI2 */
1432
1433 /* Get the CLK48 clock source ----------------------------------------------*/
1434 pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE();
1435
1436 /* Get the SDMMC clock source ----------------------------------------------*/
1437 pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE();
1438
1439 /* Get the ADCDAC clock source ---------------------------------------------*/
1440 pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE();
1441
1442 /* Get the DAC1 clock source -----------------------------------------------*/
1443 pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE();
1444
1445 /* Get the OSPI clock source -----------------------------------------------*/
1446 pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE();
1447
1448 /* Get the SPI1 clock source -----------------------------------------------*/
1449 pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1450
1451 /* Get the SPI2 clock source -----------------------------------------------*/
1452 pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE();
1453
1454 /* Get the SPI3 clock source -----------------------------------------------*/
1455 pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE();
1456
1457 /* Get the RTC clock source ------------------------------------------------*/
1458 pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1459
1460 /* Get the RNG clock source ------------------------------------------------*/
1461 pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE();
1462
1463 #if defined(HSPI1)
1464 /* Get the HSPI kernel clock source ------------------------------------------------*/
1465 pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE();
1466 #endif /* defined(HSPI1) */
1467
1468 #if defined(LTDC)
1469 /* Get the LTDC clock source ------------------------------------------------*/
1470 pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE();
1471 #endif /* defined(LTDC) */
1472
1473 #if defined(DSI)
1474 /* Get the DSI clock source ------------------------------------------------*/
1475 pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1476 #endif /* defined(DSI) */
1477
1478 #if defined(USB_OTG_HS)
1479 /* Get the USB PHY clock source ------------------------------------------------*/
1480 pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
1481 #endif /* defined(USB_OTG_HS) */
1482 }
1483
1484 /**
1485 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
1486 * @note The PLL1 clock frequencies computed by this function is not the real
1487 * frequency in the chip. It is calculated based on the predefined
1488 * constant and the selected clock source:
1489 * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL
1490 * factors.
1491 * @note This function can be used by the user application to compute the
1492 * baud-rate for the communication peripherals or configure other parameters.
1493 *
1494 * @note Each time PLL1CLK changes, this function must be called to update the
1495 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
1496 * @param PLL1_Clocks structure.
1497 * @retval None
1498 */
HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef * PLL1_Clocks)1499 void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
1500 {
1501 uint32_t pll1source;
1502 uint32_t pll1m;
1503 uint32_t pll1n;
1504 uint32_t pll1fracen;
1505 float_t fracn1;
1506 float_t pll1vco;
1507
1508 pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N);
1509 pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
1510 pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
1511 pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos);
1512 fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \
1513 RCC_PLL1FRACR_PLL1FRACN_Pos));
1514
1515 switch (pll1source)
1516 {
1517
1518 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1519 pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1520 (fracn1 / (float_t)0x2000) + (float_t)1);
1521 break;
1522 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1523 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1524 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1525 break;
1526 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1527 pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
1528 (fracn1 / (float_t)0x2000) + (float_t)1);
1529 break;
1530 default:
1531 pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \
1532 ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1);
1533 break;
1534 }
1535
1536 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U)
1537 {
1538 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1539 RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \
1540 (float_t)1));
1541 }
1542 else
1543 {
1544 PLL1_Clocks->PLL1_P_Frequency = 0U;
1545 }
1546
1547 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U)
1548 {
1549 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1550 RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \
1551 (float_t)1));
1552 }
1553 else
1554 {
1555 PLL1_Clocks->PLL1_Q_Frequency = 0U;
1556 }
1557
1558 if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U)
1559 {
1560 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \
1561 RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \
1562 (float_t)1));
1563 }
1564 else
1565 {
1566 PLL1_Clocks->PLL1_R_Frequency = 0U;
1567 }
1568
1569 }
1570
1571 /**
1572 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
1573 * @note The PLL2 clock frequencies computed by this function is not the real
1574 * frequency in the chip. It is calculated based on the predefined
1575 * constant and the selected clock source:
1576 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1577 * factors.
1578 * @note This function can be used by the user application to compute the
1579 * baud-rate for the communication peripherals or configure other parameters.
1580 *
1581 * @note Each time PLL2CLK changes, this function must be called to update the
1582 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
1583 * @param PLL2_Clocks structure.
1584 * @retval None
1585 */
HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef * PLL2_Clocks)1586 void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
1587 {
1588 uint32_t pll2source;
1589 uint32_t pll2m;
1590 uint32_t pll2n;
1591 uint32_t pll2fracen;
1592 float_t fracn2;
1593 float_t pll2vco;
1594
1595 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N
1596 PLL2xCLK = PLL2_VCO / PLL2x */
1597 pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N);
1598 pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC);
1599 pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U;
1600 pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos);
1601 fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \
1602 RCC_PLL2FRACR_PLL2FRACN_Pos));
1603
1604 switch (pll2source)
1605 {
1606 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1607 pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1608 (fracn2 / (float_t)0x2000) + (float_t)1);
1609 break;
1610
1611 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1612 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \
1613 ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1614 break;
1615
1616 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1617 pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \
1618 (fracn2 / (float_t)0x2000) + (float_t)1);
1619 break;
1620
1621 default:
1622 pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \
1623 * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1);
1624 break;
1625 }
1626 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U)
1627 {
1628 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1629 RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \
1630 (float_t)1));
1631 }
1632 else
1633 {
1634 PLL2_Clocks->PLL2_P_Frequency = 0U;
1635 }
1636 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U)
1637 {
1638 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1639 RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \
1640 (float_t)1));
1641 }
1642 else
1643 {
1644 PLL2_Clocks->PLL2_Q_Frequency = 0U;
1645 }
1646 if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U)
1647 {
1648 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \
1649 RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \
1650 (float_t)1));
1651 }
1652 else
1653 {
1654 PLL2_Clocks->PLL2_R_Frequency = 0U;
1655 }
1656 }
1657
1658 /**
1659 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
1660 * @note The PLL3 clock frequencies computed by this function is not the real
1661 * frequency in the chip. It is calculated based on the predefined
1662 * constant and the selected clock source:
1663 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL
1664 * factors.
1665 * @note This function can be used by the user application to compute the
1666 * baud-rate for the communication peripherals or configure other parameters.
1667 *
1668 * @note Each time PLL3CLK changes, this function must be called to update the
1669 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
1670 * @param PLL3_Clocks structure.
1671 * @retval None
1672 */
HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef * PLL3_Clocks)1673 void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
1674 {
1675 uint32_t pll3source;
1676 uint32_t pll3m;
1677 uint32_t pll3n;
1678 uint32_t pll3fracen;
1679 float_t fracn3;
1680 float_t pll3vco;
1681
1682 /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N
1683 PLL3xCLK = PLL3_VCO / PLLxR
1684 */
1685
1686 pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N);
1687 pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC);
1688 pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U;
1689 pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos);
1690 fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \
1691 RCC_PLL3FRACR_PLL3FRACN_Pos));
1692
1693 switch (pll3source)
1694 {
1695 case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1696 pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1697 (fracn3 / (float_t)0x2000) + (float_t)1);
1698
1699 break;
1700 case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
1701 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1702 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1703 break;
1704
1705 case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1706 pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \
1707 (fracn3 / (float_t)0x2000) + (float_t)1);
1708 break;
1709
1710 default:
1711 pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \
1712 ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1);
1713 break;
1714 }
1715
1716 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U)
1717 {
1718 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1719 RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \
1720 (float_t)1));
1721 }
1722 else
1723 {
1724 PLL3_Clocks->PLL3_P_Frequency = 0U;
1725 }
1726
1727 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U)
1728 {
1729 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1730 RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \
1731 (float_t)1));
1732 }
1733 else
1734 {
1735 PLL3_Clocks->PLL3_Q_Frequency = 0U;
1736 }
1737
1738 if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U)
1739 {
1740 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \
1741 RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \
1742 (float_t)1));
1743 }
1744 else
1745 {
1746 PLL3_Clocks->PLL3_R_Frequency = 0U;
1747 }
1748
1749 }
1750
1751 /**
1752 * @brief Return the peripheral clock frequency for peripherals
1753 * @note Return 0 if peripheral clock identifier not managed by this API
1754 * @param PeriphClk Peripheral clock identifier
1755 * This parameter can be one of the following values:
1756 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
1757 * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock
1758 * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock
1759 * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock
1760 * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock
1761 * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
1762 * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock
1763 * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock
1764 * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock
1765 * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock
1766 * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock
1767 * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock
1768 * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock
1769 * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock
1770 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
1771 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
1772 * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*)
1773 * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock
1774 * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock
1775 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*)
1776 * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*)
1777 * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock
1778 * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*)
1779 * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*)
1780 * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*)
1781 * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*)
1782 * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock
1783 * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock
1784 * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock
1785 * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock
1786 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
1787 * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock
1788 * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock
1789 * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock
1790 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
1791 * @retval Frequency in Hz
1792 *
1793 * (*) value not defined in all devices.
1794 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)1795 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
1796 {
1797 PLL1_ClocksTypeDef pll1_clocks;
1798 PLL2_ClocksTypeDef pll2_clocks;
1799 PLL3_ClocksTypeDef pll3_clocks;
1800
1801 uint32_t frequency;
1802 uint32_t srcclk;
1803
1804 /* Check the parameters */
1805 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1806
1807 if (PeriphClk == RCC_PERIPHCLK_RTC)
1808 {
1809 /* Get the current RTC source */
1810 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1811
1812 /* Check if LSE is ready and if RTC clock selection is LSE */
1813 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE))
1814 {
1815 frequency = LSE_VALUE;
1816 }
1817 /* Check if LSI is ready and if RTC clock selection is LSI */
1818 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI))
1819 {
1820 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
1821 {
1822 frequency = LSI_VALUE / 128U;
1823 }
1824 else
1825 {
1826 frequency = LSI_VALUE;
1827 }
1828 }
1829 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
1830 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32))
1831 {
1832 frequency = HSE_VALUE / 32U;
1833 }
1834 /* Clock not enabled for RTC*/
1835 else
1836 {
1837 frequency = 0U;
1838 }
1839 }
1840 else if (PeriphClk == RCC_PERIPHCLK_SAI1)
1841 {
1842 srcclk = __HAL_RCC_GET_SAI1_SOURCE();
1843
1844 switch (srcclk)
1845 {
1846 case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1847
1848 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1849 frequency = pll1_clocks.PLL1_P_Frequency;
1850 break;
1851
1852 case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1853
1854 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1855 frequency = pll2_clocks.PLL2_P_Frequency;
1856 break;
1857
1858 case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1859
1860 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1861 frequency = pll3_clocks.PLL3_P_Frequency;
1862 break;
1863
1864 case RCC_SAI1CLKSOURCE_PIN:
1865
1866 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1867 break;
1868
1869 case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1870
1871 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1872 {
1873 frequency = HSI_VALUE;
1874 }
1875 else
1876 {
1877 frequency = 0U;
1878 }
1879 break;
1880
1881 default :
1882 {
1883 frequency = 0U;
1884 break;
1885 }
1886 }
1887 }
1888 #if defined(SAI2)
1889 else if (PeriphClk == RCC_PERIPHCLK_SAI2)
1890 {
1891 srcclk = __HAL_RCC_GET_SAI2_SOURCE();
1892
1893 switch (srcclk)
1894 {
1895 case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */
1896
1897 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1898 frequency = pll1_clocks.PLL1_P_Frequency;
1899 break;
1900
1901 case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */
1902
1903 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1904 frequency = pll2_clocks.PLL2_P_Frequency;
1905 break;
1906
1907 case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */
1908
1909 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
1910 frequency = pll3_clocks.PLL3_P_Frequency;
1911 break;
1912
1913 case RCC_SAI2CLKSOURCE_PIN:
1914
1915 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
1916 break;
1917
1918 case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */
1919
1920 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
1921 {
1922 frequency = HSI_VALUE;
1923 }
1924 else
1925 {
1926 frequency = 0U;
1927 }
1928 break;
1929
1930 default :
1931
1932 frequency = 0U;
1933 break;
1934 }
1935 }
1936 #endif /* SAI2 */
1937 #if defined(SAES)
1938 else if (PeriphClk == RCC_PERIPHCLK_SAES)
1939 {
1940 /* Get the current SAES source */
1941 srcclk = __HAL_RCC_GET_SAES_SOURCE();
1942
1943 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI))
1944 {
1945 frequency = HSI_VALUE;
1946 }
1947 else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2))
1948 {
1949 frequency = HSI_VALUE >> 1U;
1950 }
1951 /* Clock not enabled for SAES */
1952 else
1953 {
1954 frequency = 0U;
1955 }
1956 }
1957 #endif /* SAES */
1958 else if (PeriphClk == RCC_PERIPHCLK_ICLK)
1959 {
1960 srcclk = __HAL_RCC_GET_ICLK_SOURCE();
1961
1962 switch (srcclk)
1963 {
1964 case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
1965
1966 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
1967 frequency = pll1_clocks.PLL1_Q_Frequency;
1968 break;
1969
1970 case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
1971
1972 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
1973 frequency = pll2_clocks.PLL2_Q_Frequency;
1974 break;
1975
1976 case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
1977
1978 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
1979 {
1980 frequency = HSI48_VALUE;
1981 }
1982 else
1983 {
1984 frequency = 0U;
1985 }
1986 break;
1987
1988 case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
1989
1990 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
1991 {
1992 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
1993 }
1994 else
1995 {
1996 frequency = 0U;
1997 }
1998 break;
1999
2000 default :
2001
2002 frequency = 0U;
2003 break;
2004 }
2005 }
2006 else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
2007 {
2008 srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
2009 if (srcclk == RCC_SDMMCCLKSOURCE_CLK48)
2010 {
2011 srcclk = __HAL_RCC_GET_ICLK_SOURCE();
2012
2013 switch (srcclk)
2014 {
2015 case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */
2016 {
2017 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2018 frequency = pll1_clocks.PLL1_Q_Frequency;
2019 break;
2020 }
2021 case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */
2022 {
2023 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2024 frequency = pll2_clocks.PLL2_Q_Frequency;
2025 break;
2026 }
2027 case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */
2028 {
2029 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY))
2030 {
2031 frequency = HSI48_VALUE;
2032 }
2033 else
2034 {
2035 frequency = 0U;
2036 }
2037 break;
2038 }
2039 case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */
2040 {
2041 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2042 {
2043 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2044 }
2045 else
2046 {
2047 frequency = 0U;
2048 }
2049 break;
2050 }
2051 default :
2052 {
2053 frequency = 0U;
2054 break;
2055 }
2056 }
2057 }
2058 else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1)
2059 {
2060 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2061 frequency = pll1_clocks.PLL1_P_Frequency;
2062 }
2063 else
2064 {
2065 frequency = 0U;
2066 }
2067 }
2068 else if (PeriphClk == RCC_PERIPHCLK_USART1)
2069 {
2070 /* Get the current USART1 source */
2071 srcclk = __HAL_RCC_GET_USART1_SOURCE();
2072
2073 if (srcclk == RCC_USART1CLKSOURCE_PCLK2)
2074 {
2075 frequency = HAL_RCC_GetPCLK2Freq();
2076 }
2077 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
2078 {
2079 frequency = HAL_RCC_GetSysClockFreq();
2080 }
2081 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI))
2082 {
2083 frequency = HSI_VALUE;
2084 }
2085 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE))
2086 {
2087 frequency = LSE_VALUE;
2088 }
2089 /* Clock not enabled for USART1 */
2090 else
2091 {
2092 frequency = 0U;
2093 }
2094 }
2095 #if defined(USART2)
2096 else if (PeriphClk == RCC_PERIPHCLK_USART2)
2097 {
2098 /* Get the current USART2 source */
2099 srcclk = __HAL_RCC_GET_USART2_SOURCE();
2100
2101 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
2102 {
2103 frequency = HAL_RCC_GetPCLK1Freq();
2104 }
2105 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
2106 {
2107 frequency = HAL_RCC_GetSysClockFreq();
2108 }
2109 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI))
2110 {
2111 frequency = HSI_VALUE;
2112 }
2113 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE))
2114 {
2115 frequency = LSE_VALUE;
2116 }
2117 /* Clock not enabled for USART2 */
2118 else
2119 {
2120 frequency = 0U;
2121 }
2122 }
2123 #endif /* USART2 */
2124 else if (PeriphClk == RCC_PERIPHCLK_USART3)
2125 {
2126 /* Get the current USART3 source */
2127 srcclk = __HAL_RCC_GET_USART3_SOURCE();
2128
2129 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
2130 {
2131 frequency = HAL_RCC_GetPCLK1Freq();
2132 }
2133 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
2134 {
2135 frequency = HAL_RCC_GetSysClockFreq();
2136 }
2137 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI))
2138 {
2139 frequency = HSI_VALUE;
2140 }
2141 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE))
2142 {
2143 frequency = LSE_VALUE;
2144 }
2145 /* Clock not enabled for USART3 */
2146 else
2147 {
2148 frequency = 0U;
2149 }
2150 }
2151 else if (PeriphClk == RCC_PERIPHCLK_UART4)
2152 {
2153 /* Get the current UART4 source */
2154 srcclk = __HAL_RCC_GET_UART4_SOURCE();
2155
2156 if (srcclk == RCC_UART4CLKSOURCE_PCLK1)
2157 {
2158 frequency = HAL_RCC_GetPCLK1Freq();
2159 }
2160 else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK)
2161 {
2162 frequency = HAL_RCC_GetSysClockFreq();
2163 }
2164 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI))
2165 {
2166 frequency = HSI_VALUE;
2167 }
2168 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE))
2169 {
2170 frequency = LSE_VALUE;
2171 }
2172 /* Clock not enabled for UART4 */
2173 else
2174 {
2175 frequency = 0U;
2176 }
2177 }
2178 else if (PeriphClk == RCC_PERIPHCLK_UART5)
2179 {
2180 /* Get the current UART5 source */
2181 srcclk = __HAL_RCC_GET_UART5_SOURCE();
2182
2183 if (srcclk == RCC_UART5CLKSOURCE_PCLK1)
2184 {
2185 frequency = HAL_RCC_GetPCLK1Freq();
2186 }
2187 else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK)
2188 {
2189 frequency = HAL_RCC_GetSysClockFreq();
2190 }
2191 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI))
2192 {
2193 frequency = HSI_VALUE;
2194 }
2195 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE))
2196 {
2197 frequency = LSE_VALUE;
2198 }
2199 /* Clock not enabled for UART5 */
2200 else
2201 {
2202 frequency = 0U;
2203 }
2204 }
2205 #if defined(USART6)
2206 else if (PeriphClk == RCC_PERIPHCLK_USART6)
2207 {
2208 /* Get the current USART6 source */
2209 srcclk = __HAL_RCC_GET_USART6_SOURCE();
2210
2211 if (srcclk == RCC_USART6CLKSOURCE_PCLK1)
2212 {
2213 frequency = HAL_RCC_GetPCLK1Freq();
2214 }
2215 else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK)
2216 {
2217 frequency = HAL_RCC_GetSysClockFreq();
2218 }
2219 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI))
2220 {
2221 frequency = HSI_VALUE;
2222 }
2223 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE))
2224 {
2225 frequency = LSE_VALUE;
2226 }
2227 /* Clock not enabled for UART5 */
2228 else
2229 {
2230 frequency = 0U;
2231 }
2232 }
2233 #endif /* USART6 */
2234 else if (PeriphClk == RCC_PERIPHCLK_LPUART1)
2235 {
2236 /* Get the current LPUART1 source */
2237 srcclk = __HAL_RCC_GET_LPUART1_SOURCE();
2238
2239 if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3)
2240 {
2241 frequency = HAL_RCC_GetPCLK3Freq();
2242 }
2243 else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK)
2244 {
2245 frequency = HAL_RCC_GetSysClockFreq();
2246 }
2247 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI))
2248 {
2249 frequency = HSI_VALUE;
2250 }
2251 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE))
2252 {
2253 frequency = LSE_VALUE;
2254 }
2255 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK))
2256 {
2257 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2258 }
2259 /* Clock not enabled for LPUART1 */
2260 else
2261 {
2262 frequency = 0U;
2263 }
2264 }
2265 else if (PeriphClk == RCC_PERIPHCLK_ADCDAC)
2266 {
2267 srcclk = __HAL_RCC_GET_ADCDAC_SOURCE();
2268
2269 if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK)
2270 {
2271 frequency = HAL_RCC_GetSysClockFreq();
2272 }
2273 else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2)
2274 {
2275 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2276 frequency = pll2_clocks.PLL2_R_Frequency;
2277 }
2278 else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK)
2279 {
2280 frequency = HAL_RCC_GetHCLKFreq();
2281 }
2282 else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK)
2283 {
2284 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2285 {
2286 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2287 }
2288 else
2289 {
2290 frequency = 0U;
2291 }
2292 }
2293 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE))
2294 {
2295 frequency = HSE_VALUE;
2296 }
2297 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI))
2298 {
2299 frequency = HSI_VALUE;
2300 }
2301 /* Clock not enabled for ADC */
2302 else
2303 {
2304 frequency = 0U;
2305 }
2306 }
2307 else if (PeriphClk == RCC_PERIPHCLK_MDF1)
2308 {
2309 /* Get the current MDF1 source */
2310 srcclk = __HAL_RCC_GET_MDF1_SOURCE();
2311
2312 switch (srcclk)
2313 {
2314 case RCC_MDF1CLKSOURCE_PLL1:
2315
2316 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2317 frequency = pll1_clocks.PLL1_P_Frequency;
2318 break;
2319
2320 case RCC_MDF1CLKSOURCE_PLL3:
2321
2322 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2323 frequency = pll3_clocks.PLL3_Q_Frequency;
2324 break;
2325
2326 case RCC_MDF1CLKSOURCE_HCLK:
2327
2328 frequency = HAL_RCC_GetHCLKFreq();
2329 break;
2330
2331 case RCC_MDF1CLKSOURCE_PIN:
2332
2333 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
2334 break;
2335
2336 case RCC_MDF1CLKSOURCE_MSIK:
2337
2338 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2339 {
2340 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2341 }
2342 else
2343 {
2344 frequency = 0U;
2345 }
2346 break;
2347
2348 default:
2349
2350 frequency = 0U;
2351 break;
2352 }
2353 }
2354 else if (PeriphClk == RCC_PERIPHCLK_ADF1)
2355 {
2356 /* Get the current ADF1 source */
2357 srcclk = __HAL_RCC_GET_ADF1_SOURCE();
2358
2359 switch (srcclk)
2360 {
2361 case RCC_ADF1CLKSOURCE_PLL1:
2362
2363 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2364 frequency = pll1_clocks.PLL1_P_Frequency;
2365 break;
2366
2367 case RCC_ADF1CLKSOURCE_PLL3:
2368
2369 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2370 frequency = pll3_clocks.PLL3_Q_Frequency;
2371 break;
2372
2373 case RCC_ADF1CLKSOURCE_HCLK:
2374
2375 frequency = HAL_RCC_GetHCLKFreq();
2376 break;
2377
2378 case RCC_ADF1CLKSOURCE_PIN:
2379
2380 frequency = EXTERNAL_SAI1_CLOCK_VALUE;
2381 break;
2382
2383 case RCC_ADF1CLKSOURCE_MSIK:
2384
2385 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2386 {
2387 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2388 }
2389 else
2390 {
2391 frequency = 0U;
2392 }
2393 break;
2394
2395 default:
2396
2397 frequency = 0U;
2398 break;
2399 }
2400 }
2401 else if (PeriphClk == RCC_PERIPHCLK_I2C1)
2402 {
2403 /* Get the current I2C1 source */
2404 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
2405
2406 if (srcclk == RCC_I2C1CLKSOURCE_PCLK1)
2407 {
2408 frequency = HAL_RCC_GetPCLK1Freq();
2409 }
2410 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
2411 {
2412 frequency = HAL_RCC_GetSysClockFreq();
2413 }
2414 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI))
2415 {
2416 frequency = HSI_VALUE;
2417 }
2418 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK))
2419 {
2420 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2421 }
2422 /* Clock not enabled for I2C1 */
2423 else
2424 {
2425 frequency = 0U;
2426 }
2427 }
2428 else if (PeriphClk == RCC_PERIPHCLK_I2C2)
2429 {
2430 /* Get the current I2C2 source */
2431 srcclk = __HAL_RCC_GET_I2C2_SOURCE();
2432
2433 if (srcclk == RCC_I2C2CLKSOURCE_PCLK1)
2434 {
2435 frequency = HAL_RCC_GetPCLK1Freq();
2436 }
2437 else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK)
2438 {
2439 frequency = HAL_RCC_GetSysClockFreq();
2440 }
2441 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI))
2442 {
2443 frequency = HSI_VALUE;
2444 }
2445 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK))
2446 {
2447 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2448 }
2449 /* Clock not enabled for I2C2 */
2450 else
2451 {
2452 frequency = 0U;
2453 }
2454 }
2455 else if (PeriphClk == RCC_PERIPHCLK_I2C3)
2456 {
2457 /* Get the current I2C3 source */
2458 srcclk = __HAL_RCC_GET_I2C3_SOURCE();
2459
2460 switch (srcclk)
2461 {
2462 case RCC_I2C3CLKSOURCE_PCLK3:
2463 {
2464 frequency = HAL_RCC_GetPCLK3Freq();
2465 break;
2466 }
2467 case RCC_I2C3CLKSOURCE_HSI:
2468 {
2469 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2470 {
2471 frequency = HSI_VALUE;
2472 }
2473 else
2474 {
2475 frequency = 0U;
2476 }
2477 break;
2478 }
2479 case RCC_I2C3CLKSOURCE_SYSCLK:
2480 {
2481 frequency = HAL_RCC_GetSysClockFreq();
2482 break;
2483 }
2484 case RCC_I2C3CLKSOURCE_MSIK:
2485 {
2486 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2487 {
2488 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2489 }
2490 else
2491 {
2492 frequency = 0U;
2493 }
2494 break;
2495 }
2496 default:
2497 {
2498 frequency = 0U;
2499 break;
2500 }
2501 }
2502 }
2503 else if (PeriphClk == RCC_PERIPHCLK_I2C4)
2504 {
2505 /* Get the current I2C4 source */
2506 srcclk = __HAL_RCC_GET_I2C4_SOURCE();
2507
2508 if (srcclk == RCC_I2C4CLKSOURCE_PCLK1)
2509 {
2510 frequency = HAL_RCC_GetPCLK1Freq();
2511 }
2512 else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK)
2513 {
2514 frequency = HAL_RCC_GetSysClockFreq();
2515 }
2516 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI))
2517 {
2518 frequency = HSI_VALUE;
2519 }
2520 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK))
2521 {
2522 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2523 }
2524 /* Clock not enabled for I2C4 */
2525 else
2526 {
2527 frequency = 0U;
2528 }
2529 }
2530 #if defined (I2C5)
2531 else if (PeriphClk == RCC_PERIPHCLK_I2C5)
2532 {
2533 /* Get the current I2C5 source */
2534 srcclk = __HAL_RCC_GET_I2C5_SOURCE();
2535
2536 if (srcclk == RCC_I2C5CLKSOURCE_PCLK1)
2537 {
2538 frequency = HAL_RCC_GetPCLK1Freq();
2539 }
2540 else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK)
2541 {
2542 frequency = HAL_RCC_GetSysClockFreq();
2543 }
2544 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI))
2545 {
2546 frequency = HSI_VALUE;
2547 }
2548 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK))
2549 {
2550 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2551 }
2552 /* Clock not enabled for I2C5 */
2553 else
2554 {
2555 frequency = 0U;
2556 }
2557 }
2558 #endif /* I2C5 */
2559 #if defined (I2C6)
2560 else if (PeriphClk == RCC_PERIPHCLK_I2C6)
2561 {
2562 /* Get the current I2C6 source */
2563 srcclk = __HAL_RCC_GET_I2C6_SOURCE();
2564
2565 if (srcclk == RCC_I2C6CLKSOURCE_PCLK1)
2566 {
2567 frequency = HAL_RCC_GetPCLK1Freq();
2568 }
2569 else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK)
2570 {
2571 frequency = HAL_RCC_GetSysClockFreq();
2572 }
2573 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI))
2574 {
2575 frequency = HSI_VALUE;
2576 }
2577 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK))
2578 {
2579 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2580 }
2581 /* Clock not enabled for I2C6 */
2582 else
2583 {
2584 frequency = 0U;
2585 }
2586 }
2587 #endif /* I2C6 */
2588 else if (PeriphClk == RCC_PERIPHCLK_LPTIM34)
2589 {
2590 /* Get the current LPTIM34 source */
2591 srcclk = __HAL_RCC_GET_LPTIM34_SOURCE();
2592
2593 if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK)
2594 {
2595 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2596 {
2597 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2598 }
2599 else
2600 {
2601 frequency = 0U;
2602 }
2603 }
2604 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI))
2605 {
2606 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2607 {
2608 frequency = LSI_VALUE / 128U;
2609 }
2610 else
2611 {
2612 frequency = LSI_VALUE;
2613 }
2614 }
2615 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI))
2616 {
2617 frequency = HSI_VALUE;
2618 }
2619 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE))
2620 {
2621 frequency = LSE_VALUE;
2622 }
2623 /* Clock not enabled for LPTIM34 */
2624 else
2625 {
2626 frequency = 0U;
2627 }
2628 }
2629 else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
2630 {
2631 /* Get the current LPTIM1 source */
2632 srcclk = __HAL_RCC_GET_LPTIM1_SOURCE();
2633
2634 if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK)
2635 {
2636 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2637 {
2638 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2639 }
2640 else
2641 {
2642 frequency = 0U;
2643 }
2644 }
2645 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI))
2646 {
2647 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2648 {
2649 frequency = LSI_VALUE / 128U;
2650 }
2651 else
2652 {
2653 frequency = LSI_VALUE;
2654 }
2655 }
2656 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI))
2657 {
2658 frequency = HSI_VALUE;
2659 }
2660 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE))
2661 {
2662 frequency = LSE_VALUE;
2663 }
2664 /* Clock not enabled for LPTIM1 */
2665 else
2666 {
2667 frequency = 0U;
2668 }
2669 }
2670 else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
2671 {
2672 /* Get the current LPTIM2 source */
2673 srcclk = __HAL_RCC_GET_LPTIM2_SOURCE();
2674
2675 if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1)
2676 {
2677 frequency = HAL_RCC_GetPCLK1Freq();
2678 }
2679 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI))
2680 {
2681 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2682 {
2683 frequency = LSI_VALUE / 128U;
2684 }
2685 else
2686 {
2687 frequency = LSI_VALUE;
2688 }
2689 }
2690 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI))
2691 {
2692 frequency = HSI_VALUE;
2693 }
2694 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE))
2695 {
2696 frequency = LSE_VALUE;
2697 }
2698 /* Clock not enabled for LPTIM2 */
2699 else
2700 {
2701 frequency = 0U;
2702 }
2703 }
2704 else if (PeriphClk == RCC_PERIPHCLK_FDCAN1)
2705 {
2706 /* Get the current FDCAN1 kernel source */
2707 srcclk = __HAL_RCC_GET_FDCAN1_SOURCE();
2708
2709 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE))
2710 {
2711 frequency = HSE_VALUE;
2712 }
2713 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */
2714 {
2715 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2716 frequency = pll1_clocks.PLL1_Q_Frequency;
2717 }
2718 else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */
2719 {
2720 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2721 frequency = pll2_clocks.PLL2_P_Frequency;
2722 }
2723 /* Clock not enabled for FDCAN1 */
2724 else
2725 {
2726 frequency = 0U;
2727 }
2728 }
2729 else if (PeriphClk == RCC_PERIPHCLK_SPI1)
2730 {
2731 /* Get the current SPI1 kernel source */
2732 srcclk = __HAL_RCC_GET_SPI1_SOURCE();
2733 switch (srcclk)
2734 {
2735 case RCC_SPI1CLKSOURCE_PCLK2:
2736
2737 frequency = HAL_RCC_GetPCLK2Freq();
2738 break;
2739
2740 case RCC_SPI1CLKSOURCE_SYSCLK:
2741
2742 frequency = HAL_RCC_GetSysClockFreq();
2743 break;
2744
2745 case RCC_SPI1CLKSOURCE_HSI:
2746
2747 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2748 {
2749 frequency = HSI_VALUE;
2750 }
2751 else
2752 {
2753 frequency = 0U;
2754 }
2755 break;
2756
2757 case RCC_SPI1CLKSOURCE_MSIK:
2758
2759 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2760 {
2761 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2762 }
2763 else
2764 {
2765 frequency = 0U;
2766 }
2767 break;
2768
2769 default:
2770
2771 frequency = 0U;
2772 break;
2773 }
2774 }
2775 else if (PeriphClk == RCC_PERIPHCLK_SPI2)
2776 {
2777 /* Get the current SPI2 kernel source */
2778 srcclk = __HAL_RCC_GET_SPI2_SOURCE();
2779 switch (srcclk)
2780 {
2781 case RCC_SPI2CLKSOURCE_PCLK1:
2782
2783 frequency = HAL_RCC_GetPCLK1Freq();
2784 break;
2785
2786 case RCC_SPI2CLKSOURCE_SYSCLK:
2787
2788 frequency = HAL_RCC_GetSysClockFreq();
2789 break;
2790
2791 case RCC_SPI2CLKSOURCE_HSI:
2792
2793 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2794 {
2795 frequency = HSI_VALUE;
2796 }
2797 else
2798 {
2799 frequency = 0U;
2800 }
2801 break;
2802
2803 case RCC_SPI2CLKSOURCE_MSIK:
2804
2805 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2806 {
2807 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2808 }
2809 else
2810 {
2811 frequency = 0U;
2812 }
2813 break;
2814
2815 default:
2816
2817 frequency = 0U;
2818 break;
2819 }
2820 }
2821 else if (PeriphClk == RCC_PERIPHCLK_SPI3)
2822 {
2823 /* Get the current SPI3 kernel source */
2824 srcclk = __HAL_RCC_GET_SPI3_SOURCE();
2825 switch (srcclk)
2826 {
2827 case RCC_SPI3CLKSOURCE_PCLK3:
2828
2829 frequency = HAL_RCC_GetPCLK3Freq();
2830 break;
2831
2832 case RCC_SPI3CLKSOURCE_SYSCLK:
2833
2834 frequency = HAL_RCC_GetSysClockFreq();
2835 break;
2836
2837 case RCC_SPI3CLKSOURCE_HSI:
2838
2839 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
2840 {
2841 frequency = HSI_VALUE;
2842 }
2843 else
2844 {
2845 frequency = 0U;
2846 }
2847 break;
2848
2849 case RCC_SPI3CLKSOURCE_MSIK:
2850
2851 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2852 {
2853 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2854 }
2855 else
2856 {
2857 frequency = 0U;
2858 }
2859 break;
2860
2861 default:
2862
2863 frequency = 0U;
2864 break;
2865 }
2866 }
2867 else if (PeriphClk == RCC_PERIPHCLK_OSPI)
2868 {
2869 /* Get the current OSPI kernel source */
2870 srcclk = __HAL_RCC_GET_OSPI_SOURCE();
2871
2872 switch (srcclk)
2873 {
2874 case RCC_OSPICLKSOURCE_PLL2:
2875
2876 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2877 frequency = pll2_clocks.PLL2_Q_Frequency;
2878 break;
2879
2880 case RCC_OSPICLKSOURCE_PLL1:
2881
2882 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2883 frequency = pll1_clocks.PLL1_Q_Frequency;
2884 break;
2885
2886 case RCC_OSPICLKSOURCE_SYSCLK:
2887
2888 frequency = HAL_RCC_GetSysClockFreq();
2889 break;
2890
2891 case RCC_OSPICLKSOURCE_MSIK:
2892
2893 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY))
2894 {
2895 frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)];
2896 }
2897 else
2898 {
2899 frequency = 0U;
2900 }
2901 break;
2902
2903 default:
2904
2905 frequency = 0U;
2906 break;
2907 }
2908 }
2909 #if defined(HSPI1)
2910
2911 else if (PeriphClk == RCC_PERIPHCLK_HSPI)
2912 {
2913 /* Get the current HSPI kernel source */
2914 srcclk = __HAL_RCC_GET_HSPI_SOURCE();
2915
2916 switch (srcclk)
2917 {
2918 case RCC_HSPICLKSOURCE_SYSCLK:
2919
2920 frequency = HAL_RCC_GetSysClockFreq();
2921 break;
2922
2923 case RCC_HSPICLKSOURCE_PLL1:
2924
2925 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
2926 frequency = pll1_clocks.PLL1_Q_Frequency;
2927 break;
2928
2929 case RCC_HSPICLKSOURCE_PLL2:
2930
2931 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
2932 frequency = pll2_clocks.PLL2_Q_Frequency;
2933 break;
2934 case RCC_HSPICLKSOURCE_PLL3:
2935
2936 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
2937 frequency = pll3_clocks.PLL3_R_Frequency;
2938 break;
2939
2940 default:
2941
2942 frequency = 0U;
2943 break;
2944 }
2945 }
2946 #endif /* defined(HSPI1) */
2947 else if (PeriphClk == RCC_PERIPHCLK_DAC1)
2948 {
2949 /* Get the current DAC1 kernel source */
2950 srcclk = __HAL_RCC_GET_DAC1_SOURCE();
2951
2952 /* Check if LSE is ready and if DAC1 clock selection is LSE */
2953 if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE))
2954 {
2955 frequency = LSE_VALUE;
2956 }
2957 /* Check if LSI is ready and if DAC1 clock selection is LSI */
2958 else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI))
2959 {
2960 if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV))
2961 {
2962 frequency = LSI_VALUE / 128U;
2963 }
2964 else
2965 {
2966 frequency = LSI_VALUE;
2967 }
2968 }
2969 /* Clock not enabled for DAC1*/
2970 else
2971 {
2972 frequency = 0U;
2973 }
2974
2975 }
2976 else if (PeriphClk == RCC_PERIPHCLK_RNG)
2977 {
2978 /* Get the current RNG kernel source */
2979 srcclk = __HAL_RCC_GET_RNG_SOURCE();
2980
2981 /* Check if HSI48 is ready and if RNG clock selection is HSI48 */
2982 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48))
2983 {
2984 frequency = HSI48_VALUE;
2985 }
2986
2987 /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */
2988 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2))
2989 {
2990 frequency = HSI48_VALUE >> 1U ;
2991 }
2992
2993 /* Check if HSI is ready and if RNG clock selection is HSI */
2994 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI))
2995 {
2996 frequency = HSI_VALUE;
2997 }
2998 /* Clock not enabled for RNG */
2999 else
3000 {
3001 frequency = 0U;
3002 }
3003 }
3004 #if defined(LTDC)
3005 else if (PeriphClk == RCC_PERIPHCLK_LTDC)
3006 {
3007 /* Get the current LTDC kernel source */
3008 srcclk = __HAL_RCC_GET_LTDC_SOURCE();
3009
3010 switch (srcclk)
3011 {
3012 case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */
3013
3014 HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
3015 frequency = pll3_clocks.PLL3_R_Frequency;
3016 break;
3017
3018 case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */
3019
3020 HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
3021 frequency = pll2_clocks.PLL2_R_Frequency;
3022 break;
3023
3024 default:
3025
3026 frequency = 0U;
3027 break;
3028 }
3029 }
3030 #endif /* defined(LTDC) */
3031
3032 #if defined(USB_OTG_HS)
3033
3034 else if (PeriphClk == RCC_PERIPHCLK_USBPHY)
3035 {
3036 /* Get the current USB_OTG_HS kernel source */
3037 srcclk = __HAL_RCC_GET_USBPHY_SOURCE();
3038
3039 if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE))
3040 {
3041 frequency = HSE_VALUE;
3042 }
3043 else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2))
3044 {
3045 frequency = HSE_VALUE >> 1U ;
3046 }
3047 else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */
3048 {
3049 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3050 frequency = pll1_clocks.PLL1_P_Frequency;
3051 }
3052 else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */
3053 {
3054 HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
3055 frequency = (pll1_clocks.PLL1_P_Frequency) / 2U;
3056 }
3057 /* Clock not enabled for USB_OTG_HS */
3058 else
3059 {
3060 frequency = 0U;
3061 }
3062 }
3063 #endif /* defined(USB_OTG_HS) */
3064
3065 else
3066 {
3067 frequency = 0;
3068 }
3069 return (frequency);
3070 }
3071
3072
3073 /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
3074 * @brief Extended Clock management functions
3075 *
3076 @verbatim
3077 ===============================================================================
3078 ##### Extended clock management functions #####
3079 ===============================================================================
3080 [..]
3081 This subsection provides a set of functions allowing to control the
3082 activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS,
3083 Low speed clock output and clock after wake-up from STOP mode.
3084 @endverbatim
3085 * @{
3086 */
3087
3088 /**
3089 * @brief Enable PLL2.
3090 * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
3091 * contains the configuration information for the PLL2
3092 * @retval HAL status
3093 */
HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef * PLL2Init)3094 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init)
3095 {
3096 uint32_t tickstart;
3097 HAL_StatusTypeDef status = HAL_OK;
3098
3099 /* check for PLL2 Parameters used to output PLL2CLK */
3100 assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source));
3101 assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M));
3102 assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N));
3103 assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P));
3104 assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q));
3105 assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R));
3106 assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut));
3107
3108 /* Disable the PLL2 */
3109 __HAL_RCC_PLL2_DISABLE();
3110
3111 /* Get Start Tick*/
3112 tickstart = HAL_GetTick();
3113
3114 /* Wait till PLL2 is ready to be updated */
3115 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
3116 {
3117 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3118 {
3119 status = HAL_TIMEOUT;
3120 break;
3121 }
3122 }
3123
3124 if (status == HAL_OK)
3125 {
3126 /* Make sure PLL2Source is ready */
3127 status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source);
3128
3129 if (status == HAL_OK)
3130 {
3131 /* Configure the PLL2 clock source, multiplication factor N, */
3132 /* and division factors M, P, Q and R */
3133 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N,
3134 PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R);
3135
3136 /* Disable PLL2FRACN */
3137 __HAL_RCC_PLL2FRACN_DISABLE();
3138
3139 /* Configure PLL PLL2FRACN */
3140 __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN);
3141
3142 /* Enable PLL2FRACN */
3143 __HAL_RCC_PLL2FRACN_ENABLE();
3144
3145 /* Select PLL2 input reference frequency range: VCI */
3146 __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE);
3147
3148 /* Configure the PLL2 Clock output(s) */
3149 __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut);
3150
3151 /* Enable the PLL2 again by setting PLL2ON to 1*/
3152 __HAL_RCC_PLL2_ENABLE();
3153
3154 /* Get Start Tick*/
3155 tickstart = HAL_GetTick();
3156
3157 /* Wait till PLL2 is ready */
3158 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U)
3159 {
3160 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3161 {
3162 status = HAL_TIMEOUT;
3163 break;
3164 }
3165 }
3166 }
3167 }
3168
3169 return status;
3170 }
3171
3172 /**
3173 * @brief Disable PLL2.
3174 * @retval HAL status
3175 */
HAL_RCCEx_DisablePLL2(void)3176 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
3177 {
3178 uint32_t tickstart;
3179 HAL_StatusTypeDef status = HAL_OK;
3180
3181 /* Disable the PLL2 */
3182 __HAL_RCC_PLL2_DISABLE();
3183
3184 /* Get Start Tick*/
3185 tickstart = HAL_GetTick();
3186
3187 /* Wait till PLL2 is ready */
3188 while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U)
3189 {
3190 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
3191 {
3192 status = HAL_TIMEOUT;
3193 break;
3194 }
3195 }
3196
3197 /* To save power disable the PLL2 Source, FRACN and Clock outputs */
3198 CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \
3199 RCC_PLL2CFGR_PLL2FRACEN);
3200
3201 return status;
3202 }
3203
3204 /**
3205 * @brief Enable PLL3.
3206 * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that
3207 * contains the configuration information for the PLL3
3208 * @retval HAL status
3209 */
HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef * PLL3Init)3210 HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init)
3211 {
3212 uint32_t tickstart;
3213 HAL_StatusTypeDef status = HAL_OK;
3214
3215 /* check for PLL3 Parameters used to output PLL3CLK */
3216 assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source));
3217 assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M));
3218 assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N));
3219 assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P));
3220 assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut));
3221
3222 /* Disable the PLL3 */
3223 __HAL_RCC_PLL3_DISABLE();
3224
3225 /* Get Start Tick*/
3226 tickstart = HAL_GetTick();
3227
3228 /* Wait till PLL3 is ready to be updated */
3229 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
3230 {
3231 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3232 {
3233 status = HAL_TIMEOUT;
3234 break;
3235 }
3236 }
3237
3238 if (status == HAL_OK)
3239 {
3240 /* Make sure PLL3Source is ready */
3241 status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source);
3242
3243 if (status == HAL_OK)
3244 {
3245 /* Configure the PLL3 clock source, multiplication factor N, */
3246 /* and division factors M and P */
3247 __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \
3248 PLL3Init->PLL3R);
3249
3250 /* Disable PLL3FRACN . */
3251 __HAL_RCC_PLL3FRACN_DISABLE();
3252
3253 /* Configure PLL PLL3FRACN */
3254 __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN);
3255
3256 /* Enable PLL3FRACN . */
3257 __HAL_RCC_PLL3FRACN_ENABLE();
3258
3259 /* Select PLL3 input reference frequency range: VCI */
3260 __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE);
3261
3262 /* Configure the PLL3 Clock output(s) */
3263 __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut);
3264
3265 /* Enable the PLL3 again by setting PLL3ON to 1*/
3266 __HAL_RCC_PLL3_ENABLE();
3267
3268 /* Get Start Tick*/
3269 tickstart = HAL_GetTick();
3270
3271 /* Wait till PLL3 is ready */
3272 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U)
3273 {
3274 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3275 {
3276 status = HAL_TIMEOUT;
3277 break;
3278 }
3279 }
3280 }
3281 }
3282
3283 return status;
3284 }
3285
3286 /**
3287 * @brief Disable PLL3.
3288 * @retval HAL status
3289 */
HAL_RCCEx_DisablePLL3(void)3290 HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void)
3291 {
3292 uint32_t tickstart;
3293 HAL_StatusTypeDef status = HAL_OK;
3294
3295 /* Disable the PLL3 */
3296 __HAL_RCC_PLL3_DISABLE();
3297
3298 /* Get Start Tick*/
3299 tickstart = HAL_GetTick();
3300
3301 /* Wait till PLL3 is ready */
3302 while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U)
3303 {
3304 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
3305 {
3306 status = HAL_TIMEOUT;
3307 break;
3308 }
3309 }
3310
3311 /* To save power disable the PLL3 Source and Clock outputs */
3312 CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \
3313 RCC_PLL3CFGR_PLL3FRACEN);
3314
3315 return status;
3316 }
3317
3318 /**
3319 * @brief Select which MSI output clock uses the PLL mode.
3320 * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection.
3321 * @note The MSI kernel clock output uses the same oscillator source than the MSI system
3322 * clock output, then the PLL mode is applied to the both clocks outputs.
3323 * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode.
3324 * This parameter can be one of the following values:
3325 * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output
3326 * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output
3327 * @retval HAL status
3328 */
HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)3329 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection)
3330 {
3331 HAL_StatusTypeDef status = HAL_ERROR;
3332
3333 assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection));
3334 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U)
3335 {
3336 /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */
3337 if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL)
3338 {
3339 SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
3340 }
3341 else
3342 {
3343 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL);
3344 }
3345 status = HAL_OK;
3346 }
3347
3348 return status;
3349 }
3350
3351 /**
3352 * @brief Enable the fast PLL mode start-up of the MSI clock
3353 * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup.
3354 * @note The fast start-up feature is not active the first time the PLL mode is selected. The
3355 * fast start-up is active when the MSI in PLL mode returns from switch off.
3356 * @retval HAL status
3357 */
HAL_RCCEx_EnableMSIPLLFastStartup(void)3358 HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void)
3359 {
3360 HAL_StatusTypeDef status = HAL_ERROR;
3361
3362 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
3363 {
3364 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
3365 SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
3366 status = HAL_OK;
3367 }
3368
3369 return status;
3370 }
3371
3372 /**
3373 * @brief Disable the fast PLL mode start-up of the MSI clock
3374 * @note the MSI fast startup mode disabled only when PLL-mode is enabled
3375 * @retval HAL status
3376 */
HAL_RCCEx_DisableMSIPLLFastStartup(void)3377 HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void)
3378 {
3379 HAL_StatusTypeDef status = HAL_ERROR;
3380
3381 if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN)
3382 {
3383 /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */
3384 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST);
3385 status = HAL_OK;
3386 }
3387 return status;
3388 }
3389
3390 /**
3391 * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock.
3392 * @param WakeUpClk Wakeup clock
3393 * This parameter can be one of the following values:
3394 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection
3395 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection
3396 * @note This function shall not be called after the Clock Security System on HSE has been
3397 * enabled.
3398 * @retval None
3399 */
HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)3400 void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk)
3401 {
3402 assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk));
3403
3404 __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3405 }
3406
3407 /**
3408 * @brief Configure the oscillator Kernel clock source for wakeup from Stop
3409 * @param WakeUpClk: Kernel Wakeup clock
3410 * This parameter can be one of the following values:
3411 * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection
3412 * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection
3413 * @retval None
3414 */
HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)3415 void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
3416 {
3417 assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk));
3418
3419 __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
3420 }
3421
3422 /**
3423 * @brief Configure the MSI range after standby mode.
3424 * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz).
3425 * @param MSIRange MSI range
3426 * This parameter can be one of the following values:
3427 * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value)
3428 * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz
3429 * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz
3430 * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz
3431 * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz
3432 * @retval None
3433 */
HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)3434 void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange)
3435 {
3436 assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange));
3437
3438 __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange);
3439 }
3440
3441 /**
3442 * @brief Configure the MSIK range after standby mode.
3443 * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz).
3444 * @param MSIKRange MSIK range
3445 * This parameter can be one of the following values:
3446 * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value)
3447 * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz
3448 * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz
3449 * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz
3450 * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz
3451 * @retval None
3452 */
HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange)3453 void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange)
3454 {
3455 assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange));
3456
3457 __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange);
3458 }
3459
3460 /**
3461 * @brief Enable the LSE Clock Security System.
3462 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
3463 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
3464 * clock with HAL_RCCEx_PeriphCLKConfig().
3465 * @retval None
3466 */
HAL_RCCEx_EnableLSECSS(void)3467 void HAL_RCCEx_EnableLSECSS(void)
3468 {
3469 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
3470 }
3471
3472 /**
3473 * @brief Disable the LSE Clock Security System.
3474 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
3475 * @retval None
3476 */
HAL_RCCEx_DisableLSECSS(void)3477 void HAL_RCCEx_DisableLSECSS(void)
3478 {
3479 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
3480 }
3481
3482 /**
3483 * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line.
3484 * @note LSE Clock Security System Interrupt is mapped on EXTI line
3485 * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3486 * @retval None
3487 */
HAL_RCCEx_EnableLSECSS_IT(void)3488 void HAL_RCCEx_EnableLSECSS_IT(void)
3489 {
3490 /* Enable LSE CSS */
3491 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ;
3492
3493 /* Enable IT on LSECSS EXTI Line */
3494 SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS);
3495 /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */
3496 SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS);
3497 }
3498
3499 /**
3500 * @brief Handle the RCC LSE Clock Security System interrupt request.
3501 * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3502 * @retval None
3503 */
HAL_RCCEx_LSECSS_IRQHandler(void)3504 void HAL_RCCEx_LSECSS_IRQHandler(void)
3505 {
3506 uint32_t falling_edge_flag;
3507 uint32_t rising_edge_flag;
3508
3509 if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U)
3510 {
3511 /* Read Falling Edge flag on LSECSS EXTI interrupt */
3512 falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
3513
3514 /* Read Rising Edge flag on LSECSS EXTI interrupt */
3515 rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
3516
3517 /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */
3518 if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \
3519 (rising_edge_flag == RCC_EXTI_LINE_LSECSS))
3520 {
3521 if (rising_edge_flag == RCC_EXTI_LINE_LSECSS)
3522 {
3523 /* Clear the RCC LSECSS EXTI Rising Edge flag */
3524 WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS);
3525 }
3526 if (falling_edge_flag == RCC_EXTI_LINE_LSECSS)
3527 {
3528 /* Clear the RCC LSECSS EXTI Falling Edge flag */
3529 WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS);
3530 }
3531 }
3532 /* RCC LSECSS interrupt user callback */
3533 HAL_RCCEx_LSECSS_Callback();
3534 }
3535 }
3536
3537 /**
3538 * @brief RCCEx LSE Clock Security System interrupt callback.
3539 * @retval none
3540 */
HAL_RCCEx_LSECSS_Callback(void)3541 __weak void HAL_RCCEx_LSECSS_Callback(void)
3542 {
3543 /* NOTE : This function should not be modified, when the callback is needed,
3544 the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
3545 */
3546 }
3547
3548 /**
3549 * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line.
3550 * @note MSI PLL Unlock Interrupt is mapped on EXTI line
3551 * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3552 * @retval None
3553 */
HAL_RCCEx_EnableMSIPLLUNLCK_IT(void)3554 void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void)
3555 {
3556 /* Enable IT on MSI PLL Unlock EXTI Line */
3557 SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3558 /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */
3559 SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3560 }
3561
3562 /**
3563 * @brief Handle the RCC MSI PLL Unlock interrupt request.
3564 * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3565 * @retval None
3566 */
HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void)3567 void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void)
3568 {
3569 uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3570 uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3571
3572 /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */
3573 if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \
3574 (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK))
3575 {
3576 if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
3577 {
3578 /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */
3579 WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3580 }
3581 if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)
3582 {
3583 /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */
3584 WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK);
3585 }
3586 /* RCC MSI PLL Unlock interrupt user callback */
3587 HAL_RCCEx_MSIPLLUNLCK_Callback();
3588 }
3589 }
3590
3591 /**
3592 * @brief RCCEx RCC MSI PLL Unlock interrupt callback.
3593 * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices.
3594 * @retval none
3595 */
HAL_RCCEx_MSIPLLUNLCK_Callback(void)3596 __weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void)
3597 {
3598 /* NOTE : This function should not be modified, when the callback is needed,
3599 the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file
3600 */
3601 }
3602
3603 /**
3604 * @brief Select the Low Speed clock source to output on LSCO pin (PA2).
3605 * @param LSCOSource specifies the Low Speed clock source to output.
3606 * This parameter can be one of the following values:
3607 * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source
3608 * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source
3609 * @retval None
3610 */
HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)3611 void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource)
3612 {
3613 FlagStatus pwrclkchanged = RESET;
3614 FlagStatus backupchanged = RESET;
3615
3616 /* Check the parameters */
3617 assert_param(IS_RCC_LSCOSOURCE(LSCOSource));
3618
3619 /* Update LSCOSEL clock source in Backup Domain control register */
3620 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
3621 {
3622 __HAL_RCC_PWR_CLK_ENABLE();
3623 pwrclkchanged = SET;
3624 }
3625 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
3626 {
3627 HAL_PWR_EnableBkUpAccess();
3628 backupchanged = SET;
3629 }
3630
3631 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN);
3632
3633 if (backupchanged == SET)
3634 {
3635 HAL_PWR_DisableBkUpAccess();
3636 }
3637 if (pwrclkchanged == SET)
3638 {
3639 __HAL_RCC_PWR_CLK_DISABLE();
3640 }
3641 }
3642
3643 /**
3644 * @brief Disable the Low Speed clock output.
3645 * @retval None
3646 */
HAL_RCCEx_DisableLSCO(void)3647 void HAL_RCCEx_DisableLSCO(void)
3648 {
3649 FlagStatus pwrclkchanged = RESET;
3650 FlagStatus backupchanged = RESET;
3651
3652 /* Update LSCOEN bit in Backup Domain control register */
3653 if (__HAL_RCC_PWR_IS_CLK_DISABLED())
3654 {
3655 __HAL_RCC_PWR_CLK_ENABLE();
3656 pwrclkchanged = SET;
3657 }
3658 if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP))
3659 {
3660 /* Enable access to the backup domain */
3661 HAL_PWR_EnableBkUpAccess();
3662 backupchanged = SET;
3663 }
3664
3665 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
3666
3667 /* Restore previous configuration */
3668 if (backupchanged == SET)
3669 {
3670 /* Disable access to the backup domain */
3671 HAL_PWR_DisableBkUpAccess();
3672 }
3673 if (pwrclkchanged == SET)
3674 {
3675 __HAL_RCC_PWR_CLK_DISABLE();
3676 }
3677 }
3678
3679 /**
3680 * @brief Enable the PLL-mode of the MSI.
3681 * @note Prior to enable the PLL-mode of the MSI for automatic hardware
3682 * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig().
3683 * @retval None
3684 */
HAL_RCCEx_EnableMSIPLLMode(void)3685 void HAL_RCCEx_EnableMSIPLLMode(void)
3686 {
3687 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
3688 }
3689
3690 /**
3691 * @brief Disable the PLL-mode of the MSI.
3692 * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled.
3693 * @retval None
3694 */
HAL_RCCEx_DisableMSIPLLMode(void)3695 void HAL_RCCEx_DisableMSIPLLMode(void)
3696 {
3697 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
3698 }
3699 /**
3700 * @}
3701 */
3702
3703 #if defined(CRS)
3704
3705 /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
3706 * @brief Extended Clock Recovery System Control functions
3707 *
3708 @verbatim
3709 ===============================================================================
3710 ##### Extended Clock Recovery System Control functions #####
3711 ===============================================================================
3712 [..]
3713 For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
3714
3715 (#) In System clock config, HSI48 needs to be enabled
3716
3717 (#) Enable CRS clock in IP MSP init which will use CRS functions
3718
3719 (#) Call CRS functions as follows:
3720 (##) Prepare synchronization configuration necessary for HSI48 calibration
3721 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
3722 and also HSI48 oscillator smooth trimming.
3723 (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate
3724 directly reload value with target and synchronization frequencies values
3725 (##) Call function HAL_RCCEx_CRSConfig which
3726 (+++) Resets CRS registers to their default values.
3727 (+++) Configures CRS registers with synchronization configuration
3728 (+++) Enables automatic calibration and frequency error counter feature
3729 Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
3730 periodic USB SOF will not be generated by the host. No SYNC signal will therefore be
3731 provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock
3732 precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
3733 should be used as SYNC signal.
3734
3735 (##) A polling function is provided to wait for complete synchronization
3736 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
3737 (+++) According to CRS status, user can decide to adjust again the calibration or continue
3738 application if synchronization is OK
3739
3740 (#) User can retrieve information related to synchronization in calling function
3741 HAL_RCCEx_CRSGetSynchronizationInfo()
3742
3743 (#) Regarding synchronization status and synchronization information, user can try a new calibration
3744 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
3745 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
3746 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
3747 incremented), while when it is detected during the upcounting phase it means that the actual frequency
3748 is higher (and that the TRIM value should be decremented).
3749
3750 (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go
3751 through CRS Handler (CRS_IRQn/CRS_IRQHandler)
3752 (++) Call function HAL_RCCEx_CRSConfig()
3753 (++) Enable CRS_IRQn (thanks to NVIC functions)
3754 (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT)
3755 (++) Implement CRS status management in the following user callbacks called from
3756 HAL_RCCEx_CRS_IRQHandler():
3757 (+++) HAL_RCCEx_CRS_SyncOkCallback()
3758 (+++) HAL_RCCEx_CRS_SyncWarnCallback()
3759 (+++) HAL_RCCEx_CRS_ExpectedSyncCallback()
3760 (+++) HAL_RCCEx_CRS_ErrorCallback()
3761
3762 (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate().
3763 This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
3764
3765 @endverbatim
3766 * @{
3767 */
3768
3769 /**
3770 * @brief Start automatic synchronization for polling mode
3771 * @param pInit Pointer on RCC_CRSInitTypeDef structure
3772 * @retval None
3773 */
HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef * const pInit)3774 void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit)
3775 {
3776 uint32_t value;
3777
3778 /* Check the parameters */
3779 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
3780 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
3781 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
3782 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
3783 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
3784 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
3785
3786 /* CONFIGURATION */
3787
3788 /* Before configuration, reset CRS registers to their default values*/
3789 __HAL_RCC_CRS_FORCE_RESET();
3790 __HAL_RCC_CRS_RELEASE_RESET();
3791
3792 /* Set the SYNCDIV[2:0] bits according to Prescaler value */
3793 /* Set the SYNCSRC[1:0] bits according to Source value */
3794 /* Set the SYNCSPOL bit according to Polarity value */
3795 value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
3796 /* Set the RELOAD[15:0] bits according to ReloadValue value */
3797 value |= pInit->ReloadValue;
3798 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
3799 value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos);
3800 WRITE_REG(CRS->CFGR, value);
3801
3802 /* Adjust HSI48 oscillator smooth trimming */
3803 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
3804 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos));
3805
3806 /* START AUTOMATIC SYNCHRONIZATION*/
3807
3808 /* Enable Automatic trimming & Frequency error counter */
3809 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN);
3810 }
3811
3812 /**
3813 * @brief Generate the software synchronization event
3814 * @retval None
3815 */
HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)3816 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
3817 {
3818 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
3819 }
3820
3821 /**
3822 * @brief Return synchronization info
3823 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
3824 * @retval None
3825 */
HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef * pSynchroInfo)3826 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
3827 {
3828 /* Check the parameter */
3829 assert_param(pSynchroInfo != (void *) NULL);
3830
3831 /* Get the reload value */
3832 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
3833
3834 /* Get HSI48 oscillator smooth trimming */
3835 pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
3836
3837 /* Get Frequency error capture */
3838 pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
3839
3840 /* Get Frequency error direction */
3841 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
3842 }
3843
3844 /**
3845 * @brief Wait for CRS Synchronization status.
3846 * @param Timeout Duration of the timeout
3847 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
3848 * frequency.
3849 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
3850 * @retval Combination of Synchronization status
3851 * This parameter can be a combination of the following values:
3852 * @arg @ref RCC_CRS_TIMEOUT
3853 * @arg @ref RCC_CRS_SYNCOK
3854 * @arg @ref RCC_CRS_SYNCWARN
3855 * @arg @ref RCC_CRS_SYNCERR
3856 * @arg @ref RCC_CRS_SYNCMISS
3857 * @arg @ref RCC_CRS_TRIMOVF
3858 */
HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)3859 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
3860 {
3861 uint32_t crsstatus = RCC_CRS_NONE;
3862 uint32_t tickstart;
3863
3864 /* Get timeout */
3865 tickstart = HAL_GetTick();
3866
3867 /* Wait for CRS flag or timeout detection */
3868 do
3869 {
3870 if (Timeout != HAL_MAX_DELAY)
3871 {
3872 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3873 {
3874 crsstatus = RCC_CRS_TIMEOUT;
3875 }
3876 }
3877 /* Check CRS SYNCOK flag */
3878 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
3879 {
3880 /* CRS SYNC event OK */
3881 crsstatus |= RCC_CRS_SYNCOK;
3882
3883 /* Clear CRS SYNC event OK bit */
3884 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
3885 }
3886
3887 /* Check CRS SYNCWARN flag */
3888 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
3889 {
3890 /* CRS SYNC warning */
3891 crsstatus |= RCC_CRS_SYNCWARN;
3892
3893 /* Clear CRS SYNCWARN bit */
3894 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
3895 }
3896
3897 /* Check CRS TRIM overflow flag */
3898 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
3899 {
3900 /* CRS SYNC Error */
3901 crsstatus |= RCC_CRS_TRIMOVF;
3902
3903 /* Clear CRS Error bit */
3904 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
3905 }
3906
3907 /* Check CRS Error flag */
3908 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
3909 {
3910 /* CRS SYNC Error */
3911 crsstatus |= RCC_CRS_SYNCERR;
3912
3913 /* Clear CRS Error bit */
3914 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
3915 }
3916
3917 /* Check CRS SYNC Missed flag */
3918 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
3919 {
3920 /* CRS SYNC Missed */
3921 crsstatus |= RCC_CRS_SYNCMISS;
3922
3923 /* Clear CRS SYNC Missed bit */
3924 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
3925 }
3926
3927 /* Check CRS Expected SYNC flag */
3928 if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
3929 {
3930 /* frequency error counter reached a zero value */
3931 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
3932 }
3933 } while (RCC_CRS_NONE == crsstatus);
3934
3935 return crsstatus;
3936 }
3937
3938 /**
3939 * @brief Handle the Clock Recovery System interrupt request.
3940 * @retval None
3941 */
HAL_RCCEx_CRS_IRQHandler(void)3942 void HAL_RCCEx_CRS_IRQHandler(void)
3943 {
3944 uint32_t crserror = RCC_CRS_NONE;
3945 /* Get current IT flags and IT sources values */
3946 uint32_t itflags = READ_REG(CRS->ISR);
3947 uint32_t itsources = READ_REG(CRS->CR);
3948
3949 /* Check CRS SYNCOK flag */
3950 if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
3951 {
3952 /* Clear CRS SYNC event OK flag */
3953 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
3954
3955 /* user callback */
3956 HAL_RCCEx_CRS_SyncOkCallback();
3957 }
3958 /* Check CRS SYNCWARN flag */
3959 else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
3960 {
3961 /* Clear CRS SYNCWARN flag */
3962 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
3963
3964 /* user callback */
3965 HAL_RCCEx_CRS_SyncWarnCallback();
3966 }
3967 /* Check CRS Expected SYNC flag */
3968 else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
3969 {
3970 /* frequency error counter reached a zero value */
3971 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
3972
3973 /* user callback */
3974 HAL_RCCEx_CRS_ExpectedSyncCallback();
3975 }
3976 /* Check CRS Error flags */
3977 else
3978 {
3979 if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
3980 {
3981 if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
3982 {
3983 crserror |= RCC_CRS_SYNCERR;
3984 }
3985 if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
3986 {
3987 crserror |= RCC_CRS_SYNCMISS;
3988 }
3989 if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
3990 {
3991 crserror |= RCC_CRS_TRIMOVF;
3992 }
3993
3994 /* Clear CRS Error flags */
3995 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
3996
3997 /* user error callback */
3998 HAL_RCCEx_CRS_ErrorCallback(crserror);
3999 }
4000 }
4001 }
4002
4003 /**
4004 * @brief RCCEx Clock Recovery System SYNCOK interrupt callback.
4005 * @retval none
4006 */
HAL_RCCEx_CRS_SyncOkCallback(void)4007 __weak void HAL_RCCEx_CRS_SyncOkCallback(void)
4008 {
4009 /* NOTE : This function should not be modified, when the callback is needed,
4010 the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file
4011 */
4012 }
4013
4014 /**
4015 * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback.
4016 * @retval none
4017 */
HAL_RCCEx_CRS_SyncWarnCallback(void)4018 __weak void HAL_RCCEx_CRS_SyncWarnCallback(void)
4019 {
4020 /* NOTE : This function should not be modified, when the callback is needed,
4021 the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file
4022 */
4023 }
4024
4025 /**
4026 * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback.
4027 * @retval none
4028 */
HAL_RCCEx_CRS_ExpectedSyncCallback(void)4029 __weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void)
4030 {
4031 /* NOTE : This function should not be modified, when the callback is needed,
4032 the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file
4033 */
4034 }
4035
4036 /**
4037 * @brief RCCEx Clock Recovery System Error interrupt callback.
4038 * @param Error Combination of Error status.
4039 * This parameter can be a combination of the following values:
4040 * @arg @ref RCC_CRS_SYNCERR
4041 * @arg @ref RCC_CRS_SYNCMISS
4042 * @arg @ref RCC_CRS_TRIMOVF
4043 * @retval none
4044 */
HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)4045 __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
4046 {
4047 /* Prevent unused argument(s) compilation warning */
4048 UNUSED(Error);
4049
4050 /* NOTE : This function should not be modified, when the callback is needed,
4051 the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file
4052 */
4053 }
4054
4055 /**
4056 * @}
4057 */
4058
4059 #endif /* CRS */
4060
4061 /**
4062 * @}
4063 */
4064
4065 /** @addtogroup RCCEx_Private_Functions
4066 * @{
4067 */
4068 /**
4069 * @brief Configure the PLL 1 source clock.
4070 * @param PllSource PLL1 source clock it can be :
4071 * RCC_PLLSOURCE_NONE
4072 * RCC_PLLSOURCE_MSI
4073 * RCC_PLLSOURCE_HSI
4074 * RCC_PLLSOURCE_HSE
4075 *
4076 * @retval HAL status
4077 */
RCCEx_PLLSource_Enable(uint32_t PllSource)4078 static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource)
4079 {
4080 uint32_t tickstart;
4081 HAL_StatusTypeDef status = HAL_OK;
4082
4083 switch (PllSource)
4084 {
4085 case RCC_PLLSOURCE_MSI:
4086 /* Check whether MSI in not ready and enable it */
4087 if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
4088 {
4089 /* Enable the Internal Multi Speed oscillator (MSI). */
4090 __HAL_RCC_MSI_ENABLE();
4091
4092 /* Get timeout */
4093 tickstart = HAL_GetTick();
4094
4095 /* Wait till MSI is ready */
4096 while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U)
4097 {
4098 if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
4099 {
4100 status = HAL_TIMEOUT;
4101 break;
4102 }
4103 }
4104 }
4105 break;
4106
4107 case RCC_PLLSOURCE_HSI:
4108 /* Check whether HSI in not ready and enable it */
4109 if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
4110 {
4111 /* Enable the Internal High Speed oscillator (HSI) */
4112 __HAL_RCC_HSI_ENABLE();
4113
4114 /* Get timeout */
4115 tickstart = HAL_GetTick();
4116
4117 /* Wait till MSI is ready */
4118 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
4119 {
4120 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
4121 {
4122 status = HAL_TIMEOUT;
4123 break;
4124 }
4125 }
4126 }
4127 break;
4128
4129 case RCC_PLLSOURCE_HSE:
4130 /* Check whether HSE in not ready and enable it */
4131 if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
4132 {
4133 /* Enable the External High Speed oscillator (HSE) */
4134 SET_BIT(RCC->CR, RCC_CR_HSEON);
4135
4136 /* Get Start Tick*/
4137 tickstart = HAL_GetTick();
4138
4139 /* Wait till HSE is ready */
4140 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
4141 {
4142 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
4143 {
4144 status = HAL_TIMEOUT;
4145 break;
4146 }
4147 }
4148 }
4149 break;
4150
4151 default:
4152 status = HAL_ERROR;
4153 break;
4154 }
4155
4156 return status;
4157 }
4158
4159 /**
4160 * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it
4161 * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that
4162 * contains the configuration parameters as well as VCI clock ranges.
4163 * @note PLL2 is temporary disabled to apply new parameters
4164 *
4165 * @retval HAL status
4166 */
RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef * pll2)4167 static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2)
4168 {
4169
4170 uint32_t tickstart;
4171 assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source));
4172 assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M));
4173 assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N));
4174 assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P));
4175 assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q));
4176 assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R));
4177
4178 /* Disable PLL2 */
4179 __HAL_RCC_PLL2_DISABLE();
4180
4181 /* Get Start Tick*/
4182 tickstart = HAL_GetTick();
4183
4184 /* Wait till PLL is ready */
4185 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
4186 {
4187 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
4188 {
4189 return HAL_TIMEOUT;
4190 }
4191 }
4192
4193 /* Configure PLL2 multiplication and division factors */
4194 __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source,
4195 pll2->PLL2M,
4196 pll2->PLL2N,
4197 pll2->PLL2P,
4198 pll2->PLL2Q,
4199 pll2->PLL2R);
4200
4201 /* Select PLL2 input reference frequency range: VCI */
4202 __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE);
4203
4204 /* Configure the PLL2 Clock output(s) */
4205 __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut);
4206
4207 /* Disable PLL2FRACN */
4208 __HAL_RCC_PLL2FRACN_DISABLE();
4209
4210 /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */
4211 __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
4212
4213 /* Enable PLL2FRACN */
4214 __HAL_RCC_PLL2FRACN_ENABLE();
4215
4216 /* Enable PLL2 */
4217 __HAL_RCC_PLL2_ENABLE();
4218
4219 /* Get Start Tick*/
4220 tickstart = HAL_GetTick();
4221
4222 /* Wait till PLL2 is ready */
4223 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
4224 {
4225 if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
4226 {
4227 return HAL_TIMEOUT;
4228 }
4229 }
4230 return HAL_OK;
4231
4232 }
4233
4234 /**
4235 * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it
4236 * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that
4237 * contains the configuration parameters as well as VCI clock ranges.
4238 * @note PLL3 is temporary disabled to apply new parameters
4239 * @retval HAL status
4240 */
RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef * pll3)4241 static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3)
4242 {
4243 uint32_t tickstart;
4244 assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source));
4245 assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M));
4246 assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N));
4247 assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P));
4248 assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q));
4249 assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R));
4250
4251 /* Disable PLL3 */
4252 __HAL_RCC_PLL3_DISABLE();
4253
4254 /* Get Start Tick*/
4255 tickstart = HAL_GetTick();
4256
4257 /* Wait till PLL is ready */
4258 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
4259 {
4260 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
4261 {
4262 return HAL_TIMEOUT;
4263 }
4264 }
4265
4266 /* Configure PLL3 multiplication and division factors */
4267 __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source,
4268 pll3->PLL3M,
4269 pll3->PLL3N,
4270 pll3->PLL3P,
4271 pll3->PLL3Q,
4272 pll3->PLL3R);
4273
4274 /* Select PLL3 input reference frequency range: VCI */
4275 __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE);
4276
4277 /* Configure the PLL3 Clock output(s) */
4278 __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut);
4279
4280 /* Disable PLL3FRACN */
4281 __HAL_RCC_PLL3FRACN_DISABLE();
4282
4283 /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */
4284 __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
4285
4286 /* Enable PLL3FRACN */
4287 __HAL_RCC_PLL3FRACN_ENABLE();
4288
4289 /* Enable PLL3 */
4290 __HAL_RCC_PLL3_ENABLE();
4291
4292 /* Get Start Tick*/
4293 tickstart = HAL_GetTick();
4294
4295 /* Wait till PLL3 is ready */
4296 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
4297 {
4298 if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
4299 {
4300 return HAL_TIMEOUT;
4301 }
4302 }
4303 return HAL_OK;
4304 }
4305
4306 /**
4307 * @}
4308 */
4309
4310 #endif /* HAL_RCC_MODULE_ENABLED */
4311 /**
4312 * @}
4313 */
4314
4315 /**
4316 * @}
4317 */
4318
4319 /**
4320 * @}
4321 */
4322
4323
