1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State and Errors functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2021 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for
43 the transmit or receive channel
44 (+++) Enable the DMAx interface clock using
45 (+++) Configure the DMA handle parameters
46 (+++) Configure the DMA Tx or Rx channel
47 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
48 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
49 the DMA Tx or Rx channel
50
51 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
52 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
53
54 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
55 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
56
57 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
58
59 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
60
61 *** Polling mode IO operation ***
62 =================================
63 [..]
64 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
65 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
66 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
67 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
68
69 *** Polling mode IO MEM operation ***
70 =====================================
71 [..]
72 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
73 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
74
75
76 *** Interrupt mode IO operation ***
77 ===================================
78 [..]
79 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
80 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
81 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
82 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
83 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
84 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
85 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
86 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
87 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
88 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
89 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
90 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
91 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
92 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
93 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
94 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
95 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
96 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
97 This action will inform Master to generate a Stop condition to discard the communication.
98
99
100 *** Interrupt mode or DMA mode IO sequential operation ***
101 ==========================================================
102 [..]
103 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
104 when a direction change during transfer
105 [..]
106 (+) A specific option field manage the different steps of a sequential transfer
107 (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
108 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
109 no sequential mode
110 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
111 and data to transfer without a final stop condition
112 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
113 start condition, address and data to transfer without a final stop condition,
114 an then permit a call the same master sequential interface several times
115 (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
116 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
117 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
118 and with new data to transfer if the direction change or manage only the new data to
119 transfer
120 if no direction change and without a final stop condition in both cases
121 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
122 and with new data to transfer if the direction change or manage only the new data to
123 transfer
124 if no direction change and with a final stop condition in both cases
125 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
126 after several call of the same master sequential interface several times
127 (link with option I2C_FIRST_AND_NEXT_FRAME).
128 Usage can, transfer several bytes one by one using
129 HAL_I2C_Master_Seq_Transmit_IT
130 or HAL_I2C_Master_Seq_Receive_IT
131 or HAL_I2C_Master_Seq_Transmit_DMA
132 or HAL_I2C_Master_Seq_Receive_DMA
133 with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
134 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
135 Receive sequence permit to call the opposite interface Receive or Transmit
136 without stopping the communication and so generate a restart condition.
137 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
138 each call of the same master sequential
139 interface.
140 Usage can, transfer several bytes one by one with a restart with slave address between
141 each bytes using
142 HAL_I2C_Master_Seq_Transmit_IT
143 or HAL_I2C_Master_Seq_Receive_IT
144 or HAL_I2C_Master_Seq_Transmit_DMA
145 or HAL_I2C_Master_Seq_Receive_DMA
146 with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
147 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
148 generation of STOP condition.
149
150 (+) Different sequential I2C interfaces are listed below:
151 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
152 HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
153 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
154 users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
155 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
156 HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
157 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
158 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
159 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
160 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
161 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
162 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
163 HAL_I2C_DisableListen_IT()
164 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
165 add their own code to check the Address Match Code and the transmission direction request by master
166 (Write/Read).
167 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
168 add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
169 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
170 HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
171 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
172 users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
173 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
174 HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
175 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
176 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
177 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
178 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
179 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
180 This action will inform Master to generate a Stop condition to discard the communication.
181
182 *** Interrupt mode IO MEM operation ***
183 =======================================
184 [..]
185 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
186 HAL_I2C_Mem_Write_IT()
187 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
188 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
189 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
190 HAL_I2C_Mem_Read_IT()
191 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
192 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
193 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
194 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
195
196 *** DMA mode IO operation ***
197 ==============================
198 [..]
199 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
200 HAL_I2C_Master_Transmit_DMA()
201 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
202 add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
203 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
204 HAL_I2C_Master_Receive_DMA()
205 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
206 add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
207 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
208 HAL_I2C_Slave_Transmit_DMA()
209 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
210 add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
211 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
212 HAL_I2C_Slave_Receive_DMA()
213 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
214 add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
215 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
216 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
217 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
218 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
219 add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
220 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
221 This action will inform Master to generate a Stop condition to discard the communication.
222
223 *** DMA mode IO MEM operation ***
224 =================================
225 [..]
226 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
227 HAL_I2C_Mem_Write_DMA()
228 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
229 add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
230 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
231 HAL_I2C_Mem_Read_DMA()
232 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
233 add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
234 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
235 add their own code by customization of function pointer HAL_I2C_ErrorCallback()
236
237
238 *** I2C HAL driver macros list ***
239 ==================================
240 [..]
241 Below the list of most used macros in I2C HAL driver.
242
243 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
244 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
245 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
246 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
247 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
248 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
249 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
250
251 *** Callback registration ***
252 =============================================
253 [..]
254 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
255 allows the user to configure dynamically the driver callbacks.
256 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
257 to register an interrupt callback.
258 [..]
259 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
260 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
261 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
262 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
263 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
264 (+) ListenCpltCallback : callback for end of listen mode.
265 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
266 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
267 (+) ErrorCallback : callback for error detection.
268 (+) AbortCpltCallback : callback for abort completion process.
269 (+) MspInitCallback : callback for Msp Init.
270 (+) MspDeInitCallback : callback for Msp DeInit.
271 This function takes as parameters the HAL peripheral handle, the Callback ID
272 and a pointer to the user callback function.
273 [..]
274 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
275 [..]
276 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
277 weak function.
278 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
279 and the Callback ID.
280 This function allows to reset following callbacks:
281 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
282 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
283 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
284 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
285 (+) ListenCpltCallback : callback for end of listen mode.
286 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
287 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
288 (+) ErrorCallback : callback for error detection.
289 (+) AbortCpltCallback : callback for abort completion process.
290 (+) MspInitCallback : callback for Msp Init.
291 (+) MspDeInitCallback : callback for Msp DeInit.
292 [..]
293 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
294 [..]
295 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
296 all callbacks are set to the corresponding weak functions:
297 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
298 Exception done for MspInit and MspDeInit functions that are
299 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
300 these callbacks are null (not registered beforehand).
301 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
302 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
303 [..]
304 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
305 Exception done MspInit/MspDeInit functions that can be registered/unregistered
306 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
307 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
308 Then, the user first registers the MspInit/MspDeInit user callbacks
309 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
310 or HAL_I2C_Init() function.
311 [..]
312 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
313 not defined, the callback registration feature is not available and all callbacks
314 are set to the corresponding weak functions.
315
316 [..]
317 (@) You can refer to the I2C HAL driver header file for more useful macros
318
319 @endverbatim
320 */
321
322 /* Includes ------------------------------------------------------------------*/
323 #include "stm32u5xx_hal.h"
324
325 /** @addtogroup STM32U5xx_HAL_Driver
326 * @{
327 */
328
329 /** @defgroup I2C I2C
330 * @brief I2C HAL module driver
331 * @{
332 */
333
334 #ifdef HAL_I2C_MODULE_ENABLED
335
336 /* Private typedef -----------------------------------------------------------*/
337 /* Private define ------------------------------------------------------------*/
338
339 /** @defgroup I2C_Private_Define I2C Private Define
340 * @{
341 */
342 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
343 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
344 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
345 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
346 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
347 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
348 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
349 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
350 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
351 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
352
353 #define MAX_NBYTE_SIZE 255U
354 #define SLAVE_ADDR_SHIFT 7U
355 #define SLAVE_ADDR_MSK 0x06U
356
357 /* Private define for @ref PreviousState usage */
358 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
359 (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
360 (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
361 /*!< Mask State define, keep only RX and TX bits */
362 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE))
363 /*!< Default Value */
364 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
365 (uint32_t)HAL_I2C_MODE_MASTER))
366 /*!< Master Busy TX, combinaison of State LSB and Mode enum */
367 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
368 (uint32_t)HAL_I2C_MODE_MASTER))
369 /*!< Master Busy RX, combinaison of State LSB and Mode enum */
370 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
371 (uint32_t)HAL_I2C_MODE_SLAVE))
372 /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
373 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
374 (uint32_t)HAL_I2C_MODE_SLAVE))
375 /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
376 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
377 (uint32_t)HAL_I2C_MODE_MEM))
378 /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
379 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
380 (uint32_t)HAL_I2C_MODE_MEM))
381 /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
382
383
384 /* Private define to centralize the enable/disable of Interrupts */
385 #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with
386 @ref I2C_XFER_LISTEN_IT */
387 #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with
388 @ref I2C_XFER_LISTEN_IT */
389 #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
390 and @ref I2C_XFER_RX_IT */
391
392 #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error
393 and NACK treatment */
394 #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */
395 #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */
396
397 /* Private define Sequential Transfer Options default/reset value */
398 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
399 /**
400 * @}
401 */
402
403 /* Private macros ------------------------------------------------------------*/
404 /** @addtogroup I2C_Private_Macro
405 * @{
406 */
407 #if defined(HAL_DMA_MODULE_ENABLED)
408 /* Macro to get remaining data to transfer on DMA side */
409 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__))
410 #endif /* HAL_DMA_MODULE_ENABLED */
411 /**
412 * @}
413 */
414
415 /* Private variables ---------------------------------------------------------*/
416 /* Private function prototypes -----------------------------------------------*/
417
418 /** @defgroup I2C_Private_Functions I2C Private Functions
419 * @{
420 */
421 #if defined(HAL_DMA_MODULE_ENABLED)
422 /* Private functions to handle DMA transfer */
423 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
424 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
425 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
426 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
427 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
428 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
429
430 #endif /* HAL_DMA_MODULE_ENABLED */
431
432 /* Private functions to handle IT transfer */
433 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
434 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
435 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c);
436 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
437 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
438 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
439 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
440
441 /* Private functions to handle IT transfer */
442 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
443 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
444 uint32_t Tickstart);
445 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
446 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
447 uint32_t Tickstart);
448
449 /* Private functions for I2C transfer IRQ handler */
450 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
451 uint32_t ITSources);
452 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
453 uint32_t ITSources);
454 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
455 uint32_t ITSources);
456 #if defined(HAL_DMA_MODULE_ENABLED)
457 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
458 uint32_t ITSources);
459 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
460 uint32_t ITSources);
461 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
462 uint32_t ITSources);
463 #endif /* HAL_DMA_MODULE_ENABLED */
464
465 /* Private functions to handle flags during polling transfer */
466 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
467 uint32_t Timeout, uint32_t Tickstart);
468 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
469 uint32_t Tickstart);
470 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
471 uint32_t Tickstart);
472 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
473 uint32_t Tickstart);
474 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
475 uint32_t Tickstart);
476
477 /* Private functions to centralize the enable/disable of Interrupts */
478 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
479 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
480
481 /* Private function to treat different error callback */
482 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c);
483
484 /* Private function to flush TXDR register */
485 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
486
487 /* Private function to handle start, restart or stop a transfer */
488 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
489 uint32_t Request);
490
491 /* Private function to Convert Specific options */
492 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
493 /**
494 * @}
495 */
496
497 /* Exported functions --------------------------------------------------------*/
498
499 /** @defgroup I2C_Exported_Functions I2C Exported Functions
500 * @{
501 */
502
503 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
504 * @brief Initialization and Configuration functions
505 *
506 @verbatim
507 ===============================================================================
508 ##### Initialization and de-initialization functions #####
509 ===============================================================================
510 [..] This subsection provides a set of functions allowing to initialize and
511 deinitialize the I2Cx peripheral:
512
513 (+) User must Implement HAL_I2C_MspInit() function in which he configures
514 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
515
516 (+) Call the function HAL_I2C_Init() to configure the selected device with
517 the selected configuration:
518 (++) Clock Timing
519 (++) Own Address 1
520 (++) Addressing mode (Master, Slave)
521 (++) Dual Addressing mode
522 (++) Own Address 2
523 (++) Own Address 2 Mask
524 (++) General call mode
525 (++) Nostretch mode
526
527 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
528 of the selected I2Cx peripheral.
529
530 @endverbatim
531 * @{
532 */
533
534 /**
535 * @brief Initializes the I2C according to the specified parameters
536 * in the I2C_InitTypeDef and initialize the associated handle.
537 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
538 * the configuration information for the specified I2C.
539 * @retval HAL status
540 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)541 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
542 {
543 /* Check the I2C handle allocation */
544 if (hi2c == NULL)
545 {
546 return HAL_ERROR;
547 }
548
549 /* Check the parameters */
550 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
551 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
552 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
553 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
554 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
555 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
556 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
557 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
558
559 if (hi2c->State == HAL_I2C_STATE_RESET)
560 {
561 /* Allocate lock resource and initialize it */
562 hi2c->Lock = HAL_UNLOCKED;
563
564 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
565 /* Init the I2C Callback settings */
566 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
567 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
568 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
569 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
570 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
571 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
572 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
573 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
574 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
575 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
576
577 if (hi2c->MspInitCallback == NULL)
578 {
579 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
580 }
581
582 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
583 hi2c->MspInitCallback(hi2c);
584 #else
585 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
586 HAL_I2C_MspInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588 }
589
590 hi2c->State = HAL_I2C_STATE_BUSY;
591
592 /* Disable the selected I2C peripheral */
593 __HAL_I2C_DISABLE(hi2c);
594
595 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
596 /* Configure I2Cx: Frequency range */
597 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
598
599 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
600 /* Disable Own Address1 before set the Own Address1 configuration */
601 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
602
603 /* Configure I2Cx: Own Address1 and ack own address1 mode */
604 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
605 {
606 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
607 }
608 else /* I2C_ADDRESSINGMODE_10BIT */
609 {
610 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
611 }
612
613 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
614 /* Configure I2Cx: Addressing Master mode */
615 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
616 {
617 SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
618 }
619 else
620 {
621 /* Clear the I2C ADD10 bit */
622 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
623 }
624 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
625 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
626
627 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
628 /* Disable Own Address2 before set the Own Address2 configuration */
629 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
630
631 /* Configure I2Cx: Dual mode and Own Address2 */
632 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
633 (hi2c->Init.OwnAddress2Masks << 8));
634
635 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
636 /* Configure I2Cx: Generalcall and NoStretch mode */
637 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
638
639 /* Enable the selected I2C peripheral */
640 __HAL_I2C_ENABLE(hi2c);
641
642 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
643 hi2c->State = HAL_I2C_STATE_READY;
644 hi2c->PreviousState = I2C_STATE_NONE;
645 hi2c->Mode = HAL_I2C_MODE_NONE;
646
647 return HAL_OK;
648 }
649
650 /**
651 * @brief DeInitialize the I2C peripheral.
652 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
653 * the configuration information for the specified I2C.
654 * @retval HAL status
655 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)656 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
657 {
658 /* Check the I2C handle allocation */
659 if (hi2c == NULL)
660 {
661 return HAL_ERROR;
662 }
663
664 /* Check the parameters */
665 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
666
667 hi2c->State = HAL_I2C_STATE_BUSY;
668
669 /* Disable the I2C Peripheral Clock */
670 __HAL_I2C_DISABLE(hi2c);
671
672 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
673 if (hi2c->MspDeInitCallback == NULL)
674 {
675 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
676 }
677
678 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
679 hi2c->MspDeInitCallback(hi2c);
680 #else
681 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
682 HAL_I2C_MspDeInit(hi2c);
683 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
684
685 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
686 hi2c->State = HAL_I2C_STATE_RESET;
687 hi2c->PreviousState = I2C_STATE_NONE;
688 hi2c->Mode = HAL_I2C_MODE_NONE;
689
690 /* Release Lock */
691 __HAL_UNLOCK(hi2c);
692
693 return HAL_OK;
694 }
695
696 /**
697 * @brief Initialize the I2C MSP.
698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
699 * the configuration information for the specified I2C.
700 * @retval None
701 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)702 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
703 {
704 /* Prevent unused argument(s) compilation warning */
705 UNUSED(hi2c);
706
707 /* NOTE : This function should not be modified, when the callback is needed,
708 the HAL_I2C_MspInit could be implemented in the user file
709 */
710 }
711
712 /**
713 * @brief DeInitialize the I2C MSP.
714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
715 * the configuration information for the specified I2C.
716 * @retval None
717 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)718 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
719 {
720 /* Prevent unused argument(s) compilation warning */
721 UNUSED(hi2c);
722
723 /* NOTE : This function should not be modified, when the callback is needed,
724 the HAL_I2C_MspDeInit could be implemented in the user file
725 */
726 }
727
728 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
729 /**
730 * @brief Register a User I2C Callback
731 * To be used instead of the weak predefined callback
732 * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
733 * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
735 * the configuration information for the specified I2C.
736 * @param CallbackID ID of the callback to be registered
737 * This parameter can be one of the following values:
738 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
739 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
740 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
741 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
742 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
743 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
744 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
745 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
746 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
747 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
748 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
749 * @param pCallback pointer to the Callback function
750 * @retval HAL status
751 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)752 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
753 pI2C_CallbackTypeDef pCallback)
754 {
755 HAL_StatusTypeDef status = HAL_OK;
756
757 if (pCallback == NULL)
758 {
759 /* Update the error code */
760 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
761
762 return HAL_ERROR;
763 }
764
765 if (HAL_I2C_STATE_READY == hi2c->State)
766 {
767 switch (CallbackID)
768 {
769 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
770 hi2c->MasterTxCpltCallback = pCallback;
771 break;
772
773 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
774 hi2c->MasterRxCpltCallback = pCallback;
775 break;
776
777 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
778 hi2c->SlaveTxCpltCallback = pCallback;
779 break;
780
781 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
782 hi2c->SlaveRxCpltCallback = pCallback;
783 break;
784
785 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
786 hi2c->ListenCpltCallback = pCallback;
787 break;
788
789 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
790 hi2c->MemTxCpltCallback = pCallback;
791 break;
792
793 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
794 hi2c->MemRxCpltCallback = pCallback;
795 break;
796
797 case HAL_I2C_ERROR_CB_ID :
798 hi2c->ErrorCallback = pCallback;
799 break;
800
801 case HAL_I2C_ABORT_CB_ID :
802 hi2c->AbortCpltCallback = pCallback;
803 break;
804
805 case HAL_I2C_MSPINIT_CB_ID :
806 hi2c->MspInitCallback = pCallback;
807 break;
808
809 case HAL_I2C_MSPDEINIT_CB_ID :
810 hi2c->MspDeInitCallback = pCallback;
811 break;
812
813 default :
814 /* Update the error code */
815 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
816
817 /* Return error status */
818 status = HAL_ERROR;
819 break;
820 }
821 }
822 else if (HAL_I2C_STATE_RESET == hi2c->State)
823 {
824 switch (CallbackID)
825 {
826 case HAL_I2C_MSPINIT_CB_ID :
827 hi2c->MspInitCallback = pCallback;
828 break;
829
830 case HAL_I2C_MSPDEINIT_CB_ID :
831 hi2c->MspDeInitCallback = pCallback;
832 break;
833
834 default :
835 /* Update the error code */
836 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
837
838 /* Return error status */
839 status = HAL_ERROR;
840 break;
841 }
842 }
843 else
844 {
845 /* Update the error code */
846 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
847
848 /* Return error status */
849 status = HAL_ERROR;
850 }
851
852 return status;
853 }
854
855 /**
856 * @brief Unregister an I2C Callback
857 * I2C callback is redirected to the weak predefined callback
858 * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
859 * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
860 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
861 * the configuration information for the specified I2C.
862 * @param CallbackID ID of the callback to be unregistered
863 * This parameter can be one of the following values:
864 * This parameter can be one of the following values:
865 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
866 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
867 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
868 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
869 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
870 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
871 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
872 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
873 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
874 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
875 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
876 * @retval HAL status
877 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)878 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
879 {
880 HAL_StatusTypeDef status = HAL_OK;
881
882 if (HAL_I2C_STATE_READY == hi2c->State)
883 {
884 switch (CallbackID)
885 {
886 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
887 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
888 break;
889
890 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
891 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
892 break;
893
894 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
895 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
896 break;
897
898 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
899 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
900 break;
901
902 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
903 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
904 break;
905
906 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
907 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
908 break;
909
910 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
911 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
912 break;
913
914 case HAL_I2C_ERROR_CB_ID :
915 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
916 break;
917
918 case HAL_I2C_ABORT_CB_ID :
919 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
920 break;
921
922 case HAL_I2C_MSPINIT_CB_ID :
923 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
924 break;
925
926 case HAL_I2C_MSPDEINIT_CB_ID :
927 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
928 break;
929
930 default :
931 /* Update the error code */
932 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
933
934 /* Return error status */
935 status = HAL_ERROR;
936 break;
937 }
938 }
939 else if (HAL_I2C_STATE_RESET == hi2c->State)
940 {
941 switch (CallbackID)
942 {
943 case HAL_I2C_MSPINIT_CB_ID :
944 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
945 break;
946
947 case HAL_I2C_MSPDEINIT_CB_ID :
948 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
949 break;
950
951 default :
952 /* Update the error code */
953 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
954
955 /* Return error status */
956 status = HAL_ERROR;
957 break;
958 }
959 }
960 else
961 {
962 /* Update the error code */
963 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
964
965 /* Return error status */
966 status = HAL_ERROR;
967 }
968
969 return status;
970 }
971
972 /**
973 * @brief Register the Slave Address Match I2C Callback
974 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
975 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
976 * the configuration information for the specified I2C.
977 * @param pCallback pointer to the Address Match Callback function
978 * @retval HAL status
979 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)980 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
981 {
982 HAL_StatusTypeDef status = HAL_OK;
983
984 if (pCallback == NULL)
985 {
986 /* Update the error code */
987 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
988
989 return HAL_ERROR;
990 }
991
992 if (HAL_I2C_STATE_READY == hi2c->State)
993 {
994 hi2c->AddrCallback = pCallback;
995 }
996 else
997 {
998 /* Update the error code */
999 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1000
1001 /* Return error status */
1002 status = HAL_ERROR;
1003 }
1004
1005 return status;
1006 }
1007
1008 /**
1009 * @brief UnRegister the Slave Address Match I2C Callback
1010 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
1011 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1012 * the configuration information for the specified I2C.
1013 * @retval HAL status
1014 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)1015 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
1016 {
1017 HAL_StatusTypeDef status = HAL_OK;
1018
1019 if (HAL_I2C_STATE_READY == hi2c->State)
1020 {
1021 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
1022 }
1023 else
1024 {
1025 /* Update the error code */
1026 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
1027
1028 /* Return error status */
1029 status = HAL_ERROR;
1030 }
1031
1032 return status;
1033 }
1034
1035 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
1036
1037 /**
1038 * @}
1039 */
1040
1041 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
1042 * @brief Data transfers functions
1043 *
1044 @verbatim
1045 ===============================================================================
1046 ##### IO operation functions #####
1047 ===============================================================================
1048 [..]
1049 This subsection provides a set of functions allowing to manage the I2C data
1050 transfers.
1051
1052 (#) There are two modes of transfer:
1053 (++) Blocking mode : The communication is performed in the polling mode.
1054 The status of all data processing is returned by the same function
1055 after finishing transfer.
1056 (++) No-Blocking mode : The communication is performed using Interrupts
1057 or DMA. These functions return the status of the transfer startup.
1058 The end of the data processing will be indicated through the
1059 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
1060 using DMA mode.
1061
1062 (#) Blocking mode functions are :
1063 (++) HAL_I2C_Master_Transmit()
1064 (++) HAL_I2C_Master_Receive()
1065 (++) HAL_I2C_Slave_Transmit()
1066 (++) HAL_I2C_Slave_Receive()
1067 (++) HAL_I2C_Mem_Write()
1068 (++) HAL_I2C_Mem_Read()
1069 (++) HAL_I2C_IsDeviceReady()
1070
1071 (#) No-Blocking mode functions with Interrupt are :
1072 (++) HAL_I2C_Master_Transmit_IT()
1073 (++) HAL_I2C_Master_Receive_IT()
1074 (++) HAL_I2C_Slave_Transmit_IT()
1075 (++) HAL_I2C_Slave_Receive_IT()
1076 (++) HAL_I2C_Mem_Write_IT()
1077 (++) HAL_I2C_Mem_Read_IT()
1078 (++) HAL_I2C_Master_Seq_Transmit_IT()
1079 (++) HAL_I2C_Master_Seq_Receive_IT()
1080 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1081 (++) HAL_I2C_Slave_Seq_Receive_IT()
1082 (++) HAL_I2C_EnableListen_IT()
1083 (++) HAL_I2C_DisableListen_IT()
1084 (++) HAL_I2C_Master_Abort_IT()
1085
1086 (#) No-Blocking mode functions with DMA are :
1087 (++) HAL_I2C_Master_Transmit_DMA()
1088 (++) HAL_I2C_Master_Receive_DMA()
1089 (++) HAL_I2C_Slave_Transmit_DMA()
1090 (++) HAL_I2C_Slave_Receive_DMA()
1091 (++) HAL_I2C_Mem_Write_DMA()
1092 (++) HAL_I2C_Mem_Read_DMA()
1093 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1094 (++) HAL_I2C_Master_Seq_Receive_DMA()
1095 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1096 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1097
1098 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1099 (++) HAL_I2C_MasterTxCpltCallback()
1100 (++) HAL_I2C_MasterRxCpltCallback()
1101 (++) HAL_I2C_SlaveTxCpltCallback()
1102 (++) HAL_I2C_SlaveRxCpltCallback()
1103 (++) HAL_I2C_MemTxCpltCallback()
1104 (++) HAL_I2C_MemRxCpltCallback()
1105 (++) HAL_I2C_AddrCallback()
1106 (++) HAL_I2C_ListenCpltCallback()
1107 (++) HAL_I2C_ErrorCallback()
1108 (++) HAL_I2C_AbortCpltCallback()
1109
1110 @endverbatim
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Transmits in master mode an amount of data in blocking mode.
1116 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1117 * the configuration information for the specified I2C.
1118 * @param DevAddress Target device address: The device 7 bits address value
1119 * in datasheet must be shifted to the left before calling the interface
1120 * @param pData Pointer to data buffer
1121 * @param Size Amount of data to be sent
1122 * @param Timeout Timeout duration
1123 * @retval HAL status
1124 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1125 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1126 uint16_t Size, uint32_t Timeout)
1127 {
1128 uint32_t tickstart;
1129
1130 if (hi2c->State == HAL_I2C_STATE_READY)
1131 {
1132 /* Process Locked */
1133 __HAL_LOCK(hi2c);
1134
1135 /* Init tickstart for timeout management*/
1136 tickstart = HAL_GetTick();
1137
1138 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1139 {
1140 return HAL_ERROR;
1141 }
1142
1143 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1144 hi2c->Mode = HAL_I2C_MODE_MASTER;
1145 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1146
1147 /* Prepare transfer parameters */
1148 hi2c->pBuffPtr = pData;
1149 hi2c->XferCount = Size;
1150 hi2c->XferISR = NULL;
1151
1152 /* Send Slave Address */
1153 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1154 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1155 {
1156 hi2c->XferSize = MAX_NBYTE_SIZE;
1157 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1158 I2C_GENERATE_START_WRITE);
1159 }
1160 else
1161 {
1162 hi2c->XferSize = hi2c->XferCount;
1163 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1164 I2C_GENERATE_START_WRITE);
1165 }
1166
1167 while (hi2c->XferCount > 0U)
1168 {
1169 /* Wait until TXIS flag is set */
1170 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1171 {
1172 return HAL_ERROR;
1173 }
1174 /* Write data to TXDR */
1175 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1176
1177 /* Increment Buffer pointer */
1178 hi2c->pBuffPtr++;
1179
1180 hi2c->XferCount--;
1181 hi2c->XferSize--;
1182
1183 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1184 {
1185 /* Wait until TCR flag is set */
1186 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1187 {
1188 return HAL_ERROR;
1189 }
1190
1191 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1192 {
1193 hi2c->XferSize = MAX_NBYTE_SIZE;
1194 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1195 I2C_NO_STARTSTOP);
1196 }
1197 else
1198 {
1199 hi2c->XferSize = hi2c->XferCount;
1200 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1201 I2C_NO_STARTSTOP);
1202 }
1203 }
1204 }
1205
1206 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1207 /* Wait until STOPF flag is set */
1208 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1209 {
1210 return HAL_ERROR;
1211 }
1212
1213 /* Clear STOP Flag */
1214 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1215
1216 /* Clear Configuration Register 2 */
1217 I2C_RESET_CR2(hi2c);
1218
1219 hi2c->State = HAL_I2C_STATE_READY;
1220 hi2c->Mode = HAL_I2C_MODE_NONE;
1221
1222 /* Process Unlocked */
1223 __HAL_UNLOCK(hi2c);
1224
1225 return HAL_OK;
1226 }
1227 else
1228 {
1229 return HAL_BUSY;
1230 }
1231 }
1232
1233 /**
1234 * @brief Receives in master mode an amount of data in blocking mode.
1235 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1236 * the configuration information for the specified I2C.
1237 * @param DevAddress Target device address: The device 7 bits address value
1238 * in datasheet must be shifted to the left before calling the interface
1239 * @param pData Pointer to data buffer
1240 * @param Size Amount of data to be sent
1241 * @param Timeout Timeout duration
1242 * @retval HAL status
1243 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1244 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1245 uint16_t Size, uint32_t Timeout)
1246 {
1247 uint32_t tickstart;
1248
1249 if (hi2c->State == HAL_I2C_STATE_READY)
1250 {
1251 /* Process Locked */
1252 __HAL_LOCK(hi2c);
1253
1254 /* Init tickstart for timeout management*/
1255 tickstart = HAL_GetTick();
1256
1257 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1258 {
1259 return HAL_ERROR;
1260 }
1261
1262 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1263 hi2c->Mode = HAL_I2C_MODE_MASTER;
1264 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1265
1266 /* Prepare transfer parameters */
1267 hi2c->pBuffPtr = pData;
1268 hi2c->XferCount = Size;
1269 hi2c->XferISR = NULL;
1270
1271 /* Send Slave Address */
1272 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1273 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1274 {
1275 hi2c->XferSize = MAX_NBYTE_SIZE;
1276 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1277 I2C_GENERATE_START_READ);
1278 }
1279 else
1280 {
1281 hi2c->XferSize = hi2c->XferCount;
1282 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1283 I2C_GENERATE_START_READ);
1284 }
1285
1286 while (hi2c->XferCount > 0U)
1287 {
1288 /* Wait until RXNE flag is set */
1289 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1290 {
1291 return HAL_ERROR;
1292 }
1293
1294 /* Read data from RXDR */
1295 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1296
1297 /* Increment Buffer pointer */
1298 hi2c->pBuffPtr++;
1299
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
1304 {
1305 /* Wait until TCR flag is set */
1306 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1307 {
1308 return HAL_ERROR;
1309 }
1310
1311 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1312 {
1313 hi2c->XferSize = MAX_NBYTE_SIZE;
1314 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
1315 I2C_NO_STARTSTOP);
1316 }
1317 else
1318 {
1319 hi2c->XferSize = hi2c->XferCount;
1320 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
1321 I2C_NO_STARTSTOP);
1322 }
1323 }
1324 }
1325
1326 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1327 /* Wait until STOPF flag is set */
1328 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1329 {
1330 return HAL_ERROR;
1331 }
1332
1333 /* Clear STOP Flag */
1334 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1335
1336 /* Clear Configuration Register 2 */
1337 I2C_RESET_CR2(hi2c);
1338
1339 hi2c->State = HAL_I2C_STATE_READY;
1340 hi2c->Mode = HAL_I2C_MODE_NONE;
1341
1342 /* Process Unlocked */
1343 __HAL_UNLOCK(hi2c);
1344
1345 return HAL_OK;
1346 }
1347 else
1348 {
1349 return HAL_BUSY;
1350 }
1351 }
1352
1353 /**
1354 * @brief Transmits in slave mode an amount of data in blocking mode.
1355 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1356 * the configuration information for the specified I2C.
1357 * @param pData Pointer to data buffer
1358 * @param Size Amount of data to be sent
1359 * @param Timeout Timeout duration
1360 * @retval HAL status
1361 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1362 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1363 uint32_t Timeout)
1364 {
1365 uint32_t tickstart;
1366
1367 if (hi2c->State == HAL_I2C_STATE_READY)
1368 {
1369 if ((pData == NULL) || (Size == 0U))
1370 {
1371 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1372 return HAL_ERROR;
1373 }
1374 /* Process Locked */
1375 __HAL_LOCK(hi2c);
1376
1377 /* Init tickstart for timeout management*/
1378 tickstart = HAL_GetTick();
1379
1380 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1381 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1382 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1383
1384 /* Prepare transfer parameters */
1385 hi2c->pBuffPtr = pData;
1386 hi2c->XferCount = Size;
1387 hi2c->XferISR = NULL;
1388
1389 /* Enable Address Acknowledge */
1390 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1391
1392 /* Wait until ADDR flag is set */
1393 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1394 {
1395 /* Disable Address Acknowledge */
1396 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1397 return HAL_ERROR;
1398 }
1399
1400 /* Preload TX data if no stretch enable */
1401 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1402 {
1403 /* Preload TX register */
1404 /* Write data to TXDR */
1405 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1406
1407 /* Increment Buffer pointer */
1408 hi2c->pBuffPtr++;
1409
1410 hi2c->XferCount--;
1411 }
1412
1413 /* Clear ADDR flag */
1414 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1415
1416 /* If 10bit addressing mode is selected */
1417 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1418 {
1419 /* Wait until ADDR flag is set */
1420 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1421 {
1422 /* Disable Address Acknowledge */
1423 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1424 return HAL_ERROR;
1425 }
1426
1427 /* Clear ADDR flag */
1428 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1429 }
1430
1431 /* Wait until DIR flag is set Transmitter mode */
1432 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
1433 {
1434 /* Disable Address Acknowledge */
1435 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1436 return HAL_ERROR;
1437 }
1438
1439 while (hi2c->XferCount > 0U)
1440 {
1441 /* Wait until TXIS flag is set */
1442 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1443 {
1444 /* Disable Address Acknowledge */
1445 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1446 return HAL_ERROR;
1447 }
1448
1449 /* Write data to TXDR */
1450 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1451
1452 /* Increment Buffer pointer */
1453 hi2c->pBuffPtr++;
1454
1455 hi2c->XferCount--;
1456 }
1457
1458 /* Wait until AF flag is set */
1459 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1460 {
1461 /* Disable Address Acknowledge */
1462 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1463 return HAL_ERROR;
1464 }
1465
1466 /* Flush TX register */
1467 I2C_Flush_TXDR(hi2c);
1468
1469 /* Clear AF flag */
1470 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1471
1472 /* Wait until STOP flag is set */
1473 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1474 {
1475 /* Disable Address Acknowledge */
1476 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1477
1478 return HAL_ERROR;
1479 }
1480
1481 /* Clear STOP flag */
1482 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1483
1484 /* Wait until BUSY flag is reset */
1485 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1486 {
1487 /* Disable Address Acknowledge */
1488 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1489 return HAL_ERROR;
1490 }
1491
1492 /* Disable Address Acknowledge */
1493 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1494
1495 hi2c->State = HAL_I2C_STATE_READY;
1496 hi2c->Mode = HAL_I2C_MODE_NONE;
1497
1498 /* Process Unlocked */
1499 __HAL_UNLOCK(hi2c);
1500
1501 return HAL_OK;
1502 }
1503 else
1504 {
1505 return HAL_BUSY;
1506 }
1507 }
1508
1509 /**
1510 * @brief Receive in slave mode an amount of data in blocking mode
1511 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1512 * the configuration information for the specified I2C.
1513 * @param pData Pointer to data buffer
1514 * @param Size Amount of data to be sent
1515 * @param Timeout Timeout duration
1516 * @retval HAL status
1517 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1518 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
1519 uint32_t Timeout)
1520 {
1521 uint32_t tickstart;
1522
1523 if (hi2c->State == HAL_I2C_STATE_READY)
1524 {
1525 if ((pData == NULL) || (Size == 0U))
1526 {
1527 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
1528 return HAL_ERROR;
1529 }
1530 /* Process Locked */
1531 __HAL_LOCK(hi2c);
1532
1533 /* Init tickstart for timeout management*/
1534 tickstart = HAL_GetTick();
1535
1536 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1537 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1538 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1539
1540 /* Prepare transfer parameters */
1541 hi2c->pBuffPtr = pData;
1542 hi2c->XferCount = Size;
1543 hi2c->XferSize = hi2c->XferCount;
1544 hi2c->XferISR = NULL;
1545
1546 /* Enable Address Acknowledge */
1547 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1548
1549 /* Wait until ADDR flag is set */
1550 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1551 {
1552 /* Disable Address Acknowledge */
1553 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1554 return HAL_ERROR;
1555 }
1556
1557 /* Clear ADDR flag */
1558 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
1559
1560 /* Wait until DIR flag is reset Receiver mode */
1561 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1562 {
1563 /* Disable Address Acknowledge */
1564 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1565 return HAL_ERROR;
1566 }
1567
1568 while (hi2c->XferCount > 0U)
1569 {
1570 /* Wait until RXNE flag is set */
1571 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1572 {
1573 /* Disable Address Acknowledge */
1574 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1575
1576 /* Store Last receive data if any */
1577 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1578 {
1579 /* Read data from RXDR */
1580 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1581
1582 /* Increment Buffer pointer */
1583 hi2c->pBuffPtr++;
1584
1585 hi2c->XferCount--;
1586 hi2c->XferSize--;
1587 }
1588
1589 return HAL_ERROR;
1590 }
1591
1592 /* Read data from RXDR */
1593 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
1594
1595 /* Increment Buffer pointer */
1596 hi2c->pBuffPtr++;
1597
1598 hi2c->XferCount--;
1599 hi2c->XferSize--;
1600 }
1601
1602 /* Wait until STOP flag is set */
1603 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1604 {
1605 /* Disable Address Acknowledge */
1606 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1607 return HAL_ERROR;
1608 }
1609
1610 /* Clear STOP flag */
1611 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1612
1613 /* Wait until BUSY flag is reset */
1614 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1615 {
1616 /* Disable Address Acknowledge */
1617 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1618 return HAL_ERROR;
1619 }
1620
1621 /* Disable Address Acknowledge */
1622 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1623
1624 hi2c->State = HAL_I2C_STATE_READY;
1625 hi2c->Mode = HAL_I2C_MODE_NONE;
1626
1627 /* Process Unlocked */
1628 __HAL_UNLOCK(hi2c);
1629
1630 return HAL_OK;
1631 }
1632 else
1633 {
1634 return HAL_BUSY;
1635 }
1636 }
1637
1638 /**
1639 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1640 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1641 * the configuration information for the specified I2C.
1642 * @param DevAddress Target device address: The device 7 bits address value
1643 * in datasheet must be shifted to the left before calling the interface
1644 * @param pData Pointer to data buffer
1645 * @param Size Amount of data to be sent
1646 * @retval HAL status
1647 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1648 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1649 uint16_t Size)
1650 {
1651 uint32_t xfermode;
1652
1653 if (hi2c->State == HAL_I2C_STATE_READY)
1654 {
1655 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1656 {
1657 return HAL_BUSY;
1658 }
1659
1660 /* Process Locked */
1661 __HAL_LOCK(hi2c);
1662
1663 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1664 hi2c->Mode = HAL_I2C_MODE_MASTER;
1665 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1666
1667 /* Prepare transfer parameters */
1668 hi2c->pBuffPtr = pData;
1669 hi2c->XferCount = Size;
1670 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1671 hi2c->XferISR = I2C_Master_ISR_IT;
1672
1673 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1674 {
1675 hi2c->XferSize = MAX_NBYTE_SIZE;
1676 xfermode = I2C_RELOAD_MODE;
1677 }
1678 else
1679 {
1680 hi2c->XferSize = hi2c->XferCount;
1681 xfermode = I2C_AUTOEND_MODE;
1682 }
1683
1684 /* Send Slave Address */
1685 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1686 /* Check if the Autonomous mode is enabled */
1687 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
1688 {
1689 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE);
1690 }
1691 else
1692 {
1693 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1694 }
1695
1696 /* Process Unlocked */
1697 __HAL_UNLOCK(hi2c);
1698
1699 /* Note : The I2C interrupts must be enabled after unlocking current process
1700 to avoid the risk of I2C interrupt handle execution before current
1701 process unlock */
1702
1703 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1704 /* possible to enable all of these */
1705 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1706 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1707 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1708
1709 return HAL_OK;
1710 }
1711 else
1712 {
1713 return HAL_BUSY;
1714 }
1715 }
1716
1717 /**
1718 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1719 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1720 * the configuration information for the specified I2C.
1721 * @param DevAddress Target device address: The device 7 bits address value
1722 * in datasheet must be shifted to the left before calling the interface
1723 * @param pData Pointer to data buffer
1724 * @param Size Amount of data to be sent
1725 * @retval HAL status
1726 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1727 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1728 uint16_t Size)
1729 {
1730 uint32_t xfermode;
1731
1732 if (hi2c->State == HAL_I2C_STATE_READY)
1733 {
1734 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1735 {
1736 return HAL_BUSY;
1737 }
1738
1739 /* Process Locked */
1740 __HAL_LOCK(hi2c);
1741
1742 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1743 hi2c->Mode = HAL_I2C_MODE_MASTER;
1744 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1745
1746 /* Prepare transfer parameters */
1747 hi2c->pBuffPtr = pData;
1748 hi2c->XferCount = Size;
1749 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1750 hi2c->XferISR = I2C_Master_ISR_IT;
1751
1752 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1753 {
1754 hi2c->XferSize = MAX_NBYTE_SIZE;
1755 xfermode = I2C_RELOAD_MODE;
1756 }
1757 else
1758 {
1759 hi2c->XferSize = hi2c->XferCount;
1760 xfermode = I2C_AUTOEND_MODE;
1761 }
1762
1763 /* Send Slave Address */
1764 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1765 /* Check if the Autonomous mode is enabled */
1766 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
1767 {
1768 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ);
1769 }
1770 else
1771 {
1772 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1773 }
1774
1775 /* Process Unlocked */
1776 __HAL_UNLOCK(hi2c);
1777
1778 /* Note : The I2C interrupts must be enabled after unlocking current process
1779 to avoid the risk of I2C interrupt handle execution before current
1780 process unlock */
1781
1782 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1783 /* possible to enable all of these */
1784 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1785 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1786 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1787
1788 return HAL_OK;
1789 }
1790 else
1791 {
1792 return HAL_BUSY;
1793 }
1794 }
1795
1796 /**
1797 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1798 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1799 * the configuration information for the specified I2C.
1800 * @param pData Pointer to data buffer
1801 * @param Size Amount of data to be sent
1802 * @retval HAL status
1803 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1804 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1805 {
1806 if (hi2c->State == HAL_I2C_STATE_READY)
1807 {
1808 /* Process Locked */
1809 __HAL_LOCK(hi2c);
1810
1811 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1812 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1813 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1814
1815 /* Enable Address Acknowledge */
1816 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1817
1818 /* Prepare transfer parameters */
1819 hi2c->pBuffPtr = pData;
1820 hi2c->XferCount = Size;
1821 hi2c->XferSize = hi2c->XferCount;
1822 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1823 hi2c->XferISR = I2C_Slave_ISR_IT;
1824
1825 /* Preload TX data if no stretch enable */
1826 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
1827 {
1828 /* Preload TX register */
1829 /* Write data to TXDR */
1830 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
1831
1832 /* Increment Buffer pointer */
1833 hi2c->pBuffPtr++;
1834
1835 hi2c->XferCount--;
1836 hi2c->XferSize--;
1837 }
1838
1839 /* Process Unlocked */
1840 __HAL_UNLOCK(hi2c);
1841
1842 /* Note : The I2C interrupts must be enabled after unlocking current process
1843 to avoid the risk of I2C interrupt handle execution before current
1844 process unlock */
1845
1846 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1847 /* possible to enable all of these */
1848 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1849 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1850 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1851
1852 return HAL_OK;
1853 }
1854 else
1855 {
1856 return HAL_BUSY;
1857 }
1858 }
1859
1860 /**
1861 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1862 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1863 * the configuration information for the specified I2C.
1864 * @param pData Pointer to data buffer
1865 * @param Size Amount of data to be sent
1866 * @retval HAL status
1867 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1868 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1869 {
1870 if (hi2c->State == HAL_I2C_STATE_READY)
1871 {
1872 /* Process Locked */
1873 __HAL_LOCK(hi2c);
1874
1875 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1876 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1877 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1878
1879 /* Enable Address Acknowledge */
1880 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1881
1882 /* Prepare transfer parameters */
1883 hi2c->pBuffPtr = pData;
1884 hi2c->XferCount = Size;
1885 hi2c->XferSize = hi2c->XferCount;
1886 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1887 hi2c->XferISR = I2C_Slave_ISR_IT;
1888
1889 /* Process Unlocked */
1890 __HAL_UNLOCK(hi2c);
1891
1892 /* Note : The I2C interrupts must be enabled after unlocking current process
1893 to avoid the risk of I2C interrupt handle execution before current
1894 process unlock */
1895
1896 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1897 /* possible to enable all of these */
1898 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
1899 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1900 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1901
1902 return HAL_OK;
1903 }
1904 else
1905 {
1906 return HAL_BUSY;
1907 }
1908 }
1909
1910 #if defined(HAL_DMA_MODULE_ENABLED)
1911 /**
1912 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1914 * the configuration information for the specified I2C.
1915 * @param DevAddress Target device address: The device 7 bits address value
1916 * in datasheet must be shifted to the left before calling the interface
1917 * @param pData Pointer to data buffer
1918 * @param Size Amount of data to be sent
1919 * @retval HAL status
1920 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1921 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
1922 uint16_t Size)
1923 {
1924 uint32_t xfermode;
1925 HAL_StatusTypeDef dmaxferstatus;
1926
1927 if (hi2c->State == HAL_I2C_STATE_READY)
1928 {
1929 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1930 {
1931 return HAL_BUSY;
1932 }
1933
1934 /* Process Locked */
1935 __HAL_LOCK(hi2c);
1936
1937 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1938 hi2c->Mode = HAL_I2C_MODE_MASTER;
1939 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1940
1941 /* Prepare transfer parameters */
1942 hi2c->pBuffPtr = pData;
1943 hi2c->XferCount = Size;
1944 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1945 hi2c->XferISR = I2C_Master_ISR_DMA;
1946
1947 if (hi2c->XferCount > MAX_NBYTE_SIZE)
1948 {
1949 hi2c->XferSize = MAX_NBYTE_SIZE;
1950 xfermode = I2C_RELOAD_MODE;
1951 }
1952 else
1953 {
1954 hi2c->XferSize = hi2c->XferCount;
1955 xfermode = I2C_AUTOEND_MODE;
1956 }
1957
1958 if (hi2c->XferSize > 0U)
1959 {
1960 if (hi2c->hdmatx != NULL)
1961 {
1962 /* Set the I2C DMA transfer complete callback */
1963 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1964
1965 /* Set the DMA error callback */
1966 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1967
1968 /* Set the unused DMA callbacks to NULL */
1969 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1970 hi2c->hdmatx->XferAbortCallback = NULL;
1971
1972 /* Enable the DMA channel */
1973 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
1974 {
1975 if (hi2c->hdmatx->LinkedListQueue != NULL)
1976 {
1977 /* Set DMA data size */
1978 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
1979
1980 /* Set DMA source address */
1981 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
1982
1983 /* Set DMA destination address */
1984 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
1985 = (uint32_t)&hi2c->Instance->TXDR;
1986
1987 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
1988 }
1989 else
1990 {
1991 /* Update I2C state */
1992 hi2c->State = HAL_I2C_STATE_READY;
1993 hi2c->Mode = HAL_I2C_MODE_NONE;
1994
1995 /* Update I2C error code */
1996 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
1997
1998 /* Process Unlocked */
1999 __HAL_UNLOCK(hi2c);
2000
2001 return HAL_ERROR;
2002 }
2003 }
2004 else
2005 {
2006 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
2007 hi2c->XferSize);
2008 }
2009 }
2010 else
2011 {
2012 /* Update I2C state */
2013 hi2c->State = HAL_I2C_STATE_READY;
2014 hi2c->Mode = HAL_I2C_MODE_NONE;
2015
2016 /* Update I2C error code */
2017 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2018
2019 /* Process Unlocked */
2020 __HAL_UNLOCK(hi2c);
2021
2022 return HAL_ERROR;
2023 }
2024
2025 if (dmaxferstatus == HAL_OK)
2026 {
2027 /* Send Slave Address */
2028 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2029 /* Check if the Autonomous mode is enabled */
2030 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
2031 {
2032 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
2033 I2C_GENERATE_NO_START_WRITE);
2034 }
2035 else
2036 {
2037 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
2038 }
2039
2040 /* Update XferCount value */
2041 hi2c->XferCount -= hi2c->XferSize;
2042
2043 /* Process Unlocked */
2044 __HAL_UNLOCK(hi2c);
2045
2046 /* Note : The I2C interrupts must be enabled after unlocking current process
2047 to avoid the risk of I2C interrupt handle execution before current
2048 process unlock */
2049 /* Enable ERR and NACK interrupts */
2050 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2051
2052 /* Enable DMA Request */
2053 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2054 }
2055 else
2056 {
2057 /* Update I2C state */
2058 hi2c->State = HAL_I2C_STATE_READY;
2059 hi2c->Mode = HAL_I2C_MODE_NONE;
2060
2061 /* Update I2C error code */
2062 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2063
2064 /* Process Unlocked */
2065 __HAL_UNLOCK(hi2c);
2066
2067 return HAL_ERROR;
2068 }
2069 }
2070 else
2071 {
2072 /* Update Transfer ISR function pointer */
2073 hi2c->XferISR = I2C_Master_ISR_IT;
2074
2075 /* Send Slave Address */
2076 /* Set NBYTES to write and generate START condition */
2077 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2078 I2C_GENERATE_START_WRITE);
2079
2080 /* Process Unlocked */
2081 __HAL_UNLOCK(hi2c);
2082
2083 /* Note : The I2C interrupts must be enabled after unlocking current process
2084 to avoid the risk of I2C interrupt handle execution before current
2085 process unlock */
2086 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2087 /* possible to enable all of these */
2088 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2089 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2090 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2091 }
2092
2093 return HAL_OK;
2094 }
2095 else
2096 {
2097 return HAL_BUSY;
2098 }
2099 }
2100
2101 /**
2102 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2103 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2104 * the configuration information for the specified I2C.
2105 * @param DevAddress Target device address: The device 7 bits address value
2106 * in datasheet must be shifted to the left before calling the interface
2107 * @param pData Pointer to data buffer
2108 * @param Size Amount of data to be sent
2109 * @retval HAL status
2110 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2111 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
2112 uint16_t Size)
2113 {
2114 uint32_t xfermode;
2115 HAL_StatusTypeDef dmaxferstatus;
2116
2117 if (hi2c->State == HAL_I2C_STATE_READY)
2118 {
2119 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2120 {
2121 return HAL_BUSY;
2122 }
2123
2124 /* Process Locked */
2125 __HAL_LOCK(hi2c);
2126
2127 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2128 hi2c->Mode = HAL_I2C_MODE_MASTER;
2129 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2130
2131 /* Prepare transfer parameters */
2132 hi2c->pBuffPtr = pData;
2133 hi2c->XferCount = Size;
2134 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2135 hi2c->XferISR = I2C_Master_ISR_DMA;
2136
2137 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2138 {
2139 hi2c->XferSize = MAX_NBYTE_SIZE;
2140 xfermode = I2C_RELOAD_MODE;
2141 }
2142 else
2143 {
2144 hi2c->XferSize = hi2c->XferCount;
2145 xfermode = I2C_AUTOEND_MODE;
2146 }
2147
2148 if (hi2c->XferSize > 0U)
2149 {
2150 if (hi2c->hdmarx != NULL)
2151 {
2152 /* Set the I2C DMA transfer complete callback */
2153 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2154
2155 /* Set the DMA error callback */
2156 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2157
2158 /* Set the unused DMA callbacks to NULL */
2159 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2160 hi2c->hdmarx->XferAbortCallback = NULL;
2161
2162 /* Enable the DMA channel */
2163 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2164 {
2165 if (hi2c->hdmarx->LinkedListQueue != NULL)
2166 {
2167 /* Set DMA data size */
2168 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2169
2170 /* Set DMA source address */
2171 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2172 = (uint32_t)&hi2c->Instance->RXDR;
2173
2174 /* Set DMA destination address */
2175 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2176
2177 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2178 }
2179 else
2180 {
2181 /* Update I2C state */
2182 hi2c->State = HAL_I2C_STATE_READY;
2183 hi2c->Mode = HAL_I2C_MODE_NONE;
2184
2185 /* Update I2C error code */
2186 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2187
2188 /* Process Unlocked */
2189 __HAL_UNLOCK(hi2c);
2190
2191 return HAL_ERROR;
2192 }
2193 }
2194 else
2195 {
2196 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2197 hi2c->XferSize);
2198 }
2199 }
2200 else
2201 {
2202 /* Update I2C state */
2203 hi2c->State = HAL_I2C_STATE_READY;
2204 hi2c->Mode = HAL_I2C_MODE_NONE;
2205
2206 /* Update I2C error code */
2207 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2208
2209 /* Process Unlocked */
2210 __HAL_UNLOCK(hi2c);
2211
2212 return HAL_ERROR;
2213 }
2214
2215 if (dmaxferstatus == HAL_OK)
2216 {
2217 /* Send Slave Address */
2218 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2219 /* Check if the Autonomous mode is enabled */
2220 if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN)
2221 {
2222 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
2223 I2C_GENERATE_NO_START_READ);
2224 }
2225 else
2226 {
2227 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2228 }
2229
2230 /* Update XferCount value */
2231 hi2c->XferCount -= hi2c->XferSize;
2232
2233 /* Process Unlocked */
2234 __HAL_UNLOCK(hi2c);
2235
2236 /* Note : The I2C interrupts must be enabled after unlocking current process
2237 to avoid the risk of I2C interrupt handle execution before current
2238 process unlock */
2239 /* Enable ERR and NACK interrupts */
2240 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2241
2242 /* Enable DMA Request */
2243 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2244 }
2245 else
2246 {
2247 /* Update I2C state */
2248 hi2c->State = HAL_I2C_STATE_READY;
2249 hi2c->Mode = HAL_I2C_MODE_NONE;
2250
2251 /* Update I2C error code */
2252 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2253
2254 /* Process Unlocked */
2255 __HAL_UNLOCK(hi2c);
2256
2257 return HAL_ERROR;
2258 }
2259 }
2260 else
2261 {
2262 /* Update Transfer ISR function pointer */
2263 hi2c->XferISR = I2C_Master_ISR_IT;
2264
2265 /* Send Slave Address */
2266 /* Set NBYTES to read and generate START condition */
2267 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2268 I2C_GENERATE_START_READ);
2269
2270 /* Process Unlocked */
2271 __HAL_UNLOCK(hi2c);
2272
2273 /* Note : The I2C interrupts must be enabled after unlocking current process
2274 to avoid the risk of I2C interrupt handle execution before current
2275 process unlock */
2276 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2277 /* possible to enable all of these */
2278 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2279 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2280 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2281 }
2282
2283 return HAL_OK;
2284 }
2285 else
2286 {
2287 return HAL_BUSY;
2288 }
2289 }
2290
2291 /**
2292 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2293 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2294 * the configuration information for the specified I2C.
2295 * @param pData Pointer to data buffer
2296 * @param Size Amount of data to be sent
2297 * @retval HAL status
2298 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2299 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2300 {
2301 HAL_StatusTypeDef dmaxferstatus;
2302
2303 if (hi2c->State == HAL_I2C_STATE_READY)
2304 {
2305 if ((pData == NULL) || (Size == 0U))
2306 {
2307 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2308 return HAL_ERROR;
2309 }
2310 /* Process Locked */
2311 __HAL_LOCK(hi2c);
2312
2313 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2314 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2315 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2316
2317 /* Prepare transfer parameters */
2318 hi2c->pBuffPtr = pData;
2319 hi2c->XferCount = Size;
2320 hi2c->XferSize = hi2c->XferCount;
2321 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2322 hi2c->XferISR = I2C_Slave_ISR_DMA;
2323
2324 /* Preload TX data if no stretch enable */
2325 if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
2326 {
2327 /* Preload TX register */
2328 /* Write data to TXDR */
2329 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2330
2331 /* Increment Buffer pointer */
2332 hi2c->pBuffPtr++;
2333
2334 hi2c->XferCount--;
2335 hi2c->XferSize--;
2336 }
2337
2338 if (hi2c->XferCount != 0U)
2339 {
2340 if (hi2c->hdmatx != NULL)
2341 {
2342 /* Set the I2C DMA transfer complete callback */
2343 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
2344
2345 /* Set the DMA error callback */
2346 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2347
2348 /* Set the unused DMA callbacks to NULL */
2349 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2350 hi2c->hdmatx->XferAbortCallback = NULL;
2351
2352 /* Enable the DMA channel */
2353 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2354 {
2355 if (hi2c->hdmatx->LinkedListQueue != NULL)
2356 {
2357 /* Set DMA data size */
2358 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2359
2360 /* Set DMA source address */
2361 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
2362
2363 /* Set DMA destination address */
2364 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
2365 = (uint32_t)&hi2c->Instance->TXDR;
2366
2367 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
2368 }
2369 else
2370 {
2371 /* Update I2C state */
2372 hi2c->State = HAL_I2C_STATE_LISTEN;
2373 hi2c->Mode = HAL_I2C_MODE_NONE;
2374
2375 /* Update I2C error code */
2376 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2377
2378 /* Process Unlocked */
2379 __HAL_UNLOCK(hi2c);
2380
2381 return HAL_ERROR;
2382 }
2383 }
2384 else
2385 {
2386 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
2387 (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
2388 hi2c->XferSize);
2389 }
2390 }
2391 else
2392 {
2393 /* Update I2C state */
2394 hi2c->State = HAL_I2C_STATE_LISTEN;
2395 hi2c->Mode = HAL_I2C_MODE_NONE;
2396
2397 /* Update I2C error code */
2398 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2399
2400 /* Process Unlocked */
2401 __HAL_UNLOCK(hi2c);
2402
2403 return HAL_ERROR;
2404 }
2405
2406 if (dmaxferstatus == HAL_OK)
2407 {
2408 /* Enable Address Acknowledge */
2409 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2410
2411 /* Process Unlocked */
2412 __HAL_UNLOCK(hi2c);
2413
2414 /* Note : The I2C interrupts must be enabled after unlocking current process
2415 to avoid the risk of I2C interrupt handle execution before current
2416 process unlock */
2417 /* Enable ERR, STOP, NACK, ADDR interrupts */
2418 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2419
2420 /* Enable DMA Request */
2421 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2422 }
2423 else
2424 {
2425 /* Update I2C state */
2426 hi2c->State = HAL_I2C_STATE_LISTEN;
2427 hi2c->Mode = HAL_I2C_MODE_NONE;
2428
2429 /* Update I2C error code */
2430 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2431
2432 /* Process Unlocked */
2433 __HAL_UNLOCK(hi2c);
2434
2435 return HAL_ERROR;
2436 }
2437 }
2438 else
2439 {
2440 /* Enable Address Acknowledge */
2441 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2442
2443 /* Process Unlocked */
2444 __HAL_UNLOCK(hi2c);
2445
2446 /* Note : The I2C interrupts must be enabled after unlocking current process
2447 to avoid the risk of I2C interrupt handle execution before current
2448 process unlock */
2449 /* Enable ERR, STOP, NACK, ADDR interrupts */
2450 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2451 }
2452
2453 return HAL_OK;
2454 }
2455 else
2456 {
2457 return HAL_BUSY;
2458 }
2459 }
2460
2461 /**
2462 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2463 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2464 * the configuration information for the specified I2C.
2465 * @param pData Pointer to data buffer
2466 * @param Size Amount of data to be sent
2467 * @retval HAL status
2468 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2469 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2470 {
2471 HAL_StatusTypeDef dmaxferstatus;
2472
2473 if (hi2c->State == HAL_I2C_STATE_READY)
2474 {
2475 if ((pData == NULL) || (Size == 0U))
2476 {
2477 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2478 return HAL_ERROR;
2479 }
2480 /* Process Locked */
2481 __HAL_LOCK(hi2c);
2482
2483 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2484 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2485 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2486
2487 /* Prepare transfer parameters */
2488 hi2c->pBuffPtr = pData;
2489 hi2c->XferCount = Size;
2490 hi2c->XferSize = hi2c->XferCount;
2491 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2492 hi2c->XferISR = I2C_Slave_ISR_DMA;
2493
2494 if (hi2c->hdmarx != NULL)
2495 {
2496 /* Set the I2C DMA transfer complete callback */
2497 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
2498
2499 /* Set the DMA error callback */
2500 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2501
2502 /* Set the unused DMA callbacks to NULL */
2503 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2504 hi2c->hdmarx->XferAbortCallback = NULL;
2505
2506 /* Enable the DMA channel */
2507 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
2508 {
2509 if (hi2c->hdmarx->LinkedListQueue != NULL)
2510 {
2511 /* Set DMA data size */
2512 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
2513
2514 /* Set DMA source address */
2515 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
2516 = (uint32_t)&hi2c->Instance->RXDR;
2517
2518 /* Set DMA destination address */
2519 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
2520
2521 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
2522 }
2523 else
2524 {
2525 /* Update I2C state */
2526 hi2c->State = HAL_I2C_STATE_LISTEN;
2527 hi2c->Mode = HAL_I2C_MODE_NONE;
2528
2529 /* Update I2C error code */
2530 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2531
2532 /* Process Unlocked */
2533 __HAL_UNLOCK(hi2c);
2534
2535 return HAL_ERROR;
2536 }
2537 }
2538 else
2539 {
2540 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
2541 hi2c->XferSize);
2542 }
2543 }
2544 else
2545 {
2546 /* Update I2C state */
2547 hi2c->State = HAL_I2C_STATE_LISTEN;
2548 hi2c->Mode = HAL_I2C_MODE_NONE;
2549
2550 /* Update I2C error code */
2551 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2552
2553 /* Process Unlocked */
2554 __HAL_UNLOCK(hi2c);
2555
2556 return HAL_ERROR;
2557 }
2558
2559 if (dmaxferstatus == HAL_OK)
2560 {
2561 /* Enable Address Acknowledge */
2562 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2563
2564 /* Process Unlocked */
2565 __HAL_UNLOCK(hi2c);
2566
2567 /* Note : The I2C interrupts must be enabled after unlocking current process
2568 to avoid the risk of I2C interrupt handle execution before current
2569 process unlock */
2570 /* Enable ERR, STOP, NACK, ADDR interrupts */
2571 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2572
2573 /* Enable DMA Request */
2574 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2575 }
2576 else
2577 {
2578 /* Update I2C state */
2579 hi2c->State = HAL_I2C_STATE_LISTEN;
2580 hi2c->Mode = HAL_I2C_MODE_NONE;
2581
2582 /* Update I2C error code */
2583 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2584
2585 /* Process Unlocked */
2586 __HAL_UNLOCK(hi2c);
2587
2588 return HAL_ERROR;
2589 }
2590
2591 return HAL_OK;
2592 }
2593 else
2594 {
2595 return HAL_BUSY;
2596 }
2597 }
2598 #endif /* HAL_DMA_MODULE_ENABLED */
2599
2600 /**
2601 * @brief Write an amount of data in blocking mode to a specific memory address
2602 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2603 * the configuration information for the specified I2C.
2604 * @param DevAddress Target device address: The device 7 bits address value
2605 * in datasheet must be shifted to the left before calling the interface
2606 * @param MemAddress Internal memory address
2607 * @param MemAddSize Size of internal memory address
2608 * @param pData Pointer to data buffer
2609 * @param Size Amount of data to be sent
2610 * @param Timeout Timeout duration
2611 * @retval HAL status
2612 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2613 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2614 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2615 {
2616 uint32_t tickstart;
2617
2618 /* Check the parameters */
2619 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2620
2621 if (hi2c->State == HAL_I2C_STATE_READY)
2622 {
2623 if ((pData == NULL) || (Size == 0U))
2624 {
2625 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2626 return HAL_ERROR;
2627 }
2628
2629 /* Process Locked */
2630 __HAL_LOCK(hi2c);
2631
2632 /* Init tickstart for timeout management*/
2633 tickstart = HAL_GetTick();
2634
2635 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2636 {
2637 return HAL_ERROR;
2638 }
2639
2640 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2641 hi2c->Mode = HAL_I2C_MODE_MEM;
2642 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2643
2644 /* Prepare transfer parameters */
2645 hi2c->pBuffPtr = pData;
2646 hi2c->XferCount = Size;
2647 hi2c->XferISR = NULL;
2648
2649 /* Send Slave Address and Memory Address */
2650 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2651 {
2652 /* Process Unlocked */
2653 __HAL_UNLOCK(hi2c);
2654 return HAL_ERROR;
2655 }
2656
2657 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
2658 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2659 {
2660 hi2c->XferSize = MAX_NBYTE_SIZE;
2661 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
2662 }
2663 else
2664 {
2665 hi2c->XferSize = hi2c->XferCount;
2666 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
2667 }
2668
2669 do
2670 {
2671 /* Wait until TXIS flag is set */
2672 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2673 {
2674 return HAL_ERROR;
2675 }
2676
2677 /* Write data to TXDR */
2678 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
2679
2680 /* Increment Buffer pointer */
2681 hi2c->pBuffPtr++;
2682
2683 hi2c->XferCount--;
2684 hi2c->XferSize--;
2685
2686 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2687 {
2688 /* Wait until TCR flag is set */
2689 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2690 {
2691 return HAL_ERROR;
2692 }
2693
2694 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2695 {
2696 hi2c->XferSize = MAX_NBYTE_SIZE;
2697 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2698 I2C_NO_STARTSTOP);
2699 }
2700 else
2701 {
2702 hi2c->XferSize = hi2c->XferCount;
2703 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2704 I2C_NO_STARTSTOP);
2705 }
2706 }
2707
2708 } while (hi2c->XferCount > 0U);
2709
2710 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2711 /* Wait until STOPF flag is reset */
2712 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2713 {
2714 return HAL_ERROR;
2715 }
2716
2717 /* Clear STOP Flag */
2718 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2719
2720 /* Clear Configuration Register 2 */
2721 I2C_RESET_CR2(hi2c);
2722
2723 hi2c->State = HAL_I2C_STATE_READY;
2724 hi2c->Mode = HAL_I2C_MODE_NONE;
2725
2726 /* Process Unlocked */
2727 __HAL_UNLOCK(hi2c);
2728
2729 return HAL_OK;
2730 }
2731 else
2732 {
2733 return HAL_BUSY;
2734 }
2735 }
2736
2737 /**
2738 * @brief Read an amount of data in blocking mode from a specific memory address
2739 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2740 * the configuration information for the specified I2C.
2741 * @param DevAddress Target device address: The device 7 bits address value
2742 * in datasheet must be shifted to the left before calling the interface
2743 * @param MemAddress Internal memory address
2744 * @param MemAddSize Size of internal memory address
2745 * @param pData Pointer to data buffer
2746 * @param Size Amount of data to be sent
2747 * @param Timeout Timeout duration
2748 * @retval HAL status
2749 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2750 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2751 uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2752 {
2753 uint32_t tickstart;
2754
2755 /* Check the parameters */
2756 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2757
2758 if (hi2c->State == HAL_I2C_STATE_READY)
2759 {
2760 if ((pData == NULL) || (Size == 0U))
2761 {
2762 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2763 return HAL_ERROR;
2764 }
2765
2766 /* Process Locked */
2767 __HAL_LOCK(hi2c);
2768
2769 /* Init tickstart for timeout management*/
2770 tickstart = HAL_GetTick();
2771
2772 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
2773 {
2774 return HAL_ERROR;
2775 }
2776
2777 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2778 hi2c->Mode = HAL_I2C_MODE_MEM;
2779 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2780
2781 /* Prepare transfer parameters */
2782 hi2c->pBuffPtr = pData;
2783 hi2c->XferCount = Size;
2784 hi2c->XferISR = NULL;
2785
2786 /* Send Slave Address and Memory Address */
2787 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2788 {
2789 /* Process Unlocked */
2790 __HAL_UNLOCK(hi2c);
2791 return HAL_ERROR;
2792 }
2793
2794 /* Send Slave Address */
2795 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2796 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2797 {
2798 hi2c->XferSize = MAX_NBYTE_SIZE;
2799 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
2800 I2C_GENERATE_START_READ);
2801 }
2802 else
2803 {
2804 hi2c->XferSize = hi2c->XferCount;
2805 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2806 I2C_GENERATE_START_READ);
2807 }
2808
2809 do
2810 {
2811 /* Wait until RXNE flag is set */
2812 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
2813 {
2814 return HAL_ERROR;
2815 }
2816
2817 /* Read data from RXDR */
2818 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
2819
2820 /* Increment Buffer pointer */
2821 hi2c->pBuffPtr++;
2822
2823 hi2c->XferSize--;
2824 hi2c->XferCount--;
2825
2826 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
2827 {
2828 /* Wait until TCR flag is set */
2829 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
2830 {
2831 return HAL_ERROR;
2832 }
2833
2834 if (hi2c->XferCount > MAX_NBYTE_SIZE)
2835 {
2836 hi2c->XferSize = MAX_NBYTE_SIZE;
2837 I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
2838 I2C_NO_STARTSTOP);
2839 }
2840 else
2841 {
2842 hi2c->XferSize = hi2c->XferCount;
2843 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
2844 I2C_NO_STARTSTOP);
2845 }
2846 }
2847 } while (hi2c->XferCount > 0U);
2848
2849 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2850 /* Wait until STOPF flag is reset */
2851 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2852 {
2853 return HAL_ERROR;
2854 }
2855
2856 /* Clear STOP Flag */
2857 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2858
2859 /* Clear Configuration Register 2 */
2860 I2C_RESET_CR2(hi2c);
2861
2862 hi2c->State = HAL_I2C_STATE_READY;
2863 hi2c->Mode = HAL_I2C_MODE_NONE;
2864
2865 /* Process Unlocked */
2866 __HAL_UNLOCK(hi2c);
2867
2868 return HAL_OK;
2869 }
2870 else
2871 {
2872 return HAL_BUSY;
2873 }
2874 }
2875 /**
2876 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2877 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2878 * the configuration information for the specified I2C.
2879 * @param DevAddress Target device address: The device 7 bits address value
2880 * in datasheet must be shifted to the left before calling the interface
2881 * @param MemAddress Internal memory address
2882 * @param MemAddSize Size of internal memory address
2883 * @param pData Pointer to data buffer
2884 * @param Size Amount of data to be sent
2885 * @retval HAL status
2886 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2887 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2888 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2889 {
2890 /* Check the parameters */
2891 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2892
2893 if (hi2c->State == HAL_I2C_STATE_READY)
2894 {
2895 if ((pData == NULL) || (Size == 0U))
2896 {
2897 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2898 return HAL_ERROR;
2899 }
2900
2901 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2902 {
2903 return HAL_BUSY;
2904 }
2905
2906 /* Process Locked */
2907 __HAL_LOCK(hi2c);
2908
2909 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2910 hi2c->Mode = HAL_I2C_MODE_MEM;
2911 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2912
2913 /* Prepare transfer parameters */
2914 hi2c->pBuffPtr = pData;
2915 hi2c->XferCount = Size;
2916 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2917 hi2c->XferISR = I2C_Mem_ISR_IT;
2918 hi2c->Devaddress = DevAddress;
2919
2920 /* If Memory address size is 8Bit */
2921 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
2922 {
2923 /* Prefetch Memory Address */
2924 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
2925
2926 /* Reset Memaddress content */
2927 hi2c->Memaddress = 0xFFFFFFFFU;
2928 }
2929 /* If Memory address size is 16Bit */
2930 else
2931 {
2932 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
2933 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
2934
2935 /* Prepare Memaddress buffer for LSB part */
2936 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
2937 }
2938 /* Send Slave Address and Memory Address */
2939 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
2940
2941 /* Process Unlocked */
2942 __HAL_UNLOCK(hi2c);
2943
2944 /* Note : The I2C interrupts must be enabled after unlocking current process
2945 to avoid the risk of I2C interrupt handle execution before current
2946 process unlock */
2947
2948 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2949 /* possible to enable all of these */
2950 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
2951 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2952 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2953
2954 return HAL_OK;
2955 }
2956 else
2957 {
2958 return HAL_BUSY;
2959 }
2960 }
2961
2962 /**
2963 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2964 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2965 * the configuration information for the specified I2C.
2966 * @param DevAddress Target device address: The device 7 bits address value
2967 * in datasheet must be shifted to the left before calling the interface
2968 * @param MemAddress Internal memory address
2969 * @param MemAddSize Size of internal memory address
2970 * @param pData Pointer to data buffer
2971 * @param Size Amount of data to be sent
2972 * @retval HAL status
2973 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2974 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
2975 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2976 {
2977 /* Check the parameters */
2978 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2979
2980 if (hi2c->State == HAL_I2C_STATE_READY)
2981 {
2982 if ((pData == NULL) || (Size == 0U))
2983 {
2984 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
2985 return HAL_ERROR;
2986 }
2987
2988 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2989 {
2990 return HAL_BUSY;
2991 }
2992
2993 /* Process Locked */
2994 __HAL_LOCK(hi2c);
2995
2996 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2997 hi2c->Mode = HAL_I2C_MODE_MEM;
2998 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2999
3000 /* Prepare transfer parameters */
3001 hi2c->pBuffPtr = pData;
3002 hi2c->XferCount = Size;
3003 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3004 hi2c->XferISR = I2C_Mem_ISR_IT;
3005 hi2c->Devaddress = DevAddress;
3006
3007 /* If Memory address size is 8Bit */
3008 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3009 {
3010 /* Prefetch Memory Address */
3011 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3012
3013 /* Reset Memaddress content */
3014 hi2c->Memaddress = 0xFFFFFFFFU;
3015 }
3016 /* If Memory address size is 16Bit */
3017 else
3018 {
3019 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3020 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3021
3022 /* Prepare Memaddress buffer for LSB part */
3023 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3024 }
3025 /* Send Slave Address and Memory Address */
3026 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3027
3028 /* Process Unlocked */
3029 __HAL_UNLOCK(hi2c);
3030
3031 /* Note : The I2C interrupts must be enabled after unlocking current process
3032 to avoid the risk of I2C interrupt handle execution before current
3033 process unlock */
3034
3035 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3036 /* possible to enable all of these */
3037 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3038 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3039 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3040
3041 return HAL_OK;
3042 }
3043 else
3044 {
3045 return HAL_BUSY;
3046 }
3047 }
3048
3049 #if defined(HAL_DMA_MODULE_ENABLED)
3050 /**
3051 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3052 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3053 * the configuration information for the specified I2C.
3054 * @param DevAddress Target device address: The device 7 bits address value
3055 * in datasheet must be shifted to the left before calling the interface
3056 * @param MemAddress Internal memory address
3057 * @param MemAddSize Size of internal memory address
3058 * @param pData Pointer to data buffer
3059 * @param Size Amount of data to be sent
3060 * @retval HAL status
3061 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3062 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3063 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3064 {
3065 HAL_StatusTypeDef dmaxferstatus;
3066
3067 /* Check the parameters */
3068 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3069
3070 if (hi2c->State == HAL_I2C_STATE_READY)
3071 {
3072 if ((pData == NULL) || (Size == 0U))
3073 {
3074 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3075 return HAL_ERROR;
3076 }
3077
3078 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3079 {
3080 return HAL_BUSY;
3081 }
3082
3083 /* Process Locked */
3084 __HAL_LOCK(hi2c);
3085
3086 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3087 hi2c->Mode = HAL_I2C_MODE_MEM;
3088 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3089
3090 /* Prepare transfer parameters */
3091 hi2c->pBuffPtr = pData;
3092 hi2c->XferCount = Size;
3093 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3094 hi2c->XferISR = I2C_Mem_ISR_DMA;
3095 hi2c->Devaddress = DevAddress;
3096
3097 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3098 {
3099 hi2c->XferSize = MAX_NBYTE_SIZE;
3100 }
3101 else
3102 {
3103 hi2c->XferSize = hi2c->XferCount;
3104 }
3105
3106 /* If Memory address size is 8Bit */
3107 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3108 {
3109 /* Prefetch Memory Address */
3110 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3111
3112 /* Reset Memaddress content */
3113 hi2c->Memaddress = 0xFFFFFFFFU;
3114 }
3115 /* If Memory address size is 16Bit */
3116 else
3117 {
3118 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3119 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3120
3121 /* Prepare Memaddress buffer for LSB part */
3122 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3123 }
3124
3125 if (hi2c->hdmatx != NULL)
3126 {
3127 /* Set the I2C DMA transfer complete callback */
3128 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3129
3130 /* Set the DMA error callback */
3131 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3132
3133 /* Set the unused DMA callbacks to NULL */
3134 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3135 hi2c->hdmatx->XferAbortCallback = NULL;
3136
3137 /* Enable the DMA channel */
3138 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3139 {
3140 if (hi2c->hdmatx->LinkedListQueue != NULL)
3141 {
3142 /* Set DMA data size */
3143 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3144
3145 /* Set DMA source address */
3146 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3147
3148 /* Set DMA destination address */
3149 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3150 = (uint32_t)&hi2c->Instance->TXDR;
3151
3152 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3153 }
3154 else
3155 {
3156 /* Update I2C state */
3157 hi2c->State = HAL_I2C_STATE_READY;
3158 hi2c->Mode = HAL_I2C_MODE_NONE;
3159
3160 /* Update I2C error code */
3161 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3162
3163 /* Process Unlocked */
3164 __HAL_UNLOCK(hi2c);
3165
3166 return HAL_ERROR;
3167 }
3168 }
3169 else
3170 {
3171 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3172 hi2c->XferSize);
3173 }
3174 }
3175 else
3176 {
3177 /* Update I2C state */
3178 hi2c->State = HAL_I2C_STATE_READY;
3179 hi2c->Mode = HAL_I2C_MODE_NONE;
3180
3181 /* Update I2C error code */
3182 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3183
3184 /* Process Unlocked */
3185 __HAL_UNLOCK(hi2c);
3186
3187 return HAL_ERROR;
3188 }
3189
3190 if (dmaxferstatus == HAL_OK)
3191 {
3192 /* Send Slave Address and Memory Address */
3193 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3194
3195 /* Process Unlocked */
3196 __HAL_UNLOCK(hi2c);
3197
3198 /* Note : The I2C interrupts must be enabled after unlocking current process
3199 to avoid the risk of I2C interrupt handle execution before current
3200 process unlock */
3201 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3202 /* possible to enable all of these */
3203 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3204 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3205 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3206 }
3207 else
3208 {
3209 /* Update I2C state */
3210 hi2c->State = HAL_I2C_STATE_READY;
3211 hi2c->Mode = HAL_I2C_MODE_NONE;
3212
3213 /* Update I2C error code */
3214 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3215
3216 /* Process Unlocked */
3217 __HAL_UNLOCK(hi2c);
3218
3219 return HAL_ERROR;
3220 }
3221
3222 return HAL_OK;
3223 }
3224 else
3225 {
3226 return HAL_BUSY;
3227 }
3228 }
3229
3230 /**
3231 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3232 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3233 * the configuration information for the specified I2C.
3234 * @param DevAddress Target device address: The device 7 bits address value
3235 * in datasheet must be shifted to the left before calling the interface
3236 * @param MemAddress Internal memory address
3237 * @param MemAddSize Size of internal memory address
3238 * @param pData Pointer to data buffer
3239 * @param Size Amount of data to be read
3240 * @retval HAL status
3241 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3242 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
3243 uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3244 {
3245 HAL_StatusTypeDef dmaxferstatus;
3246
3247 /* Check the parameters */
3248 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3249
3250 if (hi2c->State == HAL_I2C_STATE_READY)
3251 {
3252 if ((pData == NULL) || (Size == 0U))
3253 {
3254 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
3255 return HAL_ERROR;
3256 }
3257
3258 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3259 {
3260 return HAL_BUSY;
3261 }
3262
3263 /* Process Locked */
3264 __HAL_LOCK(hi2c);
3265
3266 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3267 hi2c->Mode = HAL_I2C_MODE_MEM;
3268 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3269
3270 /* Prepare transfer parameters */
3271 hi2c->pBuffPtr = pData;
3272 hi2c->XferCount = Size;
3273 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3274 hi2c->XferISR = I2C_Mem_ISR_DMA;
3275 hi2c->Devaddress = DevAddress;
3276
3277 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3278 {
3279 hi2c->XferSize = MAX_NBYTE_SIZE;
3280 }
3281 else
3282 {
3283 hi2c->XferSize = hi2c->XferCount;
3284 }
3285
3286 /* If Memory address size is 8Bit */
3287 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
3288 {
3289 /* Prefetch Memory Address */
3290 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3291
3292 /* Reset Memaddress content */
3293 hi2c->Memaddress = 0xFFFFFFFFU;
3294 }
3295 /* If Memory address size is 16Bit */
3296 else
3297 {
3298 /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
3299 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3300
3301 /* Prepare Memaddress buffer for LSB part */
3302 hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
3303 }
3304
3305 if (hi2c->hdmarx != NULL)
3306 {
3307 /* Set the I2C DMA transfer complete callback */
3308 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
3309
3310 /* Set the DMA error callback */
3311 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3312
3313 /* Set the unused DMA callbacks to NULL */
3314 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3315 hi2c->hdmarx->XferAbortCallback = NULL;
3316
3317 /* Enable the DMA channel */
3318 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3319 {
3320 if (hi2c->hdmarx->LinkedListQueue != NULL)
3321 {
3322 /* Set DMA data size */
3323 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3324
3325 /* Set DMA source address */
3326 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
3327 = (uint32_t)&hi2c->Instance->RXDR;
3328
3329 /* Set DMA destination address */
3330 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
3331
3332 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
3333 }
3334 else
3335 {
3336 /* Update I2C state */
3337 hi2c->State = HAL_I2C_STATE_READY;
3338 hi2c->Mode = HAL_I2C_MODE_NONE;
3339
3340 /* Update I2C error code */
3341 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3342
3343 /* Process Unlocked */
3344 __HAL_UNLOCK(hi2c);
3345
3346 return HAL_ERROR;
3347 }
3348 }
3349 else
3350 {
3351 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
3352 hi2c->XferSize);
3353 }
3354 }
3355 else
3356 {
3357 /* Update I2C state */
3358 hi2c->State = HAL_I2C_STATE_READY;
3359 hi2c->Mode = HAL_I2C_MODE_NONE;
3360
3361 /* Update I2C error code */
3362 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3363
3364 /* Process Unlocked */
3365 __HAL_UNLOCK(hi2c);
3366
3367 return HAL_ERROR;
3368 }
3369
3370 if (dmaxferstatus == HAL_OK)
3371 {
3372 /* Send Slave Address and Memory Address */
3373 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3374
3375 /* Process Unlocked */
3376 __HAL_UNLOCK(hi2c);
3377
3378 /* Note : The I2C interrupts must be enabled after unlocking current process
3379 to avoid the risk of I2C interrupt handle execution before current
3380 process unlock */
3381 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3382 /* possible to enable all of these */
3383 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3384 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3385 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3386 }
3387 else
3388 {
3389 /* Update I2C state */
3390 hi2c->State = HAL_I2C_STATE_READY;
3391 hi2c->Mode = HAL_I2C_MODE_NONE;
3392
3393 /* Update I2C error code */
3394 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3395
3396 /* Process Unlocked */
3397 __HAL_UNLOCK(hi2c);
3398
3399 return HAL_ERROR;
3400 }
3401
3402 return HAL_OK;
3403 }
3404 else
3405 {
3406 return HAL_BUSY;
3407 }
3408 }
3409 #endif /* HAL_DMA_MODULE_ENABLED */
3410
3411 /**
3412 * @brief Checks if target device is ready for communication.
3413 * @note This function is used with Memory devices
3414 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3415 * the configuration information for the specified I2C.
3416 * @param DevAddress Target device address: The device 7 bits address value
3417 * in datasheet must be shifted to the left before calling the interface
3418 * @param Trials Number of trials
3419 * @param Timeout Timeout duration
3420 * @retval HAL status
3421 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3422 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
3423 uint32_t Timeout)
3424 {
3425 uint32_t tickstart;
3426
3427 __IO uint32_t I2C_Trials = 0UL;
3428
3429 FlagStatus tmp1;
3430 FlagStatus tmp2;
3431
3432 if (hi2c->State == HAL_I2C_STATE_READY)
3433 {
3434 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
3435 {
3436 return HAL_BUSY;
3437 }
3438
3439 /* Process Locked */
3440 __HAL_LOCK(hi2c);
3441
3442 hi2c->State = HAL_I2C_STATE_BUSY;
3443 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3444
3445 do
3446 {
3447 /* Generate Start */
3448 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
3449
3450 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
3451 /* Wait until STOPF flag is set or a NACK flag is set*/
3452 tickstart = HAL_GetTick();
3453
3454 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3455 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3456
3457 while ((tmp1 == RESET) && (tmp2 == RESET))
3458 {
3459 if (Timeout != HAL_MAX_DELAY)
3460 {
3461 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3462 {
3463 /* Update I2C state */
3464 hi2c->State = HAL_I2C_STATE_READY;
3465
3466 /* Update I2C error code */
3467 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3468
3469 /* Process Unlocked */
3470 __HAL_UNLOCK(hi2c);
3471
3472 return HAL_ERROR;
3473 }
3474 }
3475
3476 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF);
3477 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3478 }
3479
3480 /* Check if the NACKF flag has not been set */
3481 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
3482 {
3483 /* Wait until STOPF flag is reset */
3484 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3485 {
3486 return HAL_ERROR;
3487 }
3488
3489 /* Clear STOP Flag */
3490 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3491
3492 /* Device is ready */
3493 hi2c->State = HAL_I2C_STATE_READY;
3494
3495 /* Process Unlocked */
3496 __HAL_UNLOCK(hi2c);
3497
3498 return HAL_OK;
3499 }
3500 else
3501 {
3502 /* Wait until STOPF flag is reset */
3503 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3504 {
3505 return HAL_ERROR;
3506 }
3507
3508 /* Clear NACK Flag */
3509 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3510
3511 /* Clear STOP Flag, auto generated with autoend*/
3512 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3513 }
3514
3515 /* Check if the maximum allowed number of trials has been reached */
3516 if (I2C_Trials == Trials)
3517 {
3518 /* Generate Stop */
3519 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3520
3521 /* Wait until STOPF flag is reset */
3522 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
3523 {
3524 return HAL_ERROR;
3525 }
3526
3527 /* Clear STOP Flag */
3528 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3529 }
3530
3531 /* Increment Trials */
3532 I2C_Trials++;
3533 } while (I2C_Trials < Trials);
3534
3535 /* Update I2C state */
3536 hi2c->State = HAL_I2C_STATE_READY;
3537
3538 /* Update I2C error code */
3539 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3540
3541 /* Process Unlocked */
3542 __HAL_UNLOCK(hi2c);
3543
3544 return HAL_ERROR;
3545 }
3546 else
3547 {
3548 return HAL_BUSY;
3549 }
3550 }
3551
3552 /**
3553 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3554 * @note This interface allow to manage repeated start condition when a direction change during transfer
3555 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3556 * the configuration information for the specified I2C.
3557 * @param DevAddress Target device address: The device 7 bits address value
3558 * in datasheet must be shifted to the left before calling the interface
3559 * @param pData Pointer to data buffer
3560 * @param Size Amount of data to be sent
3561 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3562 * @retval HAL status
3563 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3564 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3565 uint16_t Size, uint32_t XferOptions)
3566 {
3567 uint32_t xfermode;
3568 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3569
3570 /* Check the parameters */
3571 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3572
3573 if (hi2c->State == HAL_I2C_STATE_READY)
3574 {
3575 /* Process Locked */
3576 __HAL_LOCK(hi2c);
3577
3578 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3579 hi2c->Mode = HAL_I2C_MODE_MASTER;
3580 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3581
3582 /* Prepare transfer parameters */
3583 hi2c->pBuffPtr = pData;
3584 hi2c->XferCount = Size;
3585 hi2c->XferOptions = XferOptions;
3586 hi2c->XferISR = I2C_Master_ISR_IT;
3587
3588 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3589 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3590 {
3591 hi2c->XferSize = MAX_NBYTE_SIZE;
3592 xfermode = I2C_RELOAD_MODE;
3593 }
3594 else
3595 {
3596 hi2c->XferSize = hi2c->XferCount;
3597 xfermode = hi2c->XferOptions;
3598 }
3599
3600 /* If transfer direction not change and there is no request to start another frame,
3601 do not generate Restart Condition */
3602 /* Mean Previous state is same as current state */
3603 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3604 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3605 {
3606 xferrequest = I2C_NO_STARTSTOP;
3607 }
3608 else
3609 {
3610 /* Convert OTHER_xxx XferOptions if any */
3611 I2C_ConvertOtherXferOptions(hi2c);
3612
3613 /* Update xfermode accordingly if no reload is necessary */
3614 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3615 {
3616 xfermode = hi2c->XferOptions;
3617 }
3618 }
3619
3620 /* Send Slave Address and set NBYTES to write */
3621 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3622
3623 /* Process Unlocked */
3624 __HAL_UNLOCK(hi2c);
3625
3626 /* Note : The I2C interrupts must be enabled after unlocking current process
3627 to avoid the risk of I2C interrupt handle execution before current
3628 process unlock */
3629 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3630 /* possible to enable all of these */
3631 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3632 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3633 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3634
3635 return HAL_OK;
3636 }
3637 else
3638 {
3639 return HAL_BUSY;
3640 }
3641 }
3642
3643 #if defined(HAL_DMA_MODULE_ENABLED)
3644 /**
3645 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3646 * @note This interface allow to manage repeated start condition when a direction change during transfer
3647 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3648 * the configuration information for the specified I2C.
3649 * @param DevAddress Target device address: The device 7 bits address value
3650 * in datasheet must be shifted to the left before calling the interface
3651 * @param pData Pointer to data buffer
3652 * @param Size Amount of data to be sent
3653 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3654 * @retval HAL status
3655 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3656 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3657 uint16_t Size, uint32_t XferOptions)
3658 {
3659 uint32_t xfermode;
3660 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
3661 HAL_StatusTypeDef dmaxferstatus;
3662
3663 /* Check the parameters */
3664 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3665
3666 if (hi2c->State == HAL_I2C_STATE_READY)
3667 {
3668 /* Process Locked */
3669 __HAL_LOCK(hi2c);
3670
3671 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3672 hi2c->Mode = HAL_I2C_MODE_MASTER;
3673 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3674
3675 /* Prepare transfer parameters */
3676 hi2c->pBuffPtr = pData;
3677 hi2c->XferCount = Size;
3678 hi2c->XferOptions = XferOptions;
3679 hi2c->XferISR = I2C_Master_ISR_DMA;
3680
3681 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3682 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3683 {
3684 hi2c->XferSize = MAX_NBYTE_SIZE;
3685 xfermode = I2C_RELOAD_MODE;
3686 }
3687 else
3688 {
3689 hi2c->XferSize = hi2c->XferCount;
3690 xfermode = hi2c->XferOptions;
3691 }
3692
3693 /* If transfer direction not change and there is no request to start another frame,
3694 do not generate Restart Condition */
3695 /* Mean Previous state is same as current state */
3696 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
3697 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3698 {
3699 xferrequest = I2C_NO_STARTSTOP;
3700 }
3701 else
3702 {
3703 /* Convert OTHER_xxx XferOptions if any */
3704 I2C_ConvertOtherXferOptions(hi2c);
3705
3706 /* Update xfermode accordingly if no reload is necessary */
3707 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3708 {
3709 xfermode = hi2c->XferOptions;
3710 }
3711 }
3712
3713 if (hi2c->XferSize > 0U)
3714 {
3715 if (hi2c->hdmatx != NULL)
3716 {
3717 /* Set the I2C DMA transfer complete callback */
3718 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
3719
3720 /* Set the DMA error callback */
3721 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3722
3723 /* Set the unused DMA callbacks to NULL */
3724 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3725 hi2c->hdmatx->XferAbortCallback = NULL;
3726
3727 /* Enable the DMA channel */
3728 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
3729 {
3730 if (hi2c->hdmatx->LinkedListQueue != NULL)
3731 {
3732 /* Set DMA data size */
3733 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
3734
3735 /* Set DMA source address */
3736 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
3737
3738 /* Set DMA destination address */
3739 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
3740 = (uint32_t)&hi2c->Instance->TXDR;
3741
3742 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
3743 }
3744 else
3745 {
3746 /* Update I2C state */
3747 hi2c->State = HAL_I2C_STATE_READY;
3748 hi2c->Mode = HAL_I2C_MODE_NONE;
3749
3750 /* Update I2C error code */
3751 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3752
3753 /* Process Unlocked */
3754 __HAL_UNLOCK(hi2c);
3755
3756 return HAL_ERROR;
3757 }
3758 }
3759 else
3760 {
3761 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
3762 hi2c->XferSize);
3763 }
3764 }
3765 else
3766 {
3767 /* Update I2C state */
3768 hi2c->State = HAL_I2C_STATE_READY;
3769 hi2c->Mode = HAL_I2C_MODE_NONE;
3770
3771 /* Update I2C error code */
3772 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3773
3774 /* Process Unlocked */
3775 __HAL_UNLOCK(hi2c);
3776
3777 return HAL_ERROR;
3778 }
3779
3780 if (dmaxferstatus == HAL_OK)
3781 {
3782 /* Send Slave Address and set NBYTES to write */
3783 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3784
3785 /* Update XferCount value */
3786 hi2c->XferCount -= hi2c->XferSize;
3787
3788 /* Process Unlocked */
3789 __HAL_UNLOCK(hi2c);
3790
3791 /* Note : The I2C interrupts must be enabled after unlocking current process
3792 to avoid the risk of I2C interrupt handle execution before current
3793 process unlock */
3794 /* Enable ERR and NACK interrupts */
3795 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
3796
3797 /* Enable DMA Request */
3798 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3799 }
3800 else
3801 {
3802 /* Update I2C state */
3803 hi2c->State = HAL_I2C_STATE_READY;
3804 hi2c->Mode = HAL_I2C_MODE_NONE;
3805
3806 /* Update I2C error code */
3807 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3808
3809 /* Process Unlocked */
3810 __HAL_UNLOCK(hi2c);
3811
3812 return HAL_ERROR;
3813 }
3814 }
3815 else
3816 {
3817 /* Update Transfer ISR function pointer */
3818 hi2c->XferISR = I2C_Master_ISR_IT;
3819
3820 /* Send Slave Address */
3821 /* Set NBYTES to write and generate START condition */
3822 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
3823 I2C_GENERATE_START_WRITE);
3824
3825 /* Process Unlocked */
3826 __HAL_UNLOCK(hi2c);
3827
3828 /* Note : The I2C interrupts must be enabled after unlocking current process
3829 to avoid the risk of I2C interrupt handle execution before current
3830 process unlock */
3831 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
3832 /* possible to enable all of these */
3833 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
3834 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
3835 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
3836 }
3837
3838 return HAL_OK;
3839 }
3840 else
3841 {
3842 return HAL_BUSY;
3843 }
3844 }
3845 #endif /* HAL_DMA_MODULE_ENABLED */
3846
3847 /**
3848 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3849 * @note This interface allow to manage repeated start condition when a direction change during transfer
3850 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3851 * the configuration information for the specified I2C.
3852 * @param DevAddress Target device address: The device 7 bits address value
3853 * in datasheet must be shifted to the left before calling the interface
3854 * @param pData Pointer to data buffer
3855 * @param Size Amount of data to be sent
3856 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3857 * @retval HAL status
3858 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3859 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3860 uint16_t Size, uint32_t XferOptions)
3861 {
3862 uint32_t xfermode;
3863 uint32_t xferrequest = I2C_GENERATE_START_READ;
3864
3865 /* Check the parameters */
3866 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3867
3868 if (hi2c->State == HAL_I2C_STATE_READY)
3869 {
3870 /* Process Locked */
3871 __HAL_LOCK(hi2c);
3872
3873 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3874 hi2c->Mode = HAL_I2C_MODE_MASTER;
3875 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3876
3877 /* Prepare transfer parameters */
3878 hi2c->pBuffPtr = pData;
3879 hi2c->XferCount = Size;
3880 hi2c->XferOptions = XferOptions;
3881 hi2c->XferISR = I2C_Master_ISR_IT;
3882
3883 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3884 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3885 {
3886 hi2c->XferSize = MAX_NBYTE_SIZE;
3887 xfermode = I2C_RELOAD_MODE;
3888 }
3889 else
3890 {
3891 hi2c->XferSize = hi2c->XferCount;
3892 xfermode = hi2c->XferOptions;
3893 }
3894
3895 /* If transfer direction not change and there is no request to start another frame,
3896 do not generate Restart Condition */
3897 /* Mean Previous state is same as current state */
3898 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3899 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3900 {
3901 xferrequest = I2C_NO_STARTSTOP;
3902 }
3903 else
3904 {
3905 /* Convert OTHER_xxx XferOptions if any */
3906 I2C_ConvertOtherXferOptions(hi2c);
3907
3908 /* Update xfermode accordingly if no reload is necessary */
3909 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3910 {
3911 xfermode = hi2c->XferOptions;
3912 }
3913 }
3914
3915 /* Send Slave Address and set NBYTES to read */
3916 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
3917
3918 /* Process Unlocked */
3919 __HAL_UNLOCK(hi2c);
3920
3921 /* Note : The I2C interrupts must be enabled after unlocking current process
3922 to avoid the risk of I2C interrupt handle execution before current
3923 process unlock */
3924 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
3925
3926 return HAL_OK;
3927 }
3928 else
3929 {
3930 return HAL_BUSY;
3931 }
3932 }
3933
3934 #if defined(HAL_DMA_MODULE_ENABLED)
3935 /**
3936 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA
3937 * @note This interface allow to manage repeated start condition when a direction change during transfer
3938 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3939 * the configuration information for the specified I2C.
3940 * @param DevAddress Target device address: The device 7 bits address value
3941 * in datasheet must be shifted to the left before calling the interface
3942 * @param pData Pointer to data buffer
3943 * @param Size Amount of data to be sent
3944 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
3945 * @retval HAL status
3946 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3947 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
3948 uint16_t Size, uint32_t XferOptions)
3949 {
3950 uint32_t xfermode;
3951 uint32_t xferrequest = I2C_GENERATE_START_READ;
3952 HAL_StatusTypeDef dmaxferstatus;
3953
3954 /* Check the parameters */
3955 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3956
3957 if (hi2c->State == HAL_I2C_STATE_READY)
3958 {
3959 /* Process Locked */
3960 __HAL_LOCK(hi2c);
3961
3962 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3963 hi2c->Mode = HAL_I2C_MODE_MASTER;
3964 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3965
3966 /* Prepare transfer parameters */
3967 hi2c->pBuffPtr = pData;
3968 hi2c->XferCount = Size;
3969 hi2c->XferOptions = XferOptions;
3970 hi2c->XferISR = I2C_Master_ISR_DMA;
3971
3972 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
3973 if (hi2c->XferCount > MAX_NBYTE_SIZE)
3974 {
3975 hi2c->XferSize = MAX_NBYTE_SIZE;
3976 xfermode = I2C_RELOAD_MODE;
3977 }
3978 else
3979 {
3980 hi2c->XferSize = hi2c->XferCount;
3981 xfermode = hi2c->XferOptions;
3982 }
3983
3984 /* If transfer direction not change and there is no request to start another frame,
3985 do not generate Restart Condition */
3986 /* Mean Previous state is same as current state */
3987 if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
3988 (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
3989 {
3990 xferrequest = I2C_NO_STARTSTOP;
3991 }
3992 else
3993 {
3994 /* Convert OTHER_xxx XferOptions if any */
3995 I2C_ConvertOtherXferOptions(hi2c);
3996
3997 /* Update xfermode accordingly if no reload is necessary */
3998 if (hi2c->XferCount <= MAX_NBYTE_SIZE)
3999 {
4000 xfermode = hi2c->XferOptions;
4001 }
4002 }
4003
4004 if (hi2c->XferSize > 0U)
4005 {
4006 if (hi2c->hdmarx != NULL)
4007 {
4008 /* Set the I2C DMA transfer complete callback */
4009 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
4010
4011 /* Set the DMA error callback */
4012 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4013
4014 /* Set the unused DMA callbacks to NULL */
4015 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4016 hi2c->hdmarx->XferAbortCallback = NULL;
4017
4018 /* Enable the DMA channel */
4019 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4020 {
4021 if (hi2c->hdmarx->LinkedListQueue != NULL)
4022 {
4023 /* Set DMA data size */
4024 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4025
4026 /* Set DMA source address */
4027 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4028 = (uint32_t)&hi2c->Instance->RXDR;
4029
4030 /* Set DMA destination address */
4031 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4032
4033 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4034 }
4035 else
4036 {
4037 hi2c->State = HAL_I2C_STATE_READY;
4038 hi2c->Mode = HAL_I2C_MODE_NONE;
4039
4040 /* Update I2C error code */
4041 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4042
4043 /* Process Unlocked */
4044 __HAL_UNLOCK(hi2c);
4045
4046 return HAL_ERROR;
4047 }
4048 }
4049 else
4050 {
4051 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4052 hi2c->XferSize);
4053 }
4054 }
4055 else
4056 {
4057 /* Update I2C state */
4058 hi2c->State = HAL_I2C_STATE_READY;
4059 hi2c->Mode = HAL_I2C_MODE_NONE;
4060
4061 /* Update I2C error code */
4062 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4063
4064 /* Process Unlocked */
4065 __HAL_UNLOCK(hi2c);
4066
4067 return HAL_ERROR;
4068 }
4069
4070 if (dmaxferstatus == HAL_OK)
4071 {
4072 /* Send Slave Address and set NBYTES to read */
4073 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
4074
4075 /* Update XferCount value */
4076 hi2c->XferCount -= hi2c->XferSize;
4077
4078 /* Process Unlocked */
4079 __HAL_UNLOCK(hi2c);
4080
4081 /* Note : The I2C interrupts must be enabled after unlocking current process
4082 to avoid the risk of I2C interrupt handle execution before current
4083 process unlock */
4084 /* Enable ERR and NACK interrupts */
4085 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
4086
4087 /* Enable DMA Request */
4088 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4089 }
4090 else
4091 {
4092 /* Update I2C state */
4093 hi2c->State = HAL_I2C_STATE_READY;
4094 hi2c->Mode = HAL_I2C_MODE_NONE;
4095
4096 /* Update I2C error code */
4097 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4098
4099 /* Process Unlocked */
4100 __HAL_UNLOCK(hi2c);
4101
4102 return HAL_ERROR;
4103 }
4104 }
4105 else
4106 {
4107 /* Update Transfer ISR function pointer */
4108 hi2c->XferISR = I2C_Master_ISR_IT;
4109
4110 /* Send Slave Address */
4111 /* Set NBYTES to read and generate START condition */
4112 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
4113 I2C_GENERATE_START_READ);
4114
4115 /* Process Unlocked */
4116 __HAL_UNLOCK(hi2c);
4117
4118 /* Note : The I2C interrupts must be enabled after unlocking current process
4119 to avoid the risk of I2C interrupt handle execution before current
4120 process unlock */
4121 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
4122 /* possible to enable all of these */
4123 /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
4124 I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
4125 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
4126 }
4127
4128 return HAL_OK;
4129 }
4130 else
4131 {
4132 return HAL_BUSY;
4133 }
4134 }
4135 #endif /* HAL_DMA_MODULE_ENABLED */
4136
4137 /**
4138 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4139 * @note This interface allow to manage repeated start condition when a direction change during transfer
4140 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4141 * the configuration information for the specified I2C.
4142 * @param pData Pointer to data buffer
4143 * @param Size Amount of data to be sent
4144 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4145 * @retval HAL status
4146 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4147 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4148 uint32_t XferOptions)
4149 {
4150 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4151 FlagStatus tmp;
4152
4153 /* Check the parameters */
4154 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4155
4156 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4157 {
4158 if ((pData == NULL) || (Size == 0U))
4159 {
4160 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4161 return HAL_ERROR;
4162 }
4163
4164 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4165 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4166
4167 /* Process Locked */
4168 __HAL_LOCK(hi2c);
4169
4170 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4171 /* and then toggle the HAL slave RX state to TX state */
4172 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4173 {
4174 /* Disable associated Interrupts */
4175 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4176
4177 #if defined(HAL_DMA_MODULE_ENABLED)
4178 /* Abort DMA Xfer if any */
4179 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4180 {
4181 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4182
4183 if (hi2c->hdmarx != NULL)
4184 {
4185 /* Set the I2C DMA Abort callback :
4186 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4187 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4188
4189 /* Abort DMA RX */
4190 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4191 {
4192 /* Call Directly XferAbortCallback function in case of error */
4193 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4194 }
4195 }
4196 }
4197 #endif /* HAL_DMA_MODULE_ENABLED */
4198 }
4199
4200 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4201 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4202 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4203
4204 /* Enable Address Acknowledge */
4205 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4206
4207 /* Prepare transfer parameters */
4208 hi2c->pBuffPtr = pData;
4209 hi2c->XferCount = Size;
4210 hi2c->XferSize = hi2c->XferCount;
4211 hi2c->XferOptions = XferOptions;
4212 hi2c->XferISR = I2C_Slave_ISR_IT;
4213
4214 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4215 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4216 {
4217 /* Clear ADDR flag after prepare the transfer parameters */
4218 /* This action will generate an acknowledge to the Master */
4219 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4220 }
4221
4222 /* Process Unlocked */
4223 __HAL_UNLOCK(hi2c);
4224
4225 /* Note : The I2C interrupts must be enabled after unlocking current process
4226 to avoid the risk of I2C interrupt handle execution before current
4227 process unlock */
4228 /* REnable ADDR interrupt */
4229 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
4230
4231 return HAL_OK;
4232 }
4233 else
4234 {
4235 return HAL_ERROR;
4236 }
4237 }
4238
4239 #if defined(HAL_DMA_MODULE_ENABLED)
4240 /**
4241 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA
4242 * @note This interface allow to manage repeated start condition when a direction change during transfer
4243 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4244 * the configuration information for the specified I2C.
4245 * @param pData Pointer to data buffer
4246 * @param Size Amount of data to be sent
4247 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4248 * @retval HAL status
4249 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4250 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4251 uint32_t XferOptions)
4252 {
4253 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4254 FlagStatus tmp;
4255 HAL_StatusTypeDef dmaxferstatus;
4256
4257 /* Check the parameters */
4258 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4259
4260 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4261 {
4262 if ((pData == NULL) || (Size == 0U))
4263 {
4264 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4265 return HAL_ERROR;
4266 }
4267
4268 /* Process Locked */
4269 __HAL_LOCK(hi2c);
4270
4271 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4272 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
4273
4274 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4275 /* and then toggle the HAL slave RX state to TX state */
4276 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4277 {
4278 /* Disable associated Interrupts */
4279 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4280
4281 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4282 {
4283 /* Abort DMA Xfer if any */
4284 if (hi2c->hdmarx != NULL)
4285 {
4286 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4287
4288 /* Set the I2C DMA Abort callback :
4289 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4290 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4291
4292 /* Abort DMA RX */
4293 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4294 {
4295 /* Call Directly XferAbortCallback function in case of error */
4296 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4297 }
4298 }
4299 }
4300 }
4301 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4302 {
4303 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4304 {
4305 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4306
4307 /* Abort DMA Xfer if any */
4308 if (hi2c->hdmatx != NULL)
4309 {
4310 /* Set the I2C DMA Abort callback :
4311 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4312 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4313
4314 /* Abort DMA TX */
4315 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4316 {
4317 /* Call Directly XferAbortCallback function in case of error */
4318 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4319 }
4320 }
4321 }
4322 }
4323 else
4324 {
4325 /* Nothing to do */
4326 }
4327
4328 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4329 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4330 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4331
4332 /* Enable Address Acknowledge */
4333 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4334
4335 /* Prepare transfer parameters */
4336 hi2c->pBuffPtr = pData;
4337 hi2c->XferCount = Size;
4338 hi2c->XferSize = hi2c->XferCount;
4339 hi2c->XferOptions = XferOptions;
4340 hi2c->XferISR = I2C_Slave_ISR_DMA;
4341
4342 if (hi2c->hdmatx != NULL)
4343 {
4344 /* Set the I2C DMA transfer complete callback */
4345 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
4346
4347 /* Set the DMA error callback */
4348 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4349
4350 /* Set the unused DMA callbacks to NULL */
4351 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4352 hi2c->hdmatx->XferAbortCallback = NULL;
4353
4354 /* Enable the DMA channel */
4355 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4356 {
4357 if (hi2c->hdmatx->LinkedListQueue != NULL)
4358 {
4359 /* Set DMA data size */
4360 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4361
4362 /* Set DMA source address */
4363 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
4364
4365 /* Set DMA destination address */
4366 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \
4367 = (uint32_t)&hi2c->Instance->TXDR;
4368
4369 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
4370 }
4371 else
4372 {
4373 /* Update I2C state */
4374 hi2c->State = HAL_I2C_STATE_LISTEN;
4375 hi2c->Mode = HAL_I2C_MODE_NONE;
4376
4377 /* Update I2C error code */
4378 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4379
4380 /* Process Unlocked */
4381 __HAL_UNLOCK(hi2c);
4382
4383 return HAL_ERROR;
4384 }
4385 }
4386 else
4387 {
4388 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
4389 hi2c->XferSize);
4390 }
4391 }
4392 else
4393 {
4394 /* Update I2C state */
4395 hi2c->State = HAL_I2C_STATE_LISTEN;
4396 hi2c->Mode = HAL_I2C_MODE_NONE;
4397
4398 /* Update I2C error code */
4399 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4400
4401 /* Process Unlocked */
4402 __HAL_UNLOCK(hi2c);
4403
4404 return HAL_ERROR;
4405 }
4406
4407 if (dmaxferstatus == HAL_OK)
4408 {
4409 /* Update XferCount value */
4410 hi2c->XferCount -= hi2c->XferSize;
4411
4412 /* Reset XferSize */
4413 hi2c->XferSize = 0;
4414 }
4415 else
4416 {
4417 /* Update I2C state */
4418 hi2c->State = HAL_I2C_STATE_LISTEN;
4419 hi2c->Mode = HAL_I2C_MODE_NONE;
4420
4421 /* Update I2C error code */
4422 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4423
4424 /* Process Unlocked */
4425 __HAL_UNLOCK(hi2c);
4426
4427 return HAL_ERROR;
4428 }
4429
4430 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4431 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
4432 {
4433 /* Clear ADDR flag after prepare the transfer parameters */
4434 /* This action will generate an acknowledge to the Master */
4435 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4436 }
4437
4438 /* Process Unlocked */
4439 __HAL_UNLOCK(hi2c);
4440
4441 /* Enable DMA Request */
4442 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
4443
4444 /* Note : The I2C interrupts must be enabled after unlocking current process
4445 to avoid the risk of I2C interrupt handle execution before current
4446 process unlock */
4447 /* Enable ERR, STOP, NACK, ADDR interrupts */
4448 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4449
4450 return HAL_OK;
4451 }
4452 else
4453 {
4454 return HAL_ERROR;
4455 }
4456 }
4457 #endif /* HAL_DMA_MODULE_ENABLED */
4458
4459 /**
4460 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
4461 * @note This interface allow to manage repeated start condition when a direction change during transfer
4462 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4463 * the configuration information for the specified I2C.
4464 * @param pData Pointer to data buffer
4465 * @param Size Amount of data to be sent
4466 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4467 * @retval HAL status
4468 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4469 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4470 uint32_t XferOptions)
4471 {
4472 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4473 FlagStatus tmp;
4474
4475 /* Check the parameters */
4476 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4477
4478 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4479 {
4480 if ((pData == NULL) || (Size == 0U))
4481 {
4482 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4483 return HAL_ERROR;
4484 }
4485
4486 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4487 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4488
4489 /* Process Locked */
4490 __HAL_LOCK(hi2c);
4491
4492 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4493 /* and then toggle the HAL slave TX state to RX state */
4494 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4495 {
4496 /* Disable associated Interrupts */
4497 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4498
4499 #if defined(HAL_DMA_MODULE_ENABLED)
4500 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4501 {
4502 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4503
4504 /* Abort DMA Xfer if any */
4505 if (hi2c->hdmatx != NULL)
4506 {
4507 /* Set the I2C DMA Abort callback :
4508 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4509 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4510
4511 /* Abort DMA TX */
4512 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4513 {
4514 /* Call Directly XferAbortCallback function in case of error */
4515 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4516 }
4517 }
4518 }
4519 #endif /* HAL_DMA_MODULE_ENABLED */
4520 }
4521
4522 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4523 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4524 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4525
4526 /* Enable Address Acknowledge */
4527 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4528
4529 /* Prepare transfer parameters */
4530 hi2c->pBuffPtr = pData;
4531 hi2c->XferCount = Size;
4532 hi2c->XferSize = hi2c->XferCount;
4533 hi2c->XferOptions = XferOptions;
4534 hi2c->XferISR = I2C_Slave_ISR_IT;
4535
4536 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4537 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4538 {
4539 /* Clear ADDR flag after prepare the transfer parameters */
4540 /* This action will generate an acknowledge to the Master */
4541 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4542 }
4543
4544 /* Process Unlocked */
4545 __HAL_UNLOCK(hi2c);
4546
4547 /* Note : The I2C interrupts must be enabled after unlocking current process
4548 to avoid the risk of I2C interrupt handle execution before current
4549 process unlock */
4550 /* REnable ADDR interrupt */
4551 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4552
4553 return HAL_OK;
4554 }
4555 else
4556 {
4557 return HAL_ERROR;
4558 }
4559 }
4560
4561 #if defined(HAL_DMA_MODULE_ENABLED)
4562 /**
4563 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA
4564 * @note This interface allow to manage repeated start condition when a direction change during transfer
4565 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4566 * the configuration information for the specified I2C.
4567 * @param pData Pointer to data buffer
4568 * @param Size Amount of data to be sent
4569 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
4570 * @retval HAL status
4571 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4572 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
4573 uint32_t XferOptions)
4574 {
4575 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4576 FlagStatus tmp;
4577 HAL_StatusTypeDef dmaxferstatus;
4578
4579 /* Check the parameters */
4580 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4581
4582 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4583 {
4584 if ((pData == NULL) || (Size == 0U))
4585 {
4586 hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
4587 return HAL_ERROR;
4588 }
4589
4590 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4591 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
4592
4593 /* Process Locked */
4594 __HAL_LOCK(hi2c);
4595
4596 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4597 /* and then toggle the HAL slave TX state to RX state */
4598 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4599 {
4600 /* Disable associated Interrupts */
4601 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4602
4603 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4604 {
4605 /* Abort DMA Xfer if any */
4606 if (hi2c->hdmatx != NULL)
4607 {
4608 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4609
4610 /* Set the I2C DMA Abort callback :
4611 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4612 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4613
4614 /* Abort DMA TX */
4615 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4616 {
4617 /* Call Directly XferAbortCallback function in case of error */
4618 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4619 }
4620 }
4621 }
4622 }
4623 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4624 {
4625 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4626 {
4627 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4628
4629 /* Abort DMA Xfer if any */
4630 if (hi2c->hdmarx != NULL)
4631 {
4632 /* Set the I2C DMA Abort callback :
4633 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4634 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4635
4636 /* Abort DMA RX */
4637 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4638 {
4639 /* Call Directly XferAbortCallback function in case of error */
4640 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4641 }
4642 }
4643 }
4644 }
4645 else
4646 {
4647 /* Nothing to do */
4648 }
4649
4650 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4651 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4652 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4653
4654 /* Enable Address Acknowledge */
4655 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
4656
4657 /* Prepare transfer parameters */
4658 hi2c->pBuffPtr = pData;
4659 hi2c->XferCount = Size;
4660 hi2c->XferSize = hi2c->XferCount;
4661 hi2c->XferOptions = XferOptions;
4662 hi2c->XferISR = I2C_Slave_ISR_DMA;
4663
4664 if (hi2c->hdmarx != NULL)
4665 {
4666 /* Set the I2C DMA transfer complete callback */
4667 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
4668
4669 /* Set the DMA error callback */
4670 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4671
4672 /* Set the unused DMA callbacks to NULL */
4673 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4674 hi2c->hdmarx->XferAbortCallback = NULL;
4675
4676 /* Enable the DMA channel */
4677 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
4678 {
4679 if (hi2c->hdmarx->LinkedListQueue != NULL)
4680 {
4681 /* Set DMA data size */
4682 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
4683
4684 /* Set DMA source address */
4685 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \
4686 = (uint32_t)&hi2c->Instance->RXDR;
4687
4688 /* Set DMA destination address */
4689 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData;
4690
4691 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
4692 }
4693 else
4694 {
4695 /* Update I2C state */
4696 hi2c->State = HAL_I2C_STATE_LISTEN;
4697 hi2c->Mode = HAL_I2C_MODE_NONE;
4698
4699 /* Update I2C error code */
4700 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4701
4702 /* Process Unlocked */
4703 __HAL_UNLOCK(hi2c);
4704
4705 return HAL_ERROR;
4706 }
4707 }
4708 else
4709 {
4710 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
4711 hi2c->XferSize);
4712 }
4713 }
4714 else
4715 {
4716 /* Update I2C state */
4717 hi2c->State = HAL_I2C_STATE_LISTEN;
4718 hi2c->Mode = HAL_I2C_MODE_NONE;
4719
4720 /* Update I2C error code */
4721 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4722
4723 /* Process Unlocked */
4724 __HAL_UNLOCK(hi2c);
4725
4726 return HAL_ERROR;
4727 }
4728
4729 if (dmaxferstatus == HAL_OK)
4730 {
4731 /* Update XferCount value */
4732 hi2c->XferCount -= hi2c->XferSize;
4733
4734 /* Reset XferSize */
4735 hi2c->XferSize = 0;
4736 }
4737 else
4738 {
4739 /* Update I2C state */
4740 hi2c->State = HAL_I2C_STATE_LISTEN;
4741 hi2c->Mode = HAL_I2C_MODE_NONE;
4742
4743 /* Update I2C error code */
4744 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4745
4746 /* Process Unlocked */
4747 __HAL_UNLOCK(hi2c);
4748
4749 return HAL_ERROR;
4750 }
4751
4752 tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
4753 if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
4754 {
4755 /* Clear ADDR flag after prepare the transfer parameters */
4756 /* This action will generate an acknowledge to the Master */
4757 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
4758 }
4759
4760 /* Process Unlocked */
4761 __HAL_UNLOCK(hi2c);
4762
4763 /* Enable DMA Request */
4764 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
4765
4766 /* Note : The I2C interrupts must be enabled after unlocking current process
4767 to avoid the risk of I2C interrupt handle execution before current
4768 process unlock */
4769 /* REnable ADDR interrupt */
4770 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
4771
4772 return HAL_OK;
4773 }
4774 else
4775 {
4776 return HAL_ERROR;
4777 }
4778 }
4779 #endif /* HAL_DMA_MODULE_ENABLED */
4780
4781 /**
4782 * @brief Enable the Address listen mode with Interrupt.
4783 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4784 * the configuration information for the specified I2C.
4785 * @retval HAL status
4786 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4787 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4788 {
4789 if (hi2c->State == HAL_I2C_STATE_READY)
4790 {
4791 hi2c->State = HAL_I2C_STATE_LISTEN;
4792 hi2c->XferISR = I2C_Slave_ISR_IT;
4793
4794 /* Enable the Address Match interrupt */
4795 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4796
4797 return HAL_OK;
4798 }
4799 else
4800 {
4801 return HAL_BUSY;
4802 }
4803 }
4804
4805 /**
4806 * @brief Disable the Address listen mode with Interrupt.
4807 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4808 * the configuration information for the specified I2C
4809 * @retval HAL status
4810 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4811 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4812 {
4813 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4814 uint32_t tmp;
4815
4816 /* Disable Address listen mode only if a transfer is not ongoing */
4817 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4818 {
4819 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4820 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4821 hi2c->State = HAL_I2C_STATE_READY;
4822 hi2c->Mode = HAL_I2C_MODE_NONE;
4823 hi2c->XferISR = NULL;
4824
4825 /* Disable the Address Match interrupt */
4826 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
4827
4828 return HAL_OK;
4829 }
4830 else
4831 {
4832 return HAL_BUSY;
4833 }
4834 }
4835
4836 /**
4837 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4838 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4839 * the configuration information for the specified I2C.
4840 * @param DevAddress Target device address: The device 7 bits address value
4841 * in datasheet must be shifted to the left before calling the interface
4842 * @retval HAL status
4843 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4844 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4845 {
4846 if (hi2c->Mode == HAL_I2C_MODE_MASTER)
4847 {
4848 /* Process Locked */
4849 __HAL_LOCK(hi2c);
4850
4851 /* Disable Interrupts and Store Previous state */
4852 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
4853 {
4854 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
4855 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
4856 }
4857 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
4858 {
4859 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
4860 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
4861 }
4862 else
4863 {
4864 /* Do nothing */
4865 }
4866
4867 /* Set State at HAL_I2C_STATE_ABORT */
4868 hi2c->State = HAL_I2C_STATE_ABORT;
4869
4870 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
4871 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
4872 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
4873
4874 /* Process Unlocked */
4875 __HAL_UNLOCK(hi2c);
4876
4877 /* Note : The I2C interrupts must be enabled after unlocking current process
4878 to avoid the risk of I2C interrupt handle execution before current
4879 process unlock */
4880 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4881
4882 return HAL_OK;
4883 }
4884 else
4885 {
4886 /* Wrong usage of abort function */
4887 /* This function should be used only in case of abort monitored by master device */
4888 return HAL_ERROR;
4889 }
4890 }
4891
4892 /**
4893 * @}
4894 */
4895
4896 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4897 * @{
4898 */
4899
4900 /**
4901 * @brief This function handles I2C event interrupt request.
4902 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4903 * the configuration information for the specified I2C.
4904 * @retval None
4905 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4906 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
4907 {
4908 /* Get current IT Flags and IT sources value */
4909 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4910 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4911
4912 /* I2C events treatment -------------------------------------*/
4913 if (hi2c->XferISR != NULL)
4914 {
4915 hi2c->XferISR(hi2c, itflags, itsources);
4916 }
4917 }
4918
4919 /**
4920 * @brief This function handles I2C error interrupt request.
4921 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4922 * the configuration information for the specified I2C.
4923 * @retval None
4924 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4925 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4926 {
4927 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
4928 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
4929 uint32_t tmperror;
4930
4931 /* I2C Bus error interrupt occurred ------------------------------------*/
4932 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
4933 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4934 {
4935 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
4936
4937 /* Clear BERR flag */
4938 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4939 }
4940
4941 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
4942 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
4943 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4944 {
4945 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
4946
4947 /* Clear OVR flag */
4948 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4949 }
4950
4951 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
4952 if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
4953 (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
4954 {
4955 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
4956
4957 /* Clear ARLO flag */
4958 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4959 }
4960
4961 /* Store current volatile hi2c->ErrorCode, misra rule */
4962 tmperror = hi2c->ErrorCode;
4963
4964 /* Call the Error Callback in case of Error detected */
4965 if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
4966 {
4967 I2C_ITError(hi2c, tmperror);
4968 }
4969 }
4970
4971 /**
4972 * @brief Master Tx Transfer completed callback.
4973 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4974 * the configuration information for the specified I2C.
4975 * @retval None
4976 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)4977 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
4978 {
4979 /* Prevent unused argument(s) compilation warning */
4980 UNUSED(hi2c);
4981
4982 /* NOTE : This function should not be modified, when the callback is needed,
4983 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
4984 */
4985 }
4986
4987 /**
4988 * @brief Master Rx Transfer completed callback.
4989 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4990 * the configuration information for the specified I2C.
4991 * @retval None
4992 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)4993 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
4994 {
4995 /* Prevent unused argument(s) compilation warning */
4996 UNUSED(hi2c);
4997
4998 /* NOTE : This function should not be modified, when the callback is needed,
4999 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5000 */
5001 }
5002
5003 /** @brief Slave Tx Transfer completed callback.
5004 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5005 * the configuration information for the specified I2C.
5006 * @retval None
5007 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5008 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5009 {
5010 /* Prevent unused argument(s) compilation warning */
5011 UNUSED(hi2c);
5012
5013 /* NOTE : This function should not be modified, when the callback is needed,
5014 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5015 */
5016 }
5017
5018 /**
5019 * @brief Slave Rx Transfer completed callback.
5020 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5021 * the configuration information for the specified I2C.
5022 * @retval None
5023 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5024 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5025 {
5026 /* Prevent unused argument(s) compilation warning */
5027 UNUSED(hi2c);
5028
5029 /* NOTE : This function should not be modified, when the callback is needed,
5030 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5031 */
5032 }
5033
5034 /**
5035 * @brief Slave Address Match callback.
5036 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5037 * the configuration information for the specified I2C.
5038 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
5039 * @param AddrMatchCode Address Match Code
5040 * @retval None
5041 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5042 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5043 {
5044 /* Prevent unused argument(s) compilation warning */
5045 UNUSED(hi2c);
5046 UNUSED(TransferDirection);
5047 UNUSED(AddrMatchCode);
5048
5049 /* NOTE : This function should not be modified, when the callback is needed,
5050 the HAL_I2C_AddrCallback() could be implemented in the user file
5051 */
5052 }
5053
5054 /**
5055 * @brief Listen Complete callback.
5056 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5057 * the configuration information for the specified I2C.
5058 * @retval None
5059 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5060 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5061 {
5062 /* Prevent unused argument(s) compilation warning */
5063 UNUSED(hi2c);
5064
5065 /* NOTE : This function should not be modified, when the callback is needed,
5066 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5067 */
5068 }
5069
5070 /**
5071 * @brief Memory Tx Transfer completed callback.
5072 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5073 * the configuration information for the specified I2C.
5074 * @retval None
5075 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5076 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5077 {
5078 /* Prevent unused argument(s) compilation warning */
5079 UNUSED(hi2c);
5080
5081 /* NOTE : This function should not be modified, when the callback is needed,
5082 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5083 */
5084 }
5085
5086 /**
5087 * @brief Memory Rx Transfer completed callback.
5088 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5089 * the configuration information for the specified I2C.
5090 * @retval None
5091 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5092 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5093 {
5094 /* Prevent unused argument(s) compilation warning */
5095 UNUSED(hi2c);
5096
5097 /* NOTE : This function should not be modified, when the callback is needed,
5098 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5099 */
5100 }
5101
5102 /**
5103 * @brief I2C error callback.
5104 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5105 * the configuration information for the specified I2C.
5106 * @retval None
5107 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5108 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5109 {
5110 /* Prevent unused argument(s) compilation warning */
5111 UNUSED(hi2c);
5112
5113 /* NOTE : This function should not be modified, when the callback is needed,
5114 the HAL_I2C_ErrorCallback could be implemented in the user file
5115 */
5116 }
5117
5118 /**
5119 * @brief I2C abort callback.
5120 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5121 * the configuration information for the specified I2C.
5122 * @retval None
5123 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5124 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5125 {
5126 /* Prevent unused argument(s) compilation warning */
5127 UNUSED(hi2c);
5128
5129 /* NOTE : This function should not be modified, when the callback is needed,
5130 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5131 */
5132 }
5133
5134 /**
5135 * @}
5136 */
5137
5138 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5139 * @brief Peripheral State, Mode and Error functions
5140 *
5141 @verbatim
5142 ===============================================================================
5143 ##### Peripheral State, Mode and Error functions #####
5144 ===============================================================================
5145 [..]
5146 This subsection permit to get in run-time the status of the peripheral
5147 and the data flow.
5148
5149 @endverbatim
5150 * @{
5151 */
5152
5153 /**
5154 * @brief Return the I2C handle state.
5155 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5156 * the configuration information for the specified I2C.
5157 * @retval HAL state
5158 */
HAL_I2C_GetState(const I2C_HandleTypeDef * hi2c)5159 HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
5160 {
5161 /* Return I2C handle state */
5162 return hi2c->State;
5163 }
5164
5165 /**
5166 * @brief Returns the I2C Master, Slave, Memory or no mode.
5167 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5168 * the configuration information for I2C module
5169 * @retval HAL mode
5170 */
HAL_I2C_GetMode(const I2C_HandleTypeDef * hi2c)5171 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
5172 {
5173 return hi2c->Mode;
5174 }
5175
5176 /**
5177 * @brief Return the I2C error code.
5178 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5179 * the configuration information for the specified I2C.
5180 * @retval I2C Error Code
5181 */
HAL_I2C_GetError(const I2C_HandleTypeDef * hi2c)5182 uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
5183 {
5184 return hi2c->ErrorCode;
5185 }
5186
5187 /**
5188 * @}
5189 */
5190
5191 /**
5192 * @}
5193 */
5194
5195 /** @addtogroup I2C_Private_Functions
5196 * @{
5197 */
5198
5199 /**
5200 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
5201 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5202 * the configuration information for the specified I2C.
5203 * @param ITFlags Interrupt flags to handle.
5204 * @param ITSources Interrupt sources enabled.
5205 * @retval HAL status
5206 */
I2C_Master_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5207 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5208 uint32_t ITSources)
5209 {
5210 uint16_t devaddress;
5211 uint32_t tmpITFlags = ITFlags;
5212
5213 /* Process Locked */
5214 __HAL_LOCK(hi2c);
5215
5216 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5217 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5218 {
5219 /* Clear NACK Flag */
5220 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5221
5222 /* Set corresponding Error Code */
5223 /* No need to generate STOP, it is automatically done */
5224 /* Error callback will be send during stop flag treatment */
5225 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5226
5227 /* Flush TX register */
5228 I2C_Flush_TXDR(hi2c);
5229 }
5230 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5231 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5232 {
5233 /* Remove RXNE flag on temporary variable as read done */
5234 tmpITFlags &= ~I2C_FLAG_RXNE;
5235
5236 /* Read data from RXDR */
5237 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5238
5239 /* Increment Buffer pointer */
5240 hi2c->pBuffPtr++;
5241
5242 hi2c->XferSize--;
5243 hi2c->XferCount--;
5244 }
5245 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5246 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5247 {
5248 /* Write data to TXDR */
5249 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5250
5251 /* Increment Buffer pointer */
5252 hi2c->pBuffPtr++;
5253
5254 hi2c->XferSize--;
5255 hi2c->XferCount--;
5256 }
5257 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5258 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5259 {
5260 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5261 {
5262 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5263
5264 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5265 {
5266 hi2c->XferSize = MAX_NBYTE_SIZE;
5267 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5268 }
5269 else
5270 {
5271 hi2c->XferSize = hi2c->XferCount;
5272 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5273 {
5274 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5275 hi2c->XferOptions, I2C_NO_STARTSTOP);
5276 }
5277 else
5278 {
5279 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
5280 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5281 }
5282 }
5283 }
5284 else
5285 {
5286 /* Call TxCpltCallback() if no stop mode is set */
5287 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5288 {
5289 /* Call I2C Master Sequential complete process */
5290 I2C_ITMasterSeqCplt(hi2c);
5291 }
5292 else
5293 {
5294 /* Wrong size Status regarding TCR flag event */
5295 /* Call the corresponding callback to inform upper layer of End of Transfer */
5296 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5297 }
5298 }
5299 }
5300 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5301 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5302 {
5303 if (hi2c->XferCount == 0U)
5304 {
5305 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5306 {
5307 /* Generate a stop condition in case of no transfer option */
5308 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5309 {
5310 /* Generate Stop */
5311 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5312 }
5313 else
5314 {
5315 /* Call I2C Master Sequential complete process */
5316 I2C_ITMasterSeqCplt(hi2c);
5317 }
5318 }
5319 }
5320 else
5321 {
5322 /* Wrong size Status regarding TC flag event */
5323 /* Call the corresponding callback to inform upper layer of End of Transfer */
5324 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5325 }
5326 }
5327 else
5328 {
5329 /* Nothing to do */
5330 }
5331
5332 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5333 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5334 {
5335 /* Call I2C Master complete process */
5336 I2C_ITMasterCplt(hi2c, tmpITFlags);
5337 }
5338
5339 /* Process Unlocked */
5340 __HAL_UNLOCK(hi2c);
5341
5342 return HAL_OK;
5343 }
5344
5345 /**
5346 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
5347 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5348 * the configuration information for the specified I2C.
5349 * @param ITFlags Interrupt flags to handle.
5350 * @param ITSources Interrupt sources enabled.
5351 * @retval HAL status
5352 */
I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5353 static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5354 uint32_t ITSources)
5355 {
5356 uint32_t direction = I2C_GENERATE_START_WRITE;
5357 uint32_t tmpITFlags = ITFlags;
5358
5359 /* Process Locked */
5360 __HAL_LOCK(hi2c);
5361
5362 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5363 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5364 {
5365 /* Clear NACK Flag */
5366 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5367
5368 /* Set corresponding Error Code */
5369 /* No need to generate STOP, it is automatically done */
5370 /* Error callback will be send during stop flag treatment */
5371 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5372
5373 /* Flush TX register */
5374 I2C_Flush_TXDR(hi2c);
5375 }
5376 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5377 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5378 {
5379 /* Remove RXNE flag on temporary variable as read done */
5380 tmpITFlags &= ~I2C_FLAG_RXNE;
5381
5382 /* Read data from RXDR */
5383 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5384
5385 /* Increment Buffer pointer */
5386 hi2c->pBuffPtr++;
5387
5388 hi2c->XferSize--;
5389 hi2c->XferCount--;
5390 }
5391 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5392 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5393 {
5394 if (hi2c->Memaddress == 0xFFFFFFFFU)
5395 {
5396 /* Write data to TXDR */
5397 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5398
5399 /* Increment Buffer pointer */
5400 hi2c->pBuffPtr++;
5401
5402 hi2c->XferSize--;
5403 hi2c->XferCount--;
5404 }
5405 else
5406 {
5407 /* Write LSB part of Memory Address */
5408 hi2c->Instance->TXDR = hi2c->Memaddress;
5409
5410 /* Reset Memaddress content */
5411 hi2c->Memaddress = 0xFFFFFFFFU;
5412 }
5413 }
5414 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
5415 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5416 {
5417 if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
5418 {
5419 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5420 {
5421 hi2c->XferSize = MAX_NBYTE_SIZE;
5422 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5423 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5424 }
5425 else
5426 {
5427 hi2c->XferSize = hi2c->XferCount;
5428 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5429 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5430 }
5431 }
5432 else
5433 {
5434 /* Wrong size Status regarding TCR flag event */
5435 /* Call the corresponding callback to inform upper layer of End of Transfer */
5436 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5437 }
5438 }
5439 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
5440 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5441 {
5442 /* Disable Interrupt related to address step */
5443 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5444
5445 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
5446 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
5447
5448 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5449 {
5450 direction = I2C_GENERATE_START_READ;
5451 }
5452
5453 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5454 {
5455 hi2c->XferSize = MAX_NBYTE_SIZE;
5456
5457 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5458 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5459 I2C_RELOAD_MODE, direction);
5460 }
5461 else
5462 {
5463 hi2c->XferSize = hi2c->XferCount;
5464
5465 /* Set NBYTES to write and generate RESTART */
5466 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5467 I2C_AUTOEND_MODE, direction);
5468 }
5469 }
5470 else
5471 {
5472 /* Nothing to do */
5473 }
5474
5475 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5476 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5477 {
5478 /* Call I2C Master complete process */
5479 I2C_ITMasterCplt(hi2c, tmpITFlags);
5480 }
5481
5482 /* Process Unlocked */
5483 __HAL_UNLOCK(hi2c);
5484
5485 return HAL_OK;
5486 }
5487
5488 /**
5489 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
5490 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5491 * the configuration information for the specified I2C.
5492 * @param ITFlags Interrupt flags to handle.
5493 * @param ITSources Interrupt sources enabled.
5494 * @retval HAL status
5495 */
I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5496 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5497 uint32_t ITSources)
5498 {
5499 uint32_t tmpoptions = hi2c->XferOptions;
5500 uint32_t tmpITFlags = ITFlags;
5501
5502 /* Process locked */
5503 __HAL_LOCK(hi2c);
5504
5505 /* Check if STOPF is set */
5506 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
5507 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5508 {
5509 /* Call I2C Slave complete process */
5510 I2C_ITSlaveCplt(hi2c, tmpITFlags);
5511 }
5512
5513 if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
5514 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5515 {
5516 /* Check that I2C transfer finished */
5517 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5518 /* Mean XferCount == 0*/
5519 /* So clear Flag NACKF only */
5520 if (hi2c->XferCount == 0U)
5521 {
5522 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5523 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5524 Warning[Pa134]: left and right operands are identical */
5525 {
5526 /* Call I2C Listen complete process */
5527 I2C_ITListenCplt(hi2c, tmpITFlags);
5528 }
5529 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5530 {
5531 /* Clear NACK Flag */
5532 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5533
5534 /* Flush TX register */
5535 I2C_Flush_TXDR(hi2c);
5536
5537 /* Last Byte is Transmitted */
5538 /* Call I2C Slave Sequential complete process */
5539 I2C_ITSlaveSeqCplt(hi2c);
5540 }
5541 else
5542 {
5543 /* Clear NACK Flag */
5544 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5545 }
5546 }
5547 else
5548 {
5549 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
5550 /* Clear NACK Flag */
5551 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5552
5553 /* Set ErrorCode corresponding to a Non-Acknowledge */
5554 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5555
5556 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
5557 {
5558 /* Call the corresponding callback to inform upper layer of End of Transfer */
5559 I2C_ITError(hi2c, hi2c->ErrorCode);
5560 }
5561 }
5562 }
5563 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
5564 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
5565 {
5566 if (hi2c->XferCount > 0U)
5567 {
5568 /* Read data from RXDR */
5569 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
5570
5571 /* Increment Buffer pointer */
5572 hi2c->pBuffPtr++;
5573
5574 hi2c->XferSize--;
5575 hi2c->XferCount--;
5576 }
5577
5578 if ((hi2c->XferCount == 0U) && \
5579 (tmpoptions != I2C_NO_OPTION_FRAME))
5580 {
5581 /* Call I2C Slave Sequential complete process */
5582 I2C_ITSlaveSeqCplt(hi2c);
5583 }
5584 }
5585 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
5586 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
5587 {
5588 I2C_ITAddrCplt(hi2c, tmpITFlags);
5589 }
5590 else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
5591 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5592 {
5593 /* Write data to TXDR only if XferCount not reach "0" */
5594 /* A TXIS flag can be set, during STOP treatment */
5595 /* Check if all Data have already been sent */
5596 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
5597 if (hi2c->XferCount > 0U)
5598 {
5599 /* Write data to TXDR */
5600 hi2c->Instance->TXDR = *hi2c->pBuffPtr;
5601
5602 /* Increment Buffer pointer */
5603 hi2c->pBuffPtr++;
5604
5605 hi2c->XferCount--;
5606 hi2c->XferSize--;
5607 }
5608 else
5609 {
5610 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
5611 {
5612 /* Last Byte is Transmitted */
5613 /* Call I2C Slave Sequential complete process */
5614 I2C_ITSlaveSeqCplt(hi2c);
5615 }
5616 }
5617 }
5618 else
5619 {
5620 /* Nothing to do */
5621 }
5622
5623 /* Process Unlocked */
5624 __HAL_UNLOCK(hi2c);
5625
5626 return HAL_OK;
5627 }
5628
5629 #if defined(HAL_DMA_MODULE_ENABLED)
5630 /**
5631 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
5632 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5633 * the configuration information for the specified I2C.
5634 * @param ITFlags Interrupt flags to handle.
5635 * @param ITSources Interrupt sources enabled.
5636 * @retval HAL status
5637 */
I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5638 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5639 uint32_t ITSources)
5640 {
5641 uint16_t devaddress;
5642 uint32_t xfermode;
5643
5644 /* Process Locked */
5645 __HAL_LOCK(hi2c);
5646
5647 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5648 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5649 {
5650 /* Clear NACK Flag */
5651 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5652
5653 /* Set corresponding Error Code */
5654 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5655
5656 /* No need to generate STOP, it is automatically done */
5657 /* But enable STOP interrupt, to treat it */
5658 /* Error callback will be send during stop flag treatment */
5659 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5660
5661 /* Flush TX register */
5662 I2C_Flush_TXDR(hi2c);
5663 }
5664 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5665 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5666 {
5667 /* Disable TC interrupt */
5668 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
5669
5670 if (hi2c->XferCount != 0U)
5671 {
5672 /* Recover Slave address */
5673 devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
5674
5675 /* Prepare the new XferSize to transfer */
5676 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5677 {
5678 hi2c->XferSize = MAX_NBYTE_SIZE;
5679 xfermode = I2C_RELOAD_MODE;
5680 }
5681 else
5682 {
5683 hi2c->XferSize = hi2c->XferCount;
5684 if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
5685 {
5686 xfermode = hi2c->XferOptions;
5687 }
5688 else
5689 {
5690 xfermode = I2C_AUTOEND_MODE;
5691 }
5692 }
5693
5694 /* Set the new XferSize in Nbytes register */
5695 I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
5696
5697 /* Update XferCount value */
5698 hi2c->XferCount -= hi2c->XferSize;
5699
5700 /* Enable DMA Request */
5701 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5702 {
5703 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5704 }
5705 else
5706 {
5707 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5708 }
5709 }
5710 else
5711 {
5712 /* Call TxCpltCallback() if no stop mode is set */
5713 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5714 {
5715 /* Call I2C Master Sequential complete process */
5716 I2C_ITMasterSeqCplt(hi2c);
5717 }
5718 else
5719 {
5720 /* Wrong size Status regarding TCR flag event */
5721 /* Call the corresponding callback to inform upper layer of End of Transfer */
5722 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5723 }
5724 }
5725 }
5726 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5727 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5728 {
5729 if (hi2c->XferCount == 0U)
5730 {
5731 if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
5732 {
5733 /* Generate a stop condition in case of no transfer option */
5734 if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
5735 {
5736 /* Generate Stop */
5737 hi2c->Instance->CR2 |= I2C_CR2_STOP;
5738 }
5739 else
5740 {
5741 /* Call I2C Master Sequential complete process */
5742 I2C_ITMasterSeqCplt(hi2c);
5743 }
5744 }
5745 }
5746 else
5747 {
5748 /* Wrong size Status regarding TC flag event */
5749 /* Call the corresponding callback to inform upper layer of End of Transfer */
5750 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5751 }
5752 }
5753 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5754 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5755 {
5756 /* Call I2C Master complete process */
5757 I2C_ITMasterCplt(hi2c, ITFlags);
5758 }
5759 else
5760 {
5761 /* Nothing to do */
5762 }
5763
5764 /* Process Unlocked */
5765 __HAL_UNLOCK(hi2c);
5766
5767 return HAL_OK;
5768 }
5769
5770 /**
5771 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
5772 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5773 * the configuration information for the specified I2C.
5774 * @param ITFlags Interrupt flags to handle.
5775 * @param ITSources Interrupt sources enabled.
5776 * @retval HAL status
5777 */
I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5778 static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5779 uint32_t ITSources)
5780 {
5781 uint32_t direction = I2C_GENERATE_START_WRITE;
5782
5783 /* Process Locked */
5784 __HAL_LOCK(hi2c);
5785
5786 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5787 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5788 {
5789 /* Clear NACK Flag */
5790 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5791
5792 /* Set corresponding Error Code */
5793 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
5794
5795 /* No need to generate STOP, it is automatically done */
5796 /* But enable STOP interrupt, to treat it */
5797 /* Error callback will be send during stop flag treatment */
5798 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
5799
5800 /* Flush TX register */
5801 I2C_Flush_TXDR(hi2c);
5802 }
5803 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
5804 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
5805 {
5806 /* Write LSB part of Memory Address */
5807 hi2c->Instance->TXDR = hi2c->Memaddress;
5808
5809 /* Reset Memaddress content */
5810 hi2c->Memaddress = 0xFFFFFFFFU;
5811 }
5812 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
5813 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5814 {
5815 /* Disable Interrupt related to address step */
5816 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5817
5818 /* Enable only Error interrupt */
5819 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5820
5821 if (hi2c->XferCount != 0U)
5822 {
5823 /* Prepare the new XferSize to transfer */
5824 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5825 {
5826 hi2c->XferSize = MAX_NBYTE_SIZE;
5827 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5828 I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
5829 }
5830 else
5831 {
5832 hi2c->XferSize = hi2c->XferCount;
5833 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5834 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
5835 }
5836
5837 /* Update XferCount value */
5838 hi2c->XferCount -= hi2c->XferSize;
5839
5840 /* Enable DMA Request */
5841 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5842 {
5843 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5844 }
5845 else
5846 {
5847 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5848 }
5849 }
5850 else
5851 {
5852 /* Wrong size Status regarding TCR flag event */
5853 /* Call the corresponding callback to inform upper layer of End of Transfer */
5854 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
5855 }
5856 }
5857 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
5858 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
5859 {
5860 /* Disable Interrupt related to address step */
5861 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
5862
5863 /* Enable only Error and NACK interrupt for data transfer */
5864 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
5865
5866 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5867 {
5868 direction = I2C_GENERATE_START_READ;
5869 }
5870
5871 if (hi2c->XferCount > MAX_NBYTE_SIZE)
5872 {
5873 hi2c->XferSize = MAX_NBYTE_SIZE;
5874
5875 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
5876 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5877 I2C_RELOAD_MODE, direction);
5878 }
5879 else
5880 {
5881 hi2c->XferSize = hi2c->XferCount;
5882
5883 /* Set NBYTES to write and generate RESTART */
5884 I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
5885 I2C_AUTOEND_MODE, direction);
5886 }
5887
5888 /* Update XferCount value */
5889 hi2c->XferCount -= hi2c->XferSize;
5890
5891 /* Enable DMA Request */
5892 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5893 {
5894 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
5895 }
5896 else
5897 {
5898 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
5899 }
5900 }
5901 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5902 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5903 {
5904 /* Call I2C Master complete process */
5905 I2C_ITMasterCplt(hi2c, ITFlags);
5906 }
5907 else
5908 {
5909 /* Nothing to do */
5910 }
5911
5912 /* Process Unlocked */
5913 __HAL_UNLOCK(hi2c);
5914
5915 return HAL_OK;
5916 }
5917
5918 /**
5919 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
5920 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5921 * the configuration information for the specified I2C.
5922 * @param ITFlags Interrupt flags to handle.
5923 * @param ITSources Interrupt sources enabled.
5924 * @retval HAL status
5925 */
I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef * hi2c,uint32_t ITFlags,uint32_t ITSources)5926 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
5927 uint32_t ITSources)
5928 {
5929 uint32_t tmpoptions = hi2c->XferOptions;
5930 uint32_t treatdmanack = 0U;
5931 HAL_I2C_StateTypeDef tmpstate;
5932
5933 /* Process locked */
5934 __HAL_LOCK(hi2c);
5935
5936 /* Check if STOPF is set */
5937 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
5938 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
5939 {
5940 /* Call I2C Slave complete process */
5941 I2C_ITSlaveCplt(hi2c, ITFlags);
5942 }
5943
5944 if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
5945 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
5946 {
5947 /* Check that I2C transfer finished */
5948 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
5949 /* Mean XferCount == 0 */
5950 /* So clear Flag NACKF only */
5951 if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) ||
5952 (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET))
5953 {
5954 /* Split check of hdmarx, for MISRA compliance */
5955 if (hi2c->hdmarx != NULL)
5956 {
5957 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
5958 {
5959 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
5960 {
5961 treatdmanack = 1U;
5962 }
5963 }
5964 }
5965
5966 /* Split check of hdmatx, for MISRA compliance */
5967 if (hi2c->hdmatx != NULL)
5968 {
5969 if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
5970 {
5971 if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
5972 {
5973 treatdmanack = 1U;
5974 }
5975 }
5976 }
5977
5978 if (treatdmanack == 1U)
5979 {
5980 if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
5981 /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
5982 Warning[Pa134]: left and right operands are identical */
5983 {
5984 /* Call I2C Listen complete process */
5985 I2C_ITListenCplt(hi2c, ITFlags);
5986 }
5987 else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
5988 {
5989 /* Clear NACK Flag */
5990 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
5991
5992 /* Flush TX register */
5993 I2C_Flush_TXDR(hi2c);
5994
5995 /* Last Byte is Transmitted */
5996 /* Call I2C Slave Sequential complete process */
5997 I2C_ITSlaveSeqCplt(hi2c);
5998 }
5999 else
6000 {
6001 /* Clear NACK Flag */
6002 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6003 }
6004 }
6005 else
6006 {
6007 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
6008 /* Clear NACK Flag */
6009 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6010
6011 /* Set ErrorCode corresponding to a Non-Acknowledge */
6012 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6013
6014 /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */
6015 tmpstate = hi2c->State;
6016
6017 if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
6018 {
6019 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN))
6020 {
6021 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6022 }
6023 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6024 {
6025 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6026 }
6027 else
6028 {
6029 /* Do nothing */
6030 }
6031
6032 /* Call the corresponding callback to inform upper layer of End of Transfer */
6033 I2C_ITError(hi2c, hi2c->ErrorCode);
6034 }
6035 }
6036 }
6037 else
6038 {
6039 /* Only Clear NACK Flag, no DMA treatment is pending */
6040 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6041 }
6042 }
6043 else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
6044 (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
6045 {
6046 I2C_ITAddrCplt(hi2c, ITFlags);
6047 }
6048 else
6049 {
6050 /* Nothing to do */
6051 }
6052
6053 /* Process Unlocked */
6054 __HAL_UNLOCK(hi2c);
6055
6056 return HAL_OK;
6057 }
6058 #endif /* HAL_DMA_MODULE_ENABLED */
6059
6060 /**
6061 * @brief Master sends target device address followed by internal memory address for write request.
6062 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6063 * the configuration information for the specified I2C.
6064 * @param DevAddress Target device address: The device 7 bits address value
6065 * in datasheet must be shifted to the left before calling the interface
6066 * @param MemAddress Internal memory address
6067 * @param MemAddSize Size of internal memory address
6068 * @param Timeout Timeout duration
6069 * @param Tickstart Tick start value
6070 * @retval HAL status
6071 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6072 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6073 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6074 uint32_t Tickstart)
6075 {
6076 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
6077
6078 /* Wait until TXIS flag is set */
6079 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6080 {
6081 return HAL_ERROR;
6082 }
6083
6084 /* If Memory address size is 8Bit */
6085 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6086 {
6087 /* Send Memory Address */
6088 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6089 }
6090 /* If Memory address size is 16Bit */
6091 else
6092 {
6093 /* Send MSB of Memory Address */
6094 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6095
6096 /* Wait until TXIS flag is set */
6097 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6098 {
6099 return HAL_ERROR;
6100 }
6101
6102 /* Send LSB of Memory Address */
6103 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6104 }
6105
6106 /* Wait until TCR flag is set */
6107 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
6108 {
6109 return HAL_ERROR;
6110 }
6111
6112 return HAL_OK;
6113 }
6114
6115 /**
6116 * @brief Master sends target device address followed by internal memory address for read request.
6117 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6118 * the configuration information for the specified I2C.
6119 * @param DevAddress Target device address: The device 7 bits address value
6120 * in datasheet must be shifted to the left before calling the interface
6121 * @param MemAddress Internal memory address
6122 * @param MemAddSize Size of internal memory address
6123 * @param Timeout Timeout duration
6124 * @param Tickstart Tick start value
6125 * @retval HAL status
6126 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6127 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
6128 uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
6129 uint32_t Tickstart)
6130 {
6131 I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
6132
6133 /* Wait until TXIS flag is set */
6134 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6135 {
6136 return HAL_ERROR;
6137 }
6138
6139 /* If Memory address size is 8Bit */
6140 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6141 {
6142 /* Send Memory Address */
6143 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6144 }
6145 /* If Memory address size is 16Bit */
6146 else
6147 {
6148 /* Send MSB of Memory Address */
6149 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
6150
6151 /* Wait until TXIS flag is set */
6152 if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6153 {
6154 return HAL_ERROR;
6155 }
6156
6157 /* Send LSB of Memory Address */
6158 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
6159 }
6160
6161 /* Wait until TC flag is set */
6162 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
6163 {
6164 return HAL_ERROR;
6165 }
6166
6167 return HAL_OK;
6168 }
6169
6170 /**
6171 * @brief I2C Address complete process callback.
6172 * @param hi2c I2C handle.
6173 * @param ITFlags Interrupt flags to handle.
6174 * @retval None
6175 */
I2C_ITAddrCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6176 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6177 {
6178 uint8_t transferdirection;
6179 uint16_t slaveaddrcode;
6180 uint16_t ownadd1code;
6181 uint16_t ownadd2code;
6182
6183 /* Prevent unused argument(s) compilation warning */
6184 UNUSED(ITFlags);
6185
6186 /* In case of Listen state, need to inform upper layer of address match code event */
6187 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6188 {
6189 transferdirection = I2C_GET_DIR(hi2c);
6190 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
6191 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
6192 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
6193
6194 /* If 10bits addressing mode is selected */
6195 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
6196 {
6197 if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
6198 {
6199 slaveaddrcode = ownadd1code;
6200 hi2c->AddrEventCount++;
6201 if (hi2c->AddrEventCount == 2U)
6202 {
6203 /* Reset Address Event counter */
6204 hi2c->AddrEventCount = 0U;
6205
6206 /* Clear ADDR flag */
6207 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6208
6209 /* Process Unlocked */
6210 __HAL_UNLOCK(hi2c);
6211
6212 /* Call Slave Addr callback */
6213 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6214 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6215 #else
6216 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6217 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6218 }
6219 }
6220 else
6221 {
6222 slaveaddrcode = ownadd2code;
6223
6224 /* Disable ADDR Interrupts */
6225 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6226
6227 /* Process Unlocked */
6228 __HAL_UNLOCK(hi2c);
6229
6230 /* Call Slave Addr callback */
6231 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6232 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6233 #else
6234 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6235 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6236 }
6237 }
6238 /* else 7 bits addressing mode is selected */
6239 else
6240 {
6241 /* Disable ADDR Interrupts */
6242 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
6243
6244 /* Process Unlocked */
6245 __HAL_UNLOCK(hi2c);
6246
6247 /* Call Slave Addr callback */
6248 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6249 hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode);
6250 #else
6251 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
6252 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6253 }
6254 }
6255 /* Else clear address flag only */
6256 else
6257 {
6258 /* Clear ADDR flag */
6259 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
6260
6261 /* Process Unlocked */
6262 __HAL_UNLOCK(hi2c);
6263 }
6264 }
6265
6266 /**
6267 * @brief I2C Master sequential complete process.
6268 * @param hi2c I2C handle.
6269 * @retval None
6270 */
I2C_ITMasterSeqCplt(I2C_HandleTypeDef * hi2c)6271 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c)
6272 {
6273 /* Reset I2C handle mode */
6274 hi2c->Mode = HAL_I2C_MODE_NONE;
6275
6276 /* No Generate Stop, to permit restart mode */
6277 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
6278 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6279 {
6280 hi2c->State = HAL_I2C_STATE_READY;
6281 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6282 hi2c->XferISR = NULL;
6283
6284 /* Disable Interrupts */
6285 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6286
6287 /* Process Unlocked */
6288 __HAL_UNLOCK(hi2c);
6289
6290 /* Call the corresponding callback to inform upper layer of End of Transfer */
6291 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6292 hi2c->MasterTxCpltCallback(hi2c);
6293 #else
6294 HAL_I2C_MasterTxCpltCallback(hi2c);
6295 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6296 }
6297 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6298 else
6299 {
6300 hi2c->State = HAL_I2C_STATE_READY;
6301 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6302 hi2c->XferISR = NULL;
6303
6304 /* Disable Interrupts */
6305 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6306
6307 /* Process Unlocked */
6308 __HAL_UNLOCK(hi2c);
6309
6310 /* Call the corresponding callback to inform upper layer of End of Transfer */
6311 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6312 hi2c->MasterRxCpltCallback(hi2c);
6313 #else
6314 HAL_I2C_MasterRxCpltCallback(hi2c);
6315 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6316 }
6317 }
6318
6319 /**
6320 * @brief I2C Slave sequential complete process.
6321 * @param hi2c I2C handle.
6322 * @retval None
6323 */
I2C_ITSlaveSeqCplt(I2C_HandleTypeDef * hi2c)6324 static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c)
6325 {
6326 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6327
6328 /* Reset I2C handle mode */
6329 hi2c->Mode = HAL_I2C_MODE_NONE;
6330
6331 #if defined(HAL_DMA_MODULE_ENABLED)
6332 /* If a DMA is ongoing, Update handle size context */
6333 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6334 {
6335 /* Disable DMA Request */
6336 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6337 }
6338 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6339 {
6340 /* Disable DMA Request */
6341 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6342 }
6343 else
6344 {
6345 /* Do nothing */
6346 }
6347 #endif /* HAL_DMA_MODULE_ENABLED */
6348
6349 if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
6350 {
6351 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
6352 hi2c->State = HAL_I2C_STATE_LISTEN;
6353 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6354
6355 /* Disable Interrupts */
6356 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6357
6358 /* Process Unlocked */
6359 __HAL_UNLOCK(hi2c);
6360
6361 /* Call the corresponding callback to inform upper layer of End of Transfer */
6362 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6363 hi2c->SlaveTxCpltCallback(hi2c);
6364 #else
6365 HAL_I2C_SlaveTxCpltCallback(hi2c);
6366 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6367 }
6368
6369 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
6370 {
6371 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
6372 hi2c->State = HAL_I2C_STATE_LISTEN;
6373 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6374
6375 /* Disable Interrupts */
6376 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6377
6378 /* Process Unlocked */
6379 __HAL_UNLOCK(hi2c);
6380
6381 /* Call the corresponding callback to inform upper layer of End of Transfer */
6382 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6383 hi2c->SlaveRxCpltCallback(hi2c);
6384 #else
6385 HAL_I2C_SlaveRxCpltCallback(hi2c);
6386 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6387 }
6388 else
6389 {
6390 /* Nothing to do */
6391 }
6392 }
6393
6394 /**
6395 * @brief I2C Master complete process.
6396 * @param hi2c I2C handle.
6397 * @param ITFlags Interrupt flags to handle.
6398 * @retval None
6399 */
I2C_ITMasterCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6400 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6401 {
6402 uint32_t tmperror;
6403 uint32_t tmpITFlags = ITFlags;
6404 __IO uint32_t tmpreg;
6405
6406 /* Clear STOP Flag */
6407 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6408
6409 /* Disable Interrupts and Store Previous state */
6410 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6411 {
6412 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
6413 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
6414 }
6415 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6416 {
6417 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
6418 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
6419 }
6420 else
6421 {
6422 /* Do nothing */
6423 }
6424
6425 /* Clear Configuration Register 2 */
6426 I2C_RESET_CR2(hi2c);
6427
6428 /* Reset handle parameters */
6429 hi2c->XferISR = NULL;
6430 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6431
6432 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET)
6433 {
6434 /* Clear NACK Flag */
6435 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6436
6437 /* Set acknowledge error code */
6438 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6439 }
6440
6441 /* Fetch Last receive data if any */
6442 if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET))
6443 {
6444 /* Read data from RXDR */
6445 tmpreg = (uint8_t)hi2c->Instance->RXDR;
6446 UNUSED(tmpreg);
6447 }
6448
6449 /* Flush TX register */
6450 I2C_Flush_TXDR(hi2c);
6451
6452 /* Store current volatile hi2c->ErrorCode, misra rule */
6453 tmperror = hi2c->ErrorCode;
6454
6455 /* Call the corresponding callback to inform upper layer of End of Transfer */
6456 if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE))
6457 {
6458 /* Call the corresponding callback to inform upper layer of End of Transfer */
6459 I2C_ITError(hi2c, hi2c->ErrorCode);
6460 }
6461 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
6462 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
6463 {
6464 hi2c->State = HAL_I2C_STATE_READY;
6465 hi2c->PreviousState = I2C_STATE_NONE;
6466
6467 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6468 {
6469 hi2c->Mode = HAL_I2C_MODE_NONE;
6470
6471 /* Process Unlocked */
6472 __HAL_UNLOCK(hi2c);
6473
6474 /* Call the corresponding callback to inform upper layer of End of Transfer */
6475 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6476 hi2c->MemTxCpltCallback(hi2c);
6477 #else
6478 HAL_I2C_MemTxCpltCallback(hi2c);
6479 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6480 }
6481 else
6482 {
6483 hi2c->Mode = HAL_I2C_MODE_NONE;
6484
6485 /* Process Unlocked */
6486 __HAL_UNLOCK(hi2c);
6487
6488 /* Call the corresponding callback to inform upper layer of End of Transfer */
6489 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6490 hi2c->MasterTxCpltCallback(hi2c);
6491 #else
6492 HAL_I2C_MasterTxCpltCallback(hi2c);
6493 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6494 }
6495 }
6496 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
6497 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6498 {
6499 hi2c->State = HAL_I2C_STATE_READY;
6500 hi2c->PreviousState = I2C_STATE_NONE;
6501
6502 if (hi2c->Mode == HAL_I2C_MODE_MEM)
6503 {
6504 hi2c->Mode = HAL_I2C_MODE_NONE;
6505
6506 /* Process Unlocked */
6507 __HAL_UNLOCK(hi2c);
6508
6509 /* Call the corresponding callback to inform upper layer of End of Transfer */
6510 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6511 hi2c->MemRxCpltCallback(hi2c);
6512 #else
6513 HAL_I2C_MemRxCpltCallback(hi2c);
6514 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6515 }
6516 else
6517 {
6518 hi2c->Mode = HAL_I2C_MODE_NONE;
6519
6520 /* Process Unlocked */
6521 __HAL_UNLOCK(hi2c);
6522
6523 /* Call the corresponding callback to inform upper layer of End of Transfer */
6524 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6525 hi2c->MasterRxCpltCallback(hi2c);
6526 #else
6527 HAL_I2C_MasterRxCpltCallback(hi2c);
6528 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6529 }
6530 }
6531 else
6532 {
6533 /* Nothing to do */
6534 }
6535 }
6536
6537 /**
6538 * @brief I2C Slave complete process.
6539 * @param hi2c I2C handle.
6540 * @param ITFlags Interrupt flags to handle.
6541 * @retval None
6542 */
I2C_ITSlaveCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6543 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6544 {
6545 uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
6546 uint32_t tmpITFlags = ITFlags;
6547 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6548
6549 /* Clear STOP Flag */
6550 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6551
6552 /* Disable Interrupts and Store Previous state */
6553 if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6554 (tmpstate == HAL_I2C_STATE_LISTEN))
6555 {
6556 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
6557 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6558 }
6559 else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6560 {
6561 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
6562 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6563 }
6564 else
6565 {
6566 /* Do nothing */
6567 }
6568
6569 /* Disable Address Acknowledge */
6570 hi2c->Instance->CR2 |= I2C_CR2_NACK;
6571
6572 /* Clear Configuration Register 2 */
6573 I2C_RESET_CR2(hi2c);
6574
6575 /* Flush TX register */
6576 I2C_Flush_TXDR(hi2c);
6577
6578 #if defined(HAL_DMA_MODULE_ENABLED)
6579 /* If a DMA is ongoing, Update handle size context */
6580 if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET)
6581 {
6582 /* Disable DMA Request */
6583 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6584
6585 if (hi2c->hdmatx != NULL)
6586 {
6587 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
6588 }
6589 }
6590 else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
6591 {
6592 /* Disable DMA Request */
6593 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6594
6595 if (hi2c->hdmarx != NULL)
6596 {
6597 hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
6598 }
6599 }
6600 else
6601 {
6602 /* Do nothing */
6603 }
6604 #endif /* HAL_DMA_MODULE_ENABLED */
6605
6606 /* Store Last receive data if any */
6607 if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
6608 {
6609 /* Remove RXNE flag on temporary variable as read done */
6610 tmpITFlags &= ~I2C_FLAG_RXNE;
6611
6612 /* Read data from RXDR */
6613 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6614
6615 /* Increment Buffer pointer */
6616 hi2c->pBuffPtr++;
6617
6618 if ((hi2c->XferSize > 0U))
6619 {
6620 hi2c->XferSize--;
6621 hi2c->XferCount--;
6622 }
6623 }
6624
6625 /* All data are not transferred, so set error code accordingly */
6626 if (hi2c->XferCount != 0U)
6627 {
6628 /* Set ErrorCode corresponding to a Non-Acknowledge */
6629 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6630 }
6631
6632 hi2c->Mode = HAL_I2C_MODE_NONE;
6633 hi2c->XferISR = NULL;
6634
6635 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6636 {
6637 /* Call the corresponding callback to inform upper layer of End of Transfer */
6638 I2C_ITError(hi2c, hi2c->ErrorCode);
6639
6640 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6641 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6642 {
6643 /* Call I2C Listen complete process */
6644 I2C_ITListenCplt(hi2c, tmpITFlags);
6645 }
6646 }
6647 else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
6648 {
6649 /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
6650 I2C_ITSlaveSeqCplt(hi2c);
6651
6652 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6653 hi2c->State = HAL_I2C_STATE_READY;
6654 hi2c->PreviousState = I2C_STATE_NONE;
6655
6656 /* Process Unlocked */
6657 __HAL_UNLOCK(hi2c);
6658
6659 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6660 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6661 hi2c->ListenCpltCallback(hi2c);
6662 #else
6663 HAL_I2C_ListenCpltCallback(hi2c);
6664 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6665 }
6666 /* Call the corresponding callback to inform upper layer of End of Transfer */
6667 else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
6668 {
6669 hi2c->State = HAL_I2C_STATE_READY;
6670 hi2c->PreviousState = I2C_STATE_NONE;
6671
6672 /* Process Unlocked */
6673 __HAL_UNLOCK(hi2c);
6674
6675 /* Call the corresponding callback to inform upper layer of End of Transfer */
6676 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6677 hi2c->SlaveRxCpltCallback(hi2c);
6678 #else
6679 HAL_I2C_SlaveRxCpltCallback(hi2c);
6680 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6681 }
6682 else
6683 {
6684 hi2c->State = HAL_I2C_STATE_READY;
6685 hi2c->PreviousState = I2C_STATE_NONE;
6686
6687 /* Process Unlocked */
6688 __HAL_UNLOCK(hi2c);
6689
6690 /* Call the corresponding callback to inform upper layer of End of Transfer */
6691 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6692 hi2c->SlaveTxCpltCallback(hi2c);
6693 #else
6694 HAL_I2C_SlaveTxCpltCallback(hi2c);
6695 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6696 }
6697 }
6698
6699 /**
6700 * @brief I2C Listen complete process.
6701 * @param hi2c I2C handle.
6702 * @param ITFlags Interrupt flags to handle.
6703 * @retval None
6704 */
I2C_ITListenCplt(I2C_HandleTypeDef * hi2c,uint32_t ITFlags)6705 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
6706 {
6707 /* Reset handle parameters */
6708 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6709 hi2c->PreviousState = I2C_STATE_NONE;
6710 hi2c->State = HAL_I2C_STATE_READY;
6711 hi2c->Mode = HAL_I2C_MODE_NONE;
6712 hi2c->XferISR = NULL;
6713
6714 /* Store Last receive data if any */
6715 if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
6716 {
6717 /* Read data from RXDR */
6718 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
6719
6720 /* Increment Buffer pointer */
6721 hi2c->pBuffPtr++;
6722
6723 if ((hi2c->XferSize > 0U))
6724 {
6725 hi2c->XferSize--;
6726 hi2c->XferCount--;
6727
6728 /* Set ErrorCode corresponding to a Non-Acknowledge */
6729 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6730 }
6731 }
6732
6733 /* Disable all Interrupts*/
6734 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6735
6736 /* Clear NACK Flag */
6737 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6738
6739 /* Process Unlocked */
6740 __HAL_UNLOCK(hi2c);
6741
6742 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6743 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6744 hi2c->ListenCpltCallback(hi2c);
6745 #else
6746 HAL_I2C_ListenCpltCallback(hi2c);
6747 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6748 }
6749
6750 /**
6751 * @brief I2C interrupts error process.
6752 * @param hi2c I2C handle.
6753 * @param ErrorCode Error code to handle.
6754 * @retval None
6755 */
I2C_ITError(I2C_HandleTypeDef * hi2c,uint32_t ErrorCode)6756 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
6757 {
6758 HAL_I2C_StateTypeDef tmpstate = hi2c->State;
6759
6760 #if defined(HAL_DMA_MODULE_ENABLED)
6761 uint32_t tmppreviousstate;
6762 #endif /* HAL_DMA_MODULE_ENABLED */
6763
6764 /* Reset handle parameters */
6765 hi2c->Mode = HAL_I2C_MODE_NONE;
6766 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6767 hi2c->XferCount = 0U;
6768
6769 /* Set new error code */
6770 hi2c->ErrorCode |= ErrorCode;
6771
6772 /* Disable Interrupts */
6773 if ((tmpstate == HAL_I2C_STATE_LISTEN) ||
6774 (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
6775 (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN))
6776 {
6777 /* Disable all interrupts, except interrupts related to LISTEN state */
6778 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6779
6780 /* keep HAL_I2C_STATE_LISTEN if set */
6781 hi2c->State = HAL_I2C_STATE_LISTEN;
6782 hi2c->XferISR = I2C_Slave_ISR_IT;
6783 }
6784 else
6785 {
6786 /* Disable all interrupts */
6787 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
6788
6789 /* Flush TX register */
6790 I2C_Flush_TXDR(hi2c);
6791
6792 /* If state is an abort treatment on going, don't change state */
6793 /* This change will be do later */
6794 if (hi2c->State != HAL_I2C_STATE_ABORT)
6795 {
6796 /* Set HAL_I2C_STATE_READY */
6797 hi2c->State = HAL_I2C_STATE_READY;
6798
6799 /* Check if a STOPF is detected */
6800 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
6801 {
6802 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
6803 {
6804 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6805 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6806 }
6807
6808 /* Clear STOP Flag */
6809 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
6810 }
6811
6812 }
6813 hi2c->XferISR = NULL;
6814 }
6815
6816 #if defined(HAL_DMA_MODULE_ENABLED)
6817 /* Abort DMA TX transfer if any */
6818 tmppreviousstate = hi2c->PreviousState;
6819
6820 if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
6821 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
6822 {
6823 if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
6824 {
6825 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6826 }
6827
6828 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6829 {
6830 /* Set the I2C DMA Abort callback :
6831 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6832 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6833
6834 /* Process Unlocked */
6835 __HAL_UNLOCK(hi2c);
6836
6837 /* Abort DMA TX */
6838 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6839 {
6840 /* Call Directly XferAbortCallback function in case of error */
6841 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6842 }
6843 }
6844 else
6845 {
6846 I2C_TreatErrorCallback(hi2c);
6847 }
6848 }
6849 /* Abort DMA RX transfer if any */
6850 else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
6851 (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
6852 {
6853 if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
6854 {
6855 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
6856 }
6857
6858 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6859 {
6860 /* Set the I2C DMA Abort callback :
6861 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6862 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6863
6864 /* Process Unlocked */
6865 __HAL_UNLOCK(hi2c);
6866
6867 /* Abort DMA RX */
6868 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6869 {
6870 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6871 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6872 }
6873 }
6874 else
6875 {
6876 I2C_TreatErrorCallback(hi2c);
6877 }
6878 }
6879 else
6880 #endif /* HAL_DMA_MODULE_ENABLED */
6881 {
6882 I2C_TreatErrorCallback(hi2c);
6883 }
6884 }
6885
6886 /**
6887 * @brief I2C Error callback treatment.
6888 * @param hi2c I2C handle.
6889 * @retval None
6890 */
I2C_TreatErrorCallback(I2C_HandleTypeDef * hi2c)6891 static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c)
6892 {
6893 if (hi2c->State == HAL_I2C_STATE_ABORT)
6894 {
6895 hi2c->State = HAL_I2C_STATE_READY;
6896 hi2c->PreviousState = I2C_STATE_NONE;
6897
6898 /* Process Unlocked */
6899 __HAL_UNLOCK(hi2c);
6900
6901 /* Call the corresponding callback to inform upper layer of End of Transfer */
6902 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6903 hi2c->AbortCpltCallback(hi2c);
6904 #else
6905 HAL_I2C_AbortCpltCallback(hi2c);
6906 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6907 }
6908 else
6909 {
6910 hi2c->PreviousState = I2C_STATE_NONE;
6911
6912 /* Process Unlocked */
6913 __HAL_UNLOCK(hi2c);
6914
6915 /* Call the corresponding callback to inform upper layer of End of Transfer */
6916 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6917 hi2c->ErrorCallback(hi2c);
6918 #else
6919 HAL_I2C_ErrorCallback(hi2c);
6920 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6921 }
6922 }
6923
6924 /**
6925 * @brief I2C Tx data register flush process.
6926 * @param hi2c I2C handle.
6927 * @retval None
6928 */
I2C_Flush_TXDR(I2C_HandleTypeDef * hi2c)6929 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
6930 {
6931 /* If a pending TXIS flag is set */
6932 /* Write a dummy data in TXDR to clear it */
6933 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
6934 {
6935 hi2c->Instance->TXDR = 0x00U;
6936 }
6937
6938 /* Flush TX register if not empty */
6939 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
6940 {
6941 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
6942 }
6943 }
6944
6945 #if defined(HAL_DMA_MODULE_ENABLED)
6946 /**
6947 * @brief DMA I2C master transmit process complete callback.
6948 * @param hdma DMA handle
6949 * @retval None
6950 */
I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef * hdma)6951 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
6952 {
6953 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
6954 /* Derogation MISRAC2012-Rule-11.5 */
6955 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
6956
6957 /* Disable DMA Request */
6958 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
6959
6960 /* If last transfer, enable STOP interrupt */
6961 if (hi2c->XferCount == 0U)
6962 {
6963 /* Enable STOP interrupt */
6964 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
6965 }
6966 /* else prepare a new DMA transfer and enable TCReload interrupt */
6967 else
6968 {
6969 /* Update Buffer pointer */
6970 hi2c->pBuffPtr += hi2c->XferSize;
6971
6972 /* Set the XferSize to transfer */
6973 if (hi2c->XferCount > MAX_NBYTE_SIZE)
6974 {
6975 hi2c->XferSize = MAX_NBYTE_SIZE;
6976 }
6977 else
6978 {
6979 hi2c->XferSize = hi2c->XferCount;
6980 }
6981
6982 /* Enable the DMA channel */
6983 if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
6984 {
6985 if (hi2c->hdmatx->LinkedListQueue != NULL)
6986 {
6987 /* Set DMA data size */
6988 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
6989
6990 /* Set DMA source address */
6991 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
6992
6993 /* Set DMA destination address */
6994 hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR;
6995
6996 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx);
6997 }
6998 else
6999 {
7000 /* Call the corresponding callback to inform upper layer of End of Transfer */
7001 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7002 }
7003 }
7004 else
7005 {
7006 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
7007 hi2c->XferSize);
7008 }
7009
7010 if (dmaxferstatus != HAL_OK)
7011 {
7012 /* Call the corresponding callback to inform upper layer of End of Transfer */
7013 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7014 }
7015 else
7016 {
7017 /* Enable TC interrupts */
7018 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7019 }
7020 }
7021 }
7022
7023
7024 /**
7025 * @brief DMA I2C slave transmit process complete callback.
7026 * @param hdma DMA handle
7027 * @retval None
7028 */
I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef * hdma)7029 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
7030 {
7031 /* Derogation MISRAC2012-Rule-11.5 */
7032 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7033 uint32_t tmpoptions = hi2c->XferOptions;
7034
7035 if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
7036 {
7037 /* Disable DMA Request */
7038 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
7039
7040 /* Last Byte is Transmitted */
7041 /* Call I2C Slave Sequential complete process */
7042 I2C_ITSlaveSeqCplt(hi2c);
7043 }
7044 else
7045 {
7046 /* No specific action, Master fully manage the generation of STOP condition */
7047 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7048 /* So STOP condition should be manage through Interrupt treatment */
7049 }
7050 }
7051
7052
7053 /**
7054 * @brief DMA I2C master receive process complete callback.
7055 * @param hdma DMA handle
7056 * @retval None
7057 */
I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef * hdma)7058 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
7059 {
7060 HAL_StatusTypeDef dmaxferstatus = HAL_OK;
7061 /* Derogation MISRAC2012-Rule-11.5 */
7062 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7063
7064 /* Disable DMA Request */
7065 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7066
7067 /* If last transfer, enable STOP interrupt */
7068 if (hi2c->XferCount == 0U)
7069 {
7070 /* Enable STOP interrupt */
7071 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
7072 }
7073 /* else prepare a new DMA transfer and enable TCReload interrupt */
7074 else
7075 {
7076 /* Update Buffer pointer */
7077 hi2c->pBuffPtr += hi2c->XferSize;
7078
7079 /* Set the XferSize to transfer */
7080 if (hi2c->XferCount > MAX_NBYTE_SIZE)
7081 {
7082 hi2c->XferSize = MAX_NBYTE_SIZE;
7083 }
7084 else
7085 {
7086 hi2c->XferSize = hi2c->XferCount;
7087 }
7088
7089 /* Enable the DMA channel */
7090 if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
7091 {
7092 if (hi2c->hdmarx->LinkedListQueue != NULL)
7093 {
7094 /* Set DMA data size */
7095 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize;
7096
7097 /* Set DMA source address */
7098 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR;
7099
7100 /* Set DMA destination address */
7101 hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr;
7102
7103 dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx);
7104 }
7105 else
7106 {
7107 /* Call the corresponding callback to inform upper layer of End of Transfer */
7108 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7109 }
7110 }
7111 else
7112 {
7113 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
7114 hi2c->XferSize);
7115 }
7116
7117 if (dmaxferstatus != HAL_OK)
7118 {
7119 /* Call the corresponding callback to inform upper layer of End of Transfer */
7120 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7121 }
7122 else
7123 {
7124 /* Enable TC interrupts */
7125 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
7126 }
7127 }
7128 }
7129
7130
7131 /**
7132 * @brief DMA I2C slave receive process complete callback.
7133 * @param hdma DMA handle
7134 * @retval None
7135 */
I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef * hdma)7136 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
7137 {
7138 /* Derogation MISRAC2012-Rule-11.5 */
7139 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7140 uint32_t tmpoptions = hi2c->XferOptions;
7141
7142 if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
7143 (tmpoptions != I2C_NO_OPTION_FRAME))
7144 {
7145 /* Disable DMA Request */
7146 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
7147
7148 /* Call I2C Slave Sequential complete process */
7149 I2C_ITSlaveSeqCplt(hi2c);
7150 }
7151 else
7152 {
7153 /* No specific action, Master fully manage the generation of STOP condition */
7154 /* Mean that this generation can arrive at any time, at the end or during DMA process */
7155 /* So STOP condition should be manage through Interrupt treatment */
7156 }
7157 }
7158
7159
7160 /**
7161 * @brief DMA I2C communication error callback.
7162 * @param hdma DMA handle
7163 * @retval None
7164 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7165 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7166 {
7167 /* Derogation MISRAC2012-Rule-11.5 */
7168 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7169
7170 /* Disable Acknowledge */
7171 hi2c->Instance->CR2 |= I2C_CR2_NACK;
7172
7173 /* Call the corresponding callback to inform upper layer of End of Transfer */
7174 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
7175 }
7176
7177
7178 /**
7179 * @brief DMA I2C communication abort callback
7180 * (To be called at end of DMA Abort procedure).
7181 * @param hdma DMA handle.
7182 * @retval None
7183 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7184 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7185 {
7186 /* Derogation MISRAC2012-Rule-11.5 */
7187 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
7188
7189 /* Reset AbortCpltCallback */
7190 if (hi2c->hdmatx != NULL)
7191 {
7192 hi2c->hdmatx->XferAbortCallback = NULL;
7193 }
7194 if (hi2c->hdmarx != NULL)
7195 {
7196 hi2c->hdmarx->XferAbortCallback = NULL;
7197 }
7198
7199 I2C_TreatErrorCallback(hi2c);
7200 }
7201
7202 #endif /* HAL_DMA_MODULE_ENABLED */
7203
7204 /**
7205 * @brief This function handles I2C Communication Timeout. It waits
7206 * until a flag is no longer in the specified status.
7207 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7208 * the configuration information for the specified I2C.
7209 * @param Flag Specifies the I2C flag to check.
7210 * @param Status The actual Flag status (SET or RESET).
7211 * @param Timeout Timeout duration
7212 * @param Tickstart Tick start value
7213 * @retval HAL status
7214 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7215 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
7216 uint32_t Timeout, uint32_t Tickstart)
7217 {
7218 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7219 {
7220 /* Check for the Timeout */
7221 if (Timeout != HAL_MAX_DELAY)
7222 {
7223 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7224 {
7225 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7226 {
7227 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7228 hi2c->State = HAL_I2C_STATE_READY;
7229 hi2c->Mode = HAL_I2C_MODE_NONE;
7230
7231 /* Process Unlocked */
7232 __HAL_UNLOCK(hi2c);
7233 return HAL_ERROR;
7234 }
7235 }
7236 }
7237 }
7238 return HAL_OK;
7239 }
7240
7241 /**
7242 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
7243 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7244 * the configuration information for the specified I2C.
7245 * @param Timeout Timeout duration
7246 * @param Tickstart Tick start value
7247 * @retval HAL status
7248 */
I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7249 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7250 uint32_t Tickstart)
7251 {
7252 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
7253 {
7254 /* Check if an error is detected */
7255 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7256 {
7257 return HAL_ERROR;
7258 }
7259
7260 /* Check for the Timeout */
7261 if (Timeout != HAL_MAX_DELAY)
7262 {
7263 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7264 {
7265 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
7266 {
7267 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7268 hi2c->State = HAL_I2C_STATE_READY;
7269 hi2c->Mode = HAL_I2C_MODE_NONE;
7270
7271 /* Process Unlocked */
7272 __HAL_UNLOCK(hi2c);
7273
7274 return HAL_ERROR;
7275 }
7276 }
7277 }
7278 }
7279 return HAL_OK;
7280 }
7281
7282 /**
7283 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7284 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7285 * the configuration information for the specified I2C.
7286 * @param Timeout Timeout duration
7287 * @param Tickstart Tick start value
7288 * @retval HAL status
7289 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7290 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7291 uint32_t Tickstart)
7292 {
7293 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7294 {
7295 /* Check if an error is detected */
7296 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7297 {
7298 return HAL_ERROR;
7299 }
7300
7301 /* Check for the Timeout */
7302 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7303 {
7304 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7305 {
7306 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7307 hi2c->State = HAL_I2C_STATE_READY;
7308 hi2c->Mode = HAL_I2C_MODE_NONE;
7309
7310 /* Process Unlocked */
7311 __HAL_UNLOCK(hi2c);
7312
7313 return HAL_ERROR;
7314 }
7315 }
7316 }
7317 return HAL_OK;
7318 }
7319
7320 /**
7321 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7322 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7323 * the configuration information for the specified I2C.
7324 * @param Timeout Timeout duration
7325 * @param Tickstart Tick start value
7326 * @retval HAL status
7327 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7328 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
7329 uint32_t Tickstart)
7330 {
7331 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7332 {
7333 /* Check if an error is detected */
7334 if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
7335 {
7336 return HAL_ERROR;
7337 }
7338
7339 /* Check if a STOPF is detected */
7340 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7341 {
7342 /* Check if an RXNE is pending */
7343 /* Store Last receive data if any */
7344 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
7345 {
7346 /* Return HAL_OK */
7347 /* The Reading of data from RXDR will be done in caller function */
7348 return HAL_OK;
7349 }
7350 else
7351 {
7352 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7353 {
7354 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7355 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
7356 }
7357 else
7358 {
7359 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7360 }
7361
7362 /* Clear STOP Flag */
7363 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7364
7365 /* Clear Configuration Register 2 */
7366 I2C_RESET_CR2(hi2c);
7367
7368 hi2c->State = HAL_I2C_STATE_READY;
7369 hi2c->Mode = HAL_I2C_MODE_NONE;
7370
7371 /* Process Unlocked */
7372 __HAL_UNLOCK(hi2c);
7373
7374 return HAL_ERROR;
7375 }
7376 }
7377
7378 /* Check for the Timeout */
7379 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7380 {
7381 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7382 {
7383 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7384 hi2c->State = HAL_I2C_STATE_READY;
7385
7386 /* Process Unlocked */
7387 __HAL_UNLOCK(hi2c);
7388
7389 return HAL_ERROR;
7390 }
7391 }
7392 }
7393 return HAL_OK;
7394 }
7395
7396 /**
7397 * @brief This function handles errors detection during an I2C Communication.
7398 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7399 * the configuration information for the specified I2C.
7400 * @param Timeout Timeout duration
7401 * @param Tickstart Tick start value
7402 * @retval HAL status
7403 */
I2C_IsErrorOccurred(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7404 static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7405 {
7406 HAL_StatusTypeDef status = HAL_OK;
7407 uint32_t itflag = hi2c->Instance->ISR;
7408 uint32_t error_code = 0;
7409 uint32_t tickstart = Tickstart;
7410 uint32_t tmp1;
7411 HAL_I2C_ModeTypeDef tmp2;
7412
7413 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
7414 {
7415 /* Clear NACKF Flag */
7416 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7417
7418 /* Wait until STOP Flag is set or timeout occurred */
7419 /* AutoEnd should be initiate after AF */
7420 while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
7421 {
7422 /* Check for the Timeout */
7423 if (Timeout != HAL_MAX_DELAY)
7424 {
7425 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7426 {
7427 tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
7428 tmp2 = hi2c->Mode;
7429
7430 /* In case of I2C still busy, try to regenerate a STOP manually */
7431 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
7432 (tmp1 != I2C_CR2_STOP) && \
7433 (tmp2 != HAL_I2C_MODE_SLAVE))
7434 {
7435 /* Generate Stop */
7436 hi2c->Instance->CR2 |= I2C_CR2_STOP;
7437
7438 /* Update Tick with new reference */
7439 tickstart = HAL_GetTick();
7440 }
7441
7442 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7443 {
7444 /* Check for the Timeout */
7445 if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
7446 {
7447 error_code |= HAL_I2C_ERROR_TIMEOUT;
7448
7449 status = HAL_ERROR;
7450
7451 break;
7452 }
7453 }
7454 }
7455 }
7456 }
7457
7458 /* In case STOP Flag is detected, clear it */
7459 if (status == HAL_OK)
7460 {
7461 /* Clear STOP Flag */
7462 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7463 }
7464
7465 error_code |= HAL_I2C_ERROR_AF;
7466
7467 status = HAL_ERROR;
7468 }
7469
7470 /* Refresh Content of Status register */
7471 itflag = hi2c->Instance->ISR;
7472
7473 /* Then verify if an additional errors occurs */
7474 /* Check if a Bus error occurred */
7475 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
7476 {
7477 error_code |= HAL_I2C_ERROR_BERR;
7478
7479 /* Clear BERR flag */
7480 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
7481
7482 status = HAL_ERROR;
7483 }
7484
7485 /* Check if an Over-Run/Under-Run error occurred */
7486 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
7487 {
7488 error_code |= HAL_I2C_ERROR_OVR;
7489
7490 /* Clear OVR flag */
7491 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
7492
7493 status = HAL_ERROR;
7494 }
7495
7496 /* Check if an Arbitration Loss error occurred */
7497 if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
7498 {
7499 error_code |= HAL_I2C_ERROR_ARLO;
7500
7501 /* Clear ARLO flag */
7502 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
7503
7504 status = HAL_ERROR;
7505 }
7506
7507 if (status != HAL_OK)
7508 {
7509 /* Flush TX register */
7510 I2C_Flush_TXDR(hi2c);
7511
7512 /* Clear Configuration Register 2 */
7513 I2C_RESET_CR2(hi2c);
7514
7515 hi2c->ErrorCode |= error_code;
7516 hi2c->State = HAL_I2C_STATE_READY;
7517 hi2c->Mode = HAL_I2C_MODE_NONE;
7518
7519 /* Process Unlocked */
7520 __HAL_UNLOCK(hi2c);
7521 }
7522
7523 return status;
7524 }
7525
7526 /**
7527 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
7528 * @param hi2c I2C handle.
7529 * @param DevAddress Specifies the slave address to be programmed.
7530 * @param Size Specifies the number of bytes to be programmed.
7531 * This parameter must be a value between 0 and 255.
7532 * @param Mode New state of the I2C START condition generation.
7533 * This parameter can be one of the following values:
7534 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
7535 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
7536 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
7537 * @param Request New state of the I2C START condition generation.
7538 * This parameter can be one of the following values:
7539 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
7540 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
7541 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
7542 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
7543 * @retval None
7544 */
I2C_TransferConfig(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t Size,uint32_t Mode,uint32_t Request)7545 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
7546 uint32_t Request)
7547 {
7548 /* Check the parameters */
7549 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
7550 assert_param(IS_TRANSFER_MODE(Mode));
7551 assert_param(IS_TRANSFER_REQUEST(Request));
7552
7553 /* Declaration of tmp to prevent undefined behavior of volatile usage */
7554 uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
7555 (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
7556 (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
7557
7558 /* update CR2 register */
7559 MODIFY_REG(hi2c->Instance->CR2, \
7560 ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
7561 (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
7562 I2C_CR2_START | I2C_CR2_STOP)), tmp);
7563 }
7564
7565 /**
7566 * @brief Manage the enabling of Interrupts.
7567 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7568 * the configuration information for the specified I2C.
7569 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7570 * @retval None
7571 */
I2C_Enable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7572 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7573 {
7574 uint32_t tmpisr = 0U;
7575
7576 #if defined(HAL_DMA_MODULE_ENABLED)
7577 if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
7578 (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
7579 (hi2c->XferISR != I2C_Mem_ISR_DMA))
7580 #endif /* HAL_DMA_MODULE_ENABLED */
7581 {
7582 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7583 {
7584 /* Enable ERR, STOP, NACK and ADDR interrupts */
7585 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7586 }
7587
7588 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7589 {
7590 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7591 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7592 }
7593
7594 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7595 {
7596 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7597 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7598 }
7599
7600 if (InterruptRequest == I2C_XFER_ERROR_IT)
7601 {
7602 /* Enable ERR and NACK interrupts */
7603 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7604 }
7605
7606 if (InterruptRequest == I2C_XFER_CPLT_IT)
7607 {
7608 /* Enable STOP interrupts */
7609 tmpisr |= I2C_IT_STOPI;
7610 }
7611 }
7612
7613 #if defined(HAL_DMA_MODULE_ENABLED)
7614 else
7615 {
7616 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7617 {
7618 /* Enable ERR, STOP, NACK and ADDR interrupts */
7619 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7620 }
7621
7622 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7623 {
7624 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
7625 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
7626 }
7627
7628 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7629 {
7630 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
7631 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
7632 }
7633
7634 if (InterruptRequest == I2C_XFER_ERROR_IT)
7635 {
7636 /* Enable ERR and NACK interrupts */
7637 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7638 }
7639
7640 if (InterruptRequest == I2C_XFER_CPLT_IT)
7641 {
7642 /* Enable STOP interrupts */
7643 tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
7644 }
7645
7646 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7647 {
7648 /* Enable TC interrupts */
7649 tmpisr |= I2C_IT_TCI;
7650 }
7651 }
7652 #endif /* HAL_DMA_MODULE_ENABLED */
7653
7654 /* Enable interrupts only at the end */
7655 /* to avoid the risk of I2C interrupt handle execution before */
7656 /* all interrupts requested done */
7657 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
7658 }
7659
7660 /**
7661 * @brief Manage the disabling of Interrupts.
7662 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7663 * the configuration information for the specified I2C.
7664 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
7665 * @retval None
7666 */
I2C_Disable_IRQ(I2C_HandleTypeDef * hi2c,uint16_t InterruptRequest)7667 static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
7668 {
7669 uint32_t tmpisr = 0U;
7670
7671 if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
7672 {
7673 /* Disable TC and TXI interrupts */
7674 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
7675
7676 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7677 {
7678 /* Disable NACK and STOP interrupts */
7679 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7680 }
7681 }
7682
7683 if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
7684 {
7685 /* Disable TC and RXI interrupts */
7686 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
7687
7688 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN)
7689 {
7690 /* Disable NACK and STOP interrupts */
7691 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7692 }
7693 }
7694
7695 if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
7696 {
7697 /* Disable ADDR, NACK and STOP interrupts */
7698 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
7699 }
7700
7701 if (InterruptRequest == I2C_XFER_ERROR_IT)
7702 {
7703 /* Enable ERR and NACK interrupts */
7704 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
7705 }
7706
7707 if (InterruptRequest == I2C_XFER_CPLT_IT)
7708 {
7709 /* Enable STOP interrupts */
7710 tmpisr |= I2C_IT_STOPI;
7711 }
7712
7713 if (InterruptRequest == I2C_XFER_RELOAD_IT)
7714 {
7715 /* Enable TC interrupts */
7716 tmpisr |= I2C_IT_TCI;
7717 }
7718
7719 /* Disable interrupts only at the end */
7720 /* to avoid a breaking situation like at "t" time */
7721 /* all disable interrupts request are not done */
7722 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
7723 }
7724
7725 /**
7726 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7727 * @param hi2c I2C handle.
7728 * @retval None
7729 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7730 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7731 {
7732 /* if user set XferOptions to I2C_OTHER_FRAME */
7733 /* it request implicitly to generate a restart condition */
7734 /* set XferOptions to I2C_FIRST_FRAME */
7735 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7736 {
7737 hi2c->XferOptions = I2C_FIRST_FRAME;
7738 }
7739 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7740 /* it request implicitly to generate a restart condition */
7741 /* then generate a stop condition at the end of transfer */
7742 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7743 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7744 {
7745 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7746 }
7747 else
7748 {
7749 /* Nothing to do */
7750 }
7751 }
7752
7753 /**
7754 * @}
7755 */
7756
7757 #endif /* HAL_I2C_MODULE_ENABLED */
7758 /**
7759 * @}
7760 */
7761
7762 /**
7763 * @}
7764 */
7765
