1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @brief Extended RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities RCC extension peripheral:
8 * + Extended Peripheral Control functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2019 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32mp1xx_hal.h"
25
26 /** @addtogroup STM32MP1xx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup RCCEx RCCEx
31 * @brief RCC HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_RCC_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 #define LSE_MASK (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)
39 /* Private defines -----------------------------------------------------------*/
40 /* Private macros ------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private function prototypes -----------------------------------------------*/
43 /** @defgroup RCCEx_Private_Function_Prototypes RCCEx Private Functions Prototypes
44 * @{
45 */
46
47 /**
48 * @}
49 */
50
51 /* Exported functions --------------------------------------------------------*/
52
53 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
54 * @{
55 */
56
57 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
58 * @brief Extended Peripheral Control functions
59 *
60 @verbatim
61 ===============================================================================
62 ##### Extended Peripheral Control functions #####
63 ===============================================================================
64 [..]
65 This subsection provides a set of functions allowing to control the RCC Clocks
66 frequencies.
67 [..]
68 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
69 select the RTC clock source; in this case the Backup domain will be reset in
70 order to modify the RTC Clock source, as consequence RTC registers (including
71 the backup registers) and RCC_BDCR register are set to their reset values.
72
73 @endverbatim
74 * @{
75 */
76 /**
77 * @brief Configures PLL2
78 * @param pll2: pointer to an RCC_PLLInitTypeDef structure
79 *
80 * @retval HAL status
81 */
82
RCCEx_PLL2_Config(RCC_PLLInitTypeDef * pll2)83 HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLLInitTypeDef *pll2)
84 {
85 uint32_t tickstart;
86
87 /* Check the parameters */
88 assert_param(IS_RCC_PLL(pll2->PLLState));
89 if ((pll2->PLLState) != RCC_PLL_NONE)
90 {
91 /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
92 if (!__IS_PLL2_IN_USE()) /* If not used then */
93 {
94 if ((pll2->PLLState) == RCC_PLL_ON)
95 {
96 /* Check the parameters */
97 assert_param(IS_RCC_PLLMODE(pll2->PLLMODE));
98 assert_param(IS_RCC_PLL12SOURCE(pll2->PLLSource));
99 assert_param(IS_RCC_PLLM2_VALUE(pll2->PLLM));
100 if (pll2->PLLMODE == RCC_PLL_FRACTIONAL)
101 {
102 assert_param(IS_RCC_PLLN2_FRAC_VALUE(pll2->PLLN));
103 }
104 else
105 {
106 assert_param(IS_RCC_PLLN2_INT_VALUE(pll2->PLLN));
107 }
108 assert_param(IS_RCC_PLLP2_VALUE(pll2->PLLP));
109 assert_param(IS_RCC_PLLQ2_VALUE(pll2->PLLQ));
110 assert_param(IS_RCC_PLLR2_VALUE(pll2->PLLR));
111
112 /* Check that PLL2 OSC clock source is already set */
113 if ((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) &&
114 (__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSE))
115 {
116 return HAL_ERROR;
117 }
118
119 /*Disable the post-dividers*/
120 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
121 /* Disable the main PLL. */
122 __HAL_RCC_PLL2_DISABLE();
123
124 /* Get Start Tick*/
125 tickstart = HAL_GetTick();
126
127 /* Wait till PLL is ready */
128 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
129 {
130 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
131 {
132 return HAL_TIMEOUT;
133 }
134 }
135
136 /*The PLL configuration below must be done before enabling the PLL:
137 -Selection of PLL clock entry (HSI or HSE)
138 -Frequency input range (PLLxRGE)
139 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
140 Once the PLL is enabled, these parameters can not be changed.
141 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
142 PLLxRDY flag to be at 0.
143 The PLL configuration below can be done at any time:
144 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
145 -Fractional Division Enable (PLLxFRACNEN)
146 -Fractional Division factor (FRACNx)*/
147
148 /* Do not change pll src if already in use */
149 if (__IS_PLL1_IN_USE())
150 {
151 if (pll2->PLLSource != __HAL_RCC_GET_PLL12_SOURCE())
152 {
153 return HAL_ERROR;
154 }
155 }
156 else
157 {
158 /* Configure PLL1 and PLL2 clock source */
159 __HAL_RCC_PLL12_SOURCE(pll2->PLLSource);
160 }
161
162 /* Configure the PLL2 multiplication and division factors. */
163 __HAL_RCC_PLL2_CONFIG(
164 pll2->PLLM,
165 pll2->PLLN,
166 pll2->PLLP,
167 pll2->PLLQ,
168 pll2->PLLR);
169
170
171 /* Configure the Fractional Divider */
172 __HAL_RCC_PLL2FRACV_DISABLE(); //Set FRACLE to ‘0’
173 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
174 if ((pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll2->PLLMODE == RCC_PLL_INTEGER))
175 {
176 /* Do not use the fractional divider */
177 __HAL_RCC_PLL2FRACV_CONFIG(0); //Set FRACV to '0'
178 }
179 else
180 {
181 /* Configure PLL PLL2FRACV in fractional mode*/
182 __HAL_RCC_PLL2FRACV_CONFIG(pll2->PLLFRACV);
183 }
184 __HAL_RCC_PLL2FRACV_ENABLE(); //Set FRACLE to ‘1’
185
186
187 /* Configure the Spread Control */
188 if (pll2->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
189 {
190 assert_param(IS_RCC_INC_STEP(pll2->INC_STEP));
191 assert_param(IS_RCC_SSCG_MODE(pll2->SSCG_MODE));
192 assert_param(IS_RCC_RPDFN_DIS(pll2->RPDFN_DIS));
193 assert_param(IS_RCC_TPDFN_DIS(pll2->TPDFN_DIS));
194 assert_param(IS_RCC_MOD_PER(pll2->MOD_PER));
195
196 __HAL_RCC_PLL2CSGCONFIG(pll2->MOD_PER, pll2->TPDFN_DIS, pll2->RPDFN_DIS,
197 pll2->SSCG_MODE, pll2->INC_STEP);
198 __HAL_RCC_PLL2_SSMODE_ENABLE();
199 }
200 else
201 {
202 __HAL_RCC_PLL2_SSMODE_DISABLE();
203 }
204
205
206 /* Enable the PLL2. */
207 __HAL_RCC_PLL2_ENABLE();
208
209 /* Get Start Tick*/
210 tickstart = HAL_GetTick();
211
212 /* Wait till PLL is ready */
213 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
214 {
215 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
216 {
217 return HAL_TIMEOUT;
218 }
219 }
220 /*Enable the post-dividers*/
221 __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
222 }
223 else
224 {
225 /*Disable the post-dividers*/
226 __HAL_RCC_PLL2CLKOUT_DISABLE(RCC_PLL2_DIVP | RCC_PLL2_DIVQ | RCC_PLL2_DIVR);
227 /* Disable the PLL2. */
228 __HAL_RCC_PLL2_DISABLE();
229
230 /* Get Start Tick*/
231 tickstart = HAL_GetTick();
232
233 /* Wait till PLL is ready */
234 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
235 {
236 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
237 {
238 return HAL_TIMEOUT;
239 }
240 }
241 }
242 }
243 else
244 {
245 return HAL_ERROR;
246 }
247 }
248 return HAL_OK;
249
250 }
251
252
253
254 /**
255 * @brief Configures PLL3
256 * @param pll3: pointer to a RCC_PLLInitTypeDef structure
257 *
258 * @retval HAL status
259 */
RCCEx_PLL3_Config(RCC_PLLInitTypeDef * pll3)260 HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLLInitTypeDef *pll3)
261 {
262
263 uint32_t tickstart;
264
265 /* Check the parameters */
266 assert_param(IS_RCC_PLL(pll3->PLLState));
267 if ((pll3->PLLState) != RCC_PLL_NONE)
268 {
269 /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
270 if (!__IS_PLL3_IN_USE()) /* If not used then*/
271 {
272 if ((pll3->PLLState) == RCC_PLL_ON)
273 {
274 /* Check the parameters */
275 assert_param(IS_RCC_PLLMODE(pll3->PLLMODE));
276 assert_param(IS_RCC_PLL3SOURCE(pll3->PLLSource));
277 assert_param(IS_RCC_PLLM1_VALUE(pll3->PLLM));
278 if (pll3->PLLMODE == RCC_PLL_FRACTIONAL)
279 {
280 assert_param(IS_RCC_PLLN3_FRAC_VALUE(pll3->PLLN));
281 }
282 else
283 {
284 assert_param(IS_RCC_PLLN3_INT_VALUE(pll3->PLLN));
285 }
286 assert_param(IS_RCC_PLLP3_VALUE(pll3->PLLP));
287 assert_param(IS_RCC_PLLQ3_VALUE(pll3->PLLQ));
288 assert_param(IS_RCC_PLLR3_VALUE(pll3->PLLR));
289
290 /*Disable the post-dividers*/
291 __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
292 /* Disable the main PLL. */
293 __HAL_RCC_PLL3_DISABLE();
294
295 /* Get Start Tick*/
296 tickstart = HAL_GetTick();
297
298 /* Wait till PLL is ready */
299 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
300 {
301 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
302 {
303 return HAL_TIMEOUT;
304 }
305 }
306
307
308 /*The PLL configuration below must be done before enabling the PLL:
309 -Selection of PLL clock entry (HSI or CSI or HSE)
310 -Frequency input range (PLLxRGE)
311 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
312 Once the PLL is enabled, these parameters can not be changed.
313 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
314 PLLxRDY flag to be at 0.
315 The PLL configuration below can be done at any time:
316 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
317 -Fractional Division Enable (PLLxFRACNEN)
318 -Fractional Division factor (FRACNx)*/
319
320 /* Configure PLL3 clock source */
321 __HAL_RCC_PLL3_SOURCE(pll3->PLLSource);
322
323 /* Wait till PLL SOURCE is ready */
324 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3SRCRDY) == RESET)
325 {
326 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
327 {
328 return HAL_TIMEOUT;
329 }
330 }
331
332 /* Select PLL3 input reference frequency range */
333 __HAL_RCC_PLL3_IFRANGE(pll3->PLLRGE) ;
334
335 /* Configure the PLL3 multiplication and division factors. */
336 __HAL_RCC_PLL3_CONFIG(
337 pll3->PLLM,
338 pll3->PLLN,
339 pll3->PLLP,
340 pll3->PLLQ,
341 pll3->PLLR);
342
343 /* Configure the Fractional Divider */
344 __HAL_RCC_PLL3FRACV_DISABLE(); //Set FRACLE to ‘0’
345 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
346 if ((pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll3->PLLMODE == RCC_PLL_INTEGER))
347 {
348 /* Do not use the fractional divider */
349 __HAL_RCC_PLL3FRACV_CONFIG(0); //Set FRACV to '0'
350 }
351 else
352 {
353 /* Configure PLL PLL3FRACV in fractional mode*/
354 __HAL_RCC_PLL3FRACV_CONFIG(pll3->PLLFRACV);
355 }
356 __HAL_RCC_PLL3FRACV_ENABLE(); //Set FRACLE to ‘1’
357
358
359 /* Configure the Spread Control */
360 if (pll3->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
361 {
362 assert_param(IS_RCC_INC_STEP(pll3->INC_STEP));
363 assert_param(IS_RCC_SSCG_MODE(pll3->SSCG_MODE));
364 assert_param(IS_RCC_RPDFN_DIS(pll3->RPDFN_DIS));
365 assert_param(IS_RCC_TPDFN_DIS(pll3->TPDFN_DIS));
366 assert_param(IS_RCC_MOD_PER(pll3->MOD_PER));
367
368 __HAL_RCC_PLL3CSGCONFIG(pll3->MOD_PER, pll3->TPDFN_DIS, pll3->RPDFN_DIS,
369 pll3->SSCG_MODE, pll3->INC_STEP);
370 __HAL_RCC_PLL3_SSMODE_ENABLE();
371 }
372 else
373 {
374 __HAL_RCC_PLL3_SSMODE_DISABLE();
375 }
376
377
378 /* Enable the PLL3. */
379 __HAL_RCC_PLL3_ENABLE();
380
381 /* Get Start Tick*/
382 tickstart = HAL_GetTick();
383
384 /* Wait till PLL is ready */
385 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
386 {
387 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
388 {
389 return HAL_TIMEOUT;
390 }
391 }
392 /* Enable the post-dividers */
393 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
394 }
395 else
396 {
397 /*Disable the post-dividers*/
398 __HAL_RCC_PLL3CLKOUT_DISABLE(RCC_PLL3_DIVP | RCC_PLL3_DIVQ | RCC_PLL3_DIVR);
399 /* Disable the PLL3. */
400 __HAL_RCC_PLL3_DISABLE();
401
402 /* Get Start Tick*/
403 tickstart = HAL_GetTick();
404
405 /* Wait till PLL is ready */
406 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != RESET)
407 {
408 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
409 {
410 return HAL_TIMEOUT;
411 }
412 }
413 }
414 }
415 else
416 {
417 return HAL_ERROR;
418 }
419 }
420 return HAL_OK;
421 }
422
423
424 /**
425 * @brief Configures PLL4
426 * @param pll4: pointer to a RCC_PLLInitTypeDef structure
427 *
428 * @retval HAL status
429 */
RCCEx_PLL4_Config(RCC_PLLInitTypeDef * pll4)430 HAL_StatusTypeDef RCCEx_PLL4_Config(RCC_PLLInitTypeDef *pll4)
431 {
432
433 uint32_t tickstart;
434
435 /* Check the parameters */
436 assert_param(IS_RCC_PLL(pll4->PLLState));
437 if ((pll4->PLLState) != RCC_PLL_NONE)
438 {
439
440 if ((pll4->PLLState) == RCC_PLL_ON)
441 {
442 /* Check the parameters */
443 assert_param(IS_RCC_PLLMODE(pll4->PLLMODE));
444 assert_param(IS_RCC_PLL4SOURCE(pll4->PLLSource));
445 assert_param(IS_RCC_PLLM4_VALUE(pll4->PLLM));
446 if (pll4->PLLMODE == RCC_PLL_FRACTIONAL)
447 {
448 assert_param(IS_RCC_PLLN4_FRAC_VALUE(pll4->PLLN));
449 }
450 else
451 {
452 assert_param(IS_RCC_PLLN4_INT_VALUE(pll4->PLLN));
453 }
454 assert_param(IS_RCC_PLLP4_VALUE(pll4->PLLP));
455 assert_param(IS_RCC_PLLQ4_VALUE(pll4->PLLQ));
456 assert_param(IS_RCC_PLLR4_VALUE(pll4->PLLR));
457
458 /*Disable the post-dividers*/
459 __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
460 /* Disable the main PLL. */
461 __HAL_RCC_PLL4_DISABLE();
462
463 /* Get Start Tick*/
464 tickstart = HAL_GetTick();
465
466 /* Wait till PLL is ready */
467 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
468 {
469 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
470 {
471 return HAL_TIMEOUT;
472 }
473 }
474
475
476 /*The PLL configuration below must be done before enabling the PLL:
477 -Selection of PLL clock entry (HSI or CSI or HSE)
478 -Frequency input range (PLLxRGE)
479 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
480 Once the PLL is enabled, these parameters can not be changed.
481 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
482 PLLxRDY flag to be at 0.
483 The PLL configuration below can be done at any time:
484 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
485 -Fractional Division Enable (PLLxFRACNEN)
486 -Fractional Division factor (FRACNx)*/
487
488 /* Configure PLL4 and PLL4 clock source */
489 __HAL_RCC_PLL4_SOURCE(pll4->PLLSource);
490
491 /* Wait till PLL SOURCE is ready */
492 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4SRCRDY) == RESET)
493 {
494 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
495 {
496 return HAL_TIMEOUT;
497 }
498 }
499
500 /* Select PLL4 input reference frequency range */
501 __HAL_RCC_PLL4_IFRANGE(pll4->PLLRGE) ;
502
503 /* Configure the PLL4 multiplication and division factors. */
504 __HAL_RCC_PLL4_CONFIG(
505 pll4->PLLM,
506 pll4->PLLN,
507 pll4->PLLP,
508 pll4->PLLQ,
509 pll4->PLLR);
510
511 /* Configure the Fractional Divider */
512 __HAL_RCC_PLL4FRACV_DISABLE(); //Set FRACLE to ‘0’
513 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
514 if ((pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll4->PLLMODE == RCC_PLL_INTEGER))
515 {
516 /* Do not use the fractional divider */
517 __HAL_RCC_PLL4FRACV_CONFIG(0); //Set FRACV to '0'
518 }
519 else
520 {
521 /* Configure PLL PLL4FRACV in fractional mode*/
522 __HAL_RCC_PLL4FRACV_CONFIG(pll4->PLLFRACV);
523 }
524 __HAL_RCC_PLL4FRACV_ENABLE(); //Set FRACLE to ‘1’
525
526 /* Configure the Spread Control */
527 if (pll4->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
528 {
529 assert_param(IS_RCC_INC_STEP(pll4->INC_STEP));
530 assert_param(IS_RCC_SSCG_MODE(pll4->SSCG_MODE));
531 assert_param(IS_RCC_RPDFN_DIS(pll4->RPDFN_DIS));
532 assert_param(IS_RCC_TPDFN_DIS(pll4->TPDFN_DIS));
533 assert_param(IS_RCC_MOD_PER(pll4->MOD_PER));
534
535 __HAL_RCC_PLL4CSGCONFIG(pll4->MOD_PER, pll4->TPDFN_DIS, pll4->RPDFN_DIS,
536 pll4->SSCG_MODE, pll4->INC_STEP);
537 __HAL_RCC_PLL4_SSMODE_ENABLE();
538 }
539 else
540 {
541 __HAL_RCC_PLL4_SSMODE_DISABLE();
542 }
543
544 /* Enable the PLL4. */
545 __HAL_RCC_PLL4_ENABLE();
546
547 /* Get Start Tick*/
548 tickstart = HAL_GetTick();
549
550 /* Wait till PLL is ready */
551 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) == RESET)
552 {
553 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
554 {
555 return HAL_TIMEOUT;
556 }
557 }
558 /* Enable PLL4P Clock output. */
559 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
560 }
561 else
562 {
563 /*Disable the post-dividers*/
564 __HAL_RCC_PLL4CLKOUT_DISABLE(RCC_PLL4_DIVP | RCC_PLL4_DIVQ | RCC_PLL4_DIVR);
565 /* Disable the PLL4. */
566 __HAL_RCC_PLL4_DISABLE();
567
568 /* Get Start Tick*/
569 tickstart = HAL_GetTick();
570
571 /* Wait till PLL is ready */
572 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY) != RESET)
573 {
574 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
575 {
576 return HAL_TIMEOUT;
577 }
578 }
579 }
580 }
581 return HAL_OK;
582 }
583
584 /**
585 * @brief Initializes the RCC extended peripherals clocks according to the
586 * specified parameters in the RCC_PeriphCLKInitTypeDef.
587 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
588 * contains a field PeriphClockSelection which can be a combination of
589 * the following values:
590 * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock
591 * @arg @ref RCC_PERIPHCLK_UART24 USART2 and UART4 peripheral clock
592 * @arg @ref RCC_PERIPHCLK_UART35 USART3 and UART5 peripheral clock
593 * @arg @ref RCC_PERIPHCLK_I2C12 I2C1 and I2C2 peripheral clock
594 * @arg @ref RCC_PERIPHCLK_I2C35 I2C3 and I2C5 peripheral clock
595 * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock
596 * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock
597 * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock
598 * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock
599 * @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
600 * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
601 * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock
602 * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock
603 * @arg @ref RCC_PERIPHCLK_UART78 UART7 and UART8 peripheral clock
604 * @arg @ref RCC_PERIPHCLK_I2C46 I2C4 and I2C6 peripheral clock
605 * @arg @ref RCC_PERIPHCLK_LPTIM23 LPTIM2 and LPTIM3 peripheral clock
606 * @arg @ref RCC_PERIPHCLK_LPTIM45 LPTIM4 and LPTIM5 peripheral clock
607 * @arg @ref RCC_PERIPHCLK_SAI3 SAI3 peripheral clock
608 * @arg @ref RCC_PERIPHCLK_FMC FMC peripheral clock
609 * @arg @ref RCC_PERIPHCLK_QSPI QSPI peripheral clock
610 * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock
611 * @arg @ref RCC_PERIPHCLK_CKPER CKPER peripheral clock
612 * @arg @ref RCC_PERIPHCLK_SPDIFRX SPDIFRX peripheral clock
613 * @arg @ref RCC_PERIPHCLK_FDCAN FDCAN peripheral clock
614 * @arg @ref RCC_PERIPHCLK_SPI1 SPI/I2S1 peripheral clock
615 * @arg @ref RCC_PERIPHCLK_SPI23 SPI/I2S2 and SPI/I2S3 peripheral clock
616 * @arg @ref RCC_PERIPHCLK_SPI45 SPI4 and SPI5 peripheral clock
617 * @arg @ref RCC_PERIPHCLK_SPI6 SPI6 peripheral clock
618 * @arg @ref RCC_PERIPHCLK_SAI4 SAI4 peripheral clock
619 * @arg @ref RCC_PERIPHCLK_SDMMC12 SDMMC1 and SDMMC2 peripheral clock
620 * @arg @ref RCC_PERIPHCLK_SDMMC3 SDMMC3 peripheral clock
621 * @arg @ref RCC_PERIPHCLK_ETH ETH peripheral clock
622 * @arg @ref RCC_PERIPHCLK_RNG1 RNG1 peripheral clock
623 * @arg @ref RCC_PERIPHCLK_RNG2 RNG2 peripheral clock
624 * @arg @ref RCC_PERIPHCLK_USBO USBO peripheral clock
625 * @arg @ref RCC_PERIPHCLK_STGEN STGEN peripheral clock
626 * @arg @ref RCC_PERIPHCLK_TIMG1 TIMG1 peripheral clock
627 * @arg @ref RCC_PERIPHCLK_TIMG2 TIMG2 peripheral clock
628 *
629 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
630 * select the RTC clock source; in this case the Backup domain will be
631 * reset in order to modify the RTC Clock source, as consequence RTC
632 * registers (including the backup registers) are set to their reset
633 * values.
634 *
635 * @retval HAL status
636 */
HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)637 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef
638 *PeriphClkInit)
639 {
640 uint32_t tmpreg = 0, RESERVED_BDCR_MASK = 0;
641 uint32_t tickstart;
642 HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
643 HAL_StatusTypeDef status = HAL_OK; /* Final status */
644
645 /* Check the parameters */
646 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
647
648 /*---------------------------- CKPER configuration -------------------------*/
649 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) ==
650 RCC_PERIPHCLK_CKPER)
651 {
652 /* Check the parameters */
653 assert_param(IS_RCC_CKPERCLKSOURCE(PeriphClkInit->CkperClockSelection));
654
655 __HAL_RCC_CKPER_CONFIG(PeriphClkInit->CkperClockSelection);
656 }
657
658 /*------------------------------ I2C12 Configuration -----------------------*/
659 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C12) ==
660 RCC_PERIPHCLK_I2C12)
661 {
662 /* Check the parameters */
663 assert_param(IS_RCC_I2C12CLKSOURCE(PeriphClkInit->I2c12ClockSelection));
664
665 if ((PeriphClkInit->I2c12ClockSelection) == RCC_I2C12CLKSOURCE_PLL4)
666 {
667 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
668 if (status != HAL_OK)
669 {
670 return status;
671 }
672 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
673 }
674
675 __HAL_RCC_I2C12_CONFIG(PeriphClkInit->I2c12ClockSelection);
676 }
677
678 /*------------------------------ I2C35 Configuration -----------------------*/
679 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C35) ==
680 RCC_PERIPHCLK_I2C35)
681 {
682 /* Check the parameters */
683 assert_param(IS_RCC_I2C35CLKSOURCE(PeriphClkInit->I2c35ClockSelection));
684
685 if ((PeriphClkInit->I2c35ClockSelection) == RCC_I2C35CLKSOURCE_PLL4)
686 {
687 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
688 if (status != HAL_OK)
689 {
690 return status;
691 }
692 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
693 }
694
695 __HAL_RCC_I2C35_CONFIG(PeriphClkInit->I2c35ClockSelection);
696 }
697
698 /*------------------------------ I2C46 Configuration -----------------------*/
699 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C46) ==
700 RCC_PERIPHCLK_I2C46)
701 {
702 /* Check the parameters */
703 assert_param(IS_RCC_I2C46CLKSOURCE(PeriphClkInit->I2c46ClockSelection));
704
705 if ((PeriphClkInit->I2c46ClockSelection) == RCC_I2C46CLKSOURCE_PLL3)
706 {
707 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
708 if (status != HAL_OK)
709 {
710 return status;
711 }
712 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
713 }
714
715 __HAL_RCC_I2C46_CONFIG(PeriphClkInit->I2c46ClockSelection);
716 }
717
718 /*---------------------------- SAI1 configuration --------------------------*/
719 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) ==
720 RCC_PERIPHCLK_SAI1)
721 {
722 /* Check the parameters */
723 assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
724
725 switch (PeriphClkInit->Sai1ClockSelection)
726 {
727 case RCC_SAI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI1*/
728
729 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
730 if (status != HAL_OK)
731 {
732 return status;
733 }
734 /* Enable SAI Clock output generated on PLL4 */
735 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
736
737 break;
738
739 case RCC_SAI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI1*/
740
741 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
742 if (status != HAL_OK)
743 {
744 return status;
745 }
746 /* Enable SAI Clock output generated on PLL3 */
747
748 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
749
750 break;
751
752 case RCC_SAI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI1*/
753
754 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
755 if (status != HAL_OK)
756 {
757 return status;
758 }
759 /* Enable SAI Clock output generated on PLL3 */
760
761 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
762
763 break;
764 }
765
766 /* Set the source of SAI1 clock*/
767 __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
768 }
769
770 /*---------------------------- SAI2 configuration --------------------------*/
771 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) ==
772 RCC_PERIPHCLK_SAI2)
773 {
774 /* Check the parameters */
775 assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
776
777 switch (PeriphClkInit->Sai2ClockSelection)
778 {
779 case RCC_SAI2CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI2*/
780
781 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
782 if (status != HAL_OK)
783 {
784 return status;
785 }
786 /* Enable SAI Clock output generated on PLL4 */
787 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
788
789 break;
790
791 case RCC_SAI2CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI2 */
792
793 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
794 if (status != HAL_OK)
795 {
796 return status;
797 }
798 /* Enable SAI Clock output generated on PLL3 */
799 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
800
801 break;
802
803 case RCC_SAI2CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI2 */
804
805 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
806 if (status != HAL_OK)
807 {
808 return status;
809 }
810 /* Enable SAI Clock output generated on PLL3 */
811 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
812
813 break;
814 }
815
816 /* Set the source of SAI2 clock*/
817 __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
818 }
819
820 /*---------------------------- SAI3 configuration --------------------------*/
821 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI3) ==
822 RCC_PERIPHCLK_SAI3)
823 {
824 /* Check the parameters */
825 assert_param(IS_RCC_SAI3CLKSOURCE(PeriphClkInit->Sai3ClockSelection));
826
827 switch (PeriphClkInit->Sai3ClockSelection)
828 {
829 case RCC_SAI3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI3*/
830
831 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
832 if (status != HAL_OK)
833 {
834 return status;
835 }
836 /* Enable SAI Clock output generated on PLL4 */
837 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
838
839 break;
840
841 case RCC_SAI3CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI3 */
842
843 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
844 if (status != HAL_OK)
845 {
846 return status;
847 }
848 /* Enable SAI Clock output generated on PLL3 */
849 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
850
851 break;
852
853 case RCC_SAI3CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI3 */
854
855 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
856 if (status != HAL_OK)
857 {
858 return status;
859 }
860 /* Enable SAI Clock output generated on PLL3 */
861 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
862
863 break;
864 }
865
866 /* Set the source of SAI3 clock*/
867 __HAL_RCC_SAI3_CONFIG(PeriphClkInit->Sai3ClockSelection);
868 }
869
870 /*---------------------------- SAI4 configuration --------------------------*/
871 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4) ==
872 RCC_PERIPHCLK_SAI4)
873 {
874 /* Check the parameters */
875 assert_param(IS_RCC_SAI4CLKSOURCE(PeriphClkInit->Sai4ClockSelection));
876
877 switch (PeriphClkInit->Sai4ClockSelection)
878 {
879 case RCC_SAI4CLKSOURCE_PLL4: /* PLL4 is used as clock source for SAI4 */
880
881 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
882 if (status != HAL_OK)
883 {
884 return status;
885 }
886 /* Enable SAI Clock output generated on PLL4 . */
887 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
888
889 break;
890
891
892 case RCC_SAI4CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SAI4 */
893
894 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
895 if (status != HAL_OK)
896 {
897 return status;
898 }
899 /* Enable SAI Clock output generated on PLL3_Q */
900 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
901
902 break;
903
904 case RCC_SAI4CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SAI4 */
905
906 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
907 if (status != HAL_OK)
908 {
909 return status;
910 }
911 /* Enable SAI Clock output generated on PLL3_R */
912 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
913
914 break;
915 }
916
917 /* Set the source of SAI4 clock*/
918 __HAL_RCC_SAI4_CONFIG(PeriphClkInit->Sai4ClockSelection);
919 }
920
921 /*---------------------------- SPI1 configuration --------------------------*/
922 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) ==
923 RCC_PERIPHCLK_SPI1)
924 {
925 /* Check the parameters */
926 assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection));
927
928 switch (PeriphClkInit->Spi1ClockSelection)
929 {
930 case RCC_SPI1CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI1 */
931
932 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
933 if (status != HAL_OK)
934 {
935 return status;
936 }
937 /* Enable SPI Clock output generated on PLL4 */
938 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
939
940 break;
941
942 case RCC_SPI1CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI1*/
943
944 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
945 if (status != HAL_OK)
946 {
947 return status;
948 }
949 /* Enable SPI Clock output generated on PLL3 */
950 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
951
952 break;
953
954 case RCC_SPI1CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI1 */
955
956 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
957 if (status != HAL_OK)
958 {
959 return status;
960 }
961 /* Enable SPI Clock output generated on PLL3 */
962 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
963
964 break;
965
966 }
967
968 /* Set the source of SPI1 clock*/
969 __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection);
970 }
971
972 /*---------------------------- SPI23 configuration -------------------------*/
973 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI23) ==
974 RCC_PERIPHCLK_SPI23)
975 {
976 /* Check the parameters */
977 assert_param(IS_RCC_SPI23CLKSOURCE(PeriphClkInit->Spi23ClockSelection));
978
979 switch (PeriphClkInit->Spi23ClockSelection)
980 {
981 case RCC_SPI23CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI23 */
982
983 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
984 if (status != HAL_OK)
985 {
986 return status;
987 }
988 /* Enable SPI Clock output generated on PLL4 . */
989 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
990
991 break;
992
993 case RCC_SPI23CLKSOURCE_PLL3_Q: /* PLL3_Q is used as clock source for SPI23 */
994
995 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
996 if (status != HAL_OK)
997 {
998 return status;
999 }
1000 /* Enable SPI Clock output generated on PLL3 . */
1001 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1002
1003 break;
1004
1005 case RCC_SPI23CLKSOURCE_PLL3_R: /* PLL3_R is used as clock source for SPI23 */
1006
1007 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1008 if (status != HAL_OK)
1009 {
1010 return status;
1011 }
1012 /* Enable SPI Clock output generated on PLL3 . */
1013 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1014
1015 break;
1016 }
1017
1018 /* Set the source of SPI2 clock*/
1019 __HAL_RCC_SPI23_CONFIG(PeriphClkInit->Spi23ClockSelection);
1020 }
1021
1022 /*---------------------------- SPI45 configuration -------------------------*/
1023 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) ==
1024 RCC_PERIPHCLK_SPI45)
1025 {
1026 /* Check the parameters */
1027 assert_param(IS_RCC_SPI45CLKSOURCE(PeriphClkInit->Spi45ClockSelection));
1028
1029 if (PeriphClkInit->Spi45ClockSelection == RCC_SPI45CLKSOURCE_PLL4)
1030 {
1031 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1032 if (status != HAL_OK)
1033 {
1034 return status;
1035 }
1036 /* Enable SPI Clock output generated on PLL4 . */
1037 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1038 }
1039
1040 /* Set the source of SPI45 clock*/
1041 __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
1042 }
1043
1044 /*---------------------------- SPI6 configuration --------------------------*/
1045 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) ==
1046 RCC_PERIPHCLK_SPI6)
1047 {
1048 /* Check the parameters */
1049 assert_param(IS_RCC_SPI6CLKSOURCE(PeriphClkInit->Spi6ClockSelection));
1050
1051 switch (PeriphClkInit->Spi6ClockSelection)
1052 {
1053 case RCC_SPI6CLKSOURCE_PLL4: /* PLL4 is used as clock source for SPI6 */
1054
1055 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1056 if (status != HAL_OK)
1057 {
1058 return status;
1059 }
1060 /* Enable SPI Clock output generated on PLL4 . */
1061 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1062
1063 break;
1064
1065 case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is used as clock source for SPI6 */
1066
1067 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1068 if (status != HAL_OK)
1069 {
1070 return status;
1071 }
1072 /* Enable SPI Clock output generated on PLL3 . */
1073 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1074
1075 break;
1076 }
1077
1078 /* Set the source of SPI6 clock*/
1079 __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
1080 }
1081
1082 /*---------------------------- USART6 configuration ------------------------*/
1083 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) ==
1084 RCC_PERIPHCLK_USART6)
1085 {
1086 /* Check the parameters */
1087 assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection));
1088
1089 if (PeriphClkInit->Usart6ClockSelection == RCC_USART6CLKSOURCE_PLL4)
1090 {
1091 /* PLL4 is used as clock source for USART6 */
1092 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1093 if (status != HAL_OK)
1094 {
1095 return status;
1096 }
1097 /* Enable USART Clock output generated on PLL4 */
1098 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1099 }
1100
1101 /* Set the source of USART6 clock*/
1102 __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection);
1103 }
1104
1105 /*---------------------------- UART24 configuration ------------------------*/
1106 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART24) ==
1107 RCC_PERIPHCLK_UART24)
1108 {
1109 /* Check the parameters */
1110 assert_param(IS_RCC_UART24CLKSOURCE(PeriphClkInit->Uart24ClockSelection));
1111
1112 if (PeriphClkInit->Uart24ClockSelection == RCC_UART24CLKSOURCE_PLL4)
1113 {
1114 /* PLL4 is used as clock source for UART24 */
1115 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1116 if (status != HAL_OK)
1117 {
1118 return status;
1119 }
1120 /* Enable UART Clock output generated on PLL4 */
1121 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1122 }
1123
1124 /* Set the source of UART24 clock*/
1125 __HAL_RCC_UART24_CONFIG(PeriphClkInit->Uart24ClockSelection);
1126 }
1127
1128 /*---------------------------- UART35 configuration ------------------------*/
1129 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART35) ==
1130 RCC_PERIPHCLK_UART35)
1131 {
1132 /* Check the parameters */
1133 assert_param(IS_RCC_UART35CLKSOURCE(PeriphClkInit->Uart35ClockSelection));
1134
1135 if (PeriphClkInit->Uart35ClockSelection == RCC_UART35CLKSOURCE_PLL4)
1136 {
1137 /* PLL4 is used as clock source for UART35 */
1138 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1139 if (status != HAL_OK)
1140 {
1141 return status;
1142 }
1143 /* Enable UART Clock output generated on PLL4 */
1144 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1145 }
1146
1147 /* Set the source of UART35 clock*/
1148 __HAL_RCC_UART35_CONFIG(PeriphClkInit->Uart35ClockSelection);
1149 }
1150
1151 /*---------------------------- UAUART78 configuration ----------------------*/
1152 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART78) ==
1153 RCC_PERIPHCLK_UART78)
1154 {
1155 /* Check the parameters */
1156 assert_param(IS_RCC_UART78CLKSOURCE(PeriphClkInit->Uart78ClockSelection));
1157
1158 if (PeriphClkInit->Uart78ClockSelection == RCC_UART78CLKSOURCE_PLL4)
1159 {
1160 /* PLL4 is used as clock source for UART78 */
1161 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1162 if (status != HAL_OK)
1163 {
1164 return status;
1165 }
1166 /* Enable UART Clock output generated on PLL4 */
1167 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1168 }
1169
1170 /* Set the source of UART78 clock*/
1171 __HAL_RCC_UART78_CONFIG(PeriphClkInit->Uart78ClockSelection);
1172 }
1173
1174 /*---------------------------- USART1 configuration ------------------------*/
1175 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) ==
1176 RCC_PERIPHCLK_USART1)
1177 {
1178 /* Check the parameters */
1179 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
1180
1181 switch (PeriphClkInit->Usart1ClockSelection)
1182 {
1183 case RCC_USART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1 */
1184
1185 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1186 if (status != HAL_OK)
1187 {
1188 return status;
1189 }
1190 /* Enable UART Clock output generated on PLL3 */
1191 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1192
1193 break;
1194
1195 case RCC_USART1CLKSOURCE_PLL4: /* PLL4 is used as clock source for USART1 */
1196
1197 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1198 if (status != HAL_OK)
1199 {
1200 return status;
1201 }
1202 /* Enable USART Clock output generated on PLL4 . */
1203 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1204
1205 break;
1206 }
1207
1208 /* Set the source of USART1 clock*/
1209 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
1210 }
1211
1212 /*---------------------------- SDMMC12 configuration -----------------------*/
1213 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC12) ==
1214 RCC_PERIPHCLK_SDMMC12)
1215 {
1216 /* Check the parameters */
1217 assert_param(IS_RCC_SDMMC12CLKSOURCE(PeriphClkInit->Sdmmc12ClockSelection));
1218
1219 switch (PeriphClkInit->Sdmmc12ClockSelection)
1220 {
1221 case RCC_SDMMC12CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC12 */
1222
1223 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1224 if (status != HAL_OK)
1225 {
1226 return status;
1227 }
1228 /* Enable SDMMC12 Clock output generated on PLL3 . */
1229 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1230
1231 break;
1232
1233 case RCC_SDMMC12CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC12 */
1234
1235 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1236 if (status != HAL_OK)
1237 {
1238 return status;
1239 }
1240 /* Enable SDMMC12 Clock output generated on PLL4 . */
1241 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1242
1243 break;
1244 }
1245
1246 /* Set the source of SDMMC12 clock*/
1247 __HAL_RCC_SDMMC12_CONFIG(PeriphClkInit->Sdmmc12ClockSelection);
1248 }
1249
1250 /*---------------------------- SDMMC3 configuration ------------------------*/
1251 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC3) ==
1252 RCC_PERIPHCLK_SDMMC3)
1253 {
1254 /* Check the parameters */
1255 assert_param(IS_RCC_SDMMC3CLKSOURCE(PeriphClkInit->Sdmmc3ClockSelection));
1256
1257 switch (PeriphClkInit->Sdmmc3ClockSelection)
1258 {
1259 case RCC_SDMMC3CLKSOURCE_PLL3: /* PLL3 is used as clock source for SDMMC3 */
1260
1261 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1262 if (status != HAL_OK)
1263 {
1264 return status;
1265 }
1266 /* Enable SDMMC3 Clock output generated on PLL3 . */
1267 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1268
1269 break;
1270
1271 case RCC_SDMMC3CLKSOURCE_PLL4: /* PLL4 is used as clock source for SDMMC3 */
1272
1273 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1274 if (status != HAL_OK)
1275 {
1276 return status;
1277 }
1278 /* Enable SDMMC3 Clock output generated on PLL4 . */
1279 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1280
1281 break;
1282 }
1283
1284 /* Set the source of SDMMC3 clock*/
1285 __HAL_RCC_SDMMC3_CONFIG(PeriphClkInit->Sdmmc3ClockSelection);
1286 }
1287
1288 /*---------------------------- ETH configuration ---------------------------*/
1289 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ETH) ==
1290 RCC_PERIPHCLK_ETH)
1291 {
1292 /* Check the parameters */
1293 assert_param(IS_RCC_ETHCLKSOURCE(PeriphClkInit->EthClockSelection));
1294
1295 switch (PeriphClkInit->EthClockSelection)
1296 {
1297 case RCC_ETHCLKSOURCE_PLL4: /* PLL4 is used as clock source for ETH */
1298
1299 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1300 if (status != HAL_OK)
1301 {
1302 return status;
1303 }
1304 /* Enable ETH Clock output generated on PLL2 . */
1305 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1306
1307 break;
1308
1309 case RCC_ETHCLKSOURCE_PLL3: /* PLL3 is used as clock source for ETH */
1310
1311 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1312 if (status != HAL_OK)
1313 {
1314 return status;
1315 }
1316 /* Enable ETH Clock output generated on PLL3 . */
1317 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1318
1319 break;
1320 }
1321
1322 /* Set the source of ETH clock*/
1323 __HAL_RCC_ETH_CONFIG(PeriphClkInit->EthClockSelection);
1324 }
1325
1326 /*---------------------------- QSPI configuration --------------------------*/
1327 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) ==
1328 RCC_PERIPHCLK_QSPI)
1329 {
1330 /* Check the parameters */
1331 assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
1332
1333 switch (PeriphClkInit->QspiClockSelection)
1334 {
1335 case RCC_QSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for QSPI */
1336
1337 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1338 if (status != HAL_OK)
1339 {
1340 return status;
1341 }
1342 /* Enable QSPI Clock output generated on PLL3 . */
1343 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1344
1345 break;
1346
1347 case RCC_QSPICLKSOURCE_PLL4: /* PLL4 is used as clock source for QSPI */
1348
1349 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1350 if (status != HAL_OK)
1351 {
1352 return status;
1353 }
1354 /* Enable QSPI Clock output generated on PLL4 . */
1355 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1356
1357 break;
1358 }
1359
1360 /* Set the source of QSPI clock*/
1361 __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
1362 }
1363
1364 /*---------------------------- FMC configuration ---------------------------*/
1365 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) ==
1366 RCC_PERIPHCLK_FMC)
1367 {
1368 /* Check the parameters */
1369 assert_param(IS_RCC_FMCCLKSOURCE(PeriphClkInit->FmcClockSelection));
1370
1371 switch (PeriphClkInit->FmcClockSelection)
1372 {
1373 case RCC_FMCCLKSOURCE_PLL3: /* PLL3 is used as clock source for FMC */
1374
1375 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1376 if (status != HAL_OK)
1377 {
1378 return status;
1379 }
1380 /* Enable FMC Clock output generated on PLL3 . */
1381 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
1382
1383 break;
1384
1385 case RCC_FMCCLKSOURCE_PLL4: /* PLL4 is used as clock source for FMC */
1386
1387 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1388 if (status != HAL_OK)
1389 {
1390 return status;
1391 }
1392 /* Enable FMC Clock output generated on PLL4 . */
1393 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1394
1395 break;
1396 }
1397
1398 /* Set the source of FMC clock*/
1399 __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
1400 }
1401
1402 #if defined(FDCAN1)
1403 /*---------------------------- FDCAN configuration -------------------------*/
1404 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) ==
1405 RCC_PERIPHCLK_FDCAN)
1406 {
1407 /* Check the parameters */
1408 assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
1409
1410 switch (PeriphClkInit->FdcanClockSelection)
1411 {
1412 case RCC_FDCANCLKSOURCE_PLL3: /* PLL3 is used as clock source for FDCAN */
1413
1414 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1415 if (status != HAL_OK)
1416 {
1417 return status;
1418 }
1419 /* Enable FDCAN Clock output generated on PLL3 . */
1420 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1421
1422 break;
1423
1424 case RCC_FDCANCLKSOURCE_PLL4_Q: /* PLL4_Q is used as clock source for FDCAN */
1425
1426 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1427 if (status != HAL_OK)
1428 {
1429 return status;
1430 }
1431 /* Enable FDCAN Clock output generated on PLL4 */
1432 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1433
1434 break;
1435
1436 case RCC_FDCANCLKSOURCE_PLL4_R: /* PLL4_R is used as clock source for FDCAN */
1437
1438 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1439 if (status != HAL_OK)
1440 {
1441 return status;
1442 }
1443 /* Enable FDCAN Clock output generated on PLL4 */
1444 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1445
1446 break;
1447 }
1448
1449 /* Set the source of FDCAN clock*/
1450 __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
1451 }
1452 #endif /*FDCAN1*/
1453
1454 /*---------------------------- SPDIFRX configuration -----------------------*/
1455 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) ==
1456 RCC_PERIPHCLK_SPDIFRX)
1457 {
1458 /* Check the parameters */
1459 assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifrxClockSelection));
1460
1461 switch (PeriphClkInit->SpdifrxClockSelection)
1462 {
1463 case RCC_SPDIFRXCLKSOURCE_PLL4: /* PLL4 is used as clock source for SPDIF */
1464
1465 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1466 if (status != HAL_OK)
1467 {
1468 return status;
1469 }
1470 /* Enable SPDIF Clock output generated on PLL4 . */
1471 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1472
1473 break;
1474
1475 case RCC_SPDIFRXCLKSOURCE_PLL3: /* PLL3 is used as clock source for SPDIF */
1476
1477 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1478 if (status != HAL_OK)
1479 {
1480 return status;
1481 }
1482 /* Enable SPDIF Clock output generated on PLL3 . */
1483 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1484
1485 break;
1486 }
1487
1488 /* Set the source of SPDIF clock*/
1489 __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
1490 }
1491
1492 /*---------------------------- CEC configuration ---------------------------*/
1493 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) ==
1494 RCC_PERIPHCLK_CEC)
1495 {
1496 /* Check the parameters */
1497 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
1498
1499 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
1500 }
1501
1502 /*---------------------------- USBPHY configuration ------------------------*/
1503 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) ==
1504 RCC_PERIPHCLK_USBPHY)
1505 {
1506 /* Check the parameters */
1507 assert_param(IS_RCC_USBPHYCLKSOURCE(PeriphClkInit->UsbphyClockSelection));
1508
1509 if (PeriphClkInit->UsbphyClockSelection == RCC_USBPHYCLKSOURCE_PLL4)
1510 {
1511 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1512 if (status != HAL_OK)
1513 {
1514 return status;
1515 }
1516 /* Enable USB PHY Clock output generated on PLL4 . */
1517 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1518 }
1519
1520 __HAL_RCC_USBPHY_CONFIG(PeriphClkInit->UsbphyClockSelection);
1521 }
1522
1523 /*---------------------------- USBO configuration --------------------------*/
1524 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBO) ==
1525 RCC_PERIPHCLK_USBO)
1526 {
1527 /* Check the parameters */
1528 assert_param(IS_RCC_USBOCLKSOURCE(PeriphClkInit->UsboClockSelection));
1529
1530 if (PeriphClkInit->UsboClockSelection == RCC_USBOCLKSOURCE_PLL4)
1531 {
1532 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1533 if (status != HAL_OK)
1534 {
1535 return status;
1536 }
1537 /* Enable USB OTG Clock output generated on PLL4 . */
1538 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1539 }
1540
1541 __HAL_RCC_USBO_CONFIG(PeriphClkInit->UsboClockSelection);
1542 }
1543
1544 /*---------------------------- RNG1 configuration --------------------------*/
1545 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG1) ==
1546 RCC_PERIPHCLK_RNG1)
1547 {
1548 /* Check the parameters */
1549 assert_param(IS_RCC_RNG1CLKSOURCE(PeriphClkInit->Rng1ClockSelection));
1550
1551 if (PeriphClkInit->Rng1ClockSelection == RCC_RNG1CLKSOURCE_PLL4)
1552 {
1553 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1554 if (status != HAL_OK)
1555 {
1556 return status;
1557 }
1558 /* Enable RNG1 Clock output generated on PLL4 . */
1559 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1560 }
1561
1562 /* Set the source of RNG1 clock*/
1563 __HAL_RCC_RNG1_CONFIG(PeriphClkInit->Rng1ClockSelection);
1564 }
1565
1566 /*---------------------------- RNG2 configuration --------------------------*/
1567 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG2) ==
1568 RCC_PERIPHCLK_RNG2)
1569 {
1570 /* Check the parameters */
1571 assert_param(IS_RCC_RNG2CLKSOURCE(PeriphClkInit->Rng2ClockSelection));
1572
1573 if (PeriphClkInit->Rng2ClockSelection == RCC_RNG2CLKSOURCE_PLL4)
1574 {
1575 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1576 if (status != HAL_OK)
1577 {
1578 return status;
1579 }
1580 /* Enable RNG2 Clock output generated on PLL4 . */
1581 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1582 }
1583
1584 /* Set the source of RNG2 clock*/
1585 __HAL_RCC_RNG2_CONFIG(PeriphClkInit->Rng2ClockSelection);
1586 }
1587
1588 /*---------------------------- STGEN configuration -------------------------*/
1589 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_STGEN) ==
1590 RCC_PERIPHCLK_STGEN)
1591 {
1592 /* Check the parameters */
1593 assert_param(IS_RCC_STGENCLKSOURCE(PeriphClkInit->StgenClockSelection));
1594
1595 __HAL_RCC_STGEN_CONFIG(PeriphClkInit->StgenClockSelection);
1596 }
1597
1598 #if defined(DSI)
1599 /*---------------------------- DSI configuration ---------------------------*/
1600 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) ==
1601 RCC_PERIPHCLK_DSI)
1602 {
1603 /* Check the parameters */
1604 assert_param(IS_RCC_DSICLKSOURCE(PeriphClkInit->DsiClockSelection));
1605
1606 if (PeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL4)
1607 {
1608 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1609 if (status != HAL_OK)
1610 {
1611 return status;
1612 }
1613 /* Enable DSI Clock output generated on PLL4 . */
1614 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1615 }
1616
1617 __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
1618 }
1619 #endif /*DSI*/
1620
1621 /*---------------------------- ADC configuration ---------------------------*/
1622 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) ==
1623 RCC_PERIPHCLK_ADC)
1624 {
1625 /* Check the parameters */
1626 assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
1627
1628 switch (PeriphClkInit->AdcClockSelection)
1629 {
1630 case RCC_ADCCLKSOURCE_PLL4: /* PLL4 is used as clock source for ADC */
1631
1632 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1633 if (status != HAL_OK)
1634 {
1635 return status;
1636 }
1637 /* Enable ADC Clock output generated on PLL4 */
1638 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVR);
1639 break;
1640
1641 case RCC_ADCCLKSOURCE_PLL3: /* PLL3 is used as clock source for ADC */
1642
1643 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1644 if (status != HAL_OK)
1645 {
1646 return status;
1647 }
1648 /* Enable ADC Clock output generated on PLL3 */
1649 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1650
1651 break;
1652 }
1653
1654 /* Set the source of ADC clock*/
1655 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1656 }
1657
1658 /*---------------------------- LPTIM45 configuration -----------------------*/
1659 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM45) ==
1660 RCC_PERIPHCLK_LPTIM45)
1661 {
1662 /* Check the parameters */
1663 assert_param(IS_RCC_LPTIM45CLKSOURCE(PeriphClkInit->Lptim45ClockSelection));
1664
1665 switch (PeriphClkInit->Lptim45ClockSelection)
1666 {
1667 case RCC_LPTIM45CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM45 */
1668
1669 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1670 if (status != HAL_OK)
1671 {
1672 return status;
1673 }
1674 /* Enable clock output generated on PLL3 . */
1675 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1676
1677 break;
1678
1679 case RCC_LPTIM45CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM45 */
1680
1681 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1682 if (status != HAL_OK)
1683 {
1684 return status;
1685 }
1686 /* Enable clock output generated on PLL4 . */
1687 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1688
1689 break;
1690 }
1691
1692 /* Set the source of LPTIM45 clock*/
1693 __HAL_RCC_LPTIM45_CONFIG(PeriphClkInit->Lptim45ClockSelection);
1694 }
1695
1696 /*---------------------------- LPTIM23 configuration -----------------------*/
1697 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM23) ==
1698 RCC_PERIPHCLK_LPTIM23)
1699 {
1700 /* Check the parameters */
1701 assert_param(IS_RCC_LPTIM23CLKSOURCE(PeriphClkInit->Lptim23ClockSelection));
1702
1703 if (PeriphClkInit->Lptim23ClockSelection == RCC_LPTIM23CLKSOURCE_PLL4)
1704 {
1705 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1706 if (status != HAL_OK)
1707 {
1708 return status;
1709 }
1710 /* Enable clock output generated on PLL4 . */
1711 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVQ);
1712 }
1713
1714 /* Set the source of LPTIM23 clock*/
1715 __HAL_RCC_LPTIM23_CONFIG(PeriphClkInit->Lptim23ClockSelection);
1716 }
1717
1718 /*---------------------------- LPTIM1 configuration ------------------------*/
1719 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) ==
1720 RCC_PERIPHCLK_LPTIM1)
1721 {
1722 /* Check the parameters */
1723 assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
1724
1725 switch (PeriphClkInit->Lptim1ClockSelection)
1726 {
1727 case RCC_LPTIM1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPTIM1 */
1728
1729 status = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3));
1730 if (status != HAL_OK)
1731 {
1732 return status;
1733 }
1734 /* Enable clock output generated on PLL3 . */
1735 __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
1736
1737 break;
1738
1739 case RCC_LPTIM1CLKSOURCE_PLL4: /* PLL4 is used as clock source for LPTIM1 */
1740
1741 status = RCCEx_PLL4_Config(&(PeriphClkInit->PLL4));
1742 if (status != HAL_OK)
1743 {
1744 return status;
1745 }
1746 /* Enable clock output generated on PLL4 . */
1747 __HAL_RCC_PLL4CLKOUT_ENABLE(RCC_PLL4_DIVP);
1748
1749 break;
1750 }
1751
1752 /* Set the source of LPTIM1 clock*/
1753 __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
1754 }
1755
1756 /*---------------------------- RTC configuration ---------------------------*/
1757 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) ==
1758 RCC_PERIPHCLK_RTC)
1759 {
1760 /* check for RTC Parameters used to output RTCCLK */
1761 assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
1762
1763 /* Enable write access to Backup domain */
1764 SET_BIT(PWR->CR1, PWR_CR1_DBP);
1765
1766 /* Wait for Backup domain Write protection disable */
1767 tickstart = HAL_GetTick();
1768
1769 while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
1770 {
1771 if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
1772 {
1773 ret = HAL_TIMEOUT;
1774 }
1775 }
1776
1777 if (ret == HAL_OK)
1778 {
1779 /* Reset the Backup domain only if the RTC Clock source selection is modified */
1780 if ((RCC->BDCR & RCC_BDCR_RTCSRC) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSRC))
1781 {
1782 /* Store the content of BDCR register before the reset of Backup Domain */
1783 tmpreg = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSRC));
1784 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1785 __HAL_RCC_BACKUPRESET_FORCE();
1786 __HAL_RCC_BACKUPRESET_RELEASE();
1787
1788 /* Set the LSEDrive value */
1789 __HAL_RCC_LSEDRIVE_CONFIG(tmpreg & RCC_BDCR_LSEDRV);
1790
1791 /* RCC_BDCR_LSEON can be enabled for RTC or another IP, re-enable it */
1792 RCC_OscInitTypeDef RCC_OscInitStructure;
1793 /* Configure LSE Oscillator*/
1794 RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_LSE;
1795 RCC_OscInitStructure.LSEState = (tmpreg & LSE_MASK);
1796
1797 RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
1798 RCC_OscInitStructure.PLL2.PLLState = RCC_PLL_NONE;
1799 RCC_OscInitStructure.PLL3.PLLState = RCC_PLL_NONE;
1800 RCC_OscInitStructure.PLL4.PLLState = RCC_PLL_NONE;
1801 ret = HAL_RCC_OscConfig(&RCC_OscInitStructure);
1802 if (ret != HAL_OK)
1803 {
1804 return ret;
1805 }
1806
1807 /* Write the RTCSRC */
1808 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
1809
1810 /* Fill up Reserved register mask for BDCR
1811 * All already filled up or what shouldn't be modified must be put on the mask */
1812 RESERVED_BDCR_MASK = ~(RCC_BDCR_VSWRST | RCC_BDCR_RTCCKEN | RCC_BDCR_RTCSRC |
1813 RCC_BDCR_LSECSSD | RCC_BDCR_LSEDRV | RCC_BDCR_DIGBYP |
1814 RCC_BDCR_LSERDY | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON);
1815
1816 /* Restore the BDCR context: RESERVED registers plus RCC_BDCR_LSECSSON */
1817 WRITE_REG(RCC->BDCR, (READ_REG(RCC->BDCR) | (tmpreg & RESERVED_BDCR_MASK)));
1818
1819 }/* End RTCSRC changed */
1820
1821 /*Enable RTC clock */
1822 __HAL_RCC_RTC_ENABLE();
1823 }
1824 else
1825 {
1826 // Enable write access to Backup domain failed
1827 /* return the error */
1828 return ret;
1829 }
1830 }
1831
1832 /*---------------------------- TIMG1 configuration -------------------------*/
1833 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG1) ==
1834 RCC_PERIPHCLK_TIMG1)
1835 {
1836 /* Check the parameters */
1837 assert_param(IS_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection));
1838
1839 /* Set TIMG1 division factor */
1840 __HAL_RCC_TIMG1PRES(PeriphClkInit->TIMG1PresSelection);
1841
1842 /* Get Start Tick*/
1843 tickstart = HAL_GetTick();
1844
1845 /* Wait till TIMG1 is ready */
1846 while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG1PRERDY) == RESET)
1847 {
1848 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1849 {
1850 return HAL_TIMEOUT;
1851 }
1852 }
1853 }
1854
1855 /*---------------------------- TIMG2 configuration -------------------------*/
1856 if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMG2) ==
1857 RCC_PERIPHCLK_TIMG2)
1858 {
1859 /* Check the parameters */
1860 assert_param(IS_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection));
1861
1862 /* Set TIMG1 division factor */
1863 __HAL_RCC_TIMG2PRES(PeriphClkInit->TIMG2PresSelection);
1864
1865 /* Get Start Tick*/
1866 tickstart = HAL_GetTick();
1867
1868 /* Wait till TIMG1 is ready */
1869 while (__HAL_RCC_GET_FLAG(RCC_FLAG_TIMG2PRERDY) == RESET)
1870 {
1871 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1872 {
1873 return HAL_TIMEOUT;
1874 }
1875 }
1876 }
1877
1878 return HAL_OK;
1879 }
1880
1881
1882
1883 /**
1884 * @brief Get the RCC_ClkInitStruct according to the internal RCC
1885 * configuration registers.
1886 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1887 * returns the configuration information for the Extended Peripherals
1888 * clocks : CKPER, I2C12, I2C35, I2C46, I2C5, SAI1, SAI2, SAI3, SAI4,
1889 * SPI1, SPI2, SPI3, SPI45, SPI6, USART1, UART24, USART3, UART24, UART35,
1890 * USART6, UART78, SDMMC12, SDMMC3, ETH, QSPI,FMC, FDCAN,
1891 * SPDIFRX, CEC, USBPHY, USBO, RNG1, RNG2, STGEN, DSI, ADC, RTC,
1892 * LPTIM1, LPTIM23, LPTIM45
1893 * @retval None
1894 */
HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef * PeriphClkInit)1895 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1896 {
1897 /* Set all possible values for the extended clock type parameter------------*/
1898 PeriphClkInit->PeriphClockSelection =
1899 RCC_PERIPHCLK_CKPER | RCC_PERIPHCLK_I2C12 | RCC_PERIPHCLK_I2C35 |
1900 RCC_PERIPHCLK_I2C46 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |
1901 RCC_PERIPHCLK_SAI3 | RCC_PERIPHCLK_SAI4 | RCC_PERIPHCLK_SPI1 |
1902 RCC_PERIPHCLK_SPI23 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 |
1903 RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_UART24 | RCC_PERIPHCLK_UART35 |
1904 RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART78 | RCC_PERIPHCLK_SDMMC12 |
1905 RCC_PERIPHCLK_SDMMC3 | RCC_PERIPHCLK_ETH | RCC_PERIPHCLK_QSPI |
1906 RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_SPDIFRX |
1907 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_USBO |
1908 RCC_PERIPHCLK_RNG1 | RCC_PERIPHCLK_RNG2 | RCC_PERIPHCLK_STGEN |
1909 RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC |
1910 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM23 | RCC_PERIPHCLK_LPTIM45;
1911
1912 /* Get the CKPER clock source ----------------------------------------------*/
1913 PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CKPER_SOURCE();
1914
1915 /* Get the I2C12 clock source ----------------------------------------------*/
1916 PeriphClkInit->I2c12ClockSelection = __HAL_RCC_GET_I2C12_SOURCE();
1917 /* Get the I2C35 clock source ----------------------------------------------*/
1918 PeriphClkInit->I2c35ClockSelection = __HAL_RCC_GET_I2C35_SOURCE();
1919 /* Get the I2C46 clock source -----------------------------------------------*/
1920 PeriphClkInit->I2c46ClockSelection = __HAL_RCC_GET_I2C46_SOURCE();
1921
1922 /* Get the SAI1 clock source -----------------------------------------------*/
1923 PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
1924 /* Get the SAI2 clock source -----------------------------------------------*/
1925 PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
1926 /* Get the SAI3 clock source -----------------------------------------------*/
1927 PeriphClkInit->Sai3ClockSelection = __HAL_RCC_GET_SAI3_SOURCE();
1928 /* Get the SAI4 clock source -----------------------------------------------*/
1929 PeriphClkInit->Sai4ClockSelection = __HAL_RCC_GET_SAI4_SOURCE();
1930
1931 /* Get the SPI1 clock source -----------------------------------------------*/
1932 PeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE();
1933 /* Get the SPI23 clock source ----------------------------------------------*/
1934 PeriphClkInit->Spi23ClockSelection = __HAL_RCC_GET_SPI23_SOURCE();
1935 /* Get the SPI45 clock source ----------------------------------------------*/
1936 PeriphClkInit->Spi45ClockSelection = __HAL_RCC_GET_SPI45_SOURCE();
1937 /* Get the SPI6 clock source -----------------------------------------------*/
1938 PeriphClkInit->Spi6ClockSelection = __HAL_RCC_GET_SPI6_SOURCE();
1939
1940 /* Get the USART1 configuration --------------------------------------------*/
1941 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
1942 /* Get the UART24 clock source ----------------------------------------------*/
1943 PeriphClkInit->Uart24ClockSelection = __HAL_RCC_GET_UART24_SOURCE();
1944 /* Get the UART35 clock source ---------------------------------------------*/
1945 PeriphClkInit->Uart35ClockSelection = __HAL_RCC_GET_UART35_SOURCE();
1946 /* Get the USART6 clock source ---------------------------------------------*/
1947 PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE();
1948 /* Get the UART78 clock source ---------------------------------------------*/
1949 PeriphClkInit->Uart78ClockSelection = __HAL_RCC_GET_UART78_SOURCE();
1950
1951 /* Get the SDMMC12 clock source --------------------------------------------*/
1952 PeriphClkInit->Sdmmc12ClockSelection = __HAL_RCC_GET_SDMMC12_SOURCE();
1953 /* Get the SDMMC3 clock source ---------------------------------------------*/
1954 PeriphClkInit->Sdmmc3ClockSelection = __HAL_RCC_GET_SDMMC3_SOURCE();
1955 /* Get the SDMMC3 clock source ---------------------------------------------*/
1956 PeriphClkInit->EthClockSelection = __HAL_RCC_GET_ETH_SOURCE();
1957
1958 /* Get the QSPI clock source -----------------------------------------------*/
1959 PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
1960 /* Get the FMC clock source ------------------------------------------------*/
1961 PeriphClkInit->FmcClockSelection = __HAL_RCC_GET_FMC_SOURCE();
1962 #if defined(FDCAN1)
1963 /* Get the FDCAN clock source ----------------------------------------------*/
1964 PeriphClkInit->FdcanClockSelection = __HAL_RCC_GET_FDCAN_SOURCE();
1965 #endif /*FDCAN1*/
1966 /* Get the SPDIFRX clock source --------------------------------------------*/
1967 PeriphClkInit->SpdifrxClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
1968 /* Get the CEC clock source ------------------------------------------------*/
1969 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
1970 /* Get the USBPHY clock source ---------------------------------------------*/
1971 PeriphClkInit-> UsbphyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE();
1972 /* Get the USBO clock source -----------------------------------------------*/
1973 PeriphClkInit-> UsboClockSelection = __HAL_RCC_GET_USBO_SOURCE();
1974 /* Get the RNG1 clock source -----------------------------------------------*/
1975 PeriphClkInit->Rng1ClockSelection = __HAL_RCC_GET_RNG1_SOURCE();
1976 /* Get the RNG2 clock source -----------------------------------------------*/
1977 PeriphClkInit->Rng2ClockSelection = __HAL_RCC_GET_RNG2_SOURCE();
1978 /* Get the STGEN clock source ----------------------------------------------*/
1979 PeriphClkInit->StgenClockSelection = __HAL_RCC_GET_STGEN_SOURCE();
1980 #if defined(DSI)
1981 /* Get the DSI clock source ------------------------------------------------*/
1982 PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
1983 #endif /*DSI*/
1984 /* Get the ADC clock source ------------------------------------------------*/
1985 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1986 /* Get the RTC clock source ------------------------------------------------*/
1987 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
1988
1989 /* Get the LPTIM1 clock source ---------------------------------------------*/
1990 PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
1991 /* Get the LPTIM23 clock source ---------------------------------------------*/
1992 PeriphClkInit->Lptim23ClockSelection = __HAL_RCC_GET_LPTIM23_SOURCE();
1993 /* Get the LPTIM45 clock source ---------------------------------------------*/
1994 PeriphClkInit->Lptim45ClockSelection = __HAL_RCC_GET_LPTIM45_SOURCE();
1995
1996 /* Get the TIM1 Prescaler configuration ------------------------------------*/
1997 PeriphClkInit->TIMG1PresSelection = __HAL_RCC_GET_TIMG1PRES();
1998 /* Get the TIM2 Prescaler configuration ------------------------------------*/
1999 PeriphClkInit->TIMG2PresSelection = __HAL_RCC_GET_TIMG2PRES();
2000 }
2001
2002 /**
2003 * @brief Enables the LSE Clock Security System.
2004 * @note After reset BDCR register is write-protected and the DBP bit in the
2005 * PWR control register 1 (PWR_CR1) has to be set before it can be written.
2006 * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled
2007 * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC
2008 * clock with HAL_RCCEx_PeriphCLKConfig().
2009 * @retval None
2010 */
HAL_RCCEx_EnableLSECSS(void)2011 void HAL_RCCEx_EnableLSECSS(void)
2012 {
2013 /* Set LSECSSON bit */
2014 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2015 }
2016
2017 /**
2018 * @brief Disables the LSE Clock Security System.
2019 * @note LSE Clock Security System can only be disabled after a LSE failure detection.
2020 * @note After reset BDCR register is write-protected and the DBP bit in the
2021 * PWR control register 1 (PWR_CR1) has to be set before it can be written.
2022 * @retval None
2023 */
HAL_RCCEx_DisableLSECSS(void)2024 void HAL_RCCEx_DisableLSECSS(void)
2025 {
2026 /* Unset LSECSSON bit */
2027 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2028 }
2029
2030
2031 /**
2032 * @brief Returns the peripheral clock frequency
2033 * @note Returns 0 if peripheral clock is unknown
2034 * @param PeriphClk: Peripheral clock identifier
2035 * This parameter can be a value of :
2036 * @ref RCCEx_Periph_Clock_Selection
2037 * @ref RCCEx_Periph_One_Clock
2038 * @retval Frequency in Hz
2039 */
HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)2040 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
2041 {
2042 uint32_t frequency = 0, clksource = 0;
2043
2044 PLL2_ClocksTypeDef pll2_clocks;
2045 PLL3_ClocksTypeDef pll3_clocks;
2046 PLL4_ClocksTypeDef pll4_clocks;
2047
2048 /* Check the parameters */
2049 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk) || IS_RCC_PERIPHONECLOCK(PeriphClk));
2050
2051 switch (PeriphClk)
2052 {
2053
2054 case RCC_PERIPHCLK_DAC:
2055 {
2056 frequency = LSI_VALUE;
2057 }
2058 break; /*RCC_PERIPHCLK_DAC*/
2059
2060
2061 case RCC_PERIPHCLK_WWDG:
2062 {
2063 frequency = HAL_RCC_GetPCLK1Freq();
2064 }
2065 break; /* RCC_PERIPHCLK_WWDG */
2066
2067
2068 case RCC_PERIPHCLK_CEC:
2069 {
2070 clksource = __HAL_RCC_GET_CEC_SOURCE();
2071
2072 switch (clksource)
2073 {
2074 case RCC_CECCLKSOURCE_LSE:
2075 frequency = LSE_VALUE;
2076 break;
2077
2078 case RCC_CECCLKSOURCE_LSI:
2079 frequency = LSI_VALUE;
2080 break;
2081
2082 case RCC_CECCLKSOURCE_CSI122:
2083 frequency = (CSI_VALUE / 122);
2084 break;
2085
2086 default:
2087 frequency = 0;
2088 break;
2089 }
2090 }
2091 break; /* RCC_PERIPHCLK_CEC */
2092
2093
2094 case RCC_PERIPHCLK_I2C12:
2095 {
2096 clksource = __HAL_RCC_GET_I2C12_SOURCE();
2097
2098 switch (clksource)
2099 {
2100 case RCC_I2C12CLKSOURCE_PCLK1:
2101 frequency = HAL_RCC_GetPCLK1Freq();
2102 break;
2103
2104 case RCC_I2C12CLKSOURCE_PLL4:
2105 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2106 frequency = pll4_clocks.PLL4_R_Frequency;
2107 break;
2108
2109 case RCC_I2C12CLKSOURCE_HSI:
2110 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2111 break;
2112
2113 case RCC_I2C12CLKSOURCE_CSI:
2114 frequency = CSI_VALUE;
2115 break;
2116 }
2117 }
2118 break; /* RCC_PERIPHCLK_I2C12 */
2119
2120
2121 case RCC_PERIPHCLK_I2C35:
2122 {
2123 clksource = __HAL_RCC_GET_I2C35_SOURCE();
2124
2125 switch (clksource)
2126 {
2127 case RCC_I2C35CLKSOURCE_PCLK1:
2128 frequency = HAL_RCC_GetPCLK1Freq();
2129 break;
2130
2131 case RCC_I2C35CLKSOURCE_PLL4:
2132 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2133 frequency = pll4_clocks.PLL4_R_Frequency;
2134 break;
2135
2136 case RCC_I2C35CLKSOURCE_HSI:
2137 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2138 break;
2139
2140 case RCC_I2C35CLKSOURCE_CSI:
2141 frequency = CSI_VALUE;
2142 break;
2143 }
2144 }
2145 break; /* RCC_PERIPHCLK_I2C35 */
2146
2147
2148 case RCC_PERIPHCLK_LPTIM1:
2149 {
2150 clksource = __HAL_RCC_GET_LPTIM1_SOURCE();
2151
2152 switch (clksource)
2153 {
2154 case RCC_LPTIM1CLKSOURCE_PCLK1:
2155 frequency = HAL_RCC_GetPCLK1Freq();
2156 break;
2157
2158 case RCC_LPTIM1CLKSOURCE_PLL4:
2159 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2160 frequency = pll4_clocks.PLL4_P_Frequency;
2161 break;
2162
2163 case RCC_LPTIM1CLKSOURCE_PLL3:
2164 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2165 frequency = pll3_clocks.PLL3_Q_Frequency;
2166 break;
2167
2168 case RCC_LPTIM1CLKSOURCE_LSE:
2169 frequency = LSE_VALUE;
2170 break;
2171
2172 case RCC_LPTIM1CLKSOURCE_LSI:
2173 frequency = LSI_VALUE;
2174 break;
2175
2176 case RCC_LPTIM1CLKSOURCE_PER:
2177 frequency = RCC_GetCKPERFreq();
2178 break;
2179
2180 default:
2181 frequency = 0;
2182 break;
2183 }
2184 }
2185 break; /* RCC_PERIPHCLK_LPTIM1 */
2186
2187
2188 case RCC_PERIPHCLK_SPDIFRX:
2189 {
2190 clksource = __HAL_RCC_GET_SPDIFRX_SOURCE();
2191
2192 switch (clksource)
2193 {
2194 case RCC_SPDIFRXCLKSOURCE_PLL4:
2195 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2196 frequency = pll4_clocks.PLL4_P_Frequency;
2197 break;
2198
2199 case RCC_SPDIFRXCLKSOURCE_PLL3:
2200 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2201 frequency = pll3_clocks.PLL3_Q_Frequency;
2202 break;
2203
2204 case RCC_SPDIFRXCLKSOURCE_HSI:
2205 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2206 break;
2207
2208 default:
2209 frequency = 0;
2210 break;
2211 }
2212 }
2213 break; /* RCC_PERIPHCLK_SPDIFRX */
2214
2215 case RCC_PERIPHCLK_SPI23:
2216 {
2217 clksource = __HAL_RCC_GET_SPI23_SOURCE();
2218
2219 switch (clksource)
2220 {
2221 case RCC_SPI23CLKSOURCE_PLL4:
2222 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2223 frequency = pll4_clocks.PLL4_P_Frequency;
2224 break;
2225
2226 case RCC_SPI23CLKSOURCE_PLL3_Q:
2227 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2228 frequency = pll3_clocks.PLL3_Q_Frequency;
2229 break;
2230
2231 case RCC_SPI23CLKSOURCE_PLL3_R:
2232 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2233 frequency = pll3_clocks.PLL3_R_Frequency;
2234 break;
2235
2236 case RCC_SPI23CLKSOURCE_I2SCKIN:
2237 frequency = EXTERNAL_CLOCK_VALUE;
2238 break;
2239
2240 case RCC_SPI23CLKSOURCE_PER:
2241 frequency = RCC_GetCKPERFreq();
2242 break;
2243
2244 default:
2245 frequency = 0;
2246 break;
2247 }
2248 }
2249 break; /* RCC_PERIPHCLK_SPI23 */
2250
2251
2252 case RCC_PERIPHCLK_UART24:
2253 {
2254 clksource = __HAL_RCC_GET_UART24_SOURCE();
2255
2256 switch (clksource)
2257 {
2258 case RCC_UART24CLKSOURCE_PCLK1:
2259 frequency = HAL_RCC_GetPCLK1Freq();
2260 break;
2261
2262 case RCC_UART24CLKSOURCE_PLL4:
2263 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2264 frequency = pll4_clocks.PLL4_Q_Frequency;
2265 break;
2266
2267 case RCC_UART24CLKSOURCE_HSI:
2268 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2269 break;
2270
2271 case RCC_UART24CLKSOURCE_CSI:
2272 frequency = CSI_VALUE;
2273 break;
2274
2275 case RCC_UART24CLKSOURCE_HSE:
2276 frequency = HSE_VALUE;
2277 break;
2278
2279 default:
2280 frequency = 0;
2281 break;
2282 }
2283 }
2284 break; /* RCC_PERIPHCLK_UART24 */
2285
2286
2287 case RCC_PERIPHCLK_UART35:
2288 {
2289 clksource = __HAL_RCC_GET_UART35_SOURCE();
2290
2291 switch (clksource)
2292 {
2293 case RCC_UART35CLKSOURCE_PCLK1:
2294 frequency = HAL_RCC_GetPCLK1Freq();
2295 break;
2296
2297 case RCC_UART35CLKSOURCE_PLL4:
2298 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2299 frequency = pll4_clocks.PLL4_Q_Frequency;
2300 break;
2301
2302 case RCC_UART35CLKSOURCE_HSI:
2303 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2304 break;
2305
2306 case RCC_UART35CLKSOURCE_CSI:
2307 frequency = CSI_VALUE;
2308 break;
2309
2310 case RCC_UART35CLKSOURCE_HSE:
2311 frequency = HSE_VALUE;
2312 break;
2313
2314 default:
2315 frequency = 0;
2316 break;
2317 }
2318 }
2319 break; /* RCC_PERIPHCLK_USART35 */
2320
2321
2322 case RCC_PERIPHCLK_UART78:
2323 {
2324 clksource = __HAL_RCC_GET_UART78_SOURCE();
2325
2326 switch (clksource)
2327 {
2328 case RCC_UART78CLKSOURCE_PCLK1:
2329 frequency = HAL_RCC_GetPCLK1Freq();
2330 break;
2331
2332 case RCC_UART78CLKSOURCE_PLL4:
2333 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2334 frequency = pll4_clocks.PLL4_Q_Frequency;
2335 break;
2336
2337 case RCC_UART78CLKSOURCE_HSI:
2338 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2339 break;
2340
2341 case RCC_UART78CLKSOURCE_CSI:
2342 frequency = CSI_VALUE;
2343 break;
2344
2345 case RCC_UART78CLKSOURCE_HSE:
2346 frequency = HSE_VALUE;
2347 break;
2348
2349 default:
2350 frequency = 0;
2351 break;
2352 }
2353 }
2354 break; /*RCC_PERIPHCLK_UART78 */
2355
2356
2357 case RCC_PERIPHCLK_DFSDM1:
2358 {
2359 frequency = HAL_RCC_GetMLHCLKFreq();
2360 }
2361 break;//RCC_PERIPHCLK_DFSDM1
2362
2363 #if defined(FDCAN1)
2364 case RCC_PERIPHCLK_FDCAN:
2365 {
2366 clksource = __HAL_RCC_GET_FDCAN_SOURCE();
2367
2368 switch (clksource)
2369 {
2370 case RCC_FDCANCLKSOURCE_HSE:
2371 frequency = HSE_VALUE;
2372 break;
2373
2374 case RCC_FDCANCLKSOURCE_PLL3:
2375 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2376 frequency = pll3_clocks.PLL3_Q_Frequency;
2377 break;
2378
2379 case RCC_FDCANCLKSOURCE_PLL4_Q:
2380 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2381 frequency = pll4_clocks.PLL4_Q_Frequency;
2382 break;
2383
2384 case RCC_FDCANCLKSOURCE_PLL4_R:
2385 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2386 frequency = pll4_clocks.PLL4_R_Frequency;
2387 break;
2388
2389 default:
2390 frequency = 0;
2391 break;
2392 }
2393 }
2394 break;//RCC_PERIPHCLK_FDCAN
2395 #endif /*FDCAN1*/
2396
2397 case RCC_PERIPHCLK_SAI1:
2398 {
2399 clksource = __HAL_RCC_GET_SAI1_SOURCE();
2400
2401 switch (clksource)
2402 {
2403 case RCC_SAI1CLKSOURCE_PLL4:
2404 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2405 frequency = pll4_clocks.PLL4_Q_Frequency;
2406 break;
2407
2408 case RCC_SAI1CLKSOURCE_PLL3_Q:
2409 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2410 frequency = pll3_clocks.PLL3_Q_Frequency;
2411 break;
2412
2413 case RCC_SAI1CLKSOURCE_PLL3_R:
2414 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2415 frequency = pll3_clocks.PLL3_R_Frequency;
2416 break;
2417
2418 case RCC_SAI1CLKSOURCE_I2SCKIN:
2419 frequency = EXTERNAL_CLOCK_VALUE;
2420 break;
2421
2422 case RCC_SAI1CLKSOURCE_PER:
2423 frequency = RCC_GetCKPERFreq();
2424 break;
2425
2426 default:
2427 frequency = 0;
2428 break;
2429 }
2430 }
2431 break;//RCC_PERIPHCLK_SAI1
2432
2433
2434 case RCC_PERIPHCLK_SAI2:
2435 {
2436 clksource = __HAL_RCC_GET_SAI2_SOURCE();
2437
2438 switch (clksource)
2439 {
2440 case RCC_SAI2CLKSOURCE_PLL4:
2441 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2442 frequency = pll4_clocks.PLL4_Q_Frequency;
2443 break;
2444
2445 case RCC_SAI2CLKSOURCE_PLL3_Q:
2446 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2447 frequency = pll3_clocks.PLL3_Q_Frequency;
2448 break;
2449
2450 case RCC_SAI2CLKSOURCE_PLL3_R:
2451 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2452 frequency = pll3_clocks.PLL3_R_Frequency;
2453 break;
2454
2455 case RCC_SAI2CLKSOURCE_I2SCKIN:
2456 frequency = EXTERNAL_CLOCK_VALUE;
2457 break;
2458
2459 case RCC_SAI2CLKSOURCE_PER:
2460 frequency = RCC_GetCKPERFreq();
2461 break;
2462
2463 case RCC_SAI2CLKSOURCE_SPDIF:
2464 frequency = 0; //SAI2 manage this SPDIF_CKSYMB_VALUE
2465 break;
2466
2467 default:
2468 frequency = 0;
2469 break;
2470 }
2471 }
2472 break;//RCC_PERIPHCLK_SAI2
2473
2474
2475 case RCC_PERIPHCLK_SAI3:
2476 {
2477 clksource = __HAL_RCC_GET_SAI3_SOURCE();
2478
2479 switch (clksource)
2480 {
2481 case RCC_SAI3CLKSOURCE_PLL4:
2482 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2483 frequency = pll4_clocks.PLL4_Q_Frequency;
2484 break;
2485
2486 case RCC_SAI3CLKSOURCE_PLL3_Q:
2487 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2488 frequency = pll3_clocks.PLL3_Q_Frequency;
2489 break;
2490
2491 case RCC_SAI3CLKSOURCE_PLL3_R:
2492 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2493 frequency = pll3_clocks.PLL3_R_Frequency;
2494 break;
2495
2496 case RCC_SAI3CLKSOURCE_I2SCKIN:
2497 frequency = EXTERNAL_CLOCK_VALUE;
2498 break;
2499
2500 case RCC_SAI2CLKSOURCE_PER:
2501 frequency = RCC_GetCKPERFreq();
2502 break;
2503
2504 default:
2505 frequency = 0;
2506 break;
2507 }
2508 }
2509 break;//RCC_PERIPHCLK_SAI3
2510
2511
2512 case RCC_PERIPHCLK_SPI1:
2513 {
2514 clksource = __HAL_RCC_GET_SPI1_SOURCE();
2515
2516 switch (clksource)
2517 {
2518 case RCC_SPI1CLKSOURCE_PLL4:
2519 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2520 frequency = pll4_clocks.PLL4_Q_Frequency;
2521 break;
2522
2523 case RCC_SPI1CLKSOURCE_PLL3_Q:
2524 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2525 frequency = pll3_clocks.PLL3_Q_Frequency;
2526 break;
2527
2528 case RCC_SPI1CLKSOURCE_PLL3_R:
2529 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2530 frequency = pll3_clocks.PLL3_R_Frequency;
2531 break;
2532
2533 case RCC_SPI1CLKSOURCE_I2SCKIN:
2534 frequency = EXTERNAL_CLOCK_VALUE;
2535 break;
2536
2537 case RCC_SPI1CLKSOURCE_PER:
2538 frequency = RCC_GetCKPERFreq();
2539 break;
2540
2541 default:
2542 frequency = 0;
2543 break;
2544 }
2545 }
2546 break;//RCC_PERIPHCLK_SPI1
2547
2548
2549 case RCC_PERIPHCLK_SPI45:
2550 {
2551 clksource = __HAL_RCC_GET_SPI45_SOURCE();
2552
2553 switch (clksource)
2554 {
2555 case RCC_SPI45CLKSOURCE_PCLK2:
2556 frequency = HAL_RCC_GetPCLK2Freq();
2557 break;
2558
2559 case RCC_SPI45CLKSOURCE_PLL4:
2560 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2561 frequency = pll4_clocks.PLL4_Q_Frequency;
2562 break;
2563
2564 case RCC_SPI45CLKSOURCE_HSI:
2565 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2566 break;
2567
2568 case RCC_SPI45CLKSOURCE_CSI:
2569 frequency = CSI_VALUE;
2570 break;
2571
2572 case RCC_SPI45CLKSOURCE_HSE:
2573 frequency = HSE_VALUE;
2574 break;
2575
2576 default:
2577 frequency = 0;
2578 break;
2579 }
2580 }
2581 break; /* RCC_PERIPHCLK_SPI45 */
2582
2583
2584 case RCC_PERIPHCLK_USART6:
2585 {
2586 clksource = __HAL_RCC_GET_USART6_SOURCE();
2587
2588 switch (clksource)
2589 {
2590 case RCC_USART6CLKSOURCE_PCLK2:
2591 frequency = HAL_RCC_GetPCLK2Freq();
2592 break;
2593
2594 case RCC_USART6CLKSOURCE_PLL4:
2595 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2596 frequency = pll4_clocks.PLL4_Q_Frequency;
2597 break;
2598
2599 case RCC_USART6CLKSOURCE_HSI:
2600 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2601 break;
2602
2603 case RCC_USART6CLKSOURCE_CSI:
2604 frequency = CSI_VALUE;
2605 break;
2606
2607 case RCC_USART6CLKSOURCE_HSE:
2608 frequency = HSE_VALUE;
2609 break;
2610
2611 default:
2612 frequency = 0;
2613 break;
2614 }
2615 }
2616 break;//RCC_PERIPHCLK_USART6
2617
2618 case RCC_PERIPHCLK_LPTIM23:
2619 {
2620 clksource = __HAL_RCC_GET_LPTIM23_SOURCE();
2621
2622 switch (clksource)
2623 {
2624 case RCC_LPTIM23CLKSOURCE_PCLK3:
2625 frequency = HAL_RCC_GetPCLK3Freq();
2626 break;
2627
2628 case RCC_LPTIM23CLKSOURCE_PLL4:
2629 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2630 frequency = pll4_clocks.PLL4_Q_Frequency;
2631 break;
2632
2633 case RCC_LPTIM23CLKSOURCE_PER:
2634 frequency = RCC_GetCKPERFreq();
2635 break;
2636
2637 case RCC_LPTIM23CLKSOURCE_LSE:
2638 frequency = LSE_VALUE;
2639 break;
2640
2641 case RCC_LPTIM23CLKSOURCE_LSI:
2642 frequency = LSI_VALUE;
2643 break;
2644
2645 default:
2646 frequency = 0;
2647 break;
2648 }
2649 }
2650 break; /* RCC_PERIPHCLK_LPTIM23 */
2651
2652 case RCC_PERIPHCLK_LPTIM45:
2653 {
2654 clksource = __HAL_RCC_GET_LPTIM45_SOURCE();
2655
2656 switch (clksource)
2657 {
2658 case RCC_LPTIM45CLKSOURCE_PCLK3:
2659 frequency = HAL_RCC_GetPCLK3Freq();
2660 break;
2661
2662 case RCC_LPTIM45CLKSOURCE_PLL4:
2663 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2664 frequency = pll4_clocks.PLL4_P_Frequency;
2665 break;
2666
2667 case RCC_LPTIM45CLKSOURCE_PLL3:
2668 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2669 frequency = pll3_clocks.PLL3_Q_Frequency;
2670 break;
2671
2672 case RCC_LPTIM45CLKSOURCE_LSE:
2673 frequency = LSE_VALUE;
2674 break;
2675
2676 case RCC_LPTIM45CLKSOURCE_LSI:
2677 frequency = LSI_VALUE;
2678 break;
2679
2680 case RCC_LPTIM45CLKSOURCE_PER:
2681 frequency = RCC_GetCKPERFreq();
2682 break;
2683
2684 default:
2685 frequency = 0;
2686 break;
2687 }
2688 }
2689 break; /* RCC_PERIPHCLK_LPTIM45 */
2690
2691
2692 case RCC_PERIPHCLK_SAI4:
2693 {
2694 clksource = __HAL_RCC_GET_SAI4_SOURCE();
2695
2696 switch (clksource)
2697 {
2698 case RCC_SAI4CLKSOURCE_PLL4:
2699 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2700 frequency = pll4_clocks.PLL4_Q_Frequency;
2701 break;
2702
2703 case RCC_SAI4CLKSOURCE_PLL3_Q:
2704 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2705 frequency = pll3_clocks.PLL3_Q_Frequency;
2706 break;
2707
2708 case RCC_SAI4CLKSOURCE_PLL3_R:
2709 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2710 frequency = pll3_clocks.PLL3_R_Frequency;
2711 break;
2712
2713 case RCC_SAI4CLKSOURCE_I2SCKIN:
2714 frequency = EXTERNAL_CLOCK_VALUE;
2715 break;
2716
2717 case RCC_SAI4CLKSOURCE_PER:
2718 frequency = RCC_GetCKPERFreq();
2719 break;
2720
2721 default:
2722 frequency = 0;
2723 break;
2724 }
2725 }
2726 break;//RCC_PERIPHCLK_SAI4
2727
2728
2729 case RCC_PERIPHCLK_TEMP:
2730 {
2731 frequency = LSE_VALUE;
2732 }
2733 break;//RCC_PERIPHCLK_TEMP
2734
2735
2736 #if defined(DSI)
2737 case RCC_PERIPHCLK_DSI:
2738 {
2739 clksource = __HAL_RCC_GET_DSI_SOURCE();
2740
2741 switch (clksource)
2742 {
2743 case RCC_DSICLKSOURCE_PHY:
2744 /* It has no sense to ask for DSIPHY freq. because it is generated
2745 * by DSI itself, so send back 0 as kernel frequency
2746 */
2747 frequency = 0;
2748 break;
2749
2750 case RCC_DSICLKSOURCE_PLL4:
2751 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2752 frequency = pll4_clocks.PLL4_P_Frequency;
2753 break;
2754 }
2755 }
2756 break;//RCC_PERIPHCLK_DSI
2757 #endif /*DSI*/
2758
2759 case RCC_PERIPHCLK_LTDC:
2760 {
2761 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2762 frequency = pll4_clocks.PLL4_Q_Frequency;
2763 }
2764 break;//RCC_PERIPHCLK_LTDC
2765
2766
2767 case RCC_PERIPHCLK_USBPHY:
2768 {
2769 clksource = __HAL_RCC_GET_USBPHY_SOURCE();
2770
2771 switch (clksource)
2772 {
2773 case RCC_USBPHYCLKSOURCE_HSE:
2774 frequency = HSE_VALUE;
2775 break;
2776
2777 case RCC_USBPHYCLKSOURCE_PLL4:
2778 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2779 frequency = pll4_clocks.PLL4_R_Frequency;
2780 break;
2781
2782 case RCC_USBPHYCLKSOURCE_HSE2:
2783 frequency = (HSE_VALUE / 2UL);
2784 break;
2785
2786 default:
2787 frequency = 0;
2788 break;
2789 }
2790 }
2791 break;//RCC_PERIPHCLK_USBPHY
2792
2793
2794 case RCC_PERIPHCLK_IWDG2:
2795 {
2796 frequency = LSI_VALUE;
2797 }
2798 break;//RCC_PERIPHCLK_IWDG2
2799
2800
2801 case RCC_PERIPHCLK_DDRPHYC:
2802 {
2803 HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
2804 frequency = pll2_clocks.PLL2_R_Frequency;
2805 }
2806 break;//RCC_PERIPHCLK_DDRPHYC
2807
2808
2809 case RCC_PERIPHCLK_RTC:
2810 {
2811 clksource = __HAL_RCC_GET_RTC_SOURCE();
2812
2813 switch (clksource)
2814 {
2815 case RCC_RTCCLKSOURCE_OFF:
2816 frequency = 0;
2817 break;
2818
2819 case RCC_RTCCLKSOURCE_LSE:
2820 frequency = LSE_VALUE;
2821 break;
2822
2823 case RCC_RTCCLKSOURCE_LSI:
2824 frequency = LSI_VALUE;
2825 break;
2826
2827 case RCC_RTCCLKSOURCE_HSE_DIV:
2828 frequency = (HSE_VALUE / __HAL_RCC_GET_RTC_HSEDIV());
2829 break;
2830 }
2831 }
2832 break;//RCC_PERIPHCLK_RTC
2833
2834
2835 case RCC_PERIPHCLK_IWDG1:
2836 {
2837 frequency = LSI_VALUE;
2838 }
2839 break;//RCC_PERIPHCLK_IWDG1
2840
2841
2842 case RCC_PERIPHCLK_I2C46:
2843 {
2844 clksource = __HAL_RCC_GET_I2C46_SOURCE();
2845
2846 switch (clksource)
2847 {
2848 case RCC_I2C46CLKSOURCE_PCLK5:
2849 frequency = HAL_RCC_GetPCLK5Freq();
2850 break;
2851
2852 case RCC_I2C46CLKSOURCE_PLL3:
2853 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2854 frequency = pll3_clocks.PLL3_Q_Frequency;
2855 break;
2856
2857 case RCC_I2C46CLKSOURCE_HSI:
2858 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2859 break;
2860
2861 case RCC_I2C46CLKSOURCE_CSI:
2862 frequency = CSI_VALUE;
2863 break;
2864
2865 default:
2866 frequency = 0;
2867 break;
2868 }
2869 }
2870 break; /* RCC_PERIPHCLK_I2C46 */
2871
2872
2873 case RCC_PERIPHCLK_SPI6:
2874 {
2875 clksource = __HAL_RCC_GET_SPI6_SOURCE();
2876
2877 switch (clksource)
2878 {
2879 case RCC_SPI6CLKSOURCE_PCLK5:
2880 frequency = HAL_RCC_GetPCLK5Freq();
2881 break;
2882
2883 case RCC_SPI6CLKSOURCE_PLL4:
2884 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2885 frequency = pll4_clocks.PLL4_Q_Frequency;
2886 break;
2887
2888 case RCC_SPI6CLKSOURCE_HSI:
2889 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2890 break;
2891
2892 case RCC_SPI6CLKSOURCE_CSI:
2893 frequency = CSI_VALUE;
2894 break;
2895
2896 case RCC_SPI6CLKSOURCE_HSE:
2897 frequency = HSE_VALUE;
2898 break;
2899
2900 case RCC_SPI6CLKSOURCE_PLL3:
2901 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2902 frequency = pll3_clocks.PLL3_Q_Frequency;
2903 break;
2904
2905 default:
2906 frequency = 0;
2907 break;
2908 }
2909 }
2910 break;//RCC_PERIPHCLK_SPI6
2911
2912 case RCC_PERIPHCLK_USART1:
2913 {
2914 clksource = __HAL_RCC_GET_USART1_SOURCE();
2915
2916 switch (clksource)
2917 {
2918 case RCC_USART1CLKSOURCE_PCLK5:
2919 frequency = HAL_RCC_GetPCLK5Freq();
2920 break;
2921
2922 case RCC_USART1CLKSOURCE_PLL3:
2923 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2924 frequency = pll3_clocks.PLL3_Q_Frequency;
2925 break;
2926
2927 case RCC_USART1CLKSOURCE_HSI:
2928 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2929 break;
2930
2931 case RCC_USART1CLKSOURCE_CSI:
2932 frequency = CSI_VALUE;
2933 break;
2934
2935 case RCC_USART1CLKSOURCE_PLL4:
2936 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2937 frequency = pll4_clocks.PLL4_Q_Frequency;
2938 break;
2939
2940 case RCC_USART1CLKSOURCE_HSE:
2941 frequency = HSE_VALUE;
2942 break;
2943
2944 default:
2945 frequency = 0;
2946 break;
2947 }
2948 }
2949 break;//RCC_PERIPHCLK_USART1
2950
2951
2952 case RCC_PERIPHCLK_STGEN:
2953 {
2954 clksource = __HAL_RCC_GET_STGEN_SOURCE();
2955
2956 switch (clksource)
2957 {
2958 case RCC_STGENCLKSOURCE_HSI:
2959 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2960 break;
2961
2962 case RCC_STGENCLKSOURCE_HSE:
2963 frequency = HSE_VALUE;
2964 break;
2965
2966 default:
2967 frequency = 0;
2968 break;
2969 }
2970 }
2971 break;//RCC_PERIPHCLK_STGEN
2972
2973
2974 case RCC_PERIPHCLK_QSPI:
2975 {
2976 clksource = __HAL_RCC_GET_QSPI_SOURCE();
2977
2978 switch (clksource)
2979 {
2980 case RCC_QSPICLKSOURCE_ACLK:
2981 frequency = HAL_RCC_GetACLKFreq();
2982 break;
2983
2984 case RCC_QSPICLKSOURCE_PLL3:
2985 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2986 frequency = pll3_clocks.PLL3_R_Frequency;
2987 break;
2988
2989 case RCC_QSPICLKSOURCE_PLL4:
2990 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
2991 frequency = pll4_clocks.PLL4_P_Frequency;
2992 break;
2993
2994 case RCC_QSPICLKSOURCE_PER:
2995 frequency = RCC_GetCKPERFreq();
2996 break;
2997
2998 default:
2999 frequency = 0;
3000 break;
3001 }
3002 }
3003 break;//RCC_PERIPHCLK_QSPI
3004
3005
3006 case RCC_PERIPHCLK_ETH:
3007 {
3008 clksource = __HAL_RCC_GET_ETH_SOURCE();
3009
3010 switch (clksource)
3011 {
3012 case RCC_ETHCLKSOURCE_PLL4:
3013 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3014 frequency = pll4_clocks.PLL4_P_Frequency;
3015 break;
3016
3017 case RCC_ETHCLKSOURCE_PLL3:
3018 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3019 frequency = pll3_clocks.PLL3_Q_Frequency;
3020 break;
3021
3022 default:
3023 frequency = 0;
3024 break;
3025 }
3026 }
3027 break;//RCC_PERIPHCLK_ETH
3028
3029
3030 case RCC_PERIPHCLK_FMC:
3031 {
3032 clksource = __HAL_RCC_GET_FMC_SOURCE();
3033
3034 switch (clksource)
3035 {
3036 case RCC_FMCCLKSOURCE_ACLK:
3037 frequency = HAL_RCC_GetACLKFreq();
3038 break;
3039
3040 case RCC_FMCCLKSOURCE_PLL3:
3041 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3042 frequency = pll3_clocks.PLL3_R_Frequency;
3043 break;
3044
3045 case RCC_FMCCLKSOURCE_PLL4:
3046 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3047 frequency = pll4_clocks.PLL4_P_Frequency;
3048 break;
3049
3050 case RCC_FMCCLKSOURCE_PER:
3051 frequency = RCC_GetCKPERFreq();
3052 break;
3053
3054 }
3055 }
3056 break;//RCC_PERIPHCLK_FMC
3057
3058
3059 case RCC_PERIPHCLK_GPU:
3060 {
3061 HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
3062 frequency = pll2_clocks.PLL2_Q_Frequency;
3063 }
3064 break;//RCC_PERIPHCLK_GPU
3065
3066
3067 case RCC_PERIPHCLK_USBO:
3068 {
3069 clksource = __HAL_RCC_GET_USBO_SOURCE();
3070
3071 switch (clksource)
3072 {
3073 case RCC_USBOCLKSOURCE_PLL4:
3074 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3075 frequency = pll4_clocks.PLL4_R_Frequency;
3076 break;
3077
3078 case RCC_USBOCLKSOURCE_PHY:
3079 frequency = USB_PHY_VALUE;
3080 break;
3081 }
3082 }
3083 break;//RCC_PERIPHCLK_USBO
3084
3085
3086 case RCC_PERIPHCLK_SDMMC3:
3087 {
3088 clksource = __HAL_RCC_GET_SDMMC3_SOURCE();
3089
3090 switch (clksource)
3091 {
3092 case RCC_SDMMC3CLKSOURCE_HCLK2:
3093 frequency = HAL_RCC_GetHCLK2Freq();
3094 break;
3095
3096 case RCC_SDMMC3CLKSOURCE_PLL3:
3097 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3098 frequency = pll3_clocks.PLL3_R_Frequency;
3099 break;
3100
3101 case RCC_SDMMC3CLKSOURCE_PLL4:
3102 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3103 frequency = pll4_clocks.PLL4_P_Frequency;
3104 break;
3105
3106 case RCC_SDMMC3CLKSOURCE_HSI:
3107 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
3108 break;
3109
3110 default:
3111 frequency = 0;
3112 break;
3113 }
3114 }
3115 break;//RCC_PERIPHCLK_SDMMC3
3116
3117
3118 case RCC_PERIPHCLK_ADC:
3119 {
3120 clksource = __HAL_RCC_GET_ADC_SOURCE();
3121
3122 switch (clksource)
3123 {
3124 case RCC_ADCCLKSOURCE_PLL4:
3125 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3126 frequency = pll4_clocks.PLL4_R_Frequency;
3127 break;
3128
3129 case RCC_ADCCLKSOURCE_PER:
3130 frequency = RCC_GetCKPERFreq();
3131 break;
3132
3133 case RCC_ADCCLKSOURCE_PLL3:
3134 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3135 frequency = pll3_clocks.PLL3_Q_Frequency;
3136 break;
3137
3138 default:
3139 frequency = 0;
3140 break;
3141 }
3142 }
3143 break; /* RCC_PERIPHCLK_ADC */
3144
3145
3146 case RCC_PERIPHCLK_RNG2:
3147 {
3148 clksource = __HAL_RCC_GET_RNG2_SOURCE();
3149
3150 switch (clksource)
3151 {
3152 case RCC_RNG2CLKSOURCE_CSI:
3153 frequency = CSI_VALUE;
3154 break;
3155
3156 case RCC_RNG2CLKSOURCE_PLL4:
3157 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3158 frequency = pll4_clocks.PLL4_R_Frequency;
3159 break;
3160
3161 case RCC_RNG2CLKSOURCE_LSE:
3162 frequency = LSE_VALUE;
3163 break;
3164
3165 case RCC_RNG2CLKSOURCE_LSI:
3166 frequency = LSI_VALUE;
3167 break;
3168 }
3169 }
3170 break;//RCC_PERIPHCLK_RNG2
3171
3172
3173 case RCC_PERIPHCLK_RNG1:
3174 {
3175 clksource = __HAL_RCC_GET_RNG1_SOURCE();
3176
3177 switch (clksource)
3178 {
3179 case RCC_RNG1CLKSOURCE_CSI:
3180 frequency = CSI_VALUE;
3181 break;
3182
3183 case RCC_RNG1CLKSOURCE_PLL4:
3184 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3185 frequency = pll4_clocks.PLL4_R_Frequency;
3186 break;
3187
3188 case RCC_RNG1CLKSOURCE_LSE:
3189 frequency = LSE_VALUE;
3190 break;
3191
3192 case RCC_RNG1CLKSOURCE_LSI:
3193 frequency = LSI_VALUE;
3194 break;
3195 }
3196 }
3197 break;//RCC_PERIPHCLK_RNG1
3198
3199 case RCC_PERIPHCLK_SDMMC12:
3200 {
3201 clksource = __HAL_RCC_GET_SDMMC12_SOURCE();
3202
3203 switch (clksource)
3204 {
3205 case RCC_SDMMC12CLKSOURCE_HCLK6:
3206 frequency = HAL_RCC_GetHCLK6Freq();
3207 break;
3208
3209 case RCC_SDMMC12CLKSOURCE_PLL3:
3210 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
3211 frequency = pll3_clocks.PLL3_R_Frequency;
3212 break;
3213
3214 case RCC_SDMMC12CLKSOURCE_PLL4:
3215 HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
3216 frequency = pll4_clocks.PLL4_P_Frequency;
3217 break;
3218
3219 case RCC_SDMMC12CLKSOURCE_HSI:
3220 frequency = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
3221 break;
3222
3223 default:
3224 frequency = 0;
3225 break;
3226 }
3227 }
3228 break; /* RCC_PERIPHCLK_SDMMC12 */
3229
3230 case RCC_PERIPHCLK_TIMG1:
3231 {
3232 frequency = HAL_RCC_GetMCUFreq();
3233 if (__HAL_RCC_GET_TIMG1PRES() == RCC_TIMG1PRES_ACTIVATED)
3234 {
3235 switch (__HAL_RCC_GET_APB1_DIV())
3236 {
3237 case RCC_APB1_DIV1:
3238 case RCC_APB1_DIV2:
3239 case RCC_APB1_DIV4:
3240 break;
3241 case RCC_APB1_DIV8:
3242 frequency /= 2UL;
3243 break;
3244 case RCC_APB1_DIV16:
3245 frequency /= 4UL;
3246 break;
3247 }
3248 }
3249 else
3250 {
3251 switch (__HAL_RCC_GET_APB1_DIV())
3252 {
3253 case RCC_APB1_DIV1:
3254 case RCC_APB1_DIV2:
3255 break;
3256 case RCC_APB1_DIV4:
3257 frequency /= 2UL;
3258 break;
3259 case RCC_APB1_DIV8:
3260 frequency /= 4UL;
3261 break;
3262 case RCC_APB1_DIV16:
3263 frequency /= 8UL;
3264 break;
3265 }
3266 }
3267 }
3268 break;
3269
3270
3271 case RCC_PERIPHCLK_TIMG2:
3272 {
3273 frequency = HAL_RCC_GetMCUFreq();
3274 if (__HAL_RCC_GET_TIMG2PRES() == RCC_TIMG2PRES_ACTIVATED)
3275 {
3276 switch (__HAL_RCC_GET_APB2_DIV())
3277 {
3278 case RCC_APB2_DIV1:
3279 case RCC_APB2_DIV2:
3280 case RCC_APB2_DIV4:
3281 break;
3282 case RCC_APB2_DIV8:
3283 frequency /= 2UL;
3284 break;
3285 case RCC_APB2_DIV16:
3286 frequency /= 4UL;
3287 break;
3288 }
3289 }
3290 else
3291 {
3292 switch (__HAL_RCC_GET_APB2_DIV())
3293 {
3294 case RCC_APB2_DIV1:
3295 case RCC_APB2_DIV2:
3296 break;
3297 case RCC_APB2_DIV4:
3298 frequency /= 2UL;
3299 break;
3300 case RCC_APB2_DIV8:
3301 frequency /= 4UL;
3302 break;
3303 case RCC_APB2_DIV16:
3304 frequency /= 8UL;
3305 break;
3306 }
3307 }
3308 }
3309 break;
3310
3311 }
3312
3313 return (frequency);
3314 }
3315
3316 #ifdef CORE_CA7
3317 /**
3318 * @brief Control the enable boot function when the system exits from STANDBY
3319 * @param RCC_BootCx: Boot Core to be enabled (set to 1)
3320 * This parameter can be one (or both) of the following values:
3321 * @arg RCC_BOOT_C1: CA7 core selection
3322 * @arg RCC_BOOT_C2: CM4 core selection
3323 *
3324 * @note Next combinations are possible:
3325 * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
3326 * 0 0 MPU boots, MCU does not boot
3327 * 0 1 Only MCU boots
3328 * 1 0 Only MPU boots
3329 * 1 1 MPU and MCU boot
3330 *
3331 * @note This function is reset when a system reset occurs, but not when the
3332 * circuit exits from STANDBY (rst_app reset)
3333 * @note This function can only be called by the CA7
3334 * @retval None
3335 */
HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)3336 void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
3337 {
3338 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3339 SET_BIT(RCC->MP_BOOTCR, RCC_BootCx);
3340 }
3341
3342 /**
3343 * @brief Control the disable boot function when the system exits from STANDBY
3344 * @param RCC_BootCx: Boot Core to be disabled (set to 0)
3345 * This parameter can be one (or both) of the following values:
3346 * @arg RCC_BOOT_C1: CA7 core selection
3347 * @arg RCC_BOOT_C2: CM4 core selection
3348 *
3349 * @note Next combinations are possible:
3350 * RCC_BOOT_C1 RCC_BOOT_C2 Expected result
3351 * 0 0 MPU boots, MCU does not boot
3352 * 0 1 Only MCU boots
3353 * 1 0 Only MPU boots
3354 * 1 1 MPU and MCU boot
3355 *
3356 * @note This function is reset when a system reset occurs, but not when the
3357 * circuit exits from STANDBY (rst_app reset)
3358 * @note This function can only be called by the CA7
3359 * @retval None
3360 */
HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx)3361 void HAL_RCCEx_DisableBootCore(uint32_t RCC_BootCx)
3362 {
3363 assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
3364 CLEAR_BIT(RCC->MP_BOOTCR, RCC_BootCx);
3365 }
3366
3367
3368 /**
3369 * @brief The MCU will be set in HOLD_BOOT when the next MCU core reset occurs
3370 * @retval None
3371 */
HAL_RCCEx_HoldBootMCU(void)3372 void HAL_RCCEx_HoldBootMCU(void)
3373 {
3374 CLEAR_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
3375 }
3376
3377 /**
3378 * @brief The MCU will not be in HOLD_BOOT mode when the next MCU core reset occurs.
3379 * @note If the MCU was in HOLD_BOOT it will cause the MCU to boot.
3380 * @retval None
3381 */
HAL_RCCEx_BootMCU(void)3382 void HAL_RCCEx_BootMCU(void)
3383 {
3384 SET_BIT(RCC->MP_GCR, RCC_MP_GCR_BOOT_MCU);
3385 }
3386
3387 #endif /*CORE_CA7*/
3388
3389 /**
3390 * @}
3391 */
3392
3393 /**
3394 * @}
3395 */
3396
3397 #endif /* HAL_RCC_MODULE_ENABLED */
3398 /**
3399 * @}
3400 */
3401
3402 /**
3403 * @}
3404 */
3405
