1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_HSEM_H
21 #define STM32MP1xx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_COREID COREID Defines
53 * @{
54 */
55 #define LL_HSEM_COREID_NONE 0U
56 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
57 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT
58 /**
59 * @}
60 */
61
62 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
63 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
64 * @{
65 */
66
67 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
68 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
69 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
70 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
71 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
72 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
73 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
74 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
75 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
76 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
77 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
78 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
79 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
80 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
81 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
82 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
83 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
84 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
85 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
86 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
87 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
88 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
89 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
90 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
91 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
92 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
93 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
94 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
95 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
96 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
97 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
98 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
99 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
100 /**
101 * @}
102 */
103
104 /**
105 * @}
106 */
107
108 /* Exported macro ------------------------------------------------------------*/
109 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
110 * @{
111 */
112
113 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
114 * @{
115 */
116
117 /**
118 * @brief Write a value in HSEM register
119 * @param __INSTANCE__ HSEM Instance
120 * @param __REG__ Register to be written
121 * @param __VALUE__ Value to be written in the register
122 * @retval None
123 */
124 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
125
126 /**
127 * @brief Read a value in HSEM register
128 * @param __INSTANCE__ HSEM Instance
129 * @param __REG__ Register to be read
130 * @retval Register value
131 */
132 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
133 /**
134 * @}
135 */
136
137 /**
138 * @}
139 */
140
141 /* Exported functions --------------------------------------------------------*/
142 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
143 * @{
144 */
145
146 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
147 * @{
148 */
149
150
151 /**
152 * @brief Return 1 if the semaphore is locked, else return 0.
153 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
154 * @param HSEMx HSEM Instance.
155 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
156 * @retval State of bit (1 or 0).
157 */
LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef * HSEMx,uint32_t Semaphore)158 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
159 {
160 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
161 }
162
163 /**
164 * @brief Get core id.
165 * @rmtoll R COREID LL_HSEM_GetCoreId
166 * @param HSEMx HSEM Instance.
167 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
168 * @retval Returned value can be one of the following values:
169 * @arg @ref LL_HSEM_COREID_NONE
170 * @arg @ref LL_HSEM_COREID_CPU1
171 */
LL_HSEM_GetCoreId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)172 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
173 {
174 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
175 }
176
177 /**
178 * @brief Get process id.
179 * @rmtoll R PROCID LL_HSEM_GetProcessId
180 * @param HSEMx HSEM Instance.
181 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
182 * @retval Process number. Value between Min_Data=0 and Max_Data=255
183 */
LL_HSEM_GetProcessId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)184 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
185 {
186 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
187 }
188
189 /**
190 * @brief Get the lock by writing in R register.
191 * @note The R register has to be read to determined if the lock is taken.
192 * @rmtoll R LOCK LL_HSEM_SetLock
193 * @rmtoll R COREID LL_HSEM_SetLock
194 * @rmtoll R PROCID LL_HSEM_SetLock
195 * @param HSEMx HSEM Instance.
196 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
197 * @param process Process id. Value between Min_Data=0 and Max_Data=255
198 * @retval None
199 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)200 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
201 {
202 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
203 }
204
205 /**
206 * @brief Get the lock with 2-step lock.
207 * @rmtoll R LOCK LL_HSEM_2StepLock
208 * @rmtoll R COREID LL_HSEM_2StepLock
209 * @rmtoll R PROCID LL_HSEM_2StepLock
210 * @param HSEMx HSEM Instance.
211 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
212 * @param process Process id. Value between Min_Data=0 and Max_Data=255
213 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
214 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)215 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
216 {
217 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
218 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
219 }
220
221 /**
222 * @brief Get the lock with 1-step lock.
223 * @rmtoll RLR LOCK LL_HSEM_1StepLock
224 * @rmtoll RLR COREID LL_HSEM_1StepLock
225 * @rmtoll RLR PROCID LL_HSEM_1StepLock
226 * @param HSEMx HSEM Instance.
227 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
228 * @retval 1 lock fail, 0 lock successful or already locked by same core
229 */
LL_HSEM_1StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore)230 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
231 {
232 return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
233 }
234
235 /**
236 * @brief Release the lock of the semaphore.
237 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
238 * @rmtoll R LOCK LL_HSEM_ReleaseLock
239 * @param HSEMx HSEM Instance.
240 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
241 * @param process Process number. Value between Min_Data=0 and Max_Data=255
242 * @retval None
243 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)244 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
245 {
246 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
247 }
248
249 /**
250 * @brief Get the lock status of the semaphore.
251 * @rmtoll R LOCK LL_HSEM_GetStatus
252 * @param HSEMx HSEM Instance.
253 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
254 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(HSEM_TypeDef * HSEMx,uint32_t Semaphore)255 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
256 {
257 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
258 }
259
260 /**
261 * @brief Set the key.
262 * @rmtoll KEYR KEY LL_HSEM_SetKey
263 * @param HSEMx HSEM Instance.
264 * @param key Key value.
265 * @retval None
266 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)267 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
268 {
269 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
270 }
271
272 /**
273 * @brief Get the key.
274 * @rmtoll KEYR KEY LL_HSEM_GetKey
275 * @param HSEMx HSEM Instance.
276 * @retval key to unlock all semaphore from the same core
277 */
LL_HSEM_GetKey(HSEM_TypeDef * HSEMx)278 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
279 {
280 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
281 }
282
283 /**
284 * @brief Release all semaphore with the same core id.
285 * @rmtoll CR KEY LL_HSEM_ResetAllLock
286 * @param HSEMx HSEM Instance.
287 * @param key Key value.
288 * @param core This parameter can be one of the following values:
289 * @arg @ref LL_HSEM_COREID_CPU1
290 * @retval None
291 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core)292 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
293 {
294 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
295 }
296
297 /**
298 * @}
299 */
300
301 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
302 * @{
303 */
304
305 /**
306 * @brief Enable interrupt.
307 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER
308 * @param HSEMx HSEM Instance.
309 * @param SemaphoreMask This parameter can be a combination of the following values:
310 * @arg @ref LL_HSEM_SEMAPHORE_0
311 * @arg @ref LL_HSEM_SEMAPHORE_1
312 * @arg @ref LL_HSEM_SEMAPHORE_2
313 * @arg @ref LL_HSEM_SEMAPHORE_3
314 * @arg @ref LL_HSEM_SEMAPHORE_4
315 * @arg @ref LL_HSEM_SEMAPHORE_5
316 * @arg @ref LL_HSEM_SEMAPHORE_6
317 * @arg @ref LL_HSEM_SEMAPHORE_7
318 * @arg @ref LL_HSEM_SEMAPHORE_8
319 * @arg @ref LL_HSEM_SEMAPHORE_9
320 * @arg @ref LL_HSEM_SEMAPHORE_10
321 * @arg @ref LL_HSEM_SEMAPHORE_11
322 * @arg @ref LL_HSEM_SEMAPHORE_12
323 * @arg @ref LL_HSEM_SEMAPHORE_13
324 * @arg @ref LL_HSEM_SEMAPHORE_14
325 * @arg @ref LL_HSEM_SEMAPHORE_15
326 * @arg @ref LL_HSEM_SEMAPHORE_16
327 * @arg @ref LL_HSEM_SEMAPHORE_17
328 * @arg @ref LL_HSEM_SEMAPHORE_18
329 * @arg @ref LL_HSEM_SEMAPHORE_19
330 * @arg @ref LL_HSEM_SEMAPHORE_20
331 * @arg @ref LL_HSEM_SEMAPHORE_21
332 * @arg @ref LL_HSEM_SEMAPHORE_22
333 * @arg @ref LL_HSEM_SEMAPHORE_23
334 * @arg @ref LL_HSEM_SEMAPHORE_24
335 * @arg @ref LL_HSEM_SEMAPHORE_25
336 * @arg @ref LL_HSEM_SEMAPHORE_26
337 * @arg @ref LL_HSEM_SEMAPHORE_27
338 * @arg @ref LL_HSEM_SEMAPHORE_28
339 * @arg @ref LL_HSEM_SEMAPHORE_29
340 * @arg @ref LL_HSEM_SEMAPHORE_30
341 * @arg @ref LL_HSEM_SEMAPHORE_31
342 * @arg @ref LL_HSEM_SEMAPHORE_ALL
343 * @retval None
344 */
LL_HSEM_EnableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)345 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
346 {
347 SET_BIT(HSEMx->C1IER, SemaphoreMask);
348 }
349
350 /**
351 * @brief Disable interrupt.
352 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER
353 * @param HSEMx HSEM Instance.
354 * @param SemaphoreMask This parameter can be a combination of the following values:
355 * @arg @ref LL_HSEM_SEMAPHORE_0
356 * @arg @ref LL_HSEM_SEMAPHORE_1
357 * @arg @ref LL_HSEM_SEMAPHORE_2
358 * @arg @ref LL_HSEM_SEMAPHORE_3
359 * @arg @ref LL_HSEM_SEMAPHORE_4
360 * @arg @ref LL_HSEM_SEMAPHORE_5
361 * @arg @ref LL_HSEM_SEMAPHORE_6
362 * @arg @ref LL_HSEM_SEMAPHORE_7
363 * @arg @ref LL_HSEM_SEMAPHORE_8
364 * @arg @ref LL_HSEM_SEMAPHORE_9
365 * @arg @ref LL_HSEM_SEMAPHORE_10
366 * @arg @ref LL_HSEM_SEMAPHORE_11
367 * @arg @ref LL_HSEM_SEMAPHORE_12
368 * @arg @ref LL_HSEM_SEMAPHORE_13
369 * @arg @ref LL_HSEM_SEMAPHORE_14
370 * @arg @ref LL_HSEM_SEMAPHORE_15
371 * @arg @ref LL_HSEM_SEMAPHORE_16
372 * @arg @ref LL_HSEM_SEMAPHORE_17
373 * @arg @ref LL_HSEM_SEMAPHORE_18
374 * @arg @ref LL_HSEM_SEMAPHORE_19
375 * @arg @ref LL_HSEM_SEMAPHORE_20
376 * @arg @ref LL_HSEM_SEMAPHORE_21
377 * @arg @ref LL_HSEM_SEMAPHORE_22
378 * @arg @ref LL_HSEM_SEMAPHORE_23
379 * @arg @ref LL_HSEM_SEMAPHORE_24
380 * @arg @ref LL_HSEM_SEMAPHORE_25
381 * @arg @ref LL_HSEM_SEMAPHORE_26
382 * @arg @ref LL_HSEM_SEMAPHORE_27
383 * @arg @ref LL_HSEM_SEMAPHORE_28
384 * @arg @ref LL_HSEM_SEMAPHORE_29
385 * @arg @ref LL_HSEM_SEMAPHORE_30
386 * @arg @ref LL_HSEM_SEMAPHORE_31
387 * @arg @ref LL_HSEM_SEMAPHORE_ALL
388 * @retval None
389 */
LL_HSEM_DisableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)390 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
391 {
392 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
393 }
394
395 /**
396 * @brief Check if interrupt is enabled.
397 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
398 * @param HSEMx HSEM Instance.
399 * @param SemaphoreMask This parameter can be a combination of the following values:
400 * @arg @ref LL_HSEM_SEMAPHORE_0
401 * @arg @ref LL_HSEM_SEMAPHORE_1
402 * @arg @ref LL_HSEM_SEMAPHORE_2
403 * @arg @ref LL_HSEM_SEMAPHORE_3
404 * @arg @ref LL_HSEM_SEMAPHORE_4
405 * @arg @ref LL_HSEM_SEMAPHORE_5
406 * @arg @ref LL_HSEM_SEMAPHORE_6
407 * @arg @ref LL_HSEM_SEMAPHORE_7
408 * @arg @ref LL_HSEM_SEMAPHORE_8
409 * @arg @ref LL_HSEM_SEMAPHORE_9
410 * @arg @ref LL_HSEM_SEMAPHORE_10
411 * @arg @ref LL_HSEM_SEMAPHORE_11
412 * @arg @ref LL_HSEM_SEMAPHORE_12
413 * @arg @ref LL_HSEM_SEMAPHORE_13
414 * @arg @ref LL_HSEM_SEMAPHORE_14
415 * @arg @ref LL_HSEM_SEMAPHORE_15
416 * @arg @ref LL_HSEM_SEMAPHORE_16
417 * @arg @ref LL_HSEM_SEMAPHORE_17
418 * @arg @ref LL_HSEM_SEMAPHORE_18
419 * @arg @ref LL_HSEM_SEMAPHORE_19
420 * @arg @ref LL_HSEM_SEMAPHORE_20
421 * @arg @ref LL_HSEM_SEMAPHORE_21
422 * @arg @ref LL_HSEM_SEMAPHORE_22
423 * @arg @ref LL_HSEM_SEMAPHORE_23
424 * @arg @ref LL_HSEM_SEMAPHORE_24
425 * @arg @ref LL_HSEM_SEMAPHORE_25
426 * @arg @ref LL_HSEM_SEMAPHORE_26
427 * @arg @ref LL_HSEM_SEMAPHORE_27
428 * @arg @ref LL_HSEM_SEMAPHORE_28
429 * @arg @ref LL_HSEM_SEMAPHORE_29
430 * @arg @ref LL_HSEM_SEMAPHORE_30
431 * @arg @ref LL_HSEM_SEMAPHORE_31
432 * @arg @ref LL_HSEM_SEMAPHORE_ALL
433 * @retval State of bit (1 or 0).
434 */
LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)435 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
436 {
437 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
438 }
439
440
441 /**
442 * @}
443 */
444
445 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
446 * @{
447 */
448
449 /**
450 * @brief Clear interrupt status.
451 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
452 * @param HSEMx HSEM Instance.
453 * @param SemaphoreMask This parameter can be a combination of the following values:
454 * @arg @ref LL_HSEM_SEMAPHORE_0
455 * @arg @ref LL_HSEM_SEMAPHORE_1
456 * @arg @ref LL_HSEM_SEMAPHORE_2
457 * @arg @ref LL_HSEM_SEMAPHORE_3
458 * @arg @ref LL_HSEM_SEMAPHORE_4
459 * @arg @ref LL_HSEM_SEMAPHORE_5
460 * @arg @ref LL_HSEM_SEMAPHORE_6
461 * @arg @ref LL_HSEM_SEMAPHORE_7
462 * @arg @ref LL_HSEM_SEMAPHORE_8
463 * @arg @ref LL_HSEM_SEMAPHORE_9
464 * @arg @ref LL_HSEM_SEMAPHORE_10
465 * @arg @ref LL_HSEM_SEMAPHORE_11
466 * @arg @ref LL_HSEM_SEMAPHORE_12
467 * @arg @ref LL_HSEM_SEMAPHORE_13
468 * @arg @ref LL_HSEM_SEMAPHORE_14
469 * @arg @ref LL_HSEM_SEMAPHORE_15
470 * @arg @ref LL_HSEM_SEMAPHORE_16
471 * @arg @ref LL_HSEM_SEMAPHORE_17
472 * @arg @ref LL_HSEM_SEMAPHORE_18
473 * @arg @ref LL_HSEM_SEMAPHORE_19
474 * @arg @ref LL_HSEM_SEMAPHORE_20
475 * @arg @ref LL_HSEM_SEMAPHORE_21
476 * @arg @ref LL_HSEM_SEMAPHORE_22
477 * @arg @ref LL_HSEM_SEMAPHORE_23
478 * @arg @ref LL_HSEM_SEMAPHORE_24
479 * @arg @ref LL_HSEM_SEMAPHORE_25
480 * @arg @ref LL_HSEM_SEMAPHORE_26
481 * @arg @ref LL_HSEM_SEMAPHORE_27
482 * @arg @ref LL_HSEM_SEMAPHORE_28
483 * @arg @ref LL_HSEM_SEMAPHORE_29
484 * @arg @ref LL_HSEM_SEMAPHORE_30
485 * @arg @ref LL_HSEM_SEMAPHORE_31
486 * @arg @ref LL_HSEM_SEMAPHORE_ALL
487 * @retval None
488 */
LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)489 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
490 {
491 WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
492 }
493
494 /**
495 * @brief Get interrupt status from ISR register.
496 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
497 * @param HSEMx HSEM Instance.
498 * @param SemaphoreMask This parameter can be a combination of the following values:
499 * @arg @ref LL_HSEM_SEMAPHORE_0
500 * @arg @ref LL_HSEM_SEMAPHORE_1
501 * @arg @ref LL_HSEM_SEMAPHORE_2
502 * @arg @ref LL_HSEM_SEMAPHORE_3
503 * @arg @ref LL_HSEM_SEMAPHORE_4
504 * @arg @ref LL_HSEM_SEMAPHORE_5
505 * @arg @ref LL_HSEM_SEMAPHORE_6
506 * @arg @ref LL_HSEM_SEMAPHORE_7
507 * @arg @ref LL_HSEM_SEMAPHORE_8
508 * @arg @ref LL_HSEM_SEMAPHORE_9
509 * @arg @ref LL_HSEM_SEMAPHORE_10
510 * @arg @ref LL_HSEM_SEMAPHORE_11
511 * @arg @ref LL_HSEM_SEMAPHORE_12
512 * @arg @ref LL_HSEM_SEMAPHORE_13
513 * @arg @ref LL_HSEM_SEMAPHORE_14
514 * @arg @ref LL_HSEM_SEMAPHORE_15
515 * @arg @ref LL_HSEM_SEMAPHORE_16
516 * @arg @ref LL_HSEM_SEMAPHORE_17
517 * @arg @ref LL_HSEM_SEMAPHORE_18
518 * @arg @ref LL_HSEM_SEMAPHORE_19
519 * @arg @ref LL_HSEM_SEMAPHORE_20
520 * @arg @ref LL_HSEM_SEMAPHORE_21
521 * @arg @ref LL_HSEM_SEMAPHORE_22
522 * @arg @ref LL_HSEM_SEMAPHORE_23
523 * @arg @ref LL_HSEM_SEMAPHORE_24
524 * @arg @ref LL_HSEM_SEMAPHORE_25
525 * @arg @ref LL_HSEM_SEMAPHORE_26
526 * @arg @ref LL_HSEM_SEMAPHORE_27
527 * @arg @ref LL_HSEM_SEMAPHORE_28
528 * @arg @ref LL_HSEM_SEMAPHORE_29
529 * @arg @ref LL_HSEM_SEMAPHORE_30
530 * @arg @ref LL_HSEM_SEMAPHORE_31
531 * @arg @ref LL_HSEM_SEMAPHORE_ALL
532 * @retval State of bit (1 or 0).
533 */
LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)534 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
535 {
536 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
537 }
538
539 /**
540 * @brief Get interrupt status from MISR register.
541 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
542 * @param HSEMx HSEM Instance.
543 * @param SemaphoreMask This parameter can be a combination of the following values:
544 * @arg @ref LL_HSEM_SEMAPHORE_0
545 * @arg @ref LL_HSEM_SEMAPHORE_1
546 * @arg @ref LL_HSEM_SEMAPHORE_2
547 * @arg @ref LL_HSEM_SEMAPHORE_3
548 * @arg @ref LL_HSEM_SEMAPHORE_4
549 * @arg @ref LL_HSEM_SEMAPHORE_5
550 * @arg @ref LL_HSEM_SEMAPHORE_6
551 * @arg @ref LL_HSEM_SEMAPHORE_7
552 * @arg @ref LL_HSEM_SEMAPHORE_8
553 * @arg @ref LL_HSEM_SEMAPHORE_9
554 * @arg @ref LL_HSEM_SEMAPHORE_10
555 * @arg @ref LL_HSEM_SEMAPHORE_11
556 * @arg @ref LL_HSEM_SEMAPHORE_12
557 * @arg @ref LL_HSEM_SEMAPHORE_13
558 * @arg @ref LL_HSEM_SEMAPHORE_14
559 * @arg @ref LL_HSEM_SEMAPHORE_15
560 * @arg @ref LL_HSEM_SEMAPHORE_16
561 * @arg @ref LL_HSEM_SEMAPHORE_17
562 * @arg @ref LL_HSEM_SEMAPHORE_18
563 * @arg @ref LL_HSEM_SEMAPHORE_19
564 * @arg @ref LL_HSEM_SEMAPHORE_20
565 * @arg @ref LL_HSEM_SEMAPHORE_21
566 * @arg @ref LL_HSEM_SEMAPHORE_22
567 * @arg @ref LL_HSEM_SEMAPHORE_23
568 * @arg @ref LL_HSEM_SEMAPHORE_24
569 * @arg @ref LL_HSEM_SEMAPHORE_25
570 * @arg @ref LL_HSEM_SEMAPHORE_26
571 * @arg @ref LL_HSEM_SEMAPHORE_27
572 * @arg @ref LL_HSEM_SEMAPHORE_28
573 * @arg @ref LL_HSEM_SEMAPHORE_29
574 * @arg @ref LL_HSEM_SEMAPHORE_30
575 * @arg @ref LL_HSEM_SEMAPHORE_31
576 * @arg @ref LL_HSEM_SEMAPHORE_ALL
577 * @retval State of bit (1 or 0).
578 */
LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)579 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
580 {
581 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
582 }
583
584 /**
585 * @}
586 */
587
588 /**
589 * @}
590 */
591
592 /**
593 * @}
594 */
595
596 #endif /* defined(HSEM) */
597
598 /**
599 * @}
600 */
601
602 #ifdef __cplusplus
603 }
604 #endif
605
606 #endif /* __STM32MP1xx_LL_HSEM_H */
607
