1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_spi.h 4 * @author MCD Application Team 5 * @brief Header file of SPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_SPI_H 21 #define STM32MP1xx_HAL_SPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /** @addtogroup STM32MP1xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup SPI 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup SPI_Exported_Types SPI Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief SPI Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Mode; /*!< Specifies the SPI operating mode. 49 This parameter can be a value of @ref SPI_Mode */ 50 51 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 52 This parameter can be a value of @ref SPI_Direction */ 53 54 uint32_t DataSize; /*!< Specifies the SPI data size. 55 This parameter can be a value of @ref SPI_Data_Size */ 56 57 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 58 This parameter can be a value of @ref SPI_Clock_Polarity */ 59 60 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 61 This parameter can be a value of @ref SPI_Clock_Phase */ 62 63 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 64 hardware (NSS pin) or by software using the SSI bit. 65 This parameter can be a value of 66 @ref SPI_Slave_Select_Management */ 67 68 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 69 used to configure the transmit and receive SCK clock. 70 This parameter can be a value of @ref SPI_BaudRate_Prescaler 71 @note The communication clock is derived from the master 72 clock. The slave clock does not need to be set. */ 73 74 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 75 This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ 76 77 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 78 This parameter can be a value of @ref SPI_TI_Mode */ 79 80 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 81 This parameter can be a value of @ref SPI_CRC_Calculation */ 82 83 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 84 This parameter must be an odd number between 85 Min_Data = 0 and Max_Data = 65535 */ 86 87 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 88 This parameter can be a value of @ref SPI_CRC_length */ 89 90 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 91 This parameter can be a value of @ref SPI_NSSP_Mode 92 This mode is activated by the SSOM bit in the SPIx_CR2 register 93 and it takes effect only if the SPI interface is configured 94 as Motorola SPI master (FRF=0). */ 95 96 uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal 97 (present on SS pin) is considered as active one. 98 This parameter can be a value of @ref SPI_NSS_Polarity */ 99 100 uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. 101 This parameter can be a value of @ref SPI_Fifo_Threshold */ 102 103 uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for 104 the CRC calculation. This parameter can be a value of 105 @ref SPI_CRC_Calculation_Initialization_Pattern */ 106 107 uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for 108 the CRC calculation. This parameter can be a value of 109 @ref SPI_CRC_Calculation_Initialization_Pattern */ 110 111 uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle 112 periods, inserted additionally between active edge of SS 113 and first data transaction start in master mode. 114 This parameter can be a value of @ref SPI_Master_SS_Idleness */ 115 116 uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) 117 inserted between two consecutive data frames in master mode. 118 This parameter can be a value of 119 @ref SPI_Master_InterData_Idleness */ 120 121 uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode 122 and automatic management in order to avoid overrun condition. 123 This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ 124 125 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state 126 This parameter can be a value of @ref SPI_Master_Keep_IO_State */ 127 128 uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions 129 This parameter can be a value of @ref SPI_IO_Swap */ 130 } SPI_InitTypeDef; 131 132 /** 133 * @brief HAL SPI State structure definition 134 */ 135 typedef enum 136 { 137 HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ 138 HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ 139 HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ 140 HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ 141 HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ 142 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ 143 HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ 144 HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ 145 } HAL_SPI_StateTypeDef; 146 147 #if defined(USE_SPI_RELOAD_TRANSFER) 148 /** 149 * @brief SPI Reload Structure definition 150 */ 151 typedef struct 152 { 153 const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 154 155 uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ 156 157 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 158 159 uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */ 160 161 uint32_t Requested; /*!< SPI reload request */ 162 163 } SPI_ReloadTypeDef; 164 #endif /* USE_SPI_RELOAD_TRANSFER */ 165 166 /** 167 * @brief SPI handle Structure definition 168 */ 169 typedef struct __SPI_HandleTypeDef 170 { 171 SPI_TypeDef *Instance; /*!< SPI registers base address */ 172 173 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 174 175 const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 176 177 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 178 179 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 180 181 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 182 183 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 184 185 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 186 187 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 188 189 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 190 191 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 192 193 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 194 195 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 196 197 HAL_LockTypeDef Lock; /*!< Locking object */ 198 199 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 200 201 __IO uint32_t ErrorCode; /*!< SPI Error code */ 202 203 #if defined(USE_SPI_RELOAD_TRANSFER) 204 205 SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */ 206 207 #endif /* USE_SPI_RELOAD_TRANSFER */ 208 209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 210 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 211 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 212 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 213 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 214 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 215 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 216 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 217 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 218 void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ 219 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 220 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 221 222 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 223 } SPI_HandleTypeDef; 224 225 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 226 /** 227 * @brief HAL SPI Callback ID enumeration definition 228 */ 229 typedef enum 230 { 231 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ 232 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ 233 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ 234 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ 235 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ 236 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ 237 HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ 238 HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ 239 HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ 240 HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ 241 HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ 242 243 } HAL_SPI_CallbackIDTypeDef; 244 245 /** 246 * @brief HAL SPI Callback pointer definition 247 */ 248 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 249 250 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 251 /** 252 * @} 253 */ 254 255 /* Exported constants --------------------------------------------------------*/ 256 257 /** @defgroup SPI_Exported_Constants SPI Exported Constants 258 * @{ 259 */ 260 261 /** @defgroup SPI_FIFO_Type SPI FIFO Type 262 * @{ 263 */ 264 #define SPI_LOWEND_FIFO_SIZE 8UL 265 #define SPI_HIGHEND_FIFO_SIZE 16UL 266 /** 267 * @} 268 */ 269 270 /** @defgroup SPI_Error_Code SPI Error Codes 271 * @{ 272 */ 273 #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ 274 #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ 275 #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ 276 #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ 277 #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ 278 #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ 279 #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ 280 #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ 281 #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ 282 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ 283 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ 284 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ 285 #define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */ 286 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 287 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ 288 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 289 /** 290 * @} 291 */ 292 293 /** @defgroup SPI_Mode SPI Mode 294 * @{ 295 */ 296 #define SPI_MODE_SLAVE (0x00000000UL) 297 #define SPI_MODE_MASTER SPI_CFG2_MASTER 298 /** 299 * @} 300 */ 301 302 /** @defgroup SPI_Direction SPI Direction Mode 303 * @{ 304 */ 305 #define SPI_DIRECTION_2LINES (0x00000000UL) 306 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 307 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 308 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM 309 /** 310 * @} 311 */ 312 313 /** @defgroup SPI_Data_Size SPI Data Size 314 * @{ 315 */ 316 #define SPI_DATASIZE_4BIT (0x00000003UL) 317 #define SPI_DATASIZE_5BIT (0x00000004UL) 318 #define SPI_DATASIZE_6BIT (0x00000005UL) 319 #define SPI_DATASIZE_7BIT (0x00000006UL) 320 #define SPI_DATASIZE_8BIT (0x00000007UL) 321 #define SPI_DATASIZE_9BIT (0x00000008UL) 322 #define SPI_DATASIZE_10BIT (0x00000009UL) 323 #define SPI_DATASIZE_11BIT (0x0000000AUL) 324 #define SPI_DATASIZE_12BIT (0x0000000BUL) 325 #define SPI_DATASIZE_13BIT (0x0000000CUL) 326 #define SPI_DATASIZE_14BIT (0x0000000DUL) 327 #define SPI_DATASIZE_15BIT (0x0000000EUL) 328 #define SPI_DATASIZE_16BIT (0x0000000FUL) 329 #define SPI_DATASIZE_17BIT (0x00000010UL) 330 #define SPI_DATASIZE_18BIT (0x00000011UL) 331 #define SPI_DATASIZE_19BIT (0x00000012UL) 332 #define SPI_DATASIZE_20BIT (0x00000013UL) 333 #define SPI_DATASIZE_21BIT (0x00000014UL) 334 #define SPI_DATASIZE_22BIT (0x00000015UL) 335 #define SPI_DATASIZE_23BIT (0x00000016UL) 336 #define SPI_DATASIZE_24BIT (0x00000017UL) 337 #define SPI_DATASIZE_25BIT (0x00000018UL) 338 #define SPI_DATASIZE_26BIT (0x00000019UL) 339 #define SPI_DATASIZE_27BIT (0x0000001AUL) 340 #define SPI_DATASIZE_28BIT (0x0000001BUL) 341 #define SPI_DATASIZE_29BIT (0x0000001CUL) 342 #define SPI_DATASIZE_30BIT (0x0000001DUL) 343 #define SPI_DATASIZE_31BIT (0x0000001EUL) 344 #define SPI_DATASIZE_32BIT (0x0000001FUL) 345 /** 346 * @} 347 */ 348 349 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 350 * @{ 351 */ 352 #define SPI_POLARITY_LOW (0x00000000UL) 353 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL 354 /** 355 * @} 356 */ 357 358 /** @defgroup SPI_Clock_Phase SPI Clock Phase 359 * @{ 360 */ 361 #define SPI_PHASE_1EDGE (0x00000000UL) 362 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA 363 /** 364 * @} 365 */ 366 367 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management 368 * @{ 369 */ 370 #define SPI_NSS_SOFT SPI_CFG2_SSM 371 #define SPI_NSS_HARD_INPUT (0x00000000UL) 372 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE 373 /** 374 * @} 375 */ 376 377 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 378 * @{ 379 */ 380 #define SPI_NSS_PULSE_DISABLE (0x00000000UL) 381 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM 382 /** 383 * @} 384 */ 385 386 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 387 * @{ 388 */ 389 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) 390 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) 391 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) 392 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) 393 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) 394 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) 395 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) 396 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) 397 /** 398 * @} 399 */ 400 401 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission 402 * @{ 403 */ 404 #define SPI_FIRSTBIT_MSB (0x00000000UL) 405 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST 406 /** 407 * @} 408 */ 409 410 /** @defgroup SPI_TI_Mode SPI TI Mode 411 * @{ 412 */ 413 #define SPI_TIMODE_DISABLE (0x00000000UL) 414 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 415 /** 416 * @} 417 */ 418 419 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 420 * @{ 421 */ 422 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL) 423 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN 424 /** 425 * @} 426 */ 427 428 /** @defgroup SPI_CRC_length SPI CRC Length 429 * @{ 430 */ 431 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) 432 #define SPI_CRC_LENGTH_4BIT (0x00030000UL) 433 #define SPI_CRC_LENGTH_5BIT (0x00040000UL) 434 #define SPI_CRC_LENGTH_6BIT (0x00050000UL) 435 #define SPI_CRC_LENGTH_7BIT (0x00060000UL) 436 #define SPI_CRC_LENGTH_8BIT (0x00070000UL) 437 #define SPI_CRC_LENGTH_9BIT (0x00080000UL) 438 #define SPI_CRC_LENGTH_10BIT (0x00090000UL) 439 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL) 440 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL) 441 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL) 442 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL) 443 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL) 444 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL) 445 #define SPI_CRC_LENGTH_17BIT (0x00100000UL) 446 #define SPI_CRC_LENGTH_18BIT (0x00110000UL) 447 #define SPI_CRC_LENGTH_19BIT (0x00120000UL) 448 #define SPI_CRC_LENGTH_20BIT (0x00130000UL) 449 #define SPI_CRC_LENGTH_21BIT (0x00140000UL) 450 #define SPI_CRC_LENGTH_22BIT (0x00150000UL) 451 #define SPI_CRC_LENGTH_23BIT (0x00160000UL) 452 #define SPI_CRC_LENGTH_24BIT (0x00170000UL) 453 #define SPI_CRC_LENGTH_25BIT (0x00180000UL) 454 #define SPI_CRC_LENGTH_26BIT (0x00190000UL) 455 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL) 456 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL) 457 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL) 458 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL) 459 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL) 460 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL) 461 /** 462 * @} 463 */ 464 465 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold 466 * @{ 467 */ 468 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) 469 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) 470 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) 471 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) 472 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) 473 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) 474 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) 475 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) 476 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) 477 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) 478 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) 479 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) 480 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) 481 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) 482 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) 483 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) 484 /** 485 * @} 486 */ 487 488 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern 489 * @{ 490 */ 491 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) 492 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) 493 /** 494 * @} 495 */ 496 497 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity 498 * @{ 499 */ 500 #define SPI_NSS_POLARITY_LOW (0x00000000UL) 501 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP 502 /** 503 * @} 504 */ 505 506 /** @defgroup SPI_Master_Keep_IO_State Keep IO State 507 * @{ 508 */ 509 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) 510 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR 511 /** 512 * @} 513 */ 514 515 /** @defgroup SPI_IO_Swap Control SPI IO Swap 516 * @{ 517 */ 518 #define SPI_IO_SWAP_DISABLE (0x00000000UL) 519 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP 520 /** 521 * @} 522 */ 523 524 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness 525 * @{ 526 */ 527 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) 528 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) 529 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) 530 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) 531 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) 532 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) 533 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) 534 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) 535 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) 536 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) 537 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) 538 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) 539 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) 540 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) 541 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) 542 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) 543 /** 544 * @} 545 */ 546 547 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness 548 * @{ 549 */ 550 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) 551 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) 552 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) 553 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) 554 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) 555 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) 556 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) 557 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) 558 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) 559 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) 560 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) 561 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) 562 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) 563 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) 564 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) 565 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) 566 /** 567 * @} 568 */ 569 570 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend 571 * @{ 572 */ 573 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) 574 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX 575 /** 576 * @} 577 */ 578 579 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior 580 * @{ 581 */ 582 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) 583 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 584 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 585 /** 586 * @} 587 */ 588 589 /** @defgroup SPI_Underrun_Detection SPI Underrun Detection 590 * @{ 591 */ 592 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) 593 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 594 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 595 /** 596 * @} 597 */ 598 599 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 600 * @{ 601 */ 602 #define SPI_IT_RXP SPI_IER_RXPIE 603 #define SPI_IT_TXP SPI_IER_TXPIE 604 #define SPI_IT_DXP SPI_IER_DXPIE 605 #define SPI_IT_EOT SPI_IER_EOTIE 606 #define SPI_IT_TXTF SPI_IER_TXTFIE 607 #define SPI_IT_UDR SPI_IER_UDRIE 608 #define SPI_IT_OVR SPI_IER_OVRIE 609 #define SPI_IT_CRCERR SPI_IER_CRCEIE 610 #define SPI_IT_FRE SPI_IER_TIFREIE 611 #define SPI_IT_MODF SPI_IER_MODFIE 612 #define SPI_IT_TSERF SPI_IER_TSERFIE 613 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) 614 /** 615 * @} 616 */ 617 618 /** @defgroup SPI_Flags_definition SPI Flags Definition 619 * @{ 620 */ 621 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ 622 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ 623 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ 624 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ 625 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ 626 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ 627 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ 628 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ 629 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ 630 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ 631 #define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */ 632 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ 633 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ 634 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ 635 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 641 * @{ 642 */ 643 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ 644 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) 645 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) 646 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) 647 /** 648 * @} 649 */ 650 651 /** 652 * @} 653 */ 654 655 /* Exported macros -----------------------------------------------------------*/ 656 /** @defgroup SPI_Exported_Macros SPI Exported Macros 657 * @{ 658 */ 659 660 /** @brief Reset SPI handle state. 661 * @param __HANDLE__: specifies the SPI Handle. 662 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 663 * @retval None 664 */ 665 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 666 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 667 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 668 (__HANDLE__)->MspInitCallback = NULL; \ 669 (__HANDLE__)->MspDeInitCallback = NULL; \ 670 } while(0) 671 #else 672 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 673 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 674 675 /** @brief Enable the specified SPI interrupts. 676 * @param __HANDLE__: specifies the SPI Handle. 677 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 678 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 679 * This parameter can be one of the following values: 680 * @arg SPI_IT_RXP : Rx-Packet available interrupt 681 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 682 * @arg SPI_IT_DXP : Duplex Packet interrupt 683 * @arg SPI_IT_EOT : End of transfer interrupt 684 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 685 * @arg SPI_IT_UDR : Underrun interrupt 686 * @arg SPI_IT_OVR : Overrun interrupt 687 * @arg SPI_IT_CRCERR : CRC error interrupt 688 * @arg SPI_IT_FRE : TI mode frame format error interrupt 689 * @arg SPI_IT_MODF : Mode fault interrupt 690 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 691 * @arg SPI_IT_ERR : Error interrupt 692 * @retval None 693 */ 694 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 695 696 /** @brief Disable the specified SPI interrupts. 697 * @param __HANDLE__: specifies the SPI Handle. 698 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 699 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 700 * This parameter can be one of the following values: 701 * @arg SPI_IT_RXP : Rx-Packet available interrupt 702 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 703 * @arg SPI_IT_DXP : Duplex Packet interrupt 704 * @arg SPI_IT_EOT : End of transfer interrupt 705 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 706 * @arg SPI_IT_UDR : Underrun interrupt 707 * @arg SPI_IT_OVR : Overrun interrupt 708 * @arg SPI_IT_CRCERR : CRC error interrupt 709 * @arg SPI_IT_FRE : TI mode frame format error interrupt 710 * @arg SPI_IT_MODF : Mode fault interrupt 711 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 712 * @arg SPI_IT_ERR : Error interrupt 713 * @retval None 714 */ 715 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 716 717 /** @brief Check whether the specified SPI interrupt source is enabled or not. 718 * @param __HANDLE__: specifies the SPI Handle. 719 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 720 * @param __INTERRUPT__: specifies the SPI interrupt source to check. 721 * This parameter can be one of the following values: 722 * @arg SPI_IT_RXP : Rx-Packet available interrupt 723 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 724 * @arg SPI_IT_DXP : Duplex Packet interrupt 725 * @arg SPI_IT_EOT : End of transfer interrupt 726 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 727 * @arg SPI_IT_UDR : Underrun interrupt 728 * @arg SPI_IT_OVR : Overrun interrupt 729 * @arg SPI_IT_CRCERR : CRC error interrupt 730 * @arg SPI_IT_FRE : TI mode frame format error interrupt 731 * @arg SPI_IT_MODF : Mode fault interrupt 732 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 733 * @arg SPI_IT_ERR : Error interrupt 734 * @retval The new state of __IT__ (TRUE or FALSE). 735 */ 736 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ 737 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 738 739 /** @brief Check whether the specified SPI flag is set or not. 740 * @param __HANDLE__: specifies the SPI Handle. 741 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 742 * @param __FLAG__: specifies the flag to check. 743 * This parameter can be one of the following values: 744 * @arg SPI_FLAG_RXP : Rx-Packet available flag 745 * @arg SPI_FLAG_TXP : Tx-Packet space available flag 746 * @arg SPI_FLAG_DXP : Duplex Packet flag 747 * @arg SPI_FLAG_EOT : End of transfer flag 748 * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag 749 * @arg SPI_FLAG_UDR : Underrun flag 750 * @arg SPI_FLAG_OVR : Overrun flag 751 * @arg SPI_FLAG_CRCERR : CRC error flag 752 * @arg SPI_FLAG_FRE : TI mode frame format error flag 753 * @arg SPI_FLAG_MODF : Mode fault flag 754 * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag 755 * @arg SPI_FLAG_SUSP : Transfer suspend complete flag 756 * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag 757 * @arg SPI_FLAG_FRLVL : Fifo reception level flag 758 * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag 759 * @retval The new state of __FLAG__ (TRUE or FALSE). 760 */ 761 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 762 763 /** @brief Clear the SPI CRCERR pending flag. 764 * @param __HANDLE__: specifies the SPI Handle. 765 * @retval None 766 */ 767 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) 768 769 /** @brief Clear the SPI MODF pending flag. 770 * @param __HANDLE__: specifies the SPI Handle. 771 * @retval None 772 */ 773 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); 774 775 /** @brief Clear the SPI OVR pending flag. 776 * @param __HANDLE__: specifies the SPI Handle. 777 * @retval None 778 */ 779 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) 780 781 /** @brief Clear the SPI FRE pending flag. 782 * @param __HANDLE__: specifies the SPI Handle. 783 * @retval None 784 */ 785 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) 786 787 /** @brief Clear the SPI UDR pending flag. 788 * @param __HANDLE__: specifies the SPI Handle. 789 * @retval None 790 */ 791 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) 792 793 /** @brief Clear the SPI EOT pending flag. 794 * @param __HANDLE__: specifies the SPI Handle. 795 * @retval None 796 */ 797 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) 798 799 /** @brief Clear the SPI UDR pending flag. 800 * @param __HANDLE__: specifies the SPI Handle. 801 * @retval None 802 */ 803 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) 804 805 /** @brief Clear the SPI SUSP pending flag. 806 * @param __HANDLE__: specifies the SPI Handle. 807 * @retval None 808 */ 809 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) 810 811 /** @brief Clear the SPI TSERF pending flag. 812 * @param __HANDLE__: specifies the SPI Handle. 813 * @retval None 814 */ 815 #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC) 816 817 /** @brief Enable the SPI peripheral. 818 * @param __HANDLE__: specifies the SPI Handle. 819 * @retval None 820 */ 821 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 822 823 /** @brief Disable the SPI peripheral. 824 * @param __HANDLE__: specifies the SPI Handle. 825 * @retval None 826 */ 827 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 828 /** 829 * @} 830 */ 831 832 833 /* Include SPI HAL Extension module */ 834 #include "stm32mp1xx_hal_spi_ex.h" 835 836 837 /* Exported functions --------------------------------------------------------*/ 838 /** @addtogroup SPI_Exported_Functions 839 * @{ 840 */ 841 842 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 843 * @{ 844 */ 845 /* Initialization/de-initialization functions ********************************/ 846 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 847 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 848 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 849 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 850 851 /* Callbacks Register/UnRegister functions ***********************************/ 852 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 853 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, 854 pSPI_CallbackTypeDef pCallback); 855 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 856 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 857 /** 858 * @} 859 */ 860 861 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions 862 * @{ 863 */ 864 /* I/O operation functions ***************************************************/ 865 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); 866 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 867 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 868 uint16_t Size, uint32_t Timeout); 869 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 870 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 871 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 872 uint16_t Size); 873 874 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 875 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 876 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, 877 uint16_t Size); 878 879 #if defined(USE_SPI_RELOAD_TRANSFER) 880 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); 881 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 882 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, 883 uint8_t *pRxData, uint16_t Size); 884 #endif /* USE_SPI_RELOAD_TRANSFER */ 885 886 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 887 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 888 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 889 890 /* Transfer Abort functions */ 891 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 892 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 893 894 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 895 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 896 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 897 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 898 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 899 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 900 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 901 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 902 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 903 void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); 904 /** 905 * @} 906 */ 907 908 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 909 * @{ 910 */ 911 912 /* Peripheral State and Error functions ***************************************/ 913 HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); 914 uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); 915 /** 916 * @} 917 */ 918 919 /** 920 * @} 921 */ 922 923 /* Private macros ------------------------------------------------------------*/ 924 /** @defgroup SPI_Private_Macros SPI Private Macros 925 * @{ 926 */ 927 928 /** @brief Set the SPI transmit-only mode in 1Line configuration. 929 * @param __HANDLE__: specifies the SPI Handle. 930 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 931 * @retval None 932 */ 933 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 934 935 /** @brief Set the SPI receive-only mode in 1Line configuration. 936 * @param __HANDLE__: specifies the SPI Handle. 937 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 938 * @retval None 939 */ 940 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) 941 942 /** @brief Set the SPI transmit-only mode in 2Lines configuration. 943 * @param __HANDLE__: specifies the SPI Handle. 944 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 945 * @retval None 946 */ 947 #define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) 948 949 /** @brief Set the SPI receive-only mode in 2Lines configuration. 950 * @param __HANDLE__: specifies the SPI Handle. 951 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 952 * @retval None 953 */ 954 #define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) 955 956 /** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. 957 * @param __HANDLE__: specifies the SPI Handle. 958 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 959 * @retval None 960 */ 961 #define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) 962 963 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ 964 ((MODE) == SPI_MODE_MASTER)) 965 966 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ 967 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ 968 ((MODE) == SPI_DIRECTION_1LINE) || \ 969 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 970 971 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) 972 973 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 974 ((MODE) == SPI_DIRECTION_1LINE) || \ 975 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 976 977 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 978 ((MODE) == SPI_DIRECTION_1LINE) || \ 979 ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) 980 981 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ 982 ((DATASIZE) == SPI_DATASIZE_31BIT) || \ 983 ((DATASIZE) == SPI_DATASIZE_30BIT) || \ 984 ((DATASIZE) == SPI_DATASIZE_29BIT) || \ 985 ((DATASIZE) == SPI_DATASIZE_28BIT) || \ 986 ((DATASIZE) == SPI_DATASIZE_27BIT) || \ 987 ((DATASIZE) == SPI_DATASIZE_26BIT) || \ 988 ((DATASIZE) == SPI_DATASIZE_25BIT) || \ 989 ((DATASIZE) == SPI_DATASIZE_24BIT) || \ 990 ((DATASIZE) == SPI_DATASIZE_23BIT) || \ 991 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 992 ((DATASIZE) == SPI_DATASIZE_21BIT) || \ 993 ((DATASIZE) == SPI_DATASIZE_20BIT) || \ 994 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 995 ((DATASIZE) == SPI_DATASIZE_19BIT) || \ 996 ((DATASIZE) == SPI_DATASIZE_18BIT) || \ 997 ((DATASIZE) == SPI_DATASIZE_17BIT) || \ 998 ((DATASIZE) == SPI_DATASIZE_16BIT) || \ 999 ((DATASIZE) == SPI_DATASIZE_15BIT) || \ 1000 ((DATASIZE) == SPI_DATASIZE_14BIT) || \ 1001 ((DATASIZE) == SPI_DATASIZE_13BIT) || \ 1002 ((DATASIZE) == SPI_DATASIZE_12BIT) || \ 1003 ((DATASIZE) == SPI_DATASIZE_11BIT) || \ 1004 ((DATASIZE) == SPI_DATASIZE_10BIT) || \ 1005 ((DATASIZE) == SPI_DATASIZE_9BIT) || \ 1006 ((DATASIZE) == SPI_DATASIZE_8BIT) || \ 1007 ((DATASIZE) == SPI_DATASIZE_7BIT) || \ 1008 ((DATASIZE) == SPI_DATASIZE_6BIT) || \ 1009 ((DATASIZE) == SPI_DATASIZE_5BIT) || \ 1010 ((DATASIZE) == SPI_DATASIZE_4BIT)) 1011 1012 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 1013 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 1014 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 1015 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 1016 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 1017 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 1018 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 1019 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ 1020 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ 1021 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ 1022 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ 1023 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ 1024 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ 1025 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ 1026 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ 1027 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) 1028 1029 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ 1030 ((CPOL) == SPI_POLARITY_HIGH)) 1031 1032 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ 1033 ((CPHA) == SPI_PHASE_2EDGE)) 1034 1035 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ 1036 ((NSS) == SPI_NSS_HARD_INPUT) || \ 1037 ((NSS) == SPI_NSS_HARD_OUTPUT)) 1038 1039 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ 1040 ((NSSP) == SPI_NSS_PULSE_DISABLE)) 1041 1042 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ 1043 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ 1044 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ 1045 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ 1046 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ 1047 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ 1048 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ 1049 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) 1050 1051 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ 1052 ((BIT) == SPI_FIRSTBIT_LSB)) 1053 1054 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ 1055 ((MODE) == SPI_TIMODE_ENABLE)) 1056 1057 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ 1058 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) 1059 1060 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ 1061 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) 1062 1063 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ 1064 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ 1065 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ 1066 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ 1067 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ 1068 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ 1069 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ 1070 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ 1071 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ 1072 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ 1073 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ 1074 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ 1075 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ 1076 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ 1077 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ 1078 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ 1079 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ 1080 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ 1081 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ 1082 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ 1083 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ 1084 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ 1085 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ 1086 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ 1087 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ 1088 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 1089 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ 1090 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ 1091 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ 1092 ((LENGTH) == SPI_CRC_LENGTH_4BIT)) 1093 1094 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) 1095 1096 1097 #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \ 1098 ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \ 1099 ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS)) 1100 1101 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ 1102 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ 1103 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) 1104 1105 #define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ 1106 ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) 1107 /** 1108 * @} 1109 */ 1110 1111 /** 1112 * @} 1113 */ 1114 1115 /** 1116 * @} 1117 */ 1118 1119 #ifdef __cplusplus 1120 } 1121 #endif 1122 1123 #endif /* STM32MP1xx_HAL_SPI_H */ 1124 1125 /** 1126 * @} 1127 */ 1128
