1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_FDCAN_H 21 #define STM32MP1xx_HAL_FDCAN_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 #if defined(FDCAN1) 31 32 /** @addtogroup STM32MP1xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FDCAN 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL State structures definition 47 */ 48 typedef enum 49 { 50 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 51 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 52 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 53 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 54 } HAL_FDCAN_StateTypeDef; 55 56 /** 57 * @brief FDCAN Init structure definition 58 */ 59 typedef struct 60 { 61 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 62 This parameter can be a value of @ref FDCAN_frame_format */ 63 64 uint32_t Mode; /*!< Specifies the FDCAN mode. 65 This parameter can be a value of @ref FDCAN_operating_mode */ 66 67 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 68 This parameter can be set to ENABLE or DISABLE */ 69 70 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 71 This parameter can be set to ENABLE or DISABLE */ 72 73 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 74 This parameter can be set to ENABLE or DISABLE */ 75 76 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 77 divided for generating the nominal bit time quanta. 78 This parameter must be a number between 1 and 512 */ 79 80 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 81 hardware is allowed to lengthen or shorten a bit to perform 82 resynchronization. 83 This parameter must be a number between 1 and 128 */ 84 85 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 86 This parameter must be a number between 2 and 256 */ 87 88 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 89 This parameter must be a number between 2 and 128 */ 90 91 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 92 divided for generating the data bit time quanta. 93 This parameter must be a number between 1 and 32 */ 94 95 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 96 hardware is allowed to lengthen or shorten a data bit to 97 perform resynchronization. 98 This parameter must be a number between 1 and 16 */ 99 100 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 101 This parameter must be a number between 1 and 32 */ 102 103 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 104 This parameter must be a number between 1 and 16 */ 105 106 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address. 107 This parameter must be a number between 0 and 2560 */ 108 109 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 110 This parameter must be a number between 0 and 128 */ 111 112 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 113 This parameter must be a number between 0 and 64 */ 114 115 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements. 116 This parameter must be a number between 0 and 64 */ 117 118 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element. 119 This parameter can be a value of @ref FDCAN_data_field_size */ 120 121 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements. 122 This parameter must be a number between 0 and 64 */ 123 124 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element. 125 This parameter can be a value of @ref FDCAN_data_field_size */ 126 127 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements. 128 This parameter must be a number between 0 and 64 */ 129 130 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element. 131 This parameter can be a value of @ref FDCAN_data_field_size */ 132 133 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements. 134 This parameter must be a number between 0 and 32 */ 135 136 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers. 137 This parameter must be a number between 0 and 32 */ 138 139 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue. 140 This parameter must be a number between 0 and 32 */ 141 142 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 143 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 144 145 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element. 146 This parameter can be a value of @ref FDCAN_data_field_size */ 147 148 } FDCAN_InitTypeDef; 149 150 /** 151 * @brief FDCAN clock calibration unit structure definition 152 */ 153 typedef struct 154 { 155 uint32_t ClockCalibration; /*!< Enable or disable the clock calibration. 156 This parameter can be a value of @ref FDCAN_clock_calibration. */ 157 158 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration 159 is bypassed. 160 This parameter can be a value of @ref FDCAN_clock_divider */ 161 162 uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The 163 actual configured number of periods is MinOscClkPeriods x 32. 164 This parameter must be a number between 0x00 and 0xFF */ 165 166 uint32_t CalFieldLength; /*!< Specifies the calibration field length. 167 This parameter can be a value of @ref FDCAN_calibration_field_length */ 168 169 uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time. 170 This parameter must be a number between 4 and 25 */ 171 172 uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter. 173 If set to zero the counter is disabled. 174 This parameter must be a number between 0x0000 and 0xFFFF */ 175 176 } FDCAN_ClkCalUnitTypeDef; 177 178 /** 179 * @brief FDCAN filter structure definition 180 */ 181 typedef struct 182 { 183 uint32_t IdType; /*!< Specifies the identifier type. 184 This parameter can be a value of @ref FDCAN_id_type */ 185 186 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 187 This parameter must be a number between: 188 - 0 and 127, if IdType is FDCAN_STANDARD_ID 189 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 190 191 uint32_t FilterType; /*!< Specifies the filter type. 192 This parameter can be a value of @ref FDCAN_filter_type. 193 The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted 194 only when IdType is FDCAN_EXTENDED_ID. 195 This parameter is ignored if FilterConfig is set to 196 FDCAN_FILTER_TO_RXBUFFER */ 197 198 uint32_t FilterConfig; /*!< Specifies the filter configuration. 199 This parameter can be a value of @ref FDCAN_filter_config */ 200 201 uint32_t FilterID1; /*!< Specifies the filter identification 1. 202 This parameter must be a number between: 203 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 204 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 205 206 uint32_t FilterID2; /*!< Specifies the filter identification 2. 207 This parameter is ignored if FilterConfig is set to 208 FDCAN_FILTER_TO_RXBUFFER. 209 This parameter must be a number between: 210 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 211 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 212 213 uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the 214 matching message will be stored. 215 This parameter must be a number between 0 and 63. 216 This parameter is ignored if FilterConfig is different 217 from FDCAN_FILTER_TO_RXBUFFER */ 218 219 uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for 220 calibration messages. 221 This parameter is ignored if FilterConfig is different 222 from FDCAN_FILTER_TO_RXBUFFER. 223 This parameter can be: 224 - 0 : ordinary message 225 - 1 : calibration message */ 226 227 } FDCAN_FilterTypeDef; 228 229 /** 230 * @brief FDCAN Tx header structure definition 231 */ 232 typedef struct 233 { 234 uint32_t Identifier; /*!< Specifies the identifier. 235 This parameter must be a number between: 236 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 237 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 238 239 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 240 transmitted. 241 This parameter can be a value of @ref FDCAN_id_type */ 242 243 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 244 This parameter can be a value of @ref FDCAN_frame_type */ 245 246 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 247 This parameter can be a value of @ref FDCAN_data_length_code */ 248 249 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 250 This parameter can be a value of @ref FDCAN_error_state_indicator */ 251 252 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 253 bit rate switching. 254 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 255 256 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 257 FD format. 258 This parameter can be a value of @ref FDCAN_format */ 259 260 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 261 This parameter can be a value of @ref FDCAN_EFC */ 262 263 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 264 element for identification of Tx message status. 265 This parameter must be a number between 0 and 0xFF */ 266 267 } FDCAN_TxHeaderTypeDef; 268 269 /** 270 * @brief FDCAN Rx header structure definition 271 */ 272 typedef struct 273 { 274 uint32_t Identifier; /*!< Specifies the identifier. 275 This parameter must be a number between: 276 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 277 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 278 279 uint32_t IdType; /*!< Specifies the identifier type of the received message. 280 This parameter can be a value of @ref FDCAN_id_type */ 281 282 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 283 This parameter can be a value of @ref FDCAN_frame_type */ 284 285 uint32_t DataLength; /*!< Specifies the received frame length. 286 This parameter can be a value of @ref FDCAN_data_length_code */ 287 288 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 289 This parameter can be a value of @ref FDCAN_error_state_indicator */ 290 291 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 292 rate switching. 293 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 294 295 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 296 format. 297 This parameter can be a value of @ref FDCAN_format */ 298 299 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 300 reception. 301 This parameter must be a number between 0 and 0xFFFF */ 302 303 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 304 This parameter must be a number between: 305 - 0 and 127, if IdType is FDCAN_STANDARD_ID 306 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */ 307 308 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 309 Acceptance of non-matching frames may be enabled via 310 HAL_FDCAN_ConfigGlobalFilter(). 311 This parameter can be 0 or 1 */ 312 313 } FDCAN_RxHeaderTypeDef; 314 315 /** 316 * @brief FDCAN Tx event FIFO structure definition 317 */ 318 typedef struct 319 { 320 uint32_t Identifier; /*!< Specifies the identifier. 321 This parameter must be a number between: 322 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 323 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 324 325 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 326 This parameter can be a value of @ref FDCAN_id_type */ 327 328 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 329 This parameter can be a value of @ref FDCAN_frame_type */ 330 331 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 332 This parameter can be a value of @ref FDCAN_data_length_code */ 333 334 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 335 This parameter can be a value of @ref FDCAN_error_state_indicator */ 336 337 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 338 rate switching. 339 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 340 341 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 342 format. 343 This parameter can be a value of @ref FDCAN_format */ 344 345 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 346 transmission. 347 This parameter must be a number between 0 and 0xFFFF */ 348 349 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 350 for identification of Tx message status. 351 This parameter must be a number between 0 and 0xFF */ 352 353 uint32_t EventType; /*!< Specifies the event type. 354 This parameter can be a value of @ref FDCAN_event_type */ 355 356 } FDCAN_TxEventFifoTypeDef; 357 358 /** 359 * @brief FDCAN High Priority Message Status structure definition 360 */ 361 typedef struct 362 { 363 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 364 This parameter can be: 365 - 0 : Standard Filter List 366 - 1 : Extended Filter List */ 367 368 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 369 This parameter can be a number between: 370 - 0 and 127, if FilterList is 0 (Standard) 371 - 0 and 63, if FilterList is 1 (Extended) */ 372 373 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 374 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 375 376 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 377 message was stored. 378 This parameter is valid only when MessageStorage is: 379 FDCAN_HP_STORAGE_RXFIFO0 380 or 381 FDCAN_HP_STORAGE_RXFIFO1 */ 382 383 } FDCAN_HpMsgStatusTypeDef; 384 385 /** 386 * @brief FDCAN Protocol Status structure definition 387 */ 388 typedef struct 389 { 390 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 391 This parameter can be a value of @ref FDCAN_protocol_error_code */ 392 393 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format 394 frame with its BRS flag set. 395 This parameter can be a value of @ref FDCAN_protocol_error_code */ 396 397 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 398 This parameter can be a value of @ref FDCAN_communication_state */ 399 400 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 401 This parameter can be: 402 - 0 : The FDCAN is in Error_Active state 403 - 1 : The FDCAN is in Error_Passive state */ 404 405 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 406 This parameter can be: 407 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96 408 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 409 410 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 411 This parameter can be: 412 - 0 : The FDCAN is not in Bus_Off state 413 - 1 : The FDCAN is in Bus_Off state */ 414 415 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 416 This parameter can be: 417 - 0 : Last received CAN FD message did not have its ESI flag set 418 - 1 : Last received CAN FD message had its ESI flag set */ 419 420 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 421 This parameter can be: 422 - 0 : Last received CAN FD message did not have its BRS flag set 423 - 1 : Last received CAN FD message had its BRS flag set */ 424 425 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. 426 This parameter can be: 427 - 0 : no CAN FD message received 428 - 1 : CAN FD message received */ 429 430 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 431 This parameter can be: 432 - 0 : No protocol exception event occurred since last read access 433 - 1 : Protocol exception event occurred */ 434 435 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 436 This parameter can be a number between 0 and 127 */ 437 438 } FDCAN_ProtocolStatusTypeDef; 439 440 /** 441 * @brief FDCAN Error Counters structure definition 442 */ 443 typedef struct 444 { 445 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 446 This parameter can be a number between 0 and 255 */ 447 448 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 449 This parameter can be a number between 0 and 127 */ 450 451 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 452 This parameter can be: 453 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 454 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */ 455 456 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 457 This parameter can be a number between 0 and 255. 458 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 459 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 460 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 461 462 } FDCAN_ErrorCountersTypeDef; 463 464 /** 465 * @brief FDCAN TT Init structure definition 466 */ 467 typedef struct 468 { 469 uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode. 470 This parameter can be a value of @ref FDCAN_operation_mode */ 471 472 uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation. 473 This parameter can be a value of @ref FDCAN_TT_operation. 474 This parameter is ignored if OperationMode is set to 475 FDCAN_TT_COMMUNICATION_LEVEL0 */ 476 477 uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master. 478 This parameter can be a value of @ref FDCAN_TT_time_master */ 479 480 uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR 481 numerator : TUR = (Numerator � SDL) / Denominator. 482 With : SDL = 2^(SyncDevLimit+5). 483 This parameter must be a number between 0 and 7 */ 484 485 uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset. 486 This parameter must be a number between 0 and 127 */ 487 488 uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization. 489 This parameter can be a value of @ref FDCAN_TT_external_clk_sync. 490 This parameter is ignored if OperationMode is set to 491 FDCAN_TT_COMMUNICATION_LEVEL1 */ 492 493 uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after 494 which the application has to serve the application watchdog. 495 The application watchdog is incremented once each 256 NTUs. 496 The application watchdog can be disabled by setting AppWdgLimit to 0. 497 This parameter must be a number between 0 and 255. 498 This parameter is ignored if OperationMode is set to 499 FDCAN_TT_COMMUNICATION_LEVEL0 */ 500 501 uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering. 502 This parameter can be a value of @ref FDCAN_TT_global_time_filtering. 503 This parameter is ignored if OperationMode is set to 504 FDCAN_TT_COMMUNICATION_LEVEL1 */ 505 506 uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration. 507 This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration. 508 This parameter is ignored if OperationMode is set to 509 FDCAN_TT_COMMUNICATION_LEVEL1 */ 510 511 uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity. 512 This parameter can be a value of @ref FDCAN_TT_event_trig_polarity. 513 This parameter is ignored if OperationMode is set to 514 FDCAN_TT_COMMUNICATION_LEVEL0 */ 515 516 uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix. 517 This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */ 518 519 uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc. 520 This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */ 521 522 uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs. 523 This parameter must be a number between 1 and 16 */ 524 525 uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix. 526 This is the sum of Tx_Triggers for exclusive, single arbitrating and 527 merged arbitrating windows. 528 This parameter must be a number between 0 and 4095 */ 529 530 uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator. 531 It is adviced to set this parameter to the largest applicable value. 532 This parameter must be a number between 0x10000 and 0x1FFFF */ 533 534 uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator. 535 This parameter must be a number between 0x0001 and 0x3FFF */ 536 537 uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements. 538 This parameter must be a number between 0 and 64 */ 539 540 uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger. 541 This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */ 542 543 uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger. 544 This parameter can be a value of @ref FDCAN_TT_event_trig_selection */ 545 546 } FDCAN_TT_ConfigTypeDef; 547 548 /** 549 * @brief FDCAN Trigger structure definition 550 */ 551 typedef struct 552 { 553 uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured. 554 This parameter must be a number between 0 and 63 */ 555 556 uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active. 557 This parameter must be a number between 0 and 0xFFFF */ 558 559 uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor. 560 This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */ 561 562 uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active. 563 This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE. 564 This parameter must be a number between 0 and RepeatFactor */ 565 566 uint32_t TmEventInt; /*!< Enable or disable the internal time mark event. 567 If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element 568 becomes active. 569 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */ 570 571 uint32_t TmEventExt; /*!< Enable or disable the external time mark event. 572 If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when 573 trigger memory element becomes active. 574 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */ 575 576 uint32_t TriggerType; /*!< Specifies the trigger type. 577 This parameter can be a value of @ref FDCAN_TT_Trigger_Type */ 578 579 uint32_t FilterType; /*!< Specifies the filter identifier type. 580 This parameter can be a value of @ref FDCAN_id_type */ 581 582 uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid. 583 This parameter can be a value of @ref FDCAN_Tx_location. 584 This parameter is taken in consideration only if the trigger is configured for 585 transmission. */ 586 587 uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid. 588 This parameter is taken in consideration only if the trigger is configured for 589 reception. 590 This parameter must be a number between: 591 - 0 and 127, if FilterType is FDCAN_STANDARD_ID 592 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */ 593 594 } FDCAN_TriggerTypeDef; 595 596 /** 597 * @brief FDCAN TT Operation Status structure definition 598 */ 599 typedef struct 600 { 601 uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level. 602 This parameter can be a value of @ref FDCAN_TT_error_level */ 603 604 uint32_t MasterState; /*!< Specifies the type of the TT master state. 605 This parameter can be a value of @ref FDCAN_TT_master_state */ 606 607 uint32_t SyncState; /*!< Specifies the type of the TT synchronization state. 608 This parameter can be a value of @ref FDCAN_TT_sync_state */ 609 610 uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase. 611 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0. 612 This parameter can be: 613 - 0 : Global time not valid 614 - 1 : Global time in phase with Time Master */ 615 616 uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed. 617 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1. 618 This parameter can be: 619 - 0 : Local clock speed not synchronized to Time Master clock speed 620 - 1 : Synchronization Deviation = SDL */ 621 622 uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value. 623 This parameter can be a number between 0 and 0xFF */ 624 625 uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State. 626 This parameter can be: 627 - 0 : No global time preset pending 628 - 1 : Node waits for the global time preset to take effect */ 629 630 uint32_t GapFinished; /*!< Specifies whether a Gap is finished. 631 This parameter can be: 632 - 0 : Reset at the end of each reference message 633 - 1 : Gap finished */ 634 635 uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master. 636 This parameter can be a number between 0 and 0x7 */ 637 638 uint32_t GapStarted; /*!< Specifies whether a Gap is started. 639 This parameter can be: 640 - 0 : No Gap in schedule 641 - 1 : Gap time after Basic Cycle has started */ 642 643 uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced. 644 This parameter can be: 645 - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0 646 - 1 : Reference message with Next_is_Gap = 1 received */ 647 648 uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State. 649 This parameter can be: 650 - 0 : Application Watchdog served in time 651 - 1 : Failed to serve Application Watchdog in time */ 652 653 uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State. 654 This parameter can be: 655 - 0 : No external clock synchronization pending 656 - 1 : Node waits for external clock synchronization to take effect */ 657 658 uint32_t PhaseLock; /*!< Specifies the Phase Lock State. 659 This parameter can be: 660 - 0 : Phase outside range 661 - 1 : Phase inside range */ 662 663 } FDCAN_TTOperationStatusTypeDef; 664 665 /** 666 * @brief FDCAN Message RAM blocks 667 */ 668 typedef struct 669 { 670 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 671 This parameter must be a 32-bit word address */ 672 673 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 674 This parameter must be a 32-bit word address */ 675 676 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 677 This parameter must be a 32-bit word address */ 678 679 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 680 This parameter must be a 32-bit word address */ 681 682 uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address. 683 This parameter must be a 32-bit word address */ 684 685 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 686 This parameter must be a 32-bit word address */ 687 688 uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address. 689 This parameter must be a 32-bit word address */ 690 691 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 692 This parameter must be a 32-bit word address */ 693 694 uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address. 695 This parameter must be a 32-bit word address */ 696 697 uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM. 698 This parameter must be a 32-bit word address */ 699 700 } FDCAN_MsgRamAddressTypeDef; 701 702 /** 703 * @brief FDCAN handle structure definition 704 */ 705 typedef struct 706 { 707 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 708 709 TTCAN_TypeDef *ttcan; /*!< TT register base address */ 710 711 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 712 713 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 714 715 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 716 of latest Tx FIFO/Queue request */ 717 718 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 719 720 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 721 722 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 723 724 725 } FDCAN_HandleTypeDef; 726 727 728 /** 729 * @} 730 */ 731 732 /* Exported constants --------------------------------------------------------*/ 733 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 734 * @{ 735 */ 736 737 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 738 * @{ 739 */ 740 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 741 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 742 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 743 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 744 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 745 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 746 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 747 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 748 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 749 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 750 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 751 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 752 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 753 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 754 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 755 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 756 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */ 757 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */ 758 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */ 759 #define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */ 760 #define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */ 761 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */ 762 #define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */ 763 #define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */ 764 #define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */ 765 766 /** 767 * @} 768 */ 769 770 /** @defgroup FDCAN_frame_format FDCAN Frame Format 771 * @{ 772 */ 773 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 774 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 775 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 776 /** 777 * @} 778 */ 779 780 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 781 * @{ 782 */ 783 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 784 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 785 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 786 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 787 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 788 /** 789 * @} 790 */ 791 792 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration 793 * @{ 794 */ 795 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */ 796 #define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */ 797 /** 798 * @} 799 */ 800 801 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 802 * @{ 803 */ 804 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 805 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */ 806 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */ 807 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */ 808 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */ 809 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */ 810 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */ 811 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */ 812 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */ 813 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */ 814 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */ 815 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */ 816 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */ 817 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */ 818 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */ 819 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */ 820 /** 821 * @} 822 */ 823 824 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length 825 * @{ 826 */ 827 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */ 828 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */ 829 /** 830 * @} 831 */ 832 833 /** @defgroup FDCAN_calibration_state FDCAN Calibration State 834 * @{ 835 */ 836 #define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */ 837 #define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */ 838 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */ 839 /** 840 * @} 841 */ 842 843 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter 844 * @{ 845 */ 846 #define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */ 847 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */ 848 #define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */ 849 /** 850 * @} 851 */ 852 853 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size 854 * @{ 855 */ 856 #define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */ 857 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */ 858 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */ 859 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */ 860 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */ 861 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */ 862 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ 863 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */ 864 /** 865 * @} 866 */ 867 868 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 869 * @{ 870 */ 871 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 872 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 873 /** 874 * @} 875 */ 876 877 /** @defgroup FDCAN_id_type FDCAN ID Type 878 * @{ 879 */ 880 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 881 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 882 /** 883 * @} 884 */ 885 886 /** @defgroup FDCAN_frame_type FDCAN Frame Type 887 * @{ 888 */ 889 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 890 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 891 /** 892 * @} 893 */ 894 895 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 896 * @{ 897 */ 898 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 899 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 900 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 901 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 902 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 903 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 904 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 905 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 906 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 907 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 908 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 909 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 910 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 911 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 912 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 913 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 914 /** 915 * @} 916 */ 917 918 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 919 * @{ 920 */ 921 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 922 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 923 /** 924 * @} 925 */ 926 927 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 928 * @{ 929 */ 930 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 931 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 932 /** 933 * @} 934 */ 935 936 /** @defgroup FDCAN_format FDCAN format 937 * @{ 938 */ 939 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 940 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 941 /** 942 * @} 943 */ 944 945 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 946 * @{ 947 */ 948 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 949 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 950 /** 951 * @} 952 */ 953 954 /** @defgroup FDCAN_filter_type FDCAN Filter Type 955 * @{ 956 */ 957 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 958 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 959 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 960 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 961 /** 962 * @} 963 */ 964 965 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 966 * @{ 967 */ 968 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 969 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 970 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 971 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 972 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 973 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 974 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 975 #define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */ 976 /** 977 * @} 978 */ 979 980 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 981 * @{ 982 */ 983 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 984 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 985 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 986 #define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */ 987 #define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */ 988 #define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */ 989 #define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */ 990 #define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */ 991 #define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */ 992 #define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */ 993 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */ 994 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */ 995 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */ 996 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */ 997 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */ 998 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */ 999 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */ 1000 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */ 1001 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */ 1002 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */ 1003 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */ 1004 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */ 1005 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */ 1006 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */ 1007 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */ 1008 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */ 1009 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */ 1010 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */ 1011 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */ 1012 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */ 1013 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */ 1014 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */ 1015 /** 1016 * @} 1017 */ 1018 1019 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 1020 * @{ 1021 */ 1022 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 1023 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 1024 #define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */ 1025 #define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */ 1026 #define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */ 1027 #define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */ 1028 #define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */ 1029 #define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */ 1030 #define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */ 1031 #define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */ 1032 #define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */ 1033 #define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */ 1034 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */ 1035 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */ 1036 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */ 1037 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */ 1038 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */ 1039 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */ 1040 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */ 1041 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */ 1042 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */ 1043 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */ 1044 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */ 1045 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */ 1046 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */ 1047 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */ 1048 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */ 1049 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */ 1050 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */ 1051 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */ 1052 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */ 1053 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */ 1054 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */ 1055 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */ 1056 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */ 1057 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */ 1058 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */ 1059 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */ 1060 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */ 1061 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */ 1062 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */ 1063 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */ 1064 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */ 1065 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */ 1066 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */ 1067 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */ 1068 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */ 1069 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */ 1070 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */ 1071 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */ 1072 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */ 1073 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */ 1074 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */ 1075 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */ 1076 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */ 1077 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */ 1078 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */ 1079 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */ 1080 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */ 1081 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */ 1082 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */ 1083 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */ 1084 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */ 1085 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */ 1086 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */ 1087 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */ 1088 /** 1089 * @} 1090 */ 1091 1092 /** @defgroup FDCAN_event_type FDCAN Event Type 1093 * @{ 1094 */ 1095 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 1096 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 1097 /** 1098 * @} 1099 */ 1100 1101 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 1102 * @{ 1103 */ 1104 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 1105 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 1106 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 1107 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 1113 * @{ 1114 */ 1115 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 1116 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 1117 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 1118 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 1119 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 1120 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 1121 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 1122 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 1123 /** 1124 * @} 1125 */ 1126 1127 /** @defgroup FDCAN_communication_state FDCAN communication state 1128 * @{ 1129 */ 1130 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 1131 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 1132 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 1133 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 1134 /** 1135 * @} 1136 */ 1137 1138 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark 1139 * @{ 1140 */ 1141 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */ 1142 #define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */ 1143 #define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */ 1144 /** 1145 * @} 1146 */ 1147 1148 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 1149 * @{ 1150 */ 1151 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 1152 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */ 1153 /** 1154 * @} 1155 */ 1156 1157 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 1158 * @{ 1159 */ 1160 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 1161 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 1162 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 1163 /** 1164 * @} 1165 */ 1166 1167 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 1168 * @{ 1169 */ 1170 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 1171 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 1172 /** 1173 * @} 1174 */ 1175 1176 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 1177 * @{ 1178 */ 1179 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 1180 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 1181 /** 1182 * @} 1183 */ 1184 1185 /** @defgroup FDCAN_Timestamp FDCAN timestamp 1186 * @{ 1187 */ 1188 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 1189 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 1190 /** 1191 * @} 1192 */ 1193 1194 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 1195 * @{ 1196 */ 1197 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 1198 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */ 1199 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */ 1200 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */ 1201 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */ 1202 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */ 1203 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */ 1204 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */ 1205 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */ 1206 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */ 1207 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */ 1208 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */ 1209 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */ 1210 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */ 1211 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */ 1212 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */ 1213 /** 1214 * @} 1215 */ 1216 1217 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 1218 * @{ 1219 */ 1220 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 1221 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 1222 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 1223 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 1224 /** 1225 * @} 1226 */ 1227 1228 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload 1229 * @{ 1230 */ 1231 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */ 1232 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */ 1233 /** 1234 * @} 1235 */ 1236 1237 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor 1238 * @{ 1239 */ 1240 #define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */ 1241 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */ 1242 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */ 1243 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */ 1244 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */ 1245 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */ 1246 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */ 1247 /** 1248 * @} 1249 */ 1250 1251 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type 1252 * @{ 1253 */ 1254 #define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */ 1255 #define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */ 1256 #define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */ 1257 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */ 1258 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */ 1259 #define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */ 1260 #define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */ 1261 #define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */ 1262 #define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */ 1263 #define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */ 1264 #define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */ 1265 /** 1266 * @} 1267 */ 1268 1269 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal 1270 * @{ 1271 */ 1272 #define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1273 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */ 1274 /** 1275 * @} 1276 */ 1277 1278 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external 1279 * @{ 1280 */ 1281 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */ 1282 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */ 1283 /** 1284 * @} 1285 */ 1286 1287 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode 1288 * @{ 1289 */ 1290 #define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */ 1291 #define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */ 1292 #define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */ 1293 /** 1294 * @} 1295 */ 1296 1297 /** @defgroup FDCAN_TT_operation FDCAN TT Operation 1298 * @{ 1299 */ 1300 #define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */ 1301 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */ 1302 /** 1303 * @} 1304 */ 1305 1306 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master 1307 * @{ 1308 */ 1309 #define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */ 1310 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */ 1311 /** 1312 * @} 1313 */ 1314 1315 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization 1316 * @{ 1317 */ 1318 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */ 1319 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */ 1320 /** 1321 * @} 1322 */ 1323 1324 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering 1325 * @{ 1326 */ 1327 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */ 1328 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */ 1329 /** 1330 * @} 1331 */ 1332 1333 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration 1334 * @{ 1335 */ 1336 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */ 1337 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */ 1338 /** 1339 * @} 1340 */ 1341 1342 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity 1343 * @{ 1344 */ 1345 #define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */ 1346 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */ 1347 /** 1348 * @} 1349 */ 1350 1351 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number 1352 * @{ 1353 */ 1354 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */ 1355 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */ 1356 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */ 1357 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */ 1358 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */ 1359 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */ 1360 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */ 1361 /** 1362 * @} 1363 */ 1364 1365 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync 1366 * @{ 1367 */ 1368 #define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */ 1369 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */ 1370 #define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */ 1371 /** 1372 * @} 1373 */ 1374 1375 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection 1376 * @{ 1377 */ 1378 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */ 1379 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */ 1380 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */ 1381 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */ 1382 /** 1383 * @} 1384 */ 1385 1386 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection 1387 * @{ 1388 */ 1389 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */ 1390 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */ 1391 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */ 1392 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */ 1393 /** 1394 * @} 1395 */ 1396 1397 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source 1398 * @{ 1399 */ 1400 #define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */ 1401 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */ 1402 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */ 1403 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */ 1404 /** 1405 * @} 1406 */ 1407 1408 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity 1409 * @{ 1410 */ 1411 #define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */ 1412 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */ 1413 /** 1414 * @} 1415 */ 1416 1417 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source 1418 * @{ 1419 */ 1420 #define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */ 1421 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */ 1422 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */ 1423 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */ 1424 /** 1425 * @} 1426 */ 1427 1428 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level 1429 * @{ 1430 */ 1431 #define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */ 1432 #define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */ 1433 #define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */ 1434 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */ 1435 /** 1436 * @} 1437 */ 1438 1439 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State 1440 * @{ 1441 */ 1442 #define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */ 1443 #define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */ 1444 #define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */ 1445 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */ 1446 /** 1447 * @} 1448 */ 1449 1450 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State 1451 * @{ 1452 */ 1453 #define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */ 1454 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */ 1455 #define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */ 1456 #define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */ 1457 /** 1458 * @} 1459 */ 1460 1461 /** @defgroup Interrupt_Masks Interrupt masks 1462 * @{ 1463 */ 1464 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */ 1465 #define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */ 1466 /** 1467 * @} 1468 */ 1469 1470 /** @defgroup FDCAN_flags FDCAN Flags 1471 * @{ 1472 */ 1473 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 1474 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 1475 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 1476 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 1477 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */ 1478 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 1479 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 1480 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */ 1481 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 1482 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 1483 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 1484 #define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */ 1485 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 1486 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 1487 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 1488 #define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */ 1489 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 1490 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 1491 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 1492 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 1493 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 1494 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 1495 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 1496 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 1497 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 1498 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 1499 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 1500 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 1501 #define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */ 1502 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */ 1503 /** 1504 * @} 1505 */ 1506 1507 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 1508 * @{ 1509 */ 1510 1511 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 1512 * @{ 1513 */ 1514 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 1515 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 1516 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 1517 /** 1518 * @} 1519 */ 1520 1521 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 1522 * @{ 1523 */ 1524 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 1525 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */ 1526 /** 1527 * @} 1528 */ 1529 1530 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 1531 * @{ 1532 */ 1533 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 1534 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 1535 /** 1536 * @} 1537 */ 1538 1539 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts 1540 * @{ 1541 */ 1542 #define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */ 1543 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */ 1544 /** 1545 * @} 1546 */ 1547 1548 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 1549 * @{ 1550 */ 1551 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 1552 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 1553 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */ 1554 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 1555 /** 1556 * @} 1557 */ 1558 1559 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 1560 * @{ 1561 */ 1562 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 1563 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 1564 #define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */ 1565 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 1566 /** 1567 * @} 1568 */ 1569 1570 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 1571 * @{ 1572 */ 1573 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 1574 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 1575 #define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */ 1576 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 1577 /** 1578 * @} 1579 */ 1580 1581 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 1582 * @{ 1583 */ 1584 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 1585 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 1586 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 1587 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 1588 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 1589 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 1590 /** 1591 * @} 1592 */ 1593 1594 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 1595 * @{ 1596 */ 1597 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 1598 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 1599 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 1600 /** 1601 * @} 1602 */ 1603 1604 /** 1605 * @} 1606 */ 1607 1608 /** @defgroup FDCAN_TTflags FDCAN TT Flags 1609 * @{ 1610 */ 1611 #define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */ 1612 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */ 1613 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */ 1614 #define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */ 1615 #define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */ 1616 #define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */ 1617 #define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */ 1618 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */ 1619 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */ 1620 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */ 1621 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */ 1622 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */ 1623 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */ 1624 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */ 1625 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */ 1626 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */ 1627 #define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */ 1628 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */ 1629 #define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */ 1630 /** 1631 * @} 1632 */ 1633 1634 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts 1635 * @{ 1636 */ 1637 1638 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts 1639 * @{ 1640 */ 1641 #define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */ 1642 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */ 1643 #define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */ 1644 #define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */ 1645 /** 1646 * @} 1647 */ 1648 1649 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts 1650 * @{ 1651 */ 1652 #define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */ 1653 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */ 1654 /** 1655 * @} 1656 */ 1657 1658 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt 1659 * @{ 1660 */ 1661 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */ 1662 /** 1663 * @} 1664 */ 1665 1666 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts 1667 * @{ 1668 */ 1669 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */ 1670 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */ 1671 /** 1672 * @} 1673 */ 1674 1675 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts 1676 * @{ 1677 */ 1678 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */ 1679 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */ 1680 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */ 1681 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */ 1682 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */ 1683 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */ 1684 /** 1685 * @} 1686 */ 1687 1688 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts 1689 * @{ 1690 */ 1691 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */ 1692 #define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */ 1693 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */ 1694 #define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */ 1695 /** 1696 * @} 1697 */ 1698 1699 /** 1700 * @} 1701 */ 1702 1703 /** 1704 * @} 1705 */ 1706 1707 /* Exported macro ------------------------------------------------------------*/ 1708 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1709 * @{ 1710 */ 1711 1712 /** @brief Reset FDCAN handle state. 1713 * @param __HANDLE__ FDCAN handle. 1714 * @retval None 1715 */ 1716 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1717 1718 /** 1719 * @brief Enable the specified FDCAN interrupts. 1720 * @param __HANDLE__ FDCAN handle. 1721 * @param __INTERRUPT__ FDCAN interrupt. 1722 * This parameter can be any combination of @arg FDCAN_Interrupts 1723 * @retval None 1724 */ 1725 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1726 do{ \ 1727 (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1728 FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1729 }while(0) 1730 1731 1732 /** 1733 * @brief Disable the specified FDCAN interrupts. 1734 * @param __HANDLE__ FDCAN handle. 1735 * @param __INTERRUPT__ FDCAN interrupt. 1736 * This parameter can be any combination of @arg FDCAN_Interrupts 1737 * @retval None 1738 */ 1739 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1740 do{ \ 1741 ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \ 1742 FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1743 }while(0) 1744 1745 /** 1746 * @brief Check whether the specified FDCAN interrupt is set or not. 1747 * @param __HANDLE__ FDCAN handle. 1748 * @param __INTERRUPT__ FDCAN interrupt. 1749 * This parameter can be one of @arg FDCAN_Interrupts 1750 * @retval ITStatus 1751 */ 1752 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__))) 1753 1754 /** 1755 * @brief Clear the specified FDCAN interrupts. 1756 * @param __HANDLE__ FDCAN handle. 1757 * @param __INTERRUPT__ specifies the interrupts to clear. 1758 * This parameter can be any combination of @arg FDCAN_Interrupts 1759 * @retval None 1760 */ 1761 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1762 do{ \ 1763 ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \ 1764 FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \ 1765 }while(0) 1766 1767 /** 1768 * @brief Check whether the specified FDCAN flag is set or not. 1769 * @param __HANDLE__ FDCAN handle. 1770 * @param __FLAG__ FDCAN flag. 1771 * This parameter can be one of @arg FDCAN_flags 1772 * @retval FlagStatus 1773 */ 1774 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__))) 1775 1776 /** 1777 * @brief Clear the specified FDCAN flags. 1778 * @param __HANDLE__ FDCAN handle. 1779 * @param __FLAG__ specifies the flags to clear. 1780 * This parameter can be any combination of @arg FDCAN_flags 1781 * @retval None 1782 */ 1783 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1784 do{ \ 1785 ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \ 1786 FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \ 1787 }while(0) 1788 1789 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1790 * @param __HANDLE__ FDCAN handle. 1791 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1792 * This parameter can be a value of @arg FDCAN_Interrupts 1793 * @retval ITStatus 1794 */ 1795 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__))) 1796 1797 /** 1798 * @brief Enable the specified FDCAN TT interrupts. 1799 * @param __HANDLE__ FDCAN handle. 1800 * @param __INTERRUPT__ FDCAN TT interrupt. 1801 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1802 * @retval None 1803 */ 1804 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__)) 1805 1806 /** 1807 * @brief Disable the specified FDCAN TT interrupts. 1808 * @param __HANDLE__ FDCAN handle. 1809 * @param __INTERRUPT__ FDCAN TT interrupt. 1810 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1811 * @retval None 1812 */ 1813 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__)) 1814 1815 /** 1816 * @brief Check whether the specified FDCAN TT interrupt is set or not. 1817 * @param __HANDLE__ FDCAN handle. 1818 * @param __INTERRUPT__ FDCAN TT interrupt. 1819 * This parameter can be one of @arg FDCAN_TTInterrupts 1820 * @retval ITStatus 1821 */ 1822 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__)) 1823 1824 /** 1825 * @brief Clear the specified FDCAN TT interrupts. 1826 * @param __HANDLE__ FDCAN handle. 1827 * @param __INTERRUPT__ specifies the TT interrupts to clear. 1828 * This parameter can be any combination of @arg FDCAN_TTInterrupts 1829 * @retval None 1830 */ 1831 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__)) 1832 1833 /** 1834 * @brief Check whether the specified FDCAN TT flag is set or not. 1835 * @param __HANDLE__ FDCAN handle. 1836 * @param __FLAG__ FDCAN TT flag. 1837 * This parameter can be one of @arg FDCAN_TTflags 1838 * @retval FlagStatus 1839 */ 1840 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__)) 1841 1842 /** 1843 * @brief Clear the specified FDCAN TT flags. 1844 * @param __HANDLE__ FDCAN handle. 1845 * @param __FLAG__ specifies the TT flags to clear. 1846 * This parameter can be any combination of @arg FDCAN_TTflags 1847 * @retval None 1848 */ 1849 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__)) 1850 1851 /** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled. 1852 * @param __HANDLE__ FDCAN handle. 1853 * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check. 1854 * This parameter can be a value of @arg FDCAN_TTInterrupts 1855 * @retval ITStatus 1856 */ 1857 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__)) 1858 1859 /** 1860 * @} 1861 */ 1862 1863 /* Exported functions --------------------------------------------------------*/ 1864 /** @addtogroup FDCAN_Exported_Functions 1865 * @{ 1866 */ 1867 1868 /** @addtogroup FDCAN_Exported_Functions_Group1 1869 * @{ 1870 */ 1871 /* Initialization and de-initialization functions *****************************/ 1872 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1873 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1874 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1875 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1876 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1877 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1878 1879 /** 1880 * @} 1881 */ 1882 1883 /** @addtogroup FDCAN_Exported_Functions_Group2 1884 * @{ 1885 */ 1886 /* Configuration functions ****************************************************/ 1887 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig); 1888 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1889 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan); 1890 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter); 1891 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 1892 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt); 1893 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1894 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1895 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark); 1896 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1897 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1898 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 1899 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1900 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1901 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1902 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod); 1903 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1904 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1905 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1906 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1907 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter); 1908 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1909 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1910 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 1911 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 1912 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1913 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1914 /** 1915 * @} 1916 */ 1917 1918 /** @addtogroup FDCAN_Exported_Functions_Group3 1919 * @{ 1920 */ 1921 /* Control functions **********************************************************/ 1922 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 1923 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 1924 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData); 1925 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex); 1926 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1927 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 1928 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1929 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 1930 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 1931 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 1932 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 1933 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 1934 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex); 1935 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 1936 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 1937 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 1938 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1939 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1940 /** 1941 * @} 1942 */ 1943 1944 /** @addtogroup FDCAN_Exported_Functions_Group4 1945 * @{ 1946 */ 1947 /* TT Configuration and control functions**************************************/ 1948 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams); 1949 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload); 1950 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig); 1951 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset); 1952 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator); 1953 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity); 1954 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle); 1955 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1956 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1957 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1958 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan); 1959 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 1960 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan); 1961 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 1962 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan); 1963 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan); 1964 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan); 1965 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase); 1966 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 1967 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan); 1968 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus); 1969 /** 1970 * @} 1971 */ 1972 1973 /** @addtogroup FDCAN_Exported_Functions_Group5 1974 * @{ 1975 */ 1976 /* Interrupts management ******************************************************/ 1977 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 1978 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine); 1979 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes); 1980 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 1981 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs); 1982 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs); 1983 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 1984 /** 1985 * @} 1986 */ 1987 1988 /** @addtogroup FDCAN_Exported_Functions_Group6 1989 * @{ 1990 */ 1991 /* Callback functions *********************************************************/ 1992 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); 1993 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 1994 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 1995 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 1996 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 1997 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1998 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1999 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2000 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 2001 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 2002 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 2003 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 2004 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 2005 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); 2006 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); 2007 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); 2008 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); 2009 /** 2010 * @} 2011 */ 2012 2013 /** @addtogroup FDCAN_Exported_Functions_Group7 2014 * @{ 2015 */ 2016 /* Peripheral State functions *************************************************/ 2017 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 2018 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 2019 /** 2020 * @} 2021 */ 2022 2023 /** 2024 * @} 2025 */ 2026 2027 /* Private types -------------------------------------------------------------*/ 2028 /** @defgroup FDCAN_Private_Types FDCAN Private Types 2029 * @{ 2030 */ 2031 2032 /** 2033 * @} 2034 */ 2035 2036 /* Private variables ---------------------------------------------------------*/ 2037 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 2038 * @{ 2039 */ 2040 2041 /** 2042 * @} 2043 */ 2044 2045 /* Private constants ---------------------------------------------------------*/ 2046 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 2047 * @{ 2048 */ 2049 2050 /** 2051 * @} 2052 */ 2053 2054 /* Private macros ------------------------------------------------------------*/ 2055 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 2056 * @{ 2057 */ 2058 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 2059 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 2060 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 2061 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 2062 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 2063 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 2064 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 2065 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 2066 2067 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \ 2068 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE )) 2069 2070 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 2071 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 2072 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 2073 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 2074 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 2075 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 2076 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 2077 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 2078 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 2079 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 2080 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 2081 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 2082 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 2083 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 2084 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 2085 ((CKDIV) == FDCAN_CLOCK_DIV30)) 2086 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 2087 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 2088 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 2089 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 2090 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 2091 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 2092 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 2093 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 2094 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX)) 2095 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN)) 2096 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \ 2097 ((SIZE) == FDCAN_DATA_BYTES_12) || \ 2098 ((SIZE) == FDCAN_DATA_BYTES_16) || \ 2099 ((SIZE) == FDCAN_DATA_BYTES_20) || \ 2100 ((SIZE) == FDCAN_DATA_BYTES_24) || \ 2101 ((SIZE) == FDCAN_DATA_BYTES_32) || \ 2102 ((SIZE) == FDCAN_DATA_BYTES_48) || \ 2103 ((SIZE) == FDCAN_DATA_BYTES_64)) 2104 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 2105 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 2106 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 2107 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 2108 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 2109 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 2110 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 2111 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 2112 ((CONFIG) == FDCAN_FILTER_HP ) || \ 2113 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 2114 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \ 2115 ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER )) 2116 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 2117 ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \ 2118 ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \ 2119 ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \ 2120 ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \ 2121 ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \ 2122 ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \ 2123 ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \ 2124 ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \ 2125 ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \ 2126 ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \ 2127 ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \ 2128 ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \ 2129 ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \ 2130 ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \ 2131 ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31)) 2132 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 2133 ((FIFO) == FDCAN_RX_FIFO1)) 2134 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 2135 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 2136 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 2137 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2138 ((TYPE) == FDCAN_FILTER_MASK )) 2139 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 2140 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 2141 ((TYPE) == FDCAN_FILTER_MASK ) || \ 2142 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 2143 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 2144 ((TYPE) == FDCAN_REMOTE_FRAME)) 2145 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 2146 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 2147 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 2148 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 2149 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 2150 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 2151 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 2152 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 2153 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 2154 ((DLC) == FDCAN_DLC_BYTES_12) || \ 2155 ((DLC) == FDCAN_DLC_BYTES_16) || \ 2156 ((DLC) == FDCAN_DLC_BYTES_20) || \ 2157 ((DLC) == FDCAN_DLC_BYTES_24) || \ 2158 ((DLC) == FDCAN_DLC_BYTES_32) || \ 2159 ((DLC) == FDCAN_DLC_BYTES_48) || \ 2160 ((DLC) == FDCAN_DLC_BYTES_64)) 2161 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 2162 ((ESI) == FDCAN_ESI_PASSIVE)) 2163 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 2164 ((BRS) == FDCAN_BRS_ON )) 2165 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 2166 ((FDF) == FDCAN_FD_CAN )) 2167 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 2168 ((EFC) == FDCAN_STORE_TX_EVENTS)) 2169 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U) 2170 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U) 2171 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \ 2172 ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \ 2173 ((FIFO) == FDCAN_CFG_RX_FIFO1 )) 2174 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 2175 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 2176 ((DESTINATION) == FDCAN_REJECT )) 2177 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 2178 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 2179 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 2180 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 2181 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 2182 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 2183 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 2184 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 2185 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 2186 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 2187 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 2188 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 2189 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 2190 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 2191 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 2192 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 2193 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 2194 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 2195 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 2196 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 2197 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 2198 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 2199 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 2200 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 2201 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 2202 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 2203 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \ 2204 ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64)) 2205 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \ 2206 ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \ 2207 ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER )) 2208 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \ 2209 ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD)) 2210 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \ 2211 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \ 2212 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \ 2213 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \ 2214 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \ 2215 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \ 2216 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE)) 2217 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \ 2218 ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \ 2219 ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \ 2220 ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \ 2221 ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \ 2222 ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \ 2223 ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \ 2224 ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \ 2225 ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \ 2226 ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \ 2227 ((TYPE) == FDCAN_TT_END_OF_LIST )) 2228 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \ 2229 ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT)) 2230 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \ 2231 ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT)) 2232 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \ 2233 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \ 2234 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 )) 2235 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \ 2236 ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION)) 2237 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \ 2238 ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER)) 2239 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \ 2240 ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE )) 2241 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \ 2242 ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE )) 2243 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \ 2244 ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE )) 2245 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \ 2246 ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING)) 2247 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \ 2248 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \ 2249 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \ 2250 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \ 2251 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \ 2252 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \ 2253 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64)) 2254 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \ 2255 ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \ 2256 ((SYNC) == FDCAN_TT_SYNC_MATRIX_START )) 2257 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U)) 2258 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU)) 2259 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU)) 2260 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC))) 2261 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC))) 2262 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \ 2263 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \ 2264 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \ 2265 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3)) 2266 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \ 2267 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \ 2268 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \ 2269 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3)) 2270 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U)) 2271 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \ 2272 ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \ 2273 ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \ 2274 ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME)) 2275 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \ 2276 ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING)) 2277 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \ 2278 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \ 2279 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \ 2280 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME)) 2281 /** 2282 * @} 2283 */ 2284 2285 /* Private functions prototypes ----------------------------------------------*/ 2286 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes 2287 * @{ 2288 */ 2289 2290 /** 2291 * @} 2292 */ 2293 2294 /* Private functions ---------------------------------------------------------*/ 2295 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions 2296 * @{ 2297 */ 2298 2299 /** 2300 * @} 2301 */ 2302 /** 2303 * @} 2304 */ 2305 2306 /** 2307 * @} 2308 */ 2309 #endif /* FDCAN1 */ 2310 2311 #ifdef __cplusplus 2312 } 2313 #endif 2314 2315 #endif /* STM32MP1xx_HAL_FDCAN_H */ 2316
