1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_ADC_H 21 #define STM32MP1xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32mp1xx_ll_adc.h" 32 33 /** @addtogroup STM32MP1xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value between 1 and 1024 */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this parameter 64 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 65 (the oversampling buffer is zeroed during injection sequence). 66 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 67 68 } ADC_OversamplingTypeDef; 69 70 /** 71 * @brief Structure definition of ADC instance and ADC group regular. 72 * @note Parameters of this structure are shared within 2 scopes: 73 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 74 * ScanConvMode, EOCSelection, LowPowerAutoWait. 75 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 76 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 77 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 78 * ADC state can be either: 79 * - For all parameters: ADC disabled 80 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 81 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 82 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 83 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 84 * (which fulfills the ADC state condition) on the fly). 85 */ 86 typedef struct 87 { 88 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 89 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 90 Note: The ADC clock configuration is common to all ADC instances. 91 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 92 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 93 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 94 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 95 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 96 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 97 Note: This parameter can be modified only if all ADC instances are disabled. */ 98 99 uint32_t Resolution; /*!< Configure the ADC resolution. 100 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 101 102 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 103 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 104 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 105 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 106 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 107 Scan direction is upward: from rank 1 to rank 'n'. 108 This parameter can be a value of @ref ADC_Scan_mode */ 109 110 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 111 This parameter can be a value of @ref ADC_EOCSelection. */ 112 113 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 114 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 115 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 116 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 117 for low frequency applications. 118 This parameter can be set to ENABLE or DISABLE. 119 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 120 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 121 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 122 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 123 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 124 125 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 126 after the first ADC conversion start trigger occurred (software start or external trigger). 127 This parameter can be set to ENABLE or DISABLE. */ 128 129 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 130 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 131 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 132 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 133 continuous mode or external trigger that could launch a conversion). */ 134 135 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 136 (main sequence subdivided in successive parts). 137 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 138 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 139 This parameter can be set to ENABLE or DISABLE. */ 140 141 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 142 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 143 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 144 145 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 146 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 147 This parameter can be a value of @ref ADC_regular_external_trigger_source. 148 Caution: external trigger source is common to all ADC instances. */ 149 150 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 151 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 152 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 153 154 uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. 155 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 156 This parameter can be a value of @ref ADC_ConversionDataManagement. 157 Note: This parameter must be modified when no conversion is on going on both regular and injected groups 158 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 159 160 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 161 This parameter applies to ADC group regular only. 162 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 163 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 164 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 165 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 166 Note: Error reporting with respect to the conversion mode: 167 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 168 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 169 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 170 171 uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling. 172 This parameter can be a value of @ref ADCEx_Left_Bit_Shift */ 173 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 174 This parameter can be set to ENABLE or DISABLE. 175 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 176 177 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 178 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 179 180 } ADC_InitTypeDef; 181 182 /** 183 * @brief Structure definition of ADC channel for regular group 184 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 185 * ADC state can be either: 186 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 187 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 188 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 189 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 190 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 191 * on the fly). 192 */ 193 typedef struct 194 { 195 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 196 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 197 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 198 199 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 200 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 201 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 202 the new channel setting (or parameter number of conversions adjusted) */ 203 204 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 205 Unit: ADC clock cycles 206 Conversion time is the addition of sampling time and processing time 207 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 208 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 209 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 210 It overwrites the last setting. 211 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 212 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 213 Refer to device datasheet for timings values. */ 214 215 uint32_t SingleDiff; /*!< Select single-ended or differential input. 216 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 217 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 218 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 219 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 220 It overwrites the last setting. 221 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 222 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 223 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 224 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 225 of another parameter update on the fly) */ 226 227 uint32_t OffsetNumber; /*!< Select the offset number 228 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 229 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 230 231 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 232 Offset value must be a positive number. 233 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 234 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 235 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 236 without continuous mode or external trigger that could launch a conversion). */ 237 238 FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. 239 This parameter is applied only for 16-bit or 8-bit resolution. 240 This parameter can be set to ENABLE or DISABLE.*/ 241 242 FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not. 243 This parameter is applied only for 16-bit or 8-bit resolution. 244 This parameter can be set to ENABLE or DISABLE. */ 245 246 } ADC_ChannelConfTypeDef; 247 248 /** 249 * @brief Structure definition of ADC analog watchdog 250 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 251 * ADC state can be either: 252 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 253 */ 254 typedef struct 255 { 256 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 257 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 258 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 259 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 260 261 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 262 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 263 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 264 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 265 266 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 267 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 268 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 269 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 270 271 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 272 This parameter can be set to ENABLE or DISABLE */ 273 274 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 275 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 276 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 277 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 278 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 279 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 280 impacted: the comparison of analog watchdog thresholds is done 281 on oversampling intermediate computation (after ratio, before shift 282 application): intermediate register bitfield [32:7] (26 most significant bits). */ 283 284 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 285 Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number 286 between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. 287 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 288 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 289 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 290 impacted: the comparison of analog watchdog thresholds is done 291 on oversampling intermediate computation (after ratio, before shift 292 application): intermediate register bitfield [32:7] (26 most significant bits). */ 293 } ADC_AnalogWDGConfTypeDef; 294 295 /** 296 * @brief ADC group injected contexts queue configuration 297 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 298 */ 299 typedef struct 300 { 301 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 302 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 303 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 304 305 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 306 } ADC_InjectionConfigTypeDef; 307 308 /** @defgroup ADC_States ADC States 309 * @{ 310 */ 311 312 /** 313 * @brief HAL ADC state machine: ADC states definition (bitfields) 314 * @note ADC state machine is managed by bitfields, state must be compared 315 * with bit by bit. 316 * For example: 317 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 318 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 319 */ 320 /* States of ADC global scope */ 321 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 322 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 323 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 324 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 325 326 /* States of ADC errors */ 327 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 328 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 329 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 330 331 /* States of ADC group regular */ 332 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 333 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 334 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 335 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 336 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 337 338 /* States of ADC group injected */ 339 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 340 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 341 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 342 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 343 344 /* States of ADC analog watchdogs */ 345 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 346 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 347 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 348 349 /* States of ADC multi-mode */ 350 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 351 352 /** 353 * @} 354 */ 355 356 /** 357 * @brief ADC handle Structure definition 358 */ 359 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 360 typedef struct __ADC_HandleTypeDef 361 #else 362 typedef struct 363 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 364 { 365 ADC_TypeDef *Instance; /*!< Register base address */ 366 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 367 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 368 HAL_LockTypeDef Lock; /*!< ADC locking object */ 369 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 370 __IO uint32_t ErrorCode; /*!< ADC Error code */ 371 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 372 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 373 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 374 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 375 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 376 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 377 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 378 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 379 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 380 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 381 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 382 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 383 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 384 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 385 } ADC_HandleTypeDef; 386 387 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 388 /** 389 * @brief HAL ADC Callback ID enumeration definition 390 */ 391 typedef enum 392 { 393 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 394 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 395 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 396 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 397 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 398 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 399 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 400 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 401 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 402 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 403 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 404 } HAL_ADC_CallbackIDTypeDef; 405 406 /** 407 * @brief HAL ADC Callback pointer definition 408 */ 409 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 410 411 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 412 413 /** 414 * @} 415 */ 416 417 418 /* Exported constants --------------------------------------------------------*/ 419 420 /** @defgroup ADC_Exported_Constants ADC Exported Constants 421 * @{ 422 */ 423 424 /** @defgroup ADC_Error_Code ADC Error Code 425 * @{ 426 */ 427 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 428 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 429 enable/disable, erroneous state, ...) */ 430 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 431 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 432 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 433 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 434 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 435 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 436 /** 437 * @} 438 */ 439 440 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 441 * @{ 442 */ 443 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 444 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 445 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 446 447 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 448 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 449 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 450 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 451 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 452 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 453 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 454 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 455 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 456 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 457 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 458 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 459 /** 460 * @} 461 */ 462 463 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 464 * @{ 465 */ 466 #define ADC_RESOLUTION_16B (LL_ADC_RESOLUTION_16B) /*!< ADC resolution 16 bits */ 467 #define ADC_RESOLUTION_14B (LL_ADC_RESOLUTION_14B) /*!< ADC resolution 14 bits */ 468 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 469 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 470 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 471 /** 472 * @} 473 */ 474 475 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 476 * @{ 477 */ 478 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 479 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 480 /** 481 * @} 482 */ 483 484 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 485 * @{ 486 */ 487 /* ADC group regular trigger sources for all ADC instances */ 488 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 489 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 490 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 491 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 492 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 493 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 494 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 495 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */ 496 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 497 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 498 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 499 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 500 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 501 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 502 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 503 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 504 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 505 #define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 506 #define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 507 #define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */ 508 /** 509 * @} 510 */ 511 512 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 513 * @{ 514 */ 515 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 516 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 517 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 518 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 519 /** 520 * @} 521 */ 522 523 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 524 * @{ 525 */ 526 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 527 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 528 /** 529 * @} 530 */ 531 532 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 533 * @{ 534 */ 535 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 536 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 537 /** 538 * @} 539 */ 540 541 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 542 * @{ 543 */ 544 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 545 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 546 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 547 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 548 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 549 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 550 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 551 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 552 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 553 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 554 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 555 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 556 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 557 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 558 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 559 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 565 * @{ 566 */ 567 #define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycles */ 568 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 569 #define ADC_SAMPLETIME_8CYCLES_5 (LL_ADC_SAMPLINGTIME_8CYCLES_5) /*!< Sampling time 8.5 ADC clock cycles */ 570 #define ADC_SAMPLETIME_16CYCLES_5 (LL_ADC_SAMPLINGTIME_16CYCLES_5) /*!< Sampling time 16.5 ADC clock cycles */ 571 #define ADC_SAMPLETIME_32CYCLES_5 (LL_ADC_SAMPLINGTIME_32CYCLES_5) /*!< Sampling time 32.5 ADC clock cycles */ 572 #define ADC_SAMPLETIME_64CYCLES_5 (LL_ADC_SAMPLINGTIME_64CYCLES_5) /*!< Sampling time 64.5 ADC clock cycles */ 573 #define ADC_SAMPLETIME_387CYCLES_5 (LL_ADC_SAMPLINGTIME_387CYCLES_5) /*!< Sampling time 387.5 ADC clock cycles */ 574 #define ADC_SAMPLETIME_810CYCLES_5 (LL_ADC_SAMPLINGTIME_810CYCLES_5) /*!< Sampling time 810.5 ADC clock cycles */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode 580 * @{ 581 */ 582 #define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET) 583 #define ADC_CALIB_OFFSET_LINEARITY (LL_ADC_CALIB_OFFSET_LINEARITY) 584 /** 585 * @} 586 */ 587 588 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 589 * @{ 590 */ 591 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 592 /* all ADC instances (refer to Reference Manual). */ 593 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 594 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 595 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 596 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 597 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 598 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 599 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 600 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 601 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 602 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 603 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 604 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 605 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 606 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 607 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 608 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 609 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 610 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 611 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 612 #define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ 613 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC2. */ 614 #define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel connected to VddCore, channel specific to ADC2. */ 615 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC2. */ 616 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC2. */ 617 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 618 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management 624 * @{ 625 */ 626 #define ADC_CONVERSIONDATA_DR (0x00000000UL) /*!< Regular Conversion data stored in DR register only */ 627 #define ADC_CONVERSIONDATA_DFSDM (ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */ 628 #define ADC_CONVERSIONDATA_DMA_ONESHOT (ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */ 629 #define ADC_CONVERSIONDATA_DMA_CIRCULAR (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1) /*!< DMA circular mode selected */ 630 /** 631 * @} 632 */ 633 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 634 * @{ 635 */ 636 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 637 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 638 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 639 /** 640 * @} 641 */ 642 643 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 644 * @{ 645 */ 646 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 647 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 648 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 649 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 650 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 651 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 652 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 653 /** 654 * @} 655 */ 656 657 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 658 * @{ 659 */ 660 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 661 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 662 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 663 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 664 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 665 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 666 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 667 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 668 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 669 #define ADC_RIGHTBITSHIFT_9 (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */ 670 #define ADC_RIGHTBITSHIFT_10 (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */ 671 #define ADC_RIGHTBITSHIFT_11 (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */ 672 /** 673 * @} 674 */ 675 676 /** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift 677 * @{ 678 */ 679 #define ADC_LEFTBITSHIFT_NONE (LL_ADC_LEFT_BIT_SHIFT_NONE) /*!< ADC No bit shift */ 680 #define ADC_LEFTBITSHIFT_1 (LL_ADC_LEFT_BIT_SHIFT_1) /*!< ADC 1 bit shift */ 681 #define ADC_LEFTBITSHIFT_2 (LL_ADC_LEFT_BIT_SHIFT_2) /*!< ADC 2 bits shift */ 682 #define ADC_LEFTBITSHIFT_3 (LL_ADC_LEFT_BIT_SHIFT_3) /*!< ADC 3 bits shift */ 683 #define ADC_LEFTBITSHIFT_4 (LL_ADC_LEFT_BIT_SHIFT_4) /*!< ADC 4 bits shift */ 684 #define ADC_LEFTBITSHIFT_5 (LL_ADC_LEFT_BIT_SHIFT_5) /*!< ADC 5 bits shift */ 685 #define ADC_LEFTBITSHIFT_6 (LL_ADC_LEFT_BIT_SHIFT_6) /*!< ADC 6 bits shift */ 686 #define ADC_LEFTBITSHIFT_7 (LL_ADC_LEFT_BIT_SHIFT_7) /*!< ADC 7 bits shift */ 687 #define ADC_LEFTBITSHIFT_8 (LL_ADC_LEFT_BIT_SHIFT_8) /*!< ADC 8 bits shift */ 688 #define ADC_LEFTBITSHIFT_9 (LL_ADC_LEFT_BIT_SHIFT_9) /*!< ADC 9 bits shift */ 689 #define ADC_LEFTBITSHIFT_10 (LL_ADC_LEFT_BIT_SHIFT_10) /*!< ADC 10 bits shift */ 690 #define ADC_LEFTBITSHIFT_11 (LL_ADC_LEFT_BIT_SHIFT_11) /*!< ADC 11 bits shift */ 691 #define ADC_LEFTBITSHIFT_12 (LL_ADC_LEFT_BIT_SHIFT_12) /*!< ADC 12 bits shift */ 692 #define ADC_LEFTBITSHIFT_13 (LL_ADC_LEFT_BIT_SHIFT_13) /*!< ADC 13 bits shift */ 693 #define ADC_LEFTBITSHIFT_14 (LL_ADC_LEFT_BIT_SHIFT_14) /*!< ADC 14 bits shift */ 694 #define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */ 695 /** 696 * @} 697 */ 698 699 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 700 * @{ 701 */ 702 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 703 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 704 /** 705 * @} 706 */ 707 708 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 709 * @{ 710 */ 711 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 712 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup ADC_Event_type ADC Event type 718 * @{ 719 */ 720 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 721 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 722 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 723 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 724 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 725 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 726 /** 727 * @} 728 */ 729 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 730 731 /** @defgroup ADC_interrupts_definition ADC interrupts definition 732 * @{ 733 */ 734 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 735 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 736 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 737 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 738 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 739 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 740 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 741 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 742 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 743 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 744 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 745 746 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 747 748 /** 749 * @} 750 */ 751 752 /** @defgroup ADC_flags_definition ADC flags definition 753 * @{ 754 */ 755 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 756 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 757 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 758 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 759 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 760 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 761 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 762 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 763 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 764 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 765 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 766 767 /** 768 * @} 769 */ 770 771 /** 772 * @} 773 */ 774 775 /* Private macro -------------------------------------------------------------*/ 776 777 /** @defgroup ADC_Private_Macros ADC Private Macros 778 * @{ 779 */ 780 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 781 /* code of final user. */ 782 783 /** 784 * @brief Verify the ADC data conversion setting. 785 * @param DATA : programmed DATA conversion mode. 786 * @retval SET (DATA is a valid value) or RESET (DATA is invalid) 787 */ 788 #define IS_ADC_CONVERSIONDATAMGT(DATA) \ 789 ((((DATA) == ADC_CONVERSIONDATA_DR)) || \ 790 (((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \ 791 (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \ 792 (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR))) 793 794 /** 795 * @brief Return resolution bits in CFGR register RES[1:0] field. 796 * @param __HANDLE__ ADC handle 797 * @retval Value of bitfield RES in CFGR register. 798 */ 799 #define ADC_GET_RESOLUTION(__HANDLE__) \ 800 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 801 802 /** 803 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 804 * @param __HANDLE__ ADC handle 805 * @retval None 806 */ 807 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 808 809 /** 810 * @brief Verification of ADC state: enabled or disabled. 811 * @param __HANDLE__ ADC handle 812 * @retval SET (ADC enabled) or RESET (ADC disabled) 813 */ 814 #define ADC_IS_ENABLE(__HANDLE__) \ 815 ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 816 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 817 ) ? SET : RESET) 818 819 /** 820 * @brief Check if conversion is on going on regular group. 821 * @param __HANDLE__ ADC handle 822 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 823 */ 824 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 825 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 826 827 /** 828 * @brief Check if ADC clock mode is synchronous 829 * @param __HANDLE__: ADC handle 830 * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous) 831 */ 832 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__) \ 833 (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \ 834 ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL): RESET) 835 836 /** 837 * @brief Simultaneously clear and set specific bits of the handle State. 838 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 839 * the first parameter is the ADC handle State, the second parameter is the 840 * bit field to clear, the third and last parameter is the bit field to set. 841 * @retval None 842 */ 843 #define ADC_STATE_CLR_SET MODIFY_REG 844 845 /** 846 * @brief Verify that a given value is aligned with the ADC resolution range. 847 * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits). 848 * @param __ADC_VALUE__ value checked against the resolution. 849 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 850 */ 851 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 852 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 853 854 /** 855 * @brief Verify the length of the scheduled regular conversions group. 856 * @param __LENGTH__ number of programmed conversions. 857 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 858 */ 859 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 860 861 862 /** 863 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 864 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 865 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 866 */ 867 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 868 869 870 /** 871 * @brief Verify the ADC clock setting. 872 * @param __ADC_CLOCK__ programmed ADC clock. 873 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 874 */ 875 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 876 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 877 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 878 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 879 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 880 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 881 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 882 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 883 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 884 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 885 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 886 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 887 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 888 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 889 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 890 891 /** 892 * @brief Verify the ADC resolution setting. 893 * @param __RESOLUTION__ programmed ADC resolution. 894 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 895 */ 896 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \ 897 ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \ 898 ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 899 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 900 ((__RESOLUTION__) == ADC_RESOLUTION_8B) ) 901 /** 902 * @brief Verify the ADC resolution setting when limited to 8 bits. 903 * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits. 904 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 905 */ 906 #define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B)) 907 908 /** 909 * @brief Verify the ADC scan mode. 910 * @param __SCAN_MODE__ programmed ADC scan mode. 911 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 912 */ 913 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 914 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 915 916 /** 917 * @brief Verify the ADC edge trigger setting for regular group. 918 * @param __EDGE__ programmed ADC edge trigger setting. 919 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 920 */ 921 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 922 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 923 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 924 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 925 926 /** 927 * @brief Verify the ADC regular conversions external trigger. 928 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 929 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 930 */ 931 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 932 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 933 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 934 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 935 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 936 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 937 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 938 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 939 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 940 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 941 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 942 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 943 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 944 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 945 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 946 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 947 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \ 948 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \ 949 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \ 950 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 951 952 /** 953 * @brief Verify the ADC regular conversions check for converted data availability. 954 * @param __EOC_SELECTION__ converted data availability check. 955 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 956 */ 957 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 958 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 959 960 /** 961 * @brief Verify the ADC regular conversions overrun handling. 962 * @param __OVR__ ADC regular conversions overrun handling. 963 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 964 */ 965 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 966 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 967 968 /** 969 * @brief Verify the ADC conversions sampling time. 970 * @param __TIME__ ADC conversions sampling time. 971 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 972 */ 973 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \ 974 ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 975 ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \ 976 ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \ 977 ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \ 978 ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \ 979 ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \ 980 ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) ) 981 982 /** 983 * @brief Verify the ADC regular channel setting. 984 * @param __CHANNEL__ programmed ADC regular channel. 985 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 986 */ 987 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 988 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 989 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 990 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 991 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 992 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 993 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 994 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 995 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 996 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 997 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 998 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 999 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 1000 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 1001 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 1002 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 1003 1004 /** 1005 * @} 1006 */ 1007 1008 1009 /* Private constants ---------------------------------------------------------*/ 1010 1011 /** @defgroup ADC_Private_Constants ADC Private Constants 1012 * @{ 1013 */ 1014 1015 /* Fixed timeout values for ADC conversion (including sampling time) */ 1016 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1017 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1018 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1019 /* Minimum ADC Clock frequency is 0.14 MHz */ 1020 /* Maximum conversion time is */ 1021 /* 653 / 0.14 MHz = 4.66 ms */ 1022 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1023 1024 /* Delay for temperature sensor stabilization time. */ 1025 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1026 /* Unit: us */ 1027 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1028 1029 /* Delay for ADC voltage regulator startup time */ 1030 /* Maximum delay is 10 microseconds */ 1031 /* (refer device RM, parameter Tadcvreg_stup). */ 1032 #define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */ 1033 1034 /** 1035 * @} 1036 */ 1037 1038 /* Exported macro ------------------------------------------------------------*/ 1039 1040 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1041 * @{ 1042 */ 1043 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1044 /* final user. */ 1045 1046 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1047 * @{ 1048 */ 1049 1050 /** @brief Reset ADC handle state. 1051 * @param __HANDLE__ ADC handle 1052 * @retval None 1053 */ 1054 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1055 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1056 do{ \ 1057 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1058 (__HANDLE__)->MspInitCallback = NULL; \ 1059 (__HANDLE__)->MspDeInitCallback = NULL; \ 1060 } while(0) 1061 #else 1062 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1063 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1064 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1065 1066 /** 1067 * @brief Enable ADC interrupt. 1068 * @param __HANDLE__ ADC handle 1069 * @param __INTERRUPT__ ADC Interrupt 1070 * This parameter can be one of the following values: 1071 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1072 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1073 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1074 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1075 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1076 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1077 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1078 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1079 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1080 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1081 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1082 * @retval None 1083 */ 1084 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1085 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1086 1087 /** 1088 * @brief Disable ADC interrupt. 1089 * @param __HANDLE__ ADC handle 1090 * @param __INTERRUPT__ ADC Interrupt 1091 * This parameter can be one of the following values: 1092 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1093 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1094 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1095 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1096 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1097 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1098 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1099 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1100 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1101 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1102 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1103 * @retval None 1104 */ 1105 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1106 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1107 1108 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1109 * @param __HANDLE__ ADC handle 1110 * @param __INTERRUPT__ ADC interrupt source to check 1111 * This parameter can be one of the following values: 1112 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1113 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1114 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1115 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1116 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1117 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1118 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1119 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1120 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1121 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1122 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1123 * @retval State of interruption (SET or RESET) 1124 */ 1125 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1126 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1127 1128 /** 1129 * @brief Check whether the specified ADC flag is set or not. 1130 * @param __HANDLE__ ADC handle 1131 * @param __FLAG__ ADC flag 1132 * This parameter can be one of the following values: 1133 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1134 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1135 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1136 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1137 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1138 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1139 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1140 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1141 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1142 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1143 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1144 * @retval State of flag (TRUE or FALSE). 1145 */ 1146 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1147 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1148 1149 /** 1150 * @brief Clear the specified ADC flag. 1151 * @param __HANDLE__ ADC handle 1152 * @param __FLAG__ ADC flag 1153 * This parameter can be one of the following values: 1154 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1155 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1156 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1157 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1158 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1159 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1160 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1161 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1162 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1163 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1164 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1165 * @retval None 1166 */ 1167 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1168 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1169 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1170 1171 /** 1172 * @} 1173 */ 1174 1175 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1176 * @{ 1177 */ 1178 1179 /** 1180 * @brief Helper macro to get ADC channel number in decimal format 1181 * from literals ADC_CHANNEL_x. 1182 * @note Example: 1183 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1184 * will return decimal number "4". 1185 * @note The input can be a value from functions where a channel 1186 * number is returned, either defined with number 1187 * or with bitfield (only one bit must be set). 1188 * @param __CHANNEL__ This parameter can be one of the following values: 1189 * @arg @ref ADC_CHANNEL_0 (3) 1190 * @arg @ref ADC_CHANNEL_1 (3) 1191 * @arg @ref ADC_CHANNEL_2 (3) 1192 * @arg @ref ADC_CHANNEL_3 (3) 1193 * @arg @ref ADC_CHANNEL_4 (3) 1194 * @arg @ref ADC_CHANNEL_5 (3) 1195 * @arg @ref ADC_CHANNEL_6 1196 * @arg @ref ADC_CHANNEL_7 1197 * @arg @ref ADC_CHANNEL_8 1198 * @arg @ref ADC_CHANNEL_9 1199 * @arg @ref ADC_CHANNEL_10 1200 * @arg @ref ADC_CHANNEL_11 1201 * @arg @ref ADC_CHANNEL_12 1202 * @arg @ref ADC_CHANNEL_13 1203 * @arg @ref ADC_CHANNEL_14 1204 * @arg @ref ADC_CHANNEL_15 1205 * @arg @ref ADC_CHANNEL_16 1206 * @arg @ref ADC_CHANNEL_17 1207 * @arg @ref ADC_CHANNEL_18 1208 * @arg @ref ADC_CHANNEL_19 1209 * @arg @ref ADC_CHANNEL_VREFINT (1) 1210 * @arg @ref ADC_CHANNEL_VCORE (1) 1211 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1212 * @arg @ref ADC_CHANNEL_VBAT (1) 1213 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1214 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1215 * 1216 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1217 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1218 * Other channels are slow channels (conversion rate: refer to reference manual). 1219 * @retval Value between Min_Data=0 and Max_Data=18 1220 */ 1221 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1222 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1223 1224 /** 1225 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1226 * from number in decimal format. 1227 * @note Example: 1228 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1229 * will return a data equivalent to "ADC_CHANNEL_4". 1230 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1231 * @retval Returned value can be one of the following values: 1232 * @arg @ref ADC_CHANNEL_0 (3) 1233 * @arg @ref ADC_CHANNEL_1 (3) 1234 * @arg @ref ADC_CHANNEL_2 (3) 1235 * @arg @ref ADC_CHANNEL_3 (3) 1236 * @arg @ref ADC_CHANNEL_4 (3) 1237 * @arg @ref ADC_CHANNEL_5 (3) 1238 * @arg @ref ADC_CHANNEL_6 1239 * @arg @ref ADC_CHANNEL_7 1240 * @arg @ref ADC_CHANNEL_8 1241 * @arg @ref ADC_CHANNEL_9 1242 * @arg @ref ADC_CHANNEL_10 1243 * @arg @ref ADC_CHANNEL_11 1244 * @arg @ref ADC_CHANNEL_12 1245 * @arg @ref ADC_CHANNEL_13 1246 * @arg @ref ADC_CHANNEL_14 1247 * @arg @ref ADC_CHANNEL_15 1248 * @arg @ref ADC_CHANNEL_16 1249 * @arg @ref ADC_CHANNEL_17 1250 * @arg @ref ADC_CHANNEL_18 1251 * @arg @ref ADC_CHANNEL_19 1252 * @arg @ref ADC_CHANNEL_VREFINT (1) 1253 * @arg @ref ADC_CHANNEL_VCORE (1) 1254 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1255 * @arg @ref ADC_CHANNEL_VBAT (1) 1256 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1257 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1258 * 1259 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1260 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1261 * Other channels are slow channels (conversion rate: refer to reference manual).\n 1262 * (1) For ADC channel read back from ADC register, 1263 * comparison with internal channel parameter to be done 1264 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1265 */ 1266 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1267 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1268 1269 /** 1270 * @brief Helper macro to determine whether the selected channel 1271 * corresponds to literal definitions of driver. 1272 * @note The different literal definitions of ADC channels are: 1273 * - ADC internal channel: 1274 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1275 * - ADC external channel (channel connected to a GPIO pin): 1276 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1277 * @note The channel parameter must be a value defined from literal 1278 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1279 * ADC_CHANNEL_TEMPSENSOR, ...), 1280 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1281 * must not be a value from functions where a channel number is 1282 * returned from ADC registers, 1283 * because internal and external channels share the same channel 1284 * number in ADC registers. The differentiation is made only with 1285 * parameters definitions of driver. 1286 * @param __CHANNEL__ This parameter can be one of the following values: 1287 * @arg @ref ADC_CHANNEL_0 (3) 1288 * @arg @ref ADC_CHANNEL_1 (3) 1289 * @arg @ref ADC_CHANNEL_2 (3) 1290 * @arg @ref ADC_CHANNEL_3 (3) 1291 * @arg @ref ADC_CHANNEL_4 (3) 1292 * @arg @ref ADC_CHANNEL_5 (3) 1293 * @arg @ref ADC_CHANNEL_6 1294 * @arg @ref ADC_CHANNEL_7 1295 * @arg @ref ADC_CHANNEL_8 1296 * @arg @ref ADC_CHANNEL_9 1297 * @arg @ref ADC_CHANNEL_10 1298 * @arg @ref ADC_CHANNEL_11 1299 * @arg @ref ADC_CHANNEL_12 1300 * @arg @ref ADC_CHANNEL_13 1301 * @arg @ref ADC_CHANNEL_14 1302 * @arg @ref ADC_CHANNEL_15 1303 * @arg @ref ADC_CHANNEL_16 1304 * @arg @ref ADC_CHANNEL_17 1305 * @arg @ref ADC_CHANNEL_18 1306 * @arg @ref ADC_CHANNEL_19 1307 * @arg @ref ADC_CHANNEL_VREFINT (1) 1308 * @arg @ref ADC_CHANNEL_VCORE (1) 1309 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1310 * @arg @ref ADC_CHANNEL_VBAT (1) 1311 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1312 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1313 * 1314 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1315 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1316 * Other channels are slow channels (conversion rate: refer to reference manual). 1317 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1318 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1319 */ 1320 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1321 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1322 1323 /** 1324 * @brief Helper macro to convert a channel defined from parameter 1325 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1326 * ADC_CHANNEL_TEMPSENSOR, ...), 1327 * to its equivalent parameter definition of a ADC external channel 1328 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1329 * @note The channel parameter can be, additionally to a value 1330 * defined from parameter definition of a ADC internal channel 1331 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1332 * a value defined from parameter definition of 1333 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1334 * or a value from functions where a channel number is returned 1335 * from ADC registers. 1336 * @param __CHANNEL__ This parameter can be one of the following values: 1337 * @arg @ref ADC_CHANNEL_0 (3) 1338 * @arg @ref ADC_CHANNEL_1 (3) 1339 * @arg @ref ADC_CHANNEL_2 (3) 1340 * @arg @ref ADC_CHANNEL_3 (3) 1341 * @arg @ref ADC_CHANNEL_4 (3) 1342 * @arg @ref ADC_CHANNEL_5 (3) 1343 * @arg @ref ADC_CHANNEL_6 1344 * @arg @ref ADC_CHANNEL_7 1345 * @arg @ref ADC_CHANNEL_8 1346 * @arg @ref ADC_CHANNEL_9 1347 * @arg @ref ADC_CHANNEL_10 1348 * @arg @ref ADC_CHANNEL_11 1349 * @arg @ref ADC_CHANNEL_12 1350 * @arg @ref ADC_CHANNEL_13 1351 * @arg @ref ADC_CHANNEL_14 1352 * @arg @ref ADC_CHANNEL_15 1353 * @arg @ref ADC_CHANNEL_16 1354 * @arg @ref ADC_CHANNEL_17 1355 * @arg @ref ADC_CHANNEL_18 1356 * @arg @ref ADC_CHANNEL_19 1357 * @arg @ref ADC_CHANNEL_VREFINT (1) 1358 * @arg @ref ADC_CHANNEL_VCORE (1) 1359 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1360 * @arg @ref ADC_CHANNEL_VBAT (1) 1361 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1362 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1363 * 1364 * (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n 1365 * (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). 1366 * Other channels are slow channels (conversion rate: refer to reference manual). 1367 * @retval Returned value can be one of the following values: 1368 * @arg @ref ADC_CHANNEL_0 1369 * @arg @ref ADC_CHANNEL_1 1370 * @arg @ref ADC_CHANNEL_2 1371 * @arg @ref ADC_CHANNEL_3 1372 * @arg @ref ADC_CHANNEL_4 1373 * @arg @ref ADC_CHANNEL_5 1374 * @arg @ref ADC_CHANNEL_6 1375 * @arg @ref ADC_CHANNEL_7 1376 * @arg @ref ADC_CHANNEL_8 1377 * @arg @ref ADC_CHANNEL_9 1378 * @arg @ref ADC_CHANNEL_10 1379 * @arg @ref ADC_CHANNEL_11 1380 * @arg @ref ADC_CHANNEL_12 1381 * @arg @ref ADC_CHANNEL_13 1382 * @arg @ref ADC_CHANNEL_14 1383 * @arg @ref ADC_CHANNEL_15 1384 * @arg @ref ADC_CHANNEL_16 1385 * @arg @ref ADC_CHANNEL_17 1386 * @arg @ref ADC_CHANNEL_18 1387 */ 1388 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1389 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1390 1391 /** 1392 * @brief Helper macro to determine whether the internal channel 1393 * selected is available on the ADC instance selected. 1394 * @note The channel parameter must be a value defined from parameter 1395 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1396 * ADC_CHANNEL_TEMPSENSOR, ...), 1397 * must not be a value defined from parameter definition of 1398 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1399 * or a value from functions where a channel number is 1400 * returned from ADC registers, 1401 * because internal and external channels share the same channel 1402 * number in ADC registers. The differentiation is made only with 1403 * parameters definitions of driver. 1404 * @param __ADC_INSTANCE__ ADC instance 1405 * @param __CHANNEL__ This parameter can be one of the following values: 1406 * @arg @ref ADC_CHANNEL_VREFINT (1) 1407 * @arg @ref ADC_CHANNEL_VCORE (1) 1408 * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) 1409 * @arg @ref ADC_CHANNEL_VBAT (1) 1410 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1) 1411 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1) 1412 * 1413 * (1) On STM32MP1, parameter available only on ADC instance: ADC2. 1414 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1415 * Value "1" if the internal channel selected is available on the ADC instance selected. 1416 */ 1417 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1418 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1419 1420 #if defined(ADC_MULTIMODE_SUPPORT) 1421 /** 1422 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1423 * or ADC slave from raw value with both ADC conversion data concatenated. 1424 * @note This macro is intended to be used when multimode transfer by DMA 1425 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1426 * In this case the transferred data need to processed with this macro 1427 * to separate the conversion data of ADC master and ADC slave. 1428 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1429 * @arg @ref LL_ADC_MULTI_MASTER 1430 * @arg @ref LL_ADC_MULTI_SLAVE 1431 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1432 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1433 */ 1434 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1435 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1436 #endif /* ADC_MULTIMODE_SUPPORT */ 1437 1438 /** 1439 * @brief Helper macro to select the ADC common instance 1440 * to which is belonging the selected ADC instance. 1441 * @note ADC common register instance can be used for: 1442 * - Set parameters common to several ADC instances 1443 * - Multimode (for devices with several ADC instances) 1444 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1445 * @param __ADCx__ ADC instance 1446 * @retval ADC common register instance 1447 */ 1448 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1449 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1450 1451 /** 1452 * @brief Helper macro to check if all ADC instances sharing the same 1453 * ADC common instance are disabled. 1454 * @note This check is required by functions with setting conditioned to 1455 * ADC state: 1456 * All ADC instances of the ADC common group must be disabled. 1457 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1458 * @note On devices with only 1 ADC common instance, parameter of this macro 1459 * is useless and can be ignored (parameter kept for compatibility 1460 * with devices featuring several ADC common instances). 1461 * @param __ADCXY_COMMON__ ADC common instance 1462 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1463 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1464 * are disabled. 1465 * Value "1" if at least one ADC instance sharing the same ADC common instance 1466 * is enabled. 1467 */ 1468 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1469 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1470 1471 /** 1472 * @brief Helper macro to define the ADC conversion data full-scale digital 1473 * value corresponding to the selected ADC resolution. 1474 * @note ADC conversion data full-scale corresponds to voltage range 1475 * determined by analog voltage references Vref+ and Vref- 1476 * (refer to reference manual). 1477 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1478 * @arg @ref ADC_RESOLUTION_16B 1479 * @arg @ref ADC_RESOLUTION_14B 1480 * @arg @ref ADC_RESOLUTION_12B 1481 * @arg @ref ADC_RESOLUTION_10B 1482 * @arg @ref ADC_RESOLUTION_8B 1483 * @retval ADC conversion data full-scale digital value 1484 */ 1485 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1486 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1487 1488 /** 1489 * @brief Helper macro to convert the ADC conversion data from 1490 * a resolution to another resolution. 1491 * @param __DATA__ ADC conversion data to be converted 1492 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1493 * This parameter can be one of the following values: 1494 * @arg @ref ADC_RESOLUTION_16B 1495 * @arg @ref ADC_RESOLUTION_14B 1496 * @arg @ref ADC_RESOLUTION_12B 1497 * @arg @ref ADC_RESOLUTION_10B 1498 * @arg @ref ADC_RESOLUTION_8B 1499 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1500 * This parameter can be one of the following values: 1501 * @arg @ref ADC_RESOLUTION_16B 1502 * @arg @ref ADC_RESOLUTION_14B 1503 * @arg @ref ADC_RESOLUTION_12B 1504 * @arg @ref ADC_RESOLUTION_10B 1505 * @arg @ref ADC_RESOLUTION_8B 1506 * @retval ADC conversion data to the requested resolution 1507 */ 1508 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1509 __ADC_RESOLUTION_CURRENT__,\ 1510 __ADC_RESOLUTION_TARGET__) \ 1511 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1512 (__ADC_RESOLUTION_CURRENT__),\ 1513 (__ADC_RESOLUTION_TARGET__)) 1514 1515 /** 1516 * @brief Helper macro to calculate the voltage (unit: mVolt) 1517 * corresponding to a ADC conversion data (unit: digital value). 1518 * @note Analog reference voltage (Vref+) must be either known from 1519 * user board environment or can be calculated using ADC measurement 1520 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1521 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1522 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1523 * (unit: digital value). 1524 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1525 * @arg @ref ADC_RESOLUTION_16B 1526 * @arg @ref ADC_RESOLUTION_14B 1527 * @arg @ref ADC_RESOLUTION_12B 1528 * @arg @ref ADC_RESOLUTION_10B 1529 * @arg @ref ADC_RESOLUTION_8B 1530 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1531 */ 1532 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1533 __ADC_DATA__,\ 1534 __ADC_RESOLUTION__) \ 1535 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1536 (__ADC_DATA__),\ 1537 (__ADC_RESOLUTION__)) 1538 1539 /** 1540 * @brief Helper macro to calculate analog reference voltage (Vref+) 1541 * (unit: mVolt) from ADC conversion data of internal voltage 1542 * reference VrefInt. 1543 * @note Computation is using VrefInt calibration value 1544 * stored in system memory for each device during production. 1545 * @note This voltage depends on user board environment: voltage level 1546 * connected to pin Vref+. 1547 * On devices with small package, the pin Vref+ is not present 1548 * and internally bonded to pin Vdda. 1549 * @note On this STM32 series, calibration data of internal voltage reference 1550 * VrefInt corresponds to a resolution of 12 bits, 1551 * this is the recommended ADC resolution to convert voltage of 1552 * internal voltage reference VrefInt. 1553 * Otherwise, this macro performs the processing to scale 1554 * ADC conversion data to 12 bits. 1555 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1556 * of internal voltage reference VrefInt (unit: digital value). 1557 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1558 * @arg @ref ADC_RESOLUTION_16B 1559 * @arg @ref ADC_RESOLUTION_14B 1560 * @arg @ref ADC_RESOLUTION_12B 1561 * @arg @ref ADC_RESOLUTION_10B 1562 * @arg @ref ADC_RESOLUTION_8B 1563 * @retval Analog reference voltage (unit: mV) 1564 */ 1565 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1566 __ADC_RESOLUTION__) \ 1567 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1568 (__ADC_RESOLUTION__)) 1569 1570 /** 1571 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1572 * from ADC conversion data of internal temperature sensor. 1573 * @note Computation is using temperature sensor calibration values 1574 * stored in system memory for each device during production. 1575 * @note Calculation formula: 1576 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1577 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1578 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1579 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1580 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1581 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1582 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1583 * TEMP_DEGC_CAL1 (calibrated in factory) 1584 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1585 * TEMP_DEGC_CAL2 (calibrated in factory) 1586 * Caution: Calculation relevancy under reserve that calibration 1587 * parameters are correct (address and data). 1588 * To calculate temperature using temperature sensor 1589 * datasheet typical values (generic values less, therefore 1590 * less accurate than calibrated values), 1591 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1592 * @note As calculation input, the analog reference voltage (Vref+) must be 1593 * defined as it impacts the ADC LSB equivalent voltage. 1594 * @note Analog reference voltage (Vref+) must be either known from 1595 * user board environment or can be calculated using ADC measurement 1596 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1597 * @note On this STM32 series, calibration data of temperature sensor 1598 * corresponds to a resolution of 12 bits, 1599 * this is the recommended ADC resolution to convert voltage of 1600 * temperature sensor. 1601 * Otherwise, this macro performs the processing to scale 1602 * ADC conversion data to 12 bits. 1603 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1604 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1605 * temperature sensor (unit: digital value). 1606 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1607 * sensor voltage has been measured. 1608 * This parameter can be one of the following values: 1609 * @arg @ref ADC_RESOLUTION_16B 1610 * @arg @ref ADC_RESOLUTION_14B 1611 * @arg @ref ADC_RESOLUTION_12B 1612 * @arg @ref ADC_RESOLUTION_10B 1613 * @arg @ref ADC_RESOLUTION_8B 1614 * @retval Temperature (unit: degree Celsius) 1615 */ 1616 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1617 __TEMPSENSOR_ADC_DATA__,\ 1618 __ADC_RESOLUTION__) \ 1619 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1620 (__TEMPSENSOR_ADC_DATA__),\ 1621 (__ADC_RESOLUTION__)) 1622 1623 /** 1624 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1625 * from ADC conversion data of internal temperature sensor. 1626 * @note Computation is using temperature sensor typical values 1627 * (refer to device datasheet). 1628 * @note Calculation formula: 1629 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1630 * / Avg_Slope + CALx_TEMP 1631 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1632 * (unit: digital value) 1633 * Avg_Slope = temperature sensor slope 1634 * (unit: uV/Degree Celsius) 1635 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1636 * temperature CALx_TEMP (unit: mV) 1637 * Caution: Calculation relevancy under reserve the temperature sensor 1638 * of the current device has characteristics in line with 1639 * datasheet typical values. 1640 * If temperature sensor calibration values are available on 1641 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1642 * temperature calculation will be more accurate using 1643 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1644 * @note As calculation input, the analog reference voltage (Vref+) must be 1645 * defined as it impacts the ADC LSB equivalent voltage. 1646 * @note Analog reference voltage (Vref+) must be either known from 1647 * user board environment or can be calculated using ADC measurement 1648 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1649 * @note ADC measurement data must correspond to a resolution of 12bits 1650 * (full scale digital value 4095). If not the case, the data must be 1651 * preliminarily rescaled to an equivalent resolution of 12 bits. 1652 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1653 * On STM32MP1, refer to device datasheet parameter "Avg_Slope". 1654 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1655 * On STM32MP1, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1656 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1657 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1658 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1659 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1660 * This parameter can be one of the following values: 1661 * @arg @ref ADC_RESOLUTION_16B 1662 * @arg @ref ADC_RESOLUTION_14B 1663 * @arg @ref ADC_RESOLUTION_12B 1664 * @arg @ref ADC_RESOLUTION_10B 1665 * @arg @ref ADC_RESOLUTION_8B 1666 * @retval Temperature (unit: degree Celsius) 1667 */ 1668 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1669 __TEMPSENSOR_TYP_CALX_V__,\ 1670 __TEMPSENSOR_CALX_TEMP__,\ 1671 __VREFANALOG_VOLTAGE__,\ 1672 __TEMPSENSOR_ADC_DATA__,\ 1673 __ADC_RESOLUTION__) \ 1674 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1675 (__TEMPSENSOR_TYP_CALX_V__),\ 1676 (__TEMPSENSOR_CALX_TEMP__),\ 1677 (__VREFANALOG_VOLTAGE__),\ 1678 (__TEMPSENSOR_ADC_DATA__),\ 1679 (__ADC_RESOLUTION__)) 1680 1681 /** 1682 * @} 1683 */ 1684 1685 /** 1686 * @} 1687 */ 1688 1689 /* Include ADC HAL Extended module */ 1690 #include "stm32mp1xx_hal_adc_ex.h" 1691 1692 /* Exported functions --------------------------------------------------------*/ 1693 /** @addtogroup ADC_Exported_Functions 1694 * @{ 1695 */ 1696 1697 /** @addtogroup ADC_Exported_Functions_Group1 1698 * @brief Initialization and Configuration functions 1699 * @{ 1700 */ 1701 /* Initialization and de-initialization functions ****************************/ 1702 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1703 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1704 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1705 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1706 1707 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1708 /* Callbacks Register/UnRegister functions ***********************************/ 1709 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1710 pADC_CallbackTypeDef pCallback); 1711 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1712 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1713 /** 1714 * @} 1715 */ 1716 1717 /** @addtogroup ADC_Exported_Functions_Group2 1718 * @brief IO operation functions 1719 * @{ 1720 */ 1721 /* IO operation functions *****************************************************/ 1722 1723 /* Blocking mode: Polling */ 1724 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1725 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1726 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1727 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1728 1729 /* Non-blocking mode: Interruption */ 1730 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1731 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1732 1733 /* Non-blocking mode: DMA */ 1734 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1735 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1736 1737 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1738 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1739 1740 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1741 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1742 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1743 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1744 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1745 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1746 /** 1747 * @} 1748 */ 1749 1750 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1751 * @brief Peripheral Control functions 1752 * @{ 1753 */ 1754 /* Peripheral Control functions ***********************************************/ 1755 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); 1756 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); 1757 1758 /** 1759 * @} 1760 */ 1761 1762 /* Peripheral State functions *************************************************/ 1763 /** @addtogroup ADC_Exported_Functions_Group4 1764 * @{ 1765 */ 1766 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1767 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1768 1769 /** 1770 * @} 1771 */ 1772 1773 /** 1774 * @} 1775 */ 1776 1777 /* Private functions -----------------------------------------------------------*/ 1778 /** @addtogroup ADC_Private_Functions ADC Private Functions 1779 * @{ 1780 */ 1781 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1782 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1783 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1784 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1785 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1786 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1787 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc); 1788 1789 /** 1790 * @} 1791 */ 1792 1793 /** 1794 * @} 1795 */ 1796 1797 /** 1798 * @} 1799 */ 1800 1801 #ifdef __cplusplus 1802 } 1803 #endif 1804 1805 1806 #endif /* STM32MP1xx_HAL_ADC_H */ 1807
