1 /**
2 ******************************************************************************
3 * @file system_stm32l5xx_s.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
6 * to be used in secure application when the system implements
7 * the TrustZone-M security.
8 *
9 * This file provides two functions and one global variable to be called from
10 * user application:
11 * - SystemInit(): This function is called at secure startup just after reset
12 * and before branch to secure main program.
13 * This call is made inside the "startup_stm32l5xx.s" file.
14 *
15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
16 * by the user application to setup the SysTick
17 * timer or configure other parameters.
18 *
19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
20 * be called whenever the core clock is changed
21 * during program execution.
22 *
23 * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update
24 * the variable SystemCoreClock and return
25 * its value to the non-secure calling
26 * application. It must be called whenever
27 * the core clock is changed during program
28 * execution.
29 *
30 * After each device reset the MSI (4 MHz) is used as system clock source.
31 * Then SystemInit() function is called, in "startup_stm32l5xx.s" file, to
32 * configure the system clock before to branch to main program.
33 *
34 * This file insures the system clock as follows:
35 *=============================================================================
36 *-----------------------------------------------------------------------------
37 * System Clock source | MSI
38 *-----------------------------------------------------------------------------
39 * SYSCLK(Hz) | 4000000
40 *-----------------------------------------------------------------------------
41 * HCLK(Hz) | 4000000
42 *-----------------------------------------------------------------------------
43 * AHB Prescaler | 1
44 *-----------------------------------------------------------------------------
45 * APB1 Prescaler | 1
46 *-----------------------------------------------------------------------------
47 * APB2 Prescaler | 1
48 *-----------------------------------------------------------------------------
49 * PLL_SRC | No clock
50 *-----------------------------------------------------------------------------
51 * PLL_M | 1
52 *-----------------------------------------------------------------------------
53 * PLL_N | 8
54 *-----------------------------------------------------------------------------
55 * PLL_P | 7
56 *-----------------------------------------------------------------------------
57 * PLL_Q | 2
58 *-----------------------------------------------------------------------------
59 * PLL_R | 2
60 *-----------------------------------------------------------------------------
61 * PLLSAI1_SRC | NA
62 *-----------------------------------------------------------------------------
63 * PLLSAI1_M | NA
64 *-----------------------------------------------------------------------------
65 * PLLSAI1_N | NA
66 *-----------------------------------------------------------------------------
67 * PLLSAI1_P | NA
68 *-----------------------------------------------------------------------------
69 * PLLSAI1_Q | NA
70 *-----------------------------------------------------------------------------
71 * PLLSAI1_R | NA
72 *-----------------------------------------------------------------------------
73 * PLLSAI2_SRC | NA
74 *-----------------------------------------------------------------------------
75 * PLLSAI2_M | NA
76 *-----------------------------------------------------------------------------
77 * PLLSAI2_N | NA
78 *-----------------------------------------------------------------------------
79 * PLLSAI2_P | NA
80 *-----------------------------------------------------------------------------
81 * Require 48MHz for USB FS, | Disabled
82 * SDIO and RNG clock |
83 *-----------------------------------------------------------------------------
84 *=============================================================================
85 ******************************************************************************
86 * @attention
87 *
88 * Copyright (c) 2019 STMicroelectronics.
89 * All rights reserved.
90 *
91 * This software is licensed under terms that can be found in the LICENSE file
92 * in the root directory of this software component.
93 * If no LICENSE file comes with this software, it is provided AS-IS.
94 *
95 ******************************************************************************
96 */
97
98 /** @addtogroup CMSIS
99 * @{
100 */
101
102 /** @addtogroup STM32L5xx_System
103 * @{
104 */
105
106 /** @addtogroup STM32L5xx_System_Private_Includes
107 * @{
108 */
109
110 #include "stm32l5xx.h"
111 #include "partition_stm32l5xx.h" /* Trustzone-M core secure attributes */
112
113 /**
114 * @}
115 */
116
117 /** @addtogroup STM32L5xx_System_Private_TypesDefinitions
118 * @{
119 */
120
121 #if defined ( __ICCARM__ )
122 # define CMSE_NS_ENTRY __cmse_nonsecure_entry
123 #else
124 # define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry))
125 #endif
126
127 /**
128 * @}
129 */
130
131 /** @addtogroup STM32L5xx_System_Private_Defines
132 * @{
133 */
134
135 #if !defined (HSE_VALUE)
136 #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
137 #endif /* HSE_VALUE */
138
139 #if !defined (MSI_VALUE)
140 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
141 #endif /* MSI_VALUE */
142
143 #if !defined (HSI_VALUE)
144 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
145 #endif /* HSI_VALUE */
146
147 /* Note: Following vector table addresses must be defined in line with linker
148 configuration. */
149 /*!< Uncomment the following line if you need to relocate the vector table
150 anywhere in Flash or Sram, else the vector table is kept at the automatic
151 remap of boot address selected */
152 /* #define USER_VECT_TAB_ADDRESS */
153
154 #if defined(USER_VECT_TAB_ADDRESS)
155 /*!< Uncomment the following line if you need to relocate your vector Table
156 in Sram else user remap will be done in Flash. */
157 /* #define VECT_TAB_SRAM */
158
159 #if defined(VECT_TAB_SRAM)
160 #define VECT_TAB_BASE_ADDRESS SRAM1_BASE_S /*!< Vector Table base address field.
161 This value must be a multiple of 0x200. */
162 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
163 This value must be a multiple of 0x200. */
164 #else
165 #define VECT_TAB_BASE_ADDRESS FLASH_BASE_S /*!< Vector Table base address field.
166 This value must be a multiple of 0x200. */
167 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
168 This value must be a multiple of 0x200. */
169 #endif /* VECT_TAB_SRAM */
170 #endif /* USER_VECT_TAB_ADDRESS */
171
172 /******************************************************************************/
173 /**
174 * @}
175 */
176
177 /** @addtogroup STM32L5xx_System_Private_Macros
178 * @{
179 */
180
181 /**
182 * @}
183 */
184
185 /** @addtogroup STM32L5xx_System_Private_Variables
186 * @{
187 */
188 /* The SystemCoreClock variable is updated in three ways:
189 1) by calling CMSIS function SystemCoreClockUpdate()
190 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
191 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
192 Note: If you use this function to configure the system clock; then there
193 is no need to call the 2 first functions listed above, since SystemCoreClock
194 variable is updated automatically.
195 */
196 uint32_t SystemCoreClock = 4000000U;
197
198 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
199 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
200 const uint32_t MSIRangeTable[16] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
201 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U, \
202 0U, 0U, 0U, 0U}; /* MISRAC-2012: 0U for unexpected value */
203 /**
204 * @}
205 */
206
207 /** @addtogroup STM32L5xx_System_Private_FunctionPrototypes
208 * @{
209 */
210
211 /**
212 * @}
213 */
214
215 /** @addtogroup STM32L5xx_System_Private_Functions
216 * @{
217 */
218
219 /**
220 * @brief Setup the microcontroller system.
221 * @retval None
222 */
223
SystemInit(void)224 void SystemInit(void)
225 {
226 /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */
227 TZ_SAU_Setup();
228
229 /* Configure the Vector Table location -------------------------------------*/
230 #if defined(USER_VECT_TAB_ADDRESS)
231 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
232 #endif
233
234 /* FPU settings ------------------------------------------------------------*/
235 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
236 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
237
238 SCB_NS->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
239 #endif
240 }
241
242 /**
243 * @brief Update SystemCoreClock variable according to Clock Register Values.
244 * The SystemCoreClock variable contains the core clock (HCLK), it can
245 * be used by the user application to setup the SysTick timer or configure
246 * other parameters.
247 *
248 * @note Depending on secure or non-secure compilation, the adequate RCC peripheral
249 * memory are is accessed thanks to RCC alias defined in stm32l5xxxx.h device file
250 * so either from RCC_S peripheral register mapped memory in secure or from
251 * RCC_NS peripheral register mapped memory in non-secure.
252 *
253 * @note Each time the core clock (HCLK) changes, this function must be called
254 * to update SystemCoreClock variable value. Otherwise, any configuration
255 * based on this variable will be incorrect.
256 *
257 * @note - The system frequency computed by this function is not the real
258 * frequency in the chip. It is calculated based on the predefined
259 * constant and the selected clock source:
260 *
261 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
262 *
263 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
264 *
265 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
266 *
267 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
268 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
269 *
270 * (*) MSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
271 * 4 MHz) but the real value may vary depending on the variations
272 * in voltage and temperature.
273 *
274 * (**) HSI_VALUE is a constant defined in stm32l5xx_hal.h file (default value
275 * 16 MHz) but the real value may vary depending on the variations
276 * in voltage and temperature.
277 *
278 * (***) HSE_VALUE is a constant defined in stm32l5xx_hal.h file (default value
279 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
280 * frequency of the crystal used. Otherwise, this function may
281 * have wrong result.
282 *
283 * - The result of this function could be not correct when using fractional
284 * value for HSE crystal.
285 *
286 * @retval None
287 */
SystemCoreClockUpdate(void)288 void SystemCoreClockUpdate(void)
289 {
290 uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
291
292 /* Get MSI Range frequency--------------------------------------------------*/
293 if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
294 { /* MSISRANGE from RCC_CSR applies */
295 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
296 }
297 else
298 { /* MSIRANGE from RCC_CR applies */
299 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
300 }
301 /*MSI frequency range in HZ*/
302 msirange = MSIRangeTable[msirange];
303
304 /* Get SYSCLK source -------------------------------------------------------*/
305 switch (RCC->CFGR & RCC_CFGR_SWS)
306 {
307 case 0x00: /* MSI used as system clock source */
308 SystemCoreClock = msirange;
309 break;
310
311 case 0x04: /* HSI used as system clock source */
312 SystemCoreClock = HSI_VALUE;
313 break;
314
315 case 0x08: /* HSE used as system clock source */
316 SystemCoreClock = HSE_VALUE;
317 break;
318
319 case 0x0C: /* PLL used as system clock source */
320 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
321 SYSCLK = PLL_VCO / PLLR
322 */
323 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
324 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
325
326 switch (pllsource)
327 {
328 case 0x02: /* HSI used as PLL clock source */
329 pllvco = (HSI_VALUE / pllm);
330 break;
331
332 case 0x03: /* HSE used as PLL clock source */
333 pllvco = (HSE_VALUE / pllm);
334 break;
335
336 default: /* MSI used as PLL clock source */
337 pllvco = (msirange / pllm);
338 break;
339 }
340 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
341 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
342 SystemCoreClock = pllvco/pllr;
343 break;
344
345 default:
346 SystemCoreClock = msirange;
347 break;
348 }
349 /* Compute HCLK clock frequency --------------------------------------------*/
350 /* Get HCLK prescaler */
351 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
352 /* HCLK clock frequency */
353 SystemCoreClock >>= tmp;
354 }
355
356
357 /**
358 * @brief Secure Non-Secure-Callable function to return the current
359 * SystemCoreClock value after SystemCoreClock update.
360 * The SystemCoreClock variable contains the core clock (HCLK), it can
361 * be used by the user application to setup the SysTick timer or configure
362 * other parameters.
363 * @retval SystemCoreClock value (HCLK)
364 */
SECURE_SystemCoreClockUpdate(void)365 CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void)
366 {
367 SystemCoreClockUpdate();
368
369 return SystemCoreClock;
370 }
371
372 /**
373 * @}
374 */
375
376 /**
377 * @}
378 */
379
380 /**
381 * @}
382 */
383
