1 /**
2 ******************************************************************************
3 * @file stm32l5xx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file in
18 * the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32l5xx_hal.h"
25
26 /** @addtogroup STM32L5xx_HAL_Driver
27 * @{
28 */
29
30 /** @defgroup PWR PWR
31 * @brief PWR HAL module driver
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private define ------------------------------------------------------------*/
39
40 /** @defgroup PWR_Private_Defines PWR Private Defines
41 * @{
42 */
43
44 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
45 * @{
46 */
47 #define PVD_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVD threshold crossing */
48 #define PVD_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVD threshold crossing */
49 #define PVD_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVD trigger */
50 #define PVD_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVD trigger */
51 /**
52 * @}
53 */
54
55 /**
56 * @}
57 */
58
59 /* Private macro -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private function prototypes -----------------------------------------------*/
62 /* Exported functions --------------------------------------------------------*/
63
64 /** @defgroup PWR_Exported_Functions PWR Exported Functions
65 * @{
66 */
67
68 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
69 * @brief Initialization and de-initialization functions
70 *
71 @verbatim
72 ===============================================================================
73 ##### Initialization and de-initialization functions #####
74 ===============================================================================
75 [..]
76
77 @endverbatim
78 * @{
79 */
80
81 /**
82 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
83 * @retval None
84 */
HAL_PWR_DeInit(void)85 void HAL_PWR_DeInit(void)
86 {
87 __HAL_RCC_PWR_FORCE_RESET();
88 __HAL_RCC_PWR_RELEASE_RESET();
89 }
90
91 /**
92 * @brief Enable access to the backup domain
93 * (RTC registers, RTC backup data registers).
94 * @note After reset, the backup domain is protected against
95 * possible unwanted write accesses.
96 * @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
97 * In order to set or modify the RTC clock, the backup domain access must be
98 * disabled.
99 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
100 * back-up domain.
101 * @retval None
102 */
HAL_PWR_EnableBkUpAccess(void)103 void HAL_PWR_EnableBkUpAccess(void)
104 {
105 SET_BIT(PWR->CR1, PWR_CR1_DBP);
106 }
107
108 /**
109 * @brief Disable access to the backup domain
110 * (RTC registers, RTC backup data registers).
111 * @retval None
112 */
HAL_PWR_DisableBkUpAccess(void)113 void HAL_PWR_DisableBkUpAccess(void)
114 {
115 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
116 }
117
118
119
120
121 /**
122 * @}
123 */
124
125
126
127 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
128 * @brief Low Power modes configuration functions
129 *
130 @verbatim
131
132 ===============================================================================
133 ##### Peripheral Control functions #####
134 ===============================================================================
135
136 [..]
137 *** PVD configuration ***
138 =========================
139 [..]
140 (+) The PVD is used to monitor the VDD power supply by comparing it to a
141 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
142
143 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
144 than the PVD threshold. This event is internally connected to the EXTI
145 line16 and can generate an interrupt if enabled. This is done through
146 __HAL_PVD_EXTI_ENABLE_IT() macro.
147 (+) The PVD is stopped in Standby mode.
148
149
150 *** WakeUp pin configuration ***
151 ================================
152 [..]
153 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
154 The polarity of these pins can be set to configure event detection on high
155 level (rising edge) or low level (falling edge).
156
157
158
159 *** Low Power modes configuration ***
160 =====================================
161 [..]
162 The devices feature 8 low-power modes:
163 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
164 (+) Sleep mode: Cortex-M33 core clock stopped, peripherals kept running, main and low power regulators on.
165 (+) Low-power Sleep mode: Cortex-M33 core clock stopped, peripherals kept running, main regulator off, low power regulator on.
166 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
167 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
168 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
169 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
170 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
171 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
172
173
174 *** Low-power run mode ***
175 ==========================
176 [..]
177 (+) Entry: (from main run mode)
178 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
179
180 (+) Exit:
181 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
182 then can the system clock frequency be increased above 2 MHz.
183
184
185 *** Sleep mode / Low-power sleep mode ***
186 =========================================
187 [..]
188 (+) Entry:
189 The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
190 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
191 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
192 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
193 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
194 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
195 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
196
197 (+) WFI Exit:
198 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
199 controller (NVIC) or any wake-up event.
200
201 (+) WFE Exit:
202 (++) Any wake-up event such as an EXTI line configured in event mode.
203
204 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
205 the MCU is in Low-power Run mode.
206
207 *** Stop 0, Stop 1 and Stop 2 modes ***
208 ===============================
209 [..]
210 (+) Entry:
211 The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
212 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
213 (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
214 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
215 (++) PWR_MAINREGULATOR_ON
216 (++) PWR_LOWPOWERREGULATOR_ON
217 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
218 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
219 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
220
221 (+) WFI Exit:
222 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
223 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
224 when programmed in wakeup mode.
225 (+) WFE Exit:
226 (++) Any EXTI Line (Internal or External) configured in Event mode.
227
228 [..]
229 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
230 depending on the LPR bit setting.
231 When exiting Stop 2 mode, the MCU is in Run mode.
232
233 *** Standby mode ***
234 ====================
235 [..]
236 The Standby mode offers two options:
237 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
238 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
239 and Standby circuitry.
240 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
241 SRAM and register contents are lost except for the RTC registers, RTC backup registers
242 and Standby circuitry.
243
244 (++) Entry:
245 (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
246 SRAM1 and register contents are lost except for registers in the Backup domain and
247 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
248 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
249 to set RRS bit.
250
251 (++) Exit:
252 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
253 external reset in NRST pin, IWDG reset.
254
255 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
256
257
258 *** Shutdown mode ***
259 ======================
260 [..]
261 In Shutdown mode,
262 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
263 SRAM and registers contents are lost except for backup domain registers.
264
265 (+) Entry:
266 The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
267
268 (+) Exit:
269 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
270 external reset in NRST pin.
271
272 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
273
274
275 *** Auto-wakeup (AWU) from low-power mode ***
276 =============================================
277 [..]
278 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
279 Wakeup event, a tamper event or a time-stamp event, without depending on
280 an external interrupt (Auto-wakeup mode).
281
282 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
283
284
285 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
286 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
287
288 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
289 is necessary to configure the RTC to detect the tamper or time stamp event using the
290 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
291
292 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
293 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
294
295 @endverbatim
296 * @{
297 */
298
299
300
301 /**
302 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
303 * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
304 * configuration information.
305 * @note Refer to the electrical characteristics of your device datasheet for
306 * more details about the voltage thresholds corresponding to each
307 * detection level.
308 * @retval None
309 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)310 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
311 {
312 /* Check the parameters */
313 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
314 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
315
316 /* Set PLS bits according to PVDLevel value */
317 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
318
319 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
320 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
321 __HAL_PWR_PVD_EXTI_DISABLE_IT();
322 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
323 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
324
325 /* Configure interrupt mode */
326 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
327 {
328 __HAL_PWR_PVD_EXTI_ENABLE_IT();
329 }
330
331 /* Configure event mode */
332 if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
333 {
334 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
335 }
336
337 /* Configure the edge */
338 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
339 {
340 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
341 }
342
343 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
344 {
345 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
346 }
347
348 return HAL_OK;
349 }
350
351
352 /**
353 * @brief Enable the Power Voltage Detector (PVD).
354 * @retval None
355 */
HAL_PWR_EnablePVD(void)356 void HAL_PWR_EnablePVD(void)
357 {
358 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
359 }
360
361 /**
362 * @brief Disable the Power Voltage Detector (PVD).
363 * @retval None
364 */
HAL_PWR_DisablePVD(void)365 void HAL_PWR_DisablePVD(void)
366 {
367 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
368 }
369
370
371
372
373 /**
374 * @brief Enable the WakeUp PINx functionality.
375 * @param WakeUpPinPolarity specifies which Wake-Up pin to enable.
376 * This parameter can be one of the following legacy values which set the default polarity
377 * i.e. detection on high level (rising edge):
378 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
379 *
380 * or one of the following value where the user can explicitly specify the enabled pin and
381 * the chosen polarity:
382 * @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
383 * @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
384 * @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
385 * @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
386 * @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
387 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
388 * @retval None
389 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)390 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
391 {
392 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
393
394 /* Specifies the Wake-Up pin polarity for the event detection
395 (rising or falling edge) */
396 MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
397
398 /* Enable wake-up pin */
399 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
400
401
402 }
403
404 /**
405 * @brief Disable the WakeUp PINx functionality.
406 * @param WakeUpPinx specifies the Power Wake-Up pin to disable.
407 * This parameter can be one of the following values:
408 * @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
409 * @retval None
410 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)411 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
412 {
413 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
414
415 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
416 }
417
418
419 /**
420 * @brief Enter Sleep or Low-power Sleep mode.
421 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
422 * @param Regulator specifies the regulator state in Sleep/Low-power Sleep mode.
423 * This parameter can be one of the following values:
424 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
425 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
426 * @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
427 * in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
428 * to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
429 * Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
430 * Additionally, the clock frequency must be reduced below 2 MHz.
431 * Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
432 * be done before calling HAL_PWR_EnterSLEEPMode() API.
433 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
434 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
435 * @param SLEEPEntry specifies if Sleep mode is entered with WFI or WFE instruction.
436 * This parameter can be one of the following values:
437 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
438 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
439 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
440 * the interrupt wake up source.
441 * @retval None
442 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)443 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
444 {
445 /* Check the parameters */
446 assert_param(IS_PWR_REGULATOR(Regulator));
447 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
448
449 /* Set Regulator parameter */
450 if (Regulator == PWR_MAINREGULATOR_ON)
451 {
452 /* If in low-power run mode at this point, exit it */
453 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
454 {
455 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
456 {
457 return ;
458 }
459 }
460 /* Regulator now in main mode. */
461 }
462 else
463 {
464 /* If in run mode, first move to low-power run mode.
465 The system clock frequency must be below 2 MHz at this point. */
466 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
467 {
468 HAL_PWREx_EnableLowPowerRunMode();
469 }
470 }
471
472 /* Clear SLEEPDEEP bit of Cortex System Control Register */
473 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
474
475 /* Select SLEEP mode entry -------------------------------------------------*/
476 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
477 {
478 /* Request Wait For Interrupt */
479 __WFI();
480 }
481 else
482 {
483 /* Request Wait For Event */
484 __SEV();
485 __WFE();
486 __WFE();
487 }
488
489 }
490
491
492 /**
493 * @brief Enter Stop mode
494 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
495 * on devices where only "Stop mode" is mentioned with main or low power regulator ON.
496 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
497 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
498 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
499 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
500 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
501 * only to the peripheral requesting it.
502 * SRAM1, SRAM2 and register contents are preserved.
503 * The BOR is available.
504 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
505 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
506 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
507 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
508 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
509 * startup delay is incurred when waking up.
510 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
511 * is higher although the startup time is reduced.
512 * @param Regulator specifies the regulator state in Stop mode.
513 * This parameter can be one of the following values:
514 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
515 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
516 * @param STOPEntry specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
517 * This parameter can be one of the following values:
518 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
519 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
520 * @retval None
521 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)522 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
523 {
524 /* Check the parameters */
525 assert_param(IS_PWR_REGULATOR(Regulator));
526
527 if (Regulator == PWR_LOWPOWERREGULATOR_ON)
528 {
529 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
530 }
531 else
532 {
533 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
534 }
535 }
536
537 /**
538 * @brief Enter Standby mode.
539 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
540 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
541 * in which case the regulator is in low-power mode.
542 * SRAM1 and register contents are lost except for registers in the Backup domain and
543 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
544 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
545 * to set RRS bit.
546 * The BOR is available.
547 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
548 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
549 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
550 * same.
551 * These states are effective in Standby mode only if APC bit is set through
552 * HAL_PWREx_EnablePullUpPullDownConfig() API.
553 * @retval None
554 */
HAL_PWR_EnterSTANDBYMode(void)555 void HAL_PWR_EnterSTANDBYMode(void)
556 {
557 /* Set Stand-by mode */
558 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
559
560 /* Set SLEEPDEEP bit of Cortex System Control Register */
561 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
562
563 /* This option is used to ensure that store operations are completed */
564 #if defined ( __CC_ARM)
565 __force_stores();
566 #endif
567 /* Request Wait For Interrupt */
568 __WFI();
569 }
570
571
572
573 /**
574 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
575 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
576 * re-enters SLEEP mode when an interruption handling is over.
577 * Setting this bit is useful when the processor is expected to run only on
578 * interruptions handling.
579 * @retval None
580 */
HAL_PWR_EnableSleepOnExit(void)581 void HAL_PWR_EnableSleepOnExit(void)
582 {
583 /* Set SLEEPONEXIT bit of Cortex System Control Register */
584 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
585 }
586
587
588 /**
589 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
590 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
591 * re-enters SLEEP mode when an interruption handling is over.
592 * @retval None
593 */
HAL_PWR_DisableSleepOnExit(void)594 void HAL_PWR_DisableSleepOnExit(void)
595 {
596 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
597 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
598 }
599
600
601
602 /**
603 * @brief Enable CORTEX M4 SEVONPEND bit.
604 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
605 * WFE to wake up when an interrupt moves from inactive to pended.
606 * @retval None
607 */
HAL_PWR_EnableSEVOnPend(void)608 void HAL_PWR_EnableSEVOnPend(void)
609 {
610 /* Set SEVONPEND bit of Cortex System Control Register */
611 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
612 }
613
614
615 /**
616 * @brief Disable CORTEX M4 SEVONPEND bit.
617 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
618 * WFE to wake up when an interrupt moves from inactive to pended.
619 * @retval None
620 */
HAL_PWR_DisableSEVOnPend(void)621 void HAL_PWR_DisableSEVOnPend(void)
622 {
623 /* Clear SEVONPEND bit of Cortex System Control Register */
624 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
625 }
626
627
628
629
630
631 /**
632 * @brief PWR PVD interrupt callback
633 * @retval None
634 */
HAL_PWR_PVDCallback(void)635 __weak void HAL_PWR_PVDCallback(void)
636 {
637 /* NOTE : This function should not be modified; when the callback is needed,
638 the HAL_PWR_PVDCallback can be implemented in the user file
639 */
640 }
641
642 /**
643 * @}
644 */
645
646 /** @defgroup PWR_Exported_Functions_Group3 Attributes management functions
647 * @brief Attributes management functions.
648 *
649 @verbatim
650 ===============================================================================
651 ##### PWR attributes functions #####
652 ===============================================================================
653
654 @endverbatim
655 * @{
656 */
657
658 /**
659 * @brief Configure the PWR item attribute(s).
660 * @note Available attributes are to secure items and set PWR as privileged.
661 * Default state is not secure and unprivileged access allowed.
662 * @note Secure and non-secure attributes can only be set from the secure
663 * state when the system implements the security (TZEN=1).
664 * @note Security and privilege attributes can be set independently.
665 * @param Item Item(s) to set attributes on.
666 * This parameter can be a one or a combination of @ref PWR_items
667 * @param Attributes can be one or a combination of the following values:
668 * @arg @ref PWR_PRIV Privileged-only access
669 * @arg @ref PWR_NPRIV Privileged/Non-privileged access
670 * @arg @ref PWR_SEC Secure-only access
671 * @arg @ref PWR_NSEC Secure/Non-secure access
672 * @retval None
673 */
HAL_PWR_ConfigAttributes(uint32_t Item,uint32_t Attributes)674 void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes)
675 {
676 /* Check the parameters */
677 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
678 assert_param(IS_PWR_ATTRIBUTES(Attributes));
679
680 /* Privilege/non-privilege attribute */
681 if ((Attributes & PWR_PRIV) == PWR_PRIV)
682 {
683 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
684 }
685 else if ((Attributes & PWR_NPRIV) == PWR_NPRIV)
686 {
687 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
688 }
689 else
690 {
691 /* do nothing */
692 }
693
694
695 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
696
697 /* Secure/non-secure attribute */
698 if ((Attributes & PWR_SEC) == PWR_SEC)
699 {
700 SET_BIT(PWR_S->SECCFGR, Item);
701 }
702 else if ((Attributes & PWR_NSEC) == PWR_NSEC)
703 {
704 CLEAR_BIT(PWR_S->SECCFGR, Item);
705 }
706 else
707 {
708 /* do nothing */
709 }
710
711 #endif /* __ARM_FEATURE_CMSE */
712 }
713
714 /**
715 * @brief Get the attribute of a PWR item.
716 * @note Secure and non-secure attributes are only available from secure state
717 * when the system implements the security (TZEN=1)
718 * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from.
719 * @param pAttributes pointer to return the attributes.
720 * @retval HAL Status.
721 */
HAL_PWR_GetConfigAttributes(uint32_t Item,uint32_t * pAttributes)722 HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes)
723 {
724 uint32_t attributes;
725
726 /* Check null pointer */
727 if (pAttributes == NULL)
728 {
729 return HAL_ERROR;
730 }
731
732 /* Check the parameters */
733 assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item));
734
735 /* Get privilege or non-privilege attribute */
736 if (READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) != 0x00U)
737 {
738 attributes = PWR_PRIV;
739 }
740 else
741 {
742 attributes = PWR_NPRIV;
743 }
744
745 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
746
747 /* Get the secure or non-secure attribute state */
748 if ((PWR_S->SECCFGR & Item) == Item)
749 {
750 attributes |= PWR_SEC;
751 }
752 else
753 {
754 attributes |= PWR_NSEC;
755 }
756
757 #endif /* __ARM_FEATURE_CMSE */
758
759 /* return value */
760 *pAttributes = attributes;
761
762 return HAL_OK;
763 }
764
765 /**
766 * @}
767 */
768
769 /**
770 * @}
771 */
772
773 #endif /* HAL_PWR_MODULE_ENABLED */
774 /**
775 * @}
776 */
777
778 /**
779 * @}
780 */
781
