1 /** 2 ****************************************************************************** 3 * @file stm32_hal_legacy.h 4 * @author MCD Application Team 5 * @brief This file contains aliases definition for the STM32Cube HAL constants 6 * macros and functions maintained for legacy purpose. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32_HAL_LEGACY 22 #define STM32_HAL_LEGACY 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 /* Exported types ------------------------------------------------------------*/ 30 /* Exported constants --------------------------------------------------------*/ 31 32 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose 33 * @{ 34 */ 35 #define AES_FLAG_RDERR CRYP_FLAG_RDERR 36 #define AES_FLAG_WRERR CRYP_FLAG_WRERR 37 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF 38 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR 39 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR 40 #if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) 41 #define CRYP_DATATYPE_32B CRYP_NO_SWAP 42 #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP 43 #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP 44 #define CRYP_DATATYPE_1B CRYP_BIT_SWAP 45 #if defined(STM32U5) 46 #define CRYP_CCF_CLEAR CRYP_CLEAR_CCF 47 #define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF 48 #endif /* STM32U5 */ 49 #endif /* STM32U5 || STM32H7 || STM32MP1 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose 55 * @{ 56 */ 57 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B 58 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B 59 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B 60 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B 61 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN 62 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED 63 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV 64 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV 65 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV 66 #define REGULAR_GROUP ADC_REGULAR_GROUP 67 #define INJECTED_GROUP ADC_INJECTED_GROUP 68 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP 69 #define AWD_EVENT ADC_AWD_EVENT 70 #define AWD1_EVENT ADC_AWD1_EVENT 71 #define AWD2_EVENT ADC_AWD2_EVENT 72 #define AWD3_EVENT ADC_AWD3_EVENT 73 #define OVR_EVENT ADC_OVR_EVENT 74 #define JQOVF_EVENT ADC_JQOVF_EVENT 75 #define ALL_CHANNELS ADC_ALL_CHANNELS 76 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS 77 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS 78 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR 79 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT 80 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 81 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 82 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 83 #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 84 #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 85 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO 86 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 87 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO 88 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 89 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO 90 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 91 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 92 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE 93 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING 94 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING 95 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING 96 #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 97 98 #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY 99 #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY 100 #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC 101 #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC 102 #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL 103 #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL 104 #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 105 106 #if defined(STM32H7) 107 #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT 108 #endif /* STM32H7 */ 109 110 #if defined(STM32U5) 111 #define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES 112 #define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES 113 #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 114 #endif /* STM32U5 */ 115 116 /** 117 * @} 118 */ 119 120 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose 121 * @{ 122 */ 123 124 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG 125 126 /** 127 * @} 128 */ 129 130 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose 131 * @{ 132 */ 133 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE 134 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE 135 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 136 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 137 #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 138 #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 139 #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 140 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 141 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 142 #if defined(STM32L0) 143 #define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ 144 #endif 145 #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR 146 #if defined(STM32F373xC) || defined(STM32F378xx) 147 #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 148 #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR 149 #endif /* STM32F373xC || STM32F378xx */ 150 151 #if defined(STM32L0) || defined(STM32L4) 152 #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON 153 154 #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 155 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 156 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 157 #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 158 #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 159 #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 160 161 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT 162 #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT 163 #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT 164 #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT 165 #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 166 #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 167 #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 168 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 169 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 170 #if defined(STM32L0) 171 /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ 172 /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ 173 /* to the second dedicated IO (only for COMP2). */ 174 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 175 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 176 #else 177 #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 178 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 179 #endif 180 #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 181 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 182 183 #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW 184 #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH 185 186 /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ 187 /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ 188 #if defined(COMP_CSR_LOCK) 189 #define COMP_FLAG_LOCK COMP_CSR_LOCK 190 #elif defined(COMP_CSR_COMP1LOCK) 191 #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK 192 #elif defined(COMP_CSR_COMPxLOCK) 193 #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK 194 #endif 195 196 #if defined(STM32L4) 197 #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 198 #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 199 #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 200 #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 201 #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 202 #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 203 #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE 204 #endif 205 206 #if defined(STM32L0) 207 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED 208 #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER 209 #else 210 #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED 211 #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED 212 #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER 213 #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER 214 #endif 215 216 #endif 217 218 #if defined(STM32U5) 219 #define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG 220 #endif 221 222 /** 223 * @} 224 */ 225 226 /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose 227 * @{ 228 */ 229 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig 230 #if defined(STM32U5) 231 #define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE 232 #define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE 233 #define MPU_DEVICE_nGRE MPU_DEVICE_NGRE 234 #endif /* STM32U5 */ 235 /** 236 * @} 237 */ 238 239 /** @defgroup CRC_Aliases CRC API aliases 240 * @{ 241 */ 242 #if defined(STM32C0) 243 #else 244 #define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ 245 #define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ 246 #endif 247 /** 248 * @} 249 */ 250 251 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose 252 * @{ 253 */ 254 255 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE 256 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE 257 258 /** 259 * @} 260 */ 261 262 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose 263 * @{ 264 */ 265 266 #define DAC1_CHANNEL_1 DAC_CHANNEL_1 267 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 268 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 269 #define DAC_WAVE_NONE 0x00000000U 270 #define DAC_WAVE_NOISE DAC_CR_WAVE1_0 271 #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 272 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE 273 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE 274 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE 275 276 #if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) 277 #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL 278 #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL 279 #endif 280 281 #if defined(STM32U5) 282 #define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 283 #define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 284 #define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 285 #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 286 #endif 287 288 #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) 289 #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID 290 #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID 291 #endif 292 293 /** 294 * @} 295 */ 296 297 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose 298 * @{ 299 */ 300 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 301 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 302 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 303 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 304 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 305 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 306 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 307 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 308 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 309 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 310 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 311 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 312 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 313 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 314 315 #define IS_HAL_REMAPDMA IS_DMA_REMAP 316 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE 317 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE 318 319 #if defined(STM32L4) 320 321 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 322 #define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 323 #define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 324 #define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 325 #define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 326 #define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 327 #define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 328 #define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 329 #define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 330 #define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 331 #define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 332 #define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 333 #define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 334 #define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 335 #define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 336 #define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 337 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 338 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 339 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 340 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 341 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 342 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 343 #define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE 344 #define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT 345 #define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 346 #define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT 347 348 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 349 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 350 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 351 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 352 353 #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 354 #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI 355 #endif 356 357 #endif /* STM32L4 */ 358 359 #if defined(STM32G0) 360 #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 361 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 362 #define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM 363 #define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM 364 365 #define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM 366 #define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM 367 #endif 368 369 #if defined(STM32H7) 370 371 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 372 #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 373 374 #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX 375 #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX 376 377 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 378 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 379 #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 380 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 381 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 382 #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 383 #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 384 #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 385 386 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 387 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 388 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 389 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 390 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 391 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 392 #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 393 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 394 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 395 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 396 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 397 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 398 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 399 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 400 #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 401 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 402 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 403 #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT 404 #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT 405 #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP 406 #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 407 #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 408 #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 409 #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT 410 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 411 #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 412 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT 413 #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 414 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 415 #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 416 417 #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT 418 #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING 419 #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING 420 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING 421 422 #define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT 423 #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT 424 #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT 425 426 #define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT 427 #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT 428 429 #endif /* STM32H7 */ 430 431 #if defined(STM32U5) 432 #define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI 433 #endif /* STM32U5 */ 434 /** 435 * @} 436 */ 437 438 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose 439 * @{ 440 */ 441 442 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE 443 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD 444 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD 445 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD 446 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS 447 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES 448 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES 449 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE 450 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE 451 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE 452 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE 453 #define OBEX_PCROP OPTIONBYTE_PCROP 454 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG 455 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE 456 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE 457 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE 458 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD 459 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD 460 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE 461 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD 462 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD 463 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE 464 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD 465 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD 466 #define PAGESIZE FLASH_PAGE_SIZE 467 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE 468 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD 469 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD 470 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 471 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 472 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 473 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 474 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST 475 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST 476 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA 477 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB 478 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA 479 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB 480 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE 481 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN 482 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE 483 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN 484 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE 485 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD 486 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG 487 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS 488 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP 489 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV 490 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR 491 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG 492 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION 493 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA 494 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE 495 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE 496 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS 497 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS 498 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST 499 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR 500 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO 501 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION 502 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS 503 #define OB_WDG_SW OB_IWDG_SW 504 #define OB_WDG_HW OB_IWDG_HW 505 #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET 506 #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET 507 #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET 508 #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET 509 #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR 510 #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 511 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 512 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 513 #if defined(STM32G0) || defined(STM32C0) 514 #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE 515 #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH 516 #else 517 #define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE 518 #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE 519 #endif 520 #if defined(STM32H7) 521 #define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 522 #define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 523 #define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 524 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 525 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 526 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 527 #define FLASH_FLAG_WDW FLASH_FLAG_WBNE 528 #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL 529 #endif /* STM32H7 */ 530 #if defined(STM32U5) 531 #define OB_USER_nRST_STOP OB_USER_NRST_STOP 532 #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY 533 #define OB_USER_nRST_SHDW OB_USER_NRST_SHDW 534 #define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 535 #define OB_USER_nBOOT0 OB_USER_NBOOT0 536 #define OB_nBOOT0_RESET OB_NBOOT0_RESET 537 #define OB_nBOOT0_SET OB_NBOOT0_SET 538 #define OB_USER_SRAM134_RST OB_USER_SRAM_RST 539 #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE 540 #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE 541 #endif /* STM32U5 */ 542 543 /** 544 * @} 545 */ 546 547 /** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose 548 * @{ 549 */ 550 551 #if defined(STM32H7) 552 #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE 553 #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE 554 #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET 555 #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET 556 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE 557 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE 558 #endif /* STM32H7 */ 559 560 /** 561 * @} 562 */ 563 564 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose 565 * @{ 566 */ 567 568 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 569 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 570 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 571 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 572 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 573 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 574 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 575 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 576 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 577 #if defined(STM32G4) 578 579 #define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster 580 #define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster 581 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD 582 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD 583 #endif /* STM32G4 */ 584 585 /** 586 * @} 587 */ 588 589 590 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose 591 * @{ 592 */ 593 #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) 594 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE 595 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE 596 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 597 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 598 #elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) 599 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE 600 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE 601 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 602 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 603 #endif 604 /** 605 * @} 606 */ 607 608 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose 609 * @{ 610 */ 611 612 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef 613 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef 614 /** 615 * @} 616 */ 617 618 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose 619 * @{ 620 */ 621 #define GET_GPIO_SOURCE GPIO_GET_INDEX 622 #define GET_GPIO_INDEX GPIO_GET_INDEX 623 624 #if defined(STM32F4) 625 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO 626 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO 627 #endif 628 629 #if defined(STM32F7) 630 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 631 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 632 #endif 633 634 #if defined(STM32L4) 635 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 636 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 637 #endif 638 639 #if defined(STM32H7) 640 #define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 641 #define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 642 #define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 643 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 644 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 645 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 646 647 #if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ 648 defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) 649 #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS 650 #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS 651 #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS 652 #endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ 653 #endif /* STM32H7 */ 654 655 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 656 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 657 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 658 659 #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) 660 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 661 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 662 #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH 663 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 664 #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ 665 666 #if defined(STM32L1) 667 #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW 668 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM 669 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH 670 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH 671 #endif /* STM32L1 */ 672 673 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) 674 #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW 675 #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM 676 #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH 677 #endif /* STM32F0 || STM32F3 || STM32F1 */ 678 679 #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 680 681 #if defined(STM32U5) 682 #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ 683 #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP 684 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 685 #endif /* STM32U5 */ 686 /** 687 * @} 688 */ 689 690 /** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose 691 * @{ 692 */ 693 #if defined(STM32U5) 694 #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI 695 #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB 696 #endif /* STM32U5 */ 697 698 /** 699 * @} 700 */ 701 702 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose 703 * @{ 704 */ 705 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED 706 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 707 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 708 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 709 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 710 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 711 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 712 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 713 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 714 715 #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER 716 #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER 717 #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD 718 #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD 719 #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER 720 #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER 721 #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE 722 #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE 723 724 #if defined(STM32G4) 725 #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig 726 #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable 727 #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable 728 #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset 729 #define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A 730 #define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B 731 #define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL 732 #define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL 733 #endif /* STM32G4 */ 734 735 #if defined(STM32H7) 736 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 737 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 738 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 739 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 740 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 741 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 742 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 743 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 744 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 745 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 746 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 747 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 748 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 749 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 750 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 751 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 752 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 753 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 754 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 755 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 756 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 757 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 758 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 759 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 760 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 761 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 762 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 763 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 764 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 765 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 766 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 767 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 768 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 769 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 770 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 771 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 772 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 773 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 774 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 775 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 776 #define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 777 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 778 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 779 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 780 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 781 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 782 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 783 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 784 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 785 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 786 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 787 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 788 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 789 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 790 791 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 792 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 793 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 794 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 795 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 796 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 797 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 798 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 799 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 800 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 801 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 802 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 803 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 804 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 805 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 806 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 807 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 808 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 809 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 810 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 811 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 812 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 813 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 814 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 815 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 816 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 817 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 818 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 819 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 820 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 821 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 822 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 823 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 824 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 825 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 826 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 827 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 828 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 829 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 830 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 831 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 832 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 833 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 834 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 835 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 836 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 837 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 838 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 839 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 840 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 841 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 842 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 843 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 844 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 845 #endif /* STM32H7 */ 846 847 #if defined(STM32F3) 848 /** @brief Constants defining available sources associated to external events. 849 */ 850 #define HRTIM_EVENTSRC_1 (0x00000000U) 851 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) 852 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) 853 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) 854 855 /** @brief Constants defining the DLL calibration periods (in micro seconds) 856 */ 857 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U 858 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) 859 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) 860 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) 861 862 #endif /* STM32F3 */ 863 /** 864 * @} 865 */ 866 867 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose 868 * @{ 869 */ 870 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE 871 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE 872 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE 873 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE 874 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE 875 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE 876 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE 877 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE 878 #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) 879 #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX 880 #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX 881 #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX 882 #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX 883 #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX 884 #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX 885 #endif 886 /** 887 * @} 888 */ 889 890 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose 891 * @{ 892 */ 893 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE 894 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE 895 896 /** 897 * @} 898 */ 899 900 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose 901 * @{ 902 */ 903 #define KR_KEY_RELOAD IWDG_KEY_RELOAD 904 #define KR_KEY_ENABLE IWDG_KEY_ENABLE 905 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE 906 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE 907 /** 908 * @} 909 */ 910 911 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 912 * @{ 913 */ 914 915 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 916 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS 917 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS 918 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS 919 920 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING 921 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING 922 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING 923 924 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 925 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS 926 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS 927 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS 928 929 /* The following 3 definition have also been present in a temporary version of lptim.h */ 930 /* They need to be renamed also to the right name, just in case */ 931 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS 932 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS 933 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS 934 935 936 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose 937 * @{ 938 */ 939 #define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue 940 /** 941 * @} 942 */ 943 944 #if defined(STM32U5) 945 #define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF 946 #define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF 947 #define LPTIM_CHANNEL_ALL 0x00000000U 948 #endif /* STM32U5 */ 949 /** 950 * @} 951 */ 952 953 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose 954 * @{ 955 */ 956 #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b 957 #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b 958 #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b 959 #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b 960 961 #define NAND_AddressTypedef NAND_AddressTypeDef 962 963 #define __ARRAY_ADDRESS ARRAY_ADDRESS 964 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE 965 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE 966 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE 967 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE 968 /** 969 * @} 970 */ 971 972 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose 973 * @{ 974 */ 975 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef 976 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS 977 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING 978 #define NOR_ERROR HAL_NOR_STATUS_ERROR 979 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT 980 981 #define __NOR_WRITE NOR_WRITE 982 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT 983 /** 984 * @} 985 */ 986 987 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose 988 * @{ 989 */ 990 991 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 992 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 993 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 994 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 995 996 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 997 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 998 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 999 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 1000 1001 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1002 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1003 1004 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 1005 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 1006 1007 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 1008 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 1009 1010 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 1011 1012 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO 1013 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 1014 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 1015 1016 #if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) 1017 #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID 1018 #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID 1019 #endif 1020 1021 #if defined(STM32L4) || defined(STM32L5) 1022 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER 1023 #elif defined(STM32G4) 1024 #define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED 1025 #endif 1026 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose 1032 * @{ 1033 */ 1034 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS 1035 1036 #if defined(STM32H7) 1037 #define I2S_IT_TXE I2S_IT_TXP 1038 #define I2S_IT_RXNE I2S_IT_RXP 1039 1040 #define I2S_FLAG_TXE I2S_FLAG_TXP 1041 #define I2S_FLAG_RXNE I2S_FLAG_RXP 1042 #endif 1043 1044 #if defined(STM32F7) 1045 #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL 1046 #endif 1047 /** 1048 * @} 1049 */ 1050 1051 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose 1052 * @{ 1053 */ 1054 1055 /* Compact Flash-ATA registers description */ 1056 #define CF_DATA ATA_DATA 1057 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT 1058 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER 1059 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW 1060 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH 1061 #define CF_CARD_HEAD ATA_CARD_HEAD 1062 #define CF_STATUS_CMD ATA_STATUS_CMD 1063 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE 1064 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA 1065 1066 /* Compact Flash-ATA commands */ 1067 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD 1068 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD 1069 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD 1070 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD 1071 1072 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef 1073 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS 1074 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING 1075 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR 1076 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT 1077 /** 1078 * @} 1079 */ 1080 1081 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose 1082 * @{ 1083 */ 1084 1085 #define FORMAT_BIN RTC_FORMAT_BIN 1086 #define FORMAT_BCD RTC_FORMAT_BCD 1087 1088 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE 1089 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE 1090 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1091 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1092 1093 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE 1094 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE 1095 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE 1096 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1097 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT 1098 1099 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT 1100 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 1101 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 1102 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 1103 1104 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE 1105 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 1106 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 1107 1108 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT 1109 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 1110 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 1111 1112 #if defined(STM32F7) 1113 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK 1114 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK 1115 #endif /* STM32F7 */ 1116 1117 #if defined(STM32H7) 1118 #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X 1119 #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT 1120 #endif /* STM32H7 */ 1121 1122 #if defined(STM32F7) || defined(STM32H7) 1123 #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 1124 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 1125 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 1126 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP 1127 #endif /* STM32F7 || STM32H7 */ 1128 1129 /** 1130 * @} 1131 */ 1132 1133 1134 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose 1135 * @{ 1136 */ 1137 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE 1138 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE 1139 1140 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1141 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1142 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE 1143 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE 1144 1145 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE 1146 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE 1147 1148 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE 1149 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE 1150 /** 1151 * @} 1152 */ 1153 1154 1155 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose 1156 * @{ 1157 */ 1158 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE 1159 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE 1160 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE 1161 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE 1162 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE 1163 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE 1164 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE 1165 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE 1166 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE 1167 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE 1168 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN 1169 /** 1170 * @} 1171 */ 1172 1173 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose 1174 * @{ 1175 */ 1176 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE 1177 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE 1178 1179 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE 1180 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE 1181 1182 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE 1183 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE 1184 1185 #if defined(STM32H7) 1186 1187 #define SPI_FLAG_TXE SPI_FLAG_TXP 1188 #define SPI_FLAG_RXNE SPI_FLAG_RXP 1189 1190 #define SPI_IT_TXE SPI_IT_TXP 1191 #define SPI_IT_RXNE SPI_IT_RXP 1192 1193 #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET 1194 #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET 1195 #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET 1196 #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET 1197 1198 #endif /* STM32H7 */ 1199 1200 /** 1201 * @} 1202 */ 1203 1204 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose 1205 * @{ 1206 */ 1207 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK 1208 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK 1209 1210 #define TIM_DMABase_CR1 TIM_DMABASE_CR1 1211 #define TIM_DMABase_CR2 TIM_DMABASE_CR2 1212 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR 1213 #define TIM_DMABase_DIER TIM_DMABASE_DIER 1214 #define TIM_DMABase_SR TIM_DMABASE_SR 1215 #define TIM_DMABase_EGR TIM_DMABASE_EGR 1216 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 1217 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 1218 #define TIM_DMABase_CCER TIM_DMABASE_CCER 1219 #define TIM_DMABase_CNT TIM_DMABASE_CNT 1220 #define TIM_DMABase_PSC TIM_DMABASE_PSC 1221 #define TIM_DMABase_ARR TIM_DMABASE_ARR 1222 #define TIM_DMABase_RCR TIM_DMABASE_RCR 1223 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 1224 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 1225 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 1226 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 1227 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR 1228 #define TIM_DMABase_DCR TIM_DMABASE_DCR 1229 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR 1230 #define TIM_DMABase_OR1 TIM_DMABASE_OR1 1231 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 1232 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 1233 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 1234 #define TIM_DMABase_OR2 TIM_DMABASE_OR2 1235 #define TIM_DMABase_OR3 TIM_DMABASE_OR3 1236 #define TIM_DMABase_OR TIM_DMABASE_OR 1237 1238 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE 1239 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 1240 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 1241 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 1242 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 1243 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM 1244 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER 1245 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK 1246 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 1247 1248 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER 1249 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS 1250 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS 1251 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS 1252 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS 1253 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS 1254 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS 1255 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS 1256 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS 1257 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS 1258 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS 1259 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS 1260 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS 1261 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS 1262 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS 1263 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS 1264 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS 1265 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS 1266 1267 #if defined(STM32L0) 1268 #define TIM22_TI1_GPIO1 TIM22_TI1_GPIO 1269 #define TIM22_TI1_GPIO2 TIM22_TI1_GPIO 1270 #endif 1271 1272 #if defined(STM32F3) 1273 #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE 1274 #endif 1275 1276 #if defined(STM32H7) 1277 #define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 1278 #define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 1279 #define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 1280 #define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 1281 #define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 1282 #define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 1283 #define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 1284 #define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 1285 #define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 1286 #define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 1287 #define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 1288 #define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 1289 #define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 1290 #define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 1291 #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 1292 #endif 1293 1294 #if defined(STM32U5) || defined(STM32MP2) 1295 #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS 1296 #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK 1297 #endif 1298 /** 1299 * @} 1300 */ 1301 1302 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose 1303 * @{ 1304 */ 1305 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING 1306 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING 1307 /** 1308 * @} 1309 */ 1310 1311 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose 1312 * @{ 1313 */ 1314 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1315 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1316 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE 1317 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE 1318 1319 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE 1320 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE 1321 1322 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16 1323 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 1324 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 1325 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 1326 1327 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8 1328 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 1329 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 1330 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 1331 1332 #define __DIV_LPUART UART_DIV_LPUART 1333 1334 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE 1335 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK 1336 1337 /** 1338 * @} 1339 */ 1340 1341 1342 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose 1343 * @{ 1344 */ 1345 1346 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE 1347 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE 1348 1349 #define USARTNACK_ENABLED USART_NACK_ENABLE 1350 #define USARTNACK_DISABLED USART_NACK_DISABLE 1351 /** 1352 * @} 1353 */ 1354 1355 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose 1356 * @{ 1357 */ 1358 #define CFR_BASE WWDG_CFR_BASE 1359 1360 /** 1361 * @} 1362 */ 1363 1364 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose 1365 * @{ 1366 */ 1367 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0 1368 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1 1369 #define CAN_IT_RQCP0 CAN_IT_TME 1370 #define CAN_IT_RQCP1 CAN_IT_TME 1371 #define CAN_IT_RQCP2 CAN_IT_TME 1372 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE 1373 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE 1374 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) 1375 #define CAN_TXSTATUS_OK ((uint8_t)0x01U) 1376 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) 1377 1378 /** 1379 * @} 1380 */ 1381 1382 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose 1383 * @{ 1384 */ 1385 1386 #define VLAN_TAG ETH_VLAN_TAG 1387 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD 1388 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD 1389 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD 1390 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK 1391 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK 1392 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK 1393 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK 1394 1395 #define ETH_MMCCR 0x00000100U 1396 #define ETH_MMCRIR 0x00000104U 1397 #define ETH_MMCTIR 0x00000108U 1398 #define ETH_MMCRIMR 0x0000010CU 1399 #define ETH_MMCTIMR 0x00000110U 1400 #define ETH_MMCTGFSCCR 0x0000014CU 1401 #define ETH_MMCTGFMSCCR 0x00000150U 1402 #define ETH_MMCTGFCR 0x00000168U 1403 #define ETH_MMCRFCECR 0x00000194U 1404 #define ETH_MMCRFAECR 0x00000198U 1405 #define ETH_MMCRGUFCR 0x000001C4U 1406 1407 #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ 1408 #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ 1409 #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ 1410 #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ 1411 #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ 1412 #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ 1413 #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ 1414 #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ 1415 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ 1416 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ 1417 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ 1418 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ 1419 #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ 1420 #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ 1421 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ 1422 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ 1423 #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ 1424 #if defined(STM32F1) 1425 #else 1426 #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ 1427 #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ 1428 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ 1429 #endif 1430 #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ 1431 #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ 1432 #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ 1433 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ 1434 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ 1435 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ 1436 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ 1437 1438 /** 1439 * @} 1440 */ 1441 1442 /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose 1443 * @{ 1444 */ 1445 #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR 1446 #define DCMI_IT_OVF DCMI_IT_OVR 1447 #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI 1448 #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI 1449 1450 #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop 1451 #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop 1452 #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop 1453 1454 /** 1455 * @} 1456 */ 1457 1458 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1459 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1460 || defined(STM32H7) 1461 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose 1462 * @{ 1463 */ 1464 #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 1465 #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 1466 #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 1467 #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 1468 #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 1469 1470 #define CM_ARGB8888 DMA2D_INPUT_ARGB8888 1471 #define CM_RGB888 DMA2D_INPUT_RGB888 1472 #define CM_RGB565 DMA2D_INPUT_RGB565 1473 #define CM_ARGB1555 DMA2D_INPUT_ARGB1555 1474 #define CM_ARGB4444 DMA2D_INPUT_ARGB4444 1475 #define CM_L8 DMA2D_INPUT_L8 1476 #define CM_AL44 DMA2D_INPUT_AL44 1477 #define CM_AL88 DMA2D_INPUT_AL88 1478 #define CM_L4 DMA2D_INPUT_L4 1479 #define CM_A8 DMA2D_INPUT_A8 1480 #define CM_A4 DMA2D_INPUT_A4 1481 /** 1482 * @} 1483 */ 1484 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ 1485 1486 #if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ 1487 || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ 1488 || defined(STM32H7) || defined(STM32U5) 1489 /** @defgroup DMA2D_Aliases DMA2D API Aliases 1490 * @{ 1491 */ 1492 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 1493 for compatibility with legacy code */ 1494 /** 1495 * @} 1496 */ 1497 1498 #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ 1499 1500 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose 1501 * @{ 1502 */ 1503 1504 /** 1505 * @} 1506 */ 1507 1508 /* Exported functions --------------------------------------------------------*/ 1509 1510 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose 1511 * @{ 1512 */ 1513 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback 1514 /** 1515 * @} 1516 */ 1517 1518 /** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose 1519 * @{ 1520 */ 1521 1522 #if defined(STM32U5) 1523 #define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr 1524 #define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT 1525 #endif /* STM32U5 */ 1526 1527 /** 1528 * @} 1529 */ 1530 1531 #if !defined(STM32F2) 1532 /** @defgroup HASH_alias HASH API alias 1533 * @{ 1534 */ 1535 #define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ 1536 /** 1537 * 1538 * @} 1539 */ 1540 #endif /* STM32F2 */ 1541 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose 1542 * @{ 1543 */ 1544 #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef 1545 #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef 1546 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish 1547 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish 1548 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish 1549 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish 1550 1551 /*HASH Algorithm Selection*/ 1552 1553 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 1554 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 1555 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 1556 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 1557 1558 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH 1559 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC 1560 1561 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY 1562 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY 1563 1564 #if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) 1565 1566 #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt 1567 #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End 1568 #define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT 1569 #define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT 1570 1571 #define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt 1572 #define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End 1573 #define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT 1574 #define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT 1575 1576 #define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt 1577 #define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End 1578 #define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT 1579 #define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT 1580 1581 #define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt 1582 #define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End 1583 #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT 1584 #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT 1585 1586 #endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ 1587 /** 1588 * @} 1589 */ 1590 1591 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose 1592 * @{ 1593 */ 1594 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode 1595 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode 1596 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode 1597 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode 1598 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode 1599 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode 1600 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ 1601 )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) 1602 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect 1603 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) 1604 #if defined(STM32L0) 1605 #else 1606 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) 1607 #endif 1608 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) 1609 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ 1610 )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) 1611 #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) 1612 #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode 1613 #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode 1614 #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode 1615 #define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode 1616 #endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ 1617 1618 /** 1619 * @} 1620 */ 1621 1622 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose 1623 * @{ 1624 */ 1625 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram 1626 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown 1627 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown 1628 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock 1629 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock 1630 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase 1631 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program 1632 1633 /** 1634 * @} 1635 */ 1636 1637 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose 1638 * @{ 1639 */ 1640 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter 1641 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter 1642 #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter 1643 #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter 1644 1645 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ 1646 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) 1647 1648 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) 1649 #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT 1650 #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT 1651 #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT 1652 #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT 1653 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1654 #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) 1655 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA 1656 #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA 1657 #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA 1658 #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA 1659 #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ 1660 1661 #if defined(STM32F4) 1662 #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT 1663 #define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT 1664 #define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT 1665 #define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT 1666 #define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA 1667 #define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA 1668 #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA 1669 #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA 1670 #endif /* STM32F4 */ 1671 /** 1672 * @} 1673 */ 1674 1675 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose 1676 * @{ 1677 */ 1678 1679 #if defined(STM32G0) 1680 #define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD 1681 #define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD 1682 #define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD 1683 #define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler 1684 #endif 1685 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD 1686 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg 1687 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown 1688 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor 1689 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg 1690 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown 1691 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor 1692 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler 1693 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD 1694 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler 1695 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback 1696 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive 1697 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive 1698 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC 1699 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC 1700 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM 1701 1702 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL 1703 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING 1704 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING 1705 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING 1706 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING 1707 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING 1708 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING 1709 1710 #define CR_OFFSET_BB PWR_CR_OFFSET_BB 1711 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB 1712 #define PMODE_BIT_NUMBER VOS_BIT_NUMBER 1713 #define CR_PMODE_BB CR_VOS_BB 1714 1715 #define DBP_BitNumber DBP_BIT_NUMBER 1716 #define PVDE_BitNumber PVDE_BIT_NUMBER 1717 #define PMODE_BitNumber PMODE_BIT_NUMBER 1718 #define EWUP_BitNumber EWUP_BIT_NUMBER 1719 #define FPDS_BitNumber FPDS_BIT_NUMBER 1720 #define ODEN_BitNumber ODEN_BIT_NUMBER 1721 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER 1722 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER 1723 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER 1724 #define BRE_BitNumber BRE_BIT_NUMBER 1725 1726 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL 1727 1728 #if defined (STM32U5) 1729 #define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP 1730 #define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP 1731 #define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP 1732 #define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP 1733 #define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP 1734 #define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP 1735 #define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP 1736 #define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP 1737 #define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP 1738 #define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP 1739 #define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP 1740 #define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP 1741 #define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP 1742 1743 #define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP 1744 #define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP 1745 #define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP 1746 1747 #define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP 1748 #define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP 1749 #define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP 1750 #define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP 1751 #define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP 1752 #define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP 1753 #define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP 1754 #define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP 1755 #define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP 1756 #define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP 1757 #define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP 1758 #define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP 1759 #define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP 1760 #define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP 1761 1762 #define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP 1763 1764 #define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP 1765 #define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP 1766 #define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP 1767 #define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP 1768 #define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP 1769 #define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP 1770 #define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP 1771 #define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP 1772 #define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP 1773 #define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP 1774 #define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP 1775 #define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP 1776 #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP 1777 #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP 1778 1779 #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP 1780 #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP 1781 #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP 1782 #define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP 1783 #define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP 1784 #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP 1785 #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP 1786 #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP 1787 1788 #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY 1789 #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY 1790 #define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY 1791 1792 #define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN 1793 #define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN 1794 #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN 1795 #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN 1796 #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN 1797 1798 #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK 1799 #endif 1800 1801 /** 1802 * @} 1803 */ 1804 1805 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose 1806 * @{ 1807 */ 1808 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT 1809 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback 1810 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback 1811 /** 1812 * @} 1813 */ 1814 1815 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose 1816 * @{ 1817 */ 1818 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo 1819 /** 1820 * @} 1821 */ 1822 1823 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose 1824 * @{ 1825 */ 1826 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt 1827 #define HAL_TIM_DMAError TIM_DMAError 1828 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt 1829 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt 1830 #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) 1831 #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro 1832 #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT 1833 #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback 1834 #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent 1835 #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT 1836 #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA 1837 #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ 1838 /** 1839 * @} 1840 */ 1841 1842 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose 1843 * @{ 1844 */ 1845 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback 1846 /** 1847 * @} 1848 */ 1849 1850 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose 1851 * @{ 1852 */ 1853 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback 1854 #define HAL_LTDC_Relaod HAL_LTDC_Reload 1855 #define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig 1856 #define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig 1857 /** 1858 * @} 1859 */ 1860 1861 1862 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose 1863 * @{ 1864 */ 1865 1866 /** 1867 * @} 1868 */ 1869 1870 /* Exported macros ------------------------------------------------------------*/ 1871 1872 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose 1873 * @{ 1874 */ 1875 #define AES_IT_CC CRYP_IT_CC 1876 #define AES_IT_ERR CRYP_IT_ERR 1877 #define AES_FLAG_CCF CRYP_FLAG_CCF 1878 /** 1879 * @} 1880 */ 1881 1882 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 1883 * @{ 1884 */ 1885 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE 1886 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH 1887 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH 1888 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM 1889 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC 1890 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM 1891 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC 1892 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI 1893 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK 1894 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG 1895 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG 1896 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE 1897 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE 1898 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 1899 1900 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY 1901 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 1902 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS 1903 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER 1904 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER 1905 1906 /** 1907 * @} 1908 */ 1909 1910 1911 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose 1912 * @{ 1913 */ 1914 #define __ADC_ENABLE __HAL_ADC_ENABLE 1915 #define __ADC_DISABLE __HAL_ADC_DISABLE 1916 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS 1917 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS 1918 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE 1919 #define __ADC_IS_ENABLED ADC_IS_ENABLE 1920 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR 1921 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED 1922 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED 1923 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR 1924 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED 1925 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING 1926 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE 1927 1928 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION 1929 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK 1930 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT 1931 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR 1932 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION 1933 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE 1934 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS 1935 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS 1936 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM 1937 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT 1938 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS 1939 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN 1940 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ 1941 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET 1942 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET 1943 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL 1944 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL 1945 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET 1946 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET 1947 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD 1948 1949 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION 1950 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION 1951 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION 1952 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER 1953 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI 1954 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1955 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE 1956 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER 1957 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER 1958 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE 1959 1960 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT 1961 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT 1962 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL 1963 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM 1964 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET 1965 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE 1966 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE 1967 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER 1968 1969 #define __HAL_ADC_SQR1 ADC_SQR1 1970 #define __HAL_ADC_SMPR1 ADC_SMPR1 1971 #define __HAL_ADC_SMPR2 ADC_SMPR2 1972 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK 1973 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK 1974 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK 1975 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS 1976 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS 1977 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV 1978 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection 1979 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq 1980 #define __HAL_ADC_JSQR ADC_JSQR 1981 1982 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL 1983 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS 1984 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF 1985 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT 1986 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS 1987 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN 1988 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR 1989 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ 1990 1991 /** 1992 * @} 1993 */ 1994 1995 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 1996 * @{ 1997 */ 1998 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT 1999 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT 2000 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT 2001 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE 2002 2003 /** 2004 * @} 2005 */ 2006 2007 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose 2008 * @{ 2009 */ 2010 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 2011 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 2012 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 2013 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 2014 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 2015 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 2016 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 2017 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 2018 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 2019 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 2020 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 2021 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 2022 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 2023 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 2024 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 2025 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 2026 2027 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 2028 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 2029 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 2030 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 2031 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 2032 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 2033 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 2034 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 2035 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 2036 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 2037 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 2038 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 2039 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 2040 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 2041 2042 2043 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 2044 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 2045 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 2046 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 2047 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 2048 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 2049 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC 2050 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC 2051 #if defined(STM32H7) 2052 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 2053 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 2054 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 2055 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 2056 #else 2057 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG 2058 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG 2059 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG 2060 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG 2061 #endif /* STM32H7 */ 2062 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT 2063 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT 2064 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT 2065 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT 2066 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT 2067 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT 2068 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 2069 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 2070 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 2071 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 2072 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 2073 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 2074 2075 /** 2076 * @} 2077 */ 2078 2079 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose 2080 * @{ 2081 */ 2082 #if defined(STM32F3) 2083 #define COMP_START __HAL_COMP_ENABLE 2084 #define COMP_STOP __HAL_COMP_DISABLE 2085 #define COMP_LOCK __HAL_COMP_LOCK 2086 2087 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) 2088 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2089 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2090 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2091 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2092 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2093 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2094 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2095 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2096 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2097 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2098 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2099 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2100 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2101 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2102 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2103 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2104 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2105 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2106 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2107 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2108 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2109 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2110 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2111 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2112 # endif 2113 # if defined(STM32F302xE) || defined(STM32F302xC) 2114 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2115 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2116 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2117 __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) 2118 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2119 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2120 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2121 __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) 2122 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2123 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2124 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2125 __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) 2126 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2127 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2128 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2129 __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) 2130 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2131 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2132 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2133 __HAL_COMP_COMP6_EXTI_ENABLE_IT()) 2134 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2135 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2136 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2137 __HAL_COMP_COMP6_EXTI_DISABLE_IT()) 2138 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2139 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2140 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2141 __HAL_COMP_COMP6_EXTI_GET_FLAG()) 2142 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2143 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2144 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2145 __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) 2146 # endif 2147 # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) 2148 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2149 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ 2150 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ 2151 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ 2152 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ 2153 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ 2154 __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) 2155 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2156 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ 2157 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ 2158 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ 2159 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ 2160 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ 2161 __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) 2162 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2163 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ 2164 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ 2165 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ 2166 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ 2167 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ 2168 __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) 2169 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2170 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ 2171 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ 2172 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ 2173 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ 2174 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ 2175 __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) 2176 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2177 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ 2178 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ 2179 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ 2180 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ 2181 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ 2182 __HAL_COMP_COMP7_EXTI_ENABLE_IT()) 2183 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2184 ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ 2185 ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ 2186 ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ 2187 ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ 2188 ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ 2189 __HAL_COMP_COMP7_EXTI_DISABLE_IT()) 2190 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2191 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ 2192 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ 2193 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ 2194 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ 2195 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ 2196 __HAL_COMP_COMP7_EXTI_GET_FLAG()) 2197 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2198 ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ 2199 ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ 2200 ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ 2201 ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ 2202 ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ 2203 __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) 2204 # endif 2205 # if defined(STM32F373xC) ||defined(STM32F378xx) 2206 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2207 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2208 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2209 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2210 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2211 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2212 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2213 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2214 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2215 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2216 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2217 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2218 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2219 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2220 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2221 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2222 # endif 2223 #else 2224 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ 2225 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) 2226 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ 2227 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) 2228 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ 2229 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) 2230 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ 2231 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) 2232 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ 2233 __HAL_COMP_COMP2_EXTI_ENABLE_IT()) 2234 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ 2235 __HAL_COMP_COMP2_EXTI_DISABLE_IT()) 2236 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ 2237 __HAL_COMP_COMP2_EXTI_GET_FLAG()) 2238 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ 2239 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) 2240 #endif 2241 2242 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE 2243 2244 #if defined(STM32L0) || defined(STM32L4) 2245 /* Note: On these STM32 families, the only argument of this macro */ 2246 /* is COMP_FLAG_LOCK. */ 2247 /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ 2248 /* argument. */ 2249 #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) 2250 #endif 2251 /** 2252 * @} 2253 */ 2254 2255 #if defined(STM32L0) || defined(STM32L4) 2256 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose 2257 * @{ 2258 */ 2259 #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2260 #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ 2261 /** 2262 * @} 2263 */ 2264 #endif 2265 2266 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose 2267 * @{ 2268 */ 2269 2270 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ 2271 ((WAVE) == DAC_WAVE_NOISE)|| \ 2272 ((WAVE) == DAC_WAVE_TRIANGLE)) 2273 2274 /** 2275 * @} 2276 */ 2277 2278 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose 2279 * @{ 2280 */ 2281 2282 #define IS_WRPAREA IS_OB_WRPAREA 2283 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM 2284 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM 2285 #define IS_TYPEERASE IS_FLASH_TYPEERASE 2286 #define IS_NBSECTORS IS_FLASH_NBSECTORS 2287 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE 2288 2289 /** 2290 * @} 2291 */ 2292 2293 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose 2294 * @{ 2295 */ 2296 2297 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 2298 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START 2299 #if defined(STM32F1) 2300 #define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE 2301 #else 2302 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE 2303 #endif /* STM32F1 */ 2304 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME 2305 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD 2306 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST 2307 #define __HAL_I2C_SPEED I2C_SPEED 2308 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE 2309 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ 2310 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS 2311 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE 2312 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ 2313 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB 2314 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB 2315 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE 2316 /** 2317 * @} 2318 */ 2319 2320 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose 2321 * @{ 2322 */ 2323 2324 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE 2325 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT 2326 2327 #if defined(STM32H7) 2328 #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG 2329 #endif 2330 2331 /** 2332 * @} 2333 */ 2334 2335 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose 2336 * @{ 2337 */ 2338 2339 #define __IRDA_DISABLE __HAL_IRDA_DISABLE 2340 #define __IRDA_ENABLE __HAL_IRDA_ENABLE 2341 2342 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2343 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2344 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE 2345 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION 2346 2347 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE 2348 2349 2350 /** 2351 * @} 2352 */ 2353 2354 2355 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose 2356 * @{ 2357 */ 2358 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS 2359 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS 2360 /** 2361 * @} 2362 */ 2363 2364 2365 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose 2366 * @{ 2367 */ 2368 2369 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT 2370 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT 2371 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE 2372 2373 /** 2374 * @} 2375 */ 2376 2377 2378 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose 2379 * @{ 2380 */ 2381 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD 2382 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX 2383 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX 2384 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX 2385 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX 2386 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L 2387 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H 2388 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM 2389 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES 2390 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX 2391 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT 2392 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION 2393 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET 2394 2395 /** 2396 * @} 2397 */ 2398 2399 2400 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose 2401 * @{ 2402 */ 2403 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2404 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2405 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2406 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2407 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2408 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2409 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE 2410 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE 2411 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE 2412 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE 2413 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE 2414 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE 2415 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine 2416 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine 2417 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig 2418 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig 2419 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) 2420 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT 2421 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT 2422 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE 2423 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2424 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE 2425 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2426 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE 2427 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE 2428 #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) 2429 #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) 2430 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention 2431 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention 2432 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 2433 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 2434 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE 2435 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE 2436 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB 2437 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB 2438 2439 #if defined (STM32F4) 2440 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() 2441 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() 2442 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() 2443 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() 2444 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() 2445 #else 2446 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG 2447 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT 2448 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT 2449 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT 2450 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG 2451 #endif /* STM32F4 */ 2452 /** 2453 * @} 2454 */ 2455 2456 2457 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose 2458 * @{ 2459 */ 2460 2461 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI 2462 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI 2463 2464 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback 2465 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ 2466 )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) 2467 2468 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE 2469 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE 2470 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE 2471 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE 2472 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET 2473 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET 2474 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE 2475 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE 2476 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET 2477 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET 2478 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE 2479 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE 2480 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE 2481 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE 2482 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET 2483 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET 2484 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE 2485 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE 2486 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET 2487 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET 2488 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 2489 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 2490 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 2491 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 2492 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 2493 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 2494 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE 2495 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE 2496 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE 2497 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE 2498 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET 2499 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET 2500 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE 2501 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE 2502 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET 2503 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET 2504 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET 2505 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET 2506 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET 2507 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET 2508 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET 2509 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET 2510 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET 2511 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET 2512 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET 2513 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET 2514 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET 2515 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET 2516 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE 2517 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE 2518 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET 2519 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET 2520 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2521 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2522 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE 2523 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE 2524 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2525 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2526 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE 2527 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE 2528 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET 2529 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET 2530 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE 2531 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE 2532 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET 2533 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET 2534 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE 2535 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE 2536 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE 2537 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE 2538 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET 2539 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET 2540 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE 2541 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE 2542 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET 2543 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET 2544 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE 2545 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE 2546 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE 2547 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE 2548 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET 2549 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET 2550 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE 2551 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE 2552 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET 2553 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET 2554 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE 2555 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE 2556 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE 2557 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE 2558 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET 2559 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET 2560 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE 2561 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE 2562 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET 2563 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET 2564 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE 2565 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE 2566 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE 2567 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE 2568 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET 2569 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET 2570 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE 2571 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE 2572 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE 2573 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE 2574 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET 2575 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET 2576 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE 2577 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE 2578 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE 2579 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE 2580 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET 2581 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET 2582 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE 2583 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE 2584 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET 2585 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET 2586 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE 2587 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE 2588 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE 2589 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE 2590 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE 2591 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE 2592 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE 2593 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE 2594 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE 2595 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE 2596 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET 2597 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET 2598 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE 2599 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE 2600 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET 2601 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET 2602 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE 2603 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE 2604 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE 2605 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE 2606 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE 2607 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE 2608 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET 2609 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET 2610 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE 2611 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE 2612 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE 2613 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE 2614 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE 2615 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE 2616 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET 2617 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET 2618 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE 2619 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE 2620 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE 2621 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE 2622 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET 2623 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET 2624 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE 2625 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE 2626 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE 2627 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE 2628 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET 2629 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET 2630 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE 2631 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE 2632 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE 2633 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE 2634 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET 2635 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET 2636 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE 2637 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE 2638 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE 2639 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE 2640 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET 2641 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET 2642 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE 2643 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE 2644 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE 2645 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE 2646 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET 2647 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET 2648 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE 2649 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE 2650 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE 2651 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE 2652 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET 2653 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET 2654 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE 2655 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE 2656 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE 2657 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE 2658 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET 2659 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET 2660 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE 2661 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE 2662 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE 2663 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE 2664 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET 2665 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET 2666 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE 2667 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE 2668 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE 2669 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE 2670 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET 2671 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET 2672 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE 2673 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE 2674 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE 2675 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE 2676 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET 2677 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET 2678 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE 2679 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE 2680 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE 2681 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE 2682 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET 2683 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET 2684 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE 2685 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE 2686 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE 2687 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE 2688 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET 2689 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET 2690 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE 2691 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE 2692 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE 2693 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE 2694 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET 2695 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET 2696 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE 2697 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE 2698 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE 2699 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE 2700 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET 2701 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET 2702 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE 2703 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE 2704 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE 2705 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE 2706 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET 2707 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET 2708 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE 2709 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE 2710 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE 2711 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE 2712 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET 2713 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET 2714 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE 2715 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE 2716 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE 2717 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE 2718 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET 2719 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET 2720 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE 2721 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE 2722 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE 2723 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE 2724 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET 2725 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET 2726 2727 #if defined(STM32WB) 2728 #define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE 2729 #define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE 2730 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE 2731 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE 2732 #define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET 2733 #define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET 2734 #define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED 2735 #define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED 2736 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED 2737 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED 2738 #define QSPI_IRQHandler QUADSPI_IRQHandler 2739 #endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ 2740 2741 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE 2742 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE 2743 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE 2744 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE 2745 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET 2746 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET 2747 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE 2748 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE 2749 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE 2750 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE 2751 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET 2752 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET 2753 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE 2754 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE 2755 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE 2756 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE 2757 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET 2758 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET 2759 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 2760 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 2761 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE 2762 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE 2763 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE 2764 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE 2765 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET 2766 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET 2767 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE 2768 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE 2769 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE 2770 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE 2771 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET 2772 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET 2773 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE 2774 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE 2775 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE 2776 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE 2777 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET 2778 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET 2779 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE 2780 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE 2781 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE 2782 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE 2783 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET 2784 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET 2785 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE 2786 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE 2787 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE 2788 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE 2789 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE 2790 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE 2791 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE 2792 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE 2793 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE 2794 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE 2795 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET 2796 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET 2797 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE 2798 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE 2799 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE 2800 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE 2801 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET 2802 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET 2803 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE 2804 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE 2805 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE 2806 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE 2807 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET 2808 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET 2809 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE 2810 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE 2811 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET 2812 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET 2813 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE 2814 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE 2815 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET 2816 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET 2817 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE 2818 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE 2819 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET 2820 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET 2821 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE 2822 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE 2823 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET 2824 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET 2825 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE 2826 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE 2827 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET 2828 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET 2829 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE 2830 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE 2831 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE 2832 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE 2833 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET 2834 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET 2835 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE 2836 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE 2837 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE 2838 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE 2839 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET 2840 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET 2841 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE 2842 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE 2843 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE 2844 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE 2845 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET 2846 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET 2847 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE 2848 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE 2849 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE 2850 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE 2851 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET 2852 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET 2853 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE 2854 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE 2855 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE 2856 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE 2857 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET 2858 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET 2859 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE 2860 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE 2861 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE 2862 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE 2863 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET 2864 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET 2865 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE 2866 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE 2867 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE 2868 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE 2869 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET 2870 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET 2871 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE 2872 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE 2873 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE 2874 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE 2875 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET 2876 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET 2877 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE 2878 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE 2879 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE 2880 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE 2881 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET 2882 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET 2883 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE 2884 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE 2885 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE 2886 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE 2887 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET 2888 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET 2889 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE 2890 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE 2891 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET 2892 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET 2893 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE 2894 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE 2895 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE 2896 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE 2897 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET 2898 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET 2899 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2900 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2901 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2902 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2903 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2904 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2905 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2906 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2907 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2908 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2909 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2910 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2911 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE 2912 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE 2913 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE 2914 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE 2915 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET 2916 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET 2917 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE 2918 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE 2919 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE 2920 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE 2921 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET 2922 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET 2923 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE 2924 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE 2925 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE 2926 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE 2927 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET 2928 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET 2929 #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE 2930 #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE 2931 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE 2932 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE 2933 #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET 2934 #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET 2935 #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE 2936 #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE 2937 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE 2938 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE 2939 #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET 2940 #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET 2941 #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 2942 #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 2943 #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 2944 #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 2945 #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 2946 #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 2947 #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 2948 #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 2949 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE 2950 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE 2951 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET 2952 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE 2953 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE 2954 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE 2955 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE 2956 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET 2957 2958 #if defined(STM32H7) 2959 #define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE 2960 #define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE 2961 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE 2962 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE 2963 2964 #define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ 2965 #define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ 2966 2967 2968 #define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED 2969 #define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED 2970 #define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 2971 #define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 2972 #define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 2973 #define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 2974 #define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 2975 #endif 2976 2977 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE 2978 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE 2979 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE 2980 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE 2981 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET 2982 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET 2983 2984 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE 2985 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE 2986 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET 2987 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET 2988 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE 2989 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE 2990 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE 2991 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE 2992 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET 2993 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET 2994 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE 2995 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE 2996 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE 2997 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE 2998 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE 2999 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE 3000 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET 3001 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET 3002 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE 3003 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE 3004 3005 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3006 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3007 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE 3008 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE 3009 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE 3010 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE 3011 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE 3012 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE 3013 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE 3014 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE 3015 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE 3016 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE 3017 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE 3018 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE 3019 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE 3020 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE 3021 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE 3022 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE 3023 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE 3024 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET 3025 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET 3026 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE 3027 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE 3028 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE 3029 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE 3030 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE 3031 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET 3032 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET 3033 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE 3034 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE 3035 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE 3036 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE 3037 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET 3038 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET 3039 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE 3040 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE 3041 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE 3042 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE 3043 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET 3044 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET 3045 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE 3046 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE 3047 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE 3048 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE 3049 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE 3050 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE 3051 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE 3052 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE 3053 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE 3054 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE 3055 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE 3056 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE 3057 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE 3058 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE 3059 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE 3060 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE 3061 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE 3062 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE 3063 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE 3064 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE 3065 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE 3066 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET 3067 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET 3068 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE 3069 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE 3070 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE 3071 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE 3072 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET 3073 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET 3074 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE 3075 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE 3076 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE 3077 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE 3078 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET 3079 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET 3080 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE 3081 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE 3082 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE 3083 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE 3084 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET 3085 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET 3086 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE 3087 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE 3088 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE 3089 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE 3090 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET 3091 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE 3092 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE 3093 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE 3094 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE 3095 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE 3096 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE 3097 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET 3098 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET 3099 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE 3100 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE 3101 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE 3102 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE 3103 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET 3104 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET 3105 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE 3106 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE 3107 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE 3108 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE 3109 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET 3110 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET 3111 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE 3112 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE 3113 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3114 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3115 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3116 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3117 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3118 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3119 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE 3120 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE 3121 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED 3122 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED 3123 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET 3124 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET 3125 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE 3126 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 3127 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED 3128 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED 3129 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE 3130 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE 3131 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE 3132 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE 3133 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE 3134 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE 3135 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE 3136 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE 3137 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE 3138 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET 3139 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET 3140 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE 3141 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE 3142 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3143 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3144 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3145 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3146 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE 3147 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE 3148 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET 3149 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET 3150 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE 3151 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE 3152 3153 /* alias define maintained for legacy */ 3154 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET 3155 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET 3156 3157 #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3158 #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3159 #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE 3160 #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE 3161 #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE 3162 #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE 3163 #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE 3164 #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE 3165 #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE 3166 #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE 3167 #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE 3168 #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE 3169 #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE 3170 #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE 3171 #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE 3172 #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE 3173 #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE 3174 #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE 3175 #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE 3176 #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE 3177 3178 #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3179 #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3180 #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET 3181 #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET 3182 #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET 3183 #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET 3184 #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET 3185 #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET 3186 #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET 3187 #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET 3188 #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET 3189 #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET 3190 #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET 3191 #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET 3192 #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET 3193 #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET 3194 #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET 3195 #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET 3196 #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET 3197 #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET 3198 3199 #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED 3200 #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED 3201 #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3202 #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3203 #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED 3204 #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED 3205 #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED 3206 #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED 3207 #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED 3208 #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED 3209 #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED 3210 #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED 3211 #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED 3212 #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED 3213 #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED 3214 #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED 3215 #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED 3216 #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED 3217 #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED 3218 #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED 3219 #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED 3220 #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED 3221 #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED 3222 #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED 3223 #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED 3224 #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED 3225 #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED 3226 #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED 3227 #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED 3228 #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED 3229 #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED 3230 #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED 3231 #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED 3232 #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED 3233 #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED 3234 #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED 3235 #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED 3236 #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED 3237 #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED 3238 #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED 3239 #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED 3240 #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED 3241 #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED 3242 #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED 3243 #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED 3244 #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED 3245 #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED 3246 #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED 3247 #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED 3248 #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED 3249 #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED 3250 #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED 3251 #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED 3252 #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED 3253 #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED 3254 #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED 3255 #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED 3256 #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED 3257 #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED 3258 #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED 3259 #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED 3260 #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED 3261 #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED 3262 #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED 3263 #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED 3264 #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED 3265 #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED 3266 #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED 3267 #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED 3268 #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED 3269 #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED 3270 #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED 3271 #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED 3272 #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED 3273 #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED 3274 #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED 3275 #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED 3276 #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED 3277 #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED 3278 #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED 3279 #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED 3280 #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED 3281 #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED 3282 #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED 3283 #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED 3284 #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED 3285 #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED 3286 #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED 3287 #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED 3288 #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED 3289 #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED 3290 #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED 3291 #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED 3292 #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED 3293 #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED 3294 #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED 3295 #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED 3296 #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED 3297 #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED 3298 #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED 3299 #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED 3300 #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED 3301 #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED 3302 #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED 3303 #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED 3304 #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED 3305 #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED 3306 #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED 3307 #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED 3308 #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED 3309 #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED 3310 #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED 3311 #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED 3312 #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED 3313 #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED 3314 #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED 3315 3316 #if defined(STM32L1) 3317 #define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE 3318 #define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE 3319 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE 3320 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE 3321 #define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET 3322 #define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET 3323 #endif /* STM32L1 */ 3324 3325 #if defined(STM32F4) 3326 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET 3327 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET 3328 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE 3329 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE 3330 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE 3331 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE 3332 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED 3333 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED 3334 #define Sdmmc1ClockSelection SdioClockSelection 3335 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO 3336 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 3337 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK 3338 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG 3339 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE 3340 #endif 3341 3342 #if defined(STM32F7) || defined(STM32L4) 3343 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET 3344 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET 3345 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE 3346 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE 3347 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE 3348 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE 3349 #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED 3350 #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED 3351 #define SdioClockSelection Sdmmc1ClockSelection 3352 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 3353 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG 3354 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE 3355 #endif 3356 3357 #if defined(STM32F7) 3358 #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 3359 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK 3360 #endif 3361 3362 #if defined(STM32H7) 3363 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() 3364 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() 3365 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() 3366 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() 3367 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() 3368 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() 3369 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() 3370 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() 3371 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() 3372 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() 3373 3374 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() 3375 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() 3376 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() 3377 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() 3378 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() 3379 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() 3380 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() 3381 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() 3382 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() 3383 #define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() 3384 #endif 3385 3386 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG 3387 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG 3388 3389 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE 3390 3391 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE 3392 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE 3393 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK 3394 #define IS_RCC_HCLK_DIV IS_RCC_PCLK 3395 #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK 3396 3397 #define RCC_IT_HSI14 RCC_IT_HSI14RDY 3398 3399 #define RCC_IT_CSSLSE RCC_IT_LSECSS 3400 #define RCC_IT_CSSHSE RCC_IT_CSS 3401 3402 #define RCC_PLLMUL_3 RCC_PLL_MUL3 3403 #define RCC_PLLMUL_4 RCC_PLL_MUL4 3404 #define RCC_PLLMUL_6 RCC_PLL_MUL6 3405 #define RCC_PLLMUL_8 RCC_PLL_MUL8 3406 #define RCC_PLLMUL_12 RCC_PLL_MUL12 3407 #define RCC_PLLMUL_16 RCC_PLL_MUL16 3408 #define RCC_PLLMUL_24 RCC_PLL_MUL24 3409 #define RCC_PLLMUL_32 RCC_PLL_MUL32 3410 #define RCC_PLLMUL_48 RCC_PLL_MUL48 3411 3412 #define RCC_PLLDIV_2 RCC_PLL_DIV2 3413 #define RCC_PLLDIV_3 RCC_PLL_DIV3 3414 #define RCC_PLLDIV_4 RCC_PLL_DIV4 3415 3416 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE 3417 #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG 3418 #define RCC_MCO_NODIV RCC_MCODIV_1 3419 #define RCC_MCO_DIV1 RCC_MCODIV_1 3420 #define RCC_MCO_DIV2 RCC_MCODIV_2 3421 #define RCC_MCO_DIV4 RCC_MCODIV_4 3422 #define RCC_MCO_DIV8 RCC_MCODIV_8 3423 #define RCC_MCO_DIV16 RCC_MCODIV_16 3424 #define RCC_MCO_DIV32 RCC_MCODIV_32 3425 #define RCC_MCO_DIV64 RCC_MCODIV_64 3426 #define RCC_MCO_DIV128 RCC_MCODIV_128 3427 #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK 3428 #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI 3429 #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE 3430 #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK 3431 #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI 3432 #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 3433 #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 3434 #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE 3435 #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK 3436 #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK 3437 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 3438 3439 #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) 3440 #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE 3441 #else 3442 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK 3443 #endif 3444 3445 #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 3446 #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL 3447 #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI 3448 #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL 3449 #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL 3450 #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 3451 #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 3452 #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 3453 3454 #define HSION_BitNumber RCC_HSION_BIT_NUMBER 3455 #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER 3456 #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER 3457 #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER 3458 #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER 3459 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER 3460 #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER 3461 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER 3462 #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER 3463 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER 3464 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER 3465 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER 3466 #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER 3467 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER 3468 #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER 3469 #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER 3470 #define LSION_BitNumber RCC_LSION_BIT_NUMBER 3471 #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER 3472 #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER 3473 #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER 3474 #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER 3475 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER 3476 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER 3477 #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER 3478 #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER 3479 #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER 3480 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS 3481 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS 3482 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS 3483 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS 3484 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE 3485 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE 3486 3487 #define CR_HSION_BB RCC_CR_HSION_BB 3488 #define CR_CSSON_BB RCC_CR_CSSON_BB 3489 #define CR_PLLON_BB RCC_CR_PLLON_BB 3490 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB 3491 #define CR_MSION_BB RCC_CR_MSION_BB 3492 #define CSR_LSION_BB RCC_CSR_LSION_BB 3493 #define CSR_LSEON_BB RCC_CSR_LSEON_BB 3494 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB 3495 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB 3496 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB 3497 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB 3498 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB 3499 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB 3500 #define CR_HSEON_BB RCC_CR_HSEON_BB 3501 #define CSR_RMVF_BB RCC_CSR_RMVF_BB 3502 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB 3503 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB 3504 3505 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE 3506 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE 3507 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE 3508 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE 3509 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE 3510 3511 #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT 3512 3513 #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN 3514 #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF 3515 3516 #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 3517 #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ 3518 #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP 3519 #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ 3520 #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE 3521 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 3522 3523 #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE 3524 #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE 3525 #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED 3526 #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED 3527 #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET 3528 #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET 3529 #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE 3530 #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE 3531 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED 3532 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED 3533 #define DfsdmClockSelection Dfsdm1ClockSelection 3534 #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 3535 #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3536 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK 3537 #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG 3538 #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE 3539 #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 3540 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 3541 #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 3542 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 3543 3544 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 3545 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 3546 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 3547 #define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 3548 #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 3549 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 3550 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 3551 #if defined(STM32U5) 3552 #define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL 3553 #define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL 3554 #define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE 3555 #define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE 3556 #define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE 3557 #define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE 3558 #define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE 3559 #define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE 3560 #define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE 3561 #define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE 3562 #define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE 3563 #define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT 3564 #define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK 3565 #define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 3566 #define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 3567 #define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 3568 #define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK 3569 #define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE 3570 #define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE 3571 #define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED 3572 #define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED 3573 #define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET 3574 #define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET 3575 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE 3576 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE 3577 #define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE 3578 #define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE 3579 #define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE 3580 #define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG 3581 #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE 3582 #endif /* STM32U5 */ 3583 3584 /** 3585 * @} 3586 */ 3587 3588 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose 3589 * @{ 3590 */ 3591 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) 3592 3593 /** 3594 * @} 3595 */ 3596 3597 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose 3598 * @{ 3599 */ 3600 #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ 3601 defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ 3602 defined (STM32C0) 3603 #else 3604 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG 3605 #endif 3606 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT 3607 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT 3608 3609 #if defined (STM32F1) 3610 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() 3611 3612 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() 3613 3614 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() 3615 3616 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() 3617 3618 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() 3619 #else 3620 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ 3621 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ 3622 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) 3623 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ 3624 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ 3625 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) 3626 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ 3627 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ 3628 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) 3629 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ 3630 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ 3631 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) 3632 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ 3633 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ 3634 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) 3635 #endif /* STM32F1 */ 3636 3637 #define IS_ALARM IS_RTC_ALARM 3638 #define IS_ALARM_MASK IS_RTC_ALARM_MASK 3639 #define IS_TAMPER IS_RTC_TAMPER 3640 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE 3641 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER 3642 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT 3643 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE 3644 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION 3645 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE 3646 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ 3647 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION 3648 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER 3649 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK 3650 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER 3651 3652 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE 3653 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE 3654 3655 /** 3656 * @} 3657 */ 3658 3659 /** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose 3660 * @{ 3661 */ 3662 3663 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE 3664 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS 3665 3666 #if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) 3667 #define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE 3668 #define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE 3669 #define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE 3670 3671 #define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV 3672 #define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV 3673 #endif 3674 3675 #if defined(STM32F4) || defined(STM32F2) 3676 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED 3677 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY 3678 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED 3679 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION 3680 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND 3681 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT 3682 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED 3683 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE 3684 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE 3685 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE 3686 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL 3687 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT 3688 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT 3689 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG 3690 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG 3691 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT 3692 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT 3693 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS 3694 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT 3695 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND 3696 /* alias CMSIS */ 3697 #define SDMMC1_IRQn SDIO_IRQn 3698 #define SDMMC1_IRQHandler SDIO_IRQHandler 3699 #endif 3700 3701 #if defined(STM32F7) || defined(STM32L4) 3702 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED 3703 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY 3704 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED 3705 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION 3706 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND 3707 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT 3708 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED 3709 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE 3710 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE 3711 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE 3712 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE 3713 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT 3714 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT 3715 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG 3716 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG 3717 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT 3718 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT 3719 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS 3720 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT 3721 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND 3722 /* alias CMSIS for compatibilities */ 3723 #define SDIO_IRQn SDMMC1_IRQn 3724 #define SDIO_IRQHandler SDMMC1_IRQHandler 3725 #endif 3726 3727 #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) 3728 #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef 3729 #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef 3730 #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef 3731 #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef 3732 #endif 3733 3734 #if defined(STM32H7) || defined(STM32L5) 3735 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback 3736 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback 3737 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback 3738 #define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback 3739 #define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback 3740 #define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback 3741 #define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback 3742 #define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback 3743 #define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback 3744 #endif 3745 /** 3746 * @} 3747 */ 3748 3749 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose 3750 * @{ 3751 */ 3752 3753 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT 3754 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT 3755 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE 3756 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE 3757 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE 3758 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE 3759 3760 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3761 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE 3762 3763 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE 3764 3765 /** 3766 * @} 3767 */ 3768 3769 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose 3770 * @{ 3771 */ 3772 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 3773 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 3774 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START 3775 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH 3776 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR 3777 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE 3778 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE 3779 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED 3780 /** 3781 * @} 3782 */ 3783 3784 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose 3785 * @{ 3786 */ 3787 3788 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX 3789 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX 3790 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC 3791 3792 /** 3793 * @} 3794 */ 3795 3796 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose 3797 * @{ 3798 */ 3799 3800 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3801 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3802 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE 3803 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION 3804 3805 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD 3806 3807 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE 3808 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE 3809 3810 /** 3811 * @} 3812 */ 3813 3814 3815 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose 3816 * @{ 3817 */ 3818 3819 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT 3820 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT 3821 #define __USART_ENABLE __HAL_USART_ENABLE 3822 #define __USART_DISABLE __HAL_USART_DISABLE 3823 3824 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3825 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE 3826 3827 #if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) 3828 #define USART_OVERSAMPLING_16 0x00000000U 3829 #define USART_OVERSAMPLING_8 USART_CR1_OVER8 3830 3831 #define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ 3832 ((__SAMPLING__) == USART_OVERSAMPLING_8)) 3833 #endif /* STM32F0 || STM32F3 || STM32F7 */ 3834 /** 3835 * @} 3836 */ 3837 3838 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose 3839 * @{ 3840 */ 3841 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE 3842 3843 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 3844 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 3845 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 3846 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE 3847 3848 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE 3849 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE 3850 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE 3851 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE 3852 3853 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT 3854 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT 3855 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG 3856 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG 3857 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE 3858 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3859 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3860 3861 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT 3862 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT 3863 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG 3864 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG 3865 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3866 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3867 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3868 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT 3869 3870 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT 3871 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT 3872 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG 3873 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG 3874 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE 3875 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE 3876 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE 3877 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT 3878 3879 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup 3880 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup 3881 3882 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo 3883 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo 3884 /** 3885 * @} 3886 */ 3887 3888 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose 3889 * @{ 3890 */ 3891 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE 3892 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE 3893 3894 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3895 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT 3896 3897 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE 3898 3899 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN 3900 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER 3901 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER 3902 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER 3903 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD 3904 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD 3905 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION 3906 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION 3907 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER 3908 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER 3909 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE 3910 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE 3911 3912 #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 3913 /** 3914 * @} 3915 */ 3916 3917 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose 3918 * @{ 3919 */ 3920 3921 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT 3922 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT 3923 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG 3924 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG 3925 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER 3926 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER 3927 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER 3928 3929 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE 3930 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE 3931 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE 3932 /** 3933 * @} 3934 */ 3935 3936 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose 3937 * @{ 3938 */ 3939 #define __HAL_LTDC_LAYER LTDC_LAYER 3940 #define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG 3941 /** 3942 * @} 3943 */ 3944 3945 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose 3946 * @{ 3947 */ 3948 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE 3949 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE 3950 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE 3951 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE 3952 #define SAI_STREOMODE SAI_STEREOMODE 3953 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY 3954 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL 3955 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL 3956 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL 3957 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL 3958 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL 3959 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE 3960 #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 3961 #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE 3962 /** 3963 * @} 3964 */ 3965 3966 /** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose 3967 * @{ 3968 */ 3969 #if defined(STM32H7) 3970 #define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow 3971 #define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT 3972 #define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA 3973 #endif 3974 /** 3975 * @} 3976 */ 3977 3978 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose 3979 * @{ 3980 */ 3981 #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) 3982 #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT 3983 #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA 3984 #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart 3985 #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT 3986 #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA 3987 #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop 3988 #endif 3989 /** 3990 * @} 3991 */ 3992 3993 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose 3994 * @{ 3995 */ 3996 #if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) 3997 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE 3998 #endif /* STM32L4 || STM32F4 || STM32F7 */ 3999 /** 4000 * @} 4001 */ 4002 4003 /** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose 4004 * @{ 4005 */ 4006 #if defined (STM32F7) 4007 #define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE 4008 #endif /* STM32F7 */ 4009 /** 4010 * @} 4011 */ 4012 4013 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose 4014 * @{ 4015 */ 4016 4017 /** 4018 * @} 4019 */ 4020 4021 #ifdef __cplusplus 4022 } 4023 #endif 4024 4025 #endif /* STM32_HAL_LEGACY */ 4026 4027 4028
