1 /**
2 ******************************************************************************
3 * @file system_stm32l4xx.c
4 * @author MCD Application Team
5 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
6 *
7 * This file provides two functions and one global variable to be called from
8 * user application:
9 * - SystemInit(): This function is called at startup just after reset and
10 * before branch to main program. This call is made inside
11 * the "startup_stm32l4xx.s" file.
12 *
13 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14 * by the user application to setup the SysTick
15 * timer or configure other parameters.
16 *
17 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18 * be called whenever the core clock is changed
19 * during program execution.
20 *
21 * After each device reset the MSI (4 MHz) is used as system clock source.
22 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
23 * configure the system clock before to branch to main program.
24 *
25 * This file configures the system clock as follows:
26 *=============================================================================
27 *-----------------------------------------------------------------------------
28 * System Clock source | MSI
29 *-----------------------------------------------------------------------------
30 * SYSCLK(Hz) | 4000000
31 *-----------------------------------------------------------------------------
32 * HCLK(Hz) | 4000000
33 *-----------------------------------------------------------------------------
34 * AHB Prescaler | 1
35 *-----------------------------------------------------------------------------
36 * APB1 Prescaler | 1
37 *-----------------------------------------------------------------------------
38 * APB2 Prescaler | 1
39 *-----------------------------------------------------------------------------
40 * PLL_M | 1
41 *-----------------------------------------------------------------------------
42 * PLL_N | 8
43 *-----------------------------------------------------------------------------
44 * PLL_P | 7
45 *-----------------------------------------------------------------------------
46 * PLL_Q | 2
47 *-----------------------------------------------------------------------------
48 * PLL_R | 2
49 *-----------------------------------------------------------------------------
50 * PLLSAI1_P | NA
51 *-----------------------------------------------------------------------------
52 * PLLSAI1_Q | NA
53 *-----------------------------------------------------------------------------
54 * PLLSAI1_R | NA
55 *-----------------------------------------------------------------------------
56 * PLLSAI2_P | NA
57 *-----------------------------------------------------------------------------
58 * PLLSAI2_Q | NA
59 *-----------------------------------------------------------------------------
60 * PLLSAI2_R | NA
61 *-----------------------------------------------------------------------------
62 * Require 48MHz for USB OTG FS, | Disabled
63 * SDIO and RNG clock |
64 *-----------------------------------------------------------------------------
65 *=============================================================================
66 ******************************************************************************
67 * @attention
68 *
69 * Copyright (c) 2017 STMicroelectronics.
70 * All rights reserved.
71 *
72 * This software is licensed under terms that can be found in the LICENSE file
73 * in the root directory of this software component.
74 * If no LICENSE file comes with this software, it is provided AS-IS.
75 *
76 ******************************************************************************
77 */
78
79 /** @addtogroup CMSIS
80 * @{
81 */
82
83 /** @addtogroup stm32l4xx_system
84 * @{
85 */
86
87 /** @addtogroup STM32L4xx_System_Private_Includes
88 * @{
89 */
90
91 #include "stm32l4xx.h"
92
93 /**
94 * @}
95 */
96
97 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
98 * @{
99 */
100
101 /**
102 * @}
103 */
104
105 /** @addtogroup STM32L4xx_System_Private_Defines
106 * @{
107 */
108
109 #if !defined (HSE_VALUE)
110 #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
111 #endif /* HSE_VALUE */
112
113 #if !defined (MSI_VALUE)
114 #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
115 #endif /* MSI_VALUE */
116
117 #if !defined (HSI_VALUE)
118 #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
119 #endif /* HSI_VALUE */
120
121 /* Note: Following vector table addresses must be defined in line with linker
122 configuration. */
123 /*!< Uncomment the following line if you need to relocate the vector table
124 anywhere in Flash or Sram, else the vector table is kept at the automatic
125 remap of boot address selected */
126 /* #define USER_VECT_TAB_ADDRESS */
127
128 #if defined(USER_VECT_TAB_ADDRESS)
129 /*!< Uncomment the following line if you need to relocate your vector Table
130 in Sram else user remap will be done in Flash. */
131 /* #define VECT_TAB_SRAM */
132
133 #if defined(VECT_TAB_SRAM)
134 #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field.
135 This value must be a multiple of 0x200. */
136 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
137 This value must be a multiple of 0x200. */
138 #else
139 #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
140 This value must be a multiple of 0x200. */
141 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
142 This value must be a multiple of 0x200. */
143 #endif /* VECT_TAB_SRAM */
144 #endif /* USER_VECT_TAB_ADDRESS */
145
146 /******************************************************************************/
147 /**
148 * @}
149 */
150
151 /** @addtogroup STM32L4xx_System_Private_Macros
152 * @{
153 */
154
155 /**
156 * @}
157 */
158
159 /** @addtogroup STM32L4xx_System_Private_Variables
160 * @{
161 */
162 /* The SystemCoreClock variable is updated in three ways:
163 1) by calling CMSIS function SystemCoreClockUpdate()
164 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
165 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
166 Note: If you use this function to configure the system clock; then there
167 is no need to call the 2 first functions listed above, since SystemCoreClock
168 variable is updated automatically.
169 */
170 uint32_t SystemCoreClock = 4000000U;
171
172 const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
173 const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
174 const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \
175 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U};
176 /**
177 * @}
178 */
179
180 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
181 * @{
182 */
183
184 /**
185 * @}
186 */
187
188 /** @addtogroup STM32L4xx_System_Private_Functions
189 * @{
190 */
191
192 /**
193 * @brief Setup the microcontroller system.
194 * @retval None
195 */
196
SystemInit(void)197 void SystemInit(void)
198 {
199 #if defined(USER_VECT_TAB_ADDRESS)
200 /* Configure the Vector Table location -------------------------------------*/
201 SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
202 #endif
203
204 /* FPU settings ------------------------------------------------------------*/
205 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
206 SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
207 #endif
208 }
209
210 /**
211 * @brief Update SystemCoreClock variable according to Clock Register Values.
212 * The SystemCoreClock variable contains the core clock (HCLK), it can
213 * be used by the user application to setup the SysTick timer or configure
214 * other parameters.
215 *
216 * @note Each time the core clock (HCLK) changes, this function must be called
217 * to update SystemCoreClock variable value. Otherwise, any configuration
218 * based on this variable will be incorrect.
219 *
220 * @note - The system frequency computed by this function is not the real
221 * frequency in the chip. It is calculated based on the predefined
222 * constant and the selected clock source:
223 *
224 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
225 *
226 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
227 *
228 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
229 *
230 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
231 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
232 *
233 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
234 * 4 MHz) but the real value may vary depending on the variations
235 * in voltage and temperature.
236 *
237 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
238 * 16 MHz) but the real value may vary depending on the variations
239 * in voltage and temperature.
240 *
241 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
242 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
243 * frequency of the crystal used. Otherwise, this function may
244 * have wrong result.
245 *
246 * - The result of this function could be not correct when using fractional
247 * value for HSE crystal.
248 *
249 * @retval None
250 */
SystemCoreClockUpdate(void)251 void SystemCoreClockUpdate(void)
252 {
253 uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr;
254
255 /* Get MSI Range frequency--------------------------------------------------*/
256 if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
257 { /* MSISRANGE from RCC_CSR applies */
258 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
259 }
260 else
261 { /* MSIRANGE from RCC_CR applies */
262 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
263 }
264 /*MSI frequency range in HZ*/
265 msirange = MSIRangeTable[msirange];
266
267 /* Get SYSCLK source -------------------------------------------------------*/
268 switch (RCC->CFGR & RCC_CFGR_SWS)
269 {
270 case 0x00: /* MSI used as system clock source */
271 SystemCoreClock = msirange;
272 break;
273
274 case 0x04: /* HSI used as system clock source */
275 SystemCoreClock = HSI_VALUE;
276 break;
277
278 case 0x08: /* HSE used as system clock source */
279 SystemCoreClock = HSE_VALUE;
280 break;
281
282 case 0x0C: /* PLL used as system clock source */
283 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
284 SYSCLK = PLL_VCO / PLLR
285 */
286 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
287 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ;
288
289 switch (pllsource)
290 {
291 case 0x02: /* HSI used as PLL clock source */
292 pllvco = (HSI_VALUE / pllm);
293 break;
294
295 case 0x03: /* HSE used as PLL clock source */
296 pllvco = (HSE_VALUE / pllm);
297 break;
298
299 default: /* MSI used as PLL clock source */
300 pllvco = (msirange / pllm);
301 break;
302 }
303 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U);
304 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U;
305 SystemCoreClock = pllvco/pllr;
306 break;
307
308 default:
309 SystemCoreClock = msirange;
310 break;
311 }
312 /* Compute HCLK clock frequency --------------------------------------------*/
313 /* Get HCLK prescaler */
314 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
315 /* HCLK clock frequency */
316 SystemCoreClock >>= tmp;
317 }
318
319
320 /**
321 * @}
322 */
323
324 /**
325 * @}
326 */
327
328 /**
329 * @}
330 */
331
332 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
333
