1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 *
7 ******************************************************************************
8 * @attention
9 *
10 * Copyright (c) 2017 STMicroelectronics.
11 * All rights reserved.
12 *
13 * This software is licensed under terms that can be found in the LICENSE file
14 * in the root directory of this software component.
15 * If no LICENSE file comes with this software, it is provided AS-IS.
16 *
17 ******************************************************************************
18 @verbatim
19 ==============================================================================
20 ##### How to use this driver #####
21 ==============================================================================
22 [..]
23 The LL UTILS driver contains a set of generic APIs that can be
24 used by user:
25 (+) Device electronic signature
26 (+) Timing functions
27 (+) PLL configuration functions
28
29 @endverbatim
30 ******************************************************************************
31 */
32
33 /* Define to prevent recursive inclusion -------------------------------------*/
34 #ifndef STM32L4xx_LL_UTILS_H
35 #define STM32L4xx_LL_UTILS_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /* Includes ------------------------------------------------------------------*/
42 #include "stm32l4xx.h"
43
44 /** @addtogroup STM32L4xx_LL_Driver
45 * @{
46 */
47
48 /** @defgroup UTILS_LL UTILS
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
57 * @{
58 */
59
60 /* Max delay can be used in LL_mDelay */
61 #define LL_MAX_DELAY 0xFFFFFFFFU
62
63 /**
64 * @brief Unique device ID register base address
65 */
66 #define UID_BASE_ADDRESS UID_BASE
67
68 /**
69 * @brief Flash size data register base address
70 */
71 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
72
73 /**
74 * @brief Package data register base address
75 */
76 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
77
78 /**
79 * @}
80 */
81
82 /* Private macros ------------------------------------------------------------*/
83 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
84 * @{
85 */
86 /**
87 * @}
88 */
89 /* Exported types ------------------------------------------------------------*/
90 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
91 * @{
92 */
93 /**
94 * @brief UTILS PLL structure definition
95 */
96 typedef struct
97 {
98 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
99 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
100
101 This feature can be modified afterwards using unitary function
102 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
103
104 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
105 This parameter must be a number between Min_Data = 8 and Max_Data = 86
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
109
110 uint32_t PLLR; /*!< Division for the main system clock.
111 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
115 } LL_UTILS_PLLInitTypeDef;
116
117 /**
118 * @brief UTILS System, AHB and APB buses clock configuration structure definition
119 */
120 typedef struct
121 {
122 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
123 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
124
125 This feature can be modified afterwards using unitary function
126 @ref LL_RCC_SetAHBPrescaler(). */
127
128 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
129 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
130
131 This feature can be modified afterwards using unitary function
132 @ref LL_RCC_SetAPB1Prescaler(). */
133
134 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
135 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
136
137 This feature can be modified afterwards using unitary function
138 @ref LL_RCC_SetAPB2Prescaler(). */
139
140 } LL_UTILS_ClkInitTypeDef;
141
142 /**
143 * @}
144 */
145
146 /* Exported constants --------------------------------------------------------*/
147 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
148 * @{
149 */
150
151 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
152 * @{
153 */
154 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
155 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
156 /**
157 * @}
158 */
159
160 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
161 * @{
162 */
163 #define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
164 #define LL_UTILS_PACKAGETYPE_WLCSP64 0x00000001U /*!< WLCSP64 package type */
165 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
166 #define LL_UTILS_PACKAGETYPE_BGA132 0x00000003U /*!< BGA132 package type */
167 #define LL_UTILS_PACKAGETYPE_LQFP144_CSP72 0x00000004U /*!< LQFP144, WLCSP81 or WLCSP72 package type */
168 #define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
169 #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
170 #define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
171 #define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
172 #define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
173 #define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
174 #define LL_UTILS_PACKAGETYPE_UFBGA169_CSP115 0x00000010U /*!< UFBGA169 or WLCSP115 package type */
175 #define LL_UTILS_PACKAGETYPE_LQFP100_DSI 0x00000012U /*!< LQFP100 with DSI package type */
176 #define LL_UTILS_PACKAGETYPE_WLCSP144_DSI 0x00000013U /*!< WLCSP144 with DSI package type */
177 #define LL_UTILS_PACKAGETYPE_UFBGA144_DSI 0x00000013U /*!< UFBGA144 with DSI package type */
178 #define LL_UTILS_PACKAGETYPE_UFBGA169_DSI 0x00000014U /*!< UFBGA169 with DSI package type */
179 #define LL_UTILS_PACKAGETYPE_LQFP144_DSI 0x00000015U /*!< LQFP144 with DSI package type */
180 /**
181 * @}
182 */
183
184 /**
185 * @}
186 */
187
188 /* Exported macro ------------------------------------------------------------*/
189
190 /* Exported functions --------------------------------------------------------*/
191 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
192 * @{
193 */
194
195 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
196 * @{
197 */
198
199 /**
200 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
201 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
202 */
LL_GetUID_Word0(void)203 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
204 {
205 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
206 }
207
208 /**
209 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
210 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
211 */
LL_GetUID_Word1(void)212 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
213 {
214 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
215 }
216
217 /**
218 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
219 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
220 */
LL_GetUID_Word2(void)221 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
222 {
223 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
224 }
225
226 /**
227 * @brief Get Flash memory size
228 * @note This bitfield indicates the size of the device Flash memory expressed in
229 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
230 * @retval FLASH_SIZE[15:0]: Flash memory size
231 */
LL_GetFlashSize(void)232 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
233 {
234 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
235 }
236
237 /**
238 * @brief Get Package type
239 * @retval Returned value can be one of the following values:
240 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)
241 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 (*)
242 * @arg @ref LL_UTILS_PACKAGETYPE_BGA132 (*)
243 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_CSP72 (*)
244 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32 (*)
245 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48 (*)
246 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 (*)
247 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49 (*)
248 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64 (*)
249 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100 (*)
250 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 (*)
251 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_DSI (*)
252 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_DSI (*)
253 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_DSI (*)
254 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_DSI (*)
255 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_DSI (*)
256 *
257 * (*) value not defined in all devices.
258 */
LL_GetPackageType(void)259 __STATIC_INLINE uint32_t LL_GetPackageType(void)
260 {
261 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
262 }
263
264 /**
265 * @}
266 */
267
268 /** @defgroup UTILS_LL_EF_DELAY DELAY
269 * @{
270 */
271
272 /**
273 * @brief This function configures the Cortex-M SysTick source of the time base.
274 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
275 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
276 * configuration by calling this function, for a delay use rather osDelay RTOS service.
277 * @param Ticks Number of ticks
278 * @retval None
279 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)280 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
281 {
282 /* Configure the SysTick to have interrupt in 1ms time base */
283 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
284 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
285 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
286 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
287 }
288
289 void LL_Init1msTick(uint32_t HCLKFrequency);
290 void LL_mDelay(uint32_t Delay);
291
292 /**
293 * @}
294 */
295
296 /** @defgroup UTILS_EF_SYSTEM SYSTEM
297 * @{
298 */
299
300 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
301 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
302 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
303 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
304 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
305 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
306 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
307 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
308
309 /**
310 * @}
311 */
312
313 /**
314 * @}
315 */
316
317 /**
318 * @}
319 */
320
321 /**
322 * @}
323 */
324
325 #ifdef __cplusplus
326 }
327 #endif
328
329 #endif /* STM32L4xx_LL_UTILS_H */
330
