1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32L4xx_LL_CRS_H
21 #define STM32L4xx_LL_CRS_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32l4xx.h"
29
30 /** @addtogroup STM32L4xx_LL_Driver
31 * @{
32 */
33
34 #if defined(CRS)
35
36 /** @defgroup CRS_LL CRS
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
48 * @{
49 */
50
51 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
52 * @brief Flags defines which can be used with LL_CRS_ReadReg function
53 * @{
54 */
55 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
56 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
57 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
58 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
59 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
60 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
61 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
62 /**
63 * @}
64 */
65
66 /** @defgroup CRS_LL_EC_IT IT Defines
67 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
68 * @{
69 */
70 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
71 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
72 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
73 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
74 /**
75 * @}
76 */
77
78 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
79 * @{
80 */
81 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
82 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
83 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
84 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
85 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
86 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
87 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
88 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
89 /**
90 * @}
91 */
92
93 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
94 * @{
95 */
96 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
97 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
98 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
99 /**
100 * @}
101 */
102
103 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
104 * @{
105 */
106 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
107 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
108 /**
109 * @}
110 */
111
112 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
113 * @{
114 */
115 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
116 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
117 /**
118 * @}
119 */
120
121 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
122 * @{
123 */
124 /**
125 * @brief Reset value of the RELOAD field
126 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
127 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
128 */
129 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
130
131 /**
132 * @brief Reset value of Frequency error limit.
133 */
134 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
135
136 /**
137 * @brief Reset value of the HSI48 Calibration field
138 * @note The default value is 64 for STM32L412xx/L422xx, 32 otherwise, which corresponds
139 * to the middle of the trimming interval.
140 * The trimming step is around 67 kHz between two consecutive TRIM steps.
141 * A higher TRIM value corresponds to a higher output frequency
142 */
143 #if defined (STM32L412xx) || defined (STM32L422xx)
144 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)64U)
145 #else
146 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)32U)
147 #endif
148 /**
149 * @}
150 */
151
152 /**
153 * @}
154 */
155
156 /* Exported macro ------------------------------------------------------------*/
157 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
158 * @{
159 */
160
161 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
162 * @{
163 */
164
165 /**
166 * @brief Write a value in CRS register
167 * @param __INSTANCE__ CRS Instance
168 * @param __REG__ Register to be written
169 * @param __VALUE__ Value to be written in the register
170 * @retval None
171 */
172 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
173
174 /**
175 * @brief Read a value in CRS register
176 * @param __INSTANCE__ CRS Instance
177 * @param __REG__ Register to be read
178 * @retval Register value
179 */
180 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
181 /**
182 * @}
183 */
184
185 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
186 * @{
187 */
188
189 /**
190 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
191 * @note The RELOAD value should be selected according to the ratio between
192 * the target frequency and the frequency of the synchronization source after
193 * prescaling. It is then decreased by one in order to reach the expected
194 * synchronization on the zero value. The formula is the following:
195 * RELOAD = (fTARGET / fSYNC) -1
196 * @param __FTARGET__ Target frequency (value in Hz)
197 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
198 * @retval Reload value (in Hz)
199 */
200 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
201
202 /**
203 * @}
204 */
205
206 /**
207 * @}
208 */
209
210 /* Exported functions --------------------------------------------------------*/
211 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
212 * @{
213 */
214
215 /** @defgroup CRS_LL_EF_Configuration Configuration
216 * @{
217 */
218
219 /**
220 * @brief Enable Frequency error counter
221 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
222 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
223 * @retval None
224 */
LL_CRS_EnableFreqErrorCounter(void)225 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
226 {
227 SET_BIT(CRS->CR, CRS_CR_CEN);
228 }
229
230 /**
231 * @brief Disable Frequency error counter
232 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
233 * @retval None
234 */
LL_CRS_DisableFreqErrorCounter(void)235 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
236 {
237 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
238 }
239
240 /**
241 * @brief Check if Frequency error counter is enabled or not
242 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
243 * @retval State of bit (1 or 0).
244 */
LL_CRS_IsEnabledFreqErrorCounter(void)245 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
246 {
247 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
248 }
249
250 /**
251 * @brief Enable Automatic trimming counter
252 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
253 * @retval None
254 */
LL_CRS_EnableAutoTrimming(void)255 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
256 {
257 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
258 }
259
260 /**
261 * @brief Disable Automatic trimming counter
262 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
263 * @retval None
264 */
LL_CRS_DisableAutoTrimming(void)265 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
266 {
267 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
268 }
269
270 /**
271 * @brief Check if Automatic trimming is enabled or not
272 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
273 * @retval State of bit (1 or 0).
274 */
LL_CRS_IsEnabledAutoTrimming(void)275 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
276 {
277 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
278 }
279
280 /**
281 * @brief Set HSI48 oscillator smooth trimming
282 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
283 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
284 * @param Value a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
285 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
286 * @retval None
287 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)288 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
289 {
290 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
291 }
292
293 /**
294 * @brief Get HSI48 oscillator smooth trimming
295 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
296 * @retval a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
297 */
LL_CRS_GetHSI48SmoothTrimming(void)298 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
299 {
300 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
301 }
302
303 /**
304 * @brief Set counter reload value
305 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
306 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
307 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
308 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
309 * @retval None
310 */
LL_CRS_SetReloadCounter(uint32_t Value)311 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
312 {
313 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
314 }
315
316 /**
317 * @brief Get counter reload value
318 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
319 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
320 */
LL_CRS_GetReloadCounter(void)321 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
322 {
323 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
324 }
325
326 /**
327 * @brief Set frequency error limit
328 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
329 * @param Value a number between Min_Data = 0 and Max_Data = 255
330 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
331 * @retval None
332 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)333 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
334 {
335 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
336 }
337
338 /**
339 * @brief Get frequency error limit
340 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
341 * @retval A number between Min_Data = 0 and Max_Data = 255
342 */
LL_CRS_GetFreqErrorLimit(void)343 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
344 {
345 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
346 }
347
348 /**
349 * @brief Set division factor for SYNC signal
350 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
351 * @param Divider This parameter can be one of the following values:
352 * @arg @ref LL_CRS_SYNC_DIV_1
353 * @arg @ref LL_CRS_SYNC_DIV_2
354 * @arg @ref LL_CRS_SYNC_DIV_4
355 * @arg @ref LL_CRS_SYNC_DIV_8
356 * @arg @ref LL_CRS_SYNC_DIV_16
357 * @arg @ref LL_CRS_SYNC_DIV_32
358 * @arg @ref LL_CRS_SYNC_DIV_64
359 * @arg @ref LL_CRS_SYNC_DIV_128
360 * @retval None
361 */
LL_CRS_SetSyncDivider(uint32_t Divider)362 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
363 {
364 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
365 }
366
367 /**
368 * @brief Get division factor for SYNC signal
369 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
370 * @retval Returned value can be one of the following values:
371 * @arg @ref LL_CRS_SYNC_DIV_1
372 * @arg @ref LL_CRS_SYNC_DIV_2
373 * @arg @ref LL_CRS_SYNC_DIV_4
374 * @arg @ref LL_CRS_SYNC_DIV_8
375 * @arg @ref LL_CRS_SYNC_DIV_16
376 * @arg @ref LL_CRS_SYNC_DIV_32
377 * @arg @ref LL_CRS_SYNC_DIV_64
378 * @arg @ref LL_CRS_SYNC_DIV_128
379 */
LL_CRS_GetSyncDivider(void)380 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
381 {
382 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
383 }
384
385 /**
386 * @brief Set SYNC signal source
387 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
388 * @param Source This parameter can be one of the following values:
389 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
390 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
391 * @arg @ref LL_CRS_SYNC_SOURCE_USB
392 * @retval None
393 */
LL_CRS_SetSyncSignalSource(uint32_t Source)394 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
395 {
396 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
397 }
398
399 /**
400 * @brief Get SYNC signal source
401 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
402 * @retval Returned value can be one of the following values:
403 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
404 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
405 * @arg @ref LL_CRS_SYNC_SOURCE_USB
406 */
LL_CRS_GetSyncSignalSource(void)407 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
408 {
409 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
410 }
411
412 /**
413 * @brief Set input polarity for the SYNC signal source
414 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
415 * @param Polarity This parameter can be one of the following values:
416 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
417 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
418 * @retval None
419 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)420 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
421 {
422 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
423 }
424
425 /**
426 * @brief Get input polarity for the SYNC signal source
427 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
428 * @retval Returned value can be one of the following values:
429 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
430 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
431 */
LL_CRS_GetSyncPolarity(void)432 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
433 {
434 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
435 }
436
437 /**
438 * @brief Configure CRS for the synchronization
439 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
440 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
441 * CFGR FELIM LL_CRS_ConfigSynchronization\n
442 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
443 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
444 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
445 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 for STM32L412xx/L422xx or 63 otherwise
446 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
447 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
448 * @param Settings This parameter can be a combination of the following values:
449 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
450 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
451 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
452 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
453 * @retval None
454 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)455 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
456 {
457 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
458 MODIFY_REG(CRS->CFGR,
459 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
460 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
461 }
462
463 /**
464 * @}
465 */
466
467 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
468 * @{
469 */
470
471 /**
472 * @brief Generate software SYNC event
473 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
474 * @retval None
475 */
LL_CRS_GenerateEvent_SWSYNC(void)476 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
477 {
478 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
479 }
480
481 /**
482 * @brief Get the frequency error direction latched in the time of the last
483 * SYNC event
484 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
485 * @retval Returned value can be one of the following values:
486 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
487 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
488 */
LL_CRS_GetFreqErrorDirection(void)489 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
490 {
491 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
492 }
493
494 /**
495 * @brief Get the frequency error counter value latched in the time of the last SYNC event
496 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
497 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
498 */
LL_CRS_GetFreqErrorCapture(void)499 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
500 {
501 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
502 }
503
504 /**
505 * @}
506 */
507
508 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
509 * @{
510 */
511
512 /**
513 * @brief Check if SYNC event OK signal occurred or not
514 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
515 * @retval State of bit (1 or 0).
516 */
LL_CRS_IsActiveFlag_SYNCOK(void)517 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
518 {
519 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
520 }
521
522 /**
523 * @brief Check if SYNC warning signal occurred or not
524 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
525 * @retval State of bit (1 or 0).
526 */
LL_CRS_IsActiveFlag_SYNCWARN(void)527 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
528 {
529 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
530 }
531
532 /**
533 * @brief Check if Synchronization or trimming error signal occurred or not
534 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
535 * @retval State of bit (1 or 0).
536 */
LL_CRS_IsActiveFlag_ERR(void)537 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
538 {
539 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
540 }
541
542 /**
543 * @brief Check if Expected SYNC signal occurred or not
544 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
545 * @retval State of bit (1 or 0).
546 */
LL_CRS_IsActiveFlag_ESYNC(void)547 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
548 {
549 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
550 }
551
552 /**
553 * @brief Check if SYNC error signal occurred or not
554 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
555 * @retval State of bit (1 or 0).
556 */
LL_CRS_IsActiveFlag_SYNCERR(void)557 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
558 {
559 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
560 }
561
562 /**
563 * @brief Check if SYNC missed error signal occurred or not
564 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
565 * @retval State of bit (1 or 0).
566 */
LL_CRS_IsActiveFlag_SYNCMISS(void)567 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
568 {
569 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
570 }
571
572 /**
573 * @brief Check if Trimming overflow or underflow occurred or not
574 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
575 * @retval State of bit (1 or 0).
576 */
LL_CRS_IsActiveFlag_TRIMOVF(void)577 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
578 {
579 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
580 }
581
582 /**
583 * @brief Clear the SYNC event OK flag
584 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
585 * @retval None
586 */
LL_CRS_ClearFlag_SYNCOK(void)587 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
588 {
589 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
590 }
591
592 /**
593 * @brief Clear the SYNC warning flag
594 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
595 * @retval None
596 */
LL_CRS_ClearFlag_SYNCWARN(void)597 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
598 {
599 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
600 }
601
602 /**
603 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
604 * the ERR flag
605 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
606 * @retval None
607 */
LL_CRS_ClearFlag_ERR(void)608 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
609 {
610 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
611 }
612
613 /**
614 * @brief Clear Expected SYNC flag
615 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
616 * @retval None
617 */
LL_CRS_ClearFlag_ESYNC(void)618 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
619 {
620 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
621 }
622
623 /**
624 * @}
625 */
626
627 /** @defgroup CRS_LL_EF_IT_Management IT_Management
628 * @{
629 */
630
631 /**
632 * @brief Enable SYNC event OK interrupt
633 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
634 * @retval None
635 */
LL_CRS_EnableIT_SYNCOK(void)636 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
637 {
638 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
639 }
640
641 /**
642 * @brief Disable SYNC event OK interrupt
643 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
644 * @retval None
645 */
LL_CRS_DisableIT_SYNCOK(void)646 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
647 {
648 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
649 }
650
651 /**
652 * @brief Check if SYNC event OK interrupt is enabled or not
653 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
654 * @retval State of bit (1 or 0).
655 */
LL_CRS_IsEnabledIT_SYNCOK(void)656 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
657 {
658 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
659 }
660
661 /**
662 * @brief Enable SYNC warning interrupt
663 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
664 * @retval None
665 */
LL_CRS_EnableIT_SYNCWARN(void)666 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
667 {
668 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
669 }
670
671 /**
672 * @brief Disable SYNC warning interrupt
673 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
674 * @retval None
675 */
LL_CRS_DisableIT_SYNCWARN(void)676 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
677 {
678 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
679 }
680
681 /**
682 * @brief Check if SYNC warning interrupt is enabled or not
683 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
684 * @retval State of bit (1 or 0).
685 */
LL_CRS_IsEnabledIT_SYNCWARN(void)686 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
687 {
688 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
689 }
690
691 /**
692 * @brief Enable Synchronization or trimming error interrupt
693 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
694 * @retval None
695 */
LL_CRS_EnableIT_ERR(void)696 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
697 {
698 SET_BIT(CRS->CR, CRS_CR_ERRIE);
699 }
700
701 /**
702 * @brief Disable Synchronization or trimming error interrupt
703 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
704 * @retval None
705 */
LL_CRS_DisableIT_ERR(void)706 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
707 {
708 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
709 }
710
711 /**
712 * @brief Check if Synchronization or trimming error interrupt is enabled or not
713 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
714 * @retval State of bit (1 or 0).
715 */
LL_CRS_IsEnabledIT_ERR(void)716 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
717 {
718 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
719 }
720
721 /**
722 * @brief Enable Expected SYNC interrupt
723 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
724 * @retval None
725 */
LL_CRS_EnableIT_ESYNC(void)726 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
727 {
728 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
729 }
730
731 /**
732 * @brief Disable Expected SYNC interrupt
733 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
734 * @retval None
735 */
LL_CRS_DisableIT_ESYNC(void)736 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
737 {
738 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
739 }
740
741 /**
742 * @brief Check if Expected SYNC interrupt is enabled or not
743 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
744 * @retval State of bit (1 or 0).
745 */
LL_CRS_IsEnabledIT_ESYNC(void)746 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
747 {
748 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
749 }
750
751 /**
752 * @}
753 */
754
755 #if defined(USE_FULL_LL_DRIVER)
756 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
757 * @{
758 */
759
760 ErrorStatus LL_CRS_DeInit(void);
761
762 /**
763 * @}
764 */
765 #endif /* USE_FULL_LL_DRIVER */
766
767 /**
768 * @}
769 */
770
771 /**
772 * @}
773 */
774
775 #endif /* defined(CRS) */
776
777 /**
778 * @}
779 */
780
781 #ifdef __cplusplus
782 }
783 #endif
784
785 #endif /* STM32L4xx_LL_CRS_H */
786
