1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_CORTEX_H 21 #define STM32L4xx_HAL_CORTEX_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /** @addtogroup STM32L4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @defgroup CORTEX CORTEX 35 * @brief CORTEX HAL module driver 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @brief MPU Region initialization structure 47 * @{ 48 */ 49 typedef struct 50 { 51 uint8_t Enable; /*!< Specifies the status of the region. 52 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 53 uint8_t Number; /*!< Specifies the number of the region to protect. 54 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 55 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 56 uint8_t Size; /*!< Specifies the size of the region to protect. 57 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 58 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 59 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 60 uint8_t TypeExtField; /*!< Specifies the TEX field level. 61 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 62 uint8_t AccessPermission; /*!< Specifies the region access permission type. 63 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 64 uint8_t DisableExec; /*!< Specifies the instruction access status. 65 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 66 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 67 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 68 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 69 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 70 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 71 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 72 }MPU_Region_InitTypeDef; 73 /** 74 * @} 75 */ 76 #endif /* __MPU_PRESENT */ 77 78 /** 79 * @} 80 */ 81 82 /* Exported constants --------------------------------------------------------*/ 83 84 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 85 * @{ 86 */ 87 88 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 89 * @{ 90 */ 91 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 92 4 bits for subpriority */ 93 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 94 3 bits for subpriority */ 95 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 96 2 bits for subpriority */ 97 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 98 1 bit for subpriority */ 99 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 100 0 bit for subpriority */ 101 /** 102 * @} 103 */ 104 105 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 106 * @{ 107 */ 108 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 109 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 110 111 /** 112 * @} 113 */ 114 115 #if (__MPU_PRESENT == 1) 116 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 117 * @{ 118 */ 119 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 120 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 121 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 122 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 123 /** 124 * @} 125 */ 126 127 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 128 * @{ 129 */ 130 #define MPU_REGION_ENABLE ((uint8_t)0x01) 131 #define MPU_REGION_DISABLE ((uint8_t)0x00) 132 /** 133 * @} 134 */ 135 136 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 137 * @{ 138 */ 139 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 140 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 141 /** 142 * @} 143 */ 144 145 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 146 * @{ 147 */ 148 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 149 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 150 /** 151 * @} 152 */ 153 154 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 155 * @{ 156 */ 157 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 158 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 159 /** 160 * @} 161 */ 162 163 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 164 * @{ 165 */ 166 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 167 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 168 /** 169 * @} 170 */ 171 172 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 173 * @{ 174 */ 175 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 176 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 177 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 178 #define MPU_TEX_LEVEL4 ((uint8_t)0x04) 179 /** 180 * @} 181 */ 182 183 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 184 * @{ 185 */ 186 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 187 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 188 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 189 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 190 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 191 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 192 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 193 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 194 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 195 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 196 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 197 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 198 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 199 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 200 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 201 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 202 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 203 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 204 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 205 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 206 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 207 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 208 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 209 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 210 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 211 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 212 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 213 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 214 /** 215 * @} 216 */ 217 218 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 219 * @{ 220 */ 221 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 222 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 223 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 224 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 225 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 226 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 227 /** 228 * @} 229 */ 230 231 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 232 * @{ 233 */ 234 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 235 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 236 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 237 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 238 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 239 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 240 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 241 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 242 /** 243 * @} 244 */ 245 #endif /* __MPU_PRESENT */ 246 247 /** 248 * @} 249 */ 250 251 /* Exported macros -----------------------------------------------------------*/ 252 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 253 * @{ 254 */ 255 256 /** 257 * @} 258 */ 259 260 /* Exported functions --------------------------------------------------------*/ 261 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 262 * @{ 263 */ 264 265 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 266 * @brief Initialization and Configuration functions 267 * @{ 268 */ 269 /* Initialization and Configuration functions *****************************/ 270 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 271 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 272 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 273 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 274 void HAL_NVIC_SystemReset(void); 275 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 276 277 /** 278 * @} 279 */ 280 281 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 282 * @brief Cortex control functions 283 * @{ 284 */ 285 /* Peripheral Control functions ***********************************************/ 286 uint32_t HAL_NVIC_GetPriorityGrouping(void); 287 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 288 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 289 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 290 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 291 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 292 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 293 void HAL_SYSTICK_IRQHandler(void); 294 void HAL_SYSTICK_Callback(void); 295 296 #if (__MPU_PRESENT == 1) 297 void HAL_MPU_Enable(uint32_t MPU_Control); 298 void HAL_MPU_Disable(void); 299 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 300 #endif /* __MPU_PRESENT */ 301 /** 302 * @} 303 */ 304 305 /** 306 * @} 307 */ 308 309 /* Private types -------------------------------------------------------------*/ 310 /* Private variables ---------------------------------------------------------*/ 311 /* Private constants ---------------------------------------------------------*/ 312 /* Private macros ------------------------------------------------------------*/ 313 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 314 * @{ 315 */ 316 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 317 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 318 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 319 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 320 ((GROUP) == NVIC_PRIORITYGROUP_4)) 321 322 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 323 324 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 325 326 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 327 328 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 329 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 330 331 #if (__MPU_PRESENT == 1) 332 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 333 ((STATE) == MPU_REGION_DISABLE)) 334 335 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 336 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 337 338 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 339 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 340 341 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 342 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 343 344 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 345 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 346 347 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 348 ((TYPE) == MPU_TEX_LEVEL1) || \ 349 ((TYPE) == MPU_TEX_LEVEL2) || \ 350 ((TYPE) == MPU_TEX_LEVEL4)) 351 352 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 353 ((TYPE) == MPU_REGION_PRIV_RW) || \ 354 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 355 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 356 ((TYPE) == MPU_REGION_PRIV_RO) || \ 357 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 358 359 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 360 ((NUMBER) == MPU_REGION_NUMBER1) || \ 361 ((NUMBER) == MPU_REGION_NUMBER2) || \ 362 ((NUMBER) == MPU_REGION_NUMBER3) || \ 363 ((NUMBER) == MPU_REGION_NUMBER4) || \ 364 ((NUMBER) == MPU_REGION_NUMBER5) || \ 365 ((NUMBER) == MPU_REGION_NUMBER6) || \ 366 ((NUMBER) == MPU_REGION_NUMBER7)) 367 368 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 369 ((SIZE) == MPU_REGION_SIZE_64B) || \ 370 ((SIZE) == MPU_REGION_SIZE_128B) || \ 371 ((SIZE) == MPU_REGION_SIZE_256B) || \ 372 ((SIZE) == MPU_REGION_SIZE_512B) || \ 373 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 374 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 375 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 376 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 377 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 378 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 379 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 380 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 381 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 382 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 383 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 384 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 385 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 386 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 387 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 388 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 389 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 390 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 391 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 392 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 393 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 394 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 395 ((SIZE) == MPU_REGION_SIZE_4GB)) 396 397 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 398 #endif /* __MPU_PRESENT */ 399 400 /** 401 * @} 402 */ 403 404 /* Private functions ---------------------------------------------------------*/ 405 406 /** 407 * @} 408 */ 409 410 /** 411 * @} 412 */ 413 414 #ifdef __cplusplus 415 } 416 #endif 417 418 #endif /* STM32L4xx_HAL_CORTEX_H */ 419 420 421
