1 /**
2 ******************************************************************************
3 * @file stm32l1xx_hal_i2c.c
4 * @author MCD Application Team
5 * @brief I2C HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral State, Mode and Error functions
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * Copyright (c) 2016 STMicroelectronics.
16 * All rights reserved.
17 *
18 * This software is licensed under terms that can be found in the LICENSE file
19 * in the root directory of this software component.
20 * If no LICENSE file comes with this software, it is provided AS-IS.
21 *
22 ******************************************************************************
23 @verbatim
24 ==============================================================================
25 ##### How to use this driver #####
26 ==============================================================================
27 [..]
28 The I2C HAL driver can be used as follows:
29
30 (#) Declare a I2C_HandleTypeDef handle structure, for example:
31 I2C_HandleTypeDef hi2c;
32
33 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
34 (##) Enable the I2Cx interface clock
35 (##) I2C pins configuration
36 (+++) Enable the clock for the I2C GPIOs
37 (+++) Configure I2C pins as alternate function open-drain
38 (##) NVIC configuration if you need to use interrupt process
39 (+++) Configure the I2Cx interrupt priority
40 (+++) Enable the NVIC I2C IRQ Channel
41 (##) DMA Configuration if you need to use DMA process
42 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
43 (+++) Enable the DMAx interface clock using
44 (+++) Configure the DMA handle parameters
45 (+++) Configure the DMA Tx or Rx channel
46 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
47 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
48 the DMA Tx or Rx channel
49
50 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
51 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
52
53 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
54 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API.
55
56 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
57
58 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
59
60 *** Polling mode IO operation ***
61 =================================
62 [..]
63 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
64 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
65 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
66 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
67
68 *** Polling mode IO MEM operation ***
69 =====================================
70 [..]
71 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
72 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
73
74
75 *** Interrupt mode IO operation ***
76 ===================================
77 [..]
78 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
79 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
80 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
81 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
82 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
83 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
84 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
85 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
86 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
87 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
88 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
89 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
90 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
91 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
92 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
93 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
94 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
95
96 *** Interrupt mode or DMA mode IO sequential operation ***
97 ==========================================================
98 [..]
99 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
100 when a direction change during transfer
101 [..]
102 (+) A specific option field manage the different steps of a sequential transfer
103 (+) Option field values are defined through I2C_XferOptions_definition and are listed below:
104 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
105 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
106 and data to transfer without a final stop condition
107 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
108 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
109 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
110 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
111 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
112 and with new data to transfer if the direction change or manage only the new data to transfer
113 if no direction change and without a final stop condition in both cases
114 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
115 and with new data to transfer if the direction change or manage only the new data to transfer
116 if no direction change and with a final stop condition in both cases
117 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
118 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
119 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
120 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
121 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
122 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
123 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
124 without stopping the communication and so generate a restart condition.
125 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
126 interface.
127 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
128 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
129 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
130 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
131 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
132
133 (+) Different sequential I2C interfaces are listed below:
134 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT()
135 or using HAL_I2C_Master_Seq_Transmit_DMA()
136 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
137 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
138 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT()
139 or using HAL_I2C_Master_Seq_Receive_DMA()
140 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
141 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
142 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
143 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
144 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
145 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
146 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
147 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
148 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
149 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
150 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT()
151 or using HAL_I2C_Slave_Seq_Transmit_DMA()
152 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
153 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
154 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT()
155 or using HAL_I2C_Slave_Seq_Receive_DMA()
156 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
157 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
158 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
159 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
160
161 *** Interrupt mode IO MEM operation ***
162 =======================================
163 [..]
164 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
165 HAL_I2C_Mem_Write_IT()
166 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
167 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
168 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
169 HAL_I2C_Mem_Read_IT()
170 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
171 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
172 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
173 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
174
175 *** DMA mode IO operation ***
176 ==============================
177 [..]
178 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
179 HAL_I2C_Master_Transmit_DMA()
180 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
181 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
182 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
183 HAL_I2C_Master_Receive_DMA()
184 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
185 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
186 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
187 HAL_I2C_Slave_Transmit_DMA()
188 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
189 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
190 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
191 HAL_I2C_Slave_Receive_DMA()
192 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
193 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
194 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
195 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
196 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
197 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
198 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
199
200 *** DMA mode IO MEM operation ***
201 =================================
202 [..]
203 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
204 HAL_I2C_Mem_Write_DMA()
205 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
206 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
207 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
208 HAL_I2C_Mem_Read_DMA()
209 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
210 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
211 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
212 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
213
214
215 *** I2C HAL driver macros list ***
216 ==================================
217 [..]
218 Below the list of most used macros in I2C HAL driver.
219
220 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
221 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
222 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not
223 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
224 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
225 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
226
227 *** Callback registration ***
228 =============================================
229 [..]
230 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
231 allows the user to configure dynamically the driver callbacks.
232 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
233 to register an interrupt callback.
234 [..]
235 Function HAL_I2C_RegisterCallback() allows to register following callbacks:
236 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
237 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
238 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
239 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
240 (+) ListenCpltCallback : callback for end of listen mode.
241 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
242 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
243 (+) ErrorCallback : callback for error detection.
244 (+) AbortCpltCallback : callback for abort completion process.
245 (+) MspInitCallback : callback for Msp Init.
246 (+) MspDeInitCallback : callback for Msp DeInit.
247 This function takes as parameters the HAL peripheral handle, the Callback ID
248 and a pointer to the user callback function.
249 [..]
250 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
251 [..]
252 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
253 weak function.
254 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
255 and the Callback ID.
256 This function allows to reset following callbacks:
257 (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
258 (+) MasterRxCpltCallback : callback for Master reception end of transfer.
259 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
260 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
261 (+) ListenCpltCallback : callback for end of listen mode.
262 (+) MemTxCpltCallback : callback for Memory transmission end of transfer.
263 (+) MemRxCpltCallback : callback for Memory reception end of transfer.
264 (+) ErrorCallback : callback for error detection.
265 (+) AbortCpltCallback : callback for abort completion process.
266 (+) MspInitCallback : callback for Msp Init.
267 (+) MspDeInitCallback : callback for Msp DeInit.
268 [..]
269 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
270 [..]
271 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
272 all callbacks are set to the corresponding weak functions:
273 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
274 Exception done for MspInit and MspDeInit functions that are
275 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
276 these callbacks are null (not registered beforehand).
277 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
278 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
279 [..]
280 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
281 Exception done MspInit/MspDeInit functions that can be registered/unregistered
282 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
283 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
284 Then, the user first registers the MspInit/MspDeInit user callbacks
285 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
286 or HAL_I2C_Init() function.
287 [..]
288 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
289 not defined, the callback registration feature is not available and all callbacks
290 are set to the corresponding weak functions.
291
292
293
294 [..]
295 (@) You can refer to the I2C HAL driver header file for more useful macros
296
297 @endverbatim
298 */
299
300 /* Includes ------------------------------------------------------------------*/
301 #include "stm32l1xx_hal.h"
302
303 /** @addtogroup STM32L1xx_HAL_Driver
304 * @{
305 */
306
307 /** @defgroup I2C I2C
308 * @brief I2C HAL module driver
309 * @{
310 */
311
312 #ifdef HAL_I2C_MODULE_ENABLED
313
314 /* Private typedef -----------------------------------------------------------*/
315 /* Private define ------------------------------------------------------------*/
316 /** @defgroup I2C_Private_Define I2C Private Define
317 * @{
318 */
319 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */
320 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
321 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */
322 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
323
324 /* Private define for @ref PreviousState usage */
325 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
326 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
327 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
328 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
329 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
330 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
331
332 /**
333 * @}
334 */
335
336 /* Private macro -------------------------------------------------------------*/
337 /** @addtogroup I2C_Private_Macros
338 * @{
339 */
340 /* Macro to get remaining data to transfer on DMA side */
341 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
342 /**
343 * @}
344 */
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347
348 /** @defgroup I2C_Private_Functions I2C Private Functions
349 * @{
350 */
351 /* Private functions to handle DMA transfer */
352 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
353 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
354 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
355
356 static void I2C_ITError(I2C_HandleTypeDef *hi2c);
357
358 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
359 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
360 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
361 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
362
363 /* Private functions to handle flags during polling transfer */
364 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
365 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
366 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
367 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
368 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
369 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
370 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);
371 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
372
373 /* Private functions for I2C transfer IRQ handler */
374 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
375 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
376 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
377 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
378 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c);
379 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
380 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
381
382 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
383 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
384 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
385 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
386 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);
387 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
388 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
389
390 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);
391
392 /* Private function to Convert Specific options */
393 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
394
395 /* Private function to flush DR register */
396 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c);
397 /**
398 * @}
399 */
400
401 /* Exported functions --------------------------------------------------------*/
402
403 /** @defgroup I2C_Exported_Functions I2C Exported Functions
404 * @{
405 */
406
407 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
408 * @brief Initialization and Configuration functions
409 *
410 @verbatim
411 ===============================================================================
412 ##### Initialization and de-initialization functions #####
413 ===============================================================================
414 [..] This subsection provides a set of functions allowing to initialize and
415 deinitialize the I2Cx peripheral:
416
417 (+) User must Implement HAL_I2C_MspInit() function in which he configures
418 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
419
420 (+) Call the function HAL_I2C_Init() to configure the selected device with
421 the selected configuration:
422 (++) Communication Speed
423 (++) Duty cycle
424 (++) Addressing mode
425 (++) Own Address 1
426 (++) Dual Addressing mode
427 (++) Own Address 2
428 (++) General call mode
429 (++) Nostretch mode
430
431 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
432 of the selected I2Cx peripheral.
433
434 @endverbatim
435 * @{
436 */
437
438 /**
439 * @brief Initializes the I2C according to the specified parameters
440 * in the I2C_InitTypeDef and initialize the associated handle.
441 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
442 * the configuration information for the specified I2C.
443 * @retval HAL status
444 */
HAL_I2C_Init(I2C_HandleTypeDef * hi2c)445 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
446 {
447 uint32_t freqrange;
448 uint32_t pclk1;
449
450 /* Check the I2C handle allocation */
451 if (hi2c == NULL)
452 {
453 return HAL_ERROR;
454 }
455
456 /* Check the parameters */
457 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
458 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
459 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
460 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
461 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
462 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
463 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
464 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
465 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
466
467 if (hi2c->State == HAL_I2C_STATE_RESET)
468 {
469 /* Allocate lock resource and initialize it */
470 hi2c->Lock = HAL_UNLOCKED;
471
472 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
473 /* Init the I2C Callback settings */
474 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
475 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
476 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
477 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
478 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
479 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
480 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
481 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
482 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
483 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
484
485 if (hi2c->MspInitCallback == NULL)
486 {
487 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
488 }
489
490 /* Init the low level hardware : GPIO, CLOCK, NVIC */
491 hi2c->MspInitCallback(hi2c);
492 #else
493 /* Init the low level hardware : GPIO, CLOCK, NVIC */
494 HAL_I2C_MspInit(hi2c);
495 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
496 }
497
498 hi2c->State = HAL_I2C_STATE_BUSY;
499
500 /* Disable the selected I2C peripheral */
501 __HAL_I2C_DISABLE(hi2c);
502
503 /*Reset I2C*/
504 hi2c->Instance->CR1 |= I2C_CR1_SWRST;
505 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
506
507 /* Get PCLK1 frequency */
508 pclk1 = HAL_RCC_GetPCLK1Freq();
509
510 /* Check the minimum allowed PCLK1 frequency */
511 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
512 {
513 return HAL_ERROR;
514 }
515
516 /* Calculate frequency range */
517 freqrange = I2C_FREQRANGE(pclk1);
518
519 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
520 /* Configure I2Cx: Frequency range */
521 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
522
523 /*---------------------------- I2Cx TRISE Configuration --------------------*/
524 /* Configure I2Cx: Rise Time */
525 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
526
527 /*---------------------------- I2Cx CCR Configuration ----------------------*/
528 /* Configure I2Cx: Speed */
529 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
530
531 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
532 /* Configure I2Cx: Generalcall and NoStretch mode */
533 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
534
535 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
536 /* Configure I2Cx: Own Address1 and addressing mode */
537 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
538
539 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
540 /* Configure I2Cx: Dual mode and Own Address2 */
541 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
542
543 /* Enable the selected I2C peripheral */
544 __HAL_I2C_ENABLE(hi2c);
545
546 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
547 hi2c->State = HAL_I2C_STATE_READY;
548 hi2c->PreviousState = I2C_STATE_NONE;
549 hi2c->Mode = HAL_I2C_MODE_NONE;
550
551 return HAL_OK;
552 }
553
554 /**
555 * @brief DeInitialize the I2C peripheral.
556 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
557 * the configuration information for the specified I2C.
558 * @retval HAL status
559 */
HAL_I2C_DeInit(I2C_HandleTypeDef * hi2c)560 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
561 {
562 /* Check the I2C handle allocation */
563 if (hi2c == NULL)
564 {
565 return HAL_ERROR;
566 }
567
568 /* Check the parameters */
569 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
570
571 hi2c->State = HAL_I2C_STATE_BUSY;
572
573 /* Disable the I2C Peripheral Clock */
574 __HAL_I2C_DISABLE(hi2c);
575
576 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
577 if (hi2c->MspDeInitCallback == NULL)
578 {
579 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
580 }
581
582 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
583 hi2c->MspDeInitCallback(hi2c);
584 #else
585 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
586 HAL_I2C_MspDeInit(hi2c);
587 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
588
589 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
590 hi2c->State = HAL_I2C_STATE_RESET;
591 hi2c->PreviousState = I2C_STATE_NONE;
592 hi2c->Mode = HAL_I2C_MODE_NONE;
593
594 /* Release Lock */
595 __HAL_UNLOCK(hi2c);
596
597 return HAL_OK;
598 }
599
600 /**
601 * @brief Initialize the I2C MSP.
602 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
603 * the configuration information for the specified I2C.
604 * @retval None
605 */
HAL_I2C_MspInit(I2C_HandleTypeDef * hi2c)606 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
607 {
608 /* Prevent unused argument(s) compilation warning */
609 UNUSED(hi2c);
610
611 /* NOTE : This function should not be modified, when the callback is needed,
612 the HAL_I2C_MspInit could be implemented in the user file
613 */
614 }
615
616 /**
617 * @brief DeInitialize the I2C MSP.
618 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
619 * the configuration information for the specified I2C.
620 * @retval None
621 */
HAL_I2C_MspDeInit(I2C_HandleTypeDef * hi2c)622 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
623 {
624 /* Prevent unused argument(s) compilation warning */
625 UNUSED(hi2c);
626
627 /* NOTE : This function should not be modified, when the callback is needed,
628 the HAL_I2C_MspDeInit could be implemented in the user file
629 */
630 }
631
632 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
633 /**
634 * @brief Register a User I2C Callback
635 * To be used instead of the weak predefined callback
636 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
637 * the configuration information for the specified I2C.
638 * @param CallbackID ID of the callback to be registered
639 * This parameter can be one of the following values:
640 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
641 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
642 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
643 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
644 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
645 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
646 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
647 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
648 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
649 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
650 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
651 * @param pCallback pointer to the Callback function
652 * @retval HAL status
653 */
HAL_I2C_RegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID,pI2C_CallbackTypeDef pCallback)654 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
655 {
656 HAL_StatusTypeDef status = HAL_OK;
657
658 if (pCallback == NULL)
659 {
660 /* Update the error code */
661 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
662
663 return HAL_ERROR;
664 }
665 /* Process locked */
666 __HAL_LOCK(hi2c);
667
668 if (HAL_I2C_STATE_READY == hi2c->State)
669 {
670 switch (CallbackID)
671 {
672 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
673 hi2c->MasterTxCpltCallback = pCallback;
674 break;
675
676 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
677 hi2c->MasterRxCpltCallback = pCallback;
678 break;
679
680 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
681 hi2c->SlaveTxCpltCallback = pCallback;
682 break;
683
684 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
685 hi2c->SlaveRxCpltCallback = pCallback;
686 break;
687
688 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
689 hi2c->ListenCpltCallback = pCallback;
690 break;
691
692 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
693 hi2c->MemTxCpltCallback = pCallback;
694 break;
695
696 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
697 hi2c->MemRxCpltCallback = pCallback;
698 break;
699
700 case HAL_I2C_ERROR_CB_ID :
701 hi2c->ErrorCallback = pCallback;
702 break;
703
704 case HAL_I2C_ABORT_CB_ID :
705 hi2c->AbortCpltCallback = pCallback;
706 break;
707
708 case HAL_I2C_MSPINIT_CB_ID :
709 hi2c->MspInitCallback = pCallback;
710 break;
711
712 case HAL_I2C_MSPDEINIT_CB_ID :
713 hi2c->MspDeInitCallback = pCallback;
714 break;
715
716 default :
717 /* Update the error code */
718 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
719
720 /* Return error status */
721 status = HAL_ERROR;
722 break;
723 }
724 }
725 else if (HAL_I2C_STATE_RESET == hi2c->State)
726 {
727 switch (CallbackID)
728 {
729 case HAL_I2C_MSPINIT_CB_ID :
730 hi2c->MspInitCallback = pCallback;
731 break;
732
733 case HAL_I2C_MSPDEINIT_CB_ID :
734 hi2c->MspDeInitCallback = pCallback;
735 break;
736
737 default :
738 /* Update the error code */
739 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
740
741 /* Return error status */
742 status = HAL_ERROR;
743 break;
744 }
745 }
746 else
747 {
748 /* Update the error code */
749 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
750
751 /* Return error status */
752 status = HAL_ERROR;
753 }
754
755 /* Release Lock */
756 __HAL_UNLOCK(hi2c);
757 return status;
758 }
759
760 /**
761 * @brief Unregister an I2C Callback
762 * I2C callback is redirected to the weak predefined callback
763 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
764 * the configuration information for the specified I2C.
765 * @param CallbackID ID of the callback to be unregistered
766 * This parameter can be one of the following values:
767 * This parameter can be one of the following values:
768 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID
769 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID
770 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID
771 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID
772 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID
773 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID
774 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID
775 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID
776 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID
777 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID
778 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID
779 * @retval HAL status
780 */
HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef * hi2c,HAL_I2C_CallbackIDTypeDef CallbackID)781 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)
782 {
783 HAL_StatusTypeDef status = HAL_OK;
784
785 /* Process locked */
786 __HAL_LOCK(hi2c);
787
788 if (HAL_I2C_STATE_READY == hi2c->State)
789 {
790 switch (CallbackID)
791 {
792 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :
793 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */
794 break;
795
796 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :
797 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */
798 break;
799
800 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :
801 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */
802 break;
803
804 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :
805 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */
806 break;
807
808 case HAL_I2C_LISTEN_COMPLETE_CB_ID :
809 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */
810 break;
811
812 case HAL_I2C_MEM_TX_COMPLETE_CB_ID :
813 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */
814 break;
815
816 case HAL_I2C_MEM_RX_COMPLETE_CB_ID :
817 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */
818 break;
819
820 case HAL_I2C_ERROR_CB_ID :
821 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */
822 break;
823
824 case HAL_I2C_ABORT_CB_ID :
825 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
826 break;
827
828 case HAL_I2C_MSPINIT_CB_ID :
829 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
830 break;
831
832 case HAL_I2C_MSPDEINIT_CB_ID :
833 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
834 break;
835
836 default :
837 /* Update the error code */
838 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
839
840 /* Return error status */
841 status = HAL_ERROR;
842 break;
843 }
844 }
845 else if (HAL_I2C_STATE_RESET == hi2c->State)
846 {
847 switch (CallbackID)
848 {
849 case HAL_I2C_MSPINIT_CB_ID :
850 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */
851 break;
852
853 case HAL_I2C_MSPDEINIT_CB_ID :
854 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */
855 break;
856
857 default :
858 /* Update the error code */
859 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
860
861 /* Return error status */
862 status = HAL_ERROR;
863 break;
864 }
865 }
866 else
867 {
868 /* Update the error code */
869 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
870
871 /* Return error status */
872 status = HAL_ERROR;
873 }
874
875 /* Release Lock */
876 __HAL_UNLOCK(hi2c);
877 return status;
878 }
879
880 /**
881 * @brief Register the Slave Address Match I2C Callback
882 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback
883 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
884 * the configuration information for the specified I2C.
885 * @param pCallback pointer to the Address Match Callback function
886 * @retval HAL status
887 */
HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef * hi2c,pI2C_AddrCallbackTypeDef pCallback)888 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)
889 {
890 HAL_StatusTypeDef status = HAL_OK;
891
892 if (pCallback == NULL)
893 {
894 /* Update the error code */
895 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
896
897 return HAL_ERROR;
898 }
899 /* Process locked */
900 __HAL_LOCK(hi2c);
901
902 if (HAL_I2C_STATE_READY == hi2c->State)
903 {
904 hi2c->AddrCallback = pCallback;
905 }
906 else
907 {
908 /* Update the error code */
909 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
910
911 /* Return error status */
912 status = HAL_ERROR;
913 }
914
915 /* Release Lock */
916 __HAL_UNLOCK(hi2c);
917 return status;
918 }
919
920 /**
921 * @brief UnRegister the Slave Address Match I2C Callback
922 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback
923 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
924 * the configuration information for the specified I2C.
925 * @retval HAL status
926 */
HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef * hi2c)927 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
928 {
929 HAL_StatusTypeDef status = HAL_OK;
930
931 /* Process locked */
932 __HAL_LOCK(hi2c);
933
934 if (HAL_I2C_STATE_READY == hi2c->State)
935 {
936 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */
937 }
938 else
939 {
940 /* Update the error code */
941 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;
942
943 /* Return error status */
944 status = HAL_ERROR;
945 }
946
947 /* Release Lock */
948 __HAL_UNLOCK(hi2c);
949 return status;
950 }
951
952 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
953
954 /**
955 * @brief I2C data register flush process.
956 * @param hi2c I2C handle.
957 * @retval None
958 */
I2C_Flush_DR(I2C_HandleTypeDef * hi2c)959 static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c)
960 {
961 /* Write a dummy data in DR to clear TXE flag */
962 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET)
963 {
964 hi2c->Instance->DR = 0x00U;
965 }
966 }
967
968 /**
969 * @}
970 */
971
972 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
973 * @brief Data transfers functions
974 *
975 @verbatim
976 ===============================================================================
977 ##### IO operation functions #####
978 ===============================================================================
979 [..]
980 This subsection provides a set of functions allowing to manage the I2C data
981 transfers.
982
983 (#) There are two modes of transfer:
984 (++) Blocking mode : The communication is performed in the polling mode.
985 The status of all data processing is returned by the same function
986 after finishing transfer.
987 (++) No-Blocking mode : The communication is performed using Interrupts
988 or DMA. These functions return the status of the transfer startup.
989 The end of the data processing will be indicated through the
990 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
991 using DMA mode.
992
993 (#) Blocking mode functions are :
994 (++) HAL_I2C_Master_Transmit()
995 (++) HAL_I2C_Master_Receive()
996 (++) HAL_I2C_Slave_Transmit()
997 (++) HAL_I2C_Slave_Receive()
998 (++) HAL_I2C_Mem_Write()
999 (++) HAL_I2C_Mem_Read()
1000 (++) HAL_I2C_IsDeviceReady()
1001
1002 (#) No-Blocking mode functions with Interrupt are :
1003 (++) HAL_I2C_Master_Transmit_IT()
1004 (++) HAL_I2C_Master_Receive_IT()
1005 (++) HAL_I2C_Slave_Transmit_IT()
1006 (++) HAL_I2C_Slave_Receive_IT()
1007 (++) HAL_I2C_Mem_Write_IT()
1008 (++) HAL_I2C_Mem_Read_IT()
1009 (++) HAL_I2C_Master_Seq_Transmit_IT()
1010 (++) HAL_I2C_Master_Seq_Receive_IT()
1011 (++) HAL_I2C_Slave_Seq_Transmit_IT()
1012 (++) HAL_I2C_Slave_Seq_Receive_IT()
1013 (++) HAL_I2C_EnableListen_IT()
1014 (++) HAL_I2C_DisableListen_IT()
1015 (++) HAL_I2C_Master_Abort_IT()
1016
1017 (#) No-Blocking mode functions with DMA are :
1018 (++) HAL_I2C_Master_Transmit_DMA()
1019 (++) HAL_I2C_Master_Receive_DMA()
1020 (++) HAL_I2C_Slave_Transmit_DMA()
1021 (++) HAL_I2C_Slave_Receive_DMA()
1022 (++) HAL_I2C_Mem_Write_DMA()
1023 (++) HAL_I2C_Mem_Read_DMA()
1024 (++) HAL_I2C_Master_Seq_Transmit_DMA()
1025 (++) HAL_I2C_Master_Seq_Receive_DMA()
1026 (++) HAL_I2C_Slave_Seq_Transmit_DMA()
1027 (++) HAL_I2C_Slave_Seq_Receive_DMA()
1028
1029 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
1030 (++) HAL_I2C_MasterTxCpltCallback()
1031 (++) HAL_I2C_MasterRxCpltCallback()
1032 (++) HAL_I2C_SlaveTxCpltCallback()
1033 (++) HAL_I2C_SlaveRxCpltCallback()
1034 (++) HAL_I2C_MemTxCpltCallback()
1035 (++) HAL_I2C_MemRxCpltCallback()
1036 (++) HAL_I2C_AddrCallback()
1037 (++) HAL_I2C_ListenCpltCallback()
1038 (++) HAL_I2C_ErrorCallback()
1039 (++) HAL_I2C_AbortCpltCallback()
1040
1041 @endverbatim
1042 * @{
1043 */
1044
1045 /**
1046 * @brief Transmits in master mode an amount of data in blocking mode.
1047 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1048 * the configuration information for the specified I2C.
1049 * @param DevAddress Target device address: The device 7 bits address value
1050 * in datasheet must be shifted to the left before calling the interface
1051 * @param pData Pointer to data buffer
1052 * @param Size Amount of data to be sent
1053 * @param Timeout Timeout duration
1054 * @retval HAL status
1055 */
HAL_I2C_Master_Transmit(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1056 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1057 {
1058 /* Init tickstart for timeout management*/
1059 uint32_t tickstart = HAL_GetTick();
1060
1061 if (hi2c->State == HAL_I2C_STATE_READY)
1062 {
1063 /* Wait until BUSY flag is reset */
1064 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1065 {
1066 return HAL_BUSY;
1067 }
1068
1069 /* Process Locked */
1070 __HAL_LOCK(hi2c);
1071
1072 /* Check if the I2C is already enabled */
1073 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1074 {
1075 /* Enable I2C peripheral */
1076 __HAL_I2C_ENABLE(hi2c);
1077 }
1078
1079 /* Disable Pos */
1080 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1081
1082 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1083 hi2c->Mode = HAL_I2C_MODE_MASTER;
1084 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1085
1086 /* Prepare transfer parameters */
1087 hi2c->pBuffPtr = pData;
1088 hi2c->XferCount = Size;
1089 hi2c->XferSize = hi2c->XferCount;
1090 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1091
1092 /* Send Slave Address */
1093 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1094 {
1095 return HAL_ERROR;
1096 }
1097
1098 /* Clear ADDR flag */
1099 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1100
1101 while (hi2c->XferSize > 0U)
1102 {
1103 /* Wait until TXE flag is set */
1104 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1105 {
1106 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1107 {
1108 /* Generate Stop */
1109 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1110 }
1111 return HAL_ERROR;
1112 }
1113
1114 /* Write data to DR */
1115 hi2c->Instance->DR = *hi2c->pBuffPtr;
1116
1117 /* Increment Buffer pointer */
1118 hi2c->pBuffPtr++;
1119
1120 /* Update counter */
1121 hi2c->XferCount--;
1122 hi2c->XferSize--;
1123
1124 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1125 {
1126 /* Write data to DR */
1127 hi2c->Instance->DR = *hi2c->pBuffPtr;
1128
1129 /* Increment Buffer pointer */
1130 hi2c->pBuffPtr++;
1131
1132 /* Update counter */
1133 hi2c->XferCount--;
1134 hi2c->XferSize--;
1135 }
1136
1137 /* Wait until BTF flag is set */
1138 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1139 {
1140 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1141 {
1142 /* Generate Stop */
1143 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1144 }
1145 return HAL_ERROR;
1146 }
1147 }
1148
1149 /* Generate Stop */
1150 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1151
1152 hi2c->State = HAL_I2C_STATE_READY;
1153 hi2c->Mode = HAL_I2C_MODE_NONE;
1154
1155 /* Process Unlocked */
1156 __HAL_UNLOCK(hi2c);
1157
1158 return HAL_OK;
1159 }
1160 else
1161 {
1162 return HAL_BUSY;
1163 }
1164 }
1165
1166 /**
1167 * @brief Receives in master mode an amount of data in blocking mode.
1168 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1169 * the configuration information for the specified I2C.
1170 * @param DevAddress Target device address: The device 7 bits address value
1171 * in datasheet must be shifted to the left before calling the interface
1172 * @param pData Pointer to data buffer
1173 * @param Size Amount of data to be sent
1174 * @param Timeout Timeout duration
1175 * @retval HAL status
1176 */
HAL_I2C_Master_Receive(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t Timeout)1177 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1178 {
1179 /* Init tickstart for timeout management*/
1180 uint32_t tickstart = HAL_GetTick();
1181
1182 if (hi2c->State == HAL_I2C_STATE_READY)
1183 {
1184 /* Wait until BUSY flag is reset */
1185 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
1186 {
1187 return HAL_BUSY;
1188 }
1189
1190 /* Process Locked */
1191 __HAL_LOCK(hi2c);
1192
1193 /* Check if the I2C is already enabled */
1194 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1195 {
1196 /* Enable I2C peripheral */
1197 __HAL_I2C_ENABLE(hi2c);
1198 }
1199
1200 /* Disable Pos */
1201 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1202
1203 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1204 hi2c->Mode = HAL_I2C_MODE_MASTER;
1205 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1206
1207 /* Prepare transfer parameters */
1208 hi2c->pBuffPtr = pData;
1209 hi2c->XferCount = Size;
1210 hi2c->XferSize = hi2c->XferCount;
1211 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1212
1213 /* Send Slave Address */
1214 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
1215 {
1216 return HAL_ERROR;
1217 }
1218
1219 if (hi2c->XferSize == 0U)
1220 {
1221 /* Clear ADDR flag */
1222 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1223
1224 /* Generate Stop */
1225 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1226 }
1227 else if (hi2c->XferSize == 1U)
1228 {
1229 /* Disable Acknowledge */
1230 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1231
1232 /* Clear ADDR flag */
1233 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1234
1235 /* Generate Stop */
1236 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1237 }
1238 else if (hi2c->XferSize == 2U)
1239 {
1240 /* Disable Acknowledge */
1241 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1242
1243 /* Enable Pos */
1244 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1245
1246 /* Clear ADDR flag */
1247 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1248 }
1249 else
1250 {
1251 /* Enable Acknowledge */
1252 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1253
1254 /* Clear ADDR flag */
1255 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1256 }
1257
1258 while (hi2c->XferSize > 0U)
1259 {
1260 if (hi2c->XferSize <= 3U)
1261 {
1262 /* One byte */
1263 if (hi2c->XferSize == 1U)
1264 {
1265 /* Wait until RXNE flag is set */
1266 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1267 {
1268 return HAL_ERROR;
1269 }
1270
1271 /* Read data from DR */
1272 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1273
1274 /* Increment Buffer pointer */
1275 hi2c->pBuffPtr++;
1276
1277 /* Update counter */
1278 hi2c->XferSize--;
1279 hi2c->XferCount--;
1280 }
1281 /* Two bytes */
1282 else if (hi2c->XferSize == 2U)
1283 {
1284 /* Wait until BTF flag is set */
1285 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1286 {
1287 return HAL_ERROR;
1288 }
1289
1290 /* Generate Stop */
1291 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1292
1293 /* Read data from DR */
1294 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1295
1296 /* Increment Buffer pointer */
1297 hi2c->pBuffPtr++;
1298
1299 /* Update counter */
1300 hi2c->XferSize--;
1301 hi2c->XferCount--;
1302
1303 /* Read data from DR */
1304 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1305
1306 /* Increment Buffer pointer */
1307 hi2c->pBuffPtr++;
1308
1309 /* Update counter */
1310 hi2c->XferSize--;
1311 hi2c->XferCount--;
1312 }
1313 /* 3 Last bytes */
1314 else
1315 {
1316 /* Wait until BTF flag is set */
1317 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1318 {
1319 return HAL_ERROR;
1320 }
1321
1322 /* Disable Acknowledge */
1323 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1324
1325 /* Read data from DR */
1326 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1327
1328 /* Increment Buffer pointer */
1329 hi2c->pBuffPtr++;
1330
1331 /* Update counter */
1332 hi2c->XferSize--;
1333 hi2c->XferCount--;
1334
1335 /* Wait until BTF flag is set */
1336 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
1337 {
1338 return HAL_ERROR;
1339 }
1340
1341 /* Generate Stop */
1342 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
1343
1344 /* Read data from DR */
1345 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1346
1347 /* Increment Buffer pointer */
1348 hi2c->pBuffPtr++;
1349
1350 /* Update counter */
1351 hi2c->XferSize--;
1352 hi2c->XferCount--;
1353
1354 /* Read data from DR */
1355 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1356
1357 /* Increment Buffer pointer */
1358 hi2c->pBuffPtr++;
1359
1360 /* Update counter */
1361 hi2c->XferSize--;
1362 hi2c->XferCount--;
1363 }
1364 }
1365 else
1366 {
1367 /* Wait until RXNE flag is set */
1368 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1369 {
1370 return HAL_ERROR;
1371 }
1372
1373 /* Read data from DR */
1374 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1375
1376 /* Increment Buffer pointer */
1377 hi2c->pBuffPtr++;
1378
1379 /* Update counter */
1380 hi2c->XferSize--;
1381 hi2c->XferCount--;
1382
1383 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
1384 {
1385
1386 if (hi2c->XferSize == 3U)
1387 {
1388 /* Disable Acknowledge */
1389 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1390 }
1391
1392 /* Read data from DR */
1393 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1394
1395 /* Increment Buffer pointer */
1396 hi2c->pBuffPtr++;
1397
1398 /* Update counter */
1399 hi2c->XferSize--;
1400 hi2c->XferCount--;
1401 }
1402 }
1403 }
1404
1405 hi2c->State = HAL_I2C_STATE_READY;
1406 hi2c->Mode = HAL_I2C_MODE_NONE;
1407
1408 /* Process Unlocked */
1409 __HAL_UNLOCK(hi2c);
1410
1411 return HAL_OK;
1412 }
1413 else
1414 {
1415 return HAL_BUSY;
1416 }
1417 }
1418
1419 /**
1420 * @brief Transmits in slave mode an amount of data in blocking mode.
1421 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1422 * the configuration information for the specified I2C.
1423 * @param pData Pointer to data buffer
1424 * @param Size Amount of data to be sent
1425 * @param Timeout Timeout duration
1426 * @retval HAL status
1427 */
HAL_I2C_Slave_Transmit(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1428 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1429 {
1430 /* Init tickstart for timeout management*/
1431 uint32_t tickstart = HAL_GetTick();
1432
1433 if (hi2c->State == HAL_I2C_STATE_READY)
1434 {
1435 if ((pData == NULL) || (Size == 0U))
1436 {
1437 return HAL_ERROR;
1438 }
1439
1440 /* Process Locked */
1441 __HAL_LOCK(hi2c);
1442
1443 /* Check if the I2C is already enabled */
1444 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1445 {
1446 /* Enable I2C peripheral */
1447 __HAL_I2C_ENABLE(hi2c);
1448 }
1449
1450 /* Disable Pos */
1451 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1452
1453 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1454 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1455 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1456
1457 /* Prepare transfer parameters */
1458 hi2c->pBuffPtr = pData;
1459 hi2c->XferCount = Size;
1460 hi2c->XferSize = hi2c->XferCount;
1461 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1462
1463 /* Enable Address Acknowledge */
1464 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1465
1466 /* Wait until ADDR flag is set */
1467 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1468 {
1469 return HAL_ERROR;
1470 }
1471
1472 /* Clear ADDR flag */
1473 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1474
1475 /* If 10bit addressing mode is selected */
1476 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
1477 {
1478 /* Wait until ADDR flag is set */
1479 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1480 {
1481 return HAL_ERROR;
1482 }
1483
1484 /* Clear ADDR flag */
1485 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1486 }
1487
1488 while (hi2c->XferSize > 0U)
1489 {
1490 /* Wait until TXE flag is set */
1491 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1492 {
1493 /* Disable Address Acknowledge */
1494 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1495
1496 return HAL_ERROR;
1497 }
1498
1499 /* Write data to DR */
1500 hi2c->Instance->DR = *hi2c->pBuffPtr;
1501
1502 /* Increment Buffer pointer */
1503 hi2c->pBuffPtr++;
1504
1505 /* Update counter */
1506 hi2c->XferCount--;
1507 hi2c->XferSize--;
1508
1509 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1510 {
1511 /* Write data to DR */
1512 hi2c->Instance->DR = *hi2c->pBuffPtr;
1513
1514 /* Increment Buffer pointer */
1515 hi2c->pBuffPtr++;
1516
1517 /* Update counter */
1518 hi2c->XferCount--;
1519 hi2c->XferSize--;
1520 }
1521 }
1522
1523 /* Wait until AF flag is set */
1524 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
1525 {
1526 return HAL_ERROR;
1527 }
1528
1529 /* Clear AF flag */
1530 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
1531
1532 /* Disable Address Acknowledge */
1533 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1534
1535 hi2c->State = HAL_I2C_STATE_READY;
1536 hi2c->Mode = HAL_I2C_MODE_NONE;
1537
1538 /* Process Unlocked */
1539 __HAL_UNLOCK(hi2c);
1540
1541 return HAL_OK;
1542 }
1543 else
1544 {
1545 return HAL_BUSY;
1546 }
1547 }
1548
1549 /**
1550 * @brief Receive in slave mode an amount of data in blocking mode
1551 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1552 * the configuration information for the specified I2C.
1553 * @param pData Pointer to data buffer
1554 * @param Size Amount of data to be sent
1555 * @param Timeout Timeout duration
1556 * @retval HAL status
1557 */
HAL_I2C_Slave_Receive(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t Timeout)1558 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1559 {
1560 /* Init tickstart for timeout management*/
1561 uint32_t tickstart = HAL_GetTick();
1562
1563 if (hi2c->State == HAL_I2C_STATE_READY)
1564 {
1565 if ((pData == NULL) || (Size == (uint16_t)0))
1566 {
1567 return HAL_ERROR;
1568 }
1569
1570 /* Process Locked */
1571 __HAL_LOCK(hi2c);
1572
1573 /* Check if the I2C is already enabled */
1574 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1575 {
1576 /* Enable I2C peripheral */
1577 __HAL_I2C_ENABLE(hi2c);
1578 }
1579
1580 /* Disable Pos */
1581 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1582
1583 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1584 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1585 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1586
1587 /* Prepare transfer parameters */
1588 hi2c->pBuffPtr = pData;
1589 hi2c->XferCount = Size;
1590 hi2c->XferSize = hi2c->XferCount;
1591 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1592
1593 /* Enable Address Acknowledge */
1594 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1595
1596 /* Wait until ADDR flag is set */
1597 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1598 {
1599 return HAL_ERROR;
1600 }
1601
1602 /* Clear ADDR flag */
1603 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
1604
1605 while (hi2c->XferSize > 0U)
1606 {
1607 /* Wait until RXNE flag is set */
1608 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1609 {
1610 /* Disable Address Acknowledge */
1611 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1612
1613 return HAL_ERROR;
1614 }
1615
1616 /* Read data from DR */
1617 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1618
1619 /* Increment Buffer pointer */
1620 hi2c->pBuffPtr++;
1621
1622 /* Update counter */
1623 hi2c->XferSize--;
1624 hi2c->XferCount--;
1625
1626 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
1627 {
1628 /* Read data from DR */
1629 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
1630
1631 /* Increment Buffer pointer */
1632 hi2c->pBuffPtr++;
1633
1634 /* Update counter */
1635 hi2c->XferSize--;
1636 hi2c->XferCount--;
1637 }
1638 }
1639
1640 /* Wait until STOP flag is set */
1641 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1642 {
1643 /* Disable Address Acknowledge */
1644 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1645
1646 return HAL_ERROR;
1647 }
1648
1649 /* Clear STOP flag */
1650 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
1651
1652 /* Disable Address Acknowledge */
1653 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1654
1655 hi2c->State = HAL_I2C_STATE_READY;
1656 hi2c->Mode = HAL_I2C_MODE_NONE;
1657
1658 /* Process Unlocked */
1659 __HAL_UNLOCK(hi2c);
1660
1661 return HAL_OK;
1662 }
1663 else
1664 {
1665 return HAL_BUSY;
1666 }
1667 }
1668
1669 /**
1670 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1671 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1672 * the configuration information for the specified I2C.
1673 * @param DevAddress Target device address: The device 7 bits address value
1674 * in datasheet must be shifted to the left before calling the interface
1675 * @param pData Pointer to data buffer
1676 * @param Size Amount of data to be sent
1677 * @retval HAL status
1678 */
HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1679 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1680 {
1681 __IO uint32_t count = 0U;
1682
1683 if (hi2c->State == HAL_I2C_STATE_READY)
1684 {
1685 /* Wait until BUSY flag is reset */
1686 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1687 do
1688 {
1689 count--;
1690 if (count == 0U)
1691 {
1692 hi2c->PreviousState = I2C_STATE_NONE;
1693 hi2c->State = HAL_I2C_STATE_READY;
1694 hi2c->Mode = HAL_I2C_MODE_NONE;
1695 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1696
1697 return HAL_BUSY;
1698 }
1699 }
1700 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1701
1702 /* Process Locked */
1703 __HAL_LOCK(hi2c);
1704
1705 /* Check if the I2C is already enabled */
1706 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1707 {
1708 /* Enable I2C peripheral */
1709 __HAL_I2C_ENABLE(hi2c);
1710 }
1711
1712 /* Disable Pos */
1713 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1714
1715 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1716 hi2c->Mode = HAL_I2C_MODE_MASTER;
1717 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1718
1719 /* Prepare transfer parameters */
1720 hi2c->pBuffPtr = pData;
1721 hi2c->XferCount = Size;
1722 hi2c->XferSize = hi2c->XferCount;
1723 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1724 hi2c->Devaddress = DevAddress;
1725
1726 /* Process Unlocked */
1727 __HAL_UNLOCK(hi2c);
1728
1729 /* Note : The I2C interrupts must be enabled after unlocking current process
1730 to avoid the risk of I2C interrupt handle execution before current
1731 process unlock */
1732 /* Enable EVT, BUF and ERR interrupt */
1733 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1734
1735 /* Generate Start */
1736 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1737
1738 return HAL_OK;
1739 }
1740 else
1741 {
1742 return HAL_BUSY;
1743 }
1744 }
1745
1746 /**
1747 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1748 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1749 * the configuration information for the specified I2C.
1750 * @param DevAddress Target device address: The device 7 bits address value
1751 * in datasheet must be shifted to the left before calling the interface
1752 * @param pData Pointer to data buffer
1753 * @param Size Amount of data to be sent
1754 * @retval HAL status
1755 */
HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1756 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1757 {
1758 __IO uint32_t count = 0U;
1759
1760 if (hi2c->State == HAL_I2C_STATE_READY)
1761 {
1762 /* Wait until BUSY flag is reset */
1763 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1764 do
1765 {
1766 count--;
1767 if (count == 0U)
1768 {
1769 hi2c->PreviousState = I2C_STATE_NONE;
1770 hi2c->State = HAL_I2C_STATE_READY;
1771 hi2c->Mode = HAL_I2C_MODE_NONE;
1772 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1773
1774 return HAL_BUSY;
1775 }
1776 }
1777 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1778
1779 /* Process Locked */
1780 __HAL_LOCK(hi2c);
1781
1782 /* Check if the I2C is already enabled */
1783 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1784 {
1785 /* Enable I2C peripheral */
1786 __HAL_I2C_ENABLE(hi2c);
1787 }
1788
1789 /* Disable Pos */
1790 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1791
1792 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1793 hi2c->Mode = HAL_I2C_MODE_MASTER;
1794 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1795
1796 /* Prepare transfer parameters */
1797 hi2c->pBuffPtr = pData;
1798 hi2c->XferCount = Size;
1799 hi2c->XferSize = hi2c->XferCount;
1800 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1801 hi2c->Devaddress = DevAddress;
1802
1803
1804 /* Process Unlocked */
1805 __HAL_UNLOCK(hi2c);
1806
1807 /* Note : The I2C interrupts must be enabled after unlocking current process
1808 to avoid the risk of I2C interrupt handle execution before current
1809 process unlock */
1810
1811 /* Enable EVT, BUF and ERR interrupt */
1812 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1813
1814 /* Enable Acknowledge */
1815 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1816
1817 /* Generate Start */
1818 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
1819
1820 return HAL_OK;
1821 }
1822 else
1823 {
1824 return HAL_BUSY;
1825 }
1826 }
1827
1828 /**
1829 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1830 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1831 * the configuration information for the specified I2C.
1832 * @param pData Pointer to data buffer
1833 * @param Size Amount of data to be sent
1834 * @retval HAL status
1835 */
HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1836 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1837 {
1838
1839 if (hi2c->State == HAL_I2C_STATE_READY)
1840 {
1841 if ((pData == NULL) || (Size == 0U))
1842 {
1843 return HAL_ERROR;
1844 }
1845
1846 /* Process Locked */
1847 __HAL_LOCK(hi2c);
1848
1849 /* Check if the I2C is already enabled */
1850 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1851 {
1852 /* Enable I2C peripheral */
1853 __HAL_I2C_ENABLE(hi2c);
1854 }
1855
1856 /* Disable Pos */
1857 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1858
1859 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1860 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1861 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1862
1863 /* Prepare transfer parameters */
1864 hi2c->pBuffPtr = pData;
1865 hi2c->XferCount = Size;
1866 hi2c->XferSize = hi2c->XferCount;
1867 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1868
1869 /* Enable Address Acknowledge */
1870 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1871
1872 /* Process Unlocked */
1873 __HAL_UNLOCK(hi2c);
1874
1875 /* Note : The I2C interrupts must be enabled after unlocking current process
1876 to avoid the risk of I2C interrupt handle execution before current
1877 process unlock */
1878
1879 /* Enable EVT, BUF and ERR interrupt */
1880 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1881
1882 return HAL_OK;
1883 }
1884 else
1885 {
1886 return HAL_BUSY;
1887 }
1888 }
1889
1890 /**
1891 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1892 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1893 * the configuration information for the specified I2C.
1894 * @param pData Pointer to data buffer
1895 * @param Size Amount of data to be sent
1896 * @retval HAL status
1897 */
HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)1898 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1899 {
1900
1901 if (hi2c->State == HAL_I2C_STATE_READY)
1902 {
1903 if ((pData == NULL) || (Size == 0U))
1904 {
1905 return HAL_ERROR;
1906 }
1907
1908 /* Process Locked */
1909 __HAL_LOCK(hi2c);
1910
1911 /* Check if the I2C is already enabled */
1912 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1913 {
1914 /* Enable I2C peripheral */
1915 __HAL_I2C_ENABLE(hi2c);
1916 }
1917
1918 /* Disable Pos */
1919 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1920
1921 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1922 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1923 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1924
1925 /* Prepare transfer parameters */
1926 hi2c->pBuffPtr = pData;
1927 hi2c->XferCount = Size;
1928 hi2c->XferSize = hi2c->XferCount;
1929 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1930
1931 /* Enable Address Acknowledge */
1932 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
1933
1934 /* Process Unlocked */
1935 __HAL_UNLOCK(hi2c);
1936
1937 /* Note : The I2C interrupts must be enabled after unlocking current process
1938 to avoid the risk of I2C interrupt handle execution before current
1939 process unlock */
1940
1941 /* Enable EVT, BUF and ERR interrupt */
1942 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
1943
1944 return HAL_OK;
1945 }
1946 else
1947 {
1948 return HAL_BUSY;
1949 }
1950 }
1951
1952 /**
1953 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1954 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1955 * the configuration information for the specified I2C.
1956 * @param DevAddress Target device address: The device 7 bits address value
1957 * in datasheet must be shifted to the left before calling the interface
1958 * @param pData Pointer to data buffer
1959 * @param Size Amount of data to be sent
1960 * @retval HAL status
1961 */
HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)1962 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1963 {
1964 __IO uint32_t count = 0U;
1965 HAL_StatusTypeDef dmaxferstatus;
1966
1967 if (hi2c->State == HAL_I2C_STATE_READY)
1968 {
1969 /* Wait until BUSY flag is reset */
1970 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
1971 do
1972 {
1973 count--;
1974 if (count == 0U)
1975 {
1976 hi2c->PreviousState = I2C_STATE_NONE;
1977 hi2c->State = HAL_I2C_STATE_READY;
1978 hi2c->Mode = HAL_I2C_MODE_NONE;
1979 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
1980
1981 return HAL_BUSY;
1982 }
1983 }
1984 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
1985
1986 /* Process Locked */
1987 __HAL_LOCK(hi2c);
1988
1989 /* Check if the I2C is already enabled */
1990 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
1991 {
1992 /* Enable I2C peripheral */
1993 __HAL_I2C_ENABLE(hi2c);
1994 }
1995
1996 /* Disable Pos */
1997 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
1998
1999 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2000 hi2c->Mode = HAL_I2C_MODE_MASTER;
2001 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2002
2003 /* Prepare transfer parameters */
2004 hi2c->pBuffPtr = pData;
2005 hi2c->XferCount = Size;
2006 hi2c->XferSize = hi2c->XferCount;
2007 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2008 hi2c->Devaddress = DevAddress;
2009
2010 if (hi2c->XferSize > 0U)
2011 {
2012 if (hi2c->hdmatx != NULL)
2013 {
2014 /* Set the I2C DMA transfer complete callback */
2015 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2016
2017 /* Set the DMA error callback */
2018 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2019
2020 /* Set the unused DMA callbacks to NULL */
2021 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2022 hi2c->hdmatx->XferAbortCallback = NULL;
2023
2024 /* Enable the DMA channel */
2025 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2026 }
2027 else
2028 {
2029 /* Update I2C state */
2030 hi2c->State = HAL_I2C_STATE_READY;
2031 hi2c->Mode = HAL_I2C_MODE_NONE;
2032
2033 /* Update I2C error code */
2034 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2035
2036 /* Process Unlocked */
2037 __HAL_UNLOCK(hi2c);
2038
2039 return HAL_ERROR;
2040 }
2041
2042 if (dmaxferstatus == HAL_OK)
2043 {
2044 /* Process Unlocked */
2045 __HAL_UNLOCK(hi2c);
2046
2047 /* Note : The I2C interrupts must be enabled after unlocking current process
2048 to avoid the risk of I2C interrupt handle execution before current
2049 process unlock */
2050
2051 /* Enable EVT and ERR interrupt */
2052 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2053
2054 /* Enable DMA Request */
2055 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2056
2057 /* Enable Acknowledge */
2058 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2059
2060 /* Generate Start */
2061 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2062 }
2063 else
2064 {
2065 /* Update I2C state */
2066 hi2c->State = HAL_I2C_STATE_READY;
2067 hi2c->Mode = HAL_I2C_MODE_NONE;
2068
2069 /* Update I2C error code */
2070 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2071
2072 /* Process Unlocked */
2073 __HAL_UNLOCK(hi2c);
2074
2075 return HAL_ERROR;
2076 }
2077 }
2078 else
2079 {
2080 /* Enable Acknowledge */
2081 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2082
2083 /* Generate Start */
2084 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2085
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hi2c);
2088
2089 /* Note : The I2C interrupts must be enabled after unlocking current process
2090 to avoid the risk of I2C interrupt handle execution before current
2091 process unlock */
2092
2093 /* Enable EVT, BUF and ERR interrupt */
2094 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2095 }
2096
2097 return HAL_OK;
2098 }
2099 else
2100 {
2101 return HAL_BUSY;
2102 }
2103 }
2104
2105 /**
2106 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
2107 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2108 * the configuration information for the specified I2C.
2109 * @param DevAddress Target device address: The device 7 bits address value
2110 * in datasheet must be shifted to the left before calling the interface
2111 * @param pData Pointer to data buffer
2112 * @param Size Amount of data to be sent
2113 * @retval HAL status
2114 */
HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size)2115 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
2116 {
2117 __IO uint32_t count = 0U;
2118 HAL_StatusTypeDef dmaxferstatus;
2119
2120 if (hi2c->State == HAL_I2C_STATE_READY)
2121 {
2122 /* Wait until BUSY flag is reset */
2123 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2124 do
2125 {
2126 count--;
2127 if (count == 0U)
2128 {
2129 hi2c->PreviousState = I2C_STATE_NONE;
2130 hi2c->State = HAL_I2C_STATE_READY;
2131 hi2c->Mode = HAL_I2C_MODE_NONE;
2132 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2133
2134 return HAL_BUSY;
2135 }
2136 }
2137 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2138
2139 /* Process Locked */
2140 __HAL_LOCK(hi2c);
2141
2142 /* Check if the I2C is already enabled */
2143 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2144 {
2145 /* Enable I2C peripheral */
2146 __HAL_I2C_ENABLE(hi2c);
2147 }
2148
2149 /* Disable Pos */
2150 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2151
2152 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2153 hi2c->Mode = HAL_I2C_MODE_MASTER;
2154 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2155
2156 /* Prepare transfer parameters */
2157 hi2c->pBuffPtr = pData;
2158 hi2c->XferCount = Size;
2159 hi2c->XferSize = hi2c->XferCount;
2160 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2161 hi2c->Devaddress = DevAddress;
2162
2163 if (hi2c->XferSize > 0U)
2164 {
2165 if (hi2c->hdmarx != NULL)
2166 {
2167 /* Set the I2C DMA transfer complete callback */
2168 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2169
2170 /* Set the DMA error callback */
2171 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2172
2173 /* Set the unused DMA callbacks to NULL */
2174 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2175 hi2c->hdmarx->XferAbortCallback = NULL;
2176
2177 /* Enable the DMA channel */
2178 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2179 }
2180 else
2181 {
2182 /* Update I2C state */
2183 hi2c->State = HAL_I2C_STATE_READY;
2184 hi2c->Mode = HAL_I2C_MODE_NONE;
2185
2186 /* Update I2C error code */
2187 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2188
2189 /* Process Unlocked */
2190 __HAL_UNLOCK(hi2c);
2191
2192 return HAL_ERROR;
2193 }
2194
2195 if (dmaxferstatus == HAL_OK)
2196 {
2197 /* Enable Acknowledge */
2198 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2199
2200 /* Generate Start */
2201 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2202
2203 /* Process Unlocked */
2204 __HAL_UNLOCK(hi2c);
2205
2206 /* Note : The I2C interrupts must be enabled after unlocking current process
2207 to avoid the risk of I2C interrupt handle execution before current
2208 process unlock */
2209
2210 /* Enable EVT and ERR interrupt */
2211 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2212
2213 /* Enable DMA Request */
2214 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2215 }
2216 else
2217 {
2218 /* Update I2C state */
2219 hi2c->State = HAL_I2C_STATE_READY;
2220 hi2c->Mode = HAL_I2C_MODE_NONE;
2221
2222 /* Update I2C error code */
2223 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2224
2225 /* Process Unlocked */
2226 __HAL_UNLOCK(hi2c);
2227
2228 return HAL_ERROR;
2229 }
2230 }
2231 else
2232 {
2233 /* Process Unlocked */
2234 __HAL_UNLOCK(hi2c);
2235
2236 /* Note : The I2C interrupts must be enabled after unlocking current process
2237 to avoid the risk of I2C interrupt handle execution before current
2238 process unlock */
2239
2240 /* Enable EVT, BUF and ERR interrupt */
2241 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2242
2243 /* Enable Acknowledge */
2244 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2245
2246 /* Generate Start */
2247 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2248 }
2249
2250 return HAL_OK;
2251 }
2252 else
2253 {
2254 return HAL_BUSY;
2255 }
2256 }
2257
2258 /**
2259 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
2260 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2261 * the configuration information for the specified I2C.
2262 * @param pData Pointer to data buffer
2263 * @param Size Amount of data to be sent
2264 * @retval HAL status
2265 */
HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2266 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2267 {
2268 HAL_StatusTypeDef dmaxferstatus;
2269
2270 if (hi2c->State == HAL_I2C_STATE_READY)
2271 {
2272 if ((pData == NULL) || (Size == 0U))
2273 {
2274 return HAL_ERROR;
2275 }
2276
2277 /* Process Locked */
2278 __HAL_LOCK(hi2c);
2279
2280 /* Check if the I2C is already enabled */
2281 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2282 {
2283 /* Enable I2C peripheral */
2284 __HAL_I2C_ENABLE(hi2c);
2285 }
2286
2287 /* Disable Pos */
2288 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2289
2290 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2291 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2292 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2293
2294 /* Prepare transfer parameters */
2295 hi2c->pBuffPtr = pData;
2296 hi2c->XferCount = Size;
2297 hi2c->XferSize = hi2c->XferCount;
2298 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2299
2300 if (hi2c->hdmatx != NULL)
2301 {
2302 /* Set the I2C DMA transfer complete callback */
2303 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
2304
2305 /* Set the DMA error callback */
2306 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2307
2308 /* Set the unused DMA callbacks to NULL */
2309 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2310 hi2c->hdmatx->XferAbortCallback = NULL;
2311
2312 /* Enable the DMA channel */
2313 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
2314 }
2315 else
2316 {
2317 /* Update I2C state */
2318 hi2c->State = HAL_I2C_STATE_LISTEN;
2319 hi2c->Mode = HAL_I2C_MODE_NONE;
2320
2321 /* Update I2C error code */
2322 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2323
2324 /* Process Unlocked */
2325 __HAL_UNLOCK(hi2c);
2326
2327 return HAL_ERROR;
2328 }
2329
2330 if (dmaxferstatus == HAL_OK)
2331 {
2332 /* Enable Address Acknowledge */
2333 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2334
2335 /* Process Unlocked */
2336 __HAL_UNLOCK(hi2c);
2337
2338 /* Note : The I2C interrupts must be enabled after unlocking current process
2339 to avoid the risk of I2C interrupt handle execution before current
2340 process unlock */
2341 /* Enable EVT and ERR interrupt */
2342 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2343
2344 /* Enable DMA Request */
2345 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
2346
2347 return HAL_OK;
2348 }
2349 else
2350 {
2351 /* Update I2C state */
2352 hi2c->State = HAL_I2C_STATE_READY;
2353 hi2c->Mode = HAL_I2C_MODE_NONE;
2354
2355 /* Update I2C error code */
2356 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2357
2358 /* Process Unlocked */
2359 __HAL_UNLOCK(hi2c);
2360
2361 return HAL_ERROR;
2362 }
2363 }
2364 else
2365 {
2366 return HAL_BUSY;
2367 }
2368 }
2369
2370 /**
2371 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
2372 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2373 * the configuration information for the specified I2C.
2374 * @param pData Pointer to data buffer
2375 * @param Size Amount of data to be sent
2376 * @retval HAL status
2377 */
HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size)2378 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
2379 {
2380 HAL_StatusTypeDef dmaxferstatus;
2381
2382 if (hi2c->State == HAL_I2C_STATE_READY)
2383 {
2384 if ((pData == NULL) || (Size == 0U))
2385 {
2386 return HAL_ERROR;
2387 }
2388
2389 /* Process Locked */
2390 __HAL_LOCK(hi2c);
2391
2392 /* Check if the I2C is already enabled */
2393 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2394 {
2395 /* Enable I2C peripheral */
2396 __HAL_I2C_ENABLE(hi2c);
2397 }
2398
2399 /* Disable Pos */
2400 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2401
2402 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2403 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2404 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2405
2406 /* Prepare transfer parameters */
2407 hi2c->pBuffPtr = pData;
2408 hi2c->XferCount = Size;
2409 hi2c->XferSize = hi2c->XferCount;
2410 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2411
2412 if (hi2c->hdmarx != NULL)
2413 {
2414 /* Set the I2C DMA transfer complete callback */
2415 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
2416
2417 /* Set the DMA error callback */
2418 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2419
2420 /* Set the unused DMA callbacks to NULL */
2421 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2422 hi2c->hdmarx->XferAbortCallback = NULL;
2423
2424 /* Enable the DMA channel */
2425 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
2426 }
2427 else
2428 {
2429 /* Update I2C state */
2430 hi2c->State = HAL_I2C_STATE_LISTEN;
2431 hi2c->Mode = HAL_I2C_MODE_NONE;
2432
2433 /* Update I2C error code */
2434 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
2435
2436 /* Process Unlocked */
2437 __HAL_UNLOCK(hi2c);
2438
2439 return HAL_ERROR;
2440 }
2441
2442 if (dmaxferstatus == HAL_OK)
2443 {
2444 /* Enable Address Acknowledge */
2445 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2446
2447 /* Process Unlocked */
2448 __HAL_UNLOCK(hi2c);
2449
2450 /* Note : The I2C interrupts must be enabled after unlocking current process
2451 to avoid the risk of I2C interrupt handle execution before current
2452 process unlock */
2453 /* Enable EVT and ERR interrupt */
2454 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
2455
2456 /* Enable DMA Request */
2457 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
2458
2459 return HAL_OK;
2460 }
2461 else
2462 {
2463 /* Update I2C state */
2464 hi2c->State = HAL_I2C_STATE_READY;
2465 hi2c->Mode = HAL_I2C_MODE_NONE;
2466
2467 /* Update I2C error code */
2468 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
2469
2470 /* Process Unlocked */
2471 __HAL_UNLOCK(hi2c);
2472
2473 return HAL_ERROR;
2474 }
2475 }
2476 else
2477 {
2478 return HAL_BUSY;
2479 }
2480 }
2481
2482 /**
2483 * @brief Write an amount of data in blocking mode to a specific memory address
2484 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2485 * the configuration information for the specified I2C.
2486 * @param DevAddress Target device address: The device 7 bits address value
2487 * in datasheet must be shifted to the left before calling the interface
2488 * @param MemAddress Internal memory address
2489 * @param MemAddSize Size of internal memory address
2490 * @param pData Pointer to data buffer
2491 * @param Size Amount of data to be sent
2492 * @param Timeout Timeout duration
2493 * @retval HAL status
2494 */
HAL_I2C_Mem_Write(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2495 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2496 {
2497 /* Init tickstart for timeout management*/
2498 uint32_t tickstart = HAL_GetTick();
2499
2500 /* Check the parameters */
2501 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2502
2503 if (hi2c->State == HAL_I2C_STATE_READY)
2504 {
2505 /* Wait until BUSY flag is reset */
2506 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2507 {
2508 return HAL_BUSY;
2509 }
2510
2511 /* Process Locked */
2512 __HAL_LOCK(hi2c);
2513
2514 /* Check if the I2C is already enabled */
2515 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2516 {
2517 /* Enable I2C peripheral */
2518 __HAL_I2C_ENABLE(hi2c);
2519 }
2520
2521 /* Disable Pos */
2522 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2523
2524 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2525 hi2c->Mode = HAL_I2C_MODE_MEM;
2526 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2527
2528 /* Prepare transfer parameters */
2529 hi2c->pBuffPtr = pData;
2530 hi2c->XferCount = Size;
2531 hi2c->XferSize = hi2c->XferCount;
2532 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2533
2534 /* Send Slave Address and Memory Address */
2535 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2536 {
2537 return HAL_ERROR;
2538 }
2539
2540 while (hi2c->XferSize > 0U)
2541 {
2542 /* Wait until TXE flag is set */
2543 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2544 {
2545 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2546 {
2547 /* Generate Stop */
2548 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2549 }
2550 return HAL_ERROR;
2551 }
2552
2553 /* Write data to DR */
2554 hi2c->Instance->DR = *hi2c->pBuffPtr;
2555
2556 /* Increment Buffer pointer */
2557 hi2c->pBuffPtr++;
2558
2559 /* Update counter */
2560 hi2c->XferSize--;
2561 hi2c->XferCount--;
2562
2563 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
2564 {
2565 /* Write data to DR */
2566 hi2c->Instance->DR = *hi2c->pBuffPtr;
2567
2568 /* Increment Buffer pointer */
2569 hi2c->pBuffPtr++;
2570
2571 /* Update counter */
2572 hi2c->XferSize--;
2573 hi2c->XferCount--;
2574 }
2575 }
2576
2577 /* Wait until BTF flag is set */
2578 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2579 {
2580 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2581 {
2582 /* Generate Stop */
2583 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2584 }
2585 return HAL_ERROR;
2586 }
2587
2588 /* Generate Stop */
2589 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2590
2591 hi2c->State = HAL_I2C_STATE_READY;
2592 hi2c->Mode = HAL_I2C_MODE_NONE;
2593
2594 /* Process Unlocked */
2595 __HAL_UNLOCK(hi2c);
2596
2597 return HAL_OK;
2598 }
2599 else
2600 {
2601 return HAL_BUSY;
2602 }
2603 }
2604
2605 /**
2606 * @brief Read an amount of data in blocking mode from a specific memory address
2607 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2608 * the configuration information for the specified I2C.
2609 * @param DevAddress Target device address: The device 7 bits address value
2610 * in datasheet must be shifted to the left before calling the interface
2611 * @param MemAddress Internal memory address
2612 * @param MemAddSize Size of internal memory address
2613 * @param pData Pointer to data buffer
2614 * @param Size Amount of data to be sent
2615 * @param Timeout Timeout duration
2616 * @retval HAL status
2617 */
HAL_I2C_Mem_Read(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size,uint32_t Timeout)2618 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
2619 {
2620 /* Init tickstart for timeout management*/
2621 uint32_t tickstart = HAL_GetTick();
2622
2623 /* Check the parameters */
2624 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2625
2626 if (hi2c->State == HAL_I2C_STATE_READY)
2627 {
2628 /* Wait until BUSY flag is reset */
2629 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
2630 {
2631 return HAL_BUSY;
2632 }
2633
2634 /* Process Locked */
2635 __HAL_LOCK(hi2c);
2636
2637 /* Check if the I2C is already enabled */
2638 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2639 {
2640 /* Enable I2C peripheral */
2641 __HAL_I2C_ENABLE(hi2c);
2642 }
2643
2644 /* Disable Pos */
2645 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2646
2647 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2648 hi2c->Mode = HAL_I2C_MODE_MEM;
2649 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2650
2651 /* Prepare transfer parameters */
2652 hi2c->pBuffPtr = pData;
2653 hi2c->XferCount = Size;
2654 hi2c->XferSize = hi2c->XferCount;
2655 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2656
2657 /* Send Slave Address and Memory Address */
2658 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
2659 {
2660 return HAL_ERROR;
2661 }
2662
2663 if (hi2c->XferSize == 0U)
2664 {
2665 /* Clear ADDR flag */
2666 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2667
2668 /* Generate Stop */
2669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2670 }
2671 else if (hi2c->XferSize == 1U)
2672 {
2673 /* Disable Acknowledge */
2674 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2675
2676 /* Clear ADDR flag */
2677 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2678
2679 /* Generate Stop */
2680 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2681 }
2682 else if (hi2c->XferSize == 2U)
2683 {
2684 /* Disable Acknowledge */
2685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2686
2687 /* Enable Pos */
2688 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2689
2690 /* Clear ADDR flag */
2691 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2692 }
2693 else
2694 {
2695 /* Clear ADDR flag */
2696 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
2697 }
2698
2699 while (hi2c->XferSize > 0U)
2700 {
2701 if (hi2c->XferSize <= 3U)
2702 {
2703 /* One byte */
2704 if (hi2c->XferSize == 1U)
2705 {
2706 /* Wait until RXNE flag is set */
2707 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2708 {
2709 return HAL_ERROR;
2710 }
2711
2712 /* Read data from DR */
2713 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2714
2715 /* Increment Buffer pointer */
2716 hi2c->pBuffPtr++;
2717
2718 /* Update counter */
2719 hi2c->XferSize--;
2720 hi2c->XferCount--;
2721 }
2722 /* Two bytes */
2723 else if (hi2c->XferSize == 2U)
2724 {
2725 /* Wait until BTF flag is set */
2726 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2727 {
2728 return HAL_ERROR;
2729 }
2730
2731 /* Generate Stop */
2732 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2733
2734 /* Read data from DR */
2735 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2736
2737 /* Increment Buffer pointer */
2738 hi2c->pBuffPtr++;
2739
2740 /* Update counter */
2741 hi2c->XferSize--;
2742 hi2c->XferCount--;
2743
2744 /* Read data from DR */
2745 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2746
2747 /* Increment Buffer pointer */
2748 hi2c->pBuffPtr++;
2749
2750 /* Update counter */
2751 hi2c->XferSize--;
2752 hi2c->XferCount--;
2753 }
2754 /* 3 Last bytes */
2755 else
2756 {
2757 /* Wait until BTF flag is set */
2758 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2759 {
2760 return HAL_ERROR;
2761 }
2762
2763 /* Disable Acknowledge */
2764 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
2765
2766 /* Read data from DR */
2767 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2768
2769 /* Increment Buffer pointer */
2770 hi2c->pBuffPtr++;
2771
2772 /* Update counter */
2773 hi2c->XferSize--;
2774 hi2c->XferCount--;
2775
2776 /* Wait until BTF flag is set */
2777 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
2778 {
2779 return HAL_ERROR;
2780 }
2781
2782 /* Generate Stop */
2783 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
2784
2785 /* Read data from DR */
2786 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2787
2788 /* Increment Buffer pointer */
2789 hi2c->pBuffPtr++;
2790
2791 /* Update counter */
2792 hi2c->XferSize--;
2793 hi2c->XferCount--;
2794
2795 /* Read data from DR */
2796 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2797
2798 /* Increment Buffer pointer */
2799 hi2c->pBuffPtr++;
2800
2801 /* Update counter */
2802 hi2c->XferSize--;
2803 hi2c->XferCount--;
2804 }
2805 }
2806 else
2807 {
2808 /* Wait until RXNE flag is set */
2809 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
2810 {
2811 return HAL_ERROR;
2812 }
2813
2814 /* Read data from DR */
2815 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2816
2817 /* Increment Buffer pointer */
2818 hi2c->pBuffPtr++;
2819
2820 /* Update counter */
2821 hi2c->XferSize--;
2822 hi2c->XferCount--;
2823
2824 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
2825 {
2826 /* Read data from DR */
2827 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
2828
2829 /* Increment Buffer pointer */
2830 hi2c->pBuffPtr++;
2831
2832 /* Update counter */
2833 hi2c->XferSize--;
2834 hi2c->XferCount--;
2835 }
2836 }
2837 }
2838
2839 hi2c->State = HAL_I2C_STATE_READY;
2840 hi2c->Mode = HAL_I2C_MODE_NONE;
2841
2842 /* Process Unlocked */
2843 __HAL_UNLOCK(hi2c);
2844
2845 return HAL_OK;
2846 }
2847 else
2848 {
2849 return HAL_BUSY;
2850 }
2851 }
2852
2853 /**
2854 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2855 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2856 * the configuration information for the specified I2C.
2857 * @param DevAddress Target device address: The device 7 bits address value
2858 * in datasheet must be shifted to the left before calling the interface
2859 * @param MemAddress Internal memory address
2860 * @param MemAddSize Size of internal memory address
2861 * @param pData Pointer to data buffer
2862 * @param Size Amount of data to be sent
2863 * @retval HAL status
2864 */
HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2865 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2866 {
2867 __IO uint32_t count = 0U;
2868
2869 /* Check the parameters */
2870 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2871
2872 if (hi2c->State == HAL_I2C_STATE_READY)
2873 {
2874 /* Wait until BUSY flag is reset */
2875 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2876 do
2877 {
2878 count--;
2879 if (count == 0U)
2880 {
2881 hi2c->PreviousState = I2C_STATE_NONE;
2882 hi2c->State = HAL_I2C_STATE_READY;
2883 hi2c->Mode = HAL_I2C_MODE_NONE;
2884 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2885
2886 return HAL_BUSY;
2887 }
2888 }
2889 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2890
2891 /* Process Locked */
2892 __HAL_LOCK(hi2c);
2893
2894 /* Check if the I2C is already enabled */
2895 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2896 {
2897 /* Enable I2C peripheral */
2898 __HAL_I2C_ENABLE(hi2c);
2899 }
2900
2901 /* Disable Pos */
2902 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2903
2904 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2905 hi2c->Mode = HAL_I2C_MODE_MEM;
2906 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2907
2908 /* Prepare transfer parameters */
2909 hi2c->pBuffPtr = pData;
2910 hi2c->XferCount = Size;
2911 hi2c->XferSize = hi2c->XferCount;
2912 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2913 hi2c->Devaddress = DevAddress;
2914 hi2c->Memaddress = MemAddress;
2915 hi2c->MemaddSize = MemAddSize;
2916 hi2c->EventCount = 0U;
2917
2918 /* Generate Start */
2919 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
2920
2921 /* Process Unlocked */
2922 __HAL_UNLOCK(hi2c);
2923
2924 /* Note : The I2C interrupts must be enabled after unlocking current process
2925 to avoid the risk of I2C interrupt handle execution before current
2926 process unlock */
2927
2928 /* Enable EVT, BUF and ERR interrupt */
2929 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
2930
2931 return HAL_OK;
2932 }
2933 else
2934 {
2935 return HAL_BUSY;
2936 }
2937 }
2938
2939 /**
2940 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2941 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2942 * the configuration information for the specified I2C.
2943 * @param DevAddress Target device address
2944 * @param MemAddress Internal memory address
2945 * @param MemAddSize Size of internal memory address
2946 * @param pData Pointer to data buffer
2947 * @param Size Amount of data to be sent
2948 * @retval HAL status
2949 */
HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)2950 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2951 {
2952 __IO uint32_t count = 0U;
2953
2954 /* Check the parameters */
2955 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2956
2957 if (hi2c->State == HAL_I2C_STATE_READY)
2958 {
2959 /* Wait until BUSY flag is reset */
2960 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
2961 do
2962 {
2963 count--;
2964 if (count == 0U)
2965 {
2966 hi2c->PreviousState = I2C_STATE_NONE;
2967 hi2c->State = HAL_I2C_STATE_READY;
2968 hi2c->Mode = HAL_I2C_MODE_NONE;
2969 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
2970
2971 return HAL_BUSY;
2972 }
2973 }
2974 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
2975
2976 /* Process Locked */
2977 __HAL_LOCK(hi2c);
2978
2979 /* Check if the I2C is already enabled */
2980 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
2981 {
2982 /* Enable I2C peripheral */
2983 __HAL_I2C_ENABLE(hi2c);
2984 }
2985
2986 /* Disable Pos */
2987 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
2988
2989 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2990 hi2c->Mode = HAL_I2C_MODE_MEM;
2991 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2992
2993 /* Prepare transfer parameters */
2994 hi2c->pBuffPtr = pData;
2995 hi2c->XferCount = Size;
2996 hi2c->XferSize = hi2c->XferCount;
2997 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2998 hi2c->Devaddress = DevAddress;
2999 hi2c->Memaddress = MemAddress;
3000 hi2c->MemaddSize = MemAddSize;
3001 hi2c->EventCount = 0U;
3002
3003 /* Enable Acknowledge */
3004 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3005
3006 /* Generate Start */
3007 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3008
3009 /* Process Unlocked */
3010 __HAL_UNLOCK(hi2c);
3011
3012 if (hi2c->XferSize > 0U)
3013 {
3014 /* Note : The I2C interrupts must be enabled after unlocking current process
3015 to avoid the risk of I2C interrupt handle execution before current
3016 process unlock */
3017
3018 /* Enable EVT, BUF and ERR interrupt */
3019 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3020 }
3021 return HAL_OK;
3022 }
3023 else
3024 {
3025 return HAL_BUSY;
3026 }
3027 }
3028
3029 /**
3030 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
3031 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3032 * the configuration information for the specified I2C.
3033 * @param DevAddress Target device address: The device 7 bits address value
3034 * in datasheet must be shifted to the left before calling the interface
3035 * @param MemAddress Internal memory address
3036 * @param MemAddSize Size of internal memory address
3037 * @param pData Pointer to data buffer
3038 * @param Size Amount of data to be sent
3039 * @retval HAL status
3040 */
HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3041 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3042 {
3043 __IO uint32_t count = 0U;
3044 HAL_StatusTypeDef dmaxferstatus;
3045
3046 /* Init tickstart for timeout management*/
3047 uint32_t tickstart = HAL_GetTick();
3048
3049 /* Check the parameters */
3050 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3051
3052 if (hi2c->State == HAL_I2C_STATE_READY)
3053 {
3054 /* Wait until BUSY flag is reset */
3055 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3056 do
3057 {
3058 count--;
3059 if (count == 0U)
3060 {
3061 hi2c->PreviousState = I2C_STATE_NONE;
3062 hi2c->State = HAL_I2C_STATE_READY;
3063 hi2c->Mode = HAL_I2C_MODE_NONE;
3064 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3065
3066 return HAL_BUSY;
3067 }
3068 }
3069 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3070
3071 /* Process Locked */
3072 __HAL_LOCK(hi2c);
3073
3074 /* Check if the I2C is already enabled */
3075 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3076 {
3077 /* Enable I2C peripheral */
3078 __HAL_I2C_ENABLE(hi2c);
3079 }
3080
3081 /* Disable Pos */
3082 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3083
3084 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3085 hi2c->Mode = HAL_I2C_MODE_MEM;
3086 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3087
3088 /* Prepare transfer parameters */
3089 hi2c->pBuffPtr = pData;
3090 hi2c->XferCount = Size;
3091 hi2c->XferSize = hi2c->XferCount;
3092 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3093 hi2c->Devaddress = DevAddress;
3094 hi2c->Memaddress = MemAddress;
3095 hi2c->MemaddSize = MemAddSize;
3096 hi2c->EventCount = 0U;
3097
3098 if (hi2c->XferSize > 0U)
3099 {
3100 if (hi2c->hdmatx != NULL)
3101 {
3102 /* Set the I2C DMA transfer complete callback */
3103 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3104
3105 /* Set the DMA error callback */
3106 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3107
3108 /* Set the unused DMA callbacks to NULL */
3109 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3110 hi2c->hdmatx->XferAbortCallback = NULL;
3111
3112 /* Enable the DMA channel */
3113 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3114 }
3115 else
3116 {
3117 /* Update I2C state */
3118 hi2c->State = HAL_I2C_STATE_READY;
3119 hi2c->Mode = HAL_I2C_MODE_NONE;
3120
3121 /* Update I2C error code */
3122 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3123
3124 /* Process Unlocked */
3125 __HAL_UNLOCK(hi2c);
3126
3127 return HAL_ERROR;
3128 }
3129
3130 if (dmaxferstatus == HAL_OK)
3131 {
3132 /* Send Slave Address and Memory Address */
3133 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3134 {
3135 /* Abort the ongoing DMA */
3136 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);
3137
3138 /* Prevent unused argument(s) compilation and MISRA warning */
3139 UNUSED(dmaxferstatus);
3140
3141 /* Set the unused I2C DMA transfer complete callback to NULL */
3142 hi2c->hdmatx->XferCpltCallback = NULL;
3143
3144 /* Disable Acknowledge */
3145 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3146
3147 hi2c->XferSize = 0U;
3148 hi2c->XferCount = 0U;
3149
3150 /* Disable I2C peripheral to prevent dummy data in buffer */
3151 __HAL_I2C_DISABLE(hi2c);
3152
3153 return HAL_ERROR;
3154 }
3155
3156 /* Clear ADDR flag */
3157 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3158
3159 /* Process Unlocked */
3160 __HAL_UNLOCK(hi2c);
3161
3162 /* Note : The I2C interrupts must be enabled after unlocking current process
3163 to avoid the risk of I2C interrupt handle execution before current
3164 process unlock */
3165 /* Enable ERR interrupt */
3166 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3167
3168 /* Enable DMA Request */
3169 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3170
3171 return HAL_OK;
3172 }
3173 else
3174 {
3175 /* Update I2C state */
3176 hi2c->State = HAL_I2C_STATE_READY;
3177 hi2c->Mode = HAL_I2C_MODE_NONE;
3178
3179 /* Update I2C error code */
3180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3181
3182 /* Process Unlocked */
3183 __HAL_UNLOCK(hi2c);
3184
3185 return HAL_ERROR;
3186 }
3187 }
3188 else
3189 {
3190 /* Update I2C state */
3191 hi2c->State = HAL_I2C_STATE_READY;
3192 hi2c->Mode = HAL_I2C_MODE_NONE;
3193
3194 /* Update I2C error code */
3195 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;
3196
3197 /* Process Unlocked */
3198 __HAL_UNLOCK(hi2c);
3199
3200 return HAL_ERROR;
3201 }
3202 }
3203 else
3204 {
3205 return HAL_BUSY;
3206 }
3207 }
3208
3209 /**
3210 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
3211 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3212 * the configuration information for the specified I2C.
3213 * @param DevAddress Target device address: The device 7 bits address value
3214 * in datasheet must be shifted to the left before calling the interface
3215 * @param MemAddress Internal memory address
3216 * @param MemAddSize Size of internal memory address
3217 * @param pData Pointer to data buffer
3218 * @param Size Amount of data to be read
3219 * @retval HAL status
3220 */
HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint8_t * pData,uint16_t Size)3221 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
3222 {
3223 /* Init tickstart for timeout management*/
3224 uint32_t tickstart = HAL_GetTick();
3225 __IO uint32_t count = 0U;
3226 HAL_StatusTypeDef dmaxferstatus;
3227
3228 /* Check the parameters */
3229 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
3230
3231 if (hi2c->State == HAL_I2C_STATE_READY)
3232 {
3233 /* Wait until BUSY flag is reset */
3234 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3235 do
3236 {
3237 count--;
3238 if (count == 0U)
3239 {
3240 hi2c->PreviousState = I2C_STATE_NONE;
3241 hi2c->State = HAL_I2C_STATE_READY;
3242 hi2c->Mode = HAL_I2C_MODE_NONE;
3243 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3244
3245 return HAL_BUSY;
3246 }
3247 }
3248 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3249
3250 /* Process Locked */
3251 __HAL_LOCK(hi2c);
3252
3253 /* Check if the I2C is already enabled */
3254 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3255 {
3256 /* Enable I2C peripheral */
3257 __HAL_I2C_ENABLE(hi2c);
3258 }
3259
3260 /* Disable Pos */
3261 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3262
3263 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3264 hi2c->Mode = HAL_I2C_MODE_MEM;
3265 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3266
3267 /* Prepare transfer parameters */
3268 hi2c->pBuffPtr = pData;
3269 hi2c->XferCount = Size;
3270 hi2c->XferSize = hi2c->XferCount;
3271 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3272 hi2c->Devaddress = DevAddress;
3273 hi2c->Memaddress = MemAddress;
3274 hi2c->MemaddSize = MemAddSize;
3275 hi2c->EventCount = 0U;
3276
3277 if (hi2c->XferSize > 0U)
3278 {
3279 if (hi2c->hdmarx != NULL)
3280 {
3281 /* Set the I2C DMA transfer complete callback */
3282 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
3283
3284 /* Set the DMA error callback */
3285 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
3286
3287 /* Set the unused DMA callbacks to NULL */
3288 hi2c->hdmarx->XferHalfCpltCallback = NULL;
3289 hi2c->hdmarx->XferAbortCallback = NULL;
3290
3291 /* Enable the DMA channel */
3292 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
3293 }
3294 else
3295 {
3296 /* Update I2C state */
3297 hi2c->State = HAL_I2C_STATE_READY;
3298 hi2c->Mode = HAL_I2C_MODE_NONE;
3299
3300 /* Update I2C error code */
3301 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3302
3303 /* Process Unlocked */
3304 __HAL_UNLOCK(hi2c);
3305
3306 return HAL_ERROR;
3307 }
3308
3309 if (dmaxferstatus == HAL_OK)
3310 {
3311 /* Send Slave Address and Memory Address */
3312 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3313 {
3314 /* Abort the ongoing DMA */
3315 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);
3316
3317 /* Prevent unused argument(s) compilation and MISRA warning */
3318 UNUSED(dmaxferstatus);
3319
3320 /* Set the unused I2C DMA transfer complete callback to NULL */
3321 hi2c->hdmarx->XferCpltCallback = NULL;
3322
3323 /* Disable Acknowledge */
3324 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3325
3326 hi2c->XferSize = 0U;
3327 hi2c->XferCount = 0U;
3328
3329 /* Disable I2C peripheral to prevent dummy data in buffer */
3330 __HAL_I2C_DISABLE(hi2c);
3331
3332 return HAL_ERROR;
3333 }
3334
3335 if (hi2c->XferSize == 1U)
3336 {
3337 /* Disable Acknowledge */
3338 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3339 }
3340 else
3341 {
3342 /* Enable Last DMA bit */
3343 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3344 }
3345
3346 /* Clear ADDR flag */
3347 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3348
3349 /* Process Unlocked */
3350 __HAL_UNLOCK(hi2c);
3351
3352 /* Note : The I2C interrupts must be enabled after unlocking current process
3353 to avoid the risk of I2C interrupt handle execution before current
3354 process unlock */
3355 /* Enable ERR interrupt */
3356 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
3357
3358 /* Enable DMA Request */
3359 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
3360 }
3361 else
3362 {
3363 /* Update I2C state */
3364 hi2c->State = HAL_I2C_STATE_READY;
3365 hi2c->Mode = HAL_I2C_MODE_NONE;
3366
3367 /* Update I2C error code */
3368 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3369
3370 /* Process Unlocked */
3371 __HAL_UNLOCK(hi2c);
3372
3373 return HAL_ERROR;
3374 }
3375 }
3376 else
3377 {
3378 /* Send Slave Address and Memory Address */
3379 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
3380 {
3381 return HAL_ERROR;
3382 }
3383
3384 /* Clear ADDR flag */
3385 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3386
3387 /* Generate Stop */
3388 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3389
3390 hi2c->State = HAL_I2C_STATE_READY;
3391
3392 /* Process Unlocked */
3393 __HAL_UNLOCK(hi2c);
3394 }
3395
3396 return HAL_OK;
3397 }
3398 else
3399 {
3400 return HAL_BUSY;
3401 }
3402 }
3403
3404 /**
3405 * @brief Checks if target device is ready for communication.
3406 * @note This function is used with Memory devices
3407 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3408 * the configuration information for the specified I2C.
3409 * @param DevAddress Target device address: The device 7 bits address value
3410 * in datasheet must be shifted to the left before calling the interface
3411 * @param Trials Number of trials
3412 * @param Timeout Timeout duration
3413 * @retval HAL status
3414 */
HAL_I2C_IsDeviceReady(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Trials,uint32_t Timeout)3415 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
3416 {
3417 /* Get tick */
3418 uint32_t tickstart = HAL_GetTick();
3419 uint32_t I2C_Trials = 0U;
3420 FlagStatus tmp1;
3421 FlagStatus tmp2;
3422
3423 if (hi2c->State == HAL_I2C_STATE_READY)
3424 {
3425 /* Wait until BUSY flag is reset */
3426 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3427 {
3428 return HAL_BUSY;
3429 }
3430
3431 /* Process Locked */
3432 __HAL_LOCK(hi2c);
3433
3434 /* Check if the I2C is already enabled */
3435 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3436 {
3437 /* Enable I2C peripheral */
3438 __HAL_I2C_ENABLE(hi2c);
3439 }
3440
3441 /* Disable Pos */
3442 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3443
3444 hi2c->State = HAL_I2C_STATE_BUSY;
3445 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3446 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3447
3448 do
3449 {
3450 /* Generate Start */
3451 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3452
3453 /* Wait until SB flag is set */
3454 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
3455 {
3456 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
3457 {
3458 hi2c->ErrorCode = HAL_I2C_WRONG_START;
3459 }
3460 return HAL_TIMEOUT;
3461 }
3462
3463 /* Send slave address */
3464 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
3465
3466 /* Wait until ADDR or AF flag are set */
3467 /* Get tick */
3468 tickstart = HAL_GetTick();
3469
3470 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3471 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3472 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
3473 {
3474 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3475 {
3476 hi2c->State = HAL_I2C_STATE_TIMEOUT;
3477 }
3478 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
3479 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
3480 }
3481
3482 hi2c->State = HAL_I2C_STATE_READY;
3483
3484 /* Check if the ADDR flag has been set */
3485 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
3486 {
3487 /* Generate Stop */
3488 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3489
3490 /* Clear ADDR Flag */
3491 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
3492
3493 /* Wait until BUSY flag is reset */
3494 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3495 {
3496 return HAL_ERROR;
3497 }
3498
3499 hi2c->State = HAL_I2C_STATE_READY;
3500
3501 /* Process Unlocked */
3502 __HAL_UNLOCK(hi2c);
3503
3504 return HAL_OK;
3505 }
3506 else
3507 {
3508 /* Generate Stop */
3509 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
3510
3511 /* Clear AF Flag */
3512 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3513
3514 /* Wait until BUSY flag is reset */
3515 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
3516 {
3517 return HAL_ERROR;
3518 }
3519 }
3520
3521 /* Increment Trials */
3522 I2C_Trials++;
3523 }
3524 while (I2C_Trials < Trials);
3525
3526 hi2c->State = HAL_I2C_STATE_READY;
3527
3528 /* Process Unlocked */
3529 __HAL_UNLOCK(hi2c);
3530
3531 return HAL_ERROR;
3532 }
3533 else
3534 {
3535 return HAL_BUSY;
3536 }
3537 }
3538
3539 /**
3540 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
3541 * @note This interface allow to manage repeated start condition when a direction change during transfer
3542 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3543 * the configuration information for the specified I2C.
3544 * @param DevAddress Target device address: The device 7 bits address value
3545 * in datasheet must be shifted to the left before calling the interface
3546 * @param pData Pointer to data buffer
3547 * @param Size Amount of data to be sent
3548 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3549 * @retval HAL status
3550 */
HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3551 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3552 {
3553 __IO uint32_t Prev_State = 0x00U;
3554 __IO uint32_t count = 0x00U;
3555
3556 /* Check the parameters */
3557 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3558
3559 if (hi2c->State == HAL_I2C_STATE_READY)
3560 {
3561 /* Check Busy Flag only if FIRST call of Master interface */
3562 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3563 {
3564 /* Wait until BUSY flag is reset */
3565 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3566 do
3567 {
3568 count--;
3569 if (count == 0U)
3570 {
3571 hi2c->PreviousState = I2C_STATE_NONE;
3572 hi2c->State = HAL_I2C_STATE_READY;
3573 hi2c->Mode = HAL_I2C_MODE_NONE;
3574 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3575
3576 return HAL_BUSY;
3577 }
3578 }
3579 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3580 }
3581
3582 /* Process Locked */
3583 __HAL_LOCK(hi2c);
3584
3585 /* Check if the I2C is already enabled */
3586 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3587 {
3588 /* Enable I2C peripheral */
3589 __HAL_I2C_ENABLE(hi2c);
3590 }
3591
3592 /* Disable Pos */
3593 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3594
3595 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3596 hi2c->Mode = HAL_I2C_MODE_MASTER;
3597 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3598
3599 /* Prepare transfer parameters */
3600 hi2c->pBuffPtr = pData;
3601 hi2c->XferCount = Size;
3602 hi2c->XferSize = hi2c->XferCount;
3603 hi2c->XferOptions = XferOptions;
3604 hi2c->Devaddress = DevAddress;
3605
3606 Prev_State = hi2c->PreviousState;
3607
3608 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3609 /* Mean Previous state is same as current state */
3610 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3611 {
3612 /* Generate Start */
3613 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3614 }
3615
3616 /* Process Unlocked */
3617 __HAL_UNLOCK(hi2c);
3618
3619 /* Note : The I2C interrupts must be enabled after unlocking current process
3620 to avoid the risk of I2C interrupt handle execution before current
3621 process unlock */
3622
3623 /* Enable EVT, BUF and ERR interrupt */
3624 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3625
3626 return HAL_OK;
3627 }
3628 else
3629 {
3630 return HAL_BUSY;
3631 }
3632 }
3633
3634 /**
3635 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.
3636 * @note This interface allow to manage repeated start condition when a direction change during transfer
3637 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3638 * the configuration information for the specified I2C.
3639 * @param DevAddress Target device address: The device 7 bits address value
3640 * in datasheet must be shifted to the left before calling the interface
3641 * @param pData Pointer to data buffer
3642 * @param Size Amount of data to be sent
3643 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3644 * @retval HAL status
3645 */
HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3646 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3647 {
3648 __IO uint32_t Prev_State = 0x00U;
3649 __IO uint32_t count = 0x00U;
3650 HAL_StatusTypeDef dmaxferstatus;
3651
3652 /* Check the parameters */
3653 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3654
3655 if (hi2c->State == HAL_I2C_STATE_READY)
3656 {
3657 /* Check Busy Flag only if FIRST call of Master interface */
3658 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3659 {
3660 /* Wait until BUSY flag is reset */
3661 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3662 do
3663 {
3664 count--;
3665 if (count == 0U)
3666 {
3667 hi2c->PreviousState = I2C_STATE_NONE;
3668 hi2c->State = HAL_I2C_STATE_READY;
3669 hi2c->Mode = HAL_I2C_MODE_NONE;
3670 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3671
3672 return HAL_BUSY;
3673 }
3674 }
3675 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3676 }
3677
3678 /* Process Locked */
3679 __HAL_LOCK(hi2c);
3680
3681 /* Check if the I2C is already enabled */
3682 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3683 {
3684 /* Enable I2C peripheral */
3685 __HAL_I2C_ENABLE(hi2c);
3686 }
3687
3688 /* Disable Pos */
3689 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3690
3691 hi2c->State = HAL_I2C_STATE_BUSY_TX;
3692 hi2c->Mode = HAL_I2C_MODE_MASTER;
3693 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3694
3695 /* Prepare transfer parameters */
3696 hi2c->pBuffPtr = pData;
3697 hi2c->XferCount = Size;
3698 hi2c->XferSize = hi2c->XferCount;
3699 hi2c->XferOptions = XferOptions;
3700 hi2c->Devaddress = DevAddress;
3701
3702 Prev_State = hi2c->PreviousState;
3703
3704 if (hi2c->XferSize > 0U)
3705 {
3706 if (hi2c->hdmatx != NULL)
3707 {
3708 /* Set the I2C DMA transfer complete callback */
3709 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
3710
3711 /* Set the DMA error callback */
3712 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
3713
3714 /* Set the unused DMA callbacks to NULL */
3715 hi2c->hdmatx->XferHalfCpltCallback = NULL;
3716 hi2c->hdmatx->XferAbortCallback = NULL;
3717
3718 /* Enable the DMA channel */
3719 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
3720 }
3721 else
3722 {
3723 /* Update I2C state */
3724 hi2c->State = HAL_I2C_STATE_READY;
3725 hi2c->Mode = HAL_I2C_MODE_NONE;
3726
3727 /* Update I2C error code */
3728 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
3729
3730 /* Process Unlocked */
3731 __HAL_UNLOCK(hi2c);
3732
3733 return HAL_ERROR;
3734 }
3735
3736 if (dmaxferstatus == HAL_OK)
3737 {
3738 /* Enable Acknowledge */
3739 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3740
3741 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3742 /* Mean Previous state is same as current state */
3743 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3744 {
3745 /* Generate Start */
3746 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3747 }
3748
3749 /* Process Unlocked */
3750 __HAL_UNLOCK(hi2c);
3751
3752 /* Note : The I2C interrupts must be enabled after unlocking current process
3753 to avoid the risk of I2C interrupt handle execution before current
3754 process unlock */
3755
3756 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
3757 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
3758 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
3759 {
3760 /* Enable DMA Request */
3761 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
3762 }
3763
3764 /* Enable EVT and ERR interrupt */
3765 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
3766 }
3767 else
3768 {
3769 /* Update I2C state */
3770 hi2c->State = HAL_I2C_STATE_READY;
3771 hi2c->Mode = HAL_I2C_MODE_NONE;
3772
3773 /* Update I2C error code */
3774 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
3775
3776 /* Process Unlocked */
3777 __HAL_UNLOCK(hi2c);
3778
3779 return HAL_ERROR;
3780 }
3781 }
3782 else
3783 {
3784 /* Enable Acknowledge */
3785 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3786
3787 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3788 /* Mean Previous state is same as current state */
3789 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3790 {
3791 /* Generate Start */
3792 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3793 }
3794
3795 /* Process Unlocked */
3796 __HAL_UNLOCK(hi2c);
3797
3798 /* Note : The I2C interrupts must be enabled after unlocking current process
3799 to avoid the risk of I2C interrupt handle execution before current
3800 process unlock */
3801
3802 /* Enable EVT, BUF and ERR interrupt */
3803 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3804 }
3805
3806 return HAL_OK;
3807 }
3808 else
3809 {
3810 return HAL_BUSY;
3811 }
3812 }
3813
3814 /**
3815 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
3816 * @note This interface allow to manage repeated start condition when a direction change during transfer
3817 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3818 * the configuration information for the specified I2C.
3819 * @param DevAddress Target device address: The device 7 bits address value
3820 * in datasheet must be shifted to the left before calling the interface
3821 * @param pData Pointer to data buffer
3822 * @param Size Amount of data to be sent
3823 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3824 * @retval HAL status
3825 */
HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3826 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3827 {
3828 __IO uint32_t Prev_State = 0x00U;
3829 __IO uint32_t count = 0U;
3830 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3831
3832 /* Check the parameters */
3833 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3834
3835 if (hi2c->State == HAL_I2C_STATE_READY)
3836 {
3837 /* Check Busy Flag only if FIRST call of Master interface */
3838 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3839 {
3840 /* Wait until BUSY flag is reset */
3841 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3842 do
3843 {
3844 count--;
3845 if (count == 0U)
3846 {
3847 hi2c->PreviousState = I2C_STATE_NONE;
3848 hi2c->State = HAL_I2C_STATE_READY;
3849 hi2c->Mode = HAL_I2C_MODE_NONE;
3850 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3851
3852 return HAL_BUSY;
3853 }
3854 }
3855 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3856 }
3857
3858 /* Process Locked */
3859 __HAL_LOCK(hi2c);
3860
3861 /* Check if the I2C is already enabled */
3862 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3863 {
3864 /* Enable I2C peripheral */
3865 __HAL_I2C_ENABLE(hi2c);
3866 }
3867
3868 /* Disable Pos */
3869 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3870
3871 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3872 hi2c->Mode = HAL_I2C_MODE_MASTER;
3873 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3874
3875 /* Prepare transfer parameters */
3876 hi2c->pBuffPtr = pData;
3877 hi2c->XferCount = Size;
3878 hi2c->XferSize = hi2c->XferCount;
3879 hi2c->XferOptions = XferOptions;
3880 hi2c->Devaddress = DevAddress;
3881
3882 Prev_State = hi2c->PreviousState;
3883
3884 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
3885 {
3886 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
3887 {
3888 /* Disable Acknowledge */
3889 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3890
3891 /* Enable Pos */
3892 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3893
3894 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */
3895 enableIT &= ~I2C_IT_BUF;
3896 }
3897 else
3898 {
3899 /* Enable Acknowledge */
3900 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3901 }
3902 }
3903 else
3904 {
3905 /* Enable Acknowledge */
3906 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
3907 }
3908
3909 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
3910 /* Mean Previous state is same as current state */
3911 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
3912 {
3913 /* Generate Start */
3914 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
3915 }
3916
3917 /* Process Unlocked */
3918 __HAL_UNLOCK(hi2c);
3919
3920 /* Note : The I2C interrupts must be enabled after unlocking current process
3921 to avoid the risk of I2C interrupt handle execution before current
3922 process unlock */
3923
3924 /* Enable interrupts */
3925 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
3926
3927 return HAL_OK;
3928 }
3929 else
3930 {
3931 return HAL_BUSY;
3932 }
3933 }
3934
3935 /**
3936 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA
3937 * @note This interface allow to manage repeated start condition when a direction change during transfer
3938 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3939 * the configuration information for the specified I2C.
3940 * @param DevAddress Target device address: The device 7 bits address value
3941 * in datasheet must be shifted to the left before calling the interface
3942 * @param pData Pointer to data buffer
3943 * @param Size Amount of data to be sent
3944 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
3945 * @retval HAL status
3946 */
HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint8_t * pData,uint16_t Size,uint32_t XferOptions)3947 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
3948 {
3949 __IO uint32_t Prev_State = 0x00U;
3950 __IO uint32_t count = 0U;
3951 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
3952 HAL_StatusTypeDef dmaxferstatus;
3953
3954 /* Check the parameters */
3955 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
3956
3957 if (hi2c->State == HAL_I2C_STATE_READY)
3958 {
3959 /* Check Busy Flag only if FIRST call of Master interface */
3960 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))
3961 {
3962 /* Wait until BUSY flag is reset */
3963 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);
3964 do
3965 {
3966 count--;
3967 if (count == 0U)
3968 {
3969 hi2c->PreviousState = I2C_STATE_NONE;
3970 hi2c->State = HAL_I2C_STATE_READY;
3971 hi2c->Mode = HAL_I2C_MODE_NONE;
3972 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
3973
3974 return HAL_BUSY;
3975 }
3976 }
3977 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
3978 }
3979
3980 /* Process Locked */
3981 __HAL_LOCK(hi2c);
3982
3983 /* Check if the I2C is already enabled */
3984 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
3985 {
3986 /* Enable I2C peripheral */
3987 __HAL_I2C_ENABLE(hi2c);
3988 }
3989
3990 /* Disable Pos */
3991 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
3992
3993 /* Clear Last DMA bit */
3994 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
3995
3996 hi2c->State = HAL_I2C_STATE_BUSY_RX;
3997 hi2c->Mode = HAL_I2C_MODE_MASTER;
3998 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
3999
4000 /* Prepare transfer parameters */
4001 hi2c->pBuffPtr = pData;
4002 hi2c->XferCount = Size;
4003 hi2c->XferSize = hi2c->XferCount;
4004 hi2c->XferOptions = XferOptions;
4005 hi2c->Devaddress = DevAddress;
4006
4007 Prev_State = hi2c->PreviousState;
4008
4009 if (hi2c->XferSize > 0U)
4010 {
4011 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))
4012 {
4013 if (Prev_State == I2C_STATE_MASTER_BUSY_RX)
4014 {
4015 /* Disable Acknowledge */
4016 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4017
4018 /* Enable Pos */
4019 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4020
4021 /* Enable Last DMA bit */
4022 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4023 }
4024 else
4025 {
4026 /* Enable Acknowledge */
4027 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4028 }
4029 }
4030 else
4031 {
4032 /* Enable Acknowledge */
4033 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4034
4035 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4036 {
4037 /* Enable Last DMA bit */
4038 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
4039 }
4040 }
4041 if (hi2c->hdmarx != NULL)
4042 {
4043 /* Set the I2C DMA transfer complete callback */
4044 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4045
4046 /* Set the DMA error callback */
4047 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4048
4049 /* Set the unused DMA callbacks to NULL */
4050 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4051 hi2c->hdmarx->XferAbortCallback = NULL;
4052
4053 /* Enable the DMA channel */
4054 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4055 }
4056 else
4057 {
4058 /* Update I2C state */
4059 hi2c->State = HAL_I2C_STATE_READY;
4060 hi2c->Mode = HAL_I2C_MODE_NONE;
4061
4062 /* Update I2C error code */
4063 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4064
4065 /* Process Unlocked */
4066 __HAL_UNLOCK(hi2c);
4067
4068 return HAL_ERROR;
4069 }
4070 if (dmaxferstatus == HAL_OK)
4071 {
4072 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4073 /* Mean Previous state is same as current state */
4074 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4075 {
4076 /* Generate Start */
4077 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4078
4079 /* Update interrupt for only EVT and ERR */
4080 enableIT = (I2C_IT_EVT | I2C_IT_ERR);
4081 }
4082 else
4083 {
4084 /* Update interrupt for only ERR */
4085 enableIT = I2C_IT_ERR;
4086 }
4087
4088 /* Process Unlocked */
4089 __HAL_UNLOCK(hi2c);
4090
4091 /* Note : The I2C interrupts must be enabled after unlocking current process
4092 to avoid the risk of I2C interrupt handle execution before current
4093 process unlock */
4094
4095 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */
4096 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */
4097 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))
4098 {
4099 /* Enable DMA Request */
4100 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4101 }
4102
4103 /* Enable EVT and ERR interrupt */
4104 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4105 }
4106 else
4107 {
4108 /* Update I2C state */
4109 hi2c->State = HAL_I2C_STATE_READY;
4110 hi2c->Mode = HAL_I2C_MODE_NONE;
4111
4112 /* Update I2C error code */
4113 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4114
4115 /* Process Unlocked */
4116 __HAL_UNLOCK(hi2c);
4117
4118 return HAL_ERROR;
4119 }
4120 }
4121 else
4122 {
4123 /* Enable Acknowledge */
4124 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4125
4126 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
4127 /* Mean Previous state is same as current state */
4128 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))
4129 {
4130 /* Generate Start */
4131 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
4132 }
4133
4134 /* Process Unlocked */
4135 __HAL_UNLOCK(hi2c);
4136
4137 /* Note : The I2C interrupts must be enabled after unlocking current process
4138 to avoid the risk of I2C interrupt handle execution before current
4139 process unlock */
4140
4141 /* Enable interrupts */
4142 __HAL_I2C_ENABLE_IT(hi2c, enableIT);
4143 }
4144 return HAL_OK;
4145 }
4146 else
4147 {
4148 return HAL_BUSY;
4149 }
4150 }
4151
4152 /**
4153 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt
4154 * @note This interface allow to manage repeated start condition when a direction change during transfer
4155 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4156 * the configuration information for the specified I2C.
4157 * @param pData Pointer to data buffer
4158 * @param Size Amount of data to be sent
4159 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4160 * @retval HAL status
4161 */
HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4162 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4163 {
4164 /* Check the parameters */
4165 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4166
4167 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4168 {
4169 if ((pData == NULL) || (Size == 0U))
4170 {
4171 return HAL_ERROR;
4172 }
4173
4174 /* Process Locked */
4175 __HAL_LOCK(hi2c);
4176
4177 /* Check if the I2C is already enabled */
4178 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4179 {
4180 /* Enable I2C peripheral */
4181 __HAL_I2C_ENABLE(hi2c);
4182 }
4183
4184 /* Disable Pos */
4185 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4186
4187 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4188 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4189 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4190
4191 /* Prepare transfer parameters */
4192 hi2c->pBuffPtr = pData;
4193 hi2c->XferCount = Size;
4194 hi2c->XferSize = hi2c->XferCount;
4195 hi2c->XferOptions = XferOptions;
4196
4197 /* Clear ADDR flag */
4198 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4199
4200 /* Process Unlocked */
4201 __HAL_UNLOCK(hi2c);
4202
4203 /* Note : The I2C interrupts must be enabled after unlocking current process
4204 to avoid the risk of I2C interrupt handle execution before current
4205 process unlock */
4206
4207 /* Enable EVT, BUF and ERR interrupt */
4208 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4209
4210 return HAL_OK;
4211 }
4212 else
4213 {
4214 return HAL_BUSY;
4215 }
4216 }
4217
4218 /**
4219 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA
4220 * @note This interface allow to manage repeated start condition when a direction change during transfer
4221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4222 * the configuration information for the specified I2C.
4223 * @param pData Pointer to data buffer
4224 * @param Size Amount of data to be sent
4225 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4226 * @retval HAL status
4227 */
HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4228 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4229 {
4230 HAL_StatusTypeDef dmaxferstatus;
4231
4232 /* Check the parameters */
4233 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4234
4235 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4236 {
4237 if ((pData == NULL) || (Size == 0U))
4238 {
4239 return HAL_ERROR;
4240 }
4241
4242 /* Process Locked */
4243 __HAL_LOCK(hi2c);
4244
4245 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4246 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4247
4248 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4249 /* and then toggle the HAL slave RX state to TX state */
4250 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4251 {
4252 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4253 {
4254 /* Abort DMA Xfer if any */
4255 if (hi2c->hdmarx != NULL)
4256 {
4257 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4258
4259 /* Set the I2C DMA Abort callback :
4260 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4261 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4262
4263 /* Abort DMA RX */
4264 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4265 {
4266 /* Call Directly XferAbortCallback function in case of error */
4267 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4268 }
4269 }
4270 }
4271 }
4272 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4273 {
4274 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4275 {
4276 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4277
4278 /* Abort DMA Xfer if any */
4279 if (hi2c->hdmatx != NULL)
4280 {
4281 /* Set the I2C DMA Abort callback :
4282 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4283 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4284
4285 /* Abort DMA TX */
4286 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4287 {
4288 /* Call Directly XferAbortCallback function in case of error */
4289 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4290 }
4291 }
4292 }
4293 }
4294 else
4295 {
4296 /* Nothing to do */
4297 }
4298
4299 /* Check if the I2C is already enabled */
4300 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4301 {
4302 /* Enable I2C peripheral */
4303 __HAL_I2C_ENABLE(hi2c);
4304 }
4305
4306 /* Disable Pos */
4307 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4308
4309 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
4310 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4311 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4312
4313 /* Prepare transfer parameters */
4314 hi2c->pBuffPtr = pData;
4315 hi2c->XferCount = Size;
4316 hi2c->XferSize = hi2c->XferCount;
4317 hi2c->XferOptions = XferOptions;
4318
4319 if (hi2c->hdmatx != NULL)
4320 {
4321 /* Set the I2C DMA transfer complete callback */
4322 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
4323
4324 /* Set the DMA error callback */
4325 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
4326
4327 /* Set the unused DMA callbacks to NULL */
4328 hi2c->hdmatx->XferHalfCpltCallback = NULL;
4329 hi2c->hdmatx->XferAbortCallback = NULL;
4330
4331 /* Enable the DMA channel */
4332 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
4333 }
4334 else
4335 {
4336 /* Update I2C state */
4337 hi2c->State = HAL_I2C_STATE_LISTEN;
4338 hi2c->Mode = HAL_I2C_MODE_NONE;
4339
4340 /* Update I2C error code */
4341 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4342
4343 /* Process Unlocked */
4344 __HAL_UNLOCK(hi2c);
4345
4346 return HAL_ERROR;
4347 }
4348
4349 if (dmaxferstatus == HAL_OK)
4350 {
4351 /* Enable Address Acknowledge */
4352 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4353
4354 /* Clear ADDR flag */
4355 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4356
4357 /* Process Unlocked */
4358 __HAL_UNLOCK(hi2c);
4359
4360 /* Note : The I2C interrupts must be enabled after unlocking current process
4361 to avoid the risk of I2C interrupt handle execution before current
4362 process unlock */
4363 /* Enable EVT and ERR interrupt */
4364 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4365
4366 /* Enable DMA Request */
4367 hi2c->Instance->CR2 |= I2C_CR2_DMAEN;
4368
4369 return HAL_OK;
4370 }
4371 else
4372 {
4373 /* Update I2C state */
4374 hi2c->State = HAL_I2C_STATE_READY;
4375 hi2c->Mode = HAL_I2C_MODE_NONE;
4376
4377 /* Update I2C error code */
4378 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4379
4380 /* Process Unlocked */
4381 __HAL_UNLOCK(hi2c);
4382
4383 return HAL_ERROR;
4384 }
4385 }
4386 else
4387 {
4388 return HAL_BUSY;
4389 }
4390 }
4391
4392 /**
4393 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
4394 * @note This interface allow to manage repeated start condition when a direction change during transfer
4395 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4396 * the configuration information for the specified I2C.
4397 * @param pData Pointer to data buffer
4398 * @param Size Amount of data to be sent
4399 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4400 * @retval HAL status
4401 */
HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4402 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4403 {
4404 /* Check the parameters */
4405 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4406
4407 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4408 {
4409 if ((pData == NULL) || (Size == 0U))
4410 {
4411 return HAL_ERROR;
4412 }
4413
4414 /* Process Locked */
4415 __HAL_LOCK(hi2c);
4416
4417 /* Check if the I2C is already enabled */
4418 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4419 {
4420 /* Enable I2C peripheral */
4421 __HAL_I2C_ENABLE(hi2c);
4422 }
4423
4424 /* Disable Pos */
4425 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4426
4427 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4428 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4429 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4430
4431 /* Prepare transfer parameters */
4432 hi2c->pBuffPtr = pData;
4433 hi2c->XferCount = Size;
4434 hi2c->XferSize = hi2c->XferCount;
4435 hi2c->XferOptions = XferOptions;
4436
4437 /* Clear ADDR flag */
4438 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4439
4440 /* Process Unlocked */
4441 __HAL_UNLOCK(hi2c);
4442
4443 /* Note : The I2C interrupts must be enabled after unlocking current process
4444 to avoid the risk of I2C interrupt handle execution before current
4445 process unlock */
4446
4447 /* Enable EVT, BUF and ERR interrupt */
4448 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4449
4450 return HAL_OK;
4451 }
4452 else
4453 {
4454 return HAL_BUSY;
4455 }
4456 }
4457
4458 /**
4459 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA
4460 * @note This interface allow to manage repeated start condition when a direction change during transfer
4461 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4462 * the configuration information for the specified I2C.
4463 * @param pData Pointer to data buffer
4464 * @param Size Amount of data to be sent
4465 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
4466 * @retval HAL status
4467 */
HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef * hi2c,uint8_t * pData,uint16_t Size,uint32_t XferOptions)4468 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
4469 {
4470 HAL_StatusTypeDef dmaxferstatus;
4471
4472 /* Check the parameters */
4473 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
4474
4475 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
4476 {
4477 if ((pData == NULL) || (Size == 0U))
4478 {
4479 return HAL_ERROR;
4480 }
4481
4482 /* Process Locked */
4483 __HAL_LOCK(hi2c);
4484
4485 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
4486 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4487
4488 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
4489 /* and then toggle the HAL slave RX state to TX state */
4490 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
4491 {
4492 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4493 {
4494 /* Abort DMA Xfer if any */
4495 if (hi2c->hdmarx != NULL)
4496 {
4497 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4498
4499 /* Set the I2C DMA Abort callback :
4500 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4501 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4502
4503 /* Abort DMA RX */
4504 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4505 {
4506 /* Call Directly XferAbortCallback function in case of error */
4507 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4508 }
4509 }
4510 }
4511 }
4512 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
4513 {
4514 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
4515 {
4516 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4517
4518 /* Abort DMA Xfer if any */
4519 if (hi2c->hdmatx != NULL)
4520 {
4521 /* Set the I2C DMA Abort callback :
4522 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4523 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4524
4525 /* Abort DMA TX */
4526 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4527 {
4528 /* Call Directly XferAbortCallback function in case of error */
4529 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4530 }
4531 }
4532 }
4533 }
4534 else
4535 {
4536 /* Nothing to do */
4537 }
4538
4539 /* Check if the I2C is already enabled */
4540 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4541 {
4542 /* Enable I2C peripheral */
4543 __HAL_I2C_ENABLE(hi2c);
4544 }
4545
4546 /* Disable Pos */
4547 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
4548
4549 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
4550 hi2c->Mode = HAL_I2C_MODE_SLAVE;
4551 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4552
4553 /* Prepare transfer parameters */
4554 hi2c->pBuffPtr = pData;
4555 hi2c->XferCount = Size;
4556 hi2c->XferSize = hi2c->XferCount;
4557 hi2c->XferOptions = XferOptions;
4558
4559 if (hi2c->hdmarx != NULL)
4560 {
4561 /* Set the I2C DMA transfer complete callback */
4562 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
4563
4564 /* Set the DMA error callback */
4565 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
4566
4567 /* Set the unused DMA callbacks to NULL */
4568 hi2c->hdmarx->XferHalfCpltCallback = NULL;
4569 hi2c->hdmarx->XferAbortCallback = NULL;
4570
4571 /* Enable the DMA channel */
4572 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4573 }
4574 else
4575 {
4576 /* Update I2C state */
4577 hi2c->State = HAL_I2C_STATE_LISTEN;
4578 hi2c->Mode = HAL_I2C_MODE_NONE;
4579
4580 /* Update I2C error code */
4581 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
4582
4583 /* Process Unlocked */
4584 __HAL_UNLOCK(hi2c);
4585
4586 return HAL_ERROR;
4587 }
4588
4589 if (dmaxferstatus == HAL_OK)
4590 {
4591 /* Enable Address Acknowledge */
4592 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4593
4594 /* Clear ADDR flag */
4595 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
4596
4597 /* Process Unlocked */
4598 __HAL_UNLOCK(hi2c);
4599
4600 /* Enable DMA Request */
4601 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
4602
4603 /* Note : The I2C interrupts must be enabled after unlocking current process
4604 to avoid the risk of I2C interrupt handle execution before current
4605 process unlock */
4606 /* Enable EVT and ERR interrupt */
4607 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4608
4609 return HAL_OK;
4610 }
4611 else
4612 {
4613 /* Update I2C state */
4614 hi2c->State = HAL_I2C_STATE_READY;
4615 hi2c->Mode = HAL_I2C_MODE_NONE;
4616
4617 /* Update I2C error code */
4618 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
4619
4620 /* Process Unlocked */
4621 __HAL_UNLOCK(hi2c);
4622
4623 return HAL_ERROR;
4624 }
4625 }
4626 else
4627 {
4628 return HAL_BUSY;
4629 }
4630 }
4631
4632 /**
4633 * @brief Enable the Address listen mode with Interrupt.
4634 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4635 * the configuration information for the specified I2C.
4636 * @retval HAL status
4637 */
HAL_I2C_EnableListen_IT(I2C_HandleTypeDef * hi2c)4638 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
4639 {
4640 if (hi2c->State == HAL_I2C_STATE_READY)
4641 {
4642 hi2c->State = HAL_I2C_STATE_LISTEN;
4643
4644 /* Check if the I2C is already enabled */
4645 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
4646 {
4647 /* Enable I2C peripheral */
4648 __HAL_I2C_ENABLE(hi2c);
4649 }
4650
4651 /* Enable Address Acknowledge */
4652 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4653
4654 /* Enable EVT and ERR interrupt */
4655 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4656
4657 return HAL_OK;
4658 }
4659 else
4660 {
4661 return HAL_BUSY;
4662 }
4663 }
4664
4665 /**
4666 * @brief Disable the Address listen mode with Interrupt.
4667 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4668 * the configuration information for the specified I2C.
4669 * @retval HAL status
4670 */
HAL_I2C_DisableListen_IT(I2C_HandleTypeDef * hi2c)4671 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
4672 {
4673 /* Declaration of tmp to prevent undefined behavior of volatile usage */
4674 uint32_t tmp;
4675
4676 /* Disable Address listen mode only if a transfer is not ongoing */
4677 if (hi2c->State == HAL_I2C_STATE_LISTEN)
4678 {
4679 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
4680 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
4681 hi2c->State = HAL_I2C_STATE_READY;
4682 hi2c->Mode = HAL_I2C_MODE_NONE;
4683
4684 /* Disable Address Acknowledge */
4685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4686
4687 /* Disable EVT and ERR interrupt */
4688 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
4689
4690 return HAL_OK;
4691 }
4692 else
4693 {
4694 return HAL_BUSY;
4695 }
4696 }
4697
4698 /**
4699 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
4700 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4701 * the configuration information for the specified I2C.
4702 * @param DevAddress Target device address: The device 7 bits address value
4703 * in datasheet must be shifted to the left before calling the interface
4704 * @retval HAL status
4705 */
HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef * hi2c,uint16_t DevAddress)4706 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
4707 {
4708 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
4709 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4710
4711 /* Prevent unused argument(s) compilation warning */
4712 UNUSED(DevAddress);
4713
4714 /* Abort Master transfer during Receive or Transmit process */
4715 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))
4716 {
4717 /* Process Locked */
4718 __HAL_LOCK(hi2c);
4719
4720 hi2c->PreviousState = I2C_STATE_NONE;
4721 hi2c->State = HAL_I2C_STATE_ABORT;
4722
4723 /* Disable Acknowledge */
4724 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
4725
4726 /* Generate Stop */
4727 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4728
4729 hi2c->XferCount = 0U;
4730
4731 /* Disable EVT, BUF and ERR interrupt */
4732 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
4733
4734 /* Process Unlocked */
4735 __HAL_UNLOCK(hi2c);
4736
4737 /* Call the corresponding callback to inform upper layer of End of Transfer */
4738 I2C_ITError(hi2c);
4739
4740 return HAL_OK;
4741 }
4742 else
4743 {
4744 /* Wrong usage of abort function */
4745 /* This function should be used only in case of abort monitored by master device */
4746 /* Or periphal is not in busy state, mean there is no active sequence to be abort */
4747 return HAL_ERROR;
4748 }
4749 }
4750
4751 /**
4752 * @}
4753 */
4754
4755 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
4756 * @{
4757 */
4758
4759 /**
4760 * @brief This function handles I2C event interrupt request.
4761 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4762 * the configuration information for the specified I2C.
4763 * @retval None
4764 */
HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef * hi2c)4765 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
4766 {
4767 uint32_t sr1itflags;
4768 uint32_t sr2itflags = 0U;
4769 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4770 uint32_t CurrentXferOptions = hi2c->XferOptions;
4771 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4772 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
4773
4774 /* Master or Memory mode selected */
4775 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4776 {
4777 sr2itflags = READ_REG(hi2c->Instance->SR2);
4778 sr1itflags = READ_REG(hi2c->Instance->SR1);
4779
4780 /* Exit IRQ event until Start Bit detected in case of Other frame requested */
4781 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))
4782 {
4783 return;
4784 }
4785
4786 /* SB Set ----------------------------------------------------------------*/
4787 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4788 {
4789 /* Convert OTHER_xxx XferOptions if any */
4790 I2C_ConvertOtherXferOptions(hi2c);
4791
4792 I2C_Master_SB(hi2c);
4793 }
4794 /* ADD10 Set -------------------------------------------------------------*/
4795 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4796 {
4797 I2C_Master_ADD10(hi2c);
4798 }
4799 /* ADDR Set --------------------------------------------------------------*/
4800 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4801 {
4802 I2C_Master_ADDR(hi2c);
4803 }
4804 /* I2C in mode Transmitter -----------------------------------------------*/
4805 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)
4806 {
4807 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4808 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4809 {
4810 /* TXE set and BTF reset -----------------------------------------------*/
4811 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4812 {
4813 I2C_MasterTransmit_TXE(hi2c);
4814 }
4815 /* BTF set -------------------------------------------------------------*/
4816 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4817 {
4818 if (CurrentState == HAL_I2C_STATE_BUSY_TX)
4819 {
4820 I2C_MasterTransmit_BTF(hi2c);
4821 }
4822 else /* HAL_I2C_MODE_MEM */
4823 {
4824 if (CurrentMode == HAL_I2C_MODE_MEM)
4825 {
4826 I2C_MemoryTransmit_TXE_BTF(hi2c);
4827 }
4828 }
4829 }
4830 else
4831 {
4832 /* Do nothing */
4833 }
4834 }
4835 }
4836 /* I2C in mode Receiver --------------------------------------------------*/
4837 else
4838 {
4839 /* Do not check buffer and BTF flag if a Xfer DMA is on going */
4840 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)
4841 {
4842 /* RXNE set and BTF reset -----------------------------------------------*/
4843 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4844 {
4845 I2C_MasterReceive_RXNE(hi2c);
4846 }
4847 /* BTF set -------------------------------------------------------------*/
4848 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4849 {
4850 I2C_MasterReceive_BTF(hi2c);
4851 }
4852 else
4853 {
4854 /* Do nothing */
4855 }
4856 }
4857 }
4858 }
4859 /* Slave mode selected */
4860 else
4861 {
4862 /* If an error is detected, read only SR1 register to prevent */
4863 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */
4864 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4865 {
4866 sr1itflags = READ_REG(hi2c->Instance->SR1);
4867 }
4868 else
4869 {
4870 sr2itflags = READ_REG(hi2c->Instance->SR2);
4871 sr1itflags = READ_REG(hi2c->Instance->SR1);
4872 }
4873
4874 /* ADDR set --------------------------------------------------------------*/
4875 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4876 {
4877 /* Now time to read SR2, this will clear ADDR flag automatically */
4878 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4879 {
4880 sr2itflags = READ_REG(hi2c->Instance->SR2);
4881 }
4882 I2C_Slave_ADDR(hi2c, sr2itflags);
4883 }
4884 /* STOPF set --------------------------------------------------------------*/
4885 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4886 {
4887 I2C_Slave_STOPF(hi2c);
4888 }
4889 /* I2C in mode Transmitter -----------------------------------------------*/
4890 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
4891 {
4892 /* TXE set and BTF reset -----------------------------------------------*/
4893 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4894 {
4895 I2C_SlaveTransmit_TXE(hi2c);
4896 }
4897 /* BTF set -------------------------------------------------------------*/
4898 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4899 {
4900 I2C_SlaveTransmit_BTF(hi2c);
4901 }
4902 else
4903 {
4904 /* Do nothing */
4905 }
4906 }
4907 /* I2C in mode Receiver --------------------------------------------------*/
4908 else
4909 {
4910 /* RXNE set and BTF reset ----------------------------------------------*/
4911 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))
4912 {
4913 I2C_SlaveReceive_RXNE(hi2c);
4914 }
4915 /* BTF set -------------------------------------------------------------*/
4916 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))
4917 {
4918 I2C_SlaveReceive_BTF(hi2c);
4919 }
4920 else
4921 {
4922 /* Do nothing */
4923 }
4924 }
4925 }
4926 }
4927
4928 /**
4929 * @brief This function handles I2C error interrupt request.
4930 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4931 * the configuration information for the specified I2C.
4932 * @retval None
4933 */
HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef * hi2c)4934 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
4935 {
4936 HAL_I2C_ModeTypeDef tmp1;
4937 uint32_t tmp2;
4938 HAL_I2C_StateTypeDef tmp3;
4939 uint32_t tmp4;
4940 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
4941 uint32_t itsources = READ_REG(hi2c->Instance->CR2);
4942 uint32_t error = HAL_I2C_ERROR_NONE;
4943 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
4944
4945 /* I2C Bus error interrupt occurred ----------------------------------------*/
4946 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4947 {
4948 error |= HAL_I2C_ERROR_BERR;
4949
4950 /* Clear BERR flag */
4951 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
4952 }
4953
4954 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/
4955 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4956 {
4957 error |= HAL_I2C_ERROR_ARLO;
4958
4959 /* Clear ARLO flag */
4960 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
4961 }
4962
4963 /* I2C Acknowledge failure error interrupt occurred ------------------------*/
4964 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4965 {
4966 tmp1 = CurrentMode;
4967 tmp2 = hi2c->XferCount;
4968 tmp3 = hi2c->State;
4969 tmp4 = hi2c->PreviousState;
4970 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
4971 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \
4972 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
4973 {
4974 I2C_Slave_AF(hi2c);
4975 }
4976 else
4977 {
4978 /* Clear AF flag */
4979 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4980
4981 error |= HAL_I2C_ERROR_AF;
4982
4983 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
4984 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))
4985 {
4986 /* Generate Stop */
4987 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
4988 }
4989 }
4990 }
4991
4992 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
4993 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))
4994 {
4995 error |= HAL_I2C_ERROR_OVR;
4996 /* Clear OVR flag */
4997 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
4998 }
4999
5000 /* Call the Error Callback in case of Error detected -----------------------*/
5001 if (error != HAL_I2C_ERROR_NONE)
5002 {
5003 hi2c->ErrorCode |= error;
5004 I2C_ITError(hi2c);
5005 }
5006 }
5007
5008 /**
5009 * @brief Master Tx Transfer completed callback.
5010 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5011 * the configuration information for the specified I2C.
5012 * @retval None
5013 */
HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef * hi2c)5014 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
5015 {
5016 /* Prevent unused argument(s) compilation warning */
5017 UNUSED(hi2c);
5018
5019 /* NOTE : This function should not be modified, when the callback is needed,
5020 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
5021 */
5022 }
5023
5024 /**
5025 * @brief Master Rx Transfer completed callback.
5026 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5027 * the configuration information for the specified I2C.
5028 * @retval None
5029 */
HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef * hi2c)5030 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
5031 {
5032 /* Prevent unused argument(s) compilation warning */
5033 UNUSED(hi2c);
5034
5035 /* NOTE : This function should not be modified, when the callback is needed,
5036 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
5037 */
5038 }
5039
5040 /** @brief Slave Tx Transfer completed callback.
5041 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5042 * the configuration information for the specified I2C.
5043 * @retval None
5044 */
HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef * hi2c)5045 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
5046 {
5047 /* Prevent unused argument(s) compilation warning */
5048 UNUSED(hi2c);
5049
5050 /* NOTE : This function should not be modified, when the callback is needed,
5051 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
5052 */
5053 }
5054
5055 /**
5056 * @brief Slave Rx Transfer completed callback.
5057 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5058 * the configuration information for the specified I2C.
5059 * @retval None
5060 */
HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef * hi2c)5061 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
5062 {
5063 /* Prevent unused argument(s) compilation warning */
5064 UNUSED(hi2c);
5065
5066 /* NOTE : This function should not be modified, when the callback is needed,
5067 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
5068 */
5069 }
5070
5071 /**
5072 * @brief Slave Address Match callback.
5073 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5074 * the configuration information for the specified I2C.
5075 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition
5076 * @param AddrMatchCode Address Match Code
5077 * @retval None
5078 */
HAL_I2C_AddrCallback(I2C_HandleTypeDef * hi2c,uint8_t TransferDirection,uint16_t AddrMatchCode)5079 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
5080 {
5081 /* Prevent unused argument(s) compilation warning */
5082 UNUSED(hi2c);
5083 UNUSED(TransferDirection);
5084 UNUSED(AddrMatchCode);
5085
5086 /* NOTE : This function should not be modified, when the callback is needed,
5087 the HAL_I2C_AddrCallback() could be implemented in the user file
5088 */
5089 }
5090
5091 /**
5092 * @brief Listen Complete callback.
5093 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5094 * the configuration information for the specified I2C.
5095 * @retval None
5096 */
HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef * hi2c)5097 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
5098 {
5099 /* Prevent unused argument(s) compilation warning */
5100 UNUSED(hi2c);
5101
5102 /* NOTE : This function should not be modified, when the callback is needed,
5103 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
5104 */
5105 }
5106
5107 /**
5108 * @brief Memory Tx Transfer completed callback.
5109 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5110 * the configuration information for the specified I2C.
5111 * @retval None
5112 */
HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef * hi2c)5113 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
5114 {
5115 /* Prevent unused argument(s) compilation warning */
5116 UNUSED(hi2c);
5117
5118 /* NOTE : This function should not be modified, when the callback is needed,
5119 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
5120 */
5121 }
5122
5123 /**
5124 * @brief Memory Rx Transfer completed callback.
5125 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5126 * the configuration information for the specified I2C.
5127 * @retval None
5128 */
HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef * hi2c)5129 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
5130 {
5131 /* Prevent unused argument(s) compilation warning */
5132 UNUSED(hi2c);
5133
5134 /* NOTE : This function should not be modified, when the callback is needed,
5135 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
5136 */
5137 }
5138
5139 /**
5140 * @brief I2C error callback.
5141 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5142 * the configuration information for the specified I2C.
5143 * @retval None
5144 */
HAL_I2C_ErrorCallback(I2C_HandleTypeDef * hi2c)5145 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
5146 {
5147 /* Prevent unused argument(s) compilation warning */
5148 UNUSED(hi2c);
5149
5150 /* NOTE : This function should not be modified, when the callback is needed,
5151 the HAL_I2C_ErrorCallback could be implemented in the user file
5152 */
5153 }
5154
5155 /**
5156 * @brief I2C abort callback.
5157 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5158 * the configuration information for the specified I2C.
5159 * @retval None
5160 */
HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef * hi2c)5161 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
5162 {
5163 /* Prevent unused argument(s) compilation warning */
5164 UNUSED(hi2c);
5165
5166 /* NOTE : This function should not be modified, when the callback is needed,
5167 the HAL_I2C_AbortCpltCallback could be implemented in the user file
5168 */
5169 }
5170
5171 /**
5172 * @}
5173 */
5174
5175 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
5176 * @brief Peripheral State, Mode and Error functions
5177 *
5178 @verbatim
5179 ===============================================================================
5180 ##### Peripheral State, Mode and Error functions #####
5181 ===============================================================================
5182 [..]
5183 This subsection permit to get in run-time the status of the peripheral
5184 and the data flow.
5185
5186 @endverbatim
5187 * @{
5188 */
5189
5190 /**
5191 * @brief Return the I2C handle state.
5192 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5193 * the configuration information for the specified I2C.
5194 * @retval HAL state
5195 */
HAL_I2C_GetState(I2C_HandleTypeDef * hi2c)5196 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
5197 {
5198 /* Return I2C handle state */
5199 return hi2c->State;
5200 }
5201
5202 /**
5203 * @brief Returns the I2C Master, Slave, Memory or no mode.
5204 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5205 * the configuration information for I2C module
5206 * @retval HAL mode
5207 */
HAL_I2C_GetMode(I2C_HandleTypeDef * hi2c)5208 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
5209 {
5210 return hi2c->Mode;
5211 }
5212
5213 /**
5214 * @brief Return the I2C error code.
5215 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5216 * the configuration information for the specified I2C.
5217 * @retval I2C Error Code
5218 */
HAL_I2C_GetError(I2C_HandleTypeDef * hi2c)5219 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
5220 {
5221 return hi2c->ErrorCode;
5222 }
5223
5224 /**
5225 * @}
5226 */
5227
5228 /**
5229 * @}
5230 */
5231
5232 /** @addtogroup I2C_Private_Functions
5233 * @{
5234 */
5235
5236 /**
5237 * @brief Handle TXE flag for Master
5238 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5239 * the configuration information for I2C module
5240 * @retval None
5241 */
I2C_MasterTransmit_TXE(I2C_HandleTypeDef * hi2c)5242 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
5243 {
5244 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5245 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5246 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5247 uint32_t CurrentXferOptions = hi2c->XferOptions;
5248
5249 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5250 {
5251 /* Call TxCpltCallback() directly if no stop mode is set */
5252 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5253 {
5254 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5255
5256 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5257 hi2c->Mode = HAL_I2C_MODE_NONE;
5258 hi2c->State = HAL_I2C_STATE_READY;
5259
5260 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5261 hi2c->MasterTxCpltCallback(hi2c);
5262 #else
5263 HAL_I2C_MasterTxCpltCallback(hi2c);
5264 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5265 }
5266 else /* Generate Stop condition then Call TxCpltCallback() */
5267 {
5268 /* Disable EVT, BUF and ERR interrupt */
5269 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5270
5271 /* Generate Stop */
5272 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5273
5274 hi2c->PreviousState = I2C_STATE_NONE;
5275 hi2c->State = HAL_I2C_STATE_READY;
5276
5277 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5278 {
5279 hi2c->Mode = HAL_I2C_MODE_NONE;
5280 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5281 hi2c->MemTxCpltCallback(hi2c);
5282 #else
5283 HAL_I2C_MemTxCpltCallback(hi2c);
5284 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5285 }
5286 else
5287 {
5288 hi2c->Mode = HAL_I2C_MODE_NONE;
5289 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5290 hi2c->MasterTxCpltCallback(hi2c);
5291 #else
5292 HAL_I2C_MasterTxCpltCallback(hi2c);
5293 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5294 }
5295 }
5296 }
5297 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \
5298 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
5299 {
5300 if (hi2c->XferCount == 0U)
5301 {
5302 /* Disable BUF interrupt */
5303 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5304 }
5305 else
5306 {
5307 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5308 {
5309 I2C_MemoryTransmit_TXE_BTF(hi2c);
5310 }
5311 else
5312 {
5313 /* Write data to DR */
5314 hi2c->Instance->DR = *hi2c->pBuffPtr;
5315
5316 /* Increment Buffer pointer */
5317 hi2c->pBuffPtr++;
5318
5319 /* Update counter */
5320 hi2c->XferCount--;
5321 }
5322 }
5323 }
5324 else
5325 {
5326 /* Do nothing */
5327 }
5328 }
5329
5330 /**
5331 * @brief Handle BTF flag for Master transmitter
5332 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5333 * the configuration information for I2C module
5334 * @retval None
5335 */
I2C_MasterTransmit_BTF(I2C_HandleTypeDef * hi2c)5336 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
5337 {
5338 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5339 uint32_t CurrentXferOptions = hi2c->XferOptions;
5340
5341 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5342 {
5343 if (hi2c->XferCount != 0U)
5344 {
5345 /* Write data to DR */
5346 hi2c->Instance->DR = *hi2c->pBuffPtr;
5347
5348 /* Increment Buffer pointer */
5349 hi2c->pBuffPtr++;
5350
5351 /* Update counter */
5352 hi2c->XferCount--;
5353 }
5354 else
5355 {
5356 /* Call TxCpltCallback() directly if no stop mode is set */
5357 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
5358 {
5359 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5360
5361 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
5362 hi2c->Mode = HAL_I2C_MODE_NONE;
5363 hi2c->State = HAL_I2C_STATE_READY;
5364
5365 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5366 hi2c->MasterTxCpltCallback(hi2c);
5367 #else
5368 HAL_I2C_MasterTxCpltCallback(hi2c);
5369 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5370 }
5371 else /* Generate Stop condition then Call TxCpltCallback() */
5372 {
5373 /* Disable EVT, BUF and ERR interrupt */
5374 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5375
5376 /* Generate Stop */
5377 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5378
5379 hi2c->PreviousState = I2C_STATE_NONE;
5380 hi2c->State = HAL_I2C_STATE_READY;
5381 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5382 {
5383 hi2c->Mode = HAL_I2C_MODE_NONE;
5384 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5385 hi2c->MemTxCpltCallback(hi2c);
5386 #else
5387 HAL_I2C_MemTxCpltCallback(hi2c);
5388 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5389 }
5390 else
5391 {
5392 hi2c->Mode = HAL_I2C_MODE_NONE;
5393
5394 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5395 hi2c->MasterTxCpltCallback(hi2c);
5396 #else
5397 HAL_I2C_MasterTxCpltCallback(hi2c);
5398 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5399 }
5400 }
5401 }
5402 }
5403 else
5404 {
5405 /* Do nothing */
5406 }
5407 }
5408
5409 /**
5410 * @brief Handle TXE and BTF flag for Memory transmitter
5411 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5412 * the configuration information for I2C module
5413 * @retval None
5414 */
I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef * hi2c)5415 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)
5416 {
5417 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5418 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5419
5420 if (hi2c->EventCount == 0U)
5421 {
5422 /* If Memory address size is 8Bit */
5423 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
5424 {
5425 /* Send Memory Address */
5426 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5427
5428 hi2c->EventCount += 2U;
5429 }
5430 /* If Memory address size is 16Bit */
5431 else
5432 {
5433 /* Send MSB of Memory Address */
5434 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
5435
5436 hi2c->EventCount++;
5437 }
5438 }
5439 else if (hi2c->EventCount == 1U)
5440 {
5441 /* Send LSB of Memory Address */
5442 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
5443
5444 hi2c->EventCount++;
5445 }
5446 else if (hi2c->EventCount == 2U)
5447 {
5448 if (CurrentState == HAL_I2C_STATE_BUSY_RX)
5449 {
5450 /* Generate Restart */
5451 hi2c->Instance->CR1 |= I2C_CR1_START;
5452
5453 hi2c->EventCount++;
5454 }
5455 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5456 {
5457 /* Write data to DR */
5458 hi2c->Instance->DR = *hi2c->pBuffPtr;
5459
5460 /* Increment Buffer pointer */
5461 hi2c->pBuffPtr++;
5462
5463 /* Update counter */
5464 hi2c->XferCount--;
5465 }
5466 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
5467 {
5468 /* Generate Stop condition then Call TxCpltCallback() */
5469 /* Disable EVT, BUF and ERR interrupt */
5470 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5471
5472 /* Generate Stop */
5473 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5474
5475 hi2c->PreviousState = I2C_STATE_NONE;
5476 hi2c->State = HAL_I2C_STATE_READY;
5477 hi2c->Mode = HAL_I2C_MODE_NONE;
5478 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5479 hi2c->MemTxCpltCallback(hi2c);
5480 #else
5481 HAL_I2C_MemTxCpltCallback(hi2c);
5482 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5483 }
5484 else
5485 {
5486 /* Do nothing */
5487 }
5488 }
5489 else
5490 {
5491 /* Clear TXE and BTF flags */
5492 I2C_Flush_DR(hi2c);
5493 }
5494 }
5495
5496 /**
5497 * @brief Handle RXNE flag for Master
5498 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5499 * the configuration information for I2C module
5500 * @retval None
5501 */
I2C_MasterReceive_RXNE(I2C_HandleTypeDef * hi2c)5502 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
5503 {
5504 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5505 {
5506 uint32_t tmp;
5507
5508 tmp = hi2c->XferCount;
5509 if (tmp > 3U)
5510 {
5511 /* Read data from DR */
5512 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5513
5514 /* Increment Buffer pointer */
5515 hi2c->pBuffPtr++;
5516
5517 /* Update counter */
5518 hi2c->XferCount--;
5519
5520 if (hi2c->XferCount == (uint16_t)3)
5521 {
5522 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes
5523 on BTF subroutine */
5524 /* Disable BUF interrupt */
5525 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5526 }
5527 }
5528 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))
5529 {
5530 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)
5531 {
5532 /* Disable Acknowledge */
5533 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5534
5535 /* Disable EVT, BUF and ERR interrupt */
5536 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5537
5538 /* Read data from DR */
5539 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5540
5541 /* Increment Buffer pointer */
5542 hi2c->pBuffPtr++;
5543
5544 /* Update counter */
5545 hi2c->XferCount--;
5546
5547 hi2c->State = HAL_I2C_STATE_READY;
5548
5549 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5550 {
5551 hi2c->Mode = HAL_I2C_MODE_NONE;
5552 hi2c->PreviousState = I2C_STATE_NONE;
5553
5554 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5555 hi2c->MemRxCpltCallback(hi2c);
5556 #else
5557 HAL_I2C_MemRxCpltCallback(hi2c);
5558 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5559 }
5560 else
5561 {
5562 hi2c->Mode = HAL_I2C_MODE_NONE;
5563 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5564
5565 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5566 hi2c->MasterRxCpltCallback(hi2c);
5567 #else
5568 HAL_I2C_MasterRxCpltCallback(hi2c);
5569 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5570 }
5571 }
5572 else
5573 {
5574 /* Disable EVT, BUF and ERR interrupt */
5575 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
5576
5577 /* Read data from DR */
5578 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5579
5580 /* Increment Buffer pointer */
5581 hi2c->pBuffPtr++;
5582
5583 /* Update counter */
5584 hi2c->XferCount--;
5585
5586 hi2c->State = HAL_I2C_STATE_READY;
5587 hi2c->Mode = HAL_I2C_MODE_NONE;
5588
5589 /* Call user error callback */
5590 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5591 hi2c->ErrorCallback(hi2c);
5592 #else
5593 HAL_I2C_ErrorCallback(hi2c);
5594 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5595 }
5596 }
5597 else
5598 {
5599 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5600 on BTF subroutine if there is a reception delay between N-1 and N byte */
5601 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5602 }
5603 }
5604 }
5605
5606 /**
5607 * @brief Handle BTF flag for Master receiver
5608 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5609 * the configuration information for I2C module
5610 * @retval None
5611 */
I2C_MasterReceive_BTF(I2C_HandleTypeDef * hi2c)5612 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
5613 {
5614 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5615 uint32_t CurrentXferOptions = hi2c->XferOptions;
5616
5617 if (hi2c->XferCount == 4U)
5618 {
5619 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5620 on BTF subroutine if there is a reception delay between N-1 and N byte */
5621 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5622
5623 /* Read data from DR */
5624 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5625
5626 /* Increment Buffer pointer */
5627 hi2c->pBuffPtr++;
5628
5629 /* Update counter */
5630 hi2c->XferCount--;
5631 }
5632 else if (hi2c->XferCount == 3U)
5633 {
5634 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes
5635 on BTF subroutine if there is a reception delay between N-1 and N byte */
5636 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5637
5638 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))
5639 {
5640 /* Disable Acknowledge */
5641 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5642 }
5643
5644 /* Read data from DR */
5645 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5646
5647 /* Increment Buffer pointer */
5648 hi2c->pBuffPtr++;
5649
5650 /* Update counter */
5651 hi2c->XferCount--;
5652 }
5653 else if (hi2c->XferCount == 2U)
5654 {
5655 /* Prepare next transfer or stop current transfer */
5656 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))
5657 {
5658 /* Disable Acknowledge */
5659 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5660 }
5661 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))
5662 {
5663 /* Enable Acknowledge */
5664 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5665 }
5666 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)
5667 {
5668 /* Generate Stop */
5669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5670 }
5671 else
5672 {
5673 /* Do nothing */
5674 }
5675
5676 /* Read data from DR */
5677 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5678
5679 /* Increment Buffer pointer */
5680 hi2c->pBuffPtr++;
5681
5682 /* Update counter */
5683 hi2c->XferCount--;
5684
5685 /* Read data from DR */
5686 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5687
5688 /* Increment Buffer pointer */
5689 hi2c->pBuffPtr++;
5690
5691 /* Update counter */
5692 hi2c->XferCount--;
5693
5694 /* Disable EVT and ERR interrupt */
5695 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
5696
5697 hi2c->State = HAL_I2C_STATE_READY;
5698 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5699 {
5700 hi2c->Mode = HAL_I2C_MODE_NONE;
5701 hi2c->PreviousState = I2C_STATE_NONE;
5702 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5703 hi2c->MemRxCpltCallback(hi2c);
5704 #else
5705 HAL_I2C_MemRxCpltCallback(hi2c);
5706 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5707 }
5708 else
5709 {
5710 hi2c->Mode = HAL_I2C_MODE_NONE;
5711 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
5712 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5713 hi2c->MasterRxCpltCallback(hi2c);
5714 #else
5715 HAL_I2C_MasterRxCpltCallback(hi2c);
5716 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5717 }
5718 }
5719 else
5720 {
5721 /* Read data from DR */
5722 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
5723
5724 /* Increment Buffer pointer */
5725 hi2c->pBuffPtr++;
5726
5727 /* Update counter */
5728 hi2c->XferCount--;
5729 }
5730 }
5731
5732 /**
5733 * @brief Handle SB flag for Master
5734 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5735 * the configuration information for I2C module
5736 * @retval None
5737 */
I2C_Master_SB(I2C_HandleTypeDef * hi2c)5738 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c)
5739 {
5740 if (hi2c->Mode == HAL_I2C_MODE_MEM)
5741 {
5742 if (hi2c->EventCount == 0U)
5743 {
5744 /* Send slave address */
5745 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5746 }
5747 else
5748 {
5749 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5750 }
5751 }
5752 else
5753 {
5754 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
5755 {
5756 /* Send slave 7 Bits address */
5757 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
5758 {
5759 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
5760 }
5761 else
5762 {
5763 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
5764 }
5765
5766 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5767 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5768 {
5769 /* Enable DMA Request */
5770 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5771 }
5772 }
5773 else
5774 {
5775 if (hi2c->EventCount == 0U)
5776 {
5777 /* Send header of slave address */
5778 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
5779 }
5780 else if (hi2c->EventCount == 1U)
5781 {
5782 /* Send header of slave address */
5783 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
5784 }
5785 else
5786 {
5787 /* Do nothing */
5788 }
5789 }
5790 }
5791 }
5792
5793 /**
5794 * @brief Handle ADD10 flag for Master
5795 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5796 * the configuration information for I2C module
5797 * @retval None
5798 */
I2C_Master_ADD10(I2C_HandleTypeDef * hi2c)5799 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
5800 {
5801 /* Send slave address */
5802 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
5803
5804 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))
5805 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))
5806 {
5807 /* Enable DMA Request */
5808 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
5809 }
5810 }
5811
5812 /**
5813 * @brief Handle ADDR flag for Master
5814 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5815 * the configuration information for I2C module
5816 * @retval None
5817 */
I2C_Master_ADDR(I2C_HandleTypeDef * hi2c)5818 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
5819 {
5820 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
5821 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
5822 uint32_t CurrentXferOptions = hi2c->XferOptions;
5823 uint32_t Prev_State = hi2c->PreviousState;
5824
5825 if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
5826 {
5827 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
5828 {
5829 /* Clear ADDR flag */
5830 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5831 }
5832 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
5833 {
5834 /* Clear ADDR flag */
5835 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5836
5837 /* Generate Restart */
5838 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
5839
5840 hi2c->EventCount++;
5841 }
5842 else
5843 {
5844 if (hi2c->XferCount == 0U)
5845 {
5846 /* Clear ADDR flag */
5847 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5848
5849 /* Generate Stop */
5850 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5851 }
5852 else if (hi2c->XferCount == 1U)
5853 {
5854 if (CurrentXferOptions == I2C_NO_OPTION_FRAME)
5855 {
5856 /* Disable Acknowledge */
5857 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5858
5859 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
5860 {
5861 /* Disable Acknowledge */
5862 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5863
5864 /* Clear ADDR flag */
5865 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5866 }
5867 else
5868 {
5869 /* Clear ADDR flag */
5870 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5871
5872 /* Generate Stop */
5873 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5874 }
5875 }
5876 /* Prepare next transfer or stop current transfer */
5877 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
5878 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))
5879 {
5880 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5881 {
5882 /* Disable Acknowledge */
5883 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5884 }
5885 else
5886 {
5887 /* Enable Acknowledge */
5888 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5889 }
5890
5891 /* Clear ADDR flag */
5892 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5893 }
5894 else
5895 {
5896 /* Disable Acknowledge */
5897 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5898
5899 /* Clear ADDR flag */
5900 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5901
5902 /* Generate Stop */
5903 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
5904 }
5905 }
5906 else if (hi2c->XferCount == 2U)
5907 {
5908 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))
5909 {
5910 /* Disable Acknowledge */
5911 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5912
5913 /* Enable Pos */
5914 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
5915 }
5916 else
5917 {
5918 /* Enable Acknowledge */
5919 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5920 }
5921
5922 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5923 {
5924 /* Enable Last DMA bit */
5925 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5926 }
5927
5928 /* Clear ADDR flag */
5929 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5930 }
5931 else
5932 {
5933 /* Enable Acknowledge */
5934 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
5935
5936 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))
5937 {
5938 /* Enable Last DMA bit */
5939 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
5940 }
5941
5942 /* Clear ADDR flag */
5943 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5944 }
5945
5946 /* Reset Event counter */
5947 hi2c->EventCount = 0U;
5948 }
5949 }
5950 else
5951 {
5952 /* Clear ADDR flag */
5953 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
5954 }
5955 }
5956
5957 /**
5958 * @brief Handle TXE flag for Slave
5959 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
5960 * the configuration information for I2C module
5961 * @retval None
5962 */
I2C_SlaveTransmit_TXE(I2C_HandleTypeDef * hi2c)5963 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
5964 {
5965 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
5966 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
5967
5968 if (hi2c->XferCount != 0U)
5969 {
5970 /* Write data to DR */
5971 hi2c->Instance->DR = *hi2c->pBuffPtr;
5972
5973 /* Increment Buffer pointer */
5974 hi2c->pBuffPtr++;
5975
5976 /* Update counter */
5977 hi2c->XferCount--;
5978
5979 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
5980 {
5981 /* Last Byte is received, disable Interrupt */
5982 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
5983
5984 /* Set state at HAL_I2C_STATE_LISTEN */
5985 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
5986 hi2c->State = HAL_I2C_STATE_LISTEN;
5987
5988 /* Call the corresponding callback to inform upper layer of End of Transfer */
5989 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
5990 hi2c->SlaveTxCpltCallback(hi2c);
5991 #else
5992 HAL_I2C_SlaveTxCpltCallback(hi2c);
5993 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
5994 }
5995 }
5996 }
5997
5998 /**
5999 * @brief Handle BTF flag for Slave transmitter
6000 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6001 * the configuration information for I2C module
6002 * @retval None
6003 */
I2C_SlaveTransmit_BTF(I2C_HandleTypeDef * hi2c)6004 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
6005 {
6006 if (hi2c->XferCount != 0U)
6007 {
6008 /* Write data to DR */
6009 hi2c->Instance->DR = *hi2c->pBuffPtr;
6010
6011 /* Increment Buffer pointer */
6012 hi2c->pBuffPtr++;
6013
6014 /* Update counter */
6015 hi2c->XferCount--;
6016 }
6017 }
6018
6019 /**
6020 * @brief Handle RXNE flag for Slave
6021 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6022 * the configuration information for I2C module
6023 * @retval None
6024 */
I2C_SlaveReceive_RXNE(I2C_HandleTypeDef * hi2c)6025 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
6026 {
6027 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6028 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6029
6030 if (hi2c->XferCount != 0U)
6031 {
6032 /* Read data from DR */
6033 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6034
6035 /* Increment Buffer pointer */
6036 hi2c->pBuffPtr++;
6037
6038 /* Update counter */
6039 hi2c->XferCount--;
6040
6041 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6042 {
6043 /* Last Byte is received, disable Interrupt */
6044 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
6045
6046 /* Set state at HAL_I2C_STATE_LISTEN */
6047 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6048 hi2c->State = HAL_I2C_STATE_LISTEN;
6049
6050 /* Call the corresponding callback to inform upper layer of End of Transfer */
6051 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6052 hi2c->SlaveRxCpltCallback(hi2c);
6053 #else
6054 HAL_I2C_SlaveRxCpltCallback(hi2c);
6055 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6056 }
6057 }
6058 }
6059
6060 /**
6061 * @brief Handle BTF flag for Slave receiver
6062 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6063 * the configuration information for I2C module
6064 * @retval None
6065 */
I2C_SlaveReceive_BTF(I2C_HandleTypeDef * hi2c)6066 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
6067 {
6068 if (hi2c->XferCount != 0U)
6069 {
6070 /* Read data from DR */
6071 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6072
6073 /* Increment Buffer pointer */
6074 hi2c->pBuffPtr++;
6075
6076 /* Update counter */
6077 hi2c->XferCount--;
6078 }
6079 }
6080
6081 /**
6082 * @brief Handle ADD flag for Slave
6083 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6084 * the configuration information for I2C module
6085 * @param IT2Flags Interrupt2 flags to handle.
6086 * @retval None
6087 */
I2C_Slave_ADDR(I2C_HandleTypeDef * hi2c,uint32_t IT2Flags)6088 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)
6089 {
6090 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
6091 uint16_t SlaveAddrCode;
6092
6093 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6094 {
6095 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */
6096 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));
6097
6098 /* Transfer Direction requested by Master */
6099 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)
6100 {
6101 TransferDirection = I2C_DIRECTION_TRANSMIT;
6102 }
6103
6104 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)
6105 {
6106 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;
6107 }
6108 else
6109 {
6110 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;
6111 }
6112
6113 /* Process Unlocked */
6114 __HAL_UNLOCK(hi2c);
6115
6116 /* Call Slave Addr callback */
6117 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6118 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6119 #else
6120 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
6121 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6122 }
6123 else
6124 {
6125 /* Clear ADDR flag */
6126 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6127
6128 /* Process Unlocked */
6129 __HAL_UNLOCK(hi2c);
6130 }
6131 }
6132
6133 /**
6134 * @brief Handle STOPF flag for Slave
6135 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6136 * the configuration information for I2C module
6137 * @retval None
6138 */
I2C_Slave_STOPF(I2C_HandleTypeDef * hi2c)6139 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
6140 {
6141 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6142 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6143
6144 /* Disable EVT, BUF and ERR interrupt */
6145 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6146
6147 /* Clear STOPF flag */
6148 __HAL_I2C_CLEAR_STOPFLAG(hi2c);
6149
6150 /* Disable Acknowledge */
6151 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6152
6153 /* If a DMA is ongoing, Update handle size context */
6154 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6155 {
6156 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
6157 {
6158 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx));
6159
6160 if (hi2c->XferCount != 0U)
6161 {
6162 /* Set ErrorCode corresponding to a Non-Acknowledge */
6163 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6164 }
6165
6166 /* Disable, stop the current DMA */
6167 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6168
6169 /* Abort DMA Xfer if any */
6170 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)
6171 {
6172 /* Set the I2C DMA Abort callback :
6173 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6174 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6175
6176 /* Abort DMA RX */
6177 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6178 {
6179 /* Call Directly XferAbortCallback function in case of error */
6180 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6181 }
6182 }
6183 }
6184 else
6185 {
6186 hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx));
6187
6188 if (hi2c->XferCount != 0U)
6189 {
6190 /* Set ErrorCode corresponding to a Non-Acknowledge */
6191 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6192 }
6193
6194 /* Disable, stop the current DMA */
6195 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6196
6197 /* Abort DMA Xfer if any */
6198 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)
6199 {
6200 /* Set the I2C DMA Abort callback :
6201 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6202 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6203
6204 /* Abort DMA TX */
6205 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6206 {
6207 /* Call Directly XferAbortCallback function in case of error */
6208 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6209 }
6210 }
6211 }
6212 }
6213
6214 /* All data are not transferred, so set error code accordingly */
6215 if (hi2c->XferCount != 0U)
6216 {
6217 /* Store Last receive data if any */
6218 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
6219 {
6220 /* Read data from DR */
6221 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6222
6223 /* Increment Buffer pointer */
6224 hi2c->pBuffPtr++;
6225
6226 /* Update counter */
6227 hi2c->XferCount--;
6228 }
6229
6230 /* Store Last receive data if any */
6231 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6232 {
6233 /* Read data from DR */
6234 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6235
6236 /* Increment Buffer pointer */
6237 hi2c->pBuffPtr++;
6238
6239 /* Update counter */
6240 hi2c->XferCount--;
6241 }
6242
6243 if (hi2c->XferCount != 0U)
6244 {
6245 /* Set ErrorCode corresponding to a Non-Acknowledge */
6246 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
6247 }
6248 }
6249
6250 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6251 {
6252 /* Call the corresponding callback to inform upper layer of End of Transfer */
6253 I2C_ITError(hi2c);
6254 }
6255 else
6256 {
6257 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6258 {
6259 /* Set state at HAL_I2C_STATE_LISTEN */
6260 hi2c->PreviousState = I2C_STATE_NONE;
6261 hi2c->State = HAL_I2C_STATE_LISTEN;
6262
6263 /* Call the corresponding callback to inform upper layer of End of Transfer */
6264 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6265 hi2c->SlaveRxCpltCallback(hi2c);
6266 #else
6267 HAL_I2C_SlaveRxCpltCallback(hi2c);
6268 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6269 }
6270
6271 if (hi2c->State == HAL_I2C_STATE_LISTEN)
6272 {
6273 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6274 hi2c->PreviousState = I2C_STATE_NONE;
6275 hi2c->State = HAL_I2C_STATE_READY;
6276 hi2c->Mode = HAL_I2C_MODE_NONE;
6277
6278 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6279 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6280 hi2c->ListenCpltCallback(hi2c);
6281 #else
6282 HAL_I2C_ListenCpltCallback(hi2c);
6283 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6284 }
6285 else
6286 {
6287 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))
6288 {
6289 hi2c->PreviousState = I2C_STATE_NONE;
6290 hi2c->State = HAL_I2C_STATE_READY;
6291 hi2c->Mode = HAL_I2C_MODE_NONE;
6292
6293 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6294 hi2c->SlaveRxCpltCallback(hi2c);
6295 #else
6296 HAL_I2C_SlaveRxCpltCallback(hi2c);
6297 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6298 }
6299 }
6300 }
6301 }
6302
6303 /**
6304 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6305 * the configuration information for I2C module
6306 * @retval None
6307 */
I2C_Slave_AF(I2C_HandleTypeDef * hi2c)6308 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
6309 {
6310 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */
6311 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6312 uint32_t CurrentXferOptions = hi2c->XferOptions;
6313
6314 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \
6315 (CurrentState == HAL_I2C_STATE_LISTEN))
6316 {
6317 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6318
6319 /* Disable EVT, BUF and ERR interrupt */
6320 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6321
6322 /* Clear AF flag */
6323 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6324
6325 /* Disable Acknowledge */
6326 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6327
6328 hi2c->PreviousState = I2C_STATE_NONE;
6329 hi2c->State = HAL_I2C_STATE_READY;
6330 hi2c->Mode = HAL_I2C_MODE_NONE;
6331
6332 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6333 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6334 hi2c->ListenCpltCallback(hi2c);
6335 #else
6336 HAL_I2C_ListenCpltCallback(hi2c);
6337 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6338 }
6339 else if (CurrentState == HAL_I2C_STATE_BUSY_TX)
6340 {
6341 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6342 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6343 hi2c->State = HAL_I2C_STATE_READY;
6344 hi2c->Mode = HAL_I2C_MODE_NONE;
6345
6346 /* Disable EVT, BUF and ERR interrupt */
6347 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6348
6349 /* Clear AF flag */
6350 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6351
6352 /* Disable Acknowledge */
6353 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6354
6355 /* Clear TXE flag */
6356 I2C_Flush_DR(hi2c);
6357
6358 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6359 hi2c->SlaveTxCpltCallback(hi2c);
6360 #else
6361 HAL_I2C_SlaveTxCpltCallback(hi2c);
6362 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6363 }
6364 else
6365 {
6366 /* Clear AF flag only */
6367 /* State Listen, but XferOptions == FIRST or NEXT */
6368 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
6369 }
6370 }
6371
6372 /**
6373 * @brief I2C interrupts error process
6374 * @param hi2c I2C handle.
6375 * @retval None
6376 */
I2C_ITError(I2C_HandleTypeDef * hi2c)6377 static void I2C_ITError(I2C_HandleTypeDef *hi2c)
6378 {
6379 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6380 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6381 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6382 uint32_t CurrentError;
6383
6384 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))
6385 {
6386 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
6387 hi2c->Instance->CR1 &= ~I2C_CR1_POS;
6388 }
6389
6390 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
6391 {
6392 /* keep HAL_I2C_STATE_LISTEN */
6393 hi2c->PreviousState = I2C_STATE_NONE;
6394 hi2c->State = HAL_I2C_STATE_LISTEN;
6395 }
6396 else
6397 {
6398 /* If state is an abort treatment on going, don't change state */
6399 /* This change will be do later */
6400 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))
6401 {
6402 hi2c->State = HAL_I2C_STATE_READY;
6403 hi2c->Mode = HAL_I2C_MODE_NONE;
6404 }
6405 hi2c->PreviousState = I2C_STATE_NONE;
6406 }
6407
6408 /* Abort DMA transfer */
6409 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
6410 {
6411 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
6412
6413 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)
6414 {
6415 /* Set the DMA Abort callback :
6416 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6417 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
6418
6419 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
6420 {
6421 /* Disable I2C peripheral to prevent dummy data in buffer */
6422 __HAL_I2C_DISABLE(hi2c);
6423
6424 hi2c->State = HAL_I2C_STATE_READY;
6425
6426 /* Call Directly XferAbortCallback function in case of error */
6427 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
6428 }
6429 }
6430 else
6431 {
6432 /* Set the DMA Abort callback :
6433 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
6434 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
6435
6436 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
6437 {
6438 /* Store Last receive data if any */
6439 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6440 {
6441 /* Read data from DR */
6442 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6443
6444 /* Increment Buffer pointer */
6445 hi2c->pBuffPtr++;
6446 }
6447
6448 /* Disable I2C peripheral to prevent dummy data in buffer */
6449 __HAL_I2C_DISABLE(hi2c);
6450
6451 hi2c->State = HAL_I2C_STATE_READY;
6452
6453 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
6454 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
6455 }
6456 }
6457 }
6458 else if (hi2c->State == HAL_I2C_STATE_ABORT)
6459 {
6460 hi2c->State = HAL_I2C_STATE_READY;
6461 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
6462
6463 /* Store Last receive data if any */
6464 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6465 {
6466 /* Read data from DR */
6467 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6468
6469 /* Increment Buffer pointer */
6470 hi2c->pBuffPtr++;
6471 }
6472
6473 /* Disable I2C peripheral to prevent dummy data in buffer */
6474 __HAL_I2C_DISABLE(hi2c);
6475
6476 /* Call the corresponding callback to inform upper layer of End of Transfer */
6477 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6478 hi2c->AbortCpltCallback(hi2c);
6479 #else
6480 HAL_I2C_AbortCpltCallback(hi2c);
6481 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6482 }
6483 else
6484 {
6485 /* Store Last receive data if any */
6486 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
6487 {
6488 /* Read data from DR */
6489 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;
6490
6491 /* Increment Buffer pointer */
6492 hi2c->pBuffPtr++;
6493 }
6494
6495 /* Call user error callback */
6496 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6497 hi2c->ErrorCallback(hi2c);
6498 #else
6499 HAL_I2C_ErrorCallback(hi2c);
6500 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6501 }
6502
6503 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */
6504 CurrentError = hi2c->ErrorCode;
6505
6506 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \
6507 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \
6508 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \
6509 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))
6510 {
6511 /* Disable EVT, BUF and ERR interrupt */
6512 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
6513 }
6514
6515 /* So may inform upper layer that listen phase is stopped */
6516 /* during NACK error treatment */
6517 CurrentState = hi2c->State;
6518 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))
6519 {
6520 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
6521 hi2c->PreviousState = I2C_STATE_NONE;
6522 hi2c->State = HAL_I2C_STATE_READY;
6523 hi2c->Mode = HAL_I2C_MODE_NONE;
6524
6525 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
6526 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6527 hi2c->ListenCpltCallback(hi2c);
6528 #else
6529 HAL_I2C_ListenCpltCallback(hi2c);
6530 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6531 }
6532 }
6533
6534 /**
6535 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6536 * the configuration information for I2C module
6537 * @param DevAddress Target device address: The device 7 bits address value
6538 * in datasheet must be shifted to the left before calling the interface
6539 * @param Timeout Timeout duration
6540 * @param Tickstart Tick start value
6541 * @retval HAL status
6542 */
I2C_MasterRequestWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6543 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6544 {
6545 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6546 uint32_t CurrentXferOptions = hi2c->XferOptions;
6547
6548 /* Generate Start condition if first transfer */
6549 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6550 {
6551 /* Generate Start */
6552 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6553 }
6554 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
6555 {
6556 /* Generate ReStart */
6557 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6558 }
6559 else
6560 {
6561 /* Do nothing */
6562 }
6563
6564 /* Wait until SB flag is set */
6565 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6566 {
6567 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6568 {
6569 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6570 }
6571 return HAL_TIMEOUT;
6572 }
6573
6574 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6575 {
6576 /* Send slave address */
6577 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6578 }
6579 else
6580 {
6581 /* Send header of slave address */
6582 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6583
6584 /* Wait until ADD10 flag is set */
6585 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6586 {
6587 return HAL_ERROR;
6588 }
6589
6590 /* Send slave address */
6591 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6592 }
6593
6594 /* Wait until ADDR flag is set */
6595 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6596 {
6597 return HAL_ERROR;
6598 }
6599
6600 return HAL_OK;
6601 }
6602
6603 /**
6604 * @brief Master sends target device address for read request.
6605 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6606 * the configuration information for I2C module
6607 * @param DevAddress Target device address: The device 7 bits address value
6608 * in datasheet must be shifted to the left before calling the interface
6609 * @param Timeout Timeout duration
6610 * @param Tickstart Tick start value
6611 * @retval HAL status
6612 */
I2C_MasterRequestRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint32_t Timeout,uint32_t Tickstart)6613 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
6614 {
6615 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6616 uint32_t CurrentXferOptions = hi2c->XferOptions;
6617
6618 /* Enable Acknowledge */
6619 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6620
6621 /* Generate Start condition if first transfer */
6622 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
6623 {
6624 /* Generate Start */
6625 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6626 }
6627 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
6628 {
6629 /* Generate ReStart */
6630 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6631 }
6632 else
6633 {
6634 /* Do nothing */
6635 }
6636
6637 /* Wait until SB flag is set */
6638 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6639 {
6640 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6641 {
6642 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6643 }
6644 return HAL_TIMEOUT;
6645 }
6646
6647 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
6648 {
6649 /* Send slave address */
6650 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6651 }
6652 else
6653 {
6654 /* Send header of slave address */
6655 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
6656
6657 /* Wait until ADD10 flag is set */
6658 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
6659 {
6660 return HAL_ERROR;
6661 }
6662
6663 /* Send slave address */
6664 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
6665
6666 /* Wait until ADDR flag is set */
6667 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6668 {
6669 return HAL_ERROR;
6670 }
6671
6672 /* Clear ADDR flag */
6673 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6674
6675 /* Generate Restart */
6676 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6677
6678 /* Wait until SB flag is set */
6679 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6680 {
6681 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6682 {
6683 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6684 }
6685 return HAL_TIMEOUT;
6686 }
6687
6688 /* Send header of slave address */
6689 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
6690 }
6691
6692 /* Wait until ADDR flag is set */
6693 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6694 {
6695 return HAL_ERROR;
6696 }
6697
6698 return HAL_OK;
6699 }
6700
6701 /**
6702 * @brief Master sends target device address followed by internal memory address for write request.
6703 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6704 * the configuration information for I2C module
6705 * @param DevAddress Target device address: The device 7 bits address value
6706 * in datasheet must be shifted to the left before calling the interface
6707 * @param MemAddress Internal memory address
6708 * @param MemAddSize Size of internal memory address
6709 * @param Timeout Timeout duration
6710 * @param Tickstart Tick start value
6711 * @retval HAL status
6712 */
I2C_RequestMemoryWrite(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6713 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6714 {
6715 /* Generate Start */
6716 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6717
6718 /* Wait until SB flag is set */
6719 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6720 {
6721 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6722 {
6723 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6724 }
6725 return HAL_TIMEOUT;
6726 }
6727
6728 /* Send slave address */
6729 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6730
6731 /* Wait until ADDR flag is set */
6732 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6733 {
6734 return HAL_ERROR;
6735 }
6736
6737 /* Clear ADDR flag */
6738 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6739
6740 /* Wait until TXE flag is set */
6741 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6742 {
6743 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6744 {
6745 /* Generate Stop */
6746 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6747 }
6748 return HAL_ERROR;
6749 }
6750
6751 /* If Memory address size is 8Bit */
6752 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6753 {
6754 /* Send Memory Address */
6755 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6756 }
6757 /* If Memory address size is 16Bit */
6758 else
6759 {
6760 /* Send MSB of Memory Address */
6761 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6762
6763 /* Wait until TXE flag is set */
6764 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6765 {
6766 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6767 {
6768 /* Generate Stop */
6769 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6770 }
6771 return HAL_ERROR;
6772 }
6773
6774 /* Send LSB of Memory Address */
6775 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6776 }
6777
6778 return HAL_OK;
6779 }
6780
6781 /**
6782 * @brief Master sends target device address followed by internal memory address for read request.
6783 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
6784 * the configuration information for I2C module
6785 * @param DevAddress Target device address: The device 7 bits address value
6786 * in datasheet must be shifted to the left before calling the interface
6787 * @param MemAddress Internal memory address
6788 * @param MemAddSize Size of internal memory address
6789 * @param Timeout Timeout duration
6790 * @param Tickstart Tick start value
6791 * @retval HAL status
6792 */
I2C_RequestMemoryRead(I2C_HandleTypeDef * hi2c,uint16_t DevAddress,uint16_t MemAddress,uint16_t MemAddSize,uint32_t Timeout,uint32_t Tickstart)6793 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
6794 {
6795 /* Enable Acknowledge */
6796 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6797
6798 /* Generate Start */
6799 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6800
6801 /* Wait until SB flag is set */
6802 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6803 {
6804 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6805 {
6806 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6807 }
6808 return HAL_TIMEOUT;
6809 }
6810
6811 /* Send slave address */
6812 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
6813
6814 /* Wait until ADDR flag is set */
6815 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6816 {
6817 return HAL_ERROR;
6818 }
6819
6820 /* Clear ADDR flag */
6821 __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
6822
6823 /* Wait until TXE flag is set */
6824 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6825 {
6826 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6827 {
6828 /* Generate Stop */
6829 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6830 }
6831 return HAL_ERROR;
6832 }
6833
6834 /* If Memory address size is 8Bit */
6835 if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
6836 {
6837 /* Send Memory Address */
6838 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6839 }
6840 /* If Memory address size is 16Bit */
6841 else
6842 {
6843 /* Send MSB of Memory Address */
6844 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
6845
6846 /* Wait until TXE flag is set */
6847 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6848 {
6849 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6850 {
6851 /* Generate Stop */
6852 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6853 }
6854 return HAL_ERROR;
6855 }
6856
6857 /* Send LSB of Memory Address */
6858 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
6859 }
6860
6861 /* Wait until TXE flag is set */
6862 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
6863 {
6864 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
6865 {
6866 /* Generate Stop */
6867 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6868 }
6869 return HAL_ERROR;
6870 }
6871
6872 /* Generate Restart */
6873 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
6874
6875 /* Wait until SB flag is set */
6876 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
6877 {
6878 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
6879 {
6880 hi2c->ErrorCode = HAL_I2C_WRONG_START;
6881 }
6882 return HAL_TIMEOUT;
6883 }
6884
6885 /* Send slave address */
6886 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
6887
6888 /* Wait until ADDR flag is set */
6889 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
6890 {
6891 return HAL_ERROR;
6892 }
6893
6894 return HAL_OK;
6895 }
6896
6897 /**
6898 * @brief DMA I2C process complete callback.
6899 * @param hdma DMA handle
6900 * @retval None
6901 */
I2C_DMAXferCplt(DMA_HandleTypeDef * hdma)6902 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
6903 {
6904 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
6905
6906 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
6907 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
6908 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;
6909 uint32_t CurrentXferOptions = hi2c->XferOptions;
6910
6911 /* Disable EVT and ERR interrupt */
6912 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6913
6914 /* Clear Complete callback */
6915 if (hi2c->hdmatx != NULL)
6916 {
6917 hi2c->hdmatx->XferCpltCallback = NULL;
6918 }
6919 if (hi2c->hdmarx != NULL)
6920 {
6921 hi2c->hdmarx->XferCpltCallback = NULL;
6922 }
6923
6924 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
6925 {
6926 /* Disable DMA Request */
6927 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6928
6929 hi2c->XferCount = 0U;
6930
6931 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)
6932 {
6933 /* Set state at HAL_I2C_STATE_LISTEN */
6934 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
6935 hi2c->State = HAL_I2C_STATE_LISTEN;
6936
6937 /* Call the corresponding callback to inform upper layer of End of Transfer */
6938 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6939 hi2c->SlaveTxCpltCallback(hi2c);
6940 #else
6941 HAL_I2C_SlaveTxCpltCallback(hi2c);
6942 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6943 }
6944 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)
6945 {
6946 /* Set state at HAL_I2C_STATE_LISTEN */
6947 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
6948 hi2c->State = HAL_I2C_STATE_LISTEN;
6949
6950 /* Call the corresponding callback to inform upper layer of End of Transfer */
6951 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6952 hi2c->SlaveRxCpltCallback(hi2c);
6953 #else
6954 HAL_I2C_SlaveRxCpltCallback(hi2c);
6955 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
6956 }
6957 else
6958 {
6959 /* Do nothing */
6960 }
6961
6962 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */
6963 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6964 }
6965 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */
6966 else if (hi2c->Mode != HAL_I2C_MODE_NONE)
6967 {
6968 if (hi2c->XferCount == (uint16_t)1)
6969 {
6970 /* Disable Acknowledge */
6971 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
6972 }
6973
6974 /* Disable EVT and ERR interrupt */
6975 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
6976
6977 /* Prepare next transfer or stop current transfer */
6978 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))
6979 {
6980 /* Generate Stop */
6981 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
6982 }
6983
6984 /* Disable Last DMA */
6985 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
6986
6987 /* Disable DMA Request */
6988 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
6989
6990 hi2c->XferCount = 0U;
6991
6992 /* Check if Errors has been detected during transfer */
6993 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
6994 {
6995 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
6996 hi2c->ErrorCallback(hi2c);
6997 #else
6998 HAL_I2C_ErrorCallback(hi2c);
6999 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7000 }
7001 else
7002 {
7003 hi2c->State = HAL_I2C_STATE_READY;
7004
7005 if (hi2c->Mode == HAL_I2C_MODE_MEM)
7006 {
7007 hi2c->Mode = HAL_I2C_MODE_NONE;
7008 hi2c->PreviousState = I2C_STATE_NONE;
7009
7010 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7011 hi2c->MemRxCpltCallback(hi2c);
7012 #else
7013 HAL_I2C_MemRxCpltCallback(hi2c);
7014 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7015 }
7016 else
7017 {
7018 hi2c->Mode = HAL_I2C_MODE_NONE;
7019 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
7020
7021 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7022 hi2c->MasterRxCpltCallback(hi2c);
7023 #else
7024 HAL_I2C_MasterRxCpltCallback(hi2c);
7025 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7026 }
7027 }
7028 }
7029 else
7030 {
7031 /* Do nothing */
7032 }
7033 }
7034
7035 /**
7036 * @brief DMA I2C communication error callback.
7037 * @param hdma DMA handle
7038 * @retval None
7039 */
I2C_DMAError(DMA_HandleTypeDef * hdma)7040 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
7041 {
7042 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7043
7044 /* Clear Complete callback */
7045 if (hi2c->hdmatx != NULL)
7046 {
7047 hi2c->hdmatx->XferCpltCallback = NULL;
7048 }
7049 if (hi2c->hdmarx != NULL)
7050 {
7051 hi2c->hdmarx->XferCpltCallback = NULL;
7052 }
7053
7054 /* Disable Acknowledge */
7055 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7056
7057 hi2c->XferCount = 0U;
7058 hi2c->State = HAL_I2C_STATE_READY;
7059 hi2c->Mode = HAL_I2C_MODE_NONE;
7060 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
7061
7062 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7063 hi2c->ErrorCallback(hi2c);
7064 #else
7065 HAL_I2C_ErrorCallback(hi2c);
7066 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7067 }
7068
7069 /**
7070 * @brief DMA I2C communication abort callback
7071 * (To be called at end of DMA Abort procedure).
7072 * @param hdma DMA handle.
7073 * @retval None
7074 */
I2C_DMAAbort(DMA_HandleTypeDef * hdma)7075 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
7076 {
7077 __IO uint32_t count = 0U;
7078 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
7079
7080 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
7081 HAL_I2C_StateTypeDef CurrentState = hi2c->State;
7082
7083 /* During abort treatment, check that there is no pending STOP request */
7084 /* Wait until STOP flag is reset */
7085 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);
7086 do
7087 {
7088 if (count == 0U)
7089 {
7090 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7091 break;
7092 }
7093 count--;
7094 }
7095 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7096
7097 /* Clear Complete callback */
7098 if (hi2c->hdmatx != NULL)
7099 {
7100 hi2c->hdmatx->XferCpltCallback = NULL;
7101 }
7102 if (hi2c->hdmarx != NULL)
7103 {
7104 hi2c->hdmarx->XferCpltCallback = NULL;
7105 }
7106
7107 /* Disable Acknowledge */
7108 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7109
7110 hi2c->XferCount = 0U;
7111
7112 /* Reset XferAbortCallback */
7113 if (hi2c->hdmatx != NULL)
7114 {
7115 hi2c->hdmatx->XferAbortCallback = NULL;
7116 }
7117 if (hi2c->hdmarx != NULL)
7118 {
7119 hi2c->hdmarx->XferAbortCallback = NULL;
7120 }
7121
7122 /* Disable I2C peripheral to prevent dummy data in buffer */
7123 __HAL_I2C_DISABLE(hi2c);
7124
7125 /* Check if come from abort from user */
7126 if (hi2c->State == HAL_I2C_STATE_ABORT)
7127 {
7128 hi2c->State = HAL_I2C_STATE_READY;
7129 hi2c->Mode = HAL_I2C_MODE_NONE;
7130 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
7131
7132 /* Call the corresponding callback to inform upper layer of End of Transfer */
7133 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7134 hi2c->AbortCpltCallback(hi2c);
7135 #else
7136 HAL_I2C_AbortCpltCallback(hi2c);
7137 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7138 }
7139 else
7140 {
7141 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)
7142 {
7143 /* Renable I2C peripheral */
7144 __HAL_I2C_ENABLE(hi2c);
7145
7146 /* Enable Acknowledge */
7147 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
7148
7149 /* keep HAL_I2C_STATE_LISTEN */
7150 hi2c->PreviousState = I2C_STATE_NONE;
7151 hi2c->State = HAL_I2C_STATE_LISTEN;
7152 }
7153 else
7154 {
7155 hi2c->State = HAL_I2C_STATE_READY;
7156 hi2c->Mode = HAL_I2C_MODE_NONE;
7157 }
7158
7159 /* Call the corresponding callback to inform upper layer of End of Transfer */
7160 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
7161 hi2c->ErrorCallback(hi2c);
7162 #else
7163 HAL_I2C_ErrorCallback(hi2c);
7164 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
7165 }
7166 }
7167
7168 /**
7169 * @brief This function handles I2C Communication Timeout.
7170 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7171 * the configuration information for I2C module
7172 * @param Flag specifies the I2C flag to check.
7173 * @param Status The new Flag status (SET or RESET).
7174 * @param Timeout Timeout duration
7175 * @param Tickstart Tick start value
7176 * @retval HAL status
7177 */
I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,FlagStatus Status,uint32_t Timeout,uint32_t Tickstart)7178 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
7179 {
7180 /* Wait until flag is set */
7181 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
7182 {
7183 /* Check for the Timeout */
7184 if (Timeout != HAL_MAX_DELAY)
7185 {
7186 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7187 {
7188 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
7189 {
7190 hi2c->PreviousState = I2C_STATE_NONE;
7191 hi2c->State = HAL_I2C_STATE_READY;
7192 hi2c->Mode = HAL_I2C_MODE_NONE;
7193 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7194
7195 /* Process Unlocked */
7196 __HAL_UNLOCK(hi2c);
7197
7198 return HAL_ERROR;
7199 }
7200 }
7201 }
7202 }
7203 return HAL_OK;
7204 }
7205
7206 /**
7207 * @brief This function handles I2C Communication Timeout for Master addressing phase.
7208 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7209 * the configuration information for I2C module
7210 * @param Flag specifies the I2C flag to check.
7211 * @param Timeout Timeout duration
7212 * @param Tickstart Tick start value
7213 * @retval HAL status
7214 */
I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Flag,uint32_t Timeout,uint32_t Tickstart)7215 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
7216 {
7217 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
7218 {
7219 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7220 {
7221 /* Generate Stop */
7222 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
7223
7224 /* Clear AF Flag */
7225 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7226
7227 hi2c->PreviousState = I2C_STATE_NONE;
7228 hi2c->State = HAL_I2C_STATE_READY;
7229 hi2c->Mode = HAL_I2C_MODE_NONE;
7230 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7231
7232 /* Process Unlocked */
7233 __HAL_UNLOCK(hi2c);
7234
7235 return HAL_ERROR;
7236 }
7237
7238 /* Check for the Timeout */
7239 if (Timeout != HAL_MAX_DELAY)
7240 {
7241 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7242 {
7243 if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
7244 {
7245 hi2c->PreviousState = I2C_STATE_NONE;
7246 hi2c->State = HAL_I2C_STATE_READY;
7247 hi2c->Mode = HAL_I2C_MODE_NONE;
7248 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7249
7250 /* Process Unlocked */
7251 __HAL_UNLOCK(hi2c);
7252
7253 return HAL_ERROR;
7254 }
7255 }
7256 }
7257 }
7258 return HAL_OK;
7259 }
7260
7261 /**
7262 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
7263 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7264 * the configuration information for the specified I2C.
7265 * @param Timeout Timeout duration
7266 * @param Tickstart Tick start value
7267 * @retval HAL status
7268 */
I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7269 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7270 {
7271 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
7272 {
7273 /* Check if a NACK is detected */
7274 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7275 {
7276 return HAL_ERROR;
7277 }
7278
7279 /* Check for the Timeout */
7280 if (Timeout != HAL_MAX_DELAY)
7281 {
7282 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7283 {
7284 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
7285 {
7286 hi2c->PreviousState = I2C_STATE_NONE;
7287 hi2c->State = HAL_I2C_STATE_READY;
7288 hi2c->Mode = HAL_I2C_MODE_NONE;
7289 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7290
7291 /* Process Unlocked */
7292 __HAL_UNLOCK(hi2c);
7293
7294 return HAL_ERROR;
7295 }
7296 }
7297 }
7298 }
7299 return HAL_OK;
7300 }
7301
7302 /**
7303 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
7304 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7305 * the configuration information for the specified I2C.
7306 * @param Timeout Timeout duration
7307 * @param Tickstart Tick start value
7308 * @retval HAL status
7309 */
I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7310 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7311 {
7312 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
7313 {
7314 /* Check if a NACK is detected */
7315 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7316 {
7317 return HAL_ERROR;
7318 }
7319
7320 /* Check for the Timeout */
7321 if (Timeout != HAL_MAX_DELAY)
7322 {
7323 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7324 {
7325 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
7326 {
7327 hi2c->PreviousState = I2C_STATE_NONE;
7328 hi2c->State = HAL_I2C_STATE_READY;
7329 hi2c->Mode = HAL_I2C_MODE_NONE;
7330 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7331
7332 /* Process Unlocked */
7333 __HAL_UNLOCK(hi2c);
7334
7335 return HAL_ERROR;
7336 }
7337 }
7338 }
7339 }
7340 return HAL_OK;
7341 }
7342
7343 /**
7344 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
7345 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7346 * the configuration information for the specified I2C.
7347 * @param Timeout Timeout duration
7348 * @param Tickstart Tick start value
7349 * @retval HAL status
7350 */
I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7351 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7352 {
7353 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
7354 {
7355 /* Check if a NACK is detected */
7356 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
7357 {
7358 return HAL_ERROR;
7359 }
7360
7361 /* Check for the Timeout */
7362 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7363 {
7364 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
7365 {
7366 hi2c->PreviousState = I2C_STATE_NONE;
7367 hi2c->State = HAL_I2C_STATE_READY;
7368 hi2c->Mode = HAL_I2C_MODE_NONE;
7369 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7370
7371 /* Process Unlocked */
7372 __HAL_UNLOCK(hi2c);
7373
7374 return HAL_ERROR;
7375 }
7376 }
7377 }
7378 return HAL_OK;
7379 }
7380
7381 /**
7382 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.
7383 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7384 * the configuration information for the specified I2C.
7385 * @retval HAL status
7386 */
I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef * hi2c)7387 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)
7388 {
7389 __IO uint32_t count = 0U;
7390
7391 /* Wait until STOP flag is reset */
7392 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);
7393 do
7394 {
7395 count--;
7396 if (count == 0U)
7397 {
7398 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7399
7400 return HAL_ERROR;
7401 }
7402 }
7403 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);
7404
7405 return HAL_OK;
7406 }
7407
7408 /**
7409 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
7410 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7411 * the configuration information for the specified I2C.
7412 * @param Timeout Timeout duration
7413 * @param Tickstart Tick start value
7414 * @retval HAL status
7415 */
I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef * hi2c,uint32_t Timeout,uint32_t Tickstart)7416 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
7417 {
7418
7419 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
7420 {
7421 /* Check if a STOPF is detected */
7422 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
7423 {
7424 /* Clear STOP Flag */
7425 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
7426
7427 hi2c->PreviousState = I2C_STATE_NONE;
7428 hi2c->State = HAL_I2C_STATE_READY;
7429 hi2c->Mode = HAL_I2C_MODE_NONE;
7430 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE;
7431
7432 /* Process Unlocked */
7433 __HAL_UNLOCK(hi2c);
7434
7435 return HAL_ERROR;
7436 }
7437
7438 /* Check for the Timeout */
7439 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
7440 {
7441 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
7442 {
7443 hi2c->PreviousState = I2C_STATE_NONE;
7444 hi2c->State = HAL_I2C_STATE_READY;
7445 hi2c->Mode = HAL_I2C_MODE_NONE;
7446 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
7447
7448 /* Process Unlocked */
7449 __HAL_UNLOCK(hi2c);
7450
7451 return HAL_ERROR;
7452 }
7453 }
7454 }
7455 return HAL_OK;
7456 }
7457
7458 /**
7459 * @brief This function handles Acknowledge failed detection during an I2C Communication.
7460 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
7461 * the configuration information for the specified I2C.
7462 * @retval HAL status
7463 */
I2C_IsAcknowledgeFailed(I2C_HandleTypeDef * hi2c)7464 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
7465 {
7466 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
7467 {
7468 /* Clear NACKF Flag */
7469 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
7470
7471 hi2c->PreviousState = I2C_STATE_NONE;
7472 hi2c->State = HAL_I2C_STATE_READY;
7473 hi2c->Mode = HAL_I2C_MODE_NONE;
7474 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
7475
7476 /* Process Unlocked */
7477 __HAL_UNLOCK(hi2c);
7478
7479 return HAL_ERROR;
7480 }
7481 return HAL_OK;
7482 }
7483
7484 /**
7485 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
7486 * @param hi2c I2C handle.
7487 * @retval None
7488 */
I2C_ConvertOtherXferOptions(I2C_HandleTypeDef * hi2c)7489 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
7490 {
7491 /* if user set XferOptions to I2C_OTHER_FRAME */
7492 /* it request implicitly to generate a restart condition */
7493 /* set XferOptions to I2C_FIRST_FRAME */
7494 if (hi2c->XferOptions == I2C_OTHER_FRAME)
7495 {
7496 hi2c->XferOptions = I2C_FIRST_FRAME;
7497 }
7498 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */
7499 /* it request implicitly to generate a restart condition */
7500 /* then generate a stop condition at the end of transfer */
7501 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */
7502 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)
7503 {
7504 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;
7505 }
7506 else
7507 {
7508 /* Nothing to do */
7509 }
7510 }
7511
7512 /**
7513 * @}
7514 */
7515
7516 #endif /* HAL_I2C_MODULE_ENABLED */
7517 /**
7518 * @}
7519 */
7520
7521 /**
7522 * @}
7523 */
7524
7525
