1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_tsc.h 4 * @author MCD Application Team 5 * @brief Header file of TSC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L0xx_HAL_TSC_H 21 #define STM32L0xx_HAL_TSC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l0xx_hal_def.h" 29 30 #if defined(TSC) 31 32 /** @addtogroup STM32L0xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup TSC 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup TSC_Exported_Types TSC Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief TSC state structure definition 47 */ 48 typedef enum 49 { 50 HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ 51 HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ 52 HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ 53 HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ 54 } HAL_TSC_StateTypeDef; 55 56 /** 57 * @brief TSC group status structure definition 58 */ 59 typedef enum 60 { 61 TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ 62 TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ 63 } TSC_GroupStatusTypeDef; 64 65 /** 66 * @brief TSC init structure definition 67 */ 68 typedef struct 69 { 70 uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length 71 This parameter can be a value of @ref TSC_CTPulseHL_Config */ 72 uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length 73 This parameter can be a value of @ref TSC_CTPulseLL_Config */ 74 FunctionalState SpreadSpectrum; /*!< Spread spectrum activation 75 This parameter can be set to ENABLE or DISABLE. */ 76 uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation 77 This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ 78 uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler 79 This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ 80 uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler 81 This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ 82 uint32_t MaxCountValue; /*!< Max count value 83 This parameter can be a value of @ref TSC_MaxCount_Value */ 84 uint32_t IODefaultMode; /*!< IO default mode 85 This parameter can be a value of @ref TSC_IO_Default_Mode */ 86 uint32_t SynchroPinPolarity; /*!< Synchro pin polarity 87 This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ 88 uint32_t AcquisitionMode; /*!< Acquisition mode 89 This parameter can be a value of @ref TSC_Acquisition_Mode */ 90 FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation 91 This parameter can be set to ENABLE or DISABLE. */ 92 uint32_t ChannelIOs; /*!< Channel IOs mask */ 93 uint32_t ShieldIOs; /*!< Shield IOs mask */ 94 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 95 } TSC_InitTypeDef; 96 97 /** 98 * @brief TSC IOs configuration structure definition 99 */ 100 typedef struct 101 { 102 uint32_t ChannelIOs; /*!< Channel IOs mask */ 103 uint32_t ShieldIOs; /*!< Shield IOs mask */ 104 uint32_t SamplingIOs; /*!< Sampling IOs mask */ 105 } TSC_IOConfigTypeDef; 106 107 /** 108 * @brief TSC handle Structure definition 109 */ 110 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 111 typedef struct __TSC_HandleTypeDef 112 #else 113 typedef struct 114 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 115 { 116 TSC_TypeDef *Instance; /*!< Register base address */ 117 TSC_InitTypeDef Init; /*!< Initialization parameters */ 118 __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ 119 HAL_LockTypeDef Lock; /*!< Lock feature */ 120 __IO uint32_t ErrorCode; /*!< TSC Error code */ 121 122 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 123 void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ 124 void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ 125 126 void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ 127 void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ 128 129 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 130 } TSC_HandleTypeDef; 131 132 enum 133 { 134 TSC_GROUP1_IDX = 0x00UL, 135 TSC_GROUP2_IDX, 136 TSC_GROUP3_IDX, 137 TSC_GROUP4_IDX, 138 TSC_GROUP5_IDX, 139 TSC_GROUP6_IDX, 140 TSC_GROUP7_IDX, 141 TSC_GROUP8_IDX, 142 TSC_NB_OF_GROUPS 143 }; 144 145 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 146 /** 147 * @brief HAL TSC Callback ID enumeration definition 148 */ 149 typedef enum 150 { 151 HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ 152 HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ 153 154 HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ 155 HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ 156 157 } HAL_TSC_CallbackIDTypeDef; 158 159 /** 160 * @brief HAL TSC Callback pointer definition 161 */ 162 typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ 163 164 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 165 166 /** 167 * @} 168 */ 169 170 /* Exported constants --------------------------------------------------------*/ 171 /** @defgroup TSC_Exported_Constants TSC Exported Constants 172 * @{ 173 */ 174 175 /** @defgroup TSC_Error_Code_definition TSC Error Code definition 176 * @brief TSC Error Code definition 177 * @{ 178 */ 179 #define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ 180 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 181 #define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ 182 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 183 /** 184 * @} 185 */ 186 187 /** @defgroup TSC_CTPulseHL_Config CTPulse High Length 188 * @{ 189 */ 190 #define TSC_CTPH_1CYCLE 0x00000000UL 191 /*!< Charge transfer pulse high during 1 cycle (PGCLK) */ 192 #define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 193 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */ 194 #define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 195 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */ 196 #define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 197 /*!< Charge transfer pulse high during 4 cycles (PGCLK) */ 198 #define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 199 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */ 200 #define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 201 /*!< Charge transfer pulse high during 6 cycles (PGCLK) */ 202 #define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 203 /*!< Charge transfer pulse high during 7 cycles (PGCLK) */ 204 #define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 205 /*!< Charge transfer pulse high during 8 cycles (PGCLK) */ 206 #define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 207 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */ 208 #define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) 209 /*!< Charge transfer pulse high during 10 cycles (PGCLK) */ 210 #define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) 211 /*!< Charge transfer pulse high during 11 cycles (PGCLK) */ 212 #define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 213 /*!< Charge transfer pulse high during 12 cycles (PGCLK) */ 214 #define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) 215 /*!< Charge transfer pulse high during 13 cycles (PGCLK) */ 216 #define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) 217 /*!< Charge transfer pulse high during 14 cycles (PGCLK) */ 218 #define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) 219 /*!< Charge transfer pulse high during 15 cycles (PGCLK) */ 220 #define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) 221 /*!< Charge transfer pulse high during 16 cycles (PGCLK) */ 222 /** 223 * @} 224 */ 225 226 /** @defgroup TSC_CTPulseLL_Config CTPulse Low Length 227 * @{ 228 */ 229 #define TSC_CTPL_1CYCLE 0x00000000UL 230 /*!< Charge transfer pulse low during 1 cycle (PGCLK) */ 231 #define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 232 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */ 233 #define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 234 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */ 235 #define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 236 /*!< Charge transfer pulse low during 4 cycles (PGCLK) */ 237 #define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 238 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */ 239 #define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 240 /*!< Charge transfer pulse low during 6 cycles (PGCLK) */ 241 #define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 242 /*!< Charge transfer pulse low during 7 cycles (PGCLK) */ 243 #define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 244 /*!< Charge transfer pulse low during 8 cycles (PGCLK) */ 245 #define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 246 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */ 247 #define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) 248 /*!< Charge transfer pulse low during 10 cycles (PGCLK) */ 249 #define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) 250 /*!< Charge transfer pulse low during 11 cycles (PGCLK) */ 251 #define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 252 /*!< Charge transfer pulse low during 12 cycles (PGCLK) */ 253 #define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) 254 /*!< Charge transfer pulse low during 13 cycles (PGCLK) */ 255 #define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) 256 /*!< Charge transfer pulse low during 14 cycles (PGCLK) */ 257 #define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) 258 /*!< Charge transfer pulse low during 15 cycles (PGCLK) */ 259 #define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) 260 /*!< Charge transfer pulse low during 16 cycles (PGCLK) */ 261 /** 262 * @} 263 */ 264 265 /** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler 266 * @{ 267 */ 268 #define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ 269 #define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ 270 /** 271 * @} 272 */ 273 274 /** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler 275 * @{ 276 */ 277 #define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ 278 #define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ 279 #define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ 280 #define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ 281 #define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ 282 #define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ 283 #define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ 284 #define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup TSC_MaxCount_Value Max Count Value 290 * @{ 291 */ 292 #define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ 293 #define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ 294 #define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ 295 #define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ 296 #define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ 297 #define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ 298 #define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ 299 /** 300 * @} 301 */ 302 303 /** @defgroup TSC_IO_Default_Mode IO Default Mode 304 * @{ 305 */ 306 #define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ 307 #define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ 308 /** 309 * @} 310 */ 311 312 /** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity 313 * @{ 314 */ 315 #define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ 316 #define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ 317 /** 318 * @} 319 */ 320 321 /** @defgroup TSC_Acquisition_Mode Acquisition Mode 322 * @{ 323 */ 324 #define TSC_ACQ_MODE_NORMAL 0x00000000UL 325 /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ 326 #define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM 327 /*!< Synchronized acquisition mode (acquisition starts if START bit is set and 328 when the selected signal is detected on the SYNC input pin) */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup TSC_interrupts_definition Interrupts definition 334 * @{ 335 */ 336 #define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ 337 #define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup TSC_flags_definition Flags definition 343 * @{ 344 */ 345 #define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ 346 #define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup TSC_Group_definition Group definition 352 * @{ 353 */ 354 #define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) 355 #define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) 356 #define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) 357 #define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) 358 #define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) 359 #define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) 360 #define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX) 361 #define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX) 362 363 #define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ 364 #define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ 365 #define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ 366 #define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ 367 368 #define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ 369 #define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ 370 #define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ 371 #define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ 372 373 #define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ 374 #define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ 375 #define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ 376 #define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ 377 378 #define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ 379 #define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ 380 #define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ 381 #define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ 382 383 #define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ 384 #define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ 385 #define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ 386 #define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ 387 388 #define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ 389 #define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ 390 #define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */ 391 #define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */ 392 393 #define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */ 394 #define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */ 395 #define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */ 396 #define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */ 397 398 #define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */ 399 #define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */ 400 #define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */ 401 #define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */ 402 /** 403 * @} 404 */ 405 406 /** 407 * @} 408 */ 409 410 /* Exported macros -----------------------------------------------------------*/ 411 412 /** @defgroup TSC_Exported_Macros TSC Exported Macros 413 * @{ 414 */ 415 416 /** @brief Reset TSC handle state. 417 * @param __HANDLE__ TSC handle 418 * @retval None 419 */ 420 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 421 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 422 (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ 423 (__HANDLE__)->MspInitCallback = NULL; \ 424 (__HANDLE__)->MspDeInitCallback = NULL; \ 425 } while(0) 426 #else 427 #define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) 428 #endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ 429 430 /** 431 * @brief Enable the TSC peripheral. 432 * @param __HANDLE__ TSC handle 433 * @retval None 434 */ 435 #define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) 436 437 /** 438 * @brief Disable the TSC peripheral. 439 * @param __HANDLE__ TSC handle 440 * @retval None 441 */ 442 #define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) 443 444 /** 445 * @brief Start acquisition. 446 * @param __HANDLE__ TSC handle 447 * @retval None 448 */ 449 #define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) 450 451 /** 452 * @brief Stop acquisition. 453 * @param __HANDLE__ TSC handle 454 * @retval None 455 */ 456 #define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) 457 458 /** 459 * @brief Set IO default mode to output push-pull low. 460 * @param __HANDLE__ TSC handle 461 * @retval None 462 */ 463 #define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) 464 465 /** 466 * @brief Set IO default mode to input floating. 467 * @param __HANDLE__ TSC handle 468 * @retval None 469 */ 470 #define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) 471 472 /** 473 * @brief Set synchronization polarity to falling edge. 474 * @param __HANDLE__ TSC handle 475 * @retval None 476 */ 477 #define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) 478 479 /** 480 * @brief Set synchronization polarity to rising edge and high level. 481 * @param __HANDLE__ TSC handle 482 * @retval None 483 */ 484 #define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) 485 486 /** 487 * @brief Enable TSC interrupt. 488 * @param __HANDLE__ TSC handle 489 * @param __INTERRUPT__ TSC interrupt 490 * @retval None 491 */ 492 #define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 493 494 /** 495 * @brief Disable TSC interrupt. 496 * @param __HANDLE__ TSC handle 497 * @param __INTERRUPT__ TSC interrupt 498 * @retval None 499 */ 500 #define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 501 502 /** @brief Check whether the specified TSC interrupt source is enabled or not. 503 * @param __HANDLE__ TSC Handle 504 * @param __INTERRUPT__ TSC interrupt 505 * @retval SET or RESET 506 */ 507 #define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ 508 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ 509 RESET) 510 511 /** 512 * @brief Check whether the specified TSC flag is set or not. 513 * @param __HANDLE__ TSC handle 514 * @param __FLAG__ TSC flag 515 * @retval SET or RESET 516 */ 517 #define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ 518 & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 519 520 /** 521 * @brief Clear the TSC's pending flag. 522 * @param __HANDLE__ TSC handle 523 * @param __FLAG__ TSC flag 524 * @retval None 525 */ 526 #define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 527 528 /** 529 * @brief Enable schmitt trigger hysteresis on a group of IOs. 530 * @param __HANDLE__ TSC handle 531 * @param __GX_IOY_MASK__ IOs mask 532 * @retval None 533 */ 534 #define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) 535 536 /** 537 * @brief Disable schmitt trigger hysteresis on a group of IOs. 538 * @param __HANDLE__ TSC handle 539 * @param __GX_IOY_MASK__ IOs mask 540 * @retval None 541 */ 542 #define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ 543 &= (~(__GX_IOY_MASK__))) 544 545 /** 546 * @brief Open analog switch on a group of IOs. 547 * @param __HANDLE__ TSC handle 548 * @param __GX_IOY_MASK__ IOs mask 549 * @retval None 550 */ 551 #define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ 552 &= (~(__GX_IOY_MASK__))) 553 554 /** 555 * @brief Close analog switch on a group of IOs. 556 * @param __HANDLE__ TSC handle 557 * @param __GX_IOY_MASK__ IOs mask 558 * @retval None 559 */ 560 #define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) 561 562 /** 563 * @brief Enable a group of IOs in channel mode. 564 * @param __HANDLE__ TSC handle 565 * @param __GX_IOY_MASK__ IOs mask 566 * @retval None 567 */ 568 #define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) 569 570 /** 571 * @brief Disable a group of channel IOs. 572 * @param __HANDLE__ TSC handle 573 * @param __GX_IOY_MASK__ IOs mask 574 * @retval None 575 */ 576 #define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ 577 &= (~(__GX_IOY_MASK__))) 578 579 /** 580 * @brief Enable a group of IOs in sampling mode. 581 * @param __HANDLE__ TSC handle 582 * @param __GX_IOY_MASK__ IOs mask 583 * @retval None 584 */ 585 #define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) 586 587 /** 588 * @brief Disable a group of sampling IOs. 589 * @param __HANDLE__ TSC handle 590 * @param __GX_IOY_MASK__ IOs mask 591 * @retval None 592 */ 593 #define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) 594 595 /** 596 * @brief Enable acquisition groups. 597 * @param __HANDLE__ TSC handle 598 * @param __GX_MASK__ Groups mask 599 * @retval None 600 */ 601 #define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) 602 603 /** 604 * @brief Disable acquisition groups. 605 * @param __HANDLE__ TSC handle 606 * @param __GX_MASK__ Groups mask 607 * @retval None 608 */ 609 #define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) 610 611 /** @brief Gets acquisition group status. 612 * @param __HANDLE__ TSC Handle 613 * @param __GX_INDEX__ Group index 614 * @retval SET or RESET 615 */ 616 #define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ 617 ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ 618 (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) 619 620 /** 621 * @} 622 */ 623 624 /* Private macros ------------------------------------------------------------*/ 625 626 /** @defgroup TSC_Private_Macros TSC Private Macros 627 * @{ 628 */ 629 630 #define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ 631 ((__VALUE__) == TSC_CTPH_2CYCLES) || \ 632 ((__VALUE__) == TSC_CTPH_3CYCLES) || \ 633 ((__VALUE__) == TSC_CTPH_4CYCLES) || \ 634 ((__VALUE__) == TSC_CTPH_5CYCLES) || \ 635 ((__VALUE__) == TSC_CTPH_6CYCLES) || \ 636 ((__VALUE__) == TSC_CTPH_7CYCLES) || \ 637 ((__VALUE__) == TSC_CTPH_8CYCLES) || \ 638 ((__VALUE__) == TSC_CTPH_9CYCLES) || \ 639 ((__VALUE__) == TSC_CTPH_10CYCLES) || \ 640 ((__VALUE__) == TSC_CTPH_11CYCLES) || \ 641 ((__VALUE__) == TSC_CTPH_12CYCLES) || \ 642 ((__VALUE__) == TSC_CTPH_13CYCLES) || \ 643 ((__VALUE__) == TSC_CTPH_14CYCLES) || \ 644 ((__VALUE__) == TSC_CTPH_15CYCLES) || \ 645 ((__VALUE__) == TSC_CTPH_16CYCLES)) 646 647 #define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ 648 ((__VALUE__) == TSC_CTPL_2CYCLES) || \ 649 ((__VALUE__) == TSC_CTPL_3CYCLES) || \ 650 ((__VALUE__) == TSC_CTPL_4CYCLES) || \ 651 ((__VALUE__) == TSC_CTPL_5CYCLES) || \ 652 ((__VALUE__) == TSC_CTPL_6CYCLES) || \ 653 ((__VALUE__) == TSC_CTPL_7CYCLES) || \ 654 ((__VALUE__) == TSC_CTPL_8CYCLES) || \ 655 ((__VALUE__) == TSC_CTPL_9CYCLES) || \ 656 ((__VALUE__) == TSC_CTPL_10CYCLES) || \ 657 ((__VALUE__) == TSC_CTPL_11CYCLES) || \ 658 ((__VALUE__) == TSC_CTPL_12CYCLES) || \ 659 ((__VALUE__) == TSC_CTPL_13CYCLES) || \ 660 ((__VALUE__) == TSC_CTPL_14CYCLES) || \ 661 ((__VALUE__) == TSC_CTPL_15CYCLES) || \ 662 ((__VALUE__) == TSC_CTPL_16CYCLES)) 663 664 #define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 665 || ((FunctionalState)(__VALUE__) == ENABLE)) 666 667 #define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) 668 669 #define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) 670 671 #define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ 672 ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ 673 ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ 674 ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ 675 ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ 676 ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ 677 ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ 678 ((__VALUE__) == TSC_PG_PRESC_DIV128)) 679 680 #define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ 681 ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ 682 (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ 683 ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ 684 (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ 685 (((__CTPL__) == TSC_CTPL_1CYCLE) || \ 686 ((__CTPL__) > TSC_CTPL_1CYCLE)))) 687 688 #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ 689 ((__VALUE__) == TSC_MCV_511) || \ 690 ((__VALUE__) == TSC_MCV_1023) || \ 691 ((__VALUE__) == TSC_MCV_2047) || \ 692 ((__VALUE__) == TSC_MCV_4095) || \ 693 ((__VALUE__) == TSC_MCV_8191) || \ 694 ((__VALUE__) == TSC_MCV_16383)) 695 696 #define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) 697 698 #define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ 699 || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) 700 701 #define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) 702 703 #define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ 704 || ((FunctionalState)(__VALUE__) == ENABLE)) 705 706 #define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ 707 || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) 708 709 #define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ 710 (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ 711 (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ 712 (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ 713 (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ 714 (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ 715 (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ 716 (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ 717 (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ 718 (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ 719 (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ 720 (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ 721 (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ 722 (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ 723 (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ 724 (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ 725 (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ 726 (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ 727 (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ 728 (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ 729 (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ 730 (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ 731 (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\ 732 (((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\ 733 (((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\ 734 (((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\ 735 (((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\ 736 (((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\ 737 (((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\ 738 (((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\ 739 (((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\ 740 (((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\ 741 (((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4)) 742 /** 743 * @} 744 */ 745 746 /* Exported functions --------------------------------------------------------*/ 747 /** @addtogroup TSC_Exported_Functions 748 * @{ 749 */ 750 751 /** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions 752 * @{ 753 */ 754 /* Initialization and de-initialization functions *****************************/ 755 HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); 756 HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); 757 void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); 758 void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); 759 760 /* Callbacks Register/UnRegister functions ***********************************/ 761 #if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) 762 HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, 763 pTSC_CallbackTypeDef pCallback); 764 HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); 765 #endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ 766 /** 767 * @} 768 */ 769 770 /** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions 771 * @{ 772 */ 773 /* IO operation functions *****************************************************/ 774 HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); 775 HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); 776 HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); 777 HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); 778 HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); 779 TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 780 uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); 781 /** 782 * @} 783 */ 784 785 /** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions 786 * @{ 787 */ 788 /* Peripheral Control functions ***********************************************/ 789 HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); 790 HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); 791 /** 792 * @} 793 */ 794 795 /** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions 796 * @{ 797 */ 798 /* Peripheral State and Error functions ***************************************/ 799 HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); 800 /** 801 * @} 802 */ 803 804 /** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 805 * @{ 806 */ 807 /******* TSC IRQHandler and Callbacks used in Interrupt mode */ 808 void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); 809 void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); 810 void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); 811 /** 812 * @} 813 */ 814 815 /** 816 * @} 817 */ 818 819 /** 820 * @} 821 */ 822 823 /** 824 * @} 825 */ 826 #endif /* TSC */ 827 828 #ifdef __cplusplus 829 } 830 #endif 831 832 #endif /* STM32L0xx_HAL_TSC_H */ 833
