1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_hsem.h
4 * @author MCD Application Team
5 * @brief Header file of HSEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_HSEM_H
21 #define STM32H7xx_LL_HSEM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(HSEM)
35
36 /** @defgroup HSEM_LL HSEM
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 /* Exported constants --------------------------------------------------------*/
47
48 /** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants
49 * @{
50 */
51
52 /** @defgroup HSEM_LL_EC_COREID COREID Defines
53 * @{
54 */
55 #define LL_HSEM_COREID_NONE 0U
56 #define LL_HSEM_COREID_CPU1 HSEM_CR_COREID_CPU1
57 #if defined(DUAL_CORE)
58 #define LL_HSEM_COREID_CPU2 HSEM_CR_COREID_CPU2
59 #endif /* DUAL_CORE */
60 #define LL_HSEM_COREID HSEM_CR_COREID_CURRENT
61 /**
62 * @}
63 */
64
65
66 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
67 * @brief Flags defines which can be used with LL_HSEM_ReadReg function
68 * @{
69 */
70
71 #define LL_HSEM_SEMAPHORE_0 HSEM_C1IER_ISE0
72 #define LL_HSEM_SEMAPHORE_1 HSEM_C1IER_ISE1
73 #define LL_HSEM_SEMAPHORE_2 HSEM_C1IER_ISE2
74 #define LL_HSEM_SEMAPHORE_3 HSEM_C1IER_ISE3
75 #define LL_HSEM_SEMAPHORE_4 HSEM_C1IER_ISE4
76 #define LL_HSEM_SEMAPHORE_5 HSEM_C1IER_ISE5
77 #define LL_HSEM_SEMAPHORE_6 HSEM_C1IER_ISE6
78 #define LL_HSEM_SEMAPHORE_7 HSEM_C1IER_ISE7
79 #define LL_HSEM_SEMAPHORE_8 HSEM_C1IER_ISE8
80 #define LL_HSEM_SEMAPHORE_9 HSEM_C1IER_ISE9
81 #define LL_HSEM_SEMAPHORE_10 HSEM_C1IER_ISE10
82 #define LL_HSEM_SEMAPHORE_11 HSEM_C1IER_ISE11
83 #define LL_HSEM_SEMAPHORE_12 HSEM_C1IER_ISE12
84 #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13
85 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14
86 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15
87 #if (HSEM_SEMID_MAX == 15)
88 #define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU
89 #else /* HSEM_SEMID_MAX == 31 */
90 #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16
91 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17
92 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18
93 #define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19
94 #define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20
95 #define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21
96 #define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22
97 #define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23
98 #define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24
99 #define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25
100 #define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26
101 #define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27
102 #define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28
103 #define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29
104 #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30
105 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31
106 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU
107 #endif /* HSEM_SEMID_MAX == 15 */
108 /**
109 * @}
110 */
111
112 /**
113 * @}
114 */
115
116 /* Exported macro ------------------------------------------------------------*/
117 /** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros
118 * @{
119 */
120
121 /** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros
122 * @{
123 */
124
125 /**
126 * @brief Write a value in HSEM register
127 * @param __INSTANCE__ HSEM Instance
128 * @param __REG__ Register to be written
129 * @param __VALUE__ Value to be written in the register
130 * @retval None
131 */
132 #define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
133
134 /**
135 * @brief Read a value in HSEM register
136 * @param __INSTANCE__ HSEM Instance
137 * @param __REG__ Register to be read
138 * @retval Register value
139 */
140 #define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
141 /**
142 * @}
143 */
144
145 /**
146 * @}
147 */
148
149 /* Exported functions --------------------------------------------------------*/
150 /** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions
151 * @{
152 */
153
154 /** @defgroup HSEM_LL_EF_Data_Management Data_Management
155 * @{
156 */
157
158
159 /**
160 * @brief Return 1 if the semaphore is locked, else return 0.
161 * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked
162 * @param HSEMx HSEM Instance.
163 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
164 * @retval State of bit (1 or 0).
165 */
LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef * HSEMx,uint32_t Semaphore)166 __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
167 {
168 return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
169 }
170
171 /**
172 * @brief Get core id.
173 * @rmtoll R COREID LL_HSEM_GetCoreId
174 * @param HSEMx HSEM Instance.
175 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
176 * @retval Returned value can be one of the following values:
177 * @arg @ref LL_HSEM_COREID_NONE
178 * @arg @ref LL_HSEM_COREID_CPU1
179 * @arg @ref LL_HSEM_COREID_CPU2
180 */
LL_HSEM_GetCoreId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)181 __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
182 {
183 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
184 }
185
186 /**
187 * @brief Get process id.
188 * @rmtoll R PROCID LL_HSEM_GetProcessId
189 * @param HSEMx HSEM Instance.
190 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
191 * @retval Process number. Value between Min_Data=0 and Max_Data=255
192 */
LL_HSEM_GetProcessId(HSEM_TypeDef * HSEMx,uint32_t Semaphore)193 __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
194 {
195 return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
196 }
197
198 /**
199 * @brief Get the lock by writing in R register.
200 * @note The R register has to be read to determined if the lock is taken.
201 * @rmtoll R LOCK LL_HSEM_SetLock
202 * @rmtoll R COREID LL_HSEM_SetLock
203 * @rmtoll R PROCID LL_HSEM_SetLock
204 * @param HSEMx HSEM Instance.
205 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
206 * @param process Process id. Value between Min_Data=0 and Max_Data=255
207 * @retval None
208 */
LL_HSEM_SetLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)209 __STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
210 {
211 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
212 }
213
214 /**
215 * @brief Get the lock with 2-step lock.
216 * @rmtoll R LOCK LL_HSEM_2StepLock
217 * @rmtoll R COREID LL_HSEM_2StepLock
218 * @rmtoll R PROCID LL_HSEM_2StepLock
219 * @param HSEMx HSEM Instance.
220 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
221 * @param process Process id. Value between Min_Data=0 and Max_Data=255
222 * @retval 1 lock fail, 0 lock successful or already locked by same process and core
223 */
LL_HSEM_2StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)224 __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
225 {
226 WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));
227 return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);
228 }
229
230 /**
231 * @brief Get the lock with 1-step lock.
232 * @rmtoll RLR LOCK LL_HSEM_1StepLock
233 * @rmtoll RLR COREID LL_HSEM_1StepLock
234 * @rmtoll RLR PROCID LL_HSEM_1StepLock
235 * @param HSEMx HSEM Instance.
236 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
237 * @retval 1 lock fail, 0 lock successful or already locked by same core
238 */
LL_HSEM_1StepLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore)239 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
240 {
241 return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
242 }
243
244 /**
245 * @brief Release the lock of the semaphore.
246 * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.
247 * @rmtoll R LOCK LL_HSEM_ReleaseLock
248 * @param HSEMx HSEM Instance.
249 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
250 * @param process Process number. Value between Min_Data=0 and Max_Data=255
251 * @retval None
252 */
LL_HSEM_ReleaseLock(HSEM_TypeDef * HSEMx,uint32_t Semaphore,uint32_t process)253 __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)
254 {
255 WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));
256 }
257
258 /**
259 * @brief Get the lock status of the semaphore.
260 * @rmtoll R LOCK LL_HSEM_GetStatus
261 * @param HSEMx HSEM Instance.
262 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
263 * @retval 0 semaphore is free, 1 semaphore is locked */
LL_HSEM_GetStatus(HSEM_TypeDef * HSEMx,uint32_t Semaphore)264 __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
265 {
266 return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
267 }
268
269 /**
270 * @brief Set the key.
271 * @rmtoll KEYR KEY LL_HSEM_SetKey
272 * @param HSEMx HSEM Instance.
273 * @param key Key value.
274 * @retval None
275 */
LL_HSEM_SetKey(HSEM_TypeDef * HSEMx,uint32_t key)276 __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
277 {
278 WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);
279 }
280
281 /**
282 * @brief Get the key.
283 * @rmtoll KEYR KEY LL_HSEM_GetKey
284 * @param HSEMx HSEM Instance.
285 * @retval key to unlock all semaphore from the same core
286 */
LL_HSEM_GetKey(HSEM_TypeDef * HSEMx)287 __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
288 {
289 return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
290 }
291
292 /**
293 * @brief Release all semaphore with the same core id.
294 * @rmtoll CR KEY LL_HSEM_ResetAllLock
295 * @rmtoll CR SEC LL_HSEM_ResetAllLock
296 * @rmtoll CR PRIV LL_HSEM_ResetAllLock
297 * @param HSEMx HSEM Instance.
298 * @param key Key value.
299 * @param core This parameter can be one of the following values:
300 * @arg @ref LL_HSEM_COREID_CPU1
301 * @arg @ref LL_HSEM_COREID_CPU2
302 * @retval None
303 */
LL_HSEM_ResetAllLock(HSEM_TypeDef * HSEMx,uint32_t key,uint32_t core)304 __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)
305 {
306 WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);
307 }
308
309 /**
310 * @}
311 */
312
313 /** @defgroup HSEM_LL_EF_IT_Management IT_Management
314 * @{
315 */
316
317 /**
318 * @brief Enable interrupt.
319 * @rmtoll C1IER ISEM LL_HSEM_EnableIT_C1IER
320 * @param HSEMx HSEM Instance.
321 * @param SemaphoreMask This parameter can be a combination of the following values:
322 * @arg @ref LL_HSEM_SEMAPHORE_0
323 * @arg @ref LL_HSEM_SEMAPHORE_1
324 * @arg @ref LL_HSEM_SEMAPHORE_2
325 * @arg @ref LL_HSEM_SEMAPHORE_3
326 * @arg @ref LL_HSEM_SEMAPHORE_4
327 * @arg @ref LL_HSEM_SEMAPHORE_5
328 * @arg @ref LL_HSEM_SEMAPHORE_6
329 * @arg @ref LL_HSEM_SEMAPHORE_7
330 * @arg @ref LL_HSEM_SEMAPHORE_8
331 * @arg @ref LL_HSEM_SEMAPHORE_9
332 * @arg @ref LL_HSEM_SEMAPHORE_10
333 * @arg @ref LL_HSEM_SEMAPHORE_11
334 * @arg @ref LL_HSEM_SEMAPHORE_12
335 * @arg @ref LL_HSEM_SEMAPHORE_13
336 * @arg @ref LL_HSEM_SEMAPHORE_14
337 * @arg @ref LL_HSEM_SEMAPHORE_15
338 * @arg @ref LL_HSEM_SEMAPHORE_16
339 * @arg @ref LL_HSEM_SEMAPHORE_17
340 * @arg @ref LL_HSEM_SEMAPHORE_18
341 * @arg @ref LL_HSEM_SEMAPHORE_19
342 * @arg @ref LL_HSEM_SEMAPHORE_20
343 * @arg @ref LL_HSEM_SEMAPHORE_21
344 * @arg @ref LL_HSEM_SEMAPHORE_22
345 * @arg @ref LL_HSEM_SEMAPHORE_23
346 * @arg @ref LL_HSEM_SEMAPHORE_24
347 * @arg @ref LL_HSEM_SEMAPHORE_25
348 * @arg @ref LL_HSEM_SEMAPHORE_26
349 * @arg @ref LL_HSEM_SEMAPHORE_27
350 * @arg @ref LL_HSEM_SEMAPHORE_28
351 * @arg @ref LL_HSEM_SEMAPHORE_29
352 * @arg @ref LL_HSEM_SEMAPHORE_30
353 * @arg @ref LL_HSEM_SEMAPHORE_31
354 * @arg @ref LL_HSEM_SEMAPHORE_ALL
355 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
356 * depends on devices.
357 * @retval None
358 */
LL_HSEM_EnableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)359 __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
360 {
361 SET_BIT(HSEMx->C1IER, SemaphoreMask);
362 }
363
364 /**
365 * @brief Disable interrupt.
366 * @rmtoll C1IER ISEM LL_HSEM_DisableIT_C1IER
367 * @param HSEMx HSEM Instance.
368 * @param SemaphoreMask This parameter can be a combination of the following values:
369 * @arg @ref LL_HSEM_SEMAPHORE_0
370 * @arg @ref LL_HSEM_SEMAPHORE_1
371 * @arg @ref LL_HSEM_SEMAPHORE_2
372 * @arg @ref LL_HSEM_SEMAPHORE_3
373 * @arg @ref LL_HSEM_SEMAPHORE_4
374 * @arg @ref LL_HSEM_SEMAPHORE_5
375 * @arg @ref LL_HSEM_SEMAPHORE_6
376 * @arg @ref LL_HSEM_SEMAPHORE_7
377 * @arg @ref LL_HSEM_SEMAPHORE_8
378 * @arg @ref LL_HSEM_SEMAPHORE_9
379 * @arg @ref LL_HSEM_SEMAPHORE_10
380 * @arg @ref LL_HSEM_SEMAPHORE_11
381 * @arg @ref LL_HSEM_SEMAPHORE_12
382 * @arg @ref LL_HSEM_SEMAPHORE_13
383 * @arg @ref LL_HSEM_SEMAPHORE_14
384 * @arg @ref LL_HSEM_SEMAPHORE_15
385 * @arg @ref LL_HSEM_SEMAPHORE_16
386 * @arg @ref LL_HSEM_SEMAPHORE_17
387 * @arg @ref LL_HSEM_SEMAPHORE_18
388 * @arg @ref LL_HSEM_SEMAPHORE_19
389 * @arg @ref LL_HSEM_SEMAPHORE_20
390 * @arg @ref LL_HSEM_SEMAPHORE_21
391 * @arg @ref LL_HSEM_SEMAPHORE_22
392 * @arg @ref LL_HSEM_SEMAPHORE_23
393 * @arg @ref LL_HSEM_SEMAPHORE_24
394 * @arg @ref LL_HSEM_SEMAPHORE_25
395 * @arg @ref LL_HSEM_SEMAPHORE_26
396 * @arg @ref LL_HSEM_SEMAPHORE_27
397 * @arg @ref LL_HSEM_SEMAPHORE_28
398 * @arg @ref LL_HSEM_SEMAPHORE_29
399 * @arg @ref LL_HSEM_SEMAPHORE_30
400 * @arg @ref LL_HSEM_SEMAPHORE_31
401 * @arg @ref LL_HSEM_SEMAPHORE_ALL
402 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
403 * depends on devices.
404 * @retval None
405 */
LL_HSEM_DisableIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)406 __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
407 {
408 CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);
409 }
410
411 /**
412 * @brief Check if interrupt is enabled.
413 * @rmtoll C1IER ISEM LL_HSEM_IsEnabledIT_C1IER
414 * @param HSEMx HSEM Instance.
415 * @param SemaphoreMask This parameter can be a combination of the following values:
416 * @arg @ref LL_HSEM_SEMAPHORE_0
417 * @arg @ref LL_HSEM_SEMAPHORE_1
418 * @arg @ref LL_HSEM_SEMAPHORE_2
419 * @arg @ref LL_HSEM_SEMAPHORE_3
420 * @arg @ref LL_HSEM_SEMAPHORE_4
421 * @arg @ref LL_HSEM_SEMAPHORE_5
422 * @arg @ref LL_HSEM_SEMAPHORE_6
423 * @arg @ref LL_HSEM_SEMAPHORE_7
424 * @arg @ref LL_HSEM_SEMAPHORE_8
425 * @arg @ref LL_HSEM_SEMAPHORE_9
426 * @arg @ref LL_HSEM_SEMAPHORE_10
427 * @arg @ref LL_HSEM_SEMAPHORE_11
428 * @arg @ref LL_HSEM_SEMAPHORE_12
429 * @arg @ref LL_HSEM_SEMAPHORE_13
430 * @arg @ref LL_HSEM_SEMAPHORE_14
431 * @arg @ref LL_HSEM_SEMAPHORE_15
432 * @arg @ref LL_HSEM_SEMAPHORE_16
433 * @arg @ref LL_HSEM_SEMAPHORE_17
434 * @arg @ref LL_HSEM_SEMAPHORE_18
435 * @arg @ref LL_HSEM_SEMAPHORE_19
436 * @arg @ref LL_HSEM_SEMAPHORE_20
437 * @arg @ref LL_HSEM_SEMAPHORE_21
438 * @arg @ref LL_HSEM_SEMAPHORE_22
439 * @arg @ref LL_HSEM_SEMAPHORE_23
440 * @arg @ref LL_HSEM_SEMAPHORE_24
441 * @arg @ref LL_HSEM_SEMAPHORE_25
442 * @arg @ref LL_HSEM_SEMAPHORE_26
443 * @arg @ref LL_HSEM_SEMAPHORE_27
444 * @arg @ref LL_HSEM_SEMAPHORE_28
445 * @arg @ref LL_HSEM_SEMAPHORE_29
446 * @arg @ref LL_HSEM_SEMAPHORE_30
447 * @arg @ref LL_HSEM_SEMAPHORE_31
448 * @arg @ref LL_HSEM_SEMAPHORE_ALL
449 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
450 * depends on devices.
451 * @retval State of bit (1 or 0).
452 */
LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)453 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
454 {
455 return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
456 }
457
458 #if defined(DUAL_CORE)
459 /**
460 * @brief Enable interrupt.
461 * @rmtoll C2IER ISEM LL_HSEM_EnableIT_C2IER
462 * @param HSEMx HSEM Instance.
463 * @param SemaphoreMask This parameter can be a combination of the following values:
464 * @arg @ref LL_HSEM_SEMAPHORE_0
465 * @arg @ref LL_HSEM_SEMAPHORE_1
466 * @arg @ref LL_HSEM_SEMAPHORE_2
467 * @arg @ref LL_HSEM_SEMAPHORE_3
468 * @arg @ref LL_HSEM_SEMAPHORE_4
469 * @arg @ref LL_HSEM_SEMAPHORE_5
470 * @arg @ref LL_HSEM_SEMAPHORE_6
471 * @arg @ref LL_HSEM_SEMAPHORE_7
472 * @arg @ref LL_HSEM_SEMAPHORE_8
473 * @arg @ref LL_HSEM_SEMAPHORE_9
474 * @arg @ref LL_HSEM_SEMAPHORE_10
475 * @arg @ref LL_HSEM_SEMAPHORE_11
476 * @arg @ref LL_HSEM_SEMAPHORE_12
477 * @arg @ref LL_HSEM_SEMAPHORE_13
478 * @arg @ref LL_HSEM_SEMAPHORE_14
479 * @arg @ref LL_HSEM_SEMAPHORE_15
480 * @arg @ref LL_HSEM_SEMAPHORE_16
481 * @arg @ref LL_HSEM_SEMAPHORE_17
482 * @arg @ref LL_HSEM_SEMAPHORE_18
483 * @arg @ref LL_HSEM_SEMAPHORE_19
484 * @arg @ref LL_HSEM_SEMAPHORE_20
485 * @arg @ref LL_HSEM_SEMAPHORE_21
486 * @arg @ref LL_HSEM_SEMAPHORE_22
487 * @arg @ref LL_HSEM_SEMAPHORE_23
488 * @arg @ref LL_HSEM_SEMAPHORE_24
489 * @arg @ref LL_HSEM_SEMAPHORE_25
490 * @arg @ref LL_HSEM_SEMAPHORE_26
491 * @arg @ref LL_HSEM_SEMAPHORE_27
492 * @arg @ref LL_HSEM_SEMAPHORE_28
493 * @arg @ref LL_HSEM_SEMAPHORE_29
494 * @arg @ref LL_HSEM_SEMAPHORE_30
495 * @arg @ref LL_HSEM_SEMAPHORE_31
496 * @arg @ref LL_HSEM_SEMAPHORE_ALL
497 * @retval None
498 */
LL_HSEM_EnableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)499 __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
500 {
501 SET_BIT(HSEMx->C2IER, SemaphoreMask);
502 }
503
504 /**
505 * @brief Disable interrupt.
506 * @rmtoll C2IER ISEM LL_HSEM_DisableIT_C2IER
507 * @param HSEMx HSEM Instance.
508 * @param SemaphoreMask This parameter can be a combination of the following values:
509 * @arg @ref LL_HSEM_SEMAPHORE_0
510 * @arg @ref LL_HSEM_SEMAPHORE_1
511 * @arg @ref LL_HSEM_SEMAPHORE_2
512 * @arg @ref LL_HSEM_SEMAPHORE_3
513 * @arg @ref LL_HSEM_SEMAPHORE_4
514 * @arg @ref LL_HSEM_SEMAPHORE_5
515 * @arg @ref LL_HSEM_SEMAPHORE_6
516 * @arg @ref LL_HSEM_SEMAPHORE_7
517 * @arg @ref LL_HSEM_SEMAPHORE_8
518 * @arg @ref LL_HSEM_SEMAPHORE_9
519 * @arg @ref LL_HSEM_SEMAPHORE_10
520 * @arg @ref LL_HSEM_SEMAPHORE_11
521 * @arg @ref LL_HSEM_SEMAPHORE_12
522 * @arg @ref LL_HSEM_SEMAPHORE_13
523 * @arg @ref LL_HSEM_SEMAPHORE_14
524 * @arg @ref LL_HSEM_SEMAPHORE_15
525 * @arg @ref LL_HSEM_SEMAPHORE_16
526 * @arg @ref LL_HSEM_SEMAPHORE_17
527 * @arg @ref LL_HSEM_SEMAPHORE_18
528 * @arg @ref LL_HSEM_SEMAPHORE_19
529 * @arg @ref LL_HSEM_SEMAPHORE_20
530 * @arg @ref LL_HSEM_SEMAPHORE_21
531 * @arg @ref LL_HSEM_SEMAPHORE_22
532 * @arg @ref LL_HSEM_SEMAPHORE_23
533 * @arg @ref LL_HSEM_SEMAPHORE_24
534 * @arg @ref LL_HSEM_SEMAPHORE_25
535 * @arg @ref LL_HSEM_SEMAPHORE_26
536 * @arg @ref LL_HSEM_SEMAPHORE_27
537 * @arg @ref LL_HSEM_SEMAPHORE_28
538 * @arg @ref LL_HSEM_SEMAPHORE_29
539 * @arg @ref LL_HSEM_SEMAPHORE_30
540 * @arg @ref LL_HSEM_SEMAPHORE_31
541 * @arg @ref LL_HSEM_SEMAPHORE_ALL
542 * @retval None
543 */
LL_HSEM_DisableIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)544 __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
545 {
546 CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);
547 }
548
549 /**
550 * @brief Check if interrupt is enabled.
551 * @rmtoll C2IER ISEM LL_HSEM_IsEnabledIT_C2IER
552 * @param HSEMx HSEM Instance.
553 * @param SemaphoreMask This parameter can be a combination of the following values:
554 * @arg @ref LL_HSEM_SEMAPHORE_0
555 * @arg @ref LL_HSEM_SEMAPHORE_1
556 * @arg @ref LL_HSEM_SEMAPHORE_2
557 * @arg @ref LL_HSEM_SEMAPHORE_3
558 * @arg @ref LL_HSEM_SEMAPHORE_4
559 * @arg @ref LL_HSEM_SEMAPHORE_5
560 * @arg @ref LL_HSEM_SEMAPHORE_6
561 * @arg @ref LL_HSEM_SEMAPHORE_7
562 * @arg @ref LL_HSEM_SEMAPHORE_8
563 * @arg @ref LL_HSEM_SEMAPHORE_9
564 * @arg @ref LL_HSEM_SEMAPHORE_10
565 * @arg @ref LL_HSEM_SEMAPHORE_11
566 * @arg @ref LL_HSEM_SEMAPHORE_12
567 * @arg @ref LL_HSEM_SEMAPHORE_13
568 * @arg @ref LL_HSEM_SEMAPHORE_14
569 * @arg @ref LL_HSEM_SEMAPHORE_15
570 * @arg @ref LL_HSEM_SEMAPHORE_16
571 * @arg @ref LL_HSEM_SEMAPHORE_17
572 * @arg @ref LL_HSEM_SEMAPHORE_18
573 * @arg @ref LL_HSEM_SEMAPHORE_19
574 * @arg @ref LL_HSEM_SEMAPHORE_20
575 * @arg @ref LL_HSEM_SEMAPHORE_21
576 * @arg @ref LL_HSEM_SEMAPHORE_22
577 * @arg @ref LL_HSEM_SEMAPHORE_23
578 * @arg @ref LL_HSEM_SEMAPHORE_24
579 * @arg @ref LL_HSEM_SEMAPHORE_25
580 * @arg @ref LL_HSEM_SEMAPHORE_26
581 * @arg @ref LL_HSEM_SEMAPHORE_27
582 * @arg @ref LL_HSEM_SEMAPHORE_28
583 * @arg @ref LL_HSEM_SEMAPHORE_29
584 * @arg @ref LL_HSEM_SEMAPHORE_30
585 * @arg @ref LL_HSEM_SEMAPHORE_31
586 * @arg @ref LL_HSEM_SEMAPHORE_ALL
587 * @retval State of bit (1 or 0).
588 */
LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)589 __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
590 {
591 return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
592 }
593 #endif /* DUAL_CORE */
594
595 /**
596 * @}
597 */
598
599 /** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management
600 * @{
601 */
602
603 /**
604 * @brief Clear interrupt status.
605 * @rmtoll C1ICR ISEM LL_HSEM_ClearFlag_C1ICR
606 * @param HSEMx HSEM Instance.
607 * @param SemaphoreMask This parameter can be a combination of the following values:
608 * @arg @ref LL_HSEM_SEMAPHORE_0
609 * @arg @ref LL_HSEM_SEMAPHORE_1
610 * @arg @ref LL_HSEM_SEMAPHORE_2
611 * @arg @ref LL_HSEM_SEMAPHORE_3
612 * @arg @ref LL_HSEM_SEMAPHORE_4
613 * @arg @ref LL_HSEM_SEMAPHORE_5
614 * @arg @ref LL_HSEM_SEMAPHORE_6
615 * @arg @ref LL_HSEM_SEMAPHORE_7
616 * @arg @ref LL_HSEM_SEMAPHORE_8
617 * @arg @ref LL_HSEM_SEMAPHORE_9
618 * @arg @ref LL_HSEM_SEMAPHORE_10
619 * @arg @ref LL_HSEM_SEMAPHORE_11
620 * @arg @ref LL_HSEM_SEMAPHORE_12
621 * @arg @ref LL_HSEM_SEMAPHORE_13
622 * @arg @ref LL_HSEM_SEMAPHORE_14
623 * @arg @ref LL_HSEM_SEMAPHORE_15
624 * @arg @ref LL_HSEM_SEMAPHORE_16
625 * @arg @ref LL_HSEM_SEMAPHORE_17
626 * @arg @ref LL_HSEM_SEMAPHORE_18
627 * @arg @ref LL_HSEM_SEMAPHORE_19
628 * @arg @ref LL_HSEM_SEMAPHORE_20
629 * @arg @ref LL_HSEM_SEMAPHORE_21
630 * @arg @ref LL_HSEM_SEMAPHORE_22
631 * @arg @ref LL_HSEM_SEMAPHORE_23
632 * @arg @ref LL_HSEM_SEMAPHORE_24
633 * @arg @ref LL_HSEM_SEMAPHORE_25
634 * @arg @ref LL_HSEM_SEMAPHORE_26
635 * @arg @ref LL_HSEM_SEMAPHORE_27
636 * @arg @ref LL_HSEM_SEMAPHORE_28
637 * @arg @ref LL_HSEM_SEMAPHORE_29
638 * @arg @ref LL_HSEM_SEMAPHORE_30
639 * @arg @ref LL_HSEM_SEMAPHORE_31
640 * @arg @ref LL_HSEM_SEMAPHORE_ALL
641 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
642 * depends on devices.
643 * @retval None
644 */
LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)645 __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
646 {
647 WRITE_REG(HSEMx->C1ICR, SemaphoreMask);
648 }
649
650 /**
651 * @brief Get interrupt status from ISR register.
652 * @rmtoll C1ISR ISEM LL_HSEM_IsActiveFlag_C1ISR
653 * @param HSEMx HSEM Instance.
654 * @param SemaphoreMask This parameter can be a combination of the following values:
655 * @arg @ref LL_HSEM_SEMAPHORE_0
656 * @arg @ref LL_HSEM_SEMAPHORE_1
657 * @arg @ref LL_HSEM_SEMAPHORE_2
658 * @arg @ref LL_HSEM_SEMAPHORE_3
659 * @arg @ref LL_HSEM_SEMAPHORE_4
660 * @arg @ref LL_HSEM_SEMAPHORE_5
661 * @arg @ref LL_HSEM_SEMAPHORE_6
662 * @arg @ref LL_HSEM_SEMAPHORE_7
663 * @arg @ref LL_HSEM_SEMAPHORE_8
664 * @arg @ref LL_HSEM_SEMAPHORE_9
665 * @arg @ref LL_HSEM_SEMAPHORE_10
666 * @arg @ref LL_HSEM_SEMAPHORE_11
667 * @arg @ref LL_HSEM_SEMAPHORE_12
668 * @arg @ref LL_HSEM_SEMAPHORE_13
669 * @arg @ref LL_HSEM_SEMAPHORE_14
670 * @arg @ref LL_HSEM_SEMAPHORE_15
671 * @arg @ref LL_HSEM_SEMAPHORE_16
672 * @arg @ref LL_HSEM_SEMAPHORE_17
673 * @arg @ref LL_HSEM_SEMAPHORE_18
674 * @arg @ref LL_HSEM_SEMAPHORE_19
675 * @arg @ref LL_HSEM_SEMAPHORE_20
676 * @arg @ref LL_HSEM_SEMAPHORE_21
677 * @arg @ref LL_HSEM_SEMAPHORE_22
678 * @arg @ref LL_HSEM_SEMAPHORE_23
679 * @arg @ref LL_HSEM_SEMAPHORE_24
680 * @arg @ref LL_HSEM_SEMAPHORE_25
681 * @arg @ref LL_HSEM_SEMAPHORE_26
682 * @arg @ref LL_HSEM_SEMAPHORE_27
683 * @arg @ref LL_HSEM_SEMAPHORE_28
684 * @arg @ref LL_HSEM_SEMAPHORE_29
685 * @arg @ref LL_HSEM_SEMAPHORE_30
686 * @arg @ref LL_HSEM_SEMAPHORE_31
687 * @arg @ref LL_HSEM_SEMAPHORE_ALL
688 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
689 * depends on devices.
690 * @retval State of bit (1 or 0).
691 */
LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)692 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
693 {
694 return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Get interrupt status from MISR register.
699 * @rmtoll C1MISR ISEM LL_HSEM_IsActiveFlag_C1MISR
700 * @param HSEMx HSEM Instance.
701 * @param SemaphoreMask This parameter can be a combination of the following values:
702 * @arg @ref LL_HSEM_SEMAPHORE_0
703 * @arg @ref LL_HSEM_SEMAPHORE_1
704 * @arg @ref LL_HSEM_SEMAPHORE_2
705 * @arg @ref LL_HSEM_SEMAPHORE_3
706 * @arg @ref LL_HSEM_SEMAPHORE_4
707 * @arg @ref LL_HSEM_SEMAPHORE_5
708 * @arg @ref LL_HSEM_SEMAPHORE_6
709 * @arg @ref LL_HSEM_SEMAPHORE_7
710 * @arg @ref LL_HSEM_SEMAPHORE_8
711 * @arg @ref LL_HSEM_SEMAPHORE_9
712 * @arg @ref LL_HSEM_SEMAPHORE_10
713 * @arg @ref LL_HSEM_SEMAPHORE_11
714 * @arg @ref LL_HSEM_SEMAPHORE_12
715 * @arg @ref LL_HSEM_SEMAPHORE_13
716 * @arg @ref LL_HSEM_SEMAPHORE_14
717 * @arg @ref LL_HSEM_SEMAPHORE_15
718 * @arg @ref LL_HSEM_SEMAPHORE_16
719 * @arg @ref LL_HSEM_SEMAPHORE_17
720 * @arg @ref LL_HSEM_SEMAPHORE_18
721 * @arg @ref LL_HSEM_SEMAPHORE_19
722 * @arg @ref LL_HSEM_SEMAPHORE_20
723 * @arg @ref LL_HSEM_SEMAPHORE_21
724 * @arg @ref LL_HSEM_SEMAPHORE_22
725 * @arg @ref LL_HSEM_SEMAPHORE_23
726 * @arg @ref LL_HSEM_SEMAPHORE_24
727 * @arg @ref LL_HSEM_SEMAPHORE_25
728 * @arg @ref LL_HSEM_SEMAPHORE_26
729 * @arg @ref LL_HSEM_SEMAPHORE_27
730 * @arg @ref LL_HSEM_SEMAPHORE_28
731 * @arg @ref LL_HSEM_SEMAPHORE_29
732 * @arg @ref LL_HSEM_SEMAPHORE_30
733 * @arg @ref LL_HSEM_SEMAPHORE_31
734 * @arg @ref LL_HSEM_SEMAPHORE_ALL
735 * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31
736 * depends on devices.
737 * @retval State of bit (1 or 0).
738 */
LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)739 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
740 {
741 return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
742 }
743
744 #if defined(DUAL_CORE)
745 /**
746 * @brief Clear interrupt status.
747 * @rmtoll C2ICR ISEM LL_HSEM_ClearFlag_C2ICR
748 * @param HSEMx HSEM Instance.
749 * @param SemaphoreMask This parameter can be a combination of the following values:
750 * @arg @ref LL_HSEM_SEMAPHORE_0
751 * @arg @ref LL_HSEM_SEMAPHORE_1
752 * @arg @ref LL_HSEM_SEMAPHORE_2
753 * @arg @ref LL_HSEM_SEMAPHORE_3
754 * @arg @ref LL_HSEM_SEMAPHORE_4
755 * @arg @ref LL_HSEM_SEMAPHORE_5
756 * @arg @ref LL_HSEM_SEMAPHORE_6
757 * @arg @ref LL_HSEM_SEMAPHORE_7
758 * @arg @ref LL_HSEM_SEMAPHORE_8
759 * @arg @ref LL_HSEM_SEMAPHORE_9
760 * @arg @ref LL_HSEM_SEMAPHORE_10
761 * @arg @ref LL_HSEM_SEMAPHORE_11
762 * @arg @ref LL_HSEM_SEMAPHORE_12
763 * @arg @ref LL_HSEM_SEMAPHORE_13
764 * @arg @ref LL_HSEM_SEMAPHORE_14
765 * @arg @ref LL_HSEM_SEMAPHORE_15
766 * @arg @ref LL_HSEM_SEMAPHORE_16
767 * @arg @ref LL_HSEM_SEMAPHORE_17
768 * @arg @ref LL_HSEM_SEMAPHORE_18
769 * @arg @ref LL_HSEM_SEMAPHORE_19
770 * @arg @ref LL_HSEM_SEMAPHORE_20
771 * @arg @ref LL_HSEM_SEMAPHORE_21
772 * @arg @ref LL_HSEM_SEMAPHORE_22
773 * @arg @ref LL_HSEM_SEMAPHORE_23
774 * @arg @ref LL_HSEM_SEMAPHORE_24
775 * @arg @ref LL_HSEM_SEMAPHORE_25
776 * @arg @ref LL_HSEM_SEMAPHORE_26
777 * @arg @ref LL_HSEM_SEMAPHORE_27
778 * @arg @ref LL_HSEM_SEMAPHORE_28
779 * @arg @ref LL_HSEM_SEMAPHORE_29
780 * @arg @ref LL_HSEM_SEMAPHORE_30
781 * @arg @ref LL_HSEM_SEMAPHORE_31
782 * @arg @ref LL_HSEM_SEMAPHORE_ALL
783 * @retval None
784 */
LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)785 __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
786 {
787 WRITE_REG(HSEMx->C2ICR, SemaphoreMask);
788 }
789
790 /**
791 * @brief Get interrupt status from ISR register.
792 * @rmtoll C2ISR ISEM LL_HSEM_IsActiveFlag_C2ISR
793 * @param HSEMx HSEM Instance.
794 * @param SemaphoreMask This parameter can be a combination of the following values:
795 * @arg @ref LL_HSEM_SEMAPHORE_0
796 * @arg @ref LL_HSEM_SEMAPHORE_1
797 * @arg @ref LL_HSEM_SEMAPHORE_2
798 * @arg @ref LL_HSEM_SEMAPHORE_3
799 * @arg @ref LL_HSEM_SEMAPHORE_4
800 * @arg @ref LL_HSEM_SEMAPHORE_5
801 * @arg @ref LL_HSEM_SEMAPHORE_6
802 * @arg @ref LL_HSEM_SEMAPHORE_7
803 * @arg @ref LL_HSEM_SEMAPHORE_8
804 * @arg @ref LL_HSEM_SEMAPHORE_9
805 * @arg @ref LL_HSEM_SEMAPHORE_10
806 * @arg @ref LL_HSEM_SEMAPHORE_11
807 * @arg @ref LL_HSEM_SEMAPHORE_12
808 * @arg @ref LL_HSEM_SEMAPHORE_13
809 * @arg @ref LL_HSEM_SEMAPHORE_14
810 * @arg @ref LL_HSEM_SEMAPHORE_15
811 * @arg @ref LL_HSEM_SEMAPHORE_16
812 * @arg @ref LL_HSEM_SEMAPHORE_17
813 * @arg @ref LL_HSEM_SEMAPHORE_18
814 * @arg @ref LL_HSEM_SEMAPHORE_19
815 * @arg @ref LL_HSEM_SEMAPHORE_20
816 * @arg @ref LL_HSEM_SEMAPHORE_21
817 * @arg @ref LL_HSEM_SEMAPHORE_22
818 * @arg @ref LL_HSEM_SEMAPHORE_23
819 * @arg @ref LL_HSEM_SEMAPHORE_24
820 * @arg @ref LL_HSEM_SEMAPHORE_25
821 * @arg @ref LL_HSEM_SEMAPHORE_26
822 * @arg @ref LL_HSEM_SEMAPHORE_27
823 * @arg @ref LL_HSEM_SEMAPHORE_28
824 * @arg @ref LL_HSEM_SEMAPHORE_29
825 * @arg @ref LL_HSEM_SEMAPHORE_30
826 * @arg @ref LL_HSEM_SEMAPHORE_31
827 * @arg @ref LL_HSEM_SEMAPHORE_ALL
828 * @retval State of bit (1 or 0).
829 */
LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)830 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
831 {
832 return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
833 }
834
835 /**
836 * @brief Get interrupt status from MISR register.
837 * @rmtoll C2MISR ISEM LL_HSEM_IsActiveFlag_C2MISR
838 * @param HSEMx HSEM Instance.
839 * @param SemaphoreMask This parameter can be a combination of the following values:
840 * @arg @ref LL_HSEM_SEMAPHORE_0
841 * @arg @ref LL_HSEM_SEMAPHORE_1
842 * @arg @ref LL_HSEM_SEMAPHORE_2
843 * @arg @ref LL_HSEM_SEMAPHORE_3
844 * @arg @ref LL_HSEM_SEMAPHORE_4
845 * @arg @ref LL_HSEM_SEMAPHORE_5
846 * @arg @ref LL_HSEM_SEMAPHORE_6
847 * @arg @ref LL_HSEM_SEMAPHORE_7
848 * @arg @ref LL_HSEM_SEMAPHORE_8
849 * @arg @ref LL_HSEM_SEMAPHORE_9
850 * @arg @ref LL_HSEM_SEMAPHORE_10
851 * @arg @ref LL_HSEM_SEMAPHORE_11
852 * @arg @ref LL_HSEM_SEMAPHORE_12
853 * @arg @ref LL_HSEM_SEMAPHORE_13
854 * @arg @ref LL_HSEM_SEMAPHORE_14
855 * @arg @ref LL_HSEM_SEMAPHORE_15
856 * @arg @ref LL_HSEM_SEMAPHORE_16
857 * @arg @ref LL_HSEM_SEMAPHORE_17
858 * @arg @ref LL_HSEM_SEMAPHORE_18
859 * @arg @ref LL_HSEM_SEMAPHORE_19
860 * @arg @ref LL_HSEM_SEMAPHORE_20
861 * @arg @ref LL_HSEM_SEMAPHORE_21
862 * @arg @ref LL_HSEM_SEMAPHORE_22
863 * @arg @ref LL_HSEM_SEMAPHORE_23
864 * @arg @ref LL_HSEM_SEMAPHORE_24
865 * @arg @ref LL_HSEM_SEMAPHORE_25
866 * @arg @ref LL_HSEM_SEMAPHORE_26
867 * @arg @ref LL_HSEM_SEMAPHORE_27
868 * @arg @ref LL_HSEM_SEMAPHORE_28
869 * @arg @ref LL_HSEM_SEMAPHORE_29
870 * @arg @ref LL_HSEM_SEMAPHORE_30
871 * @arg @ref LL_HSEM_SEMAPHORE_31
872 * @arg @ref LL_HSEM_SEMAPHORE_ALL
873 * @retval State of bit (1 or 0).
874 */
LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef * HSEMx,uint32_t SemaphoreMask)875 __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
876 {
877 return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
878 }
879 #endif /* DUAL_CORE */
880 /**
881 * @}
882 */
883
884 /**
885 * @}
886 */
887
888 /**
889 * @}
890 */
891
892 #endif /* defined(HSEM) */
893
894 /**
895 * @}
896 */
897
898 #ifdef __cplusplus
899 }
900 #endif
901
902 #endif /* __STM32H7xx_LL_HSEM_H */
903
