1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 ****************************************************************************** 16 */ 17 18 /* Define to prevent recursive inclusion -------------------------------------*/ 19 #ifndef STM32H7xx_HAL_FLASH_EX_H 20 #define STM32H7xx_HAL_FLASH_EX_H 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "stm32h7xx_hal_def.h" 28 29 /** @addtogroup STM32H7xx_HAL_Driver 30 * @{ 31 */ 32 33 /** @addtogroup FLASHEx 34 * @{ 35 */ 36 37 /* Exported types ------------------------------------------------------------*/ 38 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types 39 * @{ 40 */ 41 42 /** 43 * @brief FLASH Erase structure definition 44 */ 45 typedef struct 46 { 47 uint32_t TypeErase; /*!< Mass erase or sector Erase. 48 This parameter can be a value of @ref FLASHEx_Type_Erase */ 49 50 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 51 This parameter must be a value of @ref FLASHEx_Banks */ 52 53 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 54 This parameter must be a value of @ref FLASH_Sectors */ 55 56 uint32_t NbSectors; /*!< Number of sectors to be erased. 57 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 58 59 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism 60 This parameter must be a value of @ref FLASHEx_Voltage_Range */ 61 62 } FLASH_EraseInitTypeDef; 63 64 65 /** 66 * @brief FLASH Option Bytes Program structure definition 67 */ 68 typedef struct 69 { 70 uint32_t OptionType; /*!< Option byte to be configured. 71 This parameter can be a value of @ref FLASHEx_Option_Type */ 72 73 uint32_t WRPState; /*!< Write protection activation or deactivation. 74 This parameter can be a value of @ref FLASHEx_WRP_State */ 75 76 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 77 The value of this parameter depend on device used within the same series */ 78 79 uint32_t RDPLevel; /*!< Set the read protection level. 80 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ 81 82 uint32_t BORLevel; /*!< Set the BOR Level. 83 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ 84 85 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 86 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ 87 88 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / 89 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ 90 91 uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . 92 This parameter must be a value of @ref FLASHEx_Banks */ 93 94 uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not 95 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 96 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ 97 98 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 99 This parameter must be a value between begin and end of a bank */ 100 101 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 102 This parameter must be a value between PCROP Start address and end of a bank */ 103 104 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 105 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 106 107 uint32_t BootAddr0; /*!< Boot Address 0. 108 This parameter must be a value between begin and end of a bank */ 109 110 uint32_t BootAddr1; /*!< Boot Address 1. 111 This parameter must be a value between begin and end of a bank */ 112 #if defined(DUAL_CORE) 113 uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 114 or both. 115 This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 116 117 uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. 118 This parameter must be a value between begin and end of a bank */ 119 120 uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. 121 This parameter must be a value between begin and end of a bank */ 122 #endif /*DUAL_CORE*/ 123 124 uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not 125 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 126 This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ 127 128 uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. 129 This parameter must be a value between begin address and end address of bank1 */ 130 131 uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. 132 This parameter must be a value between Secure Area Start address and end address of a bank1 */ 133 134 #if defined (FLASH_OTPBL_LOCKBL) 135 uint32_t OTPBlockLock; /*!< Specifies the OTP block(s) to be locked. 136 This parameter must be a value of @ref FLASHEx_OTP_Blocks */ 137 #endif /* FLASH_OTPBL_LOCKBL */ 138 139 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 140 uint32_t SharedRamConfig; /*!< Specifies the configuration of TCM / AXI shared RAM. 141 This parameter must be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ 142 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 143 144 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 145 uint32_t FreqBoostState; /*!< Specifies the state of CPU Frequency Boost. 146 This parameter must be a value of @ref FLASHEx_OB_CPUFREQ_BOOST */ 147 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 148 149 } FLASH_OBProgramInitTypeDef; 150 151 /** 152 * @brief FLASH Erase structure definition 153 */ 154 typedef struct 155 { 156 uint32_t TypeCRC; /*!< CRC Selection Type. 157 This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ 158 159 uint32_t BurstSize; /*!< CRC Burst Size. 160 This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ 161 162 uint32_t Bank; /*!< Select bank where CRC computation is enabled. 163 This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ 164 165 uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation 166 This parameter must be a value of @ref FLASH_Sectors */ 167 168 uint32_t NbSectors; /*!< Number of sectors to be computed. 169 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 170 171 uint32_t CRCStartAddr; /*!< CRC Start address. 172 This parameter must be a value between begin address and end address of a bank */ 173 174 uint32_t CRCEndAddr; /*!< CRC End address. 175 This parameter must be a value between CRC Start address and end address of a bank */ 176 177 } FLASH_CRCInitTypeDef; 178 179 /** 180 * @} 181 */ 182 /* Exported constants --------------------------------------------------------*/ 183 184 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants 185 * @{ 186 */ 187 188 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase 189 * @{ 190 */ 191 #define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ 192 #define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ 193 /** 194 * @} 195 */ 196 197 #if defined (FLASH_CR_PSIZE) 198 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range 199 * @{ 200 */ 201 #define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ 202 #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ 203 #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ 204 #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ 205 /** 206 * @} 207 */ 208 #endif /* FLASH_CR_PSIZE */ 209 210 /** @defgroup FLASHEx_WRP_State FLASH WRP State 211 * @{ 212 */ 213 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ 214 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ 215 /** 216 * @} 217 */ 218 219 /** @defgroup FLASHEx_Option_Type FLASH Option Type 220 * @{ 221 */ 222 #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ 223 #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ 224 #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ 225 #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ 226 #define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ 227 #define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ 228 #if defined (DUAL_CORE) 229 #define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ 230 #define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ 231 #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ 232 #else /* Single core */ 233 #define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ 234 #endif /*DUAL_CORE*/ 235 #if defined (FLASH_OTPBL_LOCKBL) 236 #define OPTIONBYTE_OTP_LOCK 0x80U /*!< OTP Lock option byte configuration */ 237 #endif /* FLASH_OTPBL_LOCKBL */ 238 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 239 #define OPTIONBYTE_SHARED_RAM 0x100U /*!< TCM / AXI Shared RAM option byte configuration */ 240 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 241 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 242 #define OPTIONBYTE_FREQ_BOOST 0x200U /*!< CPU Frequency Boost option byte configuration */ 243 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 244 245 #if defined (DUAL_CORE) 246 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 247 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 248 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD) /*!< All option byte configuration */ 249 #elif defined (FLASH_OTPBL_LOCKBL) 250 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 251 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 252 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK) /*!< All option byte configuration */ 253 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) 254 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 255 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 256 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST) /*!< All option byte configuration */ 257 #else 258 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ 259 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\ 260 OPTIONBYTE_BOOTADD) /*!< All option byte configuration */ 261 #endif /* DUAL_CORE */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection 267 * @{ 268 */ 269 #define OB_RDP_LEVEL_0 0xAA00U 270 #define OB_RDP_LEVEL_1 0x5500U 271 #define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 272 it s no more possible to go back to level 1 or 0 */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog 278 * @{ 279 */ 280 #define OB_IWDG_SW OB_IWDG1_SW /*!< Software IWDG selected */ 281 #define OB_IWDG_HW OB_IWDG1_HW /*!< Hardware IWDG selected */ 282 /** 283 * @} 284 */ 285 286 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP 287 * @{ 288 */ 289 #define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ 290 #define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ 291 /** 292 * @} 293 */ 294 295 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY 296 * @{ 297 */ 298 #define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ 299 #define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ 300 /** 301 * @} 302 */ 303 304 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP 305 * @{ 306 */ 307 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ 308 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY 314 * @{ 315 */ 316 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ 317 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ 318 /** 319 * @} 320 */ 321 322 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level 323 * @{ 324 */ 325 #define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ 326 #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ 327 #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ 328 #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ 329 /** 330 * @} 331 */ 332 333 334 335 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address 336 * @{ 337 */ 338 #define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ 339 #define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ 340 #define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ 341 #define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ 342 #define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ 343 #define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ 344 #define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ 345 /** 346 * @} 347 */ 348 349 /** @defgroup FLASH_Latency FLASH Latency 350 * @{ 351 */ 352 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ 353 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ 354 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ 355 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ 356 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ 357 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ 358 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ 359 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ 360 361 /* Unused FLASH Latency defines */ 362 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ 363 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ 364 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ 365 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ 366 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ 367 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ 368 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ 369 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup FLASHEx_Banks FLASH Banks 375 * @{ 376 */ 377 #define FLASH_BANK_1 0x01U /*!< Bank 1 */ 378 #if defined (DUAL_BANK) 379 #define FLASH_BANK_2 0x02U /*!< Bank 2 */ 380 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 381 #endif /* DUAL_BANK */ 382 /** 383 * @} 384 */ 385 386 /** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP 387 * @{ 388 */ 389 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 390 is decreased from Level 1 to Level 0 or during a mass erase */ 391 #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is 392 decreased from Level 1 to Level 0 (full mass erase) */ 393 394 /** 395 * @} 396 */ 397 398 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection 399 * @{ 400 */ 401 #if (FLASH_SECTOR_TOTAL == 128) 402 #define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ 403 #define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ 404 #define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ 405 #define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ 406 #define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ 407 #define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ 408 #define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ 409 #define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ 410 #define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ 411 #define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ 412 #define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ 413 #define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ 414 #define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ 415 #define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ 416 #define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ 417 #define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ 418 #define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ 419 #define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ 420 #define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ 421 #define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ 422 #define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ 423 #define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ 424 #define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ 425 #define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ 426 #define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ 427 #define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ 428 #define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ 429 #define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ 430 #define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ 431 #define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ 432 #define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ 433 #define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ 434 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ 435 #else 436 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 437 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 438 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 439 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 440 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 441 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 442 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 443 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 444 #define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ 445 #endif /* FLASH_SECTOR_TOTAL == 128 */ 446 /** 447 * @} 448 */ 449 450 /** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY 451 * @{ 452 */ 453 #define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ 454 #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ 455 /** 456 * @} 457 */ 458 459 /** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE 460 * @{ 461 */ 462 #define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ 463 #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ 464 #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ 465 #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ 466 /** 467 * @} 468 */ 469 470 #if defined(DUAL_CORE) 471 /** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 472 * @{ 473 */ 474 #define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ 475 #define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ 476 477 /** 478 * @} 479 */ 480 481 /** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 482 * @{ 483 */ 484 #define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ 485 #define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ 486 /** 487 * @} 488 */ 489 #endif /* DUAL_CORE */ 490 491 /** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW 492 * @{ 493 */ 494 #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ 495 #define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ 496 /** 497 * @} 498 */ 499 500 #if defined(DUAL_CORE) 501 /** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW 502 * @{ 503 */ 504 #define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ 505 #define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ 506 /** 507 * @} 508 */ 509 #endif 510 511 /** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 512 * @{ 513 */ 514 #define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ 515 #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ 516 /** 517 * @} 518 */ 519 520 /** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 521 * @{ 522 */ 523 #define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ 524 #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ 525 /** 526 * @} 527 */ 528 529 #if defined (FLASH_OPTSR_NRST_STOP_D2) 530 /** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 531 * @{ 532 */ 533 #define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ 534 #define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ 535 /** 536 * @} 537 */ 538 539 /** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 540 * @{ 541 */ 542 #define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ 543 #define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ 544 /** 545 * @} 546 */ 547 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 548 549 #if defined (DUAL_BANK) 550 /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK 551 * @{ 552 */ 553 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 554 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ 555 /** 556 * @} 557 */ 558 #endif /* DUAL_BANK */ 559 560 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV 561 * @{ 562 */ 563 #define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ 564 #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ 565 /** 566 * @} 567 */ 568 569 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 570 /** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV 571 * @{ 572 */ 573 #define OB_VDDMMC_HSLV_DISABLE 0x00000000U /*!< VDDMMC HSLV disabled */ 574 #define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */ 575 /** 576 * @} 577 */ 578 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 579 580 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 581 /** @defgroup FLASHEx_OB_CPUFREQ_BOOST FLASHEx OB CPUFREQ BOOST 582 * @{ 583 */ 584 #define OB_CPUFREQ_BOOST_DISABLE 0x00000000U /*!< CPUFREQ BOOST disabled */ 585 #define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST /*!< CPUFREQ BOOST enabled */ 586 /** 587 * @} 588 */ 589 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 590 591 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 592 /** @defgroup FLASHEx_OB_TCM_AXI_SHARED FLASHEx OB TCM AXI SHARED 593 * @{ 594 */ 595 #define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U /*!< 64KB ITCM / 320KB system AXI */ 596 #define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0 /*!< 128KB ITCM / 256KB system AXI */ 597 #define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1 /*!< 192KB ITCM / 192KB system AXI */ 598 #define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED /*!< 256KB ITCM / 128KB system AXI */ 599 /** 600 * @} 601 */ 602 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 603 604 /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type 605 * @{ 606 */ 607 #define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ 608 #define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ 609 #define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ 610 #define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ 611 #define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ 612 #define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ 613 #define OB_USER_SECURITY 0x0040U /*!< security selection */ 614 #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ 615 #if defined (DUAL_BANK) 616 #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ 617 #endif /* DUAL_BANK */ 618 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 619 #define OB_USER_VDDMMC_HSLV 0x0200U /*!< VDDMMC HSLV selection */ 620 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 621 #if defined (DUAL_CORE) 622 #define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ 623 #define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ 624 #define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ 625 #endif /*DUAL_CORE*/ 626 #if defined (FLASH_OPTSR_NRST_STOP_D2) 627 #define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection */ 628 #define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection */ 629 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 630 631 #if defined (DUAL_CORE) 632 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 633 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 634 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ 635 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ 636 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) 637 #elif defined (FLASH_OPTSR_VDDMMC_HSLV) 638 #if defined (DUAL_BANK) 639 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 640 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 641 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ 642 OB_USER_VDDMMC_HSLV) 643 #else 644 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 645 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 646 OB_USER_SECURITY | OB_USER_IOHSLV |\ 647 OB_USER_VDDMMC_HSLV) 648 #endif /* DUAL_BANK */ 649 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) 650 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 651 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 652 OB_USER_SECURITY | OB_USER_IOHSLV |\ 653 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) 654 #else /* Single core */ 655 #if defined (DUAL_BANK) 656 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 657 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 658 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) 659 #else 660 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ 661 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ 662 OB_USER_SECURITY | OB_USER_IOHSLV ) 663 #endif /* DUAL_BANK */ 664 #endif /* DUAL_CORE */ 665 /** 666 * @} 667 */ 668 669 /** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION 670 * @{ 671 */ 672 #define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ 673 #define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ 674 #define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ 675 /** 676 * @} 677 */ 678 679 /** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP 680 * @{ 681 */ 682 #define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level 683 is decreased from Level 1 to Level 0 or during a mass erase */ 684 #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is 685 decreased from Level 1 to Level 0 (full mass erase) */ 686 /** 687 * @} 688 */ 689 690 /** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type 691 * @{ 692 */ 693 #define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ 694 #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ 695 #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ 696 /** 697 * @} 698 */ 699 700 /** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size 701 * @{ 702 */ 703 #define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ 704 #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ 705 #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ 706 #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ 707 /** 708 * @} 709 */ 710 711 /** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay 712 * @{ 713 */ 714 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ 715 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ 716 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ 717 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ 718 /** 719 * @} 720 */ 721 722 #if defined (FLASH_OTPBL_LOCKBL) 723 /** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks 724 * @{ 725 */ 726 #define FLASH_OTP_BLOCK_0 0x00000001U /*!< OTP Block0 */ 727 #define FLASH_OTP_BLOCK_1 0x00000002U /*!< OTP Block1 */ 728 #define FLASH_OTP_BLOCK_2 0x00000004U /*!< OTP Block2 */ 729 #define FLASH_OTP_BLOCK_3 0x00000008U /*!< OTP Block3 */ 730 #define FLASH_OTP_BLOCK_4 0x00000010U /*!< OTP Block4 */ 731 #define FLASH_OTP_BLOCK_5 0x00000020U /*!< OTP Block5 */ 732 #define FLASH_OTP_BLOCK_6 0x00000040U /*!< OTP Block6 */ 733 #define FLASH_OTP_BLOCK_7 0x00000080U /*!< OTP Block7 */ 734 #define FLASH_OTP_BLOCK_8 0x00000100U /*!< OTP Block8 */ 735 #define FLASH_OTP_BLOCK_9 0x00000200U /*!< OTP Block9 */ 736 #define FLASH_OTP_BLOCK_10 0x00000400U /*!< OTP Block10 */ 737 #define FLASH_OTP_BLOCK_11 0x00000800U /*!< OTP Block11 */ 738 #define FLASH_OTP_BLOCK_12 0x00001000U /*!< OTP Block12 */ 739 #define FLASH_OTP_BLOCK_13 0x00002000U /*!< OTP Block13 */ 740 #define FLASH_OTP_BLOCK_14 0x00004000U /*!< OTP Block14 */ 741 #define FLASH_OTP_BLOCK_15 0x00008000U /*!< OTP Block15 */ 742 #define FLASH_OTP_BLOCK_ALL 0x0000FFFFU /*!< OTP All Blocks */ 743 /** 744 * @} 745 */ 746 #endif /* FLASH_OTPBL_LOCKBL */ 747 /** 748 * @} 749 */ 750 751 /* Exported macro ------------------------------------------------------------*/ 752 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros 753 * @{ 754 */ 755 /** 756 * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) 757 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. 758 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) 759 * @retval The FLASH Boot Base Address 760 */ 761 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) 762 763 #if defined (FLASH_CR_PSIZE) 764 /** 765 * @brief Set the FLASH Program/Erase parallelism. 766 * @param __PSIZE__ FLASH Program/Erase parallelism 767 * This parameter can be a value of @ref FLASH_Program_Parallelism 768 * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 769 * @retval none 770 */ 771 #if defined (DUAL_BANK) 772 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 773 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ 774 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) 775 #else 776 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) 777 #endif /* DUAL_BANK */ 778 779 /** 780 * @brief Get the FLASH Program/Erase parallelism. 781 * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 782 * @retval FLASH Program/Erase parallelism 783 * This return value can be a value of @ref FLASH_Program_Parallelism 784 */ 785 #if defined (DUAL_BANK) 786 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 787 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ 788 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) 789 #else 790 #define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) 791 #endif /* DUAL_BANK */ 792 793 #endif /* FLASH_CR_PSIZE */ 794 795 /** 796 * @brief Set the FLASH Programming Delay. 797 * @param __DELAY__ FLASH Programming Delay 798 * This parameter can be a value of @ref FLASHEx_Programming_Delay 799 * @retval none 800 */ 801 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 802 803 /** 804 * @brief Get the FLASH Programming Delay. 805 * @retval FLASH Programming Delay 806 * This return value can be a value of @ref FLASHEx_Programming_Delay 807 */ 808 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 809 /** 810 * @} 811 */ 812 813 /* Exported functions --------------------------------------------------------*/ 814 /** @addtogroup FLASHEx_Exported_Functions 815 * @{ 816 */ 817 818 /** @addtogroup FLASHEx_Exported_Functions_Group1 819 * @{ 820 */ 821 /* Extension Program operation functions *************************************/ 822 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 823 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 824 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 825 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 826 827 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); 828 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); 829 #if defined (DUAL_BANK) 830 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); 831 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); 832 #endif /* DUAL_BANK */ 833 834 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); 835 836 /** 837 * @} 838 */ 839 840 /** 841 * @} 842 */ 843 /* Private types -------------------------------------------------------------*/ 844 /* Private variables ---------------------------------------------------------*/ 845 /* Private constants ---------------------------------------------------------*/ 846 /* Private macros ------------------------------------------------------------*/ 847 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 848 * @{ 849 */ 850 851 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 852 * @{ 853 */ 854 855 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 856 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 857 858 #if defined (FLASH_CR_PSIZE) 859 #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ 860 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ 861 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ 862 ((RANGE) == FLASH_VOLTAGE_RANGE_4)) 863 #endif /* FLASH_CR_PSIZE */ 864 865 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 866 ((VALUE) == OB_WRPSTATE_ENABLE)) 867 868 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \ 869 (((VALUE) & ~OPTIONBYTE_ALL) == 0U)) 870 871 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) 872 873 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 874 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 875 ((LEVEL) == OB_RDP_LEVEL_2)) 876 877 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 878 879 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) 880 881 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) 882 883 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) 884 885 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) 886 887 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ 888 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) 889 890 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 891 ((LATENCY) == FLASH_LATENCY_1) || \ 892 ((LATENCY) == FLASH_LATENCY_2) || \ 893 ((LATENCY) == FLASH_LATENCY_3) || \ 894 ((LATENCY) == FLASH_LATENCY_4) || \ 895 ((LATENCY) == FLASH_LATENCY_5) || \ 896 ((LATENCY) == FLASH_LATENCY_6) || \ 897 ((LATENCY) == FLASH_LATENCY_7) || \ 898 ((LATENCY) == FLASH_LATENCY_8) || \ 899 ((LATENCY) == FLASH_LATENCY_9) || \ 900 ((LATENCY) == FLASH_LATENCY_10) || \ 901 ((LATENCY) == FLASH_LATENCY_11) || \ 902 ((LATENCY) == FLASH_LATENCY_12) || \ 903 ((LATENCY) == FLASH_LATENCY_13) || \ 904 ((LATENCY) == FLASH_LATENCY_14) || \ 905 ((LATENCY) == FLASH_LATENCY_15)) 906 907 #define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) 908 909 #if (FLASH_SECTOR_TOTAL == 8U) 910 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) 911 #else 912 #define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U) 913 #endif /* FLASH_SECTOR_TOTAL == 8U */ 914 915 #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ 916 ((CONFIG) == OB_PCROP_RDP_ERASE)) 917 918 #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ 919 ((CONFIG) == OB_SECURE_RDP_ERASE)) 920 921 #if defined (DUAL_BANK) 922 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 923 #endif /* DUAL_BANK */ 924 925 #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) 926 927 #if defined (FLASH_OPTSR_VDDMMC_HSLV) 928 #define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE)) 929 #endif /* FLASH_OPTSR_VDDMMC_HSLV */ 930 931 #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) 932 #if defined (DUAL_CORE) 933 #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) 934 #endif /* DUAL_CORE */ 935 #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) 936 937 #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) 938 939 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 940 941 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 942 943 #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ 944 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) 945 946 #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) 947 948 #if defined (DUAL_CORE) 949 #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) 950 951 #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) 952 #endif /* DUAL_CORE */ 953 954 #if defined (FLASH_OPTSR_NRST_STOP_D2) 955 #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) 956 957 #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) 958 #endif /* FLASH_OPTSR_NRST_STOP_D2 */ 959 960 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED) 961 #define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \ 962 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB)) 963 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */ 964 965 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST) 966 #define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE)) 967 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */ 968 969 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \ 970 (((TYPE) & ~OB_USER_ALL) == 0U)) 971 972 #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ 973 ((VALUE) == OB_BOOT_ADD1) || \ 974 ((VALUE) == OB_BOOT_ADD_BOTH)) 975 976 #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ 977 ((VALUE) == FLASH_CRC_SECTORS) || \ 978 ((VALUE) == FLASH_CRC_BANK)) 979 980 #if defined (FLASH_OTPBL_LOCKBL) 981 #define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U)) 982 #endif /* FLASH_OTPBL_LOCKBL */ 983 /** 984 * @} 985 */ 986 987 /** 988 * @} 989 */ 990 991 /* Private functions ---------------------------------------------------------*/ 992 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 993 * @{ 994 */ 995 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); 996 /** 997 * @} 998 */ 999 1000 /** 1001 * @} 1002 */ 1003 1004 /** 1005 * @} 1006 */ 1007 1008 #ifdef __cplusplus 1009 } 1010 #endif 1011 1012 #endif /* STM32H7xx_HAL_FLASH_EX_H */ 1013 1014
