1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_dac.c
4 * @author MCD Application Team
5 * @brief DAC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Digital to Analog Converter (DAC) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 *
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2023 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### DAC Peripheral features #####
28 ==============================================================================
29 [..]
30 *** DAC Channels ***
31 ====================
32 [..]
33 STM32H5 devices integrate two 12-bit Digital Analog Converters
34
35 The 2 converters (i.e. channel1 & channel2)
36 can be used independently or simultaneously (dual mode):
37 (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip
38 peripherals (ex. ADC).
39 (#) DAC channel2 with DAC_OUT2 (PA5) as output or connected to on-chip
40 peripherals (ex. ADC).
41
42 *** DAC Triggers ***
43 ====================
44 [..]
45 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
46 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
47 [..]
48 Digital to Analog conversion can be triggered by:
49 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
50 The used pin (GPIOx_PIN_9) must be configured in input mode.
51
52 (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM8 and TIM15
53 (DAC_TRIGGER_T1_TRGO, DAC_TRIGGER_T2_TRGO...)
54
55 (#) Low Power Timers CH1: LPTIM1 and LPTIM2
56 (DAC_TRIGGER_LPTIM1_CH1, DAC_TRIGGER_LPTIM2_CH1)
57
58 (#) Software using DAC_TRIGGER_SOFTWARE
59 [..]
60 The trigger selection depends on the PWR mode:
61 in stop0, stop1 and stop2 we should select DAC_TRIGGER_EXT_IT9,
62 DAC_TRIGGER_LPTIM1_CH1 or DAC_TRIGGER_LPTIM2_CH1.The other triggers
63 are not functional.
64 *** DAC Buffer mode feature ***
65 ===============================
66 [..]
67 Each DAC channel integrates an output buffer that can be used to
68 reduce the output impedance, and to drive external loads directly
69 without having to add an external operational amplifier.
70 To enable, the output buffer use
71 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
72 [..]
73 (@) Refer to the device datasheet for more details about output
74 impedance value with and without output buffer.
75
76 *** GPIO configurations guidelines ***
77 =====================
78 [..]
79 When a DAC channel is used (ex channel1 on PA4) and the other is not
80 (ex channel2 on PA5 is configured in Analog and disabled).
81 Channel1 may disturb channel2 as coupling effect.
82 Note that there is no coupling on channel2 as soon as channel2 is turned on.
83 Coupling on adjacent channel could be avoided as follows:
84 when unused PA5 is configured as INPUT PULL-UP or DOWN.
85 PA5 is configured in ANALOG just before it is turned on.
86
87 *** DAC Sample and Hold feature ***
88 ========================
89 [..]
90 For each converter, 2 modes are supported: normal mode and
91 "sample and hold" mode (i.e. low power mode).
92 In the sample and hold mode, the DAC core converts data, then holds the
93 converted voltage on a capacitor. When not converting, the DAC cores and
94 buffer are completely turned off between samples and the DAC output is
95 tri-stated, therefore reducing the overall power consumption. A new
96 stabilization period is needed before each new conversion.
97
98 The sample and hold allow setting internal or external voltage @
99 low power consumption cost (output value can be at any given rate either
100 by CPU or DMA).
101
102 The Sample and hold block and registers uses either LSI & run in
103 several power modes: run mode, sleep mode, low power run, low power sleep
104 mode & stop1 mode.
105
106 Low power stop1 mode allows only static conversion.
107
108 To enable Sample and Hold mode
109 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
110 RCC_LSI_ON parameters.
111
112 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
113 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
114 DAC_HoldTime & DAC_RefreshTime;
115
116 *** DAC calibration feature ***
117 ===================================
118 [..]
119 (#) The 2 converters (channel1 & channel2) provide calibration capabilities.
120 (++) Calibration aims at correcting some offset of output buffer.
121 (++) The DAC uses either factory calibration settings OR user defined
122 calibration (trimming) settings (i.e. trimming mode).
123 (++) The user defined settings can be figured out using self calibration
124 handled by HAL_DACEx_SelfCalibrate.
125 (++) HAL_DACEx_SelfCalibrate:
126 (+++) Runs automatically the calibration.
127 (+++) Enables the user trimming mode
128 (+++) Updates a structure with trimming values with fresh calibration
129 results.
130 The user may store the calibration results for larger
131 (ex monitoring the trimming as a function of temperature
132 for instance)
133
134 *** DAC wave generation feature ***
135 ===================================
136 [..]
137 Both DAC channels can be used to generate
138 (#) Noise wave
139 (#) Triangle wave
140
141 *** DAC data format ***
142 =======================
143 [..]
144 The DAC data format can be:
145 (#) 8-bit right alignment using DAC_ALIGN_8B_R
146 (#) 12-bit left alignment using DAC_ALIGN_12B_L
147 (#) 12-bit right alignment using DAC_ALIGN_12B_R
148
149 *** DAC data value to voltage correspondence ***
150 ================================================
151 [..]
152 The analog output voltage on each DAC channel pin is determined
153 by the following equation:
154 [..]
155 DAC_OUTx = VREF+ * DOR / 4095
156 (+) with DOR is the Data Output Register
157 [..]
158 VREF+ is the input voltage reference (refer to the device datasheet)
159 [..]
160 e.g. To set DAC_OUT1 to 0.7V, use
161 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
162
163 *** DMA requests ***
164 =====================
165 [..]
166 A DMA request can be generated when an external trigger (but not a software trigger)
167 occurs if DMA requests are enabled using HAL_DAC_Start_DMA().
168 DMA requests are mapped as following:
169 GPDMA requests are mapped as following:
170 (+) DAC channel1 mapped on GPDMA request 2 (can be any GPDMA channel)
171 (+) DAC channel2 mapped on GPDMA request 3 (can be any GPDMA channel)
172
173 *** High frequency interface mode ***
174 =====================================
175 [..]
176 The high frequency interface informs DAC instance about the bus frequency in use.
177 It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
178 provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
179 Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
180 function figured out the correct setting.
181 The high frequency mode is same for all converters of a same DAC instance. Either same
182 parameter DAC_HighFrequency is used for all DAC converters or again self
183 DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
184
185 [..]
186 (@) For Dual mode and specific signal (Triangle and noise) generation please
187 refer to Extended Features Driver description
188
189 ##### How to use this driver #####
190 ==============================================================================
191 [..]
192 (+) DAC APB clock must be enabled to get write access to DAC
193 registers using HAL_DAC_Init()
194 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
195 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
196 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
197
198 *** Calibration mode IO operation ***
199 ======================================
200 [..]
201 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
202 (+) Run the calibration using HAL_DACEx_SelfCalibrate()
203 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
204
205 *** Polling mode IO operation ***
206 =================================
207 [..]
208 (+) Start the DAC peripheral using HAL_DAC_Start()
209 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
210 (+) Stop the DAC peripheral using HAL_DAC_Stop()
211
212 *** DMA mode IO operation ***
213 ==============================
214 [..]
215 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
216 of data to be transferred at each end of conversion
217 First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
218 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
219 function is executed and user can add his own code by customization of function pointer
220 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
221 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
222 function is executed and user can add his own code by customization of function pointer
223 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
224 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
225 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
226 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
227 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
228 function is executed and user can add his own code by customization of function pointer
229 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
230 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
231 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
232
233 *** Callback registration ***
234 =============================================
235 [..]
236 The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
237 allows the user to configure dynamically the driver callbacks.
238
239 Use Functions HAL_DAC_RegisterCallback() to register a user callback,
240 it allows to register following callbacks:
241 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
242 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
243 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
244 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
245 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
246 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
247 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
248 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
249 (+) MspInitCallback : DAC MspInit.
250 (+) MspDeInitCallback : DAC MspdeInit.
251 This function takes as parameters the HAL peripheral handle, the Callback ID
252 and a pointer to the user callback function.
253
254 Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
255 weak (overridden) function. It allows to reset following callbacks:
256 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1.
257 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
258 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1.
259 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1.
260 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2.
261 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
262 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2.
263 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2.
264 (+) MspInitCallback : DAC MspInit.
265 (+) MspDeInitCallback : DAC MspdeInit.
266 (+) All Callbacks
267 This function) takes as parameters the HAL peripheral handle and the Callback ID.
268
269 By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
270 all callbacks are reset to the corresponding legacy weak (overridden) functions.
271 Exception done for MspInit and MspDeInit callbacks that are respectively
272 reset to the legacy weak (overridden) functions in the HAL_DAC_Init
273 and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
274 If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
275 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
276
277 Callbacks can be registered/unregistered in READY state only.
278 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
279 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
280 during the Init/DeInit.
281 In that case first register the MspInit/MspDeInit user callbacks
282 using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
283 or HAL_DAC_Init function.
284
285 When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
286 not defined, the callback registering feature is not available
287 and weak (overridden) callbacks are used.
288
289 *** DAC HAL driver macros list ***
290 =============================================
291 [..]
292 Below the list of most used macros in DAC HAL driver.
293
294 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
295 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
296 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
297 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
298
299 [..]
300 (@) You can refer to the DAC HAL driver header file for more useful macros
301
302 @endverbatim
303 ******************************************************************************
304 */
305
306 /* Includes ------------------------------------------------------------------*/
307 #include "stm32h5xx_hal.h"
308
309 /** @addtogroup STM32H5xx_HAL_Driver
310 * @{
311 */
312
313 #ifdef HAL_DAC_MODULE_ENABLED
314 #if defined(DAC1)
315
316 /** @defgroup DAC DAC
317 * @brief DAC driver modules
318 * @{
319 */
320
321 /* Private typedef -----------------------------------------------------------*/
322 /* Private define ------------------------------------------------------------*/
323 /* Private constants ---------------------------------------------------------*/
324 /** @addtogroup DAC_Private_Constants DAC Private Constants
325 * @{
326 */
327 #define TIMEOUT_DAC_CALIBCONFIG 1U /* 1 ms */
328 #define HFSEL_ENABLE_THRESHOLD_80MHZ 80000000U /* 80 MHz */
329 #define HFSEL_ENABLE_THRESHOLD_160MHZ 160000000U /* 160 MHz */
330
331 /**
332 * @}
333 */
334
335 /* Private macro -------------------------------------------------------------*/
336 /* Private variables ---------------------------------------------------------*/
337 /* Private function prototypes -----------------------------------------------*/
338 /* Exported functions -------------------------------------------------------*/
339
340 /** @defgroup DAC_Exported_Functions DAC Exported Functions
341 * @{
342 */
343
344 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
345 * @brief Initialization and Configuration functions
346 *
347 @verbatim
348 ==============================================================================
349 ##### Initialization and de-initialization functions #####
350 ==============================================================================
351 [..] This section provides functions allowing to:
352 (+) Initialize and configure the DAC.
353 (+) De-initialize the DAC.
354
355 @endverbatim
356 * @{
357 */
358
359 /**
360 * @brief Initialize the DAC peripheral according to the specified parameters
361 * in the DAC_InitStruct and initialize the associated handle.
362 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
363 * the configuration information for the specified DAC.
364 * @retval HAL status
365 */
HAL_DAC_Init(DAC_HandleTypeDef * hdac)366 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
367 {
368 /* Check the DAC peripheral handle */
369 if (hdac == NULL)
370 {
371 return HAL_ERROR;
372 }
373 /* Check the parameters */
374 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
375
376 if (hdac->State == HAL_DAC_STATE_RESET)
377 {
378 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
379 /* Init the DAC Callback settings */
380 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
381 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
382 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
383 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
384
385 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
386 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
387 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
388 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
389
390 if (hdac->MspInitCallback == NULL)
391 {
392 hdac->MspInitCallback = HAL_DAC_MspInit;
393 }
394 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
395
396 /* Allocate lock resource and initialize it */
397 hdac->Lock = HAL_UNLOCKED;
398
399 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
400 /* Init the low level hardware */
401 hdac->MspInitCallback(hdac);
402 #else
403 /* Init the low level hardware */
404 HAL_DAC_MspInit(hdac);
405 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
406 }
407
408 /* Initialize the DAC state*/
409 hdac->State = HAL_DAC_STATE_BUSY;
410
411 /* Set DAC error code to none */
412 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
413
414 /* Initialize the DAC state*/
415 hdac->State = HAL_DAC_STATE_READY;
416
417 /* Return function status */
418 return HAL_OK;
419 }
420
421 /**
422 * @brief Deinitialize the DAC peripheral registers to their default reset values.
423 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
424 * the configuration information for the specified DAC.
425 * @retval HAL status
426 */
HAL_DAC_DeInit(DAC_HandleTypeDef * hdac)427 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
428 {
429 /* Check the DAC peripheral handle */
430 if (hdac == NULL)
431 {
432 return HAL_ERROR;
433 }
434
435 /* Check the parameters */
436 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
437
438 /* Change DAC state */
439 hdac->State = HAL_DAC_STATE_BUSY;
440
441 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
442 if (hdac->MspDeInitCallback == NULL)
443 {
444 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
445 }
446 /* DeInit the low level hardware */
447 hdac->MspDeInitCallback(hdac);
448 #else
449 /* DeInit the low level hardware */
450 HAL_DAC_MspDeInit(hdac);
451 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
452
453 /* Set DAC error code to none */
454 hdac->ErrorCode = HAL_DAC_ERROR_NONE;
455
456 /* Change DAC state */
457 hdac->State = HAL_DAC_STATE_RESET;
458
459 /* Release Lock */
460 __HAL_UNLOCK(hdac);
461
462 /* Return function status */
463 return HAL_OK;
464 }
465
466 /**
467 * @brief Initialize the DAC MSP.
468 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
469 * the configuration information for the specified DAC.
470 * @retval None
471 */
HAL_DAC_MspInit(DAC_HandleTypeDef * hdac)472 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
473 {
474 /* Prevent unused argument(s) compilation warning */
475 UNUSED(hdac);
476
477 /* NOTE : This function should not be modified, when the callback is needed,
478 the HAL_DAC_MspInit could be implemented in the user file
479 */
480 }
481
482 /**
483 * @brief DeInitialize the DAC MSP.
484 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
485 * the configuration information for the specified DAC.
486 * @retval None
487 */
HAL_DAC_MspDeInit(DAC_HandleTypeDef * hdac)488 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
489 {
490 /* Prevent unused argument(s) compilation warning */
491 UNUSED(hdac);
492
493 /* NOTE : This function should not be modified, when the callback is needed,
494 the HAL_DAC_MspDeInit could be implemented in the user file
495 */
496 }
497
498 /**
499 * @}
500 */
501
502 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions
503 * @brief IO operation functions
504 *
505 @verbatim
506 ==============================================================================
507 ##### IO operation functions #####
508 ==============================================================================
509 [..] This section provides functions allowing to:
510 (+) Start conversion.
511 (+) Stop conversion.
512 (+) Start conversion and enable DMA transfer.
513 (+) Stop conversion and disable DMA transfer.
514 (+) Get result of conversion.
515
516 @endverbatim
517 * @{
518 */
519
520 /**
521 * @brief Enables DAC and starts conversion of channel.
522 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
523 * the configuration information for the specified DAC.
524 * @param Channel The selected DAC channel.
525 * This parameter can be one of the following values:
526 * @arg DAC_CHANNEL_1: DAC Channel1 selected
527 * @arg DAC_CHANNEL_2: DAC Channel2 selected
528 * @retval HAL status
529 */
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)530 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
531 {
532 __IO uint32_t wait_loop_index;
533
534 /* Check the DAC peripheral handle */
535 if (hdac == NULL)
536 {
537 return HAL_ERROR;
538 }
539
540 /* Check the parameters */
541 assert_param(IS_DAC_CHANNEL(Channel));
542
543 /* Process locked */
544 __HAL_LOCK(hdac);
545
546 /* Change DAC state */
547 hdac->State = HAL_DAC_STATE_BUSY;
548
549 /* Enable the Peripheral */
550 __HAL_DAC_ENABLE(hdac, Channel);
551 /* Ensure minimum wait before using peripheral after enabling it */
552 /* Wait loop initialization and execution */
553 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
554 /* bits register capacity and handle low frequency. */
555 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
556 while (wait_loop_index != 0UL)
557 {
558 wait_loop_index--;
559 }
560
561 if (Channel == DAC_CHANNEL_1)
562 {
563 /* Check if software trigger enabled */
564 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
565 {
566 /* Enable the selected DAC software conversion */
567 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
568 }
569 }
570
571 else
572 {
573 /* Check if software trigger enabled */
574 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
575 {
576 /* Enable the selected DAC software conversion*/
577 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
578 }
579 }
580
581
582 /* Change DAC state */
583 hdac->State = HAL_DAC_STATE_READY;
584
585 /* Process unlocked */
586 __HAL_UNLOCK(hdac);
587
588 /* Return function status */
589 return HAL_OK;
590 }
591
592 /**
593 * @brief Disables DAC and stop conversion of channel.
594 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
595 * the configuration information for the specified DAC.
596 * @param Channel The selected DAC channel.
597 * This parameter can be one of the following values:
598 * @arg DAC_CHANNEL_1: DAC Channel1 selected
599 * @arg DAC_CHANNEL_2: DAC Channel2 selected
600 * @retval HAL status
601 */
HAL_DAC_Stop(DAC_HandleTypeDef * hdac,uint32_t Channel)602 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
603 {
604 /* Check the DAC peripheral handle */
605 if (hdac == NULL)
606 {
607 return HAL_ERROR;
608 }
609
610 /* Check the parameters */
611 assert_param(IS_DAC_CHANNEL(Channel));
612
613 /* Disable the Peripheral */
614 __HAL_DAC_DISABLE(hdac, Channel);
615
616 /* Change DAC state */
617 hdac->State = HAL_DAC_STATE_READY;
618
619 /* Return function status */
620 return HAL_OK;
621 }
622
623 /**
624 * @brief Enables DAC and starts conversion of channel.
625 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
626 * the configuration information for the specified DAC.
627 * @param Channel The selected DAC channel.
628 * This parameter can be one of the following values:
629 * @arg DAC_CHANNEL_1: DAC Channel1 selected
630 * @arg DAC_CHANNEL_2: DAC Channel2 selected
631 * @param pData The source Buffer address.
632 * @param Length The length of data to be transferred from memory to DAC peripheral
633 * @param Alignment Specifies the data alignment for DAC channel.
634 * This parameter can be one of the following values:
635 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
636 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
637 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
638 * @retval HAL status
639 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,const uint32_t * pData,uint32_t Length,uint32_t Alignment)640 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
641 uint32_t Alignment)
642 {
643 HAL_StatusTypeDef status;
644 uint32_t tmpreg;
645 uint32_t LengthInBytes;
646 DMA_NodeConfTypeDef node_conf;
647 __IO uint32_t wait_loop_index;
648
649 /* Check the DAC peripheral handle */
650 if (hdac == NULL)
651 {
652 return HAL_ERROR;
653 }
654
655 /* Check the parameters */
656 assert_param(IS_DAC_CHANNEL(Channel));
657 assert_param(IS_DAC_ALIGN(Alignment));
658
659 /* Process locked */
660 __HAL_LOCK(hdac);
661
662 /* Change DAC state */
663 hdac->State = HAL_DAC_STATE_BUSY;
664
665 if (Channel == DAC_CHANNEL_1)
666 {
667 /* Set the DMA transfer complete callback for channel1 */
668 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
669
670 /* Set the DMA half transfer complete callback for channel1 */
671 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
672
673 /* Set the DMA error callback for channel1 */
674 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
675
676 /* Enable the selected DAC channel1 DMA request */
677 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
678
679 /* Case of use of channel 1 */
680 switch (Alignment)
681 {
682 case DAC_ALIGN_12B_R:
683 /* Get DHR12R1 address */
684 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
685 break;
686 case DAC_ALIGN_12B_L:
687 /* Get DHR12L1 address */
688 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
689 break;
690 default: /* case DAC_ALIGN_8B_R */
691 /* Get DHR8R1 address */
692 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
693 break;
694 }
695 }
696
697 else
698 {
699 /* Set the DMA transfer complete callback for channel2 */
700 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
701
702 /* Set the DMA half transfer complete callback for channel2 */
703 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
704
705 /* Set the DMA error callback for channel2 */
706 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
707
708 /* Enable the selected DAC channel2 DMA request */
709 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
710
711 /* Case of use of channel 2 */
712 switch (Alignment)
713 {
714 case DAC_ALIGN_12B_R:
715 /* Get DHR12R2 address */
716 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
717 break;
718 case DAC_ALIGN_12B_L:
719 /* Get DHR12L2 address */
720 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
721 break;
722 default: /* case DAC_ALIGN_8B_R */
723 /* Get DHR8R2 address */
724 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
725 break;
726 }
727 }
728
729 if (Channel == DAC_CHANNEL_1)
730 {
731 /* Enable the DAC DMA underrun interrupt */
732 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
733
734 /* Enable the DMA channel */
735 /* Check linkedlist mode */
736 if ((hdac->DMA_Handle1->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
737 {
738 if ((hdac->DMA_Handle1->LinkedListQueue != NULL) && (hdac->DMA_Handle1->LinkedListQueue->Head != NULL))
739 {
740 /* Length should be converted to number of bytes */
741 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle1->LinkedListQueue->Head) != HAL_OK)
742 {
743 return HAL_ERROR;
744 }
745
746 /* Length should be converted to number of bytes */
747 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
748 {
749 /* Word -> Bytes */
750 LengthInBytes = Length * 4U;
751 }
752 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
753 {
754 /* Halfword -> Bytes */
755 LengthInBytes = Length * 2U;
756 }
757 else /* Bytes */
758 {
759 /* Same size already expressed in Bytes */
760 LengthInBytes = Length;
761 }
762
763 /* Set DMA data size */
764 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
765
766 /* Set DMA source address */
767 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
768
769 /* Set DMA destination address */
770 hdac->DMA_Handle1->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
771
772 /* Enable the DMA channel */
773 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle1);
774 }
775 else
776 {
777 /* Return error status */
778 return HAL_ERROR;
779 }
780 }
781 else
782 {
783 /* Length should be converted to number of bytes */
784 if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
785 {
786 /* Word -> Bytes */
787 LengthInBytes = Length * 4U;
788 }
789 else if (hdac->DMA_Handle1->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
790 {
791 /* Halfword -> Bytes */
792 LengthInBytes = Length * 2U;
793 }
794 else /* Bytes */
795 {
796 /* Same size already expressed in Bytes */
797 LengthInBytes = Length;
798 }
799
800 /* Enable the DMA channel */
801 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, LengthInBytes);
802 }
803 }
804
805 else
806 {
807 /* Enable the DAC DMA underrun interrupt */
808 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
809
810 /* Enable the DMA channel */
811 /* Check linkedlist mode */
812 if ((hdac->DMA_Handle2->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST)
813 {
814 if ((hdac->DMA_Handle2->LinkedListQueue != NULL) && (hdac->DMA_Handle2->LinkedListQueue->Head != NULL))
815 {
816 /* Length should be converted to number of bytes */
817 if (HAL_DMAEx_List_GetNodeConfig(&node_conf, hdac->DMA_Handle2->LinkedListQueue->Head) != HAL_OK)
818 {
819 return HAL_ERROR;
820 }
821
822 /* Length should be converted to number of bytes */
823 if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
824 {
825 /* Word -> Bytes */
826 LengthInBytes = Length * 4U;
827 }
828 else if (node_conf.Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
829 {
830 /* Halfword -> Bytes */
831 LengthInBytes = Length * 2U;
832 }
833 else /* Bytes */
834 {
835 /* Same size already expressed in Bytes */
836 LengthInBytes = Length;
837 }
838
839 /* Set DMA data size */
840 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = LengthInBytes;
841
842 /* Set DMA source address */
843 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData;
844
845 /* Set DMA destination address */
846 hdac->DMA_Handle2->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = tmpreg;
847
848 /* Enable the DMA channel */
849 status = HAL_DMAEx_List_Start_IT(hdac->DMA_Handle2);
850 }
851 else
852 {
853 /* Return error status */
854 return HAL_ERROR;
855 }
856 }
857 else
858 {
859 /* Length should be converted to number of bytes */
860 if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD)
861 {
862 /* Word -> Bytes */
863 LengthInBytes = Length * 4U;
864 }
865 else if (hdac->DMA_Handle2->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD)
866 {
867 /* Halfword -> Bytes */
868 LengthInBytes = Length * 2U;
869 }
870 else /* Bytes */
871 {
872 /* Same size already expressed in Bytes */
873 LengthInBytes = Length;
874 }
875
876 /* Enable the DMA channel */
877 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, LengthInBytes);
878 }
879 }
880
881
882 /* Process Unlocked */
883 __HAL_UNLOCK(hdac);
884
885 if (status == HAL_OK)
886 {
887 /* Enable the Peripheral */
888 __HAL_DAC_ENABLE(hdac, Channel);
889 /* Ensure minimum wait before using peripheral after enabling it */
890 /* Wait loop initialization and execution */
891 /* Note: Variable divided by 2 to compensate partially */
892 /* CPU processing cycles, scaling in us split to not */
893 /* exceed 32 bits register capacity and handle low frequency. */
894 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
895 while (wait_loop_index != 0UL)
896 {
897 wait_loop_index--;
898 }
899 }
900 else
901 {
902 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
903 }
904
905 /* Return function status */
906 return status;
907 }
908
909 /**
910 * @brief Disables DAC and stop conversion of channel.
911 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
912 * the configuration information for the specified DAC.
913 * @param Channel The selected DAC channel.
914 * This parameter can be one of the following values:
915 * @arg DAC_CHANNEL_1: DAC Channel1 selected
916 * @arg DAC_CHANNEL_2: DAC Channel2 selected
917 * @retval HAL status
918 */
HAL_DAC_Stop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)919 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
920 {
921 /* Check the DAC peripheral handle */
922 if (hdac == NULL)
923 {
924 return HAL_ERROR;
925 }
926
927 /* Check the parameters */
928 assert_param(IS_DAC_CHANNEL(Channel));
929
930 /* Disable the selected DAC channel DMA request */
931 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
932
933 /* Disable the Peripheral */
934 __HAL_DAC_DISABLE(hdac, Channel);
935
936 /* Disable the DMA channel */
937
938 /* Channel1 is used */
939 if (Channel == DAC_CHANNEL_1)
940 {
941 /* Disable the DMA channel */
942 (void)HAL_DMA_Abort(hdac->DMA_Handle1);
943
944 /* Disable the DAC DMA underrun interrupt */
945 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
946 }
947
948 else /* Channel2 is used for */
949 {
950 /* Disable the DMA channel */
951 (void)HAL_DMA_Abort(hdac->DMA_Handle2);
952
953 /* Disable the DAC DMA underrun interrupt */
954 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
955 }
956
957
958 /* Change DAC state */
959 hdac->State = HAL_DAC_STATE_READY;
960
961 /* Return function status */
962 return HAL_OK;
963 }
964
965 /**
966 * @brief Handles DAC interrupt request
967 * This function uses the interruption of DMA
968 * underrun.
969 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
970 * the configuration information for the specified DAC.
971 * @retval None
972 */
HAL_DAC_IRQHandler(DAC_HandleTypeDef * hdac)973 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
974 {
975 uint32_t itsource = hdac->Instance->CR;
976 uint32_t itflag = hdac->Instance->SR;
977
978 if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
979 {
980 /* Check underrun flag of DAC channel 1 */
981 if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
982 {
983 /* Change DAC state to error state */
984 hdac->State = HAL_DAC_STATE_ERROR;
985
986 /* Set DAC error code to channel1 DMA underrun error */
987 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
988
989 /* Clear the underrun flag */
990 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
991
992 /* Disable the selected DAC channel1 DMA request */
993 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
994
995 /* Error callback */
996 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
997 hdac->DMAUnderrunCallbackCh1(hdac);
998 #else
999 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
1000 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1001 }
1002 }
1003
1004
1005 if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
1006 {
1007 /* Check underrun flag of DAC channel 2 */
1008 if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
1009 {
1010 /* Change DAC state to error state */
1011 hdac->State = HAL_DAC_STATE_ERROR;
1012
1013 /* Set DAC error code to channel2 DMA underrun error */
1014 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
1015
1016 /* Clear the underrun flag */
1017 __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
1018
1019 /* Disable the selected DAC channel2 DMA request */
1020 __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
1021
1022 /* Error callback */
1023 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1024 hdac->DMAUnderrunCallbackCh2(hdac);
1025 #else
1026 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
1027 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1028 }
1029 }
1030
1031 }
1032
1033 /**
1034 * @brief Set the specified data holding register value for DAC channel.
1035 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1036 * the configuration information for the specified DAC.
1037 * @param Channel The selected DAC channel.
1038 * This parameter can be one of the following values:
1039 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1040 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1041 * @param Alignment Specifies the data alignment.
1042 * This parameter can be one of the following values:
1043 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
1044 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
1045 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
1046 * @param Data Data to be loaded in the selected data holding register.
1047 * @retval HAL status
1048 */
HAL_DAC_SetValue(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Alignment,uint32_t Data)1049 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
1050 {
1051 __IO uint32_t tmp = 0UL;
1052
1053 /* Check the DAC peripheral handle */
1054 if (hdac == NULL)
1055 {
1056 return HAL_ERROR;
1057 }
1058
1059 /* Check the parameters */
1060 assert_param(IS_DAC_CHANNEL(Channel));
1061 assert_param(IS_DAC_ALIGN(Alignment));
1062 /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
1063 if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
1064 {
1065 assert_param(IS_DAC_DATA(Data));
1066 }
1067
1068 tmp = (uint32_t)hdac->Instance;
1069 if (Channel == DAC_CHANNEL_1)
1070 {
1071 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
1072 }
1073
1074 else
1075 {
1076 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
1077 }
1078
1079
1080 /* Set the DAC channel selected data holding register */
1081 *(__IO uint32_t *) tmp = Data;
1082
1083 /* Return function status */
1084 return HAL_OK;
1085 }
1086
1087 /**
1088 * @brief Conversion complete callback in non-blocking mode for Channel1
1089 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1090 * the configuration information for the specified DAC.
1091 * @retval None
1092 */
HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef * hdac)1093 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1094 {
1095 /* Prevent unused argument(s) compilation warning */
1096 UNUSED(hdac);
1097
1098 /* NOTE : This function should not be modified, when the callback is needed,
1099 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
1100 */
1101 }
1102
1103 /**
1104 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1
1105 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1106 * the configuration information for the specified DAC.
1107 * @retval None
1108 */
HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef * hdac)1109 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
1110 {
1111 /* Prevent unused argument(s) compilation warning */
1112 UNUSED(hdac);
1113
1114 /* NOTE : This function should not be modified, when the callback is needed,
1115 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
1116 */
1117 }
1118
1119 /**
1120 * @brief Error DAC callback for Channel1.
1121 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1122 * the configuration information for the specified DAC.
1123 * @retval None
1124 */
HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef * hdac)1125 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
1126 {
1127 /* Prevent unused argument(s) compilation warning */
1128 UNUSED(hdac);
1129
1130 /* NOTE : This function should not be modified, when the callback is needed,
1131 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
1132 */
1133 }
1134
1135 /**
1136 * @brief DMA underrun DAC callback for channel1.
1137 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1138 * the configuration information for the specified DAC.
1139 * @retval None
1140 */
HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef * hdac)1141 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
1142 {
1143 /* Prevent unused argument(s) compilation warning */
1144 UNUSED(hdac);
1145
1146 /* NOTE : This function should not be modified, when the callback is needed,
1147 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
1148 */
1149 }
1150
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
1156 * @brief Peripheral Control functions
1157 *
1158 @verbatim
1159 ==============================================================================
1160 ##### Peripheral Control functions #####
1161 ==============================================================================
1162 [..] This section provides functions allowing to:
1163 (+) Configure channels.
1164 (+) Set the specified data holding register value for DAC channel.
1165
1166 @endverbatim
1167 * @{
1168 */
1169
1170 /**
1171 * @brief Returns the last data output value of the selected DAC channel.
1172 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1173 * the configuration information for the specified DAC.
1174 * @param Channel The selected DAC channel.
1175 * This parameter can be one of the following values:
1176 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1177 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1178 * @retval The selected DAC channel data output value.
1179 */
HAL_DAC_GetValue(const DAC_HandleTypeDef * hdac,uint32_t Channel)1180 uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
1181 {
1182 uint32_t result;
1183
1184 /* Check the DAC peripheral handle */
1185 assert_param(hdac != NULL);
1186
1187 /* Check the parameters */
1188 assert_param(IS_DAC_CHANNEL(Channel));
1189
1190 if (Channel == DAC_CHANNEL_1)
1191 {
1192 result = hdac->Instance->DOR1;
1193 }
1194
1195 else
1196 {
1197 result = hdac->Instance->DOR2;
1198 }
1199
1200 /* Returns the DAC channel data output register value */
1201 return result;
1202 }
1203
1204 /**
1205 * @brief Configures the selected DAC channel.
1206 * @note By calling this function, the high frequency interface mode (HFSEL bits)
1207 * will be set. This parameter scope is the DAC instance. As the function
1208 * is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
1209 * must be the same at each call.
1210 * (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
1211 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1212 * the configuration information for the specified DAC.
1213 * @param sConfig DAC configuration structure.
1214 * @param Channel The selected DAC channel.
1215 * This parameter can be one of the following values:
1216 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1217 * @arg DAC_CHANNEL_2: DAC Channel2 selected
1218 * @retval HAL status
1219 */
HAL_DAC_ConfigChannel(DAC_HandleTypeDef * hdac,const DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)1220 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
1221 const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
1222 {
1223 HAL_StatusTypeDef status = HAL_OK;
1224 uint32_t tmpreg1;
1225 uint32_t tmpreg2;
1226 uint32_t tickstart;
1227 uint32_t hclkfreq;
1228 uint32_t connectOnChip;
1229
1230 /* Check the DAC peripheral handle and channel configuration struct */
1231 if ((hdac == NULL) || (sConfig == NULL))
1232 {
1233 return HAL_ERROR;
1234 }
1235
1236 /* Check the DAC parameters */
1237 assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
1238 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
1239 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
1240 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
1241 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
1242 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
1243 {
1244 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
1245 }
1246 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
1247 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
1248 {
1249 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
1250 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
1251 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
1252 }
1253 assert_param(IS_DAC_CHANNEL(Channel));
1254 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
1255 assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
1256
1257 /* Process locked */
1258 __HAL_LOCK(hdac);
1259
1260 /* Change DAC state */
1261 hdac->State = HAL_DAC_STATE_BUSY;
1262
1263 /* Sample and hold configuration */
1264 if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
1265 {
1266 /* Get timeout */
1267 tickstart = HAL_GetTick();
1268
1269 if (Channel == DAC_CHANNEL_1)
1270 {
1271 /* SHSR1 can be written when BWST1 is cleared */
1272 while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1273 {
1274 /* Check for the Timeout */
1275 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1276 {
1277 /* New check to avoid false timeout detection in case of preemption */
1278 if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
1279 {
1280 /* Update error code */
1281 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1282
1283 /* Change the DMA state */
1284 hdac->State = HAL_DAC_STATE_TIMEOUT;
1285
1286 return HAL_TIMEOUT;
1287 }
1288 }
1289 }
1290 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1291 }
1292
1293 else /* Channel 2 */
1294 {
1295 /* SHSR2 can be written when BWST2 is cleared */
1296 while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1297 {
1298 /* Check for the Timeout */
1299 if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
1300 {
1301 /* New check to avoid false timeout detection in case of preemption */
1302 if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
1303 {
1304 /* Update error code */
1305 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
1306
1307 /* Change the DMA state */
1308 hdac->State = HAL_DAC_STATE_TIMEOUT;
1309
1310 return HAL_TIMEOUT;
1311 }
1312 }
1313 }
1314 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
1315 }
1316
1317
1318 /* HoldTime */
1319 MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
1320 (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
1321 /* RefreshTime */
1322 MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
1323 (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
1324 }
1325
1326 if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
1327 /* USER TRIMMING */
1328 {
1329 /* Get the DAC CCR value */
1330 tmpreg1 = hdac->Instance->CCR;
1331 /* Clear trimming value */
1332 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
1333 /* Configure for the selected trimming offset */
1334 tmpreg2 = sConfig->DAC_TrimmingValue;
1335 /* Calculate CCR register value depending on DAC_Channel */
1336 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1337 /* Write to DAC CCR */
1338 hdac->Instance->CCR = tmpreg1;
1339 }
1340 /* else factory trimming is used (factory setting are available at reset)*/
1341 /* SW Nothing has nothing to do */
1342
1343 /* Get the DAC MCR value */
1344 tmpreg1 = hdac->Instance->MCR;
1345 /* Clear DAC_MCR_MODEx bits */
1346 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
1347 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
1348
1349 #if !defined(TIM8)
1350 /* Devices STM32H503xx */
1351 /* On STM32H503EB (package WLCSP25) DAC channel 1 connection to GPIO is not available and should not be configured.
1352 Package information is stored at the address PACKAGE_BASE, WLCSP25 correspond to the value 0xF (For more
1353 information, please refer to the Reference Manual) */
1354 const __IO uint16_t *tmp_package = (uint16_t *)PACKAGE_BASE;
1355 if ((*(tmp_package) & 0x1FUL) == 0x0FUL)
1356 {
1357 if ((Channel == DAC_CHANNEL_1)
1358 && ((sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
1359 || (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH)))
1360 {
1361 /* Update return status */
1362 status = HAL_ERROR;
1363
1364 /* Change the DAC state */
1365 hdac->State = HAL_DAC_STATE_ERROR;
1366
1367 /* Update error code */
1368 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_INVALID_CONFIG);
1369 }
1370 }
1371 #endif /* Devices STM32H503xx */
1372
1373
1374 if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
1375 {
1376 connectOnChip = 0x00000000UL;
1377 }
1378 else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
1379 {
1380 connectOnChip = DAC_MCR_MODE1_0;
1381 }
1382 else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
1383 {
1384 if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
1385 {
1386 connectOnChip = DAC_MCR_MODE1_0;
1387 }
1388 else
1389 {
1390 connectOnChip = 0x00000000UL;
1391 }
1392 }
1393 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
1394 /* Clear DAC_MCR_DMADOUBLEx */
1395 tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
1396 /* Configure for the selected DAC channel: DMA double data mode */
1397 tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
1398 /* Clear DAC_MCR_SINFORMATx */
1399 tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
1400 /* Configure for the selected DAC channel: Signed format */
1401 tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
1402 /* Clear DAC_MCR_HFSEL bits */
1403 tmpreg1 &= ~(DAC_MCR_HFSEL);
1404 /* Configure for both DAC channels: high frequency mode */
1405 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
1406 {
1407 hclkfreq = HAL_RCC_GetHCLKFreq();
1408 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
1409 {
1410 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
1411 }
1412 else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
1413 {
1414 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
1415 }
1416 else
1417 {
1418 tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
1419 }
1420 }
1421 else
1422 {
1423 tmpreg1 |= sConfig->DAC_HighFrequency;
1424 }
1425 /* Calculate MCR register value depending on DAC_Channel */
1426 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1427 /* Write to DAC MCR */
1428 hdac->Instance->MCR = tmpreg1;
1429
1430 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
1431 CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
1432
1433 /* Get the DAC CR value */
1434 tmpreg1 = hdac->Instance->CR;
1435 /* Clear TENx, TSELx, WAVEx and MAMPx bits */
1436 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
1437 /* Configure for the selected DAC channel: trigger */
1438 /* Set TSELx and TENx bits according to DAC_Trigger value */
1439 tmpreg2 = sConfig->DAC_Trigger;
1440 /* Calculate CR register value depending on DAC_Channel */
1441 tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
1442 /* Write to DAC CR */
1443 hdac->Instance->CR = tmpreg1;
1444 /* Disable wave generation */
1445 CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
1446
1447 /* Change DAC state */
1448 hdac->State = HAL_DAC_STATE_READY;
1449
1450 /* Process unlocked */
1451 __HAL_UNLOCK(hdac);
1452
1453 /* Return function status */
1454 return status;
1455 }
1456
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
1462 * @brief Peripheral State and Errors functions
1463 *
1464 @verbatim
1465 ==============================================================================
1466 ##### Peripheral State and Errors functions #####
1467 ==============================================================================
1468 [..]
1469 This subsection provides functions allowing to
1470 (+) Check the DAC state.
1471 (+) Check the DAC Errors.
1472
1473 @endverbatim
1474 * @{
1475 */
1476
1477 /**
1478 * @brief return the DAC handle state
1479 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1480 * the configuration information for the specified DAC.
1481 * @retval HAL state
1482 */
HAL_DAC_GetState(const DAC_HandleTypeDef * hdac)1483 HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
1484 {
1485 /* Return DAC handle state */
1486 return hdac->State;
1487 }
1488
1489
1490 /**
1491 * @brief Return the DAC error code
1492 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1493 * the configuration information for the specified DAC.
1494 * @retval DAC Error Code
1495 */
HAL_DAC_GetError(const DAC_HandleTypeDef * hdac)1496 uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
1497 {
1498 return hdac->ErrorCode;
1499 }
1500
1501 /**
1502 * @}
1503 */
1504
1505 /**
1506 * @}
1507 */
1508
1509 /** @addtogroup DAC_Exported_Functions
1510 * @{
1511 */
1512
1513 /** @addtogroup DAC_Exported_Functions_Group1
1514 * @{
1515 */
1516 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1517 /**
1518 * @brief Register a User DAC Callback
1519 * To be used instead of the weak (overridden) predefined callback
1520 * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
1521 * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
1522 * @param hdac DAC handle
1523 * @param CallbackID ID of the callback to be registered
1524 * This parameter can be one of the following values:
1525 * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID
1526 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID
1527 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1528 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1529 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1530 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1531 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1532 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1533 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1534 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1535 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1536 *
1537 * @param pCallback pointer to the Callback function
1538 * @retval status
1539 */
HAL_DAC_RegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID,pDAC_CallbackTypeDef pCallback)1540 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
1541 pDAC_CallbackTypeDef pCallback)
1542 {
1543 HAL_StatusTypeDef status = HAL_OK;
1544
1545 /* Check the DAC peripheral handle */
1546 if (hdac == NULL)
1547 {
1548 return HAL_ERROR;
1549 }
1550
1551 if (pCallback == NULL)
1552 {
1553 /* Update the error code */
1554 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1555 return HAL_ERROR;
1556 }
1557
1558 if (hdac->State == HAL_DAC_STATE_READY)
1559 {
1560 switch (CallbackID)
1561 {
1562 case HAL_DAC_CH1_COMPLETE_CB_ID :
1563 hdac->ConvCpltCallbackCh1 = pCallback;
1564 break;
1565 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1566 hdac->ConvHalfCpltCallbackCh1 = pCallback;
1567 break;
1568 case HAL_DAC_CH1_ERROR_ID :
1569 hdac->ErrorCallbackCh1 = pCallback;
1570 break;
1571 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1572 hdac->DMAUnderrunCallbackCh1 = pCallback;
1573 break;
1574
1575 case HAL_DAC_CH2_COMPLETE_CB_ID :
1576 hdac->ConvCpltCallbackCh2 = pCallback;
1577 break;
1578 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1579 hdac->ConvHalfCpltCallbackCh2 = pCallback;
1580 break;
1581 case HAL_DAC_CH2_ERROR_ID :
1582 hdac->ErrorCallbackCh2 = pCallback;
1583 break;
1584 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1585 hdac->DMAUnderrunCallbackCh2 = pCallback;
1586 break;
1587
1588 case HAL_DAC_MSPINIT_CB_ID :
1589 hdac->MspInitCallback = pCallback;
1590 break;
1591 case HAL_DAC_MSPDEINIT_CB_ID :
1592 hdac->MspDeInitCallback = pCallback;
1593 break;
1594 default :
1595 /* Update the error code */
1596 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1597 /* update return status */
1598 status = HAL_ERROR;
1599 break;
1600 }
1601 }
1602 else if (hdac->State == HAL_DAC_STATE_RESET)
1603 {
1604 switch (CallbackID)
1605 {
1606 case HAL_DAC_MSPINIT_CB_ID :
1607 hdac->MspInitCallback = pCallback;
1608 break;
1609 case HAL_DAC_MSPDEINIT_CB_ID :
1610 hdac->MspDeInitCallback = pCallback;
1611 break;
1612 default :
1613 /* Update the error code */
1614 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1615 /* update return status */
1616 status = HAL_ERROR;
1617 break;
1618 }
1619 }
1620 else
1621 {
1622 /* Update the error code */
1623 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1624 /* update return status */
1625 status = HAL_ERROR;
1626 }
1627
1628 return status;
1629 }
1630
1631 /**
1632 * @brief Unregister a User DAC Callback
1633 * DAC Callback is redirected to the weak (overridden) predefined callback
1634 * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
1635 * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
1636 * @param hdac DAC handle
1637 * @param CallbackID ID of the callback to be unregistered
1638 * This parameter can be one of the following values:
1639 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
1640 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1641 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1642 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1643 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1644 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
1645 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID
1646 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID
1647 * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID
1648 * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID
1649 * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks
1650 * @retval status
1651 */
HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef * hdac,HAL_DAC_CallbackIDTypeDef CallbackID)1652 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
1653 {
1654 HAL_StatusTypeDef status = HAL_OK;
1655
1656 /* Check the DAC peripheral handle */
1657 if (hdac == NULL)
1658 {
1659 return HAL_ERROR;
1660 }
1661
1662 if (hdac->State == HAL_DAC_STATE_READY)
1663 {
1664 switch (CallbackID)
1665 {
1666 case HAL_DAC_CH1_COMPLETE_CB_ID :
1667 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1668 break;
1669 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
1670 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1671 break;
1672 case HAL_DAC_CH1_ERROR_ID :
1673 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1674 break;
1675 case HAL_DAC_CH1_UNDERRUN_CB_ID :
1676 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1677 break;
1678
1679 case HAL_DAC_CH2_COMPLETE_CB_ID :
1680 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1681 break;
1682 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1683 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1684 break;
1685 case HAL_DAC_CH2_ERROR_ID :
1686 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1687 break;
1688 case HAL_DAC_CH2_UNDERRUN_CB_ID :
1689 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1690 break;
1691
1692 case HAL_DAC_MSPINIT_CB_ID :
1693 hdac->MspInitCallback = HAL_DAC_MspInit;
1694 break;
1695 case HAL_DAC_MSPDEINIT_CB_ID :
1696 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1697 break;
1698 case HAL_DAC_ALL_CB_ID :
1699 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1700 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1701 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1702 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1703
1704 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1705 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1706 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1707 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1708
1709 hdac->MspInitCallback = HAL_DAC_MspInit;
1710 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1711 break;
1712 default :
1713 /* Update the error code */
1714 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1715 /* update return status */
1716 status = HAL_ERROR;
1717 break;
1718 }
1719 }
1720 else if (hdac->State == HAL_DAC_STATE_RESET)
1721 {
1722 switch (CallbackID)
1723 {
1724 case HAL_DAC_MSPINIT_CB_ID :
1725 hdac->MspInitCallback = HAL_DAC_MspInit;
1726 break;
1727 case HAL_DAC_MSPDEINIT_CB_ID :
1728 hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1729 break;
1730 default :
1731 /* Update the error code */
1732 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1733 /* update return status */
1734 status = HAL_ERROR;
1735 break;
1736 }
1737 }
1738 else
1739 {
1740 /* Update the error code */
1741 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
1742 /* update return status */
1743 status = HAL_ERROR;
1744 }
1745
1746 return status;
1747 }
1748 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1749
1750 /**
1751 * @}
1752 */
1753
1754 /**
1755 * @}
1756 */
1757
1758 /** @addtogroup DAC_Private_Functions
1759 * @{
1760 */
1761
1762 /**
1763 * @brief DMA conversion complete callback.
1764 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1765 * the configuration information for the specified DMA module.
1766 * @retval None
1767 */
DAC_DMAConvCpltCh1(DMA_HandleTypeDef * hdma)1768 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
1769 {
1770 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1771
1772 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1773 hdac->ConvCpltCallbackCh1(hdac);
1774 #else
1775 HAL_DAC_ConvCpltCallbackCh1(hdac);
1776 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1777
1778 hdac->State = HAL_DAC_STATE_READY;
1779 }
1780
1781 /**
1782 * @brief DMA half transfer complete callback.
1783 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1784 * the configuration information for the specified DMA module.
1785 * @retval None
1786 */
DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef * hdma)1787 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
1788 {
1789 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1790 /* Conversion complete callback */
1791 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1792 hdac->ConvHalfCpltCallbackCh1(hdac);
1793 #else
1794 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
1795 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1796 }
1797
1798 /**
1799 * @brief DMA error callback
1800 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1801 * the configuration information for the specified DMA module.
1802 * @retval None
1803 */
DAC_DMAErrorCh1(DMA_HandleTypeDef * hdma)1804 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
1805 {
1806 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1807
1808 /* Set DAC error code to DMA error */
1809 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1810
1811 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1812 hdac->ErrorCallbackCh1(hdac);
1813 #else
1814 HAL_DAC_ErrorCallbackCh1(hdac);
1815 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1816
1817 hdac->State = HAL_DAC_STATE_READY;
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 /**
1825 * @}
1826 */
1827
1828 #endif /* DAC1 */
1829
1830 #endif /* HAL_DAC_MODULE_ENABLED */
1831 /**
1832 * @}
1833 */
1834
