1 /**
2 ******************************************************************************
3 * @file stm32h5xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32H5xx_LL_TIM_H
21 #define __STM32H5xx_LL_TIM_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h5xx.h"
29
30 /** @addtogroup STM32H5xx_LL_Driver
31 * @{
32 */
33
34 #if defined (TIM1) \
35 || defined (TIM2) \
36 || defined (TIM3) \
37 || defined (TIM4) \
38 || defined (TIM5) \
39 || defined (TIM6) \
40 || defined (TIM7) \
41 || defined (TIM8) \
42 || defined (TIM12) \
43 || defined (TIM13) \
44 || defined (TIM14) \
45 || defined (TIM15) \
46 || defined (TIM16) \
47 || defined (TIM17)
48
49 /** @defgroup TIM_LL TIM
50 * @{
51 */
52
53 /* Private types -------------------------------------------------------------*/
54 /* Private variables ---------------------------------------------------------*/
55 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
56 * @{
57 */
58 static const uint8_t OFFSET_TAB_CCMRx[] =
59 {
60 0x00U, /* 0: TIMx_CH1 */
61 0x00U, /* 1: TIMx_CH1N */
62 0x00U, /* 2: TIMx_CH2 */
63 0x00U, /* 3: TIMx_CH2N */
64 0x04U, /* 4: TIMx_CH3 */
65 0x04U, /* 5: TIMx_CH3N */
66 0x04U, /* 6: TIMx_CH4 */
67 0x04U, /* 7: TIMx_CH4N */
68 0x38U, /* 8: TIMx_CH5 */
69 0x38U /* 9: TIMx_CH6 */
70
71 };
72
73 static const uint8_t SHIFT_TAB_OCxx[] =
74 {
75 0U, /* 0: OC1M, OC1FE, OC1PE */
76 0U, /* 1: - NA */
77 8U, /* 2: OC2M, OC2FE, OC2PE */
78 0U, /* 3: - NA */
79 0U, /* 4: OC3M, OC3FE, OC3PE */
80 0U, /* 5: - NA */
81 8U, /* 6: OC4M, OC4FE, OC4PE */
82 0U, /* 7: - NA */
83 0U, /* 8: OC5M, OC5FE, OC5PE */
84 8U /* 9: OC6M, OC6FE, OC6PE */
85 };
86
87 static const uint8_t SHIFT_TAB_ICxx[] =
88 {
89 0U, /* 0: CC1S, IC1PSC, IC1F */
90 0U, /* 1: - NA */
91 8U, /* 2: CC2S, IC2PSC, IC2F */
92 0U, /* 3: - NA */
93 0U, /* 4: CC3S, IC3PSC, IC3F */
94 0U, /* 5: - NA */
95 8U, /* 6: CC4S, IC4PSC, IC4F */
96 0U, /* 7: - NA */
97 0U, /* 8: - NA */
98 0U /* 9: - NA */
99 };
100
101 static const uint8_t SHIFT_TAB_CCxP[] =
102 {
103 0U, /* 0: CC1P */
104 2U, /* 1: CC1NP */
105 4U, /* 2: CC2P */
106 6U, /* 3: CC2NP */
107 8U, /* 4: CC3P */
108 10U, /* 5: CC3NP */
109 12U, /* 6: CC4P */
110 14U, /* 7: CC4NP */
111 16U, /* 8: CC5P */
112 20U /* 9: CC6P */
113 };
114
115 static const uint8_t SHIFT_TAB_OISx[] =
116 {
117 0U, /* 0: OIS1 */
118 1U, /* 1: OIS1N */
119 2U, /* 2: OIS2 */
120 3U, /* 3: OIS2N */
121 4U, /* 4: OIS3 */
122 5U, /* 5: OIS3N */
123 6U, /* 6: OIS4 */
124 7U, /* 7: OIS4N */
125 8U, /* 8: OIS5 */
126 10U /* 9: OIS6 */
127 };
128 /**
129 * @}
130 */
131
132 /* Private constants ---------------------------------------------------------*/
133 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
134 * @{
135 */
136
137 /* Defines used for the bit position in the register and perform offsets */
138 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
139
140 /* Generic bit definitions for TIMx_AF1 register */
141 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
142 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
143
144
145 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
146 #define DT_DELAY_1 ((uint8_t)0x7F)
147 #define DT_DELAY_2 ((uint8_t)0x3F)
148 #define DT_DELAY_3 ((uint8_t)0x1F)
149 #define DT_DELAY_4 ((uint8_t)0x1F)
150
151 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
152 #define DT_RANGE_1 ((uint8_t)0x00)
153 #define DT_RANGE_2 ((uint8_t)0x80)
154 #define DT_RANGE_3 ((uint8_t)0xC0)
155 #define DT_RANGE_4 ((uint8_t)0xE0)
156
157 /** Legacy definitions for compatibility purpose
158 @cond 0
159 */
160 /**
161 @endcond
162 */
163
164 /**
165 * @}
166 */
167
168 /* Private macros ------------------------------------------------------------*/
169 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
170 * @{
171 */
172 /** @brief Convert channel id into channel index.
173 * @param __CHANNEL__ This parameter can be one of the following values:
174 * @arg @ref LL_TIM_CHANNEL_CH1
175 * @arg @ref LL_TIM_CHANNEL_CH1N
176 * @arg @ref LL_TIM_CHANNEL_CH2
177 * @arg @ref LL_TIM_CHANNEL_CH2N
178 * @arg @ref LL_TIM_CHANNEL_CH3
179 * @arg @ref LL_TIM_CHANNEL_CH3N
180 * @arg @ref LL_TIM_CHANNEL_CH4
181 * @arg @ref LL_TIM_CHANNEL_CH4N
182 * @arg @ref LL_TIM_CHANNEL_CH5
183 * @arg @ref LL_TIM_CHANNEL_CH6
184 * @retval none
185 */
186 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
187 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
188 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
189 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
190 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
191 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
192 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
193 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
194 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
195 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
196
197 /** @brief Calculate the deadtime sampling period(in ps).
198 * @param __TIMCLK__ timer input clock frequency (in Hz).
199 * @param __CKD__ This parameter can be one of the following values:
200 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
201 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
202 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
203 * @retval none
204 */
205 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
206 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
207 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
208 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
209 /**
210 * @}
211 */
212
213
214 /* Exported types ------------------------------------------------------------*/
215 #if defined(USE_FULL_LL_DRIVER)
216 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
217 * @{
218 */
219
220 /**
221 * @brief TIM Time Base configuration structure definition.
222 */
223 typedef struct
224 {
225 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
226 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
227
228 This feature can be modified afterwards using unitary function
229 @ref LL_TIM_SetPrescaler().*/
230
231 uint32_t CounterMode; /*!< Specifies the counter mode.
232 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
233
234 This feature can be modified afterwards using unitary function
235 @ref LL_TIM_SetCounterMode().*/
236
237 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
238 Auto-Reload Register at the next update event.
239 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
240 Some timer instances may support 32 bits counters. In that case this parameter must
241 be a number between 0x0000 and 0xFFFFFFFF.
242
243 This feature can be modified afterwards using unitary function
244 @ref LL_TIM_SetAutoReload().*/
245
246 uint32_t ClockDivision; /*!< Specifies the clock division.
247 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
248
249 This feature can be modified afterwards using unitary function
250 @ref LL_TIM_SetClockDivision().*/
251
252 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
253 reaches zero, an update event is generated and counting restarts
254 from the RCR value (N).
255 This means in PWM mode that (N+1) corresponds to:
256 - the number of PWM periods in edge-aligned mode
257 - the number of half PWM period in center-aligned mode
258 GP timers: this parameter must be a number between Min_Data = 0x00 and
259 Max_Data = 0xFF.
260 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
261 Max_Data = 0xFFFF.
262
263 This feature can be modified afterwards using unitary function
264 @ref LL_TIM_SetRepetitionCounter().*/
265 } LL_TIM_InitTypeDef;
266
267 /**
268 * @brief TIM Output Compare configuration structure definition.
269 */
270 typedef struct
271 {
272 uint32_t OCMode; /*!< Specifies the output mode.
273 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
274
275 This feature can be modified afterwards using unitary function
276 @ref LL_TIM_OC_SetMode().*/
277
278 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
279 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
280
281 This feature can be modified afterwards using unitary functions
282 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
283
284 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
285 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
286
287 This feature can be modified afterwards using unitary functions
288 @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
289
290 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
291 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
292
293 This feature can be modified afterwards using unitary function
294 LL_TIM_OC_SetCompareCHx (x=1..6).*/
295
296 uint32_t OCPolarity; /*!< Specifies the output polarity.
297 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
298
299 This feature can be modified afterwards using unitary function
300 @ref LL_TIM_OC_SetPolarity().*/
301
302 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
303 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
304
305 This feature can be modified afterwards using unitary function
306 @ref LL_TIM_OC_SetPolarity().*/
307
308
309 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
310 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
311
312 This feature can be modified afterwards using unitary function
313 @ref LL_TIM_OC_SetIdleState().*/
314
315 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
316 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
317
318 This feature can be modified afterwards using unitary function
319 @ref LL_TIM_OC_SetIdleState().*/
320 } LL_TIM_OC_InitTypeDef;
321
322 /**
323 * @brief TIM Input Capture configuration structure definition.
324 */
325
326 typedef struct
327 {
328
329 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
330 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
331
332 This feature can be modified afterwards using unitary function
333 @ref LL_TIM_IC_SetPolarity().*/
334
335 uint32_t ICActiveInput; /*!< Specifies the input.
336 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
337
338 This feature can be modified afterwards using unitary function
339 @ref LL_TIM_IC_SetActiveInput().*/
340
341 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
342 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
343
344 This feature can be modified afterwards using unitary function
345 @ref LL_TIM_IC_SetPrescaler().*/
346
347 uint32_t ICFilter; /*!< Specifies the input capture filter.
348 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
349
350 This feature can be modified afterwards using unitary function
351 @ref LL_TIM_IC_SetFilter().*/
352 } LL_TIM_IC_InitTypeDef;
353
354
355 /**
356 * @brief TIM Encoder interface configuration structure definition.
357 */
358 typedef struct
359 {
360 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
361 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
362
363 This feature can be modified afterwards using unitary function
364 @ref LL_TIM_SetEncoderMode().*/
365
366 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
367 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
368
369 This feature can be modified afterwards using unitary function
370 @ref LL_TIM_IC_SetPolarity().*/
371
372 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
373 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
374
375 This feature can be modified afterwards using unitary function
376 @ref LL_TIM_IC_SetActiveInput().*/
377
378 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
379 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
380
381 This feature can be modified afterwards using unitary function
382 @ref LL_TIM_IC_SetPrescaler().*/
383
384 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
385 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
386
387 This feature can be modified afterwards using unitary function
388 @ref LL_TIM_IC_SetFilter().*/
389
390 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
391 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
392
393 This feature can be modified afterwards using unitary function
394 @ref LL_TIM_IC_SetPolarity().*/
395
396 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
397 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
398
399 This feature can be modified afterwards using unitary function
400 @ref LL_TIM_IC_SetActiveInput().*/
401
402 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
403 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
404
405 This feature can be modified afterwards using unitary function
406 @ref LL_TIM_IC_SetPrescaler().*/
407
408 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
409 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
410
411 This feature can be modified afterwards using unitary function
412 @ref LL_TIM_IC_SetFilter().*/
413
414 } LL_TIM_ENCODER_InitTypeDef;
415
416 /**
417 * @brief TIM Hall sensor interface configuration structure definition.
418 */
419 typedef struct
420 {
421
422 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
423 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
424
425 This feature can be modified afterwards using unitary function
426 @ref LL_TIM_IC_SetPolarity().*/
427
428 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
429 Prescaler must be set to get a maximum counter period longer than the
430 time interval between 2 consecutive changes on the Hall inputs.
431 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
432
433 This feature can be modified afterwards using unitary function
434 @ref LL_TIM_IC_SetPrescaler().*/
435
436 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
437 This parameter can be a value of
438 @ref TIM_LL_EC_IC_FILTER.
439
440 This feature can be modified afterwards using unitary function
441 @ref LL_TIM_IC_SetFilter().*/
442
443 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
444 A positive pulse (TRGO event) is generated with a programmable delay every time
445 a change occurs on the Hall inputs.
446 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
447
448 This feature can be modified afterwards using unitary function
449 @ref LL_TIM_OC_SetCompareCH2().*/
450 } LL_TIM_HALLSENSOR_InitTypeDef;
451
452 /**
453 * @brief BDTR (Break and Dead Time) structure definition
454 */
455 typedef struct
456 {
457 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
458 This parameter can be a value of @ref TIM_LL_EC_OSSR
459
460 This feature can be modified afterwards using unitary function
461 @ref LL_TIM_SetOffStates()
462
463 @note This bit-field cannot be modified as long as LOCK level 2 has been
464 programmed. */
465
466 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
467 This parameter can be a value of @ref TIM_LL_EC_OSSI
468
469 This feature can be modified afterwards using unitary function
470 @ref LL_TIM_SetOffStates()
471
472 @note This bit-field cannot be modified as long as LOCK level 2 has been
473 programmed. */
474
475 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
476 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
477
478 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
479 register has been written, their content is frozen until the next reset.*/
480
481 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
482 switching-on of the outputs.
483 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
484
485 This feature can be modified afterwards using unitary function
486 @ref LL_TIM_OC_SetDeadTime()
487
488 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
489 programmed. */
490
491 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
492 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
493
494 This feature can be modified afterwards using unitary functions
495 @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
496
497 @note This bit-field can not be modified as long as LOCK level 1 has been
498 programmed. */
499
500 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
501 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
502
503 This feature can be modified afterwards using unitary function
504 @ref LL_TIM_ConfigBRK()
505
506 @note This bit-field can not be modified as long as LOCK level 1 has been
507 programmed. */
508
509 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
510 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
511
512 This feature can be modified afterwards using unitary function
513 @ref LL_TIM_ConfigBRK()
514
515 @note This bit-field can not be modified as long as LOCK level 1 has been
516 programmed. */
517
518 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
519 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
520
521 This feature can be modified afterwards using unitary functions
522 @ref LL_TIM_ConfigBRK()
523
524 @note Bidirectional break input is only supported by advanced timers instances.
525
526 @note This bit-field can not be modified as long as LOCK level 1 has been
527 programmed. */
528
529 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
530 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
531
532 This feature can be modified afterwards using unitary functions
533 @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
534
535 @note This bit-field can not be modified as long as LOCK level 1 has been
536 programmed. */
537
538 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
539 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
540
541 This feature can be modified afterwards using unitary function
542 @ref LL_TIM_ConfigBRK2()
543
544 @note This bit-field can not be modified as long as LOCK level 1 has been
545 programmed. */
546
547 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
548 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
549
550 This feature can be modified afterwards using unitary function
551 @ref LL_TIM_ConfigBRK2()
552
553 @note This bit-field can not be modified as long as LOCK level 1 has been
554 programmed. */
555
556 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
557 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
558
559 This feature can be modified afterwards using unitary functions
560 @ref LL_TIM_ConfigBRK2()
561
562 @note Bidirectional break input is only supported by advanced timers instances.
563
564 @note This bit-field can not be modified as long as LOCK level 1 has been
565 programmed. */
566
567 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
568 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
569
570 This feature can be modified afterwards using unitary functions
571 @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
572
573 @note This bit-field can not be modified as long as LOCK level 1 has been
574 programmed. */
575 } LL_TIM_BDTR_InitTypeDef;
576
577 /**
578 * @}
579 */
580 #endif /* USE_FULL_LL_DRIVER */
581
582 /* Exported constants --------------------------------------------------------*/
583 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
584 * @{
585 */
586
587 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
588 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
589 * @{
590 */
591 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
592 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
593 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
594 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
595 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
596 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
597 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
598 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
599 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
600 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
601 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
602 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
603 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
604 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
605 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
606 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
607 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
608 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
609 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
610 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
611 /**
612 * @}
613 */
614
615 #if defined(USE_FULL_LL_DRIVER)
616 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
617 * @{
618 */
619 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
620 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
621 /**
622 * @}
623 */
624
625 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
626 * @{
627 */
628 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
629 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
635 * @{
636 */
637 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
638 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
639 /**
640 * @}
641 */
642 #endif /* USE_FULL_LL_DRIVER */
643
644 /** @defgroup TIM_LL_EC_IT IT Defines
645 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
646 * @{
647 */
648 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
649 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
650 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
651 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
652 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
653 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
654 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
655 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
656 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
657 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
658 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
659 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
665 * @{
666 */
667 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
668 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
669 /**
670 * @}
671 */
672
673 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
674 * @{
675 */
676 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
677 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
678 /**
679 * @}
680 */
681
682 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
683 * @{
684 */
685 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
686 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
687 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
688 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
689 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
690 /**
691 * @}
692 */
693
694 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
695 * @{
696 */
697 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
698 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
699 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
705 * @{
706 */
707 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
708 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
714 * @{
715 */
716 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
717 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
718 /**
719 * @}
720 */
721
722 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
723 * @{
724 */
725 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
726 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
727 /**
728 * @}
729 */
730
731 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
732 * @{
733 */
734 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
735 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
736 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
737 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
738 /**
739 * @}
740 */
741
742 /** @defgroup TIM_LL_EC_CHANNEL Channel
743 * @{
744 */
745 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
746 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
747 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
748 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
749 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
750 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
751 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
752 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
753 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
754 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
755 /**
756 * @}
757 */
758
759 #if defined(USE_FULL_LL_DRIVER)
760 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
761 * @{
762 */
763 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
764 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
765 /**
766 * @}
767 */
768 #endif /* USE_FULL_LL_DRIVER */
769
770 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
771 * @{
772 */
773 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
774 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
775 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
776 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
777 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
778 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
779 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
780 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
781 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
782 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
783 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
784 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
785 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
786 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
787 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
788 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
789 /**
790 * @}
791 */
792
793 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
794 * @{
795 */
796 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
797 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
803 * @{
804 */
805 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
806 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
807 /**
808 * @}
809 */
810
811 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
812 * @{
813 */
814 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
815 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
816 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
817 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
818 /**
819 * @}
820 */
821
822 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
823 * @{
824 */
825 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
826 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
827 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
828 /**
829 * @}
830 */
831
832 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
833 * @{
834 */
835 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
836 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
837 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
838 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
839 /**
840 * @}
841 */
842
843 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
844 * @{
845 */
846 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
847 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
848 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
849 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
850 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
851 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
852 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
853 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
854 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
855 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
856 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
857 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
858 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
859 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
860 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
861 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
862 /**
863 * @}
864 */
865
866 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
867 * @{
868 */
869 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
870 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
871 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
872 /**
873 * @}
874 */
875
876 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
877 * @{
878 */
879 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
880 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
881 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
882 /**
883 * @}
884 */
885
886 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
887 * @{
888 */
889 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
890 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
891 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
892 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
893 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
894 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
895 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
896 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
897 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
898 /**
899 * @}
900 */
901
902 /** @defgroup TIM_LL_EC_TRGO Trigger Output
903 * @{
904 */
905 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
906 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
907 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
908 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
909 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
910 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
911 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
912 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
913 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
914 /**
915 * @}
916 */
917
918 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
919 * @{
920 */
921 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
922 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
923 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
924 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
925 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
926 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
927 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
928 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
929 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
930 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
931 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
932 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
933 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
934 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
935 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
936 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
937 /**
938 * @}
939 */
940
941 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
942 * @{
943 */
944 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
945 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
946 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
947 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
948 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
949 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
950 the counter are controlled. */
951 /**
952 * @}
953 */
954
955 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
956 * @{
957 */
958 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
959 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
960 /**
961 * @}
962 */
963
964 /** @defgroup TIM_LL_EC_TS Trigger Selection
965 * @{
966 */
967 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
968 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
969 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
970 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
971 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
972 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
973 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
974 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
975 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
976 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
977 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
978 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
979 #define LL_TIM_TS_ITR12 (TIM_SMCR_TS_4) /*!< Internal Trigger 12 (ITR12) is used as trigger input */
980 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
981 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
982 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
983 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
984 /**
985 * @}
986 */
987
988 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
989 * @{
990 */
991 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
992 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
993 /**
994 * @}
995 */
996
997 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
998 * @{
999 */
1000 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
1001 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
1002 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
1003 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
1009 * @{
1010 */
1011 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
1012 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
1013 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
1014 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
1015 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
1016 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
1017 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
1018 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
1019 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
1020 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
1021 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
1022 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
1023 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
1024 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
1025 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
1026 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
1027 /**
1028 * @}
1029 */
1030
1031 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1032 * @{
1033 */
1034 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1035 #if defined(COMP1)
1036 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1037 #endif /* COMP1*/
1038 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 1 */
1039 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC1 analog watchdog 2 */
1040 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 3 */
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1046 * @{
1047 */
1048 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1049 #if defined(COMP1)
1050 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1051 #endif /* COMP1*/
1052 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to LSE */
1053 #if defined(SAI1)
1054 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to SAI1_FSA */
1055 #define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_2) /*!< ETR input is connected to SAI1_FSB */
1056 #endif /* SAI1 */
1057 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to TIM3 ETR */
1058 #if defined(TIM4)
1059 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_3) /*!< ETR input is connected to TIM4 ETR */
1060 #endif /* TIM4 */
1061 #if defined(TIM5)
1062 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_0 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to TIM5 ETR */
1063 #endif /* TIM5 */
1064 #if defined(ETH_NS)
1065 #define LL_TIM_TIM2_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
1066 #endif /* ETH_NS */
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1072 * @{
1073 */
1074 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1075 #if defined(COMP1)
1076 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1077 #endif /* COMP1*/
1078 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1079 #if defined(TIM4)
1080 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1081 #endif /* TIM4 */
1082 #if defined(TIM5)
1083 #define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1084 #endif /* TIM5 */
1085 #if defined(ETH_NS)
1086 #define LL_TIM_TIM3_ETRSOURCE_ETH_PPS (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
1087 #endif /* ETH_NS */
1088 /**
1089 * @}
1090 */
1091
1092 #if defined(TIM4)
1093 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1094 * @{
1095 */
1096 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1097 #define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1098 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1099 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1100 /**
1101 * @}
1102 */
1103 #endif /* TIM4 */
1104
1105 #if defined(TIM5)
1106 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1107 * @{
1108 */
1109 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1110 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to SAI2_FSA */
1111 #define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to SAI2_FSB */
1112 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1113 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1114 #define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM4 ETR */
1115 /**
1116 * @}
1117 */
1118 #endif /* TIM5 */
1119
1120 #if defined(TIM8)
1121 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1122 * @{
1123 */
1124 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1125 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1126 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 TIM1_AF1_ETRSEL_2 /*!< ADC4 analog watchdog 2 */
1127 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1128 /**
1129 * @}
1130 */
1131 #endif /* TIM8 */
1132
1133 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1134 * @{
1135 */
1136 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1137 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1143 * @{
1144 */
1145 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1146 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1147 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1148 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1149 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1150 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1151 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1152 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1153 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1154 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1155 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1156 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1157 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1158 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1159 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1160 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1166 * @{
1167 */
1168 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1169 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1175 * @{
1176 */
1177 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1178 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1179 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1180 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1181 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1182 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1183 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1184 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1185 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1186 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1187 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1188 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1189 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1190 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1191 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1192 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1193 /**
1194 * @}
1195 */
1196
1197 /** @defgroup TIM_LL_EC_OSSI OSSI
1198 * @{
1199 */
1200 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1201 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup TIM_LL_EC_OSSR OSSR
1207 * @{
1208 */
1209 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1210 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1216 * @{
1217 */
1218 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1219 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1220 /**
1221 * @}
1222 */
1223
1224 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1225 * @{
1226 */
1227 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1228 #if defined(COMP1)
1229 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1230 #endif /* COMP1 */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1236 * @{
1237 */
1238 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1239 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1240 /**
1241 * @}
1242 */
1243
1244 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1245 * @{
1246 */
1247 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1248 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1249 /**
1250 * @}
1251 */
1252
1253 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1254 * @{
1255 */
1256 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1257 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1258 /**
1259 * @}
1260 */
1261
1262 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1263 * @{
1264 */
1265 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1266 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1267 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1268 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1269 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1270 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1271 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1272 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1273 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1274 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1275 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1276 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1277 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1278 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1279 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1280 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1281 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1282 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1283 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1284 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1285 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1286 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1287 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1288 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1289 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1290 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1296 * @{
1297 */
1298 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1299 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1300 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1301 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1302 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1303 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1304 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1305 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1306 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1307 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1308 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1309 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1310 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1311 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1312 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1313 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1314 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1315 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1316 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1317 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1318 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1319 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1320 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1321 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1322 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1323 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1324 /**
1325 * @}
1326 */
1327
1328 /** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
1329 * @{
1330 */
1331 #define LL_TIM_DMA_UPDATE TIM_DCR_DBSS_0 /*!< Transfer source is update event */
1332 #define LL_TIM_DMA_CC1 TIM_DCR_DBSS_1 /*!< Transfer source is CC1 event */
1333 #define LL_TIM_DMA_CC2 (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is CC2 event */
1334 #define LL_TIM_DMA_CC3 TIM_DCR_DBSS_2 /*!< Transfer source is CC3 event */
1335 #define LL_TIM_DMA_CC4 (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0) /*!< Transfer source is CC4 event */
1336 #define LL_TIM_DMA_COM (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1) /*!< Transfer source is COM event */
1337 #define LL_TIM_DMA_TRIGGER (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0) /*!< Transfer source is trigger event */
1338 /**
1339 * @}
1340 */
1341 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap
1342 * @{
1343 */
1344 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000UL
1345 #if defined(COMP1)
1346 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0
1347 #endif /* COMP1 */
1348 /**
1349 * @}
1350 */
1351
1352 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 External Input Ch1 Remap
1353 * @{
1354 */
1355 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1356 #if defined(STM32H503xx)
1357 #define LL_TIM_TIM2_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to LSI */
1358 #define LL_TIM_TIM2_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to LSE */
1359 #define LL_TIM_TIM2_TI1_RMP_RTC (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to RTC */
1360 #define LL_TIM_TIM2_TI1_RMP_TIM3_TI1 TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to TIM3 TI1 */
1361 #endif /* STM32H503xx */
1362 #if defined(ETH_NS)
1363 #define LL_TIM_TIM2_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH_ PPS */
1364 #endif /* ETH_NS */
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 External Input Ch2 Remap
1370 * @{
1371 */
1372 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */
1373 #if defined(STM32H503xx)
1374 #define LL_TIM_TIM2_TI2_RMP_HSI_1024 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to HSI_1024 */
1375 #define LL_TIM_TIM2_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to CSI_128 */
1376 #define LL_TIM_TIM2_TI2_RMP_MCO2 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM2_TI2 is connected to MCO2 */
1377 #define LL_TIM_TIM2_TI2_RMP_MCO1 TIM_TISEL_TI2SEL_2 /*!< TIM2_TI2 is connected to MCO1 */
1378 #endif /* STM32H503xx */
1379 /**
1380 * @}
1381 */
1382
1383 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap
1384 * @{
1385 */
1386 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */
1387 #if defined(COMP1)
1388 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI2 is connected to COMP1 */
1389 #endif /* COMP1 */
1390 /**
1391 * @}
1392 */
1393
1394 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap
1395 * @{
1396 */
1397 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */
1398 #if defined(STM32H503xx)
1399 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 */
1400 #define LL_TIM_TIM3_TI1_RMP_MCO1 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to MCO1 */
1401 #define LL_TIM_TIM3_TI1_RMP_TIM2_TI1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2_TI1 is connected to TIM2 TI1 */
1402 #define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_2 /*!< TIM2_TI1 is connected to HSE 1MHZ */
1403 #endif /* STM32H503xx */
1404 #if defined(ETH_NS)
1405 #define LL_TIM_TIM3_TI1_RMP_ETH_PPS TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to ETH PPS */
1406 #endif /* ETH_NS */
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 External Input Ch2 Remap
1412 * @{
1413 */
1414 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */
1415 #if defined(STM32H503xx)
1416 #define LL_TIM_TIM3_TI2_RMP_CSI_128 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to CSI 128 */
1417 #define LL_TIM_TIM3_TI2_RMP_MCO2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to MCO2 */
1418 #define LL_TIM_TIM3_TI2_RMP_HSI_1024 (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0) /*!< TIM3_TI2 is connected to HSI 1024 */
1419 #endif /* STM32H503xx */
1420 /**
1421 * @}
1422 */
1423
1424 #if defined(TIM12)
1425 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP TIM12 External Input Ch1 Remap
1426 * @{
1427 */
1428 #define LL_TIM_TIM12_TI1_RMP_GPIO 0x00000000UL /*!< TIM12_TI1 is connected to GPIO */
1429 #define LL_TIM_TIM12_TI1_RMP_HSI_1024 TIM_TISEL_TI1SEL_2 /*!< TIM12_TI1 is connected to HSI 1024 */
1430 #define LL_TIM_TIM12_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM12_TI1 is connected to CSI 128 */
1431 /**
1432 * @}
1433 */
1434 #endif /* TIM12 */
1435
1436 #if defined(TIM15)
1437 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap
1438 * @{
1439 */
1440 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1441 #define LL_TIM_TIM15_TI1_RMP_TIM2 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 */
1442 #define LL_TIM_TIM15_TI1_RMP_TIM3 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 */
1443 #define LL_TIM_TIM15_TI1_RMP_TIM4 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to TIM4 */
1444 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_2 /*!< TIM15_TI1 is connected to LSE */
1445 #define LL_TIM_TIM15_TI1_RMP_CSI_128 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to CSI 128*/
1446 #define LL_TIM_TIM15_TI1_RMP_MCO2 (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to MCO2 */
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 External Input Ch2 Remap
1452 * @{
1453 */
1454 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */
1455 #define LL_TIM_TIM15_TI2_RMP_TIM2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to TIM2 */
1456 #define LL_TIM_TIM15_TI2_RMP_TIM3 TIM_TISEL_TI2SEL_1 /*!< TIM15_TI2 is connected to TIM3 */
1457 #define LL_TIM_TIM15_TI2_RMP_TIM4 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM4 */
1458 /**
1459 * @}
1460 */
1461 #endif /* TIM15 */
1462
1463 #if defined(TIM16)
1464 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap
1465 * @{
1466 */
1467 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */
1468 #define LL_TIM_TIM16_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16_TI1 is connected to LSI */
1469 #define LL_TIM_TIM16_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to LSE */
1470 #define LL_TIM_TIM16_TI1_RMP_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to RTC */
1471 /**
1472 * @}
1473 */
1474 #endif /* TIM16 */
1475
1476 #if defined(TIM17)
1477 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 External Input Ch1 Remap
1478 * @{
1479 */
1480 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */
1481 #define LL_TIM_TIM17_TI1_RMP_HSE_1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to HSE 1MHZ */
1482 #define LL_TIM_TIM17_TI1_RMP_MCO1 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MCO1 */
1483 /**
1484 * @}
1485 */
1486 #endif /* TIM17 */
1487
1488 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1489 * @{
1490 */
1491 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
1492 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
1493 /**
1494 * @}
1495 */
1496
1497 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1498 * @{
1499 */
1500 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1501 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1502 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1503 /**
1504 * @}
1505 */
1506
1507 /** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
1508 * @{
1509 */
1510 #define LL_TIM_INDEX_BLANK_ALWAYS 0x00000000U /*!< Index always active */
1511 #define LL_TIM_INDEX_BLANK_TI3 TIM_ECR_IBLK_0 /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
1512 #define LL_TIM_INDEX_BLANK_TI4 TIM_ECR_IBLK_1 /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
1513 /**
1514 * @}
1515 */
1516
1517 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1518 * @{
1519 */
1520 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1521 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1522 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1523 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1524 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1525 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1526 /**
1527 * @}
1528 */
1529
1530 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1531 * @{
1532 */
1533 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1534 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1535 /**
1536 * @}
1537 */
1538 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1539 * @{
1540 */
1541 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1542 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1543 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1544 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1545 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1546 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1547 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1548 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1549 /**
1550 * @}
1551 */
1552
1553 /** Legacy definitions for compatibility purpose
1554 @cond 0
1555 */
1556 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1557 /**
1558 @endcond
1559 */
1560
1561 /**
1562 * @}
1563 */
1564
1565 /* Exported macro ------------------------------------------------------------*/
1566 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1567 * @{
1568 */
1569
1570 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1571 * @{
1572 */
1573 /**
1574 * @brief Write a value in TIM register.
1575 * @param __INSTANCE__ TIM Instance
1576 * @param __REG__ Register to be written
1577 * @param __VALUE__ Value to be written in the register
1578 * @retval None
1579 */
1580 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1581
1582 /**
1583 * @brief Read a value in TIM register.
1584 * @param __INSTANCE__ TIM Instance
1585 * @param __REG__ Register to be read
1586 * @retval Register value
1587 */
1588 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1589 /**
1590 * @}
1591 */
1592
1593 /**
1594 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1595 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1596 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1597 * to TIMx_CNT register bit 31)
1598 * @param __CNT__ Counter value
1599 * @retval UIF status bit
1600 */
1601 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1602 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1603
1604 /**
1605 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1606 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1607 * @param __TIMCLK__ timer input clock frequency (in Hz)
1608 * @param __CKD__ This parameter can be one of the following values:
1609 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1610 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1611 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1612 * @param __DT__ deadtime duration (in ns)
1613 * @retval DTG[0:7]
1614 */
1615 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1616 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1617 (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1618 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1619 (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1620 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1621 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1622 (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1623 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1624 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
1625 (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
1626 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1627 0U)
1628
1629 /**
1630 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1631 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1632 * @param __TIMCLK__ timer input clock frequency (in Hz)
1633 * @param __CNTCLK__ counter clock frequency (in Hz)
1634 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1635 */
1636 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1637 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
1638
1639 /**
1640 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1641 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1642 * @param __TIMCLK__ timer input clock frequency (in Hz)
1643 * @param __PSC__ prescaler
1644 * @param __FREQ__ output signal frequency (in Hz)
1645 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1646 */
1647 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1648 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1649
1650 /**
1651 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1652 * output signal frequency.
1653 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1654 * @param __TIMCLK__ timer input clock frequency (in Hz)
1655 * @param __PSC__ prescaler
1656 * @param __FREQ__ output signal frequency (in Hz)
1657 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1658 */
1659 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1660 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
1661 (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1662
1663 /**
1664 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare
1665 * active/inactive delay.
1666 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1667 * @param __TIMCLK__ timer input clock frequency (in Hz)
1668 * @param __PSC__ prescaler
1669 * @param __DELAY__ timer output compare active/inactive delay (in us)
1670 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1671 */
1672 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1673 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1674 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1675
1676 /**
1677 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
1678 * output compare active/inactive delay.
1679 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1680 * @param __TIMCLK__ timer input clock frequency (in Hz)
1681 * @param __PSC__ prescaler
1682 * @param __DELAY__ timer output compare active/inactive delay (in us)
1683 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1684 */
1685 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1686 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1687 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1688
1689 /**
1690 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
1691 * (when the timer operates in one pulse mode).
1692 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1693 * @param __TIMCLK__ timer input clock frequency (in Hz)
1694 * @param __PSC__ prescaler
1695 * @param __DELAY__ timer output compare active/inactive delay (in us)
1696 * @param __PULSE__ pulse duration (in us)
1697 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1698 */
1699 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1700 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1701 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1702
1703 /**
1704 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
1705 * pulse duration (when the timer operates in one pulse mode).
1706 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1707 * @param __TIMCLK__ timer input clock frequency (in Hz)
1708 * @param __PSC__ prescaler
1709 * @param __DELAY__ timer output compare active/inactive delay (in us)
1710 * @param __PULSE__ pulse duration (in us)
1711 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1712 */
1713 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1714 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1715 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1716
1717 /**
1718 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1719 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1720 * @param __ICPSC__ This parameter can be one of the following values:
1721 * @arg @ref LL_TIM_ICPSC_DIV1
1722 * @arg @ref LL_TIM_ICPSC_DIV2
1723 * @arg @ref LL_TIM_ICPSC_DIV4
1724 * @arg @ref LL_TIM_ICPSC_DIV8
1725 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1726 */
1727 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1728 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1729
1730
1731 /**
1732 * @}
1733 */
1734
1735 /* Exported functions --------------------------------------------------------*/
1736 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1737 * @{
1738 */
1739
1740 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1741 * @{
1742 */
1743 /**
1744 * @brief Enable timer counter.
1745 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1746 * @param TIMx Timer instance
1747 * @retval None
1748 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1749 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1750 {
1751 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1752 }
1753
1754 /**
1755 * @brief Disable timer counter.
1756 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1757 * @param TIMx Timer instance
1758 * @retval None
1759 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1760 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1761 {
1762 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1763 }
1764
1765 /**
1766 * @brief Indicates whether the timer counter is enabled.
1767 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1768 * @param TIMx Timer instance
1769 * @retval State of bit (1 or 0).
1770 */
LL_TIM_IsEnabledCounter(const TIM_TypeDef * TIMx)1771 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
1772 {
1773 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
1774 }
1775
1776 /**
1777 * @brief Enable update event generation.
1778 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1779 * @param TIMx Timer instance
1780 * @retval None
1781 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1782 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1783 {
1784 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1785 }
1786
1787 /**
1788 * @brief Disable update event generation.
1789 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1790 * @param TIMx Timer instance
1791 * @retval None
1792 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1793 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1794 {
1795 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1796 }
1797
1798 /**
1799 * @brief Indicates whether update event generation is enabled.
1800 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1801 * @param TIMx Timer instance
1802 * @retval Inverted state of bit (0 or 1).
1803 */
LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef * TIMx)1804 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
1805 {
1806 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Set update event source
1811 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1812 * generate an update interrupt or DMA request if enabled:
1813 * - Counter overflow/underflow
1814 * - Setting the UG bit
1815 * - Update generation through the slave mode controller
1816 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1817 * overflow/underflow generates an update interrupt or DMA request if enabled.
1818 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1819 * @param TIMx Timer instance
1820 * @param UpdateSource This parameter can be one of the following values:
1821 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1822 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1823 * @retval None
1824 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1825 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1826 {
1827 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1828 }
1829
1830 /**
1831 * @brief Get actual event update source
1832 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1833 * @param TIMx Timer instance
1834 * @retval Returned value can be one of the following values:
1835 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1836 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1837 */
LL_TIM_GetUpdateSource(const TIM_TypeDef * TIMx)1838 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
1839 {
1840 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1841 }
1842
1843 /**
1844 * @brief Set one pulse mode (one shot v.s. repetitive).
1845 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1846 * @param TIMx Timer instance
1847 * @param OnePulseMode This parameter can be one of the following values:
1848 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1849 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1850 * @retval None
1851 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1852 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1853 {
1854 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1855 }
1856
1857 /**
1858 * @brief Get actual one pulse mode.
1859 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1860 * @param TIMx Timer instance
1861 * @retval Returned value can be one of the following values:
1862 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1863 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1864 */
LL_TIM_GetOnePulseMode(const TIM_TypeDef * TIMx)1865 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
1866 {
1867 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1868 }
1869
1870 /**
1871 * @brief Set the timer counter counting mode.
1872 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1873 * check whether or not the counter mode selection feature is supported
1874 * by a timer instance.
1875 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1876 * requires a timer reset to avoid unexpected direction
1877 * due to DIR bit readonly in center aligned mode.
1878 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1879 * CR1 CMS LL_TIM_SetCounterMode
1880 * @param TIMx Timer instance
1881 * @param CounterMode This parameter can be one of the following values:
1882 * @arg @ref LL_TIM_COUNTERMODE_UP
1883 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1884 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1885 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1886 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1887 * @retval None
1888 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1889 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1890 {
1891 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
1892 }
1893
1894 /**
1895 * @brief Get actual counter mode.
1896 * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1897 * check whether or not the counter mode selection feature is supported
1898 * by a timer instance.
1899 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1900 * CR1 CMS LL_TIM_GetCounterMode
1901 * @param TIMx Timer instance
1902 * @retval Returned value can be one of the following values:
1903 * @arg @ref LL_TIM_COUNTERMODE_UP
1904 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1905 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1906 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1907 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1908 */
LL_TIM_GetCounterMode(const TIM_TypeDef * TIMx)1909 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
1910 {
1911 uint32_t counter_mode;
1912
1913 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
1914
1915 if (counter_mode == 0U)
1916 {
1917 counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1918 }
1919
1920 return counter_mode;
1921 }
1922
1923 /**
1924 * @brief Enable auto-reload (ARR) preload.
1925 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1926 * @param TIMx Timer instance
1927 * @retval None
1928 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1929 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1930 {
1931 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1932 }
1933
1934 /**
1935 * @brief Disable auto-reload (ARR) preload.
1936 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1937 * @param TIMx Timer instance
1938 * @retval None
1939 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1940 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1941 {
1942 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1943 }
1944
1945 /**
1946 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1947 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1948 * @param TIMx Timer instance
1949 * @retval State of bit (1 or 0).
1950 */
LL_TIM_IsEnabledARRPreload(const TIM_TypeDef * TIMx)1951 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
1952 {
1953 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
1954 }
1955
1956 /**
1957 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
1958 * (when supported) and the digital filters.
1959 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1960 * whether or not the clock division feature is supported by the timer
1961 * instance.
1962 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1963 * @param TIMx Timer instance
1964 * @param ClockDivision This parameter can be one of the following values:
1965 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1966 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1967 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1968 * @retval None
1969 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1970 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1971 {
1972 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1973 }
1974
1975 /**
1976 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
1977 * generators (when supported) and the digital filters.
1978 * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1979 * whether or not the clock division feature is supported by the timer
1980 * instance.
1981 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1982 * @param TIMx Timer instance
1983 * @retval Returned value can be one of the following values:
1984 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1985 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1986 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1987 */
LL_TIM_GetClockDivision(const TIM_TypeDef * TIMx)1988 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
1989 {
1990 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1991 }
1992
1993 /**
1994 * @brief Set the counter value.
1995 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1996 * whether or not a timer instance supports a 32 bits counter.
1997 * @note If dithering is activated, pay attention to the Counter value interpretation
1998 * @rmtoll CNT CNT LL_TIM_SetCounter
1999 * @param TIMx Timer instance
2000 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2001 * @retval None
2002 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)2003 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2004 {
2005 WRITE_REG(TIMx->CNT, Counter);
2006 }
2007
2008 /**
2009 * @brief Get the counter value.
2010 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2011 * whether or not a timer instance supports a 32 bits counter.
2012 * @note If dithering is activated, pay attention to the Counter value interpretation
2013 * @rmtoll CNT CNT LL_TIM_GetCounter
2014 * @param TIMx Timer instance
2015 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2016 */
LL_TIM_GetCounter(const TIM_TypeDef * TIMx)2017 __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
2018 {
2019 return (uint32_t)(READ_REG(TIMx->CNT));
2020 }
2021
2022 /**
2023 * @brief Get the current direction of the counter
2024 * @rmtoll CR1 DIR LL_TIM_GetDirection
2025 * @param TIMx Timer instance
2026 * @retval Returned value can be one of the following values:
2027 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2028 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2029 */
LL_TIM_GetDirection(const TIM_TypeDef * TIMx)2030 __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
2031 {
2032 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2033 }
2034
2035 /**
2036 * @brief Set the prescaler value.
2037 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2038 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2039 * prescaler ratio is taken into account at the next update event.
2040 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2041 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2042 * @param TIMx Timer instance
2043 * @param Prescaler between Min_Data=0 and Max_Data=65535
2044 * @retval None
2045 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)2046 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2047 {
2048 WRITE_REG(TIMx->PSC, Prescaler);
2049 }
2050
2051 /**
2052 * @brief Get the prescaler value.
2053 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2054 * @param TIMx Timer instance
2055 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2056 */
LL_TIM_GetPrescaler(const TIM_TypeDef * TIMx)2057 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
2058 {
2059 return (uint32_t)(READ_REG(TIMx->PSC));
2060 }
2061
2062 /**
2063 * @brief Set the auto-reload value.
2064 * @note The counter is blocked while the auto-reload value is null.
2065 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2066 * whether or not a timer instance supports a 32 bits counter.
2067 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2068 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
2069 * parameter.
2070 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2071 * @param TIMx Timer instance
2072 * @param AutoReload between Min_Data=0 and Max_Data=65535
2073 * @retval None
2074 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)2075 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2076 {
2077 WRITE_REG(TIMx->ARR, AutoReload);
2078 }
2079
2080 /**
2081 * @brief Get the auto-reload value.
2082 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2083 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2084 * whether or not a timer instance supports a 32 bits counter.
2085 * @note If dithering is activated, pay attention to the returned value interpretation
2086 * @param TIMx Timer instance
2087 * @retval Auto-reload value
2088 */
LL_TIM_GetAutoReload(const TIM_TypeDef * TIMx)2089 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
2090 {
2091 return (uint32_t)(READ_REG(TIMx->ARR));
2092 }
2093
2094 /**
2095 * @brief Set the repetition counter value.
2096 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2097 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2098 * whether or not a timer instance supports a repetition counter.
2099 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2100 * @param TIMx Timer instance
2101 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
2102 * @retval None
2103 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)2104 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2105 {
2106 WRITE_REG(TIMx->RCR, RepetitionCounter);
2107 }
2108
2109 /**
2110 * @brief Get the repetition counter value.
2111 * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2112 * whether or not a timer instance supports a repetition counter.
2113 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2114 * @param TIMx Timer instance
2115 * @retval Repetition counter value
2116 */
LL_TIM_GetRepetitionCounter(const TIM_TypeDef * TIMx)2117 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
2118 {
2119 return (uint32_t)(READ_REG(TIMx->RCR));
2120 }
2121
2122 /**
2123 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2124 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
2125 * in an atomic way.
2126 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2127 * @param TIMx Timer instance
2128 * @retval None
2129 */
LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)2130 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2131 {
2132 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2133 }
2134
2135 /**
2136 * @brief Disable update interrupt flag (UIF) remapping.
2137 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2138 * @param TIMx Timer instance
2139 * @retval None
2140 */
LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)2141 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2142 {
2143 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2144 }
2145
2146 /**
2147 * @brief Indicate whether update interrupt flag (UIF) copy is set.
2148 * @param Counter Counter value
2149 * @retval State of bit (1 or 0).
2150 */
LL_TIM_IsActiveUIFCPY(const uint32_t Counter)2151 __STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
2152 {
2153 return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
2154 }
2155
2156 /**
2157 * @brief Enable dithering.
2158 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2159 * a timer instance provides dithering.
2160 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2161 * @param TIMx Timer instance
2162 * @retval None
2163 */
LL_TIM_EnableDithering(TIM_TypeDef * TIMx)2164 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2165 {
2166 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2167 }
2168
2169 /**
2170 * @brief Disable dithering.
2171 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2172 * a timer instance provides dithering.
2173 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2174 * @param TIMx Timer instance
2175 * @retval None
2176 */
LL_TIM_DisableDithering(TIM_TypeDef * TIMx)2177 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2178 {
2179 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2180 }
2181
2182 /**
2183 * @brief Indicates whether dithering is activated.
2184 * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2185 * a timer instance provides dithering.
2186 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2187 * @param TIMx Timer instance
2188 * @retval State of bit (1 or 0).
2189 */
LL_TIM_IsEnabledDithering(const TIM_TypeDef * TIMx)2190 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
2191 {
2192 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2193 }
2194
2195 /**
2196 * @}
2197 */
2198
2199 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2200 * @{
2201 */
2202 /**
2203 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2204 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2205 * they are updated only when a commutation event (COM) occurs.
2206 * @note Only on channels that have a complementary output.
2207 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2208 * whether or not a timer instance is able to generate a commutation event.
2209 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2210 * @param TIMx Timer instance
2211 * @retval None
2212 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)2213 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2214 {
2215 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2216 }
2217
2218 /**
2219 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2220 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2221 * whether or not a timer instance is able to generate a commutation event.
2222 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2223 * @param TIMx Timer instance
2224 * @retval None
2225 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)2226 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2227 {
2228 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2229 }
2230
2231 /**
2232 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2233 * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2234 * whether or not a timer instance is able to generate a commutation event.
2235 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2236 * @param TIMx Timer instance
2237 * @param CCUpdateSource This parameter can be one of the following values:
2238 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2239 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2240 * @retval None
2241 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)2242 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2243 {
2244 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2245 }
2246
2247 /**
2248 * @brief Set the trigger of the capture/compare DMA request.
2249 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2250 * @param TIMx Timer instance
2251 * @param DMAReqTrigger This parameter can be one of the following values:
2252 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2253 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2254 * @retval None
2255 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)2256 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2257 {
2258 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2259 }
2260
2261 /**
2262 * @brief Get actual trigger of the capture/compare DMA request.
2263 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2264 * @param TIMx Timer instance
2265 * @retval Returned value can be one of the following values:
2266 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2267 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2268 */
LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef * TIMx)2269 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
2270 {
2271 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2272 }
2273
2274 /**
2275 * @brief Set the lock level to freeze the
2276 * configuration of several capture/compare parameters.
2277 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2278 * the lock mechanism is supported by a timer instance.
2279 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2280 * @param TIMx Timer instance
2281 * @param LockLevel This parameter can be one of the following values:
2282 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2283 * @arg @ref LL_TIM_LOCKLEVEL_1
2284 * @arg @ref LL_TIM_LOCKLEVEL_2
2285 * @arg @ref LL_TIM_LOCKLEVEL_3
2286 * @retval None
2287 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)2288 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2289 {
2290 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2291 }
2292
2293 /**
2294 * @brief Enable capture/compare channels.
2295 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2296 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2297 * CCER CC2E LL_TIM_CC_EnableChannel\n
2298 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2299 * CCER CC3E LL_TIM_CC_EnableChannel\n
2300 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2301 * CCER CC4E LL_TIM_CC_EnableChannel\n
2302 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2303 * CCER CC5E LL_TIM_CC_EnableChannel\n
2304 * CCER CC6E LL_TIM_CC_EnableChannel
2305 * @param TIMx Timer instance
2306 * @param Channels This parameter can be a combination of the following values:
2307 * @arg @ref LL_TIM_CHANNEL_CH1
2308 * @arg @ref LL_TIM_CHANNEL_CH1N
2309 * @arg @ref LL_TIM_CHANNEL_CH2
2310 * @arg @ref LL_TIM_CHANNEL_CH2N
2311 * @arg @ref LL_TIM_CHANNEL_CH3
2312 * @arg @ref LL_TIM_CHANNEL_CH3N
2313 * @arg @ref LL_TIM_CHANNEL_CH4
2314 * @arg @ref LL_TIM_CHANNEL_CH4N
2315 * @arg @ref LL_TIM_CHANNEL_CH5
2316 * @arg @ref LL_TIM_CHANNEL_CH6
2317 * @retval None
2318 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2319 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2320 {
2321 SET_BIT(TIMx->CCER, Channels);
2322 }
2323
2324 /**
2325 * @brief Disable capture/compare channels.
2326 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2327 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2328 * CCER CC2E LL_TIM_CC_DisableChannel\n
2329 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2330 * CCER CC3E LL_TIM_CC_DisableChannel\n
2331 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2332 * CCER CC4E LL_TIM_CC_DisableChannel\n
2333 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2334 * CCER CC5E LL_TIM_CC_DisableChannel\n
2335 * CCER CC6E LL_TIM_CC_DisableChannel
2336 * @param TIMx Timer instance
2337 * @param Channels This parameter can be a combination of the following values:
2338 * @arg @ref LL_TIM_CHANNEL_CH1
2339 * @arg @ref LL_TIM_CHANNEL_CH1N
2340 * @arg @ref LL_TIM_CHANNEL_CH2
2341 * @arg @ref LL_TIM_CHANNEL_CH2N
2342 * @arg @ref LL_TIM_CHANNEL_CH3
2343 * @arg @ref LL_TIM_CHANNEL_CH3N
2344 * @arg @ref LL_TIM_CHANNEL_CH4
2345 * @arg @ref LL_TIM_CHANNEL_CH4N
2346 * @arg @ref LL_TIM_CHANNEL_CH5
2347 * @arg @ref LL_TIM_CHANNEL_CH6
2348 * @retval None
2349 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)2350 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2351 {
2352 CLEAR_BIT(TIMx->CCER, Channels);
2353 }
2354
2355 /**
2356 * @brief Indicate whether channel(s) is(are) enabled.
2357 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2358 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2359 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2360 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2361 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2362 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2363 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2364 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2365 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2366 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2367 * @param TIMx Timer instance
2368 * @param Channels This parameter can be a combination of the following values:
2369 * @arg @ref LL_TIM_CHANNEL_CH1
2370 * @arg @ref LL_TIM_CHANNEL_CH1N
2371 * @arg @ref LL_TIM_CHANNEL_CH2
2372 * @arg @ref LL_TIM_CHANNEL_CH2N
2373 * @arg @ref LL_TIM_CHANNEL_CH3
2374 * @arg @ref LL_TIM_CHANNEL_CH3N
2375 * @arg @ref LL_TIM_CHANNEL_CH4
2376 * @arg @ref LL_TIM_CHANNEL_CH4N
2377 * @arg @ref LL_TIM_CHANNEL_CH5
2378 * @arg @ref LL_TIM_CHANNEL_CH6
2379 * @retval State of bit (1 or 0).
2380 */
LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef * TIMx,uint32_t Channels)2381 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
2382 {
2383 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2384 }
2385
2386 /**
2387 * @}
2388 */
2389
2390 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2391 * @{
2392 */
2393 /**
2394 * @brief Configure an output channel.
2395 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2396 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2397 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2398 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2399 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2400 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2401 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2402 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2403 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2404 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2405 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2406 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2407 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2408 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2409 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2410 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2411 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2412 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2413 * @param TIMx Timer instance
2414 * @param Channel This parameter can be one of the following values:
2415 * @arg @ref LL_TIM_CHANNEL_CH1
2416 * @arg @ref LL_TIM_CHANNEL_CH2
2417 * @arg @ref LL_TIM_CHANNEL_CH3
2418 * @arg @ref LL_TIM_CHANNEL_CH4
2419 * @arg @ref LL_TIM_CHANNEL_CH5
2420 * @arg @ref LL_TIM_CHANNEL_CH6
2421 * @param Configuration This parameter must be a combination of all the following values:
2422 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2423 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2424 * @retval None
2425 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2426 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2427 {
2428 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2429 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2430 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2431 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2432 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2433 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2434 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2435 }
2436
2437 /**
2438 * @brief Define the behavior of the output reference signal OCxREF from which
2439 * OCx and OCxN (when relevant) are derived.
2440 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2441 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2442 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2443 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2444 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2445 * CCMR3 OC6M LL_TIM_OC_SetMode
2446 * @param TIMx Timer instance
2447 * @param Channel This parameter can be one of the following values:
2448 * @arg @ref LL_TIM_CHANNEL_CH1
2449 * @arg @ref LL_TIM_CHANNEL_CH2
2450 * @arg @ref LL_TIM_CHANNEL_CH3
2451 * @arg @ref LL_TIM_CHANNEL_CH4
2452 * @arg @ref LL_TIM_CHANNEL_CH5
2453 * @arg @ref LL_TIM_CHANNEL_CH6
2454 * @param Mode This parameter can be one of the following values:
2455 * @arg @ref LL_TIM_OCMODE_FROZEN
2456 * @arg @ref LL_TIM_OCMODE_ACTIVE
2457 * @arg @ref LL_TIM_OCMODE_INACTIVE
2458 * @arg @ref LL_TIM_OCMODE_TOGGLE
2459 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2460 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2461 * @arg @ref LL_TIM_OCMODE_PWM1
2462 * @arg @ref LL_TIM_OCMODE_PWM2
2463 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2464 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2465 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2466 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2467 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2468 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2469 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2470 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2471 * @retval None
2472 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)2473 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2474 {
2475 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2476 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2477 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2478 }
2479
2480 /**
2481 * @brief Get the output compare mode of an output channel.
2482 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2483 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2484 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2485 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2486 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2487 * CCMR3 OC6M LL_TIM_OC_GetMode
2488 * @param TIMx Timer instance
2489 * @param Channel This parameter can be one of the following values:
2490 * @arg @ref LL_TIM_CHANNEL_CH1
2491 * @arg @ref LL_TIM_CHANNEL_CH2
2492 * @arg @ref LL_TIM_CHANNEL_CH3
2493 * @arg @ref LL_TIM_CHANNEL_CH4
2494 * @arg @ref LL_TIM_CHANNEL_CH5
2495 * @arg @ref LL_TIM_CHANNEL_CH6
2496 * @retval Returned value can be one of the following values:
2497 * @arg @ref LL_TIM_OCMODE_FROZEN
2498 * @arg @ref LL_TIM_OCMODE_ACTIVE
2499 * @arg @ref LL_TIM_OCMODE_INACTIVE
2500 * @arg @ref LL_TIM_OCMODE_TOGGLE
2501 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2502 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2503 * @arg @ref LL_TIM_OCMODE_PWM1
2504 * @arg @ref LL_TIM_OCMODE_PWM2
2505 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2506 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2507 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2508 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2509 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2510 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2511 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2512 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2513 */
LL_TIM_OC_GetMode(const TIM_TypeDef * TIMx,uint32_t Channel)2514 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
2515 {
2516 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2517 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2518 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2519 }
2520
2521 /**
2522 * @brief Set the polarity of an output channel.
2523 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2524 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2525 * CCER CC2P LL_TIM_OC_SetPolarity\n
2526 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2527 * CCER CC3P LL_TIM_OC_SetPolarity\n
2528 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2529 * CCER CC4P LL_TIM_OC_SetPolarity\n
2530 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2531 * CCER CC5P LL_TIM_OC_SetPolarity\n
2532 * CCER CC6P LL_TIM_OC_SetPolarity
2533 * @param TIMx Timer instance
2534 * @param Channel This parameter can be one of the following values:
2535 * @arg @ref LL_TIM_CHANNEL_CH1
2536 * @arg @ref LL_TIM_CHANNEL_CH1N
2537 * @arg @ref LL_TIM_CHANNEL_CH2
2538 * @arg @ref LL_TIM_CHANNEL_CH2N
2539 * @arg @ref LL_TIM_CHANNEL_CH3
2540 * @arg @ref LL_TIM_CHANNEL_CH3N
2541 * @arg @ref LL_TIM_CHANNEL_CH4
2542 * @arg @ref LL_TIM_CHANNEL_CH4N
2543 * @arg @ref LL_TIM_CHANNEL_CH5
2544 * @arg @ref LL_TIM_CHANNEL_CH6
2545 * @param Polarity This parameter can be one of the following values:
2546 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2547 * @arg @ref LL_TIM_OCPOLARITY_LOW
2548 * @retval None
2549 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)2550 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2551 {
2552 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2553 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2554 }
2555
2556 /**
2557 * @brief Get the polarity of an output channel.
2558 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2559 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2560 * CCER CC2P LL_TIM_OC_GetPolarity\n
2561 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2562 * CCER CC3P LL_TIM_OC_GetPolarity\n
2563 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2564 * CCER CC4P LL_TIM_OC_GetPolarity\n
2565 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2566 * CCER CC5P LL_TIM_OC_GetPolarity\n
2567 * CCER CC6P LL_TIM_OC_GetPolarity
2568 * @param TIMx Timer instance
2569 * @param Channel This parameter can be one of the following values:
2570 * @arg @ref LL_TIM_CHANNEL_CH1
2571 * @arg @ref LL_TIM_CHANNEL_CH1N
2572 * @arg @ref LL_TIM_CHANNEL_CH2
2573 * @arg @ref LL_TIM_CHANNEL_CH2N
2574 * @arg @ref LL_TIM_CHANNEL_CH3
2575 * @arg @ref LL_TIM_CHANNEL_CH3N
2576 * @arg @ref LL_TIM_CHANNEL_CH4
2577 * @arg @ref LL_TIM_CHANNEL_CH4N
2578 * @arg @ref LL_TIM_CHANNEL_CH5
2579 * @arg @ref LL_TIM_CHANNEL_CH6
2580 * @retval Returned value can be one of the following values:
2581 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2582 * @arg @ref LL_TIM_OCPOLARITY_LOW
2583 */
LL_TIM_OC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)2584 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
2585 {
2586 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2587 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2588 }
2589
2590 /**
2591 * @brief Set the IDLE state of an output channel
2592 * @note This function is significant only for the timer instances
2593 * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
2594 * can be used to check whether or not a timer instance provides
2595 * a break input.
2596 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2597 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2598 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2599 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2600 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2601 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2602 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2603 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2604 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2605 * CR2 OIS6 LL_TIM_OC_SetIdleState
2606 * @param TIMx Timer instance
2607 * @param Channel This parameter can be one of the following values:
2608 * @arg @ref LL_TIM_CHANNEL_CH1
2609 * @arg @ref LL_TIM_CHANNEL_CH1N
2610 * @arg @ref LL_TIM_CHANNEL_CH2
2611 * @arg @ref LL_TIM_CHANNEL_CH2N
2612 * @arg @ref LL_TIM_CHANNEL_CH3
2613 * @arg @ref LL_TIM_CHANNEL_CH3N
2614 * @arg @ref LL_TIM_CHANNEL_CH4
2615 * @arg @ref LL_TIM_CHANNEL_CH4N
2616 * @arg @ref LL_TIM_CHANNEL_CH5
2617 * @arg @ref LL_TIM_CHANNEL_CH6
2618 * @param IdleState This parameter can be one of the following values:
2619 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2620 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2621 * @retval None
2622 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)2623 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2624 {
2625 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2626 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2627 }
2628
2629 /**
2630 * @brief Get the IDLE state of an output channel
2631 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2632 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2633 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2634 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2635 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2636 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2637 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2638 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2639 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2640 * CR2 OIS6 LL_TIM_OC_GetIdleState
2641 * @param TIMx Timer instance
2642 * @param Channel This parameter can be one of the following values:
2643 * @arg @ref LL_TIM_CHANNEL_CH1
2644 * @arg @ref LL_TIM_CHANNEL_CH1N
2645 * @arg @ref LL_TIM_CHANNEL_CH2
2646 * @arg @ref LL_TIM_CHANNEL_CH2N
2647 * @arg @ref LL_TIM_CHANNEL_CH3
2648 * @arg @ref LL_TIM_CHANNEL_CH3N
2649 * @arg @ref LL_TIM_CHANNEL_CH4
2650 * @arg @ref LL_TIM_CHANNEL_CH4N
2651 * @arg @ref LL_TIM_CHANNEL_CH5
2652 * @arg @ref LL_TIM_CHANNEL_CH6
2653 * @retval Returned value can be one of the following values:
2654 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2655 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2656 */
LL_TIM_OC_GetIdleState(const TIM_TypeDef * TIMx,uint32_t Channel)2657 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
2658 {
2659 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2660 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2661 }
2662
2663 /**
2664 * @brief Enable fast mode for the output channel.
2665 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2666 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2667 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2668 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2669 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2670 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2671 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2672 * @param TIMx Timer instance
2673 * @param Channel This parameter can be one of the following values:
2674 * @arg @ref LL_TIM_CHANNEL_CH1
2675 * @arg @ref LL_TIM_CHANNEL_CH2
2676 * @arg @ref LL_TIM_CHANNEL_CH3
2677 * @arg @ref LL_TIM_CHANNEL_CH4
2678 * @arg @ref LL_TIM_CHANNEL_CH5
2679 * @arg @ref LL_TIM_CHANNEL_CH6
2680 * @retval None
2681 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)2682 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2683 {
2684 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2685 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2686 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2687
2688 }
2689
2690 /**
2691 * @brief Disable fast mode for the output channel.
2692 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2693 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2694 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2695 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2696 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2697 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2698 * @param TIMx Timer instance
2699 * @param Channel This parameter can be one of the following values:
2700 * @arg @ref LL_TIM_CHANNEL_CH1
2701 * @arg @ref LL_TIM_CHANNEL_CH2
2702 * @arg @ref LL_TIM_CHANNEL_CH3
2703 * @arg @ref LL_TIM_CHANNEL_CH4
2704 * @arg @ref LL_TIM_CHANNEL_CH5
2705 * @arg @ref LL_TIM_CHANNEL_CH6
2706 * @retval None
2707 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)2708 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2709 {
2710 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2711 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2712 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2713
2714 }
2715
2716 /**
2717 * @brief Indicates whether fast mode is enabled for the output channel.
2718 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2719 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2720 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2721 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2722 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2723 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2724 * @param TIMx Timer instance
2725 * @param Channel This parameter can be one of the following values:
2726 * @arg @ref LL_TIM_CHANNEL_CH1
2727 * @arg @ref LL_TIM_CHANNEL_CH2
2728 * @arg @ref LL_TIM_CHANNEL_CH3
2729 * @arg @ref LL_TIM_CHANNEL_CH4
2730 * @arg @ref LL_TIM_CHANNEL_CH5
2731 * @arg @ref LL_TIM_CHANNEL_CH6
2732 * @retval State of bit (1 or 0).
2733 */
LL_TIM_OC_IsEnabledFast(const TIM_TypeDef * TIMx,uint32_t Channel)2734 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
2735 {
2736 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2737 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2738 uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2739 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2740 }
2741
2742 /**
2743 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2744 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2745 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2746 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2747 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2748 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2749 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2750 * @param TIMx Timer instance
2751 * @param Channel This parameter can be one of the following values:
2752 * @arg @ref LL_TIM_CHANNEL_CH1
2753 * @arg @ref LL_TIM_CHANNEL_CH2
2754 * @arg @ref LL_TIM_CHANNEL_CH3
2755 * @arg @ref LL_TIM_CHANNEL_CH4
2756 * @arg @ref LL_TIM_CHANNEL_CH5
2757 * @arg @ref LL_TIM_CHANNEL_CH6
2758 * @retval None
2759 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2760 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2761 {
2762 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2763 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2764 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2765 }
2766
2767 /**
2768 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2769 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2770 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2771 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2772 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2773 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2774 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2775 * @param TIMx Timer instance
2776 * @param Channel This parameter can be one of the following values:
2777 * @arg @ref LL_TIM_CHANNEL_CH1
2778 * @arg @ref LL_TIM_CHANNEL_CH2
2779 * @arg @ref LL_TIM_CHANNEL_CH3
2780 * @arg @ref LL_TIM_CHANNEL_CH4
2781 * @arg @ref LL_TIM_CHANNEL_CH5
2782 * @arg @ref LL_TIM_CHANNEL_CH6
2783 * @retval None
2784 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)2785 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2786 {
2787 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2788 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2789 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2790 }
2791
2792 /**
2793 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2794 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2795 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2796 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2797 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2798 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2799 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2800 * @param TIMx Timer instance
2801 * @param Channel This parameter can be one of the following values:
2802 * @arg @ref LL_TIM_CHANNEL_CH1
2803 * @arg @ref LL_TIM_CHANNEL_CH2
2804 * @arg @ref LL_TIM_CHANNEL_CH3
2805 * @arg @ref LL_TIM_CHANNEL_CH4
2806 * @arg @ref LL_TIM_CHANNEL_CH5
2807 * @arg @ref LL_TIM_CHANNEL_CH6
2808 * @retval State of bit (1 or 0).
2809 */
LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef * TIMx,uint32_t Channel)2810 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
2811 {
2812 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2813 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2814 uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2815 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2816 }
2817
2818 /**
2819 * @brief Enable clearing the output channel on an external event.
2820 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2821 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2822 * or not a timer instance can clear the OCxREF signal on an external event.
2823 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2824 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2825 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2826 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2827 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2828 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2829 * @param TIMx Timer instance
2830 * @param Channel This parameter can be one of the following values:
2831 * @arg @ref LL_TIM_CHANNEL_CH1
2832 * @arg @ref LL_TIM_CHANNEL_CH2
2833 * @arg @ref LL_TIM_CHANNEL_CH3
2834 * @arg @ref LL_TIM_CHANNEL_CH4
2835 * @arg @ref LL_TIM_CHANNEL_CH5
2836 * @arg @ref LL_TIM_CHANNEL_CH6
2837 * @retval None
2838 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)2839 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2840 {
2841 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2842 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2843 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2844 }
2845
2846 /**
2847 * @brief Disable clearing the output channel on an external event.
2848 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2849 * or not a timer instance can clear the OCxREF signal on an external event.
2850 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2851 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2852 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2853 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2854 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2855 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2856 * @param TIMx Timer instance
2857 * @param Channel This parameter can be one of the following values:
2858 * @arg @ref LL_TIM_CHANNEL_CH1
2859 * @arg @ref LL_TIM_CHANNEL_CH2
2860 * @arg @ref LL_TIM_CHANNEL_CH3
2861 * @arg @ref LL_TIM_CHANNEL_CH4
2862 * @arg @ref LL_TIM_CHANNEL_CH5
2863 * @arg @ref LL_TIM_CHANNEL_CH6
2864 * @retval None
2865 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)2866 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2867 {
2868 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2869 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2870 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2871 }
2872
2873 /**
2874 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2875 * @note This function enables clearing the output channel on an external event.
2876 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2877 * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2878 * or not a timer instance can clear the OCxREF signal on an external event.
2879 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2880 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2881 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2882 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2883 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2884 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2885 * @param TIMx Timer instance
2886 * @param Channel This parameter can be one of the following values:
2887 * @arg @ref LL_TIM_CHANNEL_CH1
2888 * @arg @ref LL_TIM_CHANNEL_CH2
2889 * @arg @ref LL_TIM_CHANNEL_CH3
2890 * @arg @ref LL_TIM_CHANNEL_CH4
2891 * @arg @ref LL_TIM_CHANNEL_CH5
2892 * @arg @ref LL_TIM_CHANNEL_CH6
2893 * @retval State of bit (1 or 0).
2894 */
LL_TIM_OC_IsEnabledClear(const TIM_TypeDef * TIMx,uint32_t Channel)2895 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
2896 {
2897 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2898 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2899 uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2900 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2901 }
2902
2903 /**
2904 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
2905 * the Ocx and OCxN signals).
2906 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2907 * dead-time insertion feature is supported by a timer instance.
2908 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2909 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2910 * @param TIMx Timer instance
2911 * @param DeadTime between Min_Data=0 and Max_Data=255
2912 * @retval None
2913 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2914 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2915 {
2916 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2917 }
2918
2919 /**
2920 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2921 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2922 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2923 * whether or not a timer instance supports a 32 bits counter.
2924 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2925 * output channel 1 is supported by a timer instance.
2926 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2927 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2928 * @param TIMx Timer instance
2929 * @param CompareValue between Min_Data=0 and Max_Data=65535
2930 * @retval None
2931 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2932 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2933 {
2934 WRITE_REG(TIMx->CCR1, CompareValue);
2935 }
2936
2937 /**
2938 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2939 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2940 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2941 * whether or not a timer instance supports a 32 bits counter.
2942 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2943 * output channel 2 is supported by a timer instance.
2944 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2945 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2946 * @param TIMx Timer instance
2947 * @param CompareValue between Min_Data=0 and Max_Data=65535
2948 * @retval None
2949 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2950 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2951 {
2952 WRITE_REG(TIMx->CCR2, CompareValue);
2953 }
2954
2955 /**
2956 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2957 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2958 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2959 * whether or not a timer instance supports a 32 bits counter.
2960 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2961 * output channel is supported by a timer instance.
2962 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2963 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2964 * @param TIMx Timer instance
2965 * @param CompareValue between Min_Data=0 and Max_Data=65535
2966 * @retval None
2967 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2968 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2969 {
2970 WRITE_REG(TIMx->CCR3, CompareValue);
2971 }
2972
2973 /**
2974 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2975 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2976 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2977 * whether or not a timer instance supports a 32 bits counter.
2978 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2979 * output channel 4 is supported by a timer instance.
2980 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2981 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2982 * @param TIMx Timer instance
2983 * @param CompareValue between Min_Data=0 and Max_Data=65535
2984 * @retval None
2985 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2986 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2987 {
2988 WRITE_REG(TIMx->CCR4, CompareValue);
2989 }
2990
2991 /**
2992 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2993 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2994 * output channel 5 is supported by a timer instance.
2995 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
2996 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2997 * @param TIMx Timer instance
2998 * @param CompareValue between Min_Data=0 and Max_Data=65535
2999 * @retval None
3000 */
LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx,uint32_t CompareValue)3001 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3002 {
3003 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3004 }
3005
3006 /**
3007 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3008 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3009 * output channel 6 is supported by a timer instance.
3010 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3011 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3012 * @param TIMx Timer instance
3013 * @param CompareValue between Min_Data=0 and Max_Data=65535
3014 * @retval None
3015 */
LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx,uint32_t CompareValue)3016 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3017 {
3018 WRITE_REG(TIMx->CCR6, CompareValue);
3019 }
3020
3021 /**
3022 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3023 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3024 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3025 * whether or not a timer instance supports a 32 bits counter.
3026 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3027 * output channel 1 is supported by a timer instance.
3028 * @note If dithering is activated, pay attention to the returned value interpretation.
3029 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3030 * @param TIMx Timer instance
3031 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3032 */
LL_TIM_OC_GetCompareCH1(const TIM_TypeDef * TIMx)3033 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
3034 {
3035 return (uint32_t)(READ_REG(TIMx->CCR1));
3036 }
3037
3038 /**
3039 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3040 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3041 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3042 * whether or not a timer instance supports a 32 bits counter.
3043 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3044 * output channel 2 is supported by a timer instance.
3045 * @note If dithering is activated, pay attention to the returned value interpretation.
3046 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3047 * @param TIMx Timer instance
3048 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3049 */
LL_TIM_OC_GetCompareCH2(const TIM_TypeDef * TIMx)3050 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
3051 {
3052 return (uint32_t)(READ_REG(TIMx->CCR2));
3053 }
3054
3055 /**
3056 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3057 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3058 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3059 * whether or not a timer instance supports a 32 bits counter.
3060 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3061 * output channel 3 is supported by a timer instance.
3062 * @note If dithering is activated, pay attention to the returned value interpretation.
3063 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3064 * @param TIMx Timer instance
3065 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3066 */
LL_TIM_OC_GetCompareCH3(const TIM_TypeDef * TIMx)3067 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
3068 {
3069 return (uint32_t)(READ_REG(TIMx->CCR3));
3070 }
3071
3072 /**
3073 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3074 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3075 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3076 * whether or not a timer instance supports a 32 bits counter.
3077 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3078 * output channel 4 is supported by a timer instance.
3079 * @note If dithering is activated, pay attention to the returned value interpretation.
3080 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3081 * @param TIMx Timer instance
3082 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3083 */
LL_TIM_OC_GetCompareCH4(const TIM_TypeDef * TIMx)3084 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
3085 {
3086 return (uint32_t)(READ_REG(TIMx->CCR4));
3087 }
3088
3089 /**
3090 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3091 * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3092 * output channel 5 is supported by a timer instance.
3093 * @note If dithering is activated, pay attention to the returned value interpretation.
3094 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3095 * @param TIMx Timer instance
3096 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3097 */
LL_TIM_OC_GetCompareCH5(const TIM_TypeDef * TIMx)3098 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
3099 {
3100 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3101 }
3102
3103 /**
3104 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3105 * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3106 * output channel 6 is supported by a timer instance.
3107 * @note If dithering is activated, pay attention to the returned value interpretation.
3108 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3109 * @param TIMx Timer instance
3110 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3111 */
LL_TIM_OC_GetCompareCH6(const TIM_TypeDef * TIMx)3112 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
3113 {
3114 return (uint32_t)(READ_REG(TIMx->CCR6));
3115 }
3116
3117 /**
3118 * @brief Select on which reference signal the OC5REF is combined to.
3119 * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3120 * whether or not a timer instance supports the combined 3-phase PWM mode.
3121 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3122 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3123 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3124 * @param TIMx Timer instance
3125 * @param GroupCH5 This parameter can be a combination of the following values:
3126 * @arg @ref LL_TIM_GROUPCH5_NONE
3127 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3128 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3129 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3130 * @retval None
3131 */
LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx,uint32_t GroupCH5)3132 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3133 {
3134 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3135 }
3136
3137 /**
3138 * @brief Set the pulse on compare pulse width prescaler.
3139 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3140 * whether or not the pulse on compare feature is supported by the timer
3141 * instance.
3142 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3143 * @param TIMx Timer instance
3144 * @param PulseWidthPrescaler This parameter can be one of the following values:
3145 * @arg @ref LL_TIM_PWPRSC_X1
3146 * @arg @ref LL_TIM_PWPRSC_X2
3147 * @arg @ref LL_TIM_PWPRSC_X4
3148 * @arg @ref LL_TIM_PWPRSC_X8
3149 * @arg @ref LL_TIM_PWPRSC_X16
3150 * @arg @ref LL_TIM_PWPRSC_X32
3151 * @arg @ref LL_TIM_PWPRSC_X64
3152 * @arg @ref LL_TIM_PWPRSC_X128
3153 * @retval None
3154 */
LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef * TIMx,uint32_t PulseWidthPrescaler)3155 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3156 {
3157 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3158 }
3159
3160 /**
3161 * @brief Get the pulse on compare pulse width prescaler.
3162 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3163 * whether or not the pulse on compare feature is supported by the timer
3164 * instance.
3165 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3166 * @param TIMx Timer instance
3167 * @retval Returned value can be one of the following values:
3168 * @arg @ref LL_TIM_PWPRSC_X1
3169 * @arg @ref LL_TIM_PWPRSC_X2
3170 * @arg @ref LL_TIM_PWPRSC_X4
3171 * @arg @ref LL_TIM_PWPRSC_X8
3172 * @arg @ref LL_TIM_PWPRSC_X16
3173 * @arg @ref LL_TIM_PWPRSC_X32
3174 * @arg @ref LL_TIM_PWPRSC_X64
3175 * @arg @ref LL_TIM_PWPRSC_X128
3176 */
LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef * TIMx)3177 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
3178 {
3179 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3180 }
3181
3182 /**
3183 * @brief Set the pulse on compare pulse width duration.
3184 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3185 * whether or not the pulse on compare feature is supported by the timer
3186 * instance.
3187 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3188 * @param TIMx Timer instance
3189 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3190 * @retval None
3191 */
LL_TIM_OC_SetPulseWidth(TIM_TypeDef * TIMx,uint32_t PulseWidth)3192 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3193 {
3194 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
3195 }
3196
3197 /**
3198 * @brief Get the pulse on compare pulse width duration.
3199 * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3200 * whether or not the pulse on compare feature is supported by the timer
3201 * instance.
3202 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3203 * @param TIMx Timer instance
3204 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3205 */
LL_TIM_OC_GetPulseWidth(const TIM_TypeDef * TIMx)3206 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
3207 {
3208 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3209 }
3210
3211 /**
3212 * @}
3213 */
3214
3215 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3216 * @{
3217 */
3218 /**
3219 * @brief Configure input channel.
3220 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3221 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3222 * CCMR1 IC1F LL_TIM_IC_Config\n
3223 * CCMR1 CC2S LL_TIM_IC_Config\n
3224 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3225 * CCMR1 IC2F LL_TIM_IC_Config\n
3226 * CCMR2 CC3S LL_TIM_IC_Config\n
3227 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3228 * CCMR2 IC3F LL_TIM_IC_Config\n
3229 * CCMR2 CC4S LL_TIM_IC_Config\n
3230 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3231 * CCMR2 IC4F LL_TIM_IC_Config\n
3232 * CCER CC1P LL_TIM_IC_Config\n
3233 * CCER CC1NP LL_TIM_IC_Config\n
3234 * CCER CC2P LL_TIM_IC_Config\n
3235 * CCER CC2NP LL_TIM_IC_Config\n
3236 * CCER CC3P LL_TIM_IC_Config\n
3237 * CCER CC3NP LL_TIM_IC_Config\n
3238 * CCER CC4P LL_TIM_IC_Config\n
3239 * CCER CC4NP LL_TIM_IC_Config
3240 * @param TIMx Timer instance
3241 * @param Channel This parameter can be one of the following values:
3242 * @arg @ref LL_TIM_CHANNEL_CH1
3243 * @arg @ref LL_TIM_CHANNEL_CH2
3244 * @arg @ref LL_TIM_CHANNEL_CH3
3245 * @arg @ref LL_TIM_CHANNEL_CH4
3246 * @param Configuration This parameter must be a combination of all the following values:
3247 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3248 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3249 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3250 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3251 * @retval None
3252 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)3253 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3254 {
3255 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3256 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3257 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3258 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
3259 << SHIFT_TAB_ICxx[iChannel]);
3260 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3261 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3262 }
3263
3264 /**
3265 * @brief Set the active input.
3266 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3267 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3268 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3269 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3270 * @param TIMx Timer instance
3271 * @param Channel This parameter can be one of the following values:
3272 * @arg @ref LL_TIM_CHANNEL_CH1
3273 * @arg @ref LL_TIM_CHANNEL_CH2
3274 * @arg @ref LL_TIM_CHANNEL_CH3
3275 * @arg @ref LL_TIM_CHANNEL_CH4
3276 * @param ICActiveInput This parameter can be one of the following values:
3277 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3278 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3279 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3280 * @retval None
3281 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)3282 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3283 {
3284 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3285 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3286 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3287 }
3288
3289 /**
3290 * @brief Get the current active input.
3291 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3292 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3293 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3294 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3295 * @param TIMx Timer instance
3296 * @param Channel This parameter can be one of the following values:
3297 * @arg @ref LL_TIM_CHANNEL_CH1
3298 * @arg @ref LL_TIM_CHANNEL_CH2
3299 * @arg @ref LL_TIM_CHANNEL_CH3
3300 * @arg @ref LL_TIM_CHANNEL_CH4
3301 * @retval Returned value can be one of the following values:
3302 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3303 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3304 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3305 */
LL_TIM_IC_GetActiveInput(const TIM_TypeDef * TIMx,uint32_t Channel)3306 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
3307 {
3308 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3309 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3310 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3311 }
3312
3313 /**
3314 * @brief Set the prescaler of input channel.
3315 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3316 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3317 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3318 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3319 * @param TIMx Timer instance
3320 * @param Channel This parameter can be one of the following values:
3321 * @arg @ref LL_TIM_CHANNEL_CH1
3322 * @arg @ref LL_TIM_CHANNEL_CH2
3323 * @arg @ref LL_TIM_CHANNEL_CH3
3324 * @arg @ref LL_TIM_CHANNEL_CH4
3325 * @param ICPrescaler This parameter can be one of the following values:
3326 * @arg @ref LL_TIM_ICPSC_DIV1
3327 * @arg @ref LL_TIM_ICPSC_DIV2
3328 * @arg @ref LL_TIM_ICPSC_DIV4
3329 * @arg @ref LL_TIM_ICPSC_DIV8
3330 * @retval None
3331 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)3332 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3333 {
3334 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3335 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3336 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3337 }
3338
3339 /**
3340 * @brief Get the current prescaler value acting on an input channel.
3341 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3342 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3343 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3344 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3345 * @param TIMx Timer instance
3346 * @param Channel This parameter can be one of the following values:
3347 * @arg @ref LL_TIM_CHANNEL_CH1
3348 * @arg @ref LL_TIM_CHANNEL_CH2
3349 * @arg @ref LL_TIM_CHANNEL_CH3
3350 * @arg @ref LL_TIM_CHANNEL_CH4
3351 * @retval Returned value can be one of the following values:
3352 * @arg @ref LL_TIM_ICPSC_DIV1
3353 * @arg @ref LL_TIM_ICPSC_DIV2
3354 * @arg @ref LL_TIM_ICPSC_DIV4
3355 * @arg @ref LL_TIM_ICPSC_DIV8
3356 */
LL_TIM_IC_GetPrescaler(const TIM_TypeDef * TIMx,uint32_t Channel)3357 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
3358 {
3359 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3360 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3361 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3362 }
3363
3364 /**
3365 * @brief Set the input filter duration.
3366 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3367 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3368 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3369 * CCMR2 IC4F LL_TIM_IC_SetFilter
3370 * @param TIMx Timer instance
3371 * @param Channel This parameter can be one of the following values:
3372 * @arg @ref LL_TIM_CHANNEL_CH1
3373 * @arg @ref LL_TIM_CHANNEL_CH2
3374 * @arg @ref LL_TIM_CHANNEL_CH3
3375 * @arg @ref LL_TIM_CHANNEL_CH4
3376 * @param ICFilter This parameter can be one of the following values:
3377 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3378 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3379 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3380 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3381 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3382 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3383 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3384 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3385 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3386 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3387 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3388 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3389 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3390 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3391 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3392 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3393 * @retval None
3394 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)3395 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3396 {
3397 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3398 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3399 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3400 }
3401
3402 /**
3403 * @brief Get the input filter duration.
3404 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3405 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3406 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3407 * CCMR2 IC4F LL_TIM_IC_GetFilter
3408 * @param TIMx Timer instance
3409 * @param Channel This parameter can be one of the following values:
3410 * @arg @ref LL_TIM_CHANNEL_CH1
3411 * @arg @ref LL_TIM_CHANNEL_CH2
3412 * @arg @ref LL_TIM_CHANNEL_CH3
3413 * @arg @ref LL_TIM_CHANNEL_CH4
3414 * @retval Returned value can be one of the following values:
3415 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3416 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3417 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3418 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3419 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3420 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3421 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3422 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3423 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3424 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3425 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3426 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3427 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3428 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3429 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3430 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3431 */
LL_TIM_IC_GetFilter(const TIM_TypeDef * TIMx,uint32_t Channel)3432 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
3433 {
3434 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3435 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3436 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3437 }
3438
3439 /**
3440 * @brief Set the input channel polarity.
3441 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3442 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3443 * CCER CC2P LL_TIM_IC_SetPolarity\n
3444 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3445 * CCER CC3P LL_TIM_IC_SetPolarity\n
3446 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3447 * CCER CC4P LL_TIM_IC_SetPolarity\n
3448 * CCER CC4NP LL_TIM_IC_SetPolarity
3449 * @param TIMx Timer instance
3450 * @param Channel This parameter can be one of the following values:
3451 * @arg @ref LL_TIM_CHANNEL_CH1
3452 * @arg @ref LL_TIM_CHANNEL_CH2
3453 * @arg @ref LL_TIM_CHANNEL_CH3
3454 * @arg @ref LL_TIM_CHANNEL_CH4
3455 * @param ICPolarity This parameter can be one of the following values:
3456 * @arg @ref LL_TIM_IC_POLARITY_RISING
3457 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3458 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3459 * @retval None
3460 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)3461 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3462 {
3463 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3464 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3465 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3466 }
3467
3468 /**
3469 * @brief Get the current input channel polarity.
3470 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3471 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3472 * CCER CC2P LL_TIM_IC_GetPolarity\n
3473 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3474 * CCER CC3P LL_TIM_IC_GetPolarity\n
3475 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3476 * CCER CC4P LL_TIM_IC_GetPolarity\n
3477 * CCER CC4NP LL_TIM_IC_GetPolarity
3478 * @param TIMx Timer instance
3479 * @param Channel This parameter can be one of the following values:
3480 * @arg @ref LL_TIM_CHANNEL_CH1
3481 * @arg @ref LL_TIM_CHANNEL_CH2
3482 * @arg @ref LL_TIM_CHANNEL_CH3
3483 * @arg @ref LL_TIM_CHANNEL_CH4
3484 * @retval Returned value can be one of the following values:
3485 * @arg @ref LL_TIM_IC_POLARITY_RISING
3486 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3487 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3488 */
LL_TIM_IC_GetPolarity(const TIM_TypeDef * TIMx,uint32_t Channel)3489 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
3490 {
3491 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3492 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3493 SHIFT_TAB_CCxP[iChannel]);
3494 }
3495
3496 /**
3497 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3498 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3499 * a timer instance provides an XOR input.
3500 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3501 * @param TIMx Timer instance
3502 * @retval None
3503 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)3504 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3505 {
3506 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3507 }
3508
3509 /**
3510 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3511 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3512 * a timer instance provides an XOR input.
3513 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3514 * @param TIMx Timer instance
3515 * @retval None
3516 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)3517 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3518 {
3519 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3520 }
3521
3522 /**
3523 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3524 * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3525 * a timer instance provides an XOR input.
3526 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3527 * @param TIMx Timer instance
3528 * @retval State of bit (1 or 0).
3529 */
LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef * TIMx)3530 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
3531 {
3532 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3533 }
3534
3535 /**
3536 * @brief Get captured value for input channel 1.
3537 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3538 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3539 * whether or not a timer instance supports a 32 bits counter.
3540 * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3541 * input channel 1 is supported by a timer instance.
3542 * @note If dithering is activated, pay attention to the returned value interpretation.
3543 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3544 * @param TIMx Timer instance
3545 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3546 */
LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef * TIMx)3547 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
3548 {
3549 return (uint32_t)(READ_REG(TIMx->CCR1));
3550 }
3551
3552 /**
3553 * @brief Get captured value for input channel 2.
3554 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3555 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3556 * whether or not a timer instance supports a 32 bits counter.
3557 * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3558 * input channel 2 is supported by a timer instance.
3559 * @note If dithering is activated, pay attention to the returned value interpretation.
3560 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3561 * @param TIMx Timer instance
3562 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3563 */
LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef * TIMx)3564 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
3565 {
3566 return (uint32_t)(READ_REG(TIMx->CCR2));
3567 }
3568
3569 /**
3570 * @brief Get captured value for input channel 3.
3571 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3572 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3573 * whether or not a timer instance supports a 32 bits counter.
3574 * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3575 * input channel 3 is supported by a timer instance.
3576 * @note If dithering is activated, pay attention to the returned value interpretation.
3577 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3578 * @param TIMx Timer instance
3579 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3580 */
LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef * TIMx)3581 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
3582 {
3583 return (uint32_t)(READ_REG(TIMx->CCR3));
3584 }
3585
3586 /**
3587 * @brief Get captured value for input channel 4.
3588 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3589 * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3590 * whether or not a timer instance supports a 32 bits counter.
3591 * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3592 * input channel 4 is supported by a timer instance.
3593 * @note If dithering is activated, pay attention to the returned value interpretation.
3594 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3595 * @param TIMx Timer instance
3596 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3597 */
LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef * TIMx)3598 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
3599 {
3600 return (uint32_t)(READ_REG(TIMx->CCR4));
3601 }
3602
3603 /**
3604 * @}
3605 */
3606
3607 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3608 * @{
3609 */
3610 /**
3611 * @brief Enable external clock mode 2.
3612 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3613 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3614 * whether or not a timer instance supports external clock mode2.
3615 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3616 * @param TIMx Timer instance
3617 * @retval None
3618 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)3619 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3620 {
3621 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3622 }
3623
3624 /**
3625 * @brief Disable external clock mode 2.
3626 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3627 * whether or not a timer instance supports external clock mode2.
3628 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3629 * @param TIMx Timer instance
3630 * @retval None
3631 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)3632 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3633 {
3634 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3635 }
3636
3637 /**
3638 * @brief Indicate whether external clock mode 2 is enabled.
3639 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3640 * whether or not a timer instance supports external clock mode2.
3641 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3642 * @param TIMx Timer instance
3643 * @retval State of bit (1 or 0).
3644 */
LL_TIM_IsEnabledExternalClock(const TIM_TypeDef * TIMx)3645 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
3646 {
3647 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3648 }
3649
3650 /**
3651 * @brief Set the clock source of the counter clock.
3652 * @note when selected clock source is external clock mode 1, the timer input
3653 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3654 * function. This timer input must be configured by calling
3655 * the @ref LL_TIM_IC_Config() function.
3656 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3657 * whether or not a timer instance supports external clock mode1.
3658 * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3659 * whether or not a timer instance supports external clock mode2.
3660 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3661 * SMCR ECE LL_TIM_SetClockSource
3662 * @param TIMx Timer instance
3663 * @param ClockSource This parameter can be one of the following values:
3664 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3665 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3666 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3667 * @retval None
3668 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)3669 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3670 {
3671 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3672 }
3673
3674 /**
3675 * @brief Set the encoder interface mode.
3676 * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3677 * whether or not a timer instance supports the encoder mode.
3678 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3679 * @param TIMx Timer instance
3680 * @param EncoderMode This parameter can be one of the following values:
3681 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3682 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3683 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3684 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3685 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3686 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3687 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3688 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3689 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3690 * @retval None
3691 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)3692 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3693 {
3694 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3695 }
3696
3697 /**
3698 * @}
3699 */
3700
3701 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3702 * @{
3703 */
3704 /**
3705 * @brief Set the trigger output (TRGO) used for timer synchronization .
3706 * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3707 * whether or not a timer instance can operate as a master timer.
3708 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3709 * @param TIMx Timer instance
3710 * @param TimerSynchronization This parameter can be one of the following values:
3711 * @arg @ref LL_TIM_TRGO_RESET
3712 * @arg @ref LL_TIM_TRGO_ENABLE
3713 * @arg @ref LL_TIM_TRGO_UPDATE
3714 * @arg @ref LL_TIM_TRGO_CC1IF
3715 * @arg @ref LL_TIM_TRGO_OC1REF
3716 * @arg @ref LL_TIM_TRGO_OC2REF
3717 * @arg @ref LL_TIM_TRGO_OC3REF
3718 * @arg @ref LL_TIM_TRGO_OC4REF
3719 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3720 * @retval None
3721 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)3722 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3723 {
3724 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3725 }
3726
3727 /**
3728 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3729 * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3730 * whether or not a timer instance can be used for ADC synchronization.
3731 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3732 * @param TIMx Timer Instance
3733 * @param ADCSynchronization This parameter can be one of the following values:
3734 * @arg @ref LL_TIM_TRGO2_RESET
3735 * @arg @ref LL_TIM_TRGO2_ENABLE
3736 * @arg @ref LL_TIM_TRGO2_UPDATE
3737 * @arg @ref LL_TIM_TRGO2_CC1F
3738 * @arg @ref LL_TIM_TRGO2_OC1
3739 * @arg @ref LL_TIM_TRGO2_OC2
3740 * @arg @ref LL_TIM_TRGO2_OC3
3741 * @arg @ref LL_TIM_TRGO2_OC4
3742 * @arg @ref LL_TIM_TRGO2_OC5
3743 * @arg @ref LL_TIM_TRGO2_OC6
3744 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3745 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3746 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3747 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3748 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3749 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3750 * @retval None
3751 */
LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx,uint32_t ADCSynchronization)3752 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3753 {
3754 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3755 }
3756
3757 /**
3758 * @brief Set the synchronization mode of a slave timer.
3759 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3760 * a timer instance can operate as a slave timer.
3761 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3762 * @param TIMx Timer instance
3763 * @param SlaveMode This parameter can be one of the following values:
3764 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3765 * @arg @ref LL_TIM_SLAVEMODE_RESET
3766 * @arg @ref LL_TIM_SLAVEMODE_GATED
3767 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3768 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3769 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3770 * @retval None
3771 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)3772 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3773 {
3774 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3775 }
3776
3777 /**
3778 * @brief Set the selects the trigger input to be used to synchronize the counter.
3779 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3780 * a timer instance can operate as a slave timer.
3781 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3782 * @param TIMx Timer instance
3783 * @param TriggerInput This parameter can be one of the following values:
3784 * @arg @ref LL_TIM_TS_ITR0
3785 * @arg @ref LL_TIM_TS_ITR1
3786 * @arg @ref LL_TIM_TS_ITR2
3787 * @arg @ref LL_TIM_TS_ITR3
3788 * @arg @ref LL_TIM_TS_ITR4
3789 * @arg @ref LL_TIM_TS_ITR5
3790 * @arg @ref LL_TIM_TS_ITR6
3791 * @arg @ref LL_TIM_TS_ITR7
3792 * @arg @ref LL_TIM_TS_ITR8
3793 * @arg @ref LL_TIM_TS_ITR9
3794 * @arg @ref LL_TIM_TS_ITR10
3795 * @arg @ref LL_TIM_TS_ITR11
3796 * @arg @ref LL_TIM_TS_ITR12
3797 * @arg @ref LL_TIM_TS_TI1F_ED
3798 * @arg @ref LL_TIM_TS_TI1FP1
3799 * @arg @ref LL_TIM_TS_TI2FP2
3800 * @arg @ref LL_TIM_TS_ETRF
3801 * @retval None
3802 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)3803 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3804 {
3805 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3806 }
3807
3808 /**
3809 * @brief Enable the Master/Slave mode.
3810 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3811 * a timer instance can operate as a slave timer.
3812 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3813 * @param TIMx Timer instance
3814 * @retval None
3815 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)3816 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3817 {
3818 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3819 }
3820
3821 /**
3822 * @brief Disable the Master/Slave mode.
3823 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3824 * a timer instance can operate as a slave timer.
3825 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3826 * @param TIMx Timer instance
3827 * @retval None
3828 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)3829 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3830 {
3831 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3832 }
3833
3834 /**
3835 * @brief Indicates whether the Master/Slave mode is enabled.
3836 * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3837 * a timer instance can operate as a slave timer.
3838 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3839 * @param TIMx Timer instance
3840 * @retval State of bit (1 or 0).
3841 */
LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef * TIMx)3842 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
3843 {
3844 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
3845 }
3846
3847 /**
3848 * @brief Configure the external trigger (ETR) input.
3849 * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3850 * a timer instance provides an external trigger input.
3851 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3852 * SMCR ETPS LL_TIM_ConfigETR\n
3853 * SMCR ETF LL_TIM_ConfigETR
3854 * @param TIMx Timer instance
3855 * @param ETRPolarity This parameter can be one of the following values:
3856 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3857 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3858 * @param ETRPrescaler This parameter can be one of the following values:
3859 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3860 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3861 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3862 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3863 * @param ETRFilter This parameter can be one of the following values:
3864 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3865 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3866 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3867 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3868 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3869 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3870 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3871 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3872 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3873 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3874 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3875 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3876 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3877 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3878 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3879 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3880 * @retval None
3881 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)3882 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3883 uint32_t ETRFilter)
3884 {
3885 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3886 }
3887
3888 /**
3889 * @brief Select the external trigger (ETR) input source.
3890 * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
3891 * not a timer instance supports ETR source selection.
3892 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
3893 * @param TIMx Timer instance
3894 * @param ETRSource This parameter can be one of the following values:
3895 *
3896 * TIM1: any combination of ETR_RMP where
3897 *
3898 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
3899 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*)
3900 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
3901 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
3902 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
3903 *
3904 * TIM2: any combination of ETR_RMP where
3905 *
3906 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
3907 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*)
3908 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
3909 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA (*)
3910 * @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB (*)
3911 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
3912 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (*)
3913 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
3914 * @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS (*)
3915
3916 *
3917 * TIM3: any combination of ETR_RMP where
3918 *
3919 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
3920 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*)
3921 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
3922 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (*)
3923 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR (*)
3924 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS (*)
3925 *
3926 * TIM4: any combination of ETR_RMP where (**)
3927 *
3928 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
3929 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
3930 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
3931 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
3932 *
3933 * TIM5: any combination of ETR_RMP where (**)
3934 *
3935 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
3936 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
3937 * @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
3938 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
3939 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
3940 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
3941 *
3942 * TIM8: any combination of ETR_RMP where (**)
3943 *
3944 * . . ETR_RMP can be one of the following values
3945 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
3946 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
3947 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
3948 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
3949 *
3950 * (*) Value not defined in all devices. \n
3951 * (**) Timer instance not available on all devices. \n
3952 * @retval None
3953 */
LL_TIM_SetETRSource(TIM_TypeDef * TIMx,uint32_t ETRSource)3954 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
3955 {
3956 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
3957 }
3958
3959 /**
3960 * @brief Enable SMS preload.
3961 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3962 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3963 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
3964 * @param TIMx Timer instance
3965 * @retval None
3966 */
LL_TIM_EnableSMSPreload(TIM_TypeDef * TIMx)3967 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
3968 {
3969 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3970 }
3971
3972 /**
3973 * @brief Disable SMS preload.
3974 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3975 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3976 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
3977 * @param TIMx Timer instance
3978 * @retval None
3979 */
LL_TIM_DisableSMSPreload(TIM_TypeDef * TIMx)3980 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
3981 {
3982 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
3983 }
3984
3985 /**
3986 * @brief Indicate whether SMS preload is enabled.
3987 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
3988 * whether or not a timer instance supports the preload of SMS field in SMCR register.
3989 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
3990 * @param TIMx Timer instance
3991 * @retval State of bit (1 or 0).
3992 */
LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef * TIMx)3993 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
3994 {
3995 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
3996 }
3997
3998 /**
3999 * @brief Set the preload source of SMS.
4000 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4001 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4002 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4003 * @param TIMx Timer instance
4004 * @param PreloadSource This parameter can be one of the following values:
4005 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4006 * @arg @ref LL_TIM_SMSPS_INDEX
4007 * @retval None
4008 */
LL_TIM_SetSMSPreloadSource(TIM_TypeDef * TIMx,uint32_t PreloadSource)4009 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4010 {
4011 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4012 }
4013
4014 /**
4015 * @brief Get the preload source of SMS.
4016 * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4017 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4018 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4019 * @param TIMx Timer instance
4020 * @retval Returned value can be one of the following values:
4021 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4022 * @arg @ref LL_TIM_SMSPS_INDEX
4023 */
LL_TIM_GetSMSPreloadSource(const TIM_TypeDef * TIMx)4024 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
4025 {
4026 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4027 }
4028
4029 /**
4030 * @}
4031 */
4032
4033 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4034 * @{
4035 */
4036 /**
4037 * @brief Enable the break function.
4038 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4039 * a timer instance provides a break input.
4040 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4041 * @param TIMx Timer instance
4042 * @retval None
4043 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)4044 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4045 {
4046 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4047 }
4048
4049 /**
4050 * @brief Disable the break function.
4051 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4052 * @param TIMx Timer instance
4053 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4054 * a timer instance provides a break input.
4055 * @retval None
4056 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)4057 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4058 {
4059 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4060 }
4061
4062 /**
4063 * @brief Configure the break input.
4064 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4065 * a timer instance provides a break input.
4066 * @note Bidirectional mode is only supported by advanced timer instances.
4067 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4068 * a timer instance is an advanced-control timer.
4069 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4070 * in input mode and in open drain output mode. Any active Break event will
4071 * assert a low logic level on the Break input to indicate an internal break
4072 * event to external devices.
4073 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4074 * LL_TIM_BREAK_AFMODE_INPUT.
4075 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4076 * BDTR BKF LL_TIM_ConfigBRK\n
4077 * BDTR BKBID LL_TIM_ConfigBRK
4078 * @param TIMx Timer instance
4079 * @param BreakPolarity This parameter can be one of the following values:
4080 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4081 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4082 * @param BreakFilter This parameter can be one of the following values:
4083 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4084 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4085 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4086 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4087 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4088 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4089 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4090 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4091 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4092 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4093 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4094 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4095 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4096 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4097 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4098 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4099 * @param BreakAFMode This parameter can be one of the following values:
4100 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4101 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4102 * @retval None
4103 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity,uint32_t BreakFilter,uint32_t BreakAFMode)4104 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4105 uint32_t BreakAFMode)
4106 {
4107 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4108 }
4109
4110 /**
4111 * @brief Disarm the break input (when it operates in bidirectional mode).
4112 * @note The break input can be disarmed only when it is configured in
4113 * bidirectional mode and when when MOE is reset.
4114 * @note Purpose is to be able to have the input voltage back to high-state,
4115 * whatever the time constant on the output .
4116 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4117 * @param TIMx Timer instance
4118 * @retval None
4119 */
LL_TIM_DisarmBRK(TIM_TypeDef * TIMx)4120 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4121 {
4122 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4123 }
4124
4125 /**
4126 * @brief Re-arm the break input (when it operates in bidirectional mode).
4127 * @note The Break input is automatically armed as soon as MOE bit is set.
4128 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
4129 * @param TIMx Timer instance
4130 * @retval None
4131 */
LL_TIM_ReArmBRK(TIM_TypeDef * TIMx)4132 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
4133 {
4134 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4135 }
4136
4137 /**
4138 * @brief Enable the break 2 function.
4139 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4140 * a timer instance provides a second break input.
4141 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4142 * @param TIMx Timer instance
4143 * @retval None
4144 */
LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)4145 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4146 {
4147 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4148 }
4149
4150 /**
4151 * @brief Disable the break 2 function.
4152 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4153 * a timer instance provides a second break input.
4154 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4155 * @param TIMx Timer instance
4156 * @retval None
4157 */
LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)4158 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4159 {
4160 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4161 }
4162
4163 /**
4164 * @brief Configure the break 2 input.
4165 * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4166 * a timer instance provides a second break input.
4167 * @note Bidirectional mode is only supported by advanced timer instances.
4168 * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4169 * a timer instance is an advanced-control timer.
4170 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4171 * in input mode and in open drain output mode. Any active Break event will
4172 * assert a low logic level on the Break 2 input to indicate an internal break
4173 * event to external devices.
4174 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4175 * LL_TIM_BREAK2_AFMODE_INPUT.
4176 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4177 * BDTR BK2F LL_TIM_ConfigBRK2\n
4178 * BDTR BK2BID LL_TIM_ConfigBRK2
4179 * @param TIMx Timer instance
4180 * @param Break2Polarity This parameter can be one of the following values:
4181 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4182 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4183 * @param Break2Filter This parameter can be one of the following values:
4184 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4185 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4186 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4187 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4188 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4189 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4190 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4191 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4192 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4193 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4194 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4195 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4196 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4197 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4198 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4199 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4200 * @param Break2AFMode This parameter can be one of the following values:
4201 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4202 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4203 * @retval None
4204 */
LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx,uint32_t Break2Polarity,uint32_t Break2Filter,uint32_t Break2AFMode)4205 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4206 uint32_t Break2AFMode)
4207 {
4208 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4209 }
4210
4211 /**
4212 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4213 * @note The break 2 input can be disarmed only when it is configured in
4214 * bidirectional mode and when when MOE is reset.
4215 * @note Purpose is to be able to have the input voltage back to high-state,
4216 * whatever the time constant on the output.
4217 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4218 * @param TIMx Timer instance
4219 * @retval None
4220 */
LL_TIM_DisarmBRK2(TIM_TypeDef * TIMx)4221 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4222 {
4223 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4224 }
4225
4226 /**
4227 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
4228 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
4229 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
4230 * @param TIMx Timer instance
4231 * @retval None
4232 */
LL_TIM_ReArmBRK2(TIM_TypeDef * TIMx)4233 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
4234 {
4235 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4236 }
4237
4238 /**
4239 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4240 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4241 * a timer instance provides a break input.
4242 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4243 * BDTR OSSR LL_TIM_SetOffStates
4244 * @param TIMx Timer instance
4245 * @param OffStateIdle This parameter can be one of the following values:
4246 * @arg @ref LL_TIM_OSSI_DISABLE
4247 * @arg @ref LL_TIM_OSSI_ENABLE
4248 * @param OffStateRun This parameter can be one of the following values:
4249 * @arg @ref LL_TIM_OSSR_DISABLE
4250 * @arg @ref LL_TIM_OSSR_ENABLE
4251 * @retval None
4252 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)4253 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4254 {
4255 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4256 }
4257
4258 /**
4259 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4260 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4261 * a timer instance provides a break input.
4262 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4263 * @param TIMx Timer instance
4264 * @retval None
4265 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)4266 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4267 {
4268 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4269 }
4270
4271 /**
4272 * @brief Disable automatic output (MOE can be set only by software).
4273 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4274 * a timer instance provides a break input.
4275 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4276 * @param TIMx Timer instance
4277 * @retval None
4278 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)4279 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4280 {
4281 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4282 }
4283
4284 /**
4285 * @brief Indicate whether automatic output is enabled.
4286 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4287 * a timer instance provides a break input.
4288 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4289 * @param TIMx Timer instance
4290 * @retval State of bit (1 or 0).
4291 */
LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef * TIMx)4292 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
4293 {
4294 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4295 }
4296
4297 /**
4298 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4299 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4300 * software and is reset in case of break or break2 event
4301 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4302 * a timer instance provides a break input.
4303 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4304 * @param TIMx Timer instance
4305 * @retval None
4306 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)4307 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4308 {
4309 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4310 }
4311
4312 /**
4313 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4314 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4315 * software and is reset in case of break or break2 event.
4316 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4317 * a timer instance provides a break input.
4318 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4319 * @param TIMx Timer instance
4320 * @retval None
4321 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)4322 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4323 {
4324 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4325 }
4326
4327 /**
4328 * @brief Indicates whether outputs are enabled.
4329 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4330 * a timer instance provides a break input.
4331 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4332 * @param TIMx Timer instance
4333 * @retval State of bit (1 or 0).
4334 */
LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef * TIMx)4335 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
4336 {
4337 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4338 }
4339
4340 /**
4341 * @brief Enable the signals connected to the designated timer break input.
4342 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4343 * or not a timer instance allows for break input selection.
4344 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4345 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4346 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
4347 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4348 * @param TIMx Timer instance
4349 * @param BreakInput This parameter can be one of the following values:
4350 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4351 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4352 * @param Source This parameter can be one of the following values:
4353 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4354 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4355 *
4356 * (*) Value not defined in all devices.
4357 * @retval None
4358 */
LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4359 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4360 {
4361 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4362 SET_BIT(*pReg, Source);
4363 }
4364
4365 /**
4366 * @brief Disable the signals connected to the designated timer break input.
4367 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4368 * or not a timer instance allows for break input selection.
4369 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4370 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4371 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
4372 * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n
4373 * @param TIMx Timer instance
4374 * @param BreakInput This parameter can be one of the following values:
4375 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4376 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4377 * @param Source This parameter can be one of the following values:
4378 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4379 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4380 *
4381 * (*) Value not defined in all devices.
4382 * @retval None
4383 */
LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source)4384 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4385 {
4386 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4387 CLEAR_BIT(*pReg, Source);
4388 }
4389
4390 /**
4391 * @brief Set the polarity of the break signal for the timer break input.
4392 * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4393 * or not a timer instance allows for break input selection.
4394 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4395 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4396 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4397 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4398 * @param TIMx Timer instance
4399 * @param BreakInput This parameter can be one of the following values:
4400 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4401 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4402 * @param Source This parameter can be one of the following values:
4403 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4404 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 (*)
4405 * @param Polarity This parameter can be one of the following values:
4406 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4407 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4408 *
4409 * (*) Value not defined in all devices.
4410 * @retval None
4411 */
LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx,uint32_t BreakInput,uint32_t Source,uint32_t Polarity)4412 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4413 uint32_t Polarity)
4414 {
4415 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4416 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4417 }
4418 /**
4419 * @brief Enable asymmetrical deadtime.
4420 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4421 * a timer instance provides asymmetrical deadtime.
4422 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4423 * @param TIMx Timer instance
4424 * @retval None
4425 */
LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4426 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4427 {
4428 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4429 }
4430
4431 /**
4432 * @brief Disable asymmetrical dead-time.
4433 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4434 * a timer instance provides asymmetrical deadtime.
4435 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4436 * @param TIMx Timer instance
4437 * @retval None
4438 */
LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef * TIMx)4439 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4440 {
4441 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4442 }
4443
4444 /**
4445 * @brief Indicates whether asymmetrical deadtime is activated.
4446 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4447 * a timer instance provides asymmetrical deadtime.
4448 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4449 * @param TIMx Timer instance
4450 * @retval State of bit (1 or 0).
4451 */
LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef * TIMx)4452 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
4453 {
4454 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4455 }
4456
4457 /**
4458 * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
4459 * rising edge of OCxN signals).
4460 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4461 * asymmetrical dead-time insertion feature is supported by a timer instance.
4462 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4463 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4464 * (LOCK bits in TIMx_BDTR register).
4465 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4466 * @param TIMx Timer instance
4467 * @param DeadTime between Min_Data=0 and Max_Data=255
4468 * @retval None
4469 */
LL_TIM_SetFallingDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)4470 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4471 {
4472 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4473 }
4474
4475 /**
4476 * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
4477 * the rising edge of OCxN signals).
4478 * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4479 * asymmetrical dead-time insertion feature is supported by a timer instance.
4480 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4481 * (LOCK bits in TIMx_BDTR register).
4482 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4483 * @param TIMx Timer instance
4484 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4485 */
LL_TIM_GetFallingDeadTime(const TIM_TypeDef * TIMx)4486 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
4487 {
4488 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4489 }
4490
4491 /**
4492 * @brief Enable deadtime preload.
4493 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4494 * a timer instance provides deadtime preload.
4495 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4496 * @param TIMx Timer instance
4497 * @retval None
4498 */
LL_TIM_EnableDeadTimePreload(TIM_TypeDef * TIMx)4499 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4500 {
4501 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4502 }
4503
4504 /**
4505 * @brief Disable dead-time preload.
4506 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4507 * a timer instance provides deadtime preload.
4508 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4509 * @param TIMx Timer instance
4510 * @retval None
4511 */
LL_TIM_DisableDeadTimePreload(TIM_TypeDef * TIMx)4512 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4513 {
4514 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4515 }
4516
4517 /**
4518 * @brief Indicates whether deadtime preload is activated.
4519 * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4520 * a timer instance provides deadtime preload.
4521 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4522 * @param TIMx Timer instance
4523 * @retval State of bit (1 or 0).
4524 */
LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef * TIMx)4525 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
4526 {
4527 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4528 }
4529
4530 /**
4531 * @}
4532 */
4533
4534 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4535 * @{
4536 */
4537 /**
4538 * @brief Configures the timer DMA burst feature.
4539 * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4540 * not a timer instance supports the DMA burst mode.
4541 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4542 * DCR DBA LL_TIM_ConfigDMABurst
4543 * @param TIMx Timer instance
4544 * @param DMABurstBaseAddress This parameter can be one of the following values:
4545 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4546 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4547 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4548 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4549 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4550 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4551 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4552 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4553 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4554 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4555 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4556 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4557 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4558 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4559 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4560 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4561 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4562 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4563 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4564 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4565 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4566 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4567 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4568 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4569 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4570 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4571 * @param DMABurstLength This parameter can be one of the following values:
4572 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4573 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4574 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4575 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4576 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4577 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4578 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4579 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4580 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4581 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4582 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4583 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4584 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4585 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4586 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4587 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4588 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4589 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4590 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4591 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4592 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4593 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4594 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4595 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4596 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4597 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4598 * @param DMABurstSource This parameter can be one of the following values:
4599 * @arg @ref LL_TIM_DMA_UPDATE
4600 * @arg @ref LL_TIM_DMA_CC1
4601 * @arg @ref LL_TIM_DMA_CC2
4602 * @arg @ref LL_TIM_DMA_CC3
4603 * @arg @ref LL_TIM_DMA_CC4
4604 * @arg @ref LL_TIM_DMA_COM
4605 * @arg @ref LL_TIM_DMA_TRIGGER
4606 * @retval None
4607 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength,uint32_t DMABurstSource)4608 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
4609 uint32_t DMABurstSource)
4610 {
4611 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
4612 (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
4613 }
4614
4615 /**
4616 * @}
4617 */
4618
4619 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4620 * @{
4621 */
4622
4623 /**
4624 * @brief Enable encoder index.
4625 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4626 * a timer instance provides an index input.
4627 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4628 * @param TIMx Timer instance
4629 * @retval None
4630 */
LL_TIM_EnableEncoderIndex(TIM_TypeDef * TIMx)4631 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4632 {
4633 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4634 }
4635
4636 /**
4637 * @brief Disable encoder index.
4638 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4639 * a timer instance provides an index input.
4640 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4641 * @param TIMx Timer instance
4642 * @retval None
4643 */
LL_TIM_DisableEncoderIndex(TIM_TypeDef * TIMx)4644 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4645 {
4646 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4647 }
4648
4649 /**
4650 * @brief Indicate whether encoder index is enabled.
4651 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4652 * a timer instance provides an index input.
4653 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4654 * @param TIMx Timer instance
4655 * @retval State of bit (1 or 0).
4656 */
LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef * TIMx)4657 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
4658 {
4659 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4660 }
4661
4662 /**
4663 * @brief Set index direction
4664 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4665 * a timer instance provides an index input.
4666 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4667 * @param TIMx Timer instance
4668 * @param IndexDirection This parameter can be one of the following values:
4669 * @arg @ref LL_TIM_INDEX_UP_DOWN
4670 * @arg @ref LL_TIM_INDEX_UP
4671 * @arg @ref LL_TIM_INDEX_DOWN
4672 * @retval None
4673 */
LL_TIM_SetIndexDirection(TIM_TypeDef * TIMx,uint32_t IndexDirection)4674 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4675 {
4676 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4677 }
4678
4679 /**
4680 * @brief Get actual index direction
4681 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4682 * a timer instance provides an index input.
4683 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4684 * @param TIMx Timer instance
4685 * @retval Returned value can be one of the following values:
4686 * @arg @ref LL_TIM_INDEX_UP_DOWN
4687 * @arg @ref LL_TIM_INDEX_UP
4688 * @arg @ref LL_TIM_INDEX_DOWN
4689 */
LL_TIM_GetIndexDirection(const TIM_TypeDef * TIMx)4690 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
4691 {
4692 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4693 }
4694
4695 /**
4696 * @brief Set index blanking
4697 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4698 * a timer instance provides an index input.
4699 * @rmtoll ECR IBLK LL_TIM_SetIndexblanking
4700 * @param TIMx Timer instance
4701 * @param Indexblanking This parameter can be one of the following values:
4702 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4703 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4704 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4705 * @retval None
4706 */
LL_TIM_SetIndexblanking(TIM_TypeDef * TIMx,uint32_t Indexblanking)4707 __STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
4708 {
4709 MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
4710 }
4711
4712 /**
4713 * @brief Get actual index blanking
4714 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4715 * a timer instance provides an index input.
4716 * @rmtoll ECR IBLK LL_TIM_GetIndexblanking
4717 * @param TIMx Timer instance
4718 * @retval Returned value can be one of the following values:
4719 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
4720 * @arg @ref LL_TIM_INDEX_BLANK_TI3
4721 * @arg @ref LL_TIM_INDEX_BLANK_TI4
4722 */
LL_TIM_GetIndexblanking(const TIM_TypeDef * TIMx)4723 __STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
4724 {
4725 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
4726 }
4727
4728
4729 /**
4730 * @brief Enable first index.
4731 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4732 * a timer instance provides an index input.
4733 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4734 * @param TIMx Timer instance
4735 * @retval None
4736 */
LL_TIM_EnableFirstIndex(TIM_TypeDef * TIMx)4737 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4738 {
4739 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
4740 }
4741
4742 /**
4743 * @brief Disable first index.
4744 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4745 * a timer instance provides an index input.
4746 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
4747 * @param TIMx Timer instance
4748 * @retval None
4749 */
LL_TIM_DisableFirstIndex(TIM_TypeDef * TIMx)4750 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
4751 {
4752 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
4753 }
4754
4755 /**
4756 * @brief Indicates whether first index is enabled.
4757 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4758 * a timer instance provides an index input.
4759 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
4760 * @param TIMx Timer instance
4761 * @retval State of bit (1 or 0).
4762 */
LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef * TIMx)4763 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
4764 {
4765 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
4766 }
4767
4768 /**
4769 * @brief Set index positioning
4770 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4771 * a timer instance provides an index input.
4772 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
4773 * @param TIMx Timer instance
4774 * @param IndexPositionning This parameter can be one of the following values:
4775 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4776 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4777 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4778 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4779 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4780 * @arg @ref LL_TIM_INDEX_POSITION_UP
4781 * @retval None
4782 */
LL_TIM_SetIndexPositionning(TIM_TypeDef * TIMx,uint32_t IndexPositionning)4783 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
4784 {
4785 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
4786 }
4787
4788 /**
4789 * @brief Get actual index positioning
4790 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4791 * a timer instance provides an index input.
4792 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
4793 * @param TIMx Timer instance
4794 * @retval Returned value can be one of the following values:
4795 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
4796 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
4797 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
4798 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
4799 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
4800 * @arg @ref LL_TIM_INDEX_POSITION_UP
4801 */
LL_TIM_GetIndexPositionning(const TIM_TypeDef * TIMx)4802 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
4803 {
4804 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
4805 }
4806
4807 /**
4808 * @brief Configure encoder index.
4809 * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4810 * a timer instance provides an index input.
4811 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
4812 * ECR IBLK LL_TIM_ConfigIDX\n
4813 * ECR FIDX LL_TIM_ConfigIDX\n
4814 * ECR IPOS LL_TIM_ConfigIDX
4815 * @param TIMx Timer instance
4816 * @param Configuration This parameter must be a combination of all the following values:
4817 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
4818 * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
4819 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
4820 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
4821 * @retval None
4822 */
LL_TIM_ConfigIDX(TIM_TypeDef * TIMx,uint32_t Configuration)4823 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
4824 {
4825 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
4826 }
4827
4828 /**
4829 * @}
4830 */
4831
4832 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
4833 * @{
4834 */
4835 /**
4836 * @brief Remap TIM inputs (input channel, internal/external triggers).
4837 * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
4838 * a some timer inputs can be remapped.
4839 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
4840 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
4841 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
4842 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
4843 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
4844 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
4845 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
4846 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
4847 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
4848 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
4849 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
4850 * TIM12_TISEL TI1SEL LL_TIM_SetRemap\n
4851 * TIM13_TISEL TI1SEL LL_TIM_SetRemap\n
4852 * TIM14_TISEL TI1SEL LL_TIM_SetRemap\n
4853 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
4854 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
4855 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
4856 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
4857 *
4858 * @param TIMx Timer instance
4859 * @param Remap Remap param depends on the TIMx. Description available only
4860 * in CHM version of the User Manual (not in .pdf).
4861 * Otherwise see Reference Manual description of TISEL registers.
4862 *
4863 * Below description summarizes "Timer Instance" and "Remap" param combinations:
4864 *
4865 * TIM1: one of the following values:
4866 * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO
4867 * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*)
4868 * @arg LL_TIM_TIM1_TI2_RMP_GPIO: TIM1 TI2 is connected to GPIO
4869 * @arg LL_TIM_TIM1_TI3_RMP_GPIO: TIM1 TI3 is connected to GPIO
4870 * @arg LL_TIM_TIM1_TI4_RMP_GPIO: TIM1 TI4 is connected to GPIO
4871 *
4872 * TIM2: one of the following values:
4873 * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO
4874 * @arg LL_TIM_TIM2_TI1_RMP_LSI: TIM2 TI1 is connected to LSI (*)
4875 * @arg LL_TIM_TIM2_TI1_RMP_LSE: TIM2 TI1 is connected to LSE (*)
4876 * @arg LL_TIM_TIM2_TI1_RMP_RTC: TIM2 TI1 is connected to RTC (*)
4877 * @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1: TIM2 TI1 is connected to TIM3 TI1 (*)
4878 * @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS: TIM2 TI1 is connected to ETH PPS (*)
4879 * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO
4880 * @arg LL_TIM_TIM2_TI2_RMP_HSI_1024: TIM2 TI2 is connected to HSI 1024 (*)
4881 * @arg LL_TIM_TIM2_TI2_RMP_CSI_128: TIM2 TI2 is connected to CSI 128 (*)
4882 * @arg LL_TIM_TIM2_TI2_RMP_MCO2: TIM2 TI2 is connected to MCO2 (*)
4883 * @arg LL_TIM_TIM2_TI2_RMP_MCO1: TIM2 TI2 is connected to MCO1 (*)
4884 * @arg LL_TIM_TIM2_TI3_RMP_GPIO: TIM2 TI3 is connected to GPIO
4885 * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO
4886 * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 (*)
4887 *
4888 * TIM3: one of the following values:
4889 * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO
4890 * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*)
4891 * @arg LL_TIM_TIM3_TI1_RMP_MCO1: TIM3 TI1 is connected to MCO1 (*)
4892 * @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1: TIM3 TI1 is connected to TIM2 TI1 (*)
4893 * @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ: TIM3 TI1 is connected to HSE_1MHZ (*)
4894 * @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS: TIM3 TI1 is connected to ETH PPS (*)
4895 * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO
4896 * @arg LL_TIM_TIM3_TI2_RMP_CSI_128: TIM3 TI2 is connected to CSI_128 (*)
4897 * @arg LL_TIM_TIM3_TI2_RMP_MCO2: TIM3 TI2 is connected to MCO2 (*)
4898 * @arg LL_TIM_TIM3_TI2_RMP_HSI_1024: TIM3 TI2 is connected to HSI_1024 (*)
4899 * @arg LL_TIM_TIM3_TI3_RMP_GPIO: TIM3 TI3 is connected to GPIO
4900 * @arg LL_TIM_TIM3_TI4_RMP_GPIO: TIM3 TI4 is connected to GPIO
4901 *
4902 * TIM4: one of the following values: (**)
4903 * @arg LL_TIM_TIM4_TI1_RMP_GPIO: TIM4 TI1 is connected to GPIO
4904 * @arg LL_TIM_TIM4_TI2_RMP_GPIO: TIM4 TI2 is connected to GPIO
4905 * @arg LL_TIM_TIM4_TI3_RMP_GPIO: TIM4 TI3 is connected to GPIO
4906 * @arg LL_TIM_TIM4_TI4_RMP_GPIO: TIM4 TI4 is connected to GPIO
4907 *
4908 * TIM5: one of the following values: (**)
4909 * @arg LL_TIM_TIM5_TI1_RMP_GPIO: TIM5 TI1 is connected to GPIO
4910 * @arg LL_TIM_TIM5_TI2_RMP_GPIO: TIM5 TI2 is connected to GPIO
4911 * @arg LL_TIM_TIM5_TI3_RMP_GPIO: TIM5 TI3 is connected to GPIO
4912 * @arg LL_TIM_TIM5_TI4_RMP_GPIO: TIM5 TI4 is connected to GPIO
4913 *
4914 * TIM8: one of the following values: (**)
4915 * @arg LL_TIM_TIM8_TI1_RMP_GPIO: TIM8 TI1 is connected to GPIO
4916 * @arg LL_TIM_TIM8_TI2_RMP_GPIO: TIM8 TI2 is connected to GPIO
4917 * @arg LL_TIM_TIM8_TI3_RMP_GPIO: TIM8 TI3 is connected to GPIO
4918 * @arg LL_TIM_TIM8_TI4_RMP_GPIO: TIM8 TI4 is connected to GPIO
4919 *
4920 * TIM12: one of the following values: (**)
4921 * @arg LL_TIM_TIM12_TI1_RMP_GPIO: TIM12 TI1 is connected to GPIO
4922 * @arg LL_TIM_TIM12_TI1_RMP_HSI_1024: TIM12 TI1 is connected to GPIO
4923 * @arg LL_TIM_TIM12_TI1_RMP_CSI_128: TIM12 TI1 is connected to GPIO
4924 *
4925 * TIM13: one of the following values: (**)
4926 * @arg LL_TIM_TIM13_TI1_RMP_GPIO: TIM13 TI1 is connected to GPIO
4927 *
4928 * TIM14: one of the following values: (**)
4929 * @arg LL_TIM_TIM14_TI1_RMP_GPIO: TIM14 TI1 is connected to GPIO
4930 *
4931 * TIM15: one of the following values: (**)
4932 * @arg LL_TIM_TIM15_TI1_RMP_GPIO: TIM15 TI1 is connected to GPIO
4933 * @arg LL_TIM_TIM15_TI1_RMP_TIM2: TIM15 TI1 is connected to TIM2
4934 * @arg LL_TIM_TIM15_TI1_RMP_TIM3: TIM15 TI1 is connected to TIM3
4935 * @arg LL_TIM_TIM15_TI1_RMP_TIM4: TIM15 TI1 is connected to TIM4
4936 * @arg LL_TIM_TIM15_TI1_RMP_LSE: TIM15 TI1 is connected to LSE
4937 * @arg LL_TIM_TIM15_TI1_RMP_CSI_128: TIM15 TI1 is connected to CSI/128
4938 * @arg LL_TIM_TIM15_TI1_RMP_MCO2: TIM15 TI1 is connected to MCO2
4939 * @arg LL_TIM_TIM15_TI2_RMP_GPIO: TIM15 TI1 is connected to GPIO
4940 * @arg LL_TIM_TIM15_TI2_RMP_TIM2: TIM15 TI1 is connected to TIM2
4941 * @arg LL_TIM_TIM15_TI2_RMP_TIM3: TIM15 TI1 is connected to TIM3
4942 * @arg LL_TIM_TIM15_TI2_RMP_TIM4: TIM15 TI1 is connected to TIM4
4943 *
4944 * TIM16: one of the following values: (**)
4945 * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO
4946 * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI
4947 * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE
4948 * @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP: TIM16 TI1 is connected to RTC_WKUP
4949 *
4950 * TIM17: one of the following values: (**)
4951 * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO
4952 * @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ: TIM17 TI1 is connected to HSE_1MHZ
4953 * @arg LL_TIM_TIM17_TI1_RMP_MCO1: TIM17 TI1 is connected to MCO1
4954 *
4955 * (*) Value not defined in all devices. \n
4956 * (**) Timer instance not available on all devices. \n
4957 *
4958 * @retval None
4959 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)4960 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
4961 {
4962 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
4963 }
4964
4965 /**
4966 * @}
4967 */
4968
4969 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
4970 * @{
4971 */
4972 /**
4973 * @brief Set the OCREF clear input source
4974 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
4975 * @note This function can only be used in Output compare and PWM modes.
4976 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
4977 * @param TIMx Timer instance
4978 * @param OCRefClearInputSource This parameter can be one of the following values:
4979 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
4980 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
4981 * @retval None
4982 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)4983 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
4984 {
4985 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
4986 }
4987 /**
4988 * @}
4989 */
4990
4991 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
4992 * @{
4993 */
4994 /**
4995 * @brief Clear the update interrupt flag (UIF).
4996 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
4997 * @param TIMx Timer instance
4998 * @retval None
4999 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)5000 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5001 {
5002 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5003 }
5004
5005 /**
5006 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5007 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5008 * @param TIMx Timer instance
5009 * @retval State of bit (1 or 0).
5010 */
LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef * TIMx)5011 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
5012 {
5013 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5014 }
5015
5016 /**
5017 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5018 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5019 * @param TIMx Timer instance
5020 * @retval None
5021 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)5022 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5023 {
5024 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5025 }
5026
5027 /**
5028 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5029 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5030 * @param TIMx Timer instance
5031 * @retval State of bit (1 or 0).
5032 */
LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef * TIMx)5033 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
5034 {
5035 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5036 }
5037
5038 /**
5039 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5040 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5041 * @param TIMx Timer instance
5042 * @retval None
5043 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)5044 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5045 {
5046 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5047 }
5048
5049 /**
5050 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5051 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5052 * @param TIMx Timer instance
5053 * @retval State of bit (1 or 0).
5054 */
LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef * TIMx)5055 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
5056 {
5057 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5058 }
5059
5060 /**
5061 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5062 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5063 * @param TIMx Timer instance
5064 * @retval None
5065 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)5066 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5067 {
5068 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5069 }
5070
5071 /**
5072 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5073 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5074 * @param TIMx Timer instance
5075 * @retval State of bit (1 or 0).
5076 */
LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef * TIMx)5077 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
5078 {
5079 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5080 }
5081
5082 /**
5083 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5084 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5085 * @param TIMx Timer instance
5086 * @retval None
5087 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)5088 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5089 {
5090 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5091 }
5092
5093 /**
5094 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5095 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5096 * @param TIMx Timer instance
5097 * @retval State of bit (1 or 0).
5098 */
LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef * TIMx)5099 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
5100 {
5101 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5102 }
5103
5104 /**
5105 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5106 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5107 * @param TIMx Timer instance
5108 * @retval None
5109 */
LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)5110 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5111 {
5112 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5113 }
5114
5115 /**
5116 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5117 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5118 * @param TIMx Timer instance
5119 * @retval State of bit (1 or 0).
5120 */
LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef * TIMx)5121 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
5122 {
5123 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5124 }
5125
5126 /**
5127 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5128 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5129 * @param TIMx Timer instance
5130 * @retval None
5131 */
LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)5132 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5133 {
5134 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5135 }
5136
5137 /**
5138 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5139 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5140 * @param TIMx Timer instance
5141 * @retval State of bit (1 or 0).
5142 */
LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef * TIMx)5143 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
5144 {
5145 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5146 }
5147
5148 /**
5149 * @brief Clear the commutation interrupt flag (COMIF).
5150 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5151 * @param TIMx Timer instance
5152 * @retval None
5153 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)5154 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5155 {
5156 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5157 }
5158
5159 /**
5160 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5161 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5162 * @param TIMx Timer instance
5163 * @retval State of bit (1 or 0).
5164 */
LL_TIM_IsActiveFlag_COM(const TIM_TypeDef * TIMx)5165 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
5166 {
5167 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5168 }
5169
5170 /**
5171 * @brief Clear the trigger interrupt flag (TIF).
5172 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5173 * @param TIMx Timer instance
5174 * @retval None
5175 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)5176 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5177 {
5178 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5179 }
5180
5181 /**
5182 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5183 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5184 * @param TIMx Timer instance
5185 * @retval State of bit (1 or 0).
5186 */
LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef * TIMx)5187 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
5188 {
5189 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5190 }
5191
5192 /**
5193 * @brief Clear the break interrupt flag (BIF).
5194 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5195 * @param TIMx Timer instance
5196 * @retval None
5197 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)5198 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5199 {
5200 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5201 }
5202
5203 /**
5204 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5205 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5206 * @param TIMx Timer instance
5207 * @retval State of bit (1 or 0).
5208 */
LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef * TIMx)5209 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
5210 {
5211 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5212 }
5213
5214 /**
5215 * @brief Clear the break 2 interrupt flag (B2IF).
5216 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5217 * @param TIMx Timer instance
5218 * @retval None
5219 */
LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)5220 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5221 {
5222 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5223 }
5224
5225 /**
5226 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5227 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5228 * @param TIMx Timer instance
5229 * @retval State of bit (1 or 0).
5230 */
LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef * TIMx)5231 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
5232 {
5233 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5234 }
5235
5236 /**
5237 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5238 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5239 * @param TIMx Timer instance
5240 * @retval None
5241 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)5242 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5243 {
5244 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5245 }
5246
5247 /**
5248 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
5249 * (Capture/Compare 1 interrupt is pending).
5250 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5251 * @param TIMx Timer instance
5252 * @retval State of bit (1 or 0).
5253 */
LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef * TIMx)5254 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
5255 {
5256 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5257 }
5258
5259 /**
5260 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5261 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5262 * @param TIMx Timer instance
5263 * @retval None
5264 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)5265 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5266 {
5267 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5268 }
5269
5270 /**
5271 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
5272 * (Capture/Compare 2 over-capture interrupt is pending).
5273 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5274 * @param TIMx Timer instance
5275 * @retval State of bit (1 or 0).
5276 */
LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef * TIMx)5277 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
5278 {
5279 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5280 }
5281
5282 /**
5283 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5284 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5285 * @param TIMx Timer instance
5286 * @retval None
5287 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)5288 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5289 {
5290 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5291 }
5292
5293 /**
5294 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
5295 * (Capture/Compare 3 over-capture interrupt is pending).
5296 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5297 * @param TIMx Timer instance
5298 * @retval State of bit (1 or 0).
5299 */
LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef * TIMx)5300 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
5301 {
5302 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5303 }
5304
5305 /**
5306 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5307 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5308 * @param TIMx Timer instance
5309 * @retval None
5310 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)5311 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5312 {
5313 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5314 }
5315
5316 /**
5317 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
5318 * (Capture/Compare 4 over-capture interrupt is pending).
5319 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5320 * @param TIMx Timer instance
5321 * @retval State of bit (1 or 0).
5322 */
LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef * TIMx)5323 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
5324 {
5325 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5326 }
5327
5328 /**
5329 * @brief Clear the system break interrupt flag (SBIF).
5330 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5331 * @param TIMx Timer instance
5332 * @retval None
5333 */
LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)5334 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5335 {
5336 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5337 }
5338
5339 /**
5340 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5341 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5342 * @param TIMx Timer instance
5343 * @retval State of bit (1 or 0).
5344 */
LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef * TIMx)5345 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
5346 {
5347 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5348 }
5349
5350 /**
5351 * @brief Clear the transition error interrupt flag (TERRF).
5352 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5353 * a timer instance provides encoder error management.
5354 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5355 * @param TIMx Timer instance
5356 * @retval None
5357 */
LL_TIM_ClearFlag_TERR(TIM_TypeDef * TIMx)5358 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5359 {
5360 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5361 }
5362
5363 /**
5364 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5365 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5366 * a timer instance provides encoder error management.
5367 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5368 * @param TIMx Timer instance
5369 * @retval State of bit (1 or 0).
5370 */
LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef * TIMx)5371 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
5372 {
5373 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5374 }
5375
5376 /**
5377 * @brief Clear the index error interrupt flag (IERRF).
5378 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5379 * a timer instance provides encoder error management.
5380 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5381 * @param TIMx Timer instance
5382 * @retval None
5383 */
LL_TIM_ClearFlag_IERR(TIM_TypeDef * TIMx)5384 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5385 {
5386 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5387 }
5388
5389 /**
5390 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5391 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5392 * a timer instance provides encoder error management.
5393 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5394 * @param TIMx Timer instance
5395 * @retval State of bit (1 or 0).
5396 */
LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef * TIMx)5397 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
5398 {
5399 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5400 }
5401
5402 /**
5403 * @brief Clear the direction change interrupt flag (DIRF).
5404 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5405 * a timer instance provides encoder interrupt management.
5406 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5407 * @param TIMx Timer instance
5408 * @retval None
5409 */
LL_TIM_ClearFlag_DIR(TIM_TypeDef * TIMx)5410 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5411 {
5412 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5413 }
5414
5415 /**
5416 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5417 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5418 * a timer instance provides encoder interrupt management.
5419 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5420 * @param TIMx Timer instance
5421 * @retval State of bit (1 or 0).
5422 */
LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef * TIMx)5423 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
5424 {
5425 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5426 }
5427
5428 /**
5429 * @brief Clear the index interrupt flag (IDXF).
5430 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5431 * a timer instance provides encoder interrupt management.
5432 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5433 * @param TIMx Timer instance
5434 * @retval None
5435 */
LL_TIM_ClearFlag_IDX(TIM_TypeDef * TIMx)5436 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5437 {
5438 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5439 }
5440
5441 /**
5442 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5443 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5444 * a timer instance provides encoder interrupt management.
5445 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5446 * @param TIMx Timer instance
5447 * @retval State of bit (1 or 0).
5448 */
LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef * TIMx)5449 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
5450 {
5451 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5452 }
5453 /**
5454 * @}
5455 */
5456
5457 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5458 * @{
5459 */
5460 /**
5461 * @brief Enable update interrupt (UIE).
5462 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5463 * @param TIMx Timer instance
5464 * @retval None
5465 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)5466 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5467 {
5468 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5469 }
5470
5471 /**
5472 * @brief Disable update interrupt (UIE).
5473 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5474 * @param TIMx Timer instance
5475 * @retval None
5476 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)5477 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5478 {
5479 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5480 }
5481
5482 /**
5483 * @brief Indicates whether the update interrupt (UIE) is enabled.
5484 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5485 * @param TIMx Timer instance
5486 * @retval State of bit (1 or 0).
5487 */
LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef * TIMx)5488 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
5489 {
5490 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5491 }
5492
5493 /**
5494 * @brief Enable capture/compare 1 interrupt (CC1IE).
5495 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5496 * @param TIMx Timer instance
5497 * @retval None
5498 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)5499 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5500 {
5501 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5502 }
5503
5504 /**
5505 * @brief Disable capture/compare 1 interrupt (CC1IE).
5506 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5507 * @param TIMx Timer instance
5508 * @retval None
5509 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)5510 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5511 {
5512 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5513 }
5514
5515 /**
5516 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5517 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5518 * @param TIMx Timer instance
5519 * @retval State of bit (1 or 0).
5520 */
LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef * TIMx)5521 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
5522 {
5523 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5524 }
5525
5526 /**
5527 * @brief Enable capture/compare 2 interrupt (CC2IE).
5528 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5529 * @param TIMx Timer instance
5530 * @retval None
5531 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)5532 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5533 {
5534 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5535 }
5536
5537 /**
5538 * @brief Disable capture/compare 2 interrupt (CC2IE).
5539 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5540 * @param TIMx Timer instance
5541 * @retval None
5542 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)5543 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5544 {
5545 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5546 }
5547
5548 /**
5549 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5550 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5551 * @param TIMx Timer instance
5552 * @retval State of bit (1 or 0).
5553 */
LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef * TIMx)5554 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
5555 {
5556 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5557 }
5558
5559 /**
5560 * @brief Enable capture/compare 3 interrupt (CC3IE).
5561 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5562 * @param TIMx Timer instance
5563 * @retval None
5564 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)5565 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5566 {
5567 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5568 }
5569
5570 /**
5571 * @brief Disable capture/compare 3 interrupt (CC3IE).
5572 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5573 * @param TIMx Timer instance
5574 * @retval None
5575 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)5576 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5577 {
5578 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5579 }
5580
5581 /**
5582 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5583 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5584 * @param TIMx Timer instance
5585 * @retval State of bit (1 or 0).
5586 */
LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef * TIMx)5587 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
5588 {
5589 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5590 }
5591
5592 /**
5593 * @brief Enable capture/compare 4 interrupt (CC4IE).
5594 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5595 * @param TIMx Timer instance
5596 * @retval None
5597 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)5598 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5599 {
5600 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5601 }
5602
5603 /**
5604 * @brief Disable capture/compare 4 interrupt (CC4IE).
5605 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5606 * @param TIMx Timer instance
5607 * @retval None
5608 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)5609 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5610 {
5611 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5612 }
5613
5614 /**
5615 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
5616 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
5617 * @param TIMx Timer instance
5618 * @retval State of bit (1 or 0).
5619 */
LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef * TIMx)5620 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
5621 {
5622 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
5623 }
5624
5625 /**
5626 * @brief Enable commutation interrupt (COMIE).
5627 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
5628 * @param TIMx Timer instance
5629 * @retval None
5630 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)5631 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
5632 {
5633 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
5634 }
5635
5636 /**
5637 * @brief Disable commutation interrupt (COMIE).
5638 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
5639 * @param TIMx Timer instance
5640 * @retval None
5641 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)5642 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
5643 {
5644 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
5645 }
5646
5647 /**
5648 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
5649 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
5650 * @param TIMx Timer instance
5651 * @retval State of bit (1 or 0).
5652 */
LL_TIM_IsEnabledIT_COM(const TIM_TypeDef * TIMx)5653 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
5654 {
5655 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
5656 }
5657
5658 /**
5659 * @brief Enable trigger interrupt (TIE).
5660 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
5661 * @param TIMx Timer instance
5662 * @retval None
5663 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)5664 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
5665 {
5666 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
5667 }
5668
5669 /**
5670 * @brief Disable trigger interrupt (TIE).
5671 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
5672 * @param TIMx Timer instance
5673 * @retval None
5674 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)5675 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
5676 {
5677 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
5678 }
5679
5680 /**
5681 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
5682 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
5683 * @param TIMx Timer instance
5684 * @retval State of bit (1 or 0).
5685 */
LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef * TIMx)5686 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
5687 {
5688 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
5689 }
5690
5691 /**
5692 * @brief Enable break interrupt (BIE).
5693 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
5694 * @param TIMx Timer instance
5695 * @retval None
5696 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)5697 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
5698 {
5699 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
5700 }
5701
5702 /**
5703 * @brief Disable break interrupt (BIE).
5704 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
5705 * @param TIMx Timer instance
5706 * @retval None
5707 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)5708 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
5709 {
5710 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
5711 }
5712
5713 /**
5714 * @brief Indicates whether the break interrupt (BIE) is enabled.
5715 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
5716 * @param TIMx Timer instance
5717 * @retval State of bit (1 or 0).
5718 */
LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef * TIMx)5719 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
5720 {
5721 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
5722 }
5723
5724 /**
5725 * @brief Enable transition error interrupt (TERRIE).
5726 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5727 * a timer instance provides encoder error management.
5728 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
5729 * @param TIMx Timer instance
5730 * @retval None
5731 */
LL_TIM_EnableIT_TERR(TIM_TypeDef * TIMx)5732 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
5733 {
5734 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5735 }
5736
5737 /**
5738 * @brief Disable transition error interrupt (TERRIE).
5739 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5740 * a timer instance provides encoder error management.
5741 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
5742 * @param TIMx Timer instance
5743 * @retval None
5744 */
LL_TIM_DisableIT_TERR(TIM_TypeDef * TIMx)5745 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
5746 {
5747 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
5748 }
5749
5750 /**
5751 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
5752 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5753 * a timer instance provides encoder error management.
5754 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
5755 * @param TIMx Timer instance
5756 * @retval State of bit (1 or 0).
5757 */
LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef * TIMx)5758 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
5759 {
5760 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
5761 }
5762
5763 /**
5764 * @brief Enable index error interrupt (IERRIE).
5765 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5766 * a timer instance provides encoder error management.
5767 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
5768 * @param TIMx Timer instance
5769 * @retval None
5770 */
LL_TIM_EnableIT_IERR(TIM_TypeDef * TIMx)5771 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
5772 {
5773 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5774 }
5775
5776 /**
5777 * @brief Disable index error interrupt (IERRIE).
5778 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5779 * a timer instance provides encoder error management.
5780 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
5781 * @param TIMx Timer instance
5782 * @retval None
5783 */
LL_TIM_DisableIT_IERR(TIM_TypeDef * TIMx)5784 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
5785 {
5786 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
5787 }
5788
5789 /**
5790 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
5791 * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5792 * a timer instance provides encoder error management.
5793 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
5794 * @param TIMx Timer instance
5795 * @retval State of bit (1 or 0).
5796 */
LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef * TIMx)5797 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
5798 {
5799 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
5800 }
5801
5802 /**
5803 * @brief Enable direction change interrupt (DIRIE).
5804 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5805 * a timer instance provides encoder interrupt management.
5806 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
5807 * @param TIMx Timer instance
5808 * @retval None
5809 */
LL_TIM_EnableIT_DIR(TIM_TypeDef * TIMx)5810 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
5811 {
5812 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5813 }
5814
5815 /**
5816 * @brief Disable direction change interrupt (DIRIE).
5817 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5818 * a timer instance provides encoder interrupt management.
5819 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
5820 * @param TIMx Timer instance
5821 * @retval None
5822 */
LL_TIM_DisableIT_DIR(TIM_TypeDef * TIMx)5823 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
5824 {
5825 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
5826 }
5827
5828 /**
5829 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
5830 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5831 * a timer instance provides encoder interrupt management.
5832 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
5833 * @param TIMx Timer instance
5834 * @retval State of bit (1 or 0).
5835 */
LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef * TIMx)5836 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
5837 {
5838 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
5839 }
5840
5841 /**
5842 * @brief Enable index interrupt (IDXIE).
5843 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5844 * a timer instance provides encoder interrupt management.
5845 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
5846 * @param TIMx Timer instance
5847 * @retval None
5848 */
LL_TIM_EnableIT_IDX(TIM_TypeDef * TIMx)5849 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
5850 {
5851 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5852 }
5853
5854 /**
5855 * @brief Disable index interrupt (IDXIE).
5856 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5857 * a timer instance provides encoder interrupt management.
5858 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
5859 * @param TIMx Timer instance
5860 * @retval None
5861 */
LL_TIM_DisableIT_IDX(TIM_TypeDef * TIMx)5862 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
5863 {
5864 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
5865 }
5866
5867 /**
5868 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
5869 * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5870 * a timer instance provides encoder interrupt management.
5871 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
5872 * @param TIMx Timer instance
5873 * @retval State of bit (1 or 0).
5874 */
LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef * TIMx)5875 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
5876 {
5877 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
5878 }
5879
5880 /**
5881 * @}
5882 */
5883
5884 /** @defgroup TIM_LL_EF_DMA_Management DMA Management
5885 * @{
5886 */
5887 /**
5888 * @brief Enable update DMA request (UDE).
5889 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
5890 * @param TIMx Timer instance
5891 * @retval None
5892 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)5893 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5894 {
5895 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
5896 }
5897
5898 /**
5899 * @brief Disable update DMA request (UDE).
5900 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
5901 * @param TIMx Timer instance
5902 * @retval None
5903 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)5904 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
5905 {
5906 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
5907 }
5908
5909 /**
5910 * @brief Indicates whether the update DMA request (UDE) is enabled.
5911 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
5912 * @param TIMx Timer instance
5913 * @retval State of bit (1 or 0).
5914 */
LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef * TIMx)5915 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
5916 {
5917 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
5918 }
5919
5920 /**
5921 * @brief Enable capture/compare 1 DMA request (CC1DE).
5922 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
5923 * @param TIMx Timer instance
5924 * @retval None
5925 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)5926 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
5927 {
5928 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5929 }
5930
5931 /**
5932 * @brief Disable capture/compare 1 DMA request (CC1DE).
5933 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
5934 * @param TIMx Timer instance
5935 * @retval None
5936 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)5937 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
5938 {
5939 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
5940 }
5941
5942 /**
5943 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
5944 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
5945 * @param TIMx Timer instance
5946 * @retval State of bit (1 or 0).
5947 */
LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef * TIMx)5948 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
5949 {
5950 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
5951 }
5952
5953 /**
5954 * @brief Enable capture/compare 2 DMA request (CC2DE).
5955 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
5956 * @param TIMx Timer instance
5957 * @retval None
5958 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)5959 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
5960 {
5961 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5962 }
5963
5964 /**
5965 * @brief Disable capture/compare 2 DMA request (CC2DE).
5966 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
5967 * @param TIMx Timer instance
5968 * @retval None
5969 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)5970 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
5971 {
5972 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
5973 }
5974
5975 /**
5976 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
5977 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
5978 * @param TIMx Timer instance
5979 * @retval State of bit (1 or 0).
5980 */
LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef * TIMx)5981 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
5982 {
5983 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
5984 }
5985
5986 /**
5987 * @brief Enable capture/compare 3 DMA request (CC3DE).
5988 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
5989 * @param TIMx Timer instance
5990 * @retval None
5991 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)5992 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
5993 {
5994 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
5995 }
5996
5997 /**
5998 * @brief Disable capture/compare 3 DMA request (CC3DE).
5999 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6000 * @param TIMx Timer instance
6001 * @retval None
6002 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)6003 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6004 {
6005 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6006 }
6007
6008 /**
6009 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6010 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6011 * @param TIMx Timer instance
6012 * @retval State of bit (1 or 0).
6013 */
LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef * TIMx)6014 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
6015 {
6016 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6017 }
6018
6019 /**
6020 * @brief Enable capture/compare 4 DMA request (CC4DE).
6021 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6022 * @param TIMx Timer instance
6023 * @retval None
6024 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)6025 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6026 {
6027 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6028 }
6029
6030 /**
6031 * @brief Disable capture/compare 4 DMA request (CC4DE).
6032 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6033 * @param TIMx Timer instance
6034 * @retval None
6035 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)6036 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6037 {
6038 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6039 }
6040
6041 /**
6042 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6043 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6044 * @param TIMx Timer instance
6045 * @retval State of bit (1 or 0).
6046 */
LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef * TIMx)6047 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
6048 {
6049 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6050 }
6051
6052 /**
6053 * @brief Enable commutation DMA request (COMDE).
6054 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6055 * @param TIMx Timer instance
6056 * @retval None
6057 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)6058 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6059 {
6060 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6061 }
6062
6063 /**
6064 * @brief Disable commutation DMA request (COMDE).
6065 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6066 * @param TIMx Timer instance
6067 * @retval None
6068 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)6069 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6070 {
6071 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6072 }
6073
6074 /**
6075 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6076 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6077 * @param TIMx Timer instance
6078 * @retval State of bit (1 or 0).
6079 */
LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef * TIMx)6080 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
6081 {
6082 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6083 }
6084
6085 /**
6086 * @brief Enable trigger interrupt (TDE).
6087 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6088 * @param TIMx Timer instance
6089 * @retval None
6090 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)6091 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6092 {
6093 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6094 }
6095
6096 /**
6097 * @brief Disable trigger interrupt (TDE).
6098 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6099 * @param TIMx Timer instance
6100 * @retval None
6101 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)6102 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6103 {
6104 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6105 }
6106
6107 /**
6108 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6109 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6110 * @param TIMx Timer instance
6111 * @retval State of bit (1 or 0).
6112 */
LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef * TIMx)6113 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
6114 {
6115 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6116 }
6117
6118 /**
6119 * @}
6120 */
6121
6122 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6123 * @{
6124 */
6125 /**
6126 * @brief Generate an update event.
6127 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6128 * @param TIMx Timer instance
6129 * @retval None
6130 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)6131 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6132 {
6133 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6134 }
6135
6136 /**
6137 * @brief Generate Capture/Compare 1 event.
6138 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6139 * @param TIMx Timer instance
6140 * @retval None
6141 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)6142 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6143 {
6144 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6145 }
6146
6147 /**
6148 * @brief Generate Capture/Compare 2 event.
6149 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6150 * @param TIMx Timer instance
6151 * @retval None
6152 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)6153 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6154 {
6155 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6156 }
6157
6158 /**
6159 * @brief Generate Capture/Compare 3 event.
6160 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6161 * @param TIMx Timer instance
6162 * @retval None
6163 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)6164 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6165 {
6166 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6167 }
6168
6169 /**
6170 * @brief Generate Capture/Compare 4 event.
6171 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6172 * @param TIMx Timer instance
6173 * @retval None
6174 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)6175 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6176 {
6177 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6178 }
6179
6180 /**
6181 * @brief Generate commutation event.
6182 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6183 * @param TIMx Timer instance
6184 * @retval None
6185 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)6186 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6187 {
6188 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6189 }
6190
6191 /**
6192 * @brief Generate trigger event.
6193 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6194 * @param TIMx Timer instance
6195 * @retval None
6196 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)6197 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6198 {
6199 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6200 }
6201
6202 /**
6203 * @brief Generate break event.
6204 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6205 * @param TIMx Timer instance
6206 * @retval None
6207 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)6208 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6209 {
6210 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6211 }
6212
6213 /**
6214 * @brief Generate break 2 event.
6215 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6216 * @param TIMx Timer instance
6217 * @retval None
6218 */
LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)6219 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6220 {
6221 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6222 }
6223
6224 /**
6225 * @}
6226 */
6227
6228 #if defined(USE_FULL_LL_DRIVER)
6229 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6230 * @{
6231 */
6232
6233 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
6234 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6235 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
6236 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6237 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6238 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6239 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6240 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6241 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6242 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6243 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6244 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6245 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6246 /**
6247 * @}
6248 */
6249 #endif /* USE_FULL_LL_DRIVER */
6250
6251 /**
6252 * @}
6253 */
6254
6255 /**
6256 * @}
6257 */
6258
6259 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
6260
6261 /**
6262 * @}
6263 */
6264
6265 #ifdef __cplusplus
6266 }
6267 #endif
6268
6269 #endif /* __STM32H5xx_LL_TIM_H */
6270
