1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_LL_SPI_H
21 #define STM32G4xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx.h"
29
30 /** @addtogroup STM32G4xx_LL_Driver
31 * @{
32 */
33
34 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43
44 /* Exported types ------------------------------------------------------------*/
45 #if defined(USE_FULL_LL_DRIVER)
46 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
47 * @{
48 */
49
50 /**
51 * @brief SPI Init structures definition
52 */
53 typedef struct
54 {
55 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
56 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
57
58 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
59
60 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
61 This parameter can be a value of @ref SPI_LL_EC_MODE.
62
63 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
64
65 uint32_t DataWidth; /*!< Specifies the SPI data width.
66 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
67
68 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
69
70 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
71 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
72
73 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
74
75 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
76 This parameter can be a value of @ref SPI_LL_EC_PHASE.
77
78 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
79
80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
81 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
82
83 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
84
85 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
86 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
87 @note The communication clock is derived from the master clock. The slave clock does not need to be set.
88
89 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
90
91 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
92 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
93
94 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
95
96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
97 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
98
99 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
100
101 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
103
104 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
105
106 } LL_SPI_InitTypeDef;
107
108 /**
109 * @}
110 */
111 #endif /* USE_FULL_LL_DRIVER */
112
113 /* Exported constants --------------------------------------------------------*/
114 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
115 * @{
116 */
117
118 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
119 * @brief Flags defines which can be used with LL_SPI_ReadReg function
120 * @{
121 */
122 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
123 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
124 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
125 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
126 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
127 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
128 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
129 /**
130 * @}
131 */
132
133 /** @defgroup SPI_LL_EC_IT IT Defines
134 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
135 * @{
136 */
137 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
138 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
139 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
140 /**
141 * @}
142 */
143
144 /** @defgroup SPI_LL_EC_MODE Operation Mode
145 * @{
146 */
147 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
148 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
149 /**
150 * @}
151 */
152
153 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
154 * @{
155 */
156 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
157 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
158 /**
159 * @}
160 */
161
162 /** @defgroup SPI_LL_EC_PHASE Clock Phase
163 * @{
164 */
165 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
166 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
167 /**
168 * @}
169 */
170
171 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
172 * @{
173 */
174 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
175 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
176 /**
177 * @}
178 */
179
180 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
181 * @{
182 */
183 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
184 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
185 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
186 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
187 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
188 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
189 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
190 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
191 /**
192 * @}
193 */
194
195 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
196 * @{
197 */
198 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
199 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
200 /**
201 * @}
202 */
203
204 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
205 * @{
206 */
207 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
208 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
209 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
210 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
211 /**
212 * @}
213 */
214
215 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
216 * @{
217 */
218 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
219 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
220 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
221 /**
222 * @}
223 */
224
225 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
226 * @{
227 */
228 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
229 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
230 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
231 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
232 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
233 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
234 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
235 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
236 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
237 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
238 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
239 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
240 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
241 /**
242 * @}
243 */
244 #if defined(USE_FULL_LL_DRIVER)
245
246 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
247 * @{
248 */
249 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
250 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
251 /**
252 * @}
253 */
254 #endif /* USE_FULL_LL_DRIVER */
255
256 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
257 * @{
258 */
259 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
260 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
261 /**
262 * @}
263 */
264
265 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
266 * @{
267 */
268 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
269 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
270 /**
271 * @}
272 */
273
274 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
275 * @{
276 */
277 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
278 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
279 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
280 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
281 /**
282 * @}
283 */
284
285 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
286 * @{
287 */
288 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
289 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
290 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
291 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
292 /**
293 * @}
294 */
295
296 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
297 * @{
298 */
299 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
300 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
301
302 /**
303 * @}
304 */
305
306 /**
307 * @}
308 */
309
310 /* Exported macro ------------------------------------------------------------*/
311 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
312 * @{
313 */
314
315 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
316 * @{
317 */
318
319 /**
320 * @brief Write a value in SPI register
321 * @param __INSTANCE__ SPI Instance
322 * @param __REG__ Register to be written
323 * @param __VALUE__ Value to be written in the register
324 * @retval None
325 */
326 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
327
328 /**
329 * @brief Read a value in SPI register
330 * @param __INSTANCE__ SPI Instance
331 * @param __REG__ Register to be read
332 * @retval Register value
333 */
334 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
335 /**
336 * @}
337 */
338
339 /**
340 * @}
341 */
342
343 /* Exported functions --------------------------------------------------------*/
344 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
345 * @{
346 */
347
348 /** @defgroup SPI_LL_EF_Configuration Configuration
349 * @{
350 */
351
352 /**
353 * @brief Enable SPI peripheral
354 * @rmtoll CR1 SPE LL_SPI_Enable
355 * @param SPIx SPI Instance
356 * @retval None
357 */
LL_SPI_Enable(SPI_TypeDef * SPIx)358 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
359 {
360 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
361 }
362
363 /**
364 * @brief Disable SPI peripheral
365 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
366 * @rmtoll CR1 SPE LL_SPI_Disable
367 * @param SPIx SPI Instance
368 * @retval None
369 */
LL_SPI_Disable(SPI_TypeDef * SPIx)370 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
371 {
372 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
373 }
374
375 /**
376 * @brief Check if SPI peripheral is enabled
377 * @rmtoll CR1 SPE LL_SPI_IsEnabled
378 * @param SPIx SPI Instance
379 * @retval State of bit (1 or 0).
380 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)381 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
382 {
383 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
384 }
385
386 /**
387 * @brief Set SPI operation mode to Master or Slave
388 * @note This bit should not be changed when communication is ongoing.
389 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
390 * CR1 SSI LL_SPI_SetMode
391 * @param SPIx SPI Instance
392 * @param Mode This parameter can be one of the following values:
393 * @arg @ref LL_SPI_MODE_MASTER
394 * @arg @ref LL_SPI_MODE_SLAVE
395 * @retval None
396 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)397 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
398 {
399 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
400 }
401
402 /**
403 * @brief Get SPI operation mode (Master or Slave)
404 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
405 * CR1 SSI LL_SPI_GetMode
406 * @param SPIx SPI Instance
407 * @retval Returned value can be one of the following values:
408 * @arg @ref LL_SPI_MODE_MASTER
409 * @arg @ref LL_SPI_MODE_SLAVE
410 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)411 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
412 {
413 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
414 }
415
416 /**
417 * @brief Set serial protocol used
418 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
419 * @rmtoll CR2 FRF LL_SPI_SetStandard
420 * @param SPIx SPI Instance
421 * @param Standard This parameter can be one of the following values:
422 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
423 * @arg @ref LL_SPI_PROTOCOL_TI
424 * @retval None
425 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)426 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
427 {
428 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
429 }
430
431 /**
432 * @brief Get serial protocol used
433 * @rmtoll CR2 FRF LL_SPI_GetStandard
434 * @param SPIx SPI Instance
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
437 * @arg @ref LL_SPI_PROTOCOL_TI
438 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)439 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
440 {
441 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
442 }
443
444 /**
445 * @brief Set clock phase
446 * @note This bit should not be changed when communication is ongoing.
447 * This bit is not used in SPI TI mode.
448 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
449 * @param SPIx SPI Instance
450 * @param ClockPhase This parameter can be one of the following values:
451 * @arg @ref LL_SPI_PHASE_1EDGE
452 * @arg @ref LL_SPI_PHASE_2EDGE
453 * @retval None
454 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)455 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
456 {
457 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
458 }
459
460 /**
461 * @brief Get clock phase
462 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
463 * @param SPIx SPI Instance
464 * @retval Returned value can be one of the following values:
465 * @arg @ref LL_SPI_PHASE_1EDGE
466 * @arg @ref LL_SPI_PHASE_2EDGE
467 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)468 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
469 {
470 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
471 }
472
473 /**
474 * @brief Set clock polarity
475 * @note This bit should not be changed when communication is ongoing.
476 * This bit is not used in SPI TI mode.
477 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
478 * @param SPIx SPI Instance
479 * @param ClockPolarity This parameter can be one of the following values:
480 * @arg @ref LL_SPI_POLARITY_LOW
481 * @arg @ref LL_SPI_POLARITY_HIGH
482 * @retval None
483 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)484 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
485 {
486 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
487 }
488
489 /**
490 * @brief Get clock polarity
491 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
492 * @param SPIx SPI Instance
493 * @retval Returned value can be one of the following values:
494 * @arg @ref LL_SPI_POLARITY_LOW
495 * @arg @ref LL_SPI_POLARITY_HIGH
496 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)497 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
498 {
499 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
500 }
501
502 /**
503 * @brief Set baud rate prescaler
504 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
505 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
506 * @param SPIx SPI Instance
507 * @param BaudRate This parameter can be one of the following values:
508 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
509 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
510 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
511 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
512 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
513 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
514 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
515 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
516 * @retval None
517 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t BaudRate)518 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
519 {
520 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
521 }
522
523 /**
524 * @brief Get baud rate prescaler
525 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
526 * @param SPIx SPI Instance
527 * @retval Returned value can be one of the following values:
528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
533 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
534 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
535 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
536 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)537 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
538 {
539 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
540 }
541
542 /**
543 * @brief Set transfer bit order
544 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
545 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
546 * @param SPIx SPI Instance
547 * @param BitOrder This parameter can be one of the following values:
548 * @arg @ref LL_SPI_LSB_FIRST
549 * @arg @ref LL_SPI_MSB_FIRST
550 * @retval None
551 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)552 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
553 {
554 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
555 }
556
557 /**
558 * @brief Get transfer bit order
559 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
560 * @param SPIx SPI Instance
561 * @retval Returned value can be one of the following values:
562 * @arg @ref LL_SPI_LSB_FIRST
563 * @arg @ref LL_SPI_MSB_FIRST
564 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)565 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
566 {
567 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
568 }
569
570 /**
571 * @brief Set transfer direction mode
572 * @note For Half-Duplex mode, Rx Direction is set by default.
573 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
574 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
575 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
576 * CR1 BIDIOE LL_SPI_SetTransferDirection
577 * @param SPIx SPI Instance
578 * @param TransferDirection This parameter can be one of the following values:
579 * @arg @ref LL_SPI_FULL_DUPLEX
580 * @arg @ref LL_SPI_SIMPLEX_RX
581 * @arg @ref LL_SPI_HALF_DUPLEX_RX
582 * @arg @ref LL_SPI_HALF_DUPLEX_TX
583 * @retval None
584 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)585 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
586 {
587 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
588 }
589
590 /**
591 * @brief Get transfer direction mode
592 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
593 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
594 * CR1 BIDIOE LL_SPI_GetTransferDirection
595 * @param SPIx SPI Instance
596 * @retval Returned value can be one of the following values:
597 * @arg @ref LL_SPI_FULL_DUPLEX
598 * @arg @ref LL_SPI_SIMPLEX_RX
599 * @arg @ref LL_SPI_HALF_DUPLEX_RX
600 * @arg @ref LL_SPI_HALF_DUPLEX_TX
601 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)602 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
603 {
604 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
605 }
606
607 /**
608 * @brief Set frame data width
609 * @rmtoll CR2 DS LL_SPI_SetDataWidth
610 * @param SPIx SPI Instance
611 * @param DataWidth This parameter can be one of the following values:
612 * @arg @ref LL_SPI_DATAWIDTH_4BIT
613 * @arg @ref LL_SPI_DATAWIDTH_5BIT
614 * @arg @ref LL_SPI_DATAWIDTH_6BIT
615 * @arg @ref LL_SPI_DATAWIDTH_7BIT
616 * @arg @ref LL_SPI_DATAWIDTH_8BIT
617 * @arg @ref LL_SPI_DATAWIDTH_9BIT
618 * @arg @ref LL_SPI_DATAWIDTH_10BIT
619 * @arg @ref LL_SPI_DATAWIDTH_11BIT
620 * @arg @ref LL_SPI_DATAWIDTH_12BIT
621 * @arg @ref LL_SPI_DATAWIDTH_13BIT
622 * @arg @ref LL_SPI_DATAWIDTH_14BIT
623 * @arg @ref LL_SPI_DATAWIDTH_15BIT
624 * @arg @ref LL_SPI_DATAWIDTH_16BIT
625 * @retval None
626 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)627 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
628 {
629 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
630 }
631
632 /**
633 * @brief Get frame data width
634 * @rmtoll CR2 DS LL_SPI_GetDataWidth
635 * @param SPIx SPI Instance
636 * @retval Returned value can be one of the following values:
637 * @arg @ref LL_SPI_DATAWIDTH_4BIT
638 * @arg @ref LL_SPI_DATAWIDTH_5BIT
639 * @arg @ref LL_SPI_DATAWIDTH_6BIT
640 * @arg @ref LL_SPI_DATAWIDTH_7BIT
641 * @arg @ref LL_SPI_DATAWIDTH_8BIT
642 * @arg @ref LL_SPI_DATAWIDTH_9BIT
643 * @arg @ref LL_SPI_DATAWIDTH_10BIT
644 * @arg @ref LL_SPI_DATAWIDTH_11BIT
645 * @arg @ref LL_SPI_DATAWIDTH_12BIT
646 * @arg @ref LL_SPI_DATAWIDTH_13BIT
647 * @arg @ref LL_SPI_DATAWIDTH_14BIT
648 * @arg @ref LL_SPI_DATAWIDTH_15BIT
649 * @arg @ref LL_SPI_DATAWIDTH_16BIT
650 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)651 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
652 {
653 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
654 }
655
656 /**
657 * @brief Set threshold of RXFIFO that triggers an RXNE event
658 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
659 * @param SPIx SPI Instance
660 * @param Threshold This parameter can be one of the following values:
661 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
662 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
663 * @retval None
664 */
LL_SPI_SetRxFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)665 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
666 {
667 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
668 }
669
670 /**
671 * @brief Get threshold of RXFIFO that triggers an RXNE event
672 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
673 * @param SPIx SPI Instance
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
676 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
677 */
LL_SPI_GetRxFIFOThreshold(SPI_TypeDef * SPIx)678 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
679 {
680 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
681 }
682
683 /**
684 * @}
685 */
686
687 /** @defgroup SPI_LL_EF_CRC_Management CRC Management
688 * @{
689 */
690
691 /**
692 * @brief Enable CRC
693 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
694 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
695 * @param SPIx SPI Instance
696 * @retval None
697 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)698 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
699 {
700 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
701 }
702
703 /**
704 * @brief Disable CRC
705 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
706 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
707 * @param SPIx SPI Instance
708 * @retval None
709 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)710 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
711 {
712 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
713 }
714
715 /**
716 * @brief Check if CRC is enabled
717 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
718 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
719 * @param SPIx SPI Instance
720 * @retval State of bit (1 or 0).
721 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)722 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
723 {
724 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
725 }
726
727 /**
728 * @brief Set CRC Length
729 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
730 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
731 * @param SPIx SPI Instance
732 * @param CRCLength This parameter can be one of the following values:
733 * @arg @ref LL_SPI_CRC_8BIT
734 * @arg @ref LL_SPI_CRC_16BIT
735 * @retval None
736 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)737 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
738 {
739 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
740 }
741
742 /**
743 * @brief Get CRC Length
744 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
745 * @param SPIx SPI Instance
746 * @retval Returned value can be one of the following values:
747 * @arg @ref LL_SPI_CRC_8BIT
748 * @arg @ref LL_SPI_CRC_16BIT
749 */
LL_SPI_GetCRCWidth(SPI_TypeDef * SPIx)750 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
751 {
752 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
753 }
754
755 /**
756 * @brief Set CRCNext to transfer CRC on the line
757 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
758 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
759 * @param SPIx SPI Instance
760 * @retval None
761 */
LL_SPI_SetCRCNext(SPI_TypeDef * SPIx)762 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
763 {
764 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
765 }
766
767 /**
768 * @brief Set polynomial for CRC calculation
769 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
770 * @param SPIx SPI Instance
771 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
772 * @retval None
773 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)774 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
775 {
776 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
777 }
778
779 /**
780 * @brief Get polynomial for CRC calculation
781 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
782 * @param SPIx SPI Instance
783 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
784 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)785 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
786 {
787 return (uint32_t)(READ_REG(SPIx->CRCPR));
788 }
789
790 /**
791 * @brief Get Rx CRC
792 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
793 * @param SPIx SPI Instance
794 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
795 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)796 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
797 {
798 return (uint32_t)(READ_REG(SPIx->RXCRCR));
799 }
800
801 /**
802 * @brief Get Tx CRC
803 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
804 * @param SPIx SPI Instance
805 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
806 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)807 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
808 {
809 return (uint32_t)(READ_REG(SPIx->TXCRCR));
810 }
811
812 /**
813 * @}
814 */
815
816 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
817 * @{
818 */
819
820 /**
821 * @brief Set NSS mode
822 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
823 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
824 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
825 * @param SPIx SPI Instance
826 * @param NSS This parameter can be one of the following values:
827 * @arg @ref LL_SPI_NSS_SOFT
828 * @arg @ref LL_SPI_NSS_HARD_INPUT
829 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
830 * @retval None
831 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)832 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
833 {
834 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
835 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
836 }
837
838 /**
839 * @brief Get NSS mode
840 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
841 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
842 * @param SPIx SPI Instance
843 * @retval Returned value can be one of the following values:
844 * @arg @ref LL_SPI_NSS_SOFT
845 * @arg @ref LL_SPI_NSS_HARD_INPUT
846 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
847 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)848 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
849 {
850 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
851 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
852 return (Ssm | Ssoe);
853 }
854
855 /**
856 * @brief Enable NSS pulse management
857 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
858 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
859 * @param SPIx SPI Instance
860 * @retval None
861 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)862 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
863 {
864 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
865 }
866
867 /**
868 * @brief Disable NSS pulse management
869 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
870 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
871 * @param SPIx SPI Instance
872 * @retval None
873 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)874 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
875 {
876 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
877 }
878
879 /**
880 * @brief Check if NSS pulse is enabled
881 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
882 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
883 * @param SPIx SPI Instance
884 * @retval State of bit (1 or 0).
885 */
LL_SPI_IsEnabledNSSPulse(SPI_TypeDef * SPIx)886 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
887 {
888 return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
889 }
890
891 /**
892 * @}
893 */
894
895 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
896 * @{
897 */
898
899 /**
900 * @brief Check if Rx buffer is not empty
901 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
902 * @param SPIx SPI Instance
903 * @retval State of bit (1 or 0).
904 */
LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)905 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
906 {
907 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
908 }
909
910 /**
911 * @brief Check if Tx buffer is empty
912 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
913 * @param SPIx SPI Instance
914 * @retval State of bit (1 or 0).
915 */
LL_SPI_IsActiveFlag_TXE(SPI_TypeDef * SPIx)916 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
917 {
918 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
919 }
920
921 /**
922 * @brief Get CRC error flag
923 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
924 * @param SPIx SPI Instance
925 * @retval State of bit (1 or 0).
926 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)927 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
928 {
929 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
930 }
931
932 /**
933 * @brief Get mode fault error flag
934 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
935 * @param SPIx SPI Instance
936 * @retval State of bit (1 or 0).
937 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)938 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
939 {
940 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
941 }
942
943 /**
944 * @brief Get overrun error flag
945 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
946 * @param SPIx SPI Instance
947 * @retval State of bit (1 or 0).
948 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)949 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
950 {
951 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
952 }
953
954 /**
955 * @brief Get busy flag
956 * @note The BSY flag is cleared under any one of the following conditions:
957 * -When the SPI is correctly disabled
958 * -When a fault is detected in Master mode (MODF bit set to 1)
959 * -In Master mode, when it finishes a data transmission and no new data is ready to be
960 * sent
961 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
962 * each data transfer.
963 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
964 * @param SPIx SPI Instance
965 * @retval State of bit (1 or 0).
966 */
LL_SPI_IsActiveFlag_BSY(SPI_TypeDef * SPIx)967 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
968 {
969 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
970 }
971
972 /**
973 * @brief Get frame format error flag
974 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
975 * @param SPIx SPI Instance
976 * @retval State of bit (1 or 0).
977 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)978 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
979 {
980 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
981 }
982
983 /**
984 * @brief Get FIFO reception Level
985 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
986 * @param SPIx SPI Instance
987 * @retval Returned value can be one of the following values:
988 * @arg @ref LL_SPI_RX_FIFO_EMPTY
989 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
990 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
991 * @arg @ref LL_SPI_RX_FIFO_FULL
992 */
LL_SPI_GetRxFIFOLevel(SPI_TypeDef * SPIx)993 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
994 {
995 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
996 }
997
998 /**
999 * @brief Get FIFO Transmission Level
1000 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
1001 * @param SPIx SPI Instance
1002 * @retval Returned value can be one of the following values:
1003 * @arg @ref LL_SPI_TX_FIFO_EMPTY
1004 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
1005 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
1006 * @arg @ref LL_SPI_TX_FIFO_FULL
1007 */
LL_SPI_GetTxFIFOLevel(SPI_TypeDef * SPIx)1008 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
1009 {
1010 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
1011 }
1012
1013 /**
1014 * @brief Clear CRC error flag
1015 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
1016 * @param SPIx SPI Instance
1017 * @retval None
1018 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1019 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1020 {
1021 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
1022 }
1023
1024 /**
1025 * @brief Clear mode fault error flag
1026 * @note Clearing this flag is done by a read access to the SPIx_SR
1027 * register followed by a write access to the SPIx_CR1 register
1028 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
1029 * @param SPIx SPI Instance
1030 * @retval None
1031 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1032 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1033 {
1034 __IO uint32_t tmpreg_sr;
1035 tmpreg_sr = SPIx->SR;
1036 (void) tmpreg_sr;
1037 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
1038 }
1039
1040 /**
1041 * @brief Clear overrun error flag
1042 * @note Clearing this flag is done by a read access to the SPIx_DR
1043 * register followed by a read access to the SPIx_SR register
1044 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
1045 * @param SPIx SPI Instance
1046 * @retval None
1047 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1048 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1049 {
1050 __IO uint32_t tmpreg;
1051 tmpreg = SPIx->DR;
1052 (void) tmpreg;
1053 tmpreg = SPIx->SR;
1054 (void) tmpreg;
1055 }
1056
1057 /**
1058 * @brief Clear frame format error flag
1059 * @note Clearing this flag is done by reading SPIx_SR register
1060 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
1061 * @param SPIx SPI Instance
1062 * @retval None
1063 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1064 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1065 {
1066 __IO uint32_t tmpreg;
1067 tmpreg = SPIx->SR;
1068 (void) tmpreg;
1069 }
1070
1071 /**
1072 * @}
1073 */
1074
1075 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management
1076 * @{
1077 */
1078
1079 /**
1080 * @brief Enable error interrupt
1081 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1082 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
1083 * @param SPIx SPI Instance
1084 * @retval None
1085 */
LL_SPI_EnableIT_ERR(SPI_TypeDef * SPIx)1086 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
1087 {
1088 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1089 }
1090
1091 /**
1092 * @brief Enable Rx buffer not empty interrupt
1093 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
1094 * @param SPIx SPI Instance
1095 * @retval None
1096 */
LL_SPI_EnableIT_RXNE(SPI_TypeDef * SPIx)1097 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
1098 {
1099 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1100 }
1101
1102 /**
1103 * @brief Enable Tx buffer empty interrupt
1104 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
1105 * @param SPIx SPI Instance
1106 * @retval None
1107 */
LL_SPI_EnableIT_TXE(SPI_TypeDef * SPIx)1108 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
1109 {
1110 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1111 }
1112
1113 /**
1114 * @brief Disable error interrupt
1115 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
1116 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
1117 * @param SPIx SPI Instance
1118 * @retval None
1119 */
LL_SPI_DisableIT_ERR(SPI_TypeDef * SPIx)1120 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
1121 {
1122 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
1123 }
1124
1125 /**
1126 * @brief Disable Rx buffer not empty interrupt
1127 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
1128 * @param SPIx SPI Instance
1129 * @retval None
1130 */
LL_SPI_DisableIT_RXNE(SPI_TypeDef * SPIx)1131 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
1132 {
1133 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
1134 }
1135
1136 /**
1137 * @brief Disable Tx buffer empty interrupt
1138 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
1139 * @param SPIx SPI Instance
1140 * @retval None
1141 */
LL_SPI_DisableIT_TXE(SPI_TypeDef * SPIx)1142 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
1143 {
1144 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
1145 }
1146
1147 /**
1148 * @brief Check if error interrupt is enabled
1149 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
1150 * @param SPIx SPI Instance
1151 * @retval State of bit (1 or 0).
1152 */
LL_SPI_IsEnabledIT_ERR(SPI_TypeDef * SPIx)1153 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
1154 {
1155 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
1156 }
1157
1158 /**
1159 * @brief Check if Rx buffer not empty interrupt is enabled
1160 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
1161 * @param SPIx SPI Instance
1162 * @retval State of bit (1 or 0).
1163 */
LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)1164 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
1165 {
1166 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
1167 }
1168
1169 /**
1170 * @brief Check if Tx buffer empty interrupt
1171 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
1172 * @param SPIx SPI Instance
1173 * @retval State of bit (1 or 0).
1174 */
LL_SPI_IsEnabledIT_TXE(SPI_TypeDef * SPIx)1175 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
1176 {
1177 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
1178 }
1179
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
1185 * @{
1186 */
1187
1188 /**
1189 * @brief Enable DMA Rx
1190 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
1191 * @param SPIx SPI Instance
1192 * @retval None
1193 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)1194 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1195 {
1196 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1197 }
1198
1199 /**
1200 * @brief Disable DMA Rx
1201 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
1202 * @param SPIx SPI Instance
1203 * @retval None
1204 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)1205 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1206 {
1207 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1208 }
1209
1210 /**
1211 * @brief Check if DMA Rx is enabled
1212 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
1213 * @param SPIx SPI Instance
1214 * @retval State of bit (1 or 0).
1215 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)1216 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
1217 {
1218 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1219 }
1220
1221 /**
1222 * @brief Enable DMA Tx
1223 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
1224 * @param SPIx SPI Instance
1225 * @retval None
1226 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)1227 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1228 {
1229 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1230 }
1231
1232 /**
1233 * @brief Disable DMA Tx
1234 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
1235 * @param SPIx SPI Instance
1236 * @retval None
1237 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)1238 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1239 {
1240 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1241 }
1242
1243 /**
1244 * @brief Check if DMA Tx is enabled
1245 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
1246 * @param SPIx SPI Instance
1247 * @retval State of bit (1 or 0).
1248 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)1249 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
1250 {
1251 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1252 }
1253
1254 /**
1255 * @brief Set parity of Last DMA reception
1256 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
1257 * @param SPIx SPI Instance
1258 * @param Parity This parameter can be one of the following values:
1259 * @arg @ref LL_SPI_DMA_PARITY_ODD
1260 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1261 * @retval None
1262 */
LL_SPI_SetDMAParity_RX(SPI_TypeDef * SPIx,uint32_t Parity)1263 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
1264 {
1265 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
1266 }
1267
1268 /**
1269 * @brief Get parity configuration for Last DMA reception
1270 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
1271 * @param SPIx SPI Instance
1272 * @retval Returned value can be one of the following values:
1273 * @arg @ref LL_SPI_DMA_PARITY_ODD
1274 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1275 */
LL_SPI_GetDMAParity_RX(SPI_TypeDef * SPIx)1276 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
1277 {
1278 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
1279 }
1280
1281 /**
1282 * @brief Set parity of Last DMA transmission
1283 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
1284 * @param SPIx SPI Instance
1285 * @param Parity This parameter can be one of the following values:
1286 * @arg @ref LL_SPI_DMA_PARITY_ODD
1287 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1288 * @retval None
1289 */
LL_SPI_SetDMAParity_TX(SPI_TypeDef * SPIx,uint32_t Parity)1290 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
1291 {
1292 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
1293 }
1294
1295 /**
1296 * @brief Get parity configuration for Last DMA transmission
1297 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
1298 * @param SPIx SPI Instance
1299 * @retval Returned value can be one of the following values:
1300 * @arg @ref LL_SPI_DMA_PARITY_ODD
1301 * @arg @ref LL_SPI_DMA_PARITY_EVEN
1302 */
LL_SPI_GetDMAParity_TX(SPI_TypeDef * SPIx)1303 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
1304 {
1305 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
1306 }
1307
1308 /**
1309 * @brief Get the data register address used for DMA transfer
1310 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
1311 * @param SPIx SPI Instance
1312 * @retval Address of data register
1313 */
LL_SPI_DMA_GetRegAddr(SPI_TypeDef * SPIx)1314 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
1315 {
1316 return (uint32_t) &(SPIx->DR);
1317 }
1318
1319 /**
1320 * @}
1321 */
1322
1323 /** @defgroup SPI_LL_EF_DATA_Management DATA Management
1324 * @{
1325 */
1326
1327 /**
1328 * @brief Read 8-Bits in the data register
1329 * @rmtoll DR DR LL_SPI_ReceiveData8
1330 * @param SPIx SPI Instance
1331 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1332 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)1333 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1334 {
1335 return (*((__IO uint8_t *)&SPIx->DR));
1336 }
1337
1338 /**
1339 * @brief Read 16-Bits in the data register
1340 * @rmtoll DR DR LL_SPI_ReceiveData16
1341 * @param SPIx SPI Instance
1342 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1343 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)1344 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1345 {
1346 return (uint16_t)(READ_REG(SPIx->DR));
1347 }
1348
1349 /**
1350 * @brief Write 8-Bits in the data register
1351 * @rmtoll DR DR LL_SPI_TransmitData8
1352 * @param SPIx SPI Instance
1353 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
1354 * @retval None
1355 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)1356 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1357 {
1358 #if defined (__GNUC__)
1359 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1360 *spidr = TxData;
1361 #else
1362 *((__IO uint8_t *)&SPIx->DR) = TxData;
1363 #endif /* __GNUC__ */
1364 }
1365
1366 /**
1367 * @brief Write 16-Bits in the data register
1368 * @rmtoll DR DR LL_SPI_TransmitData16
1369 * @param SPIx SPI Instance
1370 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
1371 * @retval None
1372 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)1373 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1374 {
1375 #if defined (__GNUC__)
1376 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1377 *spidr = TxData;
1378 #else
1379 SPIx->DR = TxData;
1380 #endif /* __GNUC__ */
1381 }
1382
1383 /**
1384 * @}
1385 */
1386 #if defined(USE_FULL_LL_DRIVER)
1387 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
1388 * @{
1389 */
1390
1391 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
1392 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1393 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1394
1395 /**
1396 * @}
1397 */
1398 #endif /* USE_FULL_LL_DRIVER */
1399 /**
1400 * @}
1401 */
1402
1403 /**
1404 * @}
1405 */
1406
1407 #if defined(SPI_I2S_SUPPORT)
1408 /** @defgroup I2S_LL I2S
1409 * @{
1410 */
1411
1412 /* Private variables ---------------------------------------------------------*/
1413 /* Private constants ---------------------------------------------------------*/
1414 /* Private macros ------------------------------------------------------------*/
1415
1416 /* Exported types ------------------------------------------------------------*/
1417 #if defined(USE_FULL_LL_DRIVER)
1418 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
1419 * @{
1420 */
1421
1422 /**
1423 * @brief I2S Init structure definition
1424 */
1425
1426 typedef struct
1427 {
1428 uint32_t Mode; /*!< Specifies the I2S operating mode.
1429 This parameter can be a value of @ref I2S_LL_EC_MODE
1430
1431 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
1432
1433 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
1434 This parameter can be a value of @ref I2S_LL_EC_STANDARD
1435
1436 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
1437
1438
1439 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
1440 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
1441
1442 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
1443
1444
1445 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
1446 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
1447
1448 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
1449
1450
1451 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
1452 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
1453
1454 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
1455 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
1456
1457
1458 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
1459 This parameter can be a value of @ref I2S_LL_EC_POLARITY
1460
1461 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
1462
1463 } LL_I2S_InitTypeDef;
1464
1465 /**
1466 * @}
1467 */
1468 #endif /*USE_FULL_LL_DRIVER*/
1469
1470 /* Exported constants --------------------------------------------------------*/
1471 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
1472 * @{
1473 */
1474
1475 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
1476 * @brief Flags defines which can be used with LL_I2S_ReadReg function
1477 * @{
1478 */
1479 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
1480 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
1481 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
1482 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
1483 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
1484 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
1485 /**
1486 * @}
1487 */
1488
1489 /** @defgroup SPI_LL_EC_IT IT Defines
1490 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
1491 * @{
1492 */
1493 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
1494 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
1495 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
1496 /**
1497 * @}
1498 */
1499
1500 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1501 * @{
1502 */
1503 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
1504 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
1505 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
1506 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
1507 /**
1508 * @}
1509 */
1510
1511 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
1512 * @{
1513 */
1514 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
1515 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
1516 /**
1517 * @}
1518 */
1519
1520 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
1521 * @{
1522 */
1523 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
1524 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
1525 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
1526 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
1527 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
1528 /**
1529 * @}
1530 */
1531
1532 /** @defgroup I2S_LL_EC_MODE Operation Mode
1533 * @{
1534 */
1535 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
1536 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
1537 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
1538 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
1539 /**
1540 * @}
1541 */
1542
1543 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
1544 * @{
1545 */
1546 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
1547 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
1548 /**
1549 * @}
1550 */
1551
1552 #if defined(USE_FULL_LL_DRIVER)
1553
1554 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
1555 * @{
1556 */
1557 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
1558 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
1559 /**
1560 * @}
1561 */
1562
1563 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
1564 * @{
1565 */
1566
1567 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
1568 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
1569 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
1570 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
1571 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
1572 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
1573 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
1574 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
1575 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
1576 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
1577 /**
1578 * @}
1579 */
1580 #endif /* USE_FULL_LL_DRIVER */
1581
1582 /**
1583 * @}
1584 */
1585
1586 /* Exported macro ------------------------------------------------------------*/
1587 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
1588 * @{
1589 */
1590
1591 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
1592 * @{
1593 */
1594
1595 /**
1596 * @brief Write a value in I2S register
1597 * @param __INSTANCE__ I2S Instance
1598 * @param __REG__ Register to be written
1599 * @param __VALUE__ Value to be written in the register
1600 * @retval None
1601 */
1602 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1603
1604 /**
1605 * @brief Read a value in I2S register
1606 * @param __INSTANCE__ I2S Instance
1607 * @param __REG__ Register to be read
1608 * @retval Register value
1609 */
1610 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1611 /**
1612 * @}
1613 */
1614
1615 /**
1616 * @}
1617 */
1618
1619
1620 /* Exported functions --------------------------------------------------------*/
1621
1622 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
1623 * @{
1624 */
1625
1626 /** @defgroup I2S_LL_EF_Configuration Configuration
1627 * @{
1628 */
1629
1630 /**
1631 * @brief Select I2S mode and Enable I2S peripheral
1632 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
1633 * I2SCFGR I2SE LL_I2S_Enable
1634 * @param SPIx SPI Instance
1635 * @retval None
1636 */
LL_I2S_Enable(SPI_TypeDef * SPIx)1637 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1638 {
1639 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1640 }
1641
1642 /**
1643 * @brief Disable I2S peripheral
1644 * @rmtoll I2SCFGR I2SE LL_I2S_Disable
1645 * @param SPIx SPI Instance
1646 * @retval None
1647 */
LL_I2S_Disable(SPI_TypeDef * SPIx)1648 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1649 {
1650 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1651 }
1652
1653 /**
1654 * @brief Check if I2S peripheral is enabled
1655 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
1656 * @param SPIx SPI Instance
1657 * @retval State of bit (1 or 0).
1658 */
LL_I2S_IsEnabled(SPI_TypeDef * SPIx)1659 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
1660 {
1661 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1662 }
1663
1664 /**
1665 * @brief Set I2S data frame length
1666 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
1667 * I2SCFGR CHLEN LL_I2S_SetDataFormat
1668 * @param SPIx SPI Instance
1669 * @param DataFormat This parameter can be one of the following values:
1670 * @arg @ref LL_I2S_DATAFORMAT_16B
1671 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1672 * @arg @ref LL_I2S_DATAFORMAT_24B
1673 * @arg @ref LL_I2S_DATAFORMAT_32B
1674 * @retval None
1675 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataFormat)1676 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1677 {
1678 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1679 }
1680
1681 /**
1682 * @brief Get I2S data frame length
1683 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
1684 * I2SCFGR CHLEN LL_I2S_GetDataFormat
1685 * @param SPIx SPI Instance
1686 * @retval Returned value can be one of the following values:
1687 * @arg @ref LL_I2S_DATAFORMAT_16B
1688 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
1689 * @arg @ref LL_I2S_DATAFORMAT_24B
1690 * @arg @ref LL_I2S_DATAFORMAT_32B
1691 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)1692 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
1693 {
1694 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1695 }
1696
1697 /**
1698 * @brief Set I2S clock polarity
1699 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
1700 * @param SPIx SPI Instance
1701 * @param ClockPolarity This parameter can be one of the following values:
1702 * @arg @ref LL_I2S_POLARITY_LOW
1703 * @arg @ref LL_I2S_POLARITY_HIGH
1704 * @retval None
1705 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1706 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1707 {
1708 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1709 }
1710
1711 /**
1712 * @brief Get I2S clock polarity
1713 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
1714 * @param SPIx SPI Instance
1715 * @retval Returned value can be one of the following values:
1716 * @arg @ref LL_I2S_POLARITY_LOW
1717 * @arg @ref LL_I2S_POLARITY_HIGH
1718 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)1719 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
1720 {
1721 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1722 }
1723
1724 /**
1725 * @brief Set I2S standard protocol
1726 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
1727 * I2SCFGR PCMSYNC LL_I2S_SetStandard
1728 * @param SPIx SPI Instance
1729 * @param Standard This parameter can be one of the following values:
1730 * @arg @ref LL_I2S_STANDARD_PHILIPS
1731 * @arg @ref LL_I2S_STANDARD_MSB
1732 * @arg @ref LL_I2S_STANDARD_LSB
1733 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1734 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1735 * @retval None
1736 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1737 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1738 {
1739 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1740 }
1741
1742 /**
1743 * @brief Get I2S standard protocol
1744 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
1745 * I2SCFGR PCMSYNC LL_I2S_GetStandard
1746 * @param SPIx SPI Instance
1747 * @retval Returned value can be one of the following values:
1748 * @arg @ref LL_I2S_STANDARD_PHILIPS
1749 * @arg @ref LL_I2S_STANDARD_MSB
1750 * @arg @ref LL_I2S_STANDARD_LSB
1751 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
1752 * @arg @ref LL_I2S_STANDARD_PCM_LONG
1753 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)1754 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
1755 {
1756 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1757 }
1758
1759 /**
1760 * @brief Set I2S transfer mode
1761 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
1762 * @param SPIx SPI Instance
1763 * @param Mode This parameter can be one of the following values:
1764 * @arg @ref LL_I2S_MODE_SLAVE_TX
1765 * @arg @ref LL_I2S_MODE_SLAVE_RX
1766 * @arg @ref LL_I2S_MODE_MASTER_TX
1767 * @arg @ref LL_I2S_MODE_MASTER_RX
1768 * @retval None
1769 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Mode)1770 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1771 {
1772 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1773 }
1774
1775 /**
1776 * @brief Get I2S transfer mode
1777 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
1778 * @param SPIx SPI Instance
1779 * @retval Returned value can be one of the following values:
1780 * @arg @ref LL_I2S_MODE_SLAVE_TX
1781 * @arg @ref LL_I2S_MODE_SLAVE_RX
1782 * @arg @ref LL_I2S_MODE_MASTER_TX
1783 * @arg @ref LL_I2S_MODE_MASTER_RX
1784 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)1785 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
1786 {
1787 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1788 }
1789
1790 /**
1791 * @brief Set I2S linear prescaler
1792 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
1793 * @param SPIx SPI Instance
1794 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1795 * @retval None
1796 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint8_t PrescalerLinear)1797 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1798 {
1799 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1800 }
1801
1802 /**
1803 * @brief Get I2S linear prescaler
1804 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
1805 * @param SPIx SPI Instance
1806 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
1807 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)1808 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
1809 {
1810 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1811 }
1812
1813 /**
1814 * @brief Set I2S parity prescaler
1815 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
1816 * @param SPIx SPI Instance
1817 * @param PrescalerParity This parameter can be one of the following values:
1818 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1819 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1820 * @retval None
1821 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)1822 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1823 {
1824 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1825 }
1826
1827 /**
1828 * @brief Get I2S parity prescaler
1829 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
1830 * @param SPIx SPI Instance
1831 * @retval Returned value can be one of the following values:
1832 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
1833 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
1834 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)1835 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
1836 {
1837 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1838 }
1839
1840 /**
1841 * @brief Enable the master clock output (Pin MCK)
1842 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1843 * @param SPIx SPI Instance
1844 * @retval None
1845 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)1846 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1847 {
1848 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1849 }
1850
1851 /**
1852 * @brief Disable the master clock output (Pin MCK)
1853 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1854 * @param SPIx SPI Instance
1855 * @retval None
1856 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)1857 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1858 {
1859 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1860 }
1861
1862 /**
1863 * @brief Check if the master clock output (Pin MCK) is enabled
1864 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1865 * @param SPIx SPI Instance
1866 * @retval State of bit (1 or 0).
1867 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)1868 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
1869 {
1870 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1871 }
1872
1873 #if defined(SPI_I2SCFGR_ASTRTEN)
1874 /**
1875 * @brief Enable asynchronous start
1876 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
1877 * @param SPIx SPI Instance
1878 * @retval None
1879 */
LL_I2S_EnableAsyncStart(SPI_TypeDef * SPIx)1880 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1881 {
1882 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1883 }
1884
1885 /**
1886 * @brief Disable asynchronous start
1887 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
1888 * @param SPIx SPI Instance
1889 * @retval None
1890 */
LL_I2S_DisableAsyncStart(SPI_TypeDef * SPIx)1891 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1892 {
1893 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1894 }
1895
1896 /**
1897 * @brief Check if asynchronous start is enabled
1898 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
1899 * @param SPIx SPI Instance
1900 * @retval State of bit (1 or 0).
1901 */
LL_I2S_IsEnabledAsyncStart(SPI_TypeDef * SPIx)1902 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
1903 {
1904 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
1905 }
1906 #endif /* SPI_I2SCFGR_ASTRTEN */
1907
1908 /**
1909 * @}
1910 */
1911
1912 /** @defgroup I2S_LL_EF_FLAG FLAG Management
1913 * @{
1914 */
1915
1916 /**
1917 * @brief Check if Rx buffer is not empty
1918 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
1919 * @param SPIx SPI Instance
1920 * @retval State of bit (1 or 0).
1921 */
LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef * SPIx)1922 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
1923 {
1924 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1925 }
1926
1927 /**
1928 * @brief Check if Tx buffer is empty
1929 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
1930 * @param SPIx SPI Instance
1931 * @retval State of bit (1 or 0).
1932 */
LL_I2S_IsActiveFlag_TXE(SPI_TypeDef * SPIx)1933 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
1934 {
1935 return LL_SPI_IsActiveFlag_TXE(SPIx);
1936 }
1937
1938 /**
1939 * @brief Get busy flag
1940 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
1941 * @param SPIx SPI Instance
1942 * @retval State of bit (1 or 0).
1943 */
LL_I2S_IsActiveFlag_BSY(SPI_TypeDef * SPIx)1944 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
1945 {
1946 return LL_SPI_IsActiveFlag_BSY(SPIx);
1947 }
1948
1949 /**
1950 * @brief Get overrun error flag
1951 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
1952 * @param SPIx SPI Instance
1953 * @retval State of bit (1 or 0).
1954 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1955 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1956 {
1957 return LL_SPI_IsActiveFlag_OVR(SPIx);
1958 }
1959
1960 /**
1961 * @brief Get underrun error flag
1962 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
1963 * @param SPIx SPI Instance
1964 * @retval State of bit (1 or 0).
1965 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1966 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1967 {
1968 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1969 }
1970
1971 /**
1972 * @brief Get frame format error flag
1973 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
1974 * @param SPIx SPI Instance
1975 * @retval State of bit (1 or 0).
1976 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1977 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1978 {
1979 return LL_SPI_IsActiveFlag_FRE(SPIx);
1980 }
1981
1982 /**
1983 * @brief Get channel side flag.
1984 * @note 0: Channel Left has to be transmitted or has been received\n
1985 * 1: Channel Right has to be transmitted or has been received\n
1986 * It has no significance in PCM mode.
1987 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
1988 * @param SPIx SPI Instance
1989 * @retval State of bit (1 or 0).
1990 */
LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef * SPIx)1991 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
1992 {
1993 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1994 }
1995
1996 /**
1997 * @brief Clear overrun error flag
1998 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
1999 * @param SPIx SPI Instance
2000 * @retval None
2001 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)2002 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
2003 {
2004 LL_SPI_ClearFlag_OVR(SPIx);
2005 }
2006
2007 /**
2008 * @brief Clear underrun error flag
2009 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
2010 * @param SPIx SPI Instance
2011 * @retval None
2012 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)2013 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
2014 {
2015 __IO uint32_t tmpreg;
2016 tmpreg = SPIx->SR;
2017 (void)tmpreg;
2018 }
2019
2020 /**
2021 * @brief Clear frame format error flag
2022 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE
2023 * @param SPIx SPI Instance
2024 * @retval None
2025 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)2026 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
2027 {
2028 LL_SPI_ClearFlag_FRE(SPIx);
2029 }
2030
2031 /**
2032 * @}
2033 */
2034
2035 /** @defgroup I2S_LL_EF_IT Interrupt Management
2036 * @{
2037 */
2038
2039 /**
2040 * @brief Enable error IT
2041 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
2042 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
2043 * @param SPIx SPI Instance
2044 * @retval None
2045 */
LL_I2S_EnableIT_ERR(SPI_TypeDef * SPIx)2046 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
2047 {
2048 LL_SPI_EnableIT_ERR(SPIx);
2049 }
2050
2051 /**
2052 * @brief Enable Rx buffer not empty IT
2053 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
2054 * @param SPIx SPI Instance
2055 * @retval None
2056 */
LL_I2S_EnableIT_RXNE(SPI_TypeDef * SPIx)2057 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
2058 {
2059 LL_SPI_EnableIT_RXNE(SPIx);
2060 }
2061
2062 /**
2063 * @brief Enable Tx buffer empty IT
2064 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
2065 * @param SPIx SPI Instance
2066 * @retval None
2067 */
LL_I2S_EnableIT_TXE(SPI_TypeDef * SPIx)2068 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
2069 {
2070 LL_SPI_EnableIT_TXE(SPIx);
2071 }
2072
2073 /**
2074 * @brief Disable error IT
2075 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
2076 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
2077 * @param SPIx SPI Instance
2078 * @retval None
2079 */
LL_I2S_DisableIT_ERR(SPI_TypeDef * SPIx)2080 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
2081 {
2082 LL_SPI_DisableIT_ERR(SPIx);
2083 }
2084
2085 /**
2086 * @brief Disable Rx buffer not empty IT
2087 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
2088 * @param SPIx SPI Instance
2089 * @retval None
2090 */
LL_I2S_DisableIT_RXNE(SPI_TypeDef * SPIx)2091 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
2092 {
2093 LL_SPI_DisableIT_RXNE(SPIx);
2094 }
2095
2096 /**
2097 * @brief Disable Tx buffer empty IT
2098 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
2099 * @param SPIx SPI Instance
2100 * @retval None
2101 */
LL_I2S_DisableIT_TXE(SPI_TypeDef * SPIx)2102 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
2103 {
2104 LL_SPI_DisableIT_TXE(SPIx);
2105 }
2106
2107 /**
2108 * @brief Check if ERR IT is enabled
2109 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
2110 * @param SPIx SPI Instance
2111 * @retval State of bit (1 or 0).
2112 */
LL_I2S_IsEnabledIT_ERR(SPI_TypeDef * SPIx)2113 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
2114 {
2115 return LL_SPI_IsEnabledIT_ERR(SPIx);
2116 }
2117
2118 /**
2119 * @brief Check if RXNE IT is enabled
2120 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
2121 * @param SPIx SPI Instance
2122 * @retval State of bit (1 or 0).
2123 */
LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef * SPIx)2124 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
2125 {
2126 return LL_SPI_IsEnabledIT_RXNE(SPIx);
2127 }
2128
2129 /**
2130 * @brief Check if TXE IT is enabled
2131 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
2132 * @param SPIx SPI Instance
2133 * @retval State of bit (1 or 0).
2134 */
LL_I2S_IsEnabledIT_TXE(SPI_TypeDef * SPIx)2135 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
2136 {
2137 return LL_SPI_IsEnabledIT_TXE(SPIx);
2138 }
2139
2140 /**
2141 * @}
2142 */
2143
2144 /** @defgroup I2S_LL_EF_DMA DMA Management
2145 * @{
2146 */
2147
2148 /**
2149 * @brief Enable DMA Rx
2150 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
2151 * @param SPIx SPI Instance
2152 * @retval None
2153 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)2154 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2155 {
2156 LL_SPI_EnableDMAReq_RX(SPIx);
2157 }
2158
2159 /**
2160 * @brief Disable DMA Rx
2161 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
2162 * @param SPIx SPI Instance
2163 * @retval None
2164 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)2165 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2166 {
2167 LL_SPI_DisableDMAReq_RX(SPIx);
2168 }
2169
2170 /**
2171 * @brief Check if DMA Rx is enabled
2172 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
2173 * @param SPIx SPI Instance
2174 * @retval State of bit (1 or 0).
2175 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)2176 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2177 {
2178 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
2179 }
2180
2181 /**
2182 * @brief Enable DMA Tx
2183 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
2184 * @param SPIx SPI Instance
2185 * @retval None
2186 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)2187 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2188 {
2189 LL_SPI_EnableDMAReq_TX(SPIx);
2190 }
2191
2192 /**
2193 * @brief Disable DMA Tx
2194 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
2195 * @param SPIx SPI Instance
2196 * @retval None
2197 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)2198 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2199 {
2200 LL_SPI_DisableDMAReq_TX(SPIx);
2201 }
2202
2203 /**
2204 * @brief Check if DMA Tx is enabled
2205 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
2206 * @param SPIx SPI Instance
2207 * @retval State of bit (1 or 0).
2208 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)2209 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2210 {
2211 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
2212 }
2213
2214 /**
2215 * @}
2216 */
2217
2218 /** @defgroup I2S_LL_EF_DATA DATA Management
2219 * @{
2220 */
2221
2222 /**
2223 * @brief Read 16-Bits in data register
2224 * @rmtoll DR DR LL_I2S_ReceiveData16
2225 * @param SPIx SPI Instance
2226 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
2227 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)2228 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
2229 {
2230 return LL_SPI_ReceiveData16(SPIx);
2231 }
2232
2233 /**
2234 * @brief Write 16-Bits in data register
2235 * @rmtoll DR DR LL_I2S_TransmitData16
2236 * @param SPIx SPI Instance
2237 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
2238 * @retval None
2239 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2240 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2241 {
2242 LL_SPI_TransmitData16(SPIx, TxData);
2243 }
2244
2245 /**
2246 * @}
2247 */
2248
2249 #if defined(USE_FULL_LL_DRIVER)
2250 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
2251 * @{
2252 */
2253
2254 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
2255 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
2256 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
2257 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2258
2259 /**
2260 * @}
2261 */
2262 #endif /* USE_FULL_LL_DRIVER */
2263
2264 /**
2265 * @}
2266 */
2267
2268 /**
2269 * @}
2270 */
2271 #endif /* SPI_I2S_SUPPORT */
2272
2273 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
2274
2275 /**
2276 * @}
2277 */
2278
2279 #ifdef __cplusplus
2280 }
2281 #endif
2282
2283 #endif /* STM32G4xx_LL_SPI_H */
2284
2285
