1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_tim.h 4 * @author MCD Application Team 5 * @brief Header file of TIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_TIM_H 21 #define STM32G4xx_HAL_TIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 /** @addtogroup STM32G4xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup TIM 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 /** @defgroup TIM_Exported_Types TIM Exported Types 40 * @{ 41 */ 42 43 /** 44 * @brief TIM Time base Configuration Structure definition 45 */ 46 typedef struct 47 { 48 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 49 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 50 Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ 51 52 uint32_t CounterMode; /*!< Specifies the counter mode. 53 This parameter can be a value of @ref TIM_Counter_Mode */ 54 55 uint32_t Period; /*!< Specifies the period value to be loaded into the active 56 Auto-Reload Register at the next update event. 57 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 58 (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), 59 __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), 60 __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ 61 62 uint32_t ClockDivision; /*!< Specifies the clock division. 63 This parameter can be a value of @ref TIM_ClockDivision */ 64 65 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 66 reaches zero, an update event is generated and counting restarts 67 from the RCR value (N). 68 This means in PWM mode that (N+1) corresponds to: 69 - the number of PWM periods in edge-aligned mode 70 - the number of half PWM period in center-aligned mode 71 GP timers: this parameter must be a number between Min_Data = 0x00 and 72 Max_Data = 0xFF. 73 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and 74 Max_Data = 0xFFFF. */ 75 76 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. 77 This parameter can be a value of @ref TIM_AutoReloadPreload */ 78 } TIM_Base_InitTypeDef; 79 80 /** 81 * @brief TIM Output Compare Configuration Structure definition 82 */ 83 typedef struct 84 { 85 uint32_t OCMode; /*!< Specifies the TIM mode. 86 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 87 88 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 89 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 90 (or 0xFFEF if dithering is activated) 91 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 92 Pulse value */ 93 94 uint32_t OCPolarity; /*!< Specifies the output polarity. 95 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 96 97 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 98 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 99 @note This parameter is valid only for timer instances supporting break feature. */ 100 101 uint32_t OCFastMode; /*!< Specifies the Fast mode state. 102 This parameter can be a value of @ref TIM_Output_Fast_State 103 @note This parameter is valid only in PWM1 and PWM2 mode. */ 104 105 106 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 107 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 108 @note This parameter is valid only for timer instances supporting break feature. */ 109 110 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 111 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 112 @note This parameter is valid only for timer instances supporting break feature. */ 113 } TIM_OC_InitTypeDef; 114 115 /** 116 * @brief TIM One Pulse Mode Configuration Structure definition 117 */ 118 typedef struct 119 { 120 uint32_t OCMode; /*!< Specifies the TIM mode. 121 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 122 123 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 124 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF 125 (or 0xFFEF if dithering is activated) 126 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate 127 Pulse value */ 128 129 uint32_t OCPolarity; /*!< Specifies the output polarity. 130 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 131 132 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 133 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 134 @note This parameter is valid only for timer instances supporting break feature. */ 135 136 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 137 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 138 @note This parameter is valid only for timer instances supporting break feature. */ 139 140 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 141 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 142 @note This parameter is valid only for timer instances supporting break feature. */ 143 144 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 145 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 146 147 uint32_t ICSelection; /*!< Specifies the input. 148 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 149 150 uint32_t ICFilter; /*!< Specifies the input capture filter. 151 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 152 } TIM_OnePulse_InitTypeDef; 153 154 /** 155 * @brief TIM Input Capture Configuration Structure definition 156 */ 157 typedef struct 158 { 159 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 160 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 161 162 uint32_t ICSelection; /*!< Specifies the input. 163 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 164 165 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 166 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 167 168 uint32_t ICFilter; /*!< Specifies the input capture filter. 169 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 170 } TIM_IC_InitTypeDef; 171 172 /** 173 * @brief TIM Encoder Configuration Structure definition 174 */ 175 typedef struct 176 { 177 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. 178 This parameter can be a value of @ref TIM_Encoder_Mode */ 179 180 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 181 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 182 183 uint32_t IC1Selection; /*!< Specifies the input. 184 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 185 186 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 187 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 188 189 uint32_t IC1Filter; /*!< Specifies the input capture filter. 190 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 191 192 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. 193 This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ 194 195 uint32_t IC2Selection; /*!< Specifies the input. 196 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 197 198 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. 199 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 200 201 uint32_t IC2Filter; /*!< Specifies the input capture filter. 202 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 203 } TIM_Encoder_InitTypeDef; 204 205 /** 206 * @brief Clock Configuration Handle Structure definition 207 */ 208 typedef struct 209 { 210 uint32_t ClockSource; /*!< TIM clock sources 211 This parameter can be a value of @ref TIM_Clock_Source */ 212 uint32_t ClockPolarity; /*!< TIM clock polarity 213 This parameter can be a value of @ref TIM_Clock_Polarity */ 214 uint32_t ClockPrescaler; /*!< TIM clock prescaler 215 This parameter can be a value of @ref TIM_Clock_Prescaler */ 216 uint32_t ClockFilter; /*!< TIM clock filter 217 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 218 } TIM_ClockConfigTypeDef; 219 220 /** 221 * @brief TIM Clear Input Configuration Handle Structure definition 222 */ 223 typedef struct 224 { 225 uint32_t ClearInputState; /*!< TIM clear Input state 226 This parameter can be ENABLE or DISABLE */ 227 uint32_t ClearInputSource; /*!< TIM clear Input sources 228 This parameter can be a value of @ref TIM_ClearInput_Source */ 229 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity 230 This parameter can be a value of @ref TIM_ClearInput_Polarity */ 231 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler 232 This parameter must be 0: When OCRef clear feature is used with ETR source, 233 ETR prescaler must be off */ 234 uint32_t ClearInputFilter; /*!< TIM Clear Input filter 235 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 236 } TIM_ClearInputConfigTypeDef; 237 238 /** 239 * @brief TIM Master configuration Structure definition 240 * @note Advanced timers provide TRGO2 internal line which is redirected 241 * to the ADC 242 */ 243 typedef struct 244 { 245 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection 246 This parameter can be a value of @ref TIM_Master_Mode_Selection */ 247 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection 248 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ 249 uint32_t MasterSlaveMode; /*!< Master/slave mode selection 250 This parameter can be a value of @ref TIM_Master_Slave_Mode 251 @note When the Master/slave mode is enabled, the effect of 252 an event on the trigger input (TRGI) is delayed to allow a 253 perfect synchronization between the current timer and its 254 slaves (through TRGO). It is not mandatory in case of timer 255 synchronization mode. */ 256 } TIM_MasterConfigTypeDef; 257 258 /** 259 * @brief TIM Slave configuration Structure definition 260 */ 261 typedef struct 262 { 263 uint32_t SlaveMode; /*!< Slave mode selection 264 This parameter can be a value of @ref TIM_Slave_Mode */ 265 uint32_t InputTrigger; /*!< Input Trigger source 266 This parameter can be a value of @ref TIM_Trigger_Selection */ 267 uint32_t TriggerPolarity; /*!< Input Trigger polarity 268 This parameter can be a value of @ref TIM_Trigger_Polarity */ 269 uint32_t TriggerPrescaler; /*!< Input trigger prescaler 270 This parameter can be a value of @ref TIM_Trigger_Prescaler */ 271 uint32_t TriggerFilter; /*!< Input trigger filter 272 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 273 274 } TIM_SlaveConfigTypeDef; 275 276 /** 277 * @brief TIM Break input(s) and Dead time configuration Structure definition 278 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable 279 * filter and polarity. 280 */ 281 typedef struct 282 { 283 uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ 284 285 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ 286 287 uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ 288 289 uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 290 291 uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ 292 293 uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ 294 295 uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 296 297 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ 298 299 uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ 300 301 uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ 302 303 uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 304 305 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ 306 307 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 308 309 } TIM_BreakDeadTimeConfigTypeDef; 310 311 /** 312 * @brief HAL State structures definition 313 */ 314 typedef enum 315 { 316 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ 317 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 318 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 319 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 320 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 321 } HAL_TIM_StateTypeDef; 322 323 /** 324 * @brief TIM Channel States definition 325 */ 326 typedef enum 327 { 328 HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ 329 HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ 330 HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ 331 } HAL_TIM_ChannelStateTypeDef; 332 333 /** 334 * @brief DMA Burst States definition 335 */ 336 typedef enum 337 { 338 HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ 339 HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ 340 HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ 341 } HAL_TIM_DMABurstStateTypeDef; 342 343 /** 344 * @brief HAL Active channel structures definition 345 */ 346 typedef enum 347 { 348 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ 349 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ 350 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ 351 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ 352 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ 353 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ 354 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ 355 } HAL_TIM_ActiveChannel; 356 357 /** 358 * @brief TIM Time Base Handle Structure definition 359 */ 360 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 361 typedef struct __TIM_HandleTypeDef 362 #else 363 typedef struct 364 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 365 { 366 TIM_TypeDef *Instance; /*!< Register base address */ 367 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ 368 HAL_TIM_ActiveChannel Channel; /*!< Active channel */ 369 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array 370 This array is accessed by a @ref DMA_Handle_index */ 371 HAL_LockTypeDef Lock; /*!< Locking object */ 372 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ 373 __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ 374 __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ 375 __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ 376 377 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 378 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ 379 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ 380 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ 381 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ 382 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ 383 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ 384 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ 385 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ 386 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ 387 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ 388 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ 389 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ 390 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ 391 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ 392 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ 393 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ 394 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ 395 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ 396 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ 397 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ 398 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ 399 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ 400 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ 401 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ 402 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ 403 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ 404 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ 405 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ 406 void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ 407 void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ 408 void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ 409 void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ 410 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 411 } TIM_HandleTypeDef; 412 413 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 414 /** 415 * @brief HAL TIM Callback ID enumeration definition 416 */ 417 typedef enum 418 { 419 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ 420 , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ 421 , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ 422 , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ 423 , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ 424 , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ 425 , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ 426 , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ 427 , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ 428 , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ 429 , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ 430 , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ 431 , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ 432 , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ 433 , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ 434 , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ 435 , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ 436 , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ 437 438 , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ 439 , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ 440 , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ 441 , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ 442 , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ 443 , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ 444 , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ 445 , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ 446 , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ 447 , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ 448 , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ 449 , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ 450 , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ 451 , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ 452 } HAL_TIM_CallbackIDTypeDef; 453 454 /** 455 * @brief HAL TIM Callback pointer definition 456 */ 457 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ 458 459 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 460 461 /** 462 * @} 463 */ 464 /* End of exported types -----------------------------------------------------*/ 465 466 /* Exported constants --------------------------------------------------------*/ 467 /** @defgroup TIM_Exported_Constants TIM Exported Constants 468 * @{ 469 */ 470 471 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source 472 * @{ 473 */ 474 #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ 475 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ 476 #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ 477 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ 478 #define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */ 479 #define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */ 480 #if defined (COMP5) 481 #define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */ 482 #endif /* COMP5 */ 483 #if defined (COMP6) 484 #define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */ 485 #endif /* COMP6 */ 486 #if defined (COMP7) 487 #define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */ 488 #endif /* COMP7 */ 489 /** 490 * @} 491 */ 492 493 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address 494 * @{ 495 */ 496 #define TIM_DMABASE_CR1 0x00000000U 497 #define TIM_DMABASE_CR2 0x00000001U 498 #define TIM_DMABASE_SMCR 0x00000002U 499 #define TIM_DMABASE_DIER 0x00000003U 500 #define TIM_DMABASE_SR 0x00000004U 501 #define TIM_DMABASE_EGR 0x00000005U 502 #define TIM_DMABASE_CCMR1 0x00000006U 503 #define TIM_DMABASE_CCMR2 0x00000007U 504 #define TIM_DMABASE_CCER 0x00000008U 505 #define TIM_DMABASE_CNT 0x00000009U 506 #define TIM_DMABASE_PSC 0x0000000AU 507 #define TIM_DMABASE_ARR 0x0000000BU 508 #define TIM_DMABASE_RCR 0x0000000CU 509 #define TIM_DMABASE_CCR1 0x0000000DU 510 #define TIM_DMABASE_CCR2 0x0000000EU 511 #define TIM_DMABASE_CCR3 0x0000000FU 512 #define TIM_DMABASE_CCR4 0x00000010U 513 #define TIM_DMABASE_BDTR 0x00000011U 514 #define TIM_DMABASE_CCR5 0x00000012U 515 #define TIM_DMABASE_CCR6 0x00000013U 516 #define TIM_DMABASE_CCMR3 0x00000014U 517 #define TIM_DMABASE_DTR2 0x00000015U 518 #define TIM_DMABASE_ECR 0x00000016U 519 #define TIM_DMABASE_TISEL 0x00000017U 520 #define TIM_DMABASE_AF1 0x00000018U 521 #define TIM_DMABASE_AF2 0x00000019U 522 #define TIM_DMABASE_OR 0x0000001AU 523 /** 524 * @} 525 */ 526 527 /** @defgroup TIM_Event_Source TIM Event Source 528 * @{ 529 */ 530 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ 531 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ 532 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ 533 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ 534 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ 535 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ 536 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ 537 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ 538 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ 539 /** 540 * @} 541 */ 542 543 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity 544 * @{ 545 */ 546 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ 547 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ 548 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ 549 /** 550 * @} 551 */ 552 553 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity 554 * @{ 555 */ 556 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ 557 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler 563 * @{ 564 */ 565 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ 566 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ 567 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ 568 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ 569 /** 570 * @} 571 */ 572 573 /** @defgroup TIM_Counter_Mode TIM Counter Mode 574 * @{ 575 */ 576 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ 577 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ 578 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ 579 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ 580 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ 581 /** 582 * @} 583 */ 584 585 /** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap 586 * @{ 587 */ 588 #define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ 589 #define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ 590 /** 591 * @} 592 */ 593 594 /** @defgroup TIM_ClockDivision TIM Clock Division 595 * @{ 596 */ 597 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ 598 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ 599 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ 600 /** 601 * @} 602 */ 603 604 /** @defgroup TIM_Output_Compare_State TIM Output Compare State 605 * @{ 606 */ 607 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ 608 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ 609 /** 610 * @} 611 */ 612 613 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload 614 * @{ 615 */ 616 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ 617 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ 618 619 /** 620 * @} 621 */ 622 623 /** @defgroup TIM_Output_Fast_State TIM Output Fast State 624 * @{ 625 */ 626 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ 627 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State 633 * @{ 634 */ 635 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ 636 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity 642 * @{ 643 */ 644 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ 645 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ 646 /** 647 * @} 648 */ 649 650 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity 651 * @{ 652 */ 653 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ 654 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State 660 * @{ 661 */ 662 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ 663 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ 664 /** 665 * @} 666 */ 667 668 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State 669 * @{ 670 */ 671 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ 672 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ 673 /** 674 * @} 675 */ 676 677 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity 678 * @{ 679 */ 680 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ 681 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ 682 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ 683 /** 684 * @} 685 */ 686 687 /** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity 688 * @{ 689 */ 690 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ 691 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ 692 /** 693 * @} 694 */ 695 696 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection 697 * @{ 698 */ 699 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ 700 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ 701 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ 702 /** 703 * @} 704 */ 705 706 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler 707 * @{ 708 */ 709 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ 710 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ 711 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ 712 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ 713 /** 714 * @} 715 */ 716 717 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode 718 * @{ 719 */ 720 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ 721 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ 722 /** 723 * @} 724 */ 725 726 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode 727 * @{ 728 */ 729 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ 730 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ 731 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ 732 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ 733 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ 734 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ 735 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ 736 #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ 737 #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ 738 /** 739 * @} 740 */ 741 742 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition 743 * @{ 744 */ 745 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ 746 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ 747 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ 748 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ 749 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ 750 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ 751 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ 752 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ 753 #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ 754 #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ 755 #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ 756 #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ 757 /** 758 * @} 759 */ 760 761 /** @defgroup TIM_Commutation_Source TIM Commutation Source 762 * @{ 763 */ 764 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ 765 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ 766 /** 767 * @} 768 */ 769 770 /** @defgroup TIM_DMA_sources TIM DMA Sources 771 * @{ 772 */ 773 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ 774 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ 775 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ 776 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ 777 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ 778 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ 779 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ 780 /** 781 * @} 782 */ 783 784 /** @defgroup TIM_Flag_definition TIM Flag Definition 785 * @{ 786 */ 787 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ 788 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ 789 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ 790 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ 791 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ 792 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ 793 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ 794 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ 795 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ 796 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ 797 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ 798 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ 799 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ 800 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ 801 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ 802 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ 803 #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ 804 #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ 805 #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ 806 #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ 807 /** 808 * @} 809 */ 810 811 /** @defgroup TIM_Channel TIM Channel 812 * @{ 813 */ 814 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ 815 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ 816 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ 817 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ 818 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ 819 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ 820 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup TIM_Clock_Source TIM Clock Source 826 * @{ 827 */ 828 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ 829 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ 830 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ 831 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ 832 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ 833 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ 834 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ 835 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ 836 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ 837 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ 838 #if defined (TIM5) 839 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ 840 #endif /* TIM5 */ 841 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ 842 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ 843 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ 844 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ 845 #if defined (TIM20) 846 #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ 847 #endif /* TIM20 */ 848 #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ 849 #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity 855 * @{ 856 */ 857 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ 858 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ 859 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ 860 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ 861 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ 862 /** 863 * @} 864 */ 865 866 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler 867 * @{ 868 */ 869 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 870 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ 871 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ 872 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ 873 /** 874 * @} 875 */ 876 877 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity 878 * @{ 879 */ 880 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ 881 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ 882 /** 883 * @} 884 */ 885 886 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler 887 * @{ 888 */ 889 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 890 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ 891 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ 892 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ 893 /** 894 * @} 895 */ 896 897 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state 898 * @{ 899 */ 900 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 901 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 902 /** 903 * @} 904 */ 905 906 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state 907 * @{ 908 */ 909 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ 910 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ 911 /** 912 * @} 913 */ 914 /** @defgroup TIM_Lock_level TIM Lock level 915 * @{ 916 */ 917 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ 918 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 919 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 920 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 921 /** 922 * @} 923 */ 924 925 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable 926 * @{ 927 */ 928 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ 929 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ 930 /** 931 * @} 932 */ 933 934 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity 935 * @{ 936 */ 937 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 938 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 939 /** 940 * @} 941 */ 942 943 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode 944 * @{ 945 */ 946 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ 947 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ 948 /** 949 * @} 950 */ 951 952 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable 953 * @{ 954 */ 955 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ 956 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ 957 /** 958 * @} 959 */ 960 961 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity 962 * @{ 963 */ 964 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 965 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 966 /** 967 * @} 968 */ 969 970 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode 971 * @{ 972 */ 973 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ 974 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ 975 /** 976 * @} 977 */ 978 979 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable 980 * @{ 981 */ 982 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 983 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ 984 /** 985 * @} 986 */ 987 988 /** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 989 * @{ 990 */ 991 #define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 992 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 993 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 994 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 995 /** 996 * @} 997 */ 998 999 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection 1000 * @{ 1001 */ 1002 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ 1003 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ 1004 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ 1005 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ 1006 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ 1007 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ 1008 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ 1009 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ 1010 #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) 1016 * @{ 1017 */ 1018 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ 1019 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ 1020 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ 1021 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ 1022 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ 1023 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ 1024 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ 1025 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ 1026 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ 1027 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ 1028 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ 1029 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ 1030 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ 1031 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ 1032 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1033 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ 1034 /** 1035 * @} 1036 */ 1037 1038 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode 1039 * @{ 1040 */ 1041 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ 1042 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ 1043 /** 1044 * @} 1045 */ 1046 1047 /** @defgroup TIM_Slave_Mode TIM Slave mode 1048 * @{ 1049 */ 1050 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ 1051 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ 1052 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ 1053 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ 1054 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ 1055 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ 1056 #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ 1057 /** 1058 * @} 1059 */ 1060 1061 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes 1062 * @{ 1063 */ 1064 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ 1065 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ 1066 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ 1067 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ 1068 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ 1069 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ 1070 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ 1071 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ 1072 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ 1073 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ 1074 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ 1075 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ 1076 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ 1077 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ 1078 #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ 1079 #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ 1080 /** 1081 * @} 1082 */ 1083 1084 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection 1085 * @{ 1086 */ 1087 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ 1088 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ 1089 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ 1090 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ 1091 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ 1092 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ 1093 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ 1094 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ 1095 #if defined (TIM5) 1096 #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */ 1097 #endif /* TIM5 */ 1098 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ 1099 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ 1100 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ 1101 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ 1102 #if defined (TIM20) 1103 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */ 1104 #endif /* TIM20 */ 1105 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */ 1106 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ 1107 #define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */ 1108 /** 1109 * @} 1110 */ 1111 1112 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity 1113 * @{ 1114 */ 1115 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ 1116 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ 1117 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1118 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1119 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ 1120 /** 1121 * @} 1122 */ 1123 1124 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler 1125 * @{ 1126 */ 1127 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ 1128 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ 1129 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ 1130 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ 1131 /** 1132 * @} 1133 */ 1134 1135 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection 1136 * @{ 1137 */ 1138 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ 1139 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ 1140 /** 1141 * @} 1142 */ 1143 1144 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length 1145 * @{ 1146 */ 1147 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ 1148 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1149 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1150 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1151 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1152 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1153 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1154 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1155 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1156 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1157 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1158 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1159 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1160 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1161 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1162 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1163 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1164 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1165 #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1166 #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1167 #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1168 #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1169 #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1170 #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1171 #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1172 #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup DMA_Handle_index TIM DMA Handle Index 1178 * @{ 1179 */ 1180 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ 1181 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ 1182 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ 1183 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ 1184 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ 1185 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ 1186 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ 1187 /** 1188 * @} 1189 */ 1190 1191 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State 1192 * @{ 1193 */ 1194 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ 1195 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ 1196 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ 1197 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ 1198 /** 1199 * @} 1200 */ 1201 1202 /** @defgroup TIM_Break_System TIM Break System 1203 * @{ 1204 */ 1205 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ 1206 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ 1207 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ 1208 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ 1209 /** 1210 * @} 1211 */ 1212 1213 /** 1214 * @} 1215 */ 1216 /* End of exported constants -------------------------------------------------*/ 1217 1218 /* Exported macros -----------------------------------------------------------*/ 1219 /** @defgroup TIM_Exported_Macros TIM Exported Macros 1220 * @{ 1221 */ 1222 1223 /** @brief Reset TIM handle state. 1224 * @param __HANDLE__ TIM handle. 1225 * @retval None 1226 */ 1227 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 1228 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1229 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1230 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1231 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1232 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1233 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1234 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1235 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1236 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1237 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1238 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1239 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1240 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1241 (__HANDLE__)->Base_MspInitCallback = NULL; \ 1242 (__HANDLE__)->Base_MspDeInitCallback = NULL; \ 1243 (__HANDLE__)->IC_MspInitCallback = NULL; \ 1244 (__HANDLE__)->IC_MspDeInitCallback = NULL; \ 1245 (__HANDLE__)->OC_MspInitCallback = NULL; \ 1246 (__HANDLE__)->OC_MspDeInitCallback = NULL; \ 1247 (__HANDLE__)->PWM_MspInitCallback = NULL; \ 1248 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ 1249 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ 1250 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ 1251 (__HANDLE__)->Encoder_MspInitCallback = NULL; \ 1252 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ 1253 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ 1254 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ 1255 } while(0) 1256 #else 1257 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ 1258 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ 1259 (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1260 (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1261 (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1262 (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1263 (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ 1264 (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ 1265 (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ 1266 (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ 1267 (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ 1268 (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ 1269 (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ 1270 } while(0) 1271 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 1272 1273 /** 1274 * @brief Enable the TIM peripheral. 1275 * @param __HANDLE__ TIM handle 1276 * @retval None 1277 */ 1278 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) 1279 1280 /** 1281 * @brief Enable the TIM main Output. 1282 * @param __HANDLE__ TIM handle 1283 * @retval None 1284 */ 1285 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) 1286 1287 /** 1288 * @brief Disable the TIM peripheral. 1289 * @param __HANDLE__ TIM handle 1290 * @retval None 1291 */ 1292 #define __HAL_TIM_DISABLE(__HANDLE__) \ 1293 do { \ 1294 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1295 { \ 1296 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1297 { \ 1298 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ 1299 } \ 1300 } \ 1301 } while(0) 1302 1303 /** 1304 * @brief Disable the TIM main Output. 1305 * @param __HANDLE__ TIM handle 1306 * @retval None 1307 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been 1308 * disabled 1309 */ 1310 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ 1311 do { \ 1312 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ 1313 { \ 1314 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ 1315 { \ 1316 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ 1317 } \ 1318 } \ 1319 } while(0) 1320 1321 /** 1322 * @brief Disable the TIM main Output. 1323 * @param __HANDLE__ TIM handle 1324 * @retval None 1325 * @note The Main Output Enable of a timer instance is disabled unconditionally 1326 */ 1327 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) 1328 1329 /** @brief Enable the specified TIM interrupt. 1330 * @param __HANDLE__ specifies the TIM Handle. 1331 * @param __INTERRUPT__ specifies the TIM interrupt source to enable. 1332 * This parameter can be one of the following values: 1333 * @arg TIM_IT_UPDATE: Update interrupt 1334 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1335 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1336 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1337 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1338 * @arg TIM_IT_COM: Commutation interrupt 1339 * @arg TIM_IT_TRIGGER: Trigger interrupt 1340 * @arg TIM_IT_BREAK: Break interrupt 1341 * @arg TIM_IT_IDX: Index interrupt 1342 * @arg TIM_IT_DIR: Direction change interrupt 1343 * @arg TIM_IT_IERR: Index error interrupt 1344 * @arg TIM_IT_TERR: Transition error interrupt 1345 * @retval None 1346 */ 1347 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) 1348 1349 /** @brief Disable the specified TIM interrupt. 1350 * @param __HANDLE__ specifies the TIM Handle. 1351 * @param __INTERRUPT__ specifies the TIM interrupt source to disable. 1352 * This parameter can be one of the following values: 1353 * @arg TIM_IT_UPDATE: Update interrupt 1354 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1355 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1356 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1357 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1358 * @arg TIM_IT_COM: Commutation interrupt 1359 * @arg TIM_IT_TRIGGER: Trigger interrupt 1360 * @arg TIM_IT_BREAK: Break interrupt 1361 * @arg TIM_IT_IDX: Index interrupt 1362 * @arg TIM_IT_DIR: Direction change interrupt 1363 * @arg TIM_IT_IERR: Index error interrupt 1364 * @arg TIM_IT_TERR: Transition error interrupt 1365 * @retval None 1366 */ 1367 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 1368 1369 /** @brief Enable the specified DMA request. 1370 * @param __HANDLE__ specifies the TIM Handle. 1371 * @param __DMA__ specifies the TIM DMA request to enable. 1372 * This parameter can be one of the following values: 1373 * @arg TIM_DMA_UPDATE: Update DMA request 1374 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1375 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1376 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1377 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1378 * @arg TIM_DMA_COM: Commutation DMA request 1379 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1380 * @retval None 1381 */ 1382 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) 1383 1384 /** @brief Disable the specified DMA request. 1385 * @param __HANDLE__ specifies the TIM Handle. 1386 * @param __DMA__ specifies the TIM DMA request to disable. 1387 * This parameter can be one of the following values: 1388 * @arg TIM_DMA_UPDATE: Update DMA request 1389 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request 1390 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request 1391 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request 1392 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request 1393 * @arg TIM_DMA_COM: Commutation DMA request 1394 * @arg TIM_DMA_TRIGGER: Trigger DMA request 1395 * @retval None 1396 */ 1397 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) 1398 1399 /** @brief Check whether the specified TIM interrupt flag is set or not. 1400 * @param __HANDLE__ specifies the TIM Handle. 1401 * @param __FLAG__ specifies the TIM interrupt flag to check. 1402 * This parameter can be one of the following values: 1403 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1404 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1405 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1406 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1407 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1408 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1409 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1410 * @arg TIM_FLAG_COM: Commutation interrupt flag 1411 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1412 * @arg TIM_FLAG_BREAK: Break interrupt flag 1413 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1414 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1415 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1416 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1417 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1418 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1419 * @arg TIM_FLAG_IDX: Index interrupt flag 1420 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1421 * @arg TIM_FLAG_IERR: Index error interrupt flag 1422 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1423 * @retval The new state of __FLAG__ (TRUE or FALSE). 1424 */ 1425 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) 1426 1427 /** @brief Clear the specified TIM interrupt flag. 1428 * @param __HANDLE__ specifies the TIM Handle. 1429 * @param __FLAG__ specifies the TIM interrupt flag to clear. 1430 * This parameter can be one of the following values: 1431 * @arg TIM_FLAG_UPDATE: Update interrupt flag 1432 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag 1433 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag 1434 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag 1435 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag 1436 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag 1437 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag 1438 * @arg TIM_FLAG_COM: Commutation interrupt flag 1439 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag 1440 * @arg TIM_FLAG_BREAK: Break interrupt flag 1441 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag 1442 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag 1443 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag 1444 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag 1445 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag 1446 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag 1447 * @arg TIM_FLAG_IDX: Index interrupt flag 1448 * @arg TIM_FLAG_DIR: Direction change interrupt flag 1449 * @arg TIM_FLAG_IERR: Index error interrupt flag 1450 * @arg TIM_FLAG_TERR: Transition error interrupt flag 1451 * @retval The new state of __FLAG__ (TRUE or FALSE). 1452 */ 1453 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) 1454 1455 /** 1456 * @brief Check whether the specified TIM interrupt source is enabled or not. 1457 * @param __HANDLE__ TIM handle 1458 * @param __INTERRUPT__ specifies the TIM interrupt source to check. 1459 * This parameter can be one of the following values: 1460 * @arg TIM_IT_UPDATE: Update interrupt 1461 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1462 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1463 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1464 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1465 * @arg TIM_IT_COM: Commutation interrupt 1466 * @arg TIM_IT_TRIGGER: Trigger interrupt 1467 * @arg TIM_IT_BREAK: Break interrupt 1468 * @arg TIM_IT_IDX: Index interrupt 1469 * @arg TIM_IT_DIR: Direction change interrupt 1470 * @arg TIM_IT_IERR: Index error interrupt 1471 * @arg TIM_IT_TERR: Transition error interrupt 1472 * @retval The state of TIM_IT (SET or RESET). 1473 */ 1474 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ 1475 == (__INTERRUPT__)) ? SET : RESET) 1476 1477 /** @brief Clear the TIM interrupt pending bits. 1478 * @param __HANDLE__ TIM handle 1479 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1480 * This parameter can be one of the following values: 1481 * @arg TIM_IT_UPDATE: Update interrupt 1482 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt 1483 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt 1484 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt 1485 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt 1486 * @arg TIM_IT_COM: Commutation interrupt 1487 * @arg TIM_IT_TRIGGER: Trigger interrupt 1488 * @arg TIM_IT_BREAK: Break interrupt 1489 * @arg TIM_IT_IDX: Index interrupt 1490 * @arg TIM_IT_DIR: Direction change interrupt 1491 * @arg TIM_IT_IERR: Index error interrupt 1492 * @arg TIM_IT_TERR: Transition error interrupt 1493 * @retval None 1494 */ 1495 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) 1496 1497 /** 1498 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 1499 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read 1500 * in an atomic way. 1501 * @param __HANDLE__ TIM handle. 1502 * @retval None 1503 mode. 1504 */ 1505 #define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) 1506 1507 /** 1508 * @brief Disable update interrupt flag (UIF) remapping. 1509 * @param __HANDLE__ TIM handle. 1510 * @retval None 1511 mode. 1512 */ 1513 #define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) 1514 1515 /** 1516 * @brief Get update interrupt flag (UIF) copy status. 1517 * @param __COUNTER__ Counter value. 1518 * @retval The state of UIFCPY (TRUE or FALSE). 1519 mode. 1520 */ 1521 #define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) 1522 1523 /** 1524 * @brief Indicates whether or not the TIM Counter is used as downcounter. 1525 * @param __HANDLE__ TIM handle. 1526 * @retval False (Counter used as upcounter) or True (Counter used as downcounter) 1527 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode 1528 * or Encoder mode. 1529 */ 1530 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) 1531 1532 /** 1533 * @brief Set the TIM Prescaler on runtime. 1534 * @param __HANDLE__ TIM handle. 1535 * @param __PRESC__ specifies the Prescaler new value. 1536 * @retval None 1537 */ 1538 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) 1539 1540 /** 1541 * @brief Set the TIM Counter Register value on runtime. 1542 * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in 1543 * case of 32 bits counter TIM instance. 1544 * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. 1545 * @param __HANDLE__ TIM handle. 1546 * @param __COUNTER__ specifies the Counter register new value. 1547 * @retval None 1548 */ 1549 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) 1550 1551 /** 1552 * @brief Get the TIM Counter Register value on runtime. 1553 * @param __HANDLE__ TIM handle. 1554 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) 1555 */ 1556 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) 1557 1558 /** 1559 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. 1560 * @param __HANDLE__ TIM handle. 1561 * @param __AUTORELOAD__ specifies the Counter register new value. 1562 * @retval None 1563 */ 1564 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ 1565 do{ \ 1566 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ 1567 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ 1568 } while(0) 1569 1570 /** 1571 * @brief Get the TIM Autoreload Register value on runtime. 1572 * @param __HANDLE__ TIM handle. 1573 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) 1574 */ 1575 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) 1576 1577 /** 1578 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. 1579 * @param __HANDLE__ TIM handle. 1580 * @param __CKD__ specifies the clock division value. 1581 * This parameter can be one of the following value: 1582 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1583 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1584 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1585 * @retval None 1586 */ 1587 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ 1588 do{ \ 1589 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ 1590 (__HANDLE__)->Instance->CR1 |= (__CKD__); \ 1591 (__HANDLE__)->Init.ClockDivision = (__CKD__); \ 1592 } while(0) 1593 1594 /** 1595 * @brief Get the TIM Clock Division value on runtime. 1596 * @param __HANDLE__ TIM handle. 1597 * @retval The clock division can be one of the following values: 1598 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT 1599 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT 1600 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT 1601 */ 1602 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) 1603 1604 /** 1605 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() 1606 * function. 1607 * @param __HANDLE__ TIM handle. 1608 * @param __CHANNEL__ TIM Channels to be configured. 1609 * This parameter can be one of the following values: 1610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1614 * @param __ICPSC__ specifies the Input Capture4 prescaler new value. 1615 * This parameter can be one of the following values: 1616 * @arg TIM_ICPSC_DIV1: no prescaler 1617 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1618 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1619 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1620 * @retval None 1621 */ 1622 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ 1623 do{ \ 1624 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ 1625 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ 1626 } while(0) 1627 1628 /** 1629 * @brief Get the TIM Input Capture prescaler on runtime. 1630 * @param __HANDLE__ TIM handle. 1631 * @param __CHANNEL__ TIM Channels to be configured. 1632 * This parameter can be one of the following values: 1633 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value 1634 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value 1635 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value 1636 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value 1637 * @retval The input capture prescaler can be one of the following values: 1638 * @arg TIM_ICPSC_DIV1: no prescaler 1639 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 1640 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 1641 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 1642 */ 1643 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ 1644 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ 1645 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ 1646 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ 1647 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) 1648 1649 /** 1650 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. 1651 * @param __HANDLE__ TIM handle. 1652 * @param __CHANNEL__ TIM Channels to be configured. 1653 * This parameter can be one of the following values: 1654 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1655 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1656 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1657 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1658 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1659 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1660 * @param __COMPARE__ specifies the Capture Compare register new value. 1661 * @retval None 1662 */ 1663 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ 1664 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ 1665 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ 1666 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ 1667 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ 1668 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ 1669 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) 1670 1671 /** 1672 * @brief Get the TIM Capture Compare Register value on runtime. 1673 * @param __HANDLE__ TIM handle. 1674 * @param __CHANNEL__ TIM Channel associated with the capture compare register 1675 * This parameter can be one of the following values: 1676 * @arg TIM_CHANNEL_1: get capture/compare 1 register value 1677 * @arg TIM_CHANNEL_2: get capture/compare 2 register value 1678 * @arg TIM_CHANNEL_3: get capture/compare 3 register value 1679 * @arg TIM_CHANNEL_4: get capture/compare 4 register value 1680 * @arg TIM_CHANNEL_5: get capture/compare 5 register value 1681 * @arg TIM_CHANNEL_6: get capture/compare 6 register value 1682 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) 1683 */ 1684 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ 1685 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ 1686 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ 1687 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ 1688 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ 1689 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ 1690 ((__HANDLE__)->Instance->CCR6)) 1691 1692 /** 1693 * @brief Set the TIM Output compare preload. 1694 * @param __HANDLE__ TIM handle. 1695 * @param __CHANNEL__ TIM Channels to be configured. 1696 * This parameter can be one of the following values: 1697 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1698 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1699 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1700 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1701 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1702 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1703 * @retval None 1704 */ 1705 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1706 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ 1707 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ 1708 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ 1709 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ 1710 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ 1711 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) 1712 1713 /** 1714 * @brief Reset the TIM Output compare preload. 1715 * @param __HANDLE__ TIM handle. 1716 * @param __CHANNEL__ TIM Channels to be configured. 1717 * This parameter can be one of the following values: 1718 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1719 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1720 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1721 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1722 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1723 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1724 * @retval None 1725 */ 1726 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ 1727 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ 1728 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ 1729 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ 1730 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ 1731 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ 1732 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) 1733 1734 /** 1735 * @brief Enable fast mode for a given channel. 1736 * @param __HANDLE__ TIM handle. 1737 * @param __CHANNEL__ TIM Channels to be configured. 1738 * This parameter can be one of the following values: 1739 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1740 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1741 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1742 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1743 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1744 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1745 * @note When fast mode is enabled an active edge on the trigger input acts 1746 * like a compare match on CCx output. Delay to sample the trigger 1747 * input and to activate CCx output is reduced to 3 clock cycles. 1748 * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. 1749 * @retval None 1750 */ 1751 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1752 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ 1753 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ 1754 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ 1755 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ 1756 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ 1757 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) 1758 1759 /** 1760 * @brief Disable fast mode for a given channel. 1761 * @param __HANDLE__ TIM handle. 1762 * @param __CHANNEL__ TIM Channels to be configured. 1763 * This parameter can be one of the following values: 1764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1766 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1767 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1768 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 1769 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 1770 * @note When fast mode is disabled CCx output behaves normally depending 1771 * on counter and CCRx values even when the trigger is ON. The minimum 1772 * delay to activate CCx output when an active edge occurs on the 1773 * trigger input is 5 clock cycles. 1774 * @retval None 1775 */ 1776 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ 1777 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ 1778 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ 1779 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ 1780 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ 1781 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ 1782 ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) 1783 1784 /** 1785 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. 1786 * @param __HANDLE__ TIM handle. 1787 * @note When the URS bit of the TIMx_CR1 register is set, only counter 1788 * overflow/underflow generates an update interrupt or DMA request (if 1789 * enabled) 1790 * @retval None 1791 */ 1792 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) 1793 1794 /** 1795 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. 1796 * @param __HANDLE__ TIM handle. 1797 * @note When the URS bit of the TIMx_CR1 register is reset, any of the 1798 * following events generate an update interrupt or DMA request (if 1799 * enabled): 1800 * _ Counter overflow underflow 1801 * _ Setting the UG bit 1802 * _ Update generation through the slave mode controller 1803 * @retval None 1804 */ 1805 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) 1806 1807 /** 1808 * @brief Set the TIM Capture x input polarity on runtime. 1809 * @param __HANDLE__ TIM handle. 1810 * @param __CHANNEL__ TIM Channels to be configured. 1811 * This parameter can be one of the following values: 1812 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 1813 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 1814 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 1815 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 1816 * @param __POLARITY__ Polarity for TIx source 1817 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge 1818 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge 1819 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge 1820 * @retval None 1821 */ 1822 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 1823 do{ \ 1824 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ 1825 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ 1826 }while(0) 1827 1828 /** 1829 * @} 1830 */ 1831 /* End of exported macros ----------------------------------------------------*/ 1832 1833 /* Private constants ---------------------------------------------------------*/ 1834 /** @defgroup TIM_Private_Constants TIM Private Constants 1835 * @{ 1836 */ 1837 /* The counter of a timer instance is disabled only if all the CCx and CCxN 1838 channels have been disabled */ 1839 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) 1840 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) 1841 /** 1842 * @} 1843 */ 1844 /* End of private constants --------------------------------------------------*/ 1845 1846 /* Private macros ------------------------------------------------------------*/ 1847 /** @defgroup TIM_Private_Macros TIM Private Macros 1848 * @{ 1849 */ 1850 #if defined(COMP5) && defined(COMP6) && defined(COMP7) 1851 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1852 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1853 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1854 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ 1855 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ 1856 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \ 1857 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \ 1858 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \ 1859 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1860 #else /* COMP5 && COMP6 && COMP7 */ 1861 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ 1862 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ 1863 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ 1864 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \ 1865 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \ 1866 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) 1867 #endif /* COMP5 && COMP6 && COMP7 */ 1868 1869 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ 1870 ((__BASE__) == TIM_DMABASE_CR2) || \ 1871 ((__BASE__) == TIM_DMABASE_SMCR) || \ 1872 ((__BASE__) == TIM_DMABASE_DIER) || \ 1873 ((__BASE__) == TIM_DMABASE_SR) || \ 1874 ((__BASE__) == TIM_DMABASE_EGR) || \ 1875 ((__BASE__) == TIM_DMABASE_CCMR1) || \ 1876 ((__BASE__) == TIM_DMABASE_CCMR2) || \ 1877 ((__BASE__) == TIM_DMABASE_CCER) || \ 1878 ((__BASE__) == TIM_DMABASE_CNT) || \ 1879 ((__BASE__) == TIM_DMABASE_PSC) || \ 1880 ((__BASE__) == TIM_DMABASE_ARR) || \ 1881 ((__BASE__) == TIM_DMABASE_RCR) || \ 1882 ((__BASE__) == TIM_DMABASE_CCR1) || \ 1883 ((__BASE__) == TIM_DMABASE_CCR2) || \ 1884 ((__BASE__) == TIM_DMABASE_CCR3) || \ 1885 ((__BASE__) == TIM_DMABASE_CCR4) || \ 1886 ((__BASE__) == TIM_DMABASE_BDTR) || \ 1887 ((__BASE__) == TIM_DMABASE_CCMR3) || \ 1888 ((__BASE__) == TIM_DMABASE_CCR5) || \ 1889 ((__BASE__) == TIM_DMABASE_CCR6) || \ 1890 ((__BASE__) == TIM_DMABASE_AF1) || \ 1891 ((__BASE__) == TIM_DMABASE_AF2) || \ 1892 ((__BASE__) == TIM_DMABASE_TISEL) || \ 1893 ((__BASE__) == TIM_DMABASE_DTR2) || \ 1894 ((__BASE__) == TIM_DMABASE_ECR) || \ 1895 ((__BASE__) == TIM_DMABASE_OR)) 1896 1897 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1898 1899 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ 1900 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ 1901 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ 1902 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ 1903 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) 1904 1905 #define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ 1906 ((__MODE__) == TIM_UIFREMAP_ENALE)) 1907 1908 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ 1909 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ 1910 ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) 1911 1912 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ 1913 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) 1914 1915 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ 1916 ((__STATE__) == TIM_OCFAST_ENABLE)) 1917 1918 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ 1919 ((__POLARITY__) == TIM_OCPOLARITY_LOW)) 1920 1921 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ 1922 ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) 1923 1924 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ 1925 ((__STATE__) == TIM_OCIDLESTATE_RESET)) 1926 1927 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ 1928 ((__STATE__) == TIM_OCNIDLESTATE_RESET)) 1929 1930 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ 1931 ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) 1932 1933 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ 1934 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ 1935 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) 1936 1937 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ 1938 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ 1939 ((__SELECTION__) == TIM_ICSELECTION_TRC)) 1940 1941 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ 1942 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ 1943 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ 1944 ((__PRESCALER__) == TIM_ICPSC_DIV8)) 1945 1946 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ 1947 ((__MODE__) == TIM_OPMODE_REPETITIVE)) 1948 1949 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ 1950 ((__MODE__) == TIM_ENCODERMODE_TI2) || \ 1951 ((__MODE__) == TIM_ENCODERMODE_TI12) || \ 1952 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ 1953 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ 1954 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ 1955 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ 1956 ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ 1957 ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) 1958 1959 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) 1960 1961 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1962 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1963 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1964 ((__CHANNEL__) == TIM_CHANNEL_4) || \ 1965 ((__CHANNEL__) == TIM_CHANNEL_5) || \ 1966 ((__CHANNEL__) == TIM_CHANNEL_6) || \ 1967 ((__CHANNEL__) == TIM_CHANNEL_ALL)) 1968 1969 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1970 ((__CHANNEL__) == TIM_CHANNEL_2)) 1971 1972 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ 1973 ((__CHANNEL__) == TIM_CHANNEL_2) || \ 1974 ((__CHANNEL__) == TIM_CHANNEL_3) || \ 1975 ((__CHANNEL__) == TIM_CHANNEL_4)) 1976 1977 #if defined(TIM5) && defined(TIM20) 1978 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1979 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1980 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 1981 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 1982 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 1983 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 1984 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 1985 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 1986 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 1987 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 1988 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 1989 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 1990 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 1991 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 1992 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 1993 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ 1994 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \ 1995 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 1996 #elif defined(TIM5) 1997 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 1998 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 1999 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 2000 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 2001 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 2002 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 2003 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 2004 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 2005 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 2006 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 2007 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ 2008 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 2009 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 2010 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 2011 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 2012 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 2013 #elif defined(TIM20) 2014 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 2015 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 2016 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 2017 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 2018 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 2019 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 2020 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 2021 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 2022 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 2023 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 2024 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 2025 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 2026 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 2027 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 2028 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \ 2029 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 2030 #else 2031 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ 2032 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ 2033 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ 2034 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ 2035 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ 2036 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ 2037 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ 2038 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ 2039 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ 2040 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ 2041 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ 2042 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ 2043 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ 2044 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ 2045 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) 2046 #endif /* TIM5 && TIM20 */ 2047 2048 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ 2049 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ 2050 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ 2051 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ 2052 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) 2053 2054 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ 2055 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ 2056 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ 2057 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) 2058 2059 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2060 2061 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ 2062 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) 2063 2064 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ 2065 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ 2066 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ 2067 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) 2068 2069 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2070 2071 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ 2072 ((__STATE__) == TIM_OSSR_DISABLE)) 2073 2074 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ 2075 ((__STATE__) == TIM_OSSI_DISABLE)) 2076 2077 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ 2078 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ 2079 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ 2080 ((__LEVEL__) == TIM_LOCKLEVEL_3)) 2081 2082 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) 2083 2084 2085 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ 2086 ((__STATE__) == TIM_BREAK_DISABLE)) 2087 2088 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ 2089 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) 2090 2091 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ 2092 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) 2093 2094 2095 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ 2096 ((__STATE__) == TIM_BREAK2_DISABLE)) 2097 2098 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ 2099 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) 2100 2101 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ 2102 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) 2103 2104 2105 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ 2106 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) 2107 2108 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) 2109 2110 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ 2111 ((__SOURCE__) == TIM_TRGO_ENABLE) || \ 2112 ((__SOURCE__) == TIM_TRGO_UPDATE) || \ 2113 ((__SOURCE__) == TIM_TRGO_OC1) || \ 2114 ((__SOURCE__) == TIM_TRGO_OC1REF) || \ 2115 ((__SOURCE__) == TIM_TRGO_OC2REF) || \ 2116 ((__SOURCE__) == TIM_TRGO_OC3REF) || \ 2117 ((__SOURCE__) == TIM_TRGO_OC4REF) || \ 2118 ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) 2119 2120 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ 2121 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ 2122 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ 2123 ((__SOURCE__) == TIM_TRGO2_OC1) || \ 2124 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ 2125 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ 2126 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2127 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ 2128 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ 2129 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ 2130 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ 2131 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ 2132 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ 2133 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ 2134 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ 2135 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ 2136 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) 2137 2138 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ 2139 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) 2140 2141 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ 2142 ((__MODE__) == TIM_SLAVEMODE_RESET) || \ 2143 ((__MODE__) == TIM_SLAVEMODE_GATED) || \ 2144 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ 2145 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ 2146 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ 2147 ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) 2148 2149 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ 2150 ((__MODE__) == TIM_OCMODE_PWM2) || \ 2151 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ 2152 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ 2153 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ 2154 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) 2155 2156 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ 2157 ((__MODE__) == TIM_OCMODE_ACTIVE) || \ 2158 ((__MODE__) == TIM_OCMODE_INACTIVE) || \ 2159 ((__MODE__) == TIM_OCMODE_TOGGLE) || \ 2160 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ 2161 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ 2162 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ 2163 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ 2164 ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ 2165 ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) 2166 2167 #if defined (TIM5) && defined(TIM20) 2168 2169 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2170 ((__SELECTION__) == TIM_TS_ITR1) || \ 2171 ((__SELECTION__) == TIM_TS_ITR2) || \ 2172 ((__SELECTION__) == TIM_TS_ITR3) || \ 2173 ((__SELECTION__) == TIM_TS_ITR4) || \ 2174 ((__SELECTION__) == TIM_TS_ITR5) || \ 2175 ((__SELECTION__) == TIM_TS_ITR6) || \ 2176 ((__SELECTION__) == TIM_TS_ITR7) || \ 2177 ((__SELECTION__) == TIM_TS_ITR8) || \ 2178 ((__SELECTION__) == TIM_TS_ITR9) || \ 2179 ((__SELECTION__) == TIM_TS_ITR10)|| \ 2180 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2181 ((__SELECTION__) == TIM_TS_NONE)) 2182 #elif defined (TIM5) 2183 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2184 ((__SELECTION__) == TIM_TS_ITR1) || \ 2185 ((__SELECTION__) == TIM_TS_ITR2) || \ 2186 ((__SELECTION__) == TIM_TS_ITR3) || \ 2187 ((__SELECTION__) == TIM_TS_ITR4) || \ 2188 ((__SELECTION__) == TIM_TS_ITR5) || \ 2189 ((__SELECTION__) == TIM_TS_ITR6) || \ 2190 ((__SELECTION__) == TIM_TS_ITR7) || \ 2191 ((__SELECTION__) == TIM_TS_ITR8) || \ 2192 ((__SELECTION__) == TIM_TS_ITR10)|| \ 2193 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2194 ((__SELECTION__) == TIM_TS_NONE)) 2195 #elif defined (TIM20) 2196 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2197 ((__SELECTION__) == TIM_TS_ITR1) || \ 2198 ((__SELECTION__) == TIM_TS_ITR2) || \ 2199 ((__SELECTION__) == TIM_TS_ITR3) || \ 2200 ((__SELECTION__) == TIM_TS_ITR5) || \ 2201 ((__SELECTION__) == TIM_TS_ITR6) || \ 2202 ((__SELECTION__) == TIM_TS_ITR7) || \ 2203 ((__SELECTION__) == TIM_TS_ITR8) || \ 2204 ((__SELECTION__) == TIM_TS_ITR9) || \ 2205 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2206 ((__SELECTION__) == TIM_TS_NONE)) 2207 #else 2208 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ 2209 ((__SELECTION__) == TIM_TS_ITR1) || \ 2210 ((__SELECTION__) == TIM_TS_ITR2) || \ 2211 ((__SELECTION__) == TIM_TS_ITR3) || \ 2212 ((__SELECTION__) == TIM_TS_ITR5) || \ 2213 ((__SELECTION__) == TIM_TS_ITR6) || \ 2214 ((__SELECTION__) == TIM_TS_ITR7) || \ 2215 ((__SELECTION__) == TIM_TS_ITR8) || \ 2216 ((__SELECTION__) == TIM_TS_ITR11)|| \ 2217 ((__SELECTION__) == TIM_TS_NONE)) 2218 #endif /* TIM5 && TIM20 */ 2219 2220 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ 2221 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ 2222 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ 2223 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ 2224 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) 2225 2226 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ 2227 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ 2228 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ 2229 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) 2230 2231 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2232 2233 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ 2234 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) 2235 2236 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ 2237 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ 2238 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ 2239 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ 2240 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ 2241 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ 2242 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ 2243 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ 2244 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ 2245 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ 2246 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ 2247 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ 2248 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ 2249 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ 2250 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ 2251 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ 2252 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ 2253 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ 2254 ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ 2255 ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ 2256 ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ 2257 ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ 2258 ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ 2259 ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ 2260 ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ 2261 ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) 2262 2263 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) 2264 2265 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) 2266 2267 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) 2268 2269 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ 2270 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ 2271 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ 2272 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) 2273 2274 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ 2275 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) 2276 2277 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ 2278 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ 2279 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ 2280 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ 2281 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) 2282 2283 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ 2284 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ 2285 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ 2286 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ 2287 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) 2288 2289 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ 2290 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ 2291 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ 2292 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ 2293 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) 2294 2295 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ 2296 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ 2297 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ 2298 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ 2299 ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) 2300 2301 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ 2302 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ 2303 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ 2304 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ 2305 ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ 2306 ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ 2307 (__HANDLE__)->ChannelState[5]) 2308 2309 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2310 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ 2311 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ 2312 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ 2313 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ 2314 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ 2315 ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) 2316 2317 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2318 (__HANDLE__)->ChannelState[0] = \ 2319 (__CHANNEL_STATE__); \ 2320 (__HANDLE__)->ChannelState[1] = \ 2321 (__CHANNEL_STATE__); \ 2322 (__HANDLE__)->ChannelState[2] = \ 2323 (__CHANNEL_STATE__); \ 2324 (__HANDLE__)->ChannelState[3] = \ 2325 (__CHANNEL_STATE__); \ 2326 (__HANDLE__)->ChannelState[4] = \ 2327 (__CHANNEL_STATE__); \ 2328 (__HANDLE__)->ChannelState[5] = \ 2329 (__CHANNEL_STATE__); \ 2330 } while(0) 2331 2332 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ 2333 (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ 2334 ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ 2335 ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ 2336 (__HANDLE__)->ChannelNState[3]) 2337 2338 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ 2339 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ 2340 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ 2341 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ 2342 ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) 2343 2344 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ 2345 (__HANDLE__)->ChannelNState[0] = \ 2346 (__CHANNEL_STATE__); \ 2347 (__HANDLE__)->ChannelNState[1] = \ 2348 (__CHANNEL_STATE__); \ 2349 (__HANDLE__)->ChannelNState[2] = \ 2350 (__CHANNEL_STATE__); \ 2351 (__HANDLE__)->ChannelNState[3] = \ 2352 (__CHANNEL_STATE__); \ 2353 } while(0) 2354 2355 /** 2356 * @} 2357 */ 2358 /* End of private macros -----------------------------------------------------*/ 2359 2360 /* Include TIM HAL Extended module */ 2361 #include "stm32g4xx_hal_tim_ex.h" 2362 2363 /* Exported functions --------------------------------------------------------*/ 2364 /** @addtogroup TIM_Exported_Functions TIM Exported Functions 2365 * @{ 2366 */ 2367 2368 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions 2369 * @brief Time Base functions 2370 * @{ 2371 */ 2372 /* Time Base functions ********************************************************/ 2373 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); 2374 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); 2375 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); 2376 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); 2377 /* Blocking mode: Polling */ 2378 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); 2379 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); 2380 /* Non-Blocking mode: Interrupt */ 2381 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); 2382 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); 2383 /* Non-Blocking mode: DMA */ 2384 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 2385 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); 2386 /** 2387 * @} 2388 */ 2389 2390 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions 2391 * @brief TIM Output Compare functions 2392 * @{ 2393 */ 2394 /* Timer Output Compare functions *********************************************/ 2395 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); 2396 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); 2397 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); 2398 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); 2399 /* Blocking mode: Polling */ 2400 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2401 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2402 /* Non-Blocking mode: Interrupt */ 2403 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2404 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2405 /* Non-Blocking mode: DMA */ 2406 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2407 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2408 /** 2409 * @} 2410 */ 2411 2412 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions 2413 * @brief TIM PWM functions 2414 * @{ 2415 */ 2416 /* Timer PWM functions ********************************************************/ 2417 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); 2418 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); 2419 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); 2420 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); 2421 /* Blocking mode: Polling */ 2422 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2423 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2424 /* Non-Blocking mode: Interrupt */ 2425 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2426 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2427 /* Non-Blocking mode: DMA */ 2428 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2429 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2430 /** 2431 * @} 2432 */ 2433 2434 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions 2435 * @brief TIM Input Capture functions 2436 * @{ 2437 */ 2438 /* Timer Input Capture functions **********************************************/ 2439 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); 2440 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); 2441 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); 2442 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); 2443 /* Blocking mode: Polling */ 2444 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2445 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2446 /* Non-Blocking mode: Interrupt */ 2447 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2448 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2449 /* Non-Blocking mode: DMA */ 2450 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 2451 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2452 /** 2453 * @} 2454 */ 2455 2456 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions 2457 * @brief TIM One Pulse functions 2458 * @{ 2459 */ 2460 /* Timer One Pulse functions **************************************************/ 2461 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); 2462 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); 2463 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); 2464 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); 2465 /* Blocking mode: Polling */ 2466 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2467 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2468 /* Non-Blocking mode: Interrupt */ 2469 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2470 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 2471 /** 2472 * @} 2473 */ 2474 2475 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions 2476 * @brief TIM Encoder functions 2477 * @{ 2478 */ 2479 /* Timer Encoder functions ****************************************************/ 2480 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); 2481 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); 2482 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); 2483 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); 2484 /* Blocking mode: Polling */ 2485 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 2486 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 2487 /* Non-Blocking mode: Interrupt */ 2488 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2489 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 2490 /* Non-Blocking mode: DMA */ 2491 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, 2492 uint32_t *pData2, uint16_t Length); 2493 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 2494 /** 2495 * @} 2496 */ 2497 2498 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management 2499 * @brief IRQ handler management 2500 * @{ 2501 */ 2502 /* Interrupt Handler functions ***********************************************/ 2503 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); 2504 /** 2505 * @} 2506 */ 2507 2508 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions 2509 * @brief Peripheral Control functions 2510 * @{ 2511 */ 2512 /* Control functions *********************************************************/ 2513 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2514 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); 2515 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); 2516 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, 2517 uint32_t OutputChannel, uint32_t InputChannel); 2518 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, 2519 uint32_t Channel); 2520 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); 2521 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); 2522 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2523 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); 2524 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2525 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2526 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2527 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2528 uint32_t BurstLength, uint32_t DataLength); 2529 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2530 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2531 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); 2532 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, 2533 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, 2534 uint32_t BurstLength, uint32_t DataLength); 2535 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); 2536 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); 2537 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); 2538 /** 2539 * @} 2540 */ 2541 2542 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 2543 * @brief TIM Callbacks functions 2544 * @{ 2545 */ 2546 /* Callback in non blocking modes (Interrupt and DMA) *************************/ 2547 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); 2548 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); 2549 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); 2550 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); 2551 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); 2552 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); 2553 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); 2554 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); 2555 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); 2556 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); 2557 2558 /* Callbacks Register/UnRegister functions ***********************************/ 2559 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2560 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, 2561 pTIM_CallbackTypeDef pCallback); 2562 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); 2563 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2564 2565 /** 2566 * @} 2567 */ 2568 2569 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions 2570 * @brief Peripheral State functions 2571 * @{ 2572 */ 2573 /* Peripheral State functions ************************************************/ 2574 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); 2575 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); 2576 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); 2577 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); 2578 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); 2579 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); 2580 2581 /* Peripheral Channel state functions ************************************************/ 2582 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); 2583 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); 2584 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); 2585 /** 2586 * @} 2587 */ 2588 2589 /** 2590 * @} 2591 */ 2592 /* End of exported functions -------------------------------------------------*/ 2593 2594 /* Private functions----------------------------------------------------------*/ 2595 /** @defgroup TIM_Private_Functions TIM Private Functions 2596 * @{ 2597 */ 2598 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); 2599 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); 2600 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 2601 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, 2602 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); 2603 2604 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); 2605 void TIM_DMAError(DMA_HandleTypeDef *hdma); 2606 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); 2607 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); 2608 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); 2609 2610 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) 2611 void TIM_ResetCallback(TIM_HandleTypeDef *htim); 2612 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ 2613 2614 /** 2615 * @} 2616 */ 2617 /* End of private functions --------------------------------------------------*/ 2618 2619 /** 2620 * @} 2621 */ 2622 2623 /** 2624 * @} 2625 */ 2626 2627 #ifdef __cplusplus 2628 } 2629 #endif 2630 2631 #endif /* STM32G4xx_HAL_TIM_H */ 2632
