1 /**
2   ******************************************************************************
3   * @file    stm32g071xx.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for stm32g071xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral's registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * Copyright (c) 2018-2021 STMicroelectronics.
18   * All rights reserved.
19   *
20   * This software is licensed under terms that can be found in the LICENSE file
21   * in the root directory of this software component.
22   * If no LICENSE file comes with this software, it is provided AS-IS.
23   *
24   ******************************************************************************
25   */
26 
27 /** @addtogroup CMSIS_Device
28   * @{
29   */
30 
31 /** @addtogroup stm32g071xx
32   * @{
33   */
34 
35 #ifndef STM32G071xx_H
36 #define STM32G071xx_H
37 
38 #ifdef __cplusplus
39  extern "C" {
40 #endif /* __cplusplus */
41 
42 /** @addtogroup Configuration_section_for_CMSIS
43   * @{
44   */
45 
46 /**
47   * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
48    */
49 #define __CM0PLUS_REV             0U /*!< Core Revision r0p0                            */
50 #define __MPU_PRESENT             1U /*!< STM32G0xx  provides an MPU                    */
51 #define __VTOR_PRESENT            1U /*!< Vector  Table  Register supported             */
52 #define __NVIC_PRIO_BITS          2U /*!< STM32G0xx uses 2 Bits for the Priority Levels */
53 #define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
54 
55 /**
56   * @}
57   */
58 
59 /** @addtogroup Peripheral_interrupt_number_definition
60   * @{
61   */
62 
63 /**
64  * @brief stm32g071xx Interrupt Number Definition, according to the selected device
65  *        in @ref Library_configuration_section
66  */
67 
68 /*!< Interrupt Number Definition */
69 typedef enum
70 {
71 /******  Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
72   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
73   HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
74   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
75   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
76   SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
77 /******  STM32G0xxxx specific Interrupt Numbers ****************************************************************/
78   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
79   PVD_IRQn                    = 1,      /*!< PVD through EXTI line 16                                          */
80   RTC_TAMP_IRQn               = 2,      /*!< RTC interrupt through the EXTI line 19 & 21                       */
81   FLASH_IRQn                  = 3,      /*!< FLASH global Interrupt                                            */
82   RCC_IRQn                    = 4,      /*!< RCC global Interrupt                                              */
83   EXTI0_1_IRQn                = 5,      /*!< EXTI 0 and 1 Interrupts                                           */
84   EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                                      */
85   EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                                      */
86   UCPD1_2_IRQn                = 8,      /*!< UCPD1 and UCPD2 global Interrupt                                  */
87   DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                          */
88   DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                           */
89   DMA1_Ch4_7_DMAMUX1_OVR_IRQn = 11,     /*!< DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts        */
90   ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts (combined with EXTI 17 & 18)     */
91   TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts            */
92   TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                                    */
93   TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                                    */
94   TIM3_IRQn                   = 16,     /*!< TIM3 global Interrupt                                             */
95   TIM6_DAC_LPTIM1_IRQn        = 17,     /*!< TIM6, DAC and LPTIM1 global Interrupts                            */
96   TIM7_LPTIM2_IRQn            = 18,     /*!< TIM7 and LPTIM2 global Interrupt                                  */
97   TIM14_IRQn                  = 19,     /*!< TIM14 global Interrupt                                            */
98   TIM15_IRQn                  = 20,     /*!< TIM15 global Interrupt                                            */
99   TIM16_IRQn                  = 21,     /*!< TIM16 global Interrupt                                            */
100   TIM17_IRQn                  = 22,     /*!< TIM17 global Interrupt                                            */
101   I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt  (combined with EXTI 23)                           */
102   I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                                    */
103   SPI1_IRQn                   = 25,     /*!< SPI1/I2S1 Interrupt                                               */
104   SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                                    */
105   USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                                  */
106   USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                                  */
107   USART3_4_LPUART1_IRQn       = 29,     /*!< USART3, USART4 and LPUART1 globlal Interrupts (combined with EXTI 28) */
108   CEC_IRQn                    = 30,     /*!< CEC Interrupt(combined with EXTI 27)                               */
109 } IRQn_Type;
110 
111 /**
112   * @}
113   */
114 
115 #include "core_cm0plus.h"               /* Cortex-M0+ processor and core peripherals */
116 #include "system_stm32g0xx.h"
117 #include <stdint.h>
118 
119 /** @addtogroup Peripheral_registers_structures
120   * @{
121   */
122 
123 /**
124   * @brief Analog to Digital Converter
125   */
126 typedef struct
127 {
128   __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
129   __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
130   __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
131   __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
132   __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
133   __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
134        uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
135        uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
136   __IO uint32_t AWD1TR;       /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
137   __IO uint32_t AWD2TR;       /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
138   __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
139   __IO uint32_t AWD3TR;       /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
140        uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
141   __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
142        uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
143   __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
144   __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
145        uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
146   __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
147 } ADC_TypeDef;
148 
149 typedef struct
150 {
151   __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC1 base address + 0x308 */
152 } ADC_Common_TypeDef;
153 
154 /* Legacy registers naming */
155 #define TR1     AWD1TR
156 #define TR2     AWD2TR
157 #define TR3     AWD3TR
158 
159 
160 /**
161   * @brief HDMI-CEC
162   */
163 typedef struct
164 {
165   __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
166   __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
167   __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
168   __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
169   __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
170   __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
171 }CEC_TypeDef;
172 
173 /**
174   * @brief Comparator
175   */
176 typedef struct
177 {
178   __IO uint32_t CSR;         /*!< COMP control and status register,                                                 Address offset: 0x00 */
179 } COMP_TypeDef;
180 
181 typedef struct
182 {
183   __IO uint32_t CSR_ODD;    /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */
184   __IO uint32_t CSR_EVEN;   /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */
185 } COMP_Common_TypeDef;
186 
187 /**
188   * @brief CRC calculation unit
189   */
190 typedef struct
191 {
192   __IO uint32_t DR;             /*!< CRC Data register,                         Address offset: 0x00 */
193   __IO uint32_t IDR;            /*!< CRC Independent data register,             Address offset: 0x04 */
194   __IO uint32_t CR;             /*!< CRC Control register,                      Address offset: 0x08 */
195        uint32_t RESERVED1;      /*!< Reserved,                                                  0x0C */
196   __IO uint32_t INIT;           /*!< Initial CRC value register,                Address offset: 0x10 */
197   __IO uint32_t POL;            /*!< CRC polynomial register,                   Address offset: 0x14 */
198 } CRC_TypeDef;
199 
200 /**
201   * @brief Digital to Analog Converter
202   */
203 typedef struct
204 {
205   __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
206   __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
207   __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
208   __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
209   __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
210   __IO uint32_t DHR12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
211   __IO uint32_t DHR12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
212   __IO uint32_t DHR8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
213   __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
214   __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
215   __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
216   __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
217   __IO uint32_t DOR2;        /*!< DAC channel2 data output register,                       Address offset: 0x30 */
218   __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
219   __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
220   __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
221   __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
222   __IO uint32_t SHSR2;       /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
223   __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
224   __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
225 } DAC_TypeDef;
226 
227 /**
228   * @brief Debug MCU
229   */
230 typedef struct
231 {
232   __IO uint32_t IDCODE;      /*!< MCU device ID code,              Address offset: 0x00 */
233   __IO uint32_t CR;          /*!< Debug configuration register,    Address offset: 0x04 */
234   __IO uint32_t APBFZ1;      /*!< Debug APB freeze register 1,     Address offset: 0x08 */
235   __IO uint32_t APBFZ2;      /*!< Debug APB freeze register 2,     Address offset: 0x0C */
236 } DBG_TypeDef;
237 
238 /**
239   * @brief DMA Controller
240   */
241 typedef struct
242 {
243   __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
244   __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
245   __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
246   __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
247 } DMA_Channel_TypeDef;
248 
249 typedef struct
250 {
251   __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
252   __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
253 } DMA_TypeDef;
254 
255 /**
256   * @brief DMA Multiplexer
257   */
258 typedef struct
259 {
260   __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
261 }DMAMUX_Channel_TypeDef;
262 
263 typedef struct
264 {
265   __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
266   __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
267 }DMAMUX_ChannelStatus_TypeDef;
268 
269 typedef struct
270 {
271   __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
272 }DMAMUX_RequestGen_TypeDef;
273 
274 typedef struct
275 {
276   __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
277   __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
278 }DMAMUX_RequestGenStatus_TypeDef;
279 
280 /**
281   * @brief Asynch Interrupt/Event Controller (EXTI)
282   */
283 typedef struct
284 {
285   __IO uint32_t RTSR1;          /*!< EXTI Rising Trigger Selection Register 1,        Address offset:   0x00 */
286   __IO uint32_t FTSR1;          /*!< EXTI Falling Trigger Selection Register 1,       Address offset:   0x04 */
287   __IO uint32_t SWIER1;         /*!< EXTI Software Interrupt event Register 1,        Address offset:   0x08 */
288   __IO uint32_t RPR1;           /*!< EXTI Rising Pending Register 1,                  Address offset:   0x0C */
289   __IO uint32_t FPR1;           /*!< EXTI Falling Pending Register 1,                 Address offset:   0x10 */
290        uint32_t RESERVED1[3];   /*!< Reserved 1,                                                0x14 -- 0x1C */
291        uint32_t RESERVED2[5];   /*!< Reserved 2,                                                0x20 -- 0x30 */
292        uint32_t RESERVED3[11];  /*!< Reserved 3,                                                0x34 -- 0x5C */
293   __IO uint32_t EXTICR[4];      /*!< EXTI External Interrupt Configuration Register,            0x60 -- 0x6C */
294        uint32_t RESERVED4[4];   /*!< Reserved 4,                                                0x70 -- 0x7C */
295   __IO uint32_t IMR1;           /*!< EXTI Interrupt Mask Register 1,                  Address offset:   0x80 */
296   __IO uint32_t EMR1;           /*!< EXTI Event Mask Register 1,                      Address offset:   0x84 */
297        uint32_t RESERVED5[2];   /*!< Reserved 5,                                                0x88 -- 0x8C */
298   __IO uint32_t IMR2;           /*!< EXTI Interrupt Mask Register 2,                  Address offset:   0x90 */
299   __IO uint32_t EMR2;           /*!< EXTI Event Mask Register 2,                      Address offset:   0x94 */
300 } EXTI_TypeDef;
301 
302 /**
303   * @brief FLASH Registers
304   */
305 typedef struct
306 {
307   __IO uint32_t ACR;          /*!< FLASH Access Control register,                     Address offset: 0x00 */
308        uint32_t RESERVED1;    /*!< Reserved1,                                         Address offset: 0x04 */
309   __IO uint32_t KEYR;         /*!< FLASH Key register,                                Address offset: 0x08 */
310   __IO uint32_t OPTKEYR;      /*!< FLASH Option Key register,                         Address offset: 0x0C */
311   __IO uint32_t SR;           /*!< FLASH Status register,                             Address offset: 0x10 */
312   __IO uint32_t CR;           /*!< FLASH Control register,                            Address offset: 0x14 */
313   __IO uint32_t ECCR;         /*!< FLASH ECC register,                                Address offset: 0x18 */
314        uint32_t RESERVED2;    /*!< Reserved2,                                         Address offset: 0x1C */
315   __IO uint32_t OPTR;         /*!< FLASH Option register,                             Address offset: 0x20 */
316   __IO uint32_t PCROP1ASR;    /*!< FLASH Bank PCROP area A Start address register,    Address offset: 0x24 */
317   __IO uint32_t PCROP1AER;    /*!< FLASH Bank PCROP area A End address register,      Address offset: 0x28 */
318   __IO uint32_t WRP1AR;       /*!< FLASH Bank WRP area A address register,            Address offset: 0x2C */
319   __IO uint32_t WRP1BR;       /*!< FLASH Bank WRP area B address register,            Address offset: 0x30 */
320   __IO uint32_t PCROP1BSR;    /*!< FLASH Bank PCROP area B Start address register,    Address offset: 0x34 */
321   __IO uint32_t PCROP1BER;    /*!< FLASH Bank PCROP area B End address register,      Address offset: 0x38 */
322        uint32_t RESERVED8[17];/*!< Reserved8,                                         Address offset: 0x3C--0x7C */
323   __IO uint32_t SECR;         /*!< FLASH security register ,                          Address offset: 0x80 */
324 } FLASH_TypeDef;
325 
326 /**
327   * @brief General Purpose I/O
328   */
329 typedef struct
330 {
331   __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
332   __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
333   __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
334   __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
335   __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
336   __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
337   __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
338   __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
339   __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
340   __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
341 } GPIO_TypeDef;
342 
343 
344 /**
345   * @brief Inter-integrated Circuit Interface
346   */
347 typedef struct
348 {
349   __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
350   __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
351   __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
352   __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
353   __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
354   __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
355   __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
356   __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
357   __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
358   __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
359   __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
360 } I2C_TypeDef;
361 
362 /**
363   * @brief Independent WATCHDOG
364   */
365 typedef struct
366 {
367   __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
368   __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
369   __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
370   __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
371   __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
372 } IWDG_TypeDef;
373 
374 /**
375   * @brief LPTIMER
376   */
377 typedef struct
378 {
379   __IO uint32_t ISR;              /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
380   __IO uint32_t ICR;              /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
381   __IO uint32_t IER;              /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
382   __IO uint32_t CFGR;             /*!< LPTIM Configuration register,                       Address offset: 0x0C */
383   __IO uint32_t CR;               /*!< LPTIM Control register,                             Address offset: 0x10 */
384   __IO uint32_t CMP;              /*!< LPTIM Compare register,                             Address offset: 0x14 */
385   __IO uint32_t ARR;              /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
386   __IO uint32_t CNT;              /*!< LPTIM Counter register,                             Address offset: 0x1C */
387   __IO uint32_t RESERVED1;        /*!< Reserved1,                                          Address offset: 0x20 */
388   __IO uint32_t CFGR2;            /*!< LPTIM Option register,                              Address offset: 0x24 */
389 } LPTIM_TypeDef;
390 
391 
392 /**
393   * @brief Power Control
394   */
395 typedef struct
396 {
397   __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
398   __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
399   __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
400   __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
401   __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
402   __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
403   __IO uint32_t SCR;          /*!< PWR Power Status Clear Register,                  Address offset: 0x18 */
404        uint32_t RESERVED1;    /*!< Reserved,                                         Address offset: 0x1C */
405   __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
406   __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
407   __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
408   __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
409   __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
410   __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
411   __IO uint32_t PUCRD;        /*!< PWR Pull-Up Control Register of port D,           Address offset: 0x38 */
412   __IO uint32_t PDCRD;        /*!< PWR Pull-Down Control Register of port D,         Address offset: 0x3C */
413        uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x40 */
414        uint32_t RESERVED3;    /*!< Reserved,                                         Address offset: 0x44 */
415   __IO uint32_t PUCRF;        /*!< PWR Pull-Up Control Register of port F,           Address offset: 0x48 */
416   __IO uint32_t PDCRF;        /*!< PWR Pull-Down Control Register of port F,         Address offset: 0x4C */
417 } PWR_TypeDef;
418 
419 /**
420   * @brief Reset and Clock Control
421   */
422 typedef struct
423 {
424   __IO uint32_t CR;          /*!< RCC Clock Sources Control Register,                                     Address offset: 0x00 */
425   __IO uint32_t ICSCR;       /*!< RCC Internal Clock Sources Calibration Register,                        Address offset: 0x04 */
426   __IO uint32_t CFGR;        /*!< RCC Regulated Domain Clocks Configuration Register,                     Address offset: 0x08 */
427   __IO uint32_t PLLCFGR;     /*!< RCC System PLL configuration Register,                                  Address offset: 0x0C */
428   __IO uint32_t RESERVED0;   /*!< Reserved,                                                               Address offset: 0x10 */
429   __IO uint32_t RESERVED1;   /*!< Reserved,                                                               Address offset: 0x14 */
430   __IO uint32_t CIER;        /*!< RCC Clock Interrupt Enable Register,                                    Address offset: 0x18 */
431   __IO uint32_t CIFR;        /*!< RCC Clock Interrupt Flag Register,                                      Address offset: 0x1C */
432   __IO uint32_t CICR;        /*!< RCC Clock Interrupt Clear Register,                                     Address offset: 0x20 */
433   __IO uint32_t IOPRSTR;     /*!< RCC IO port reset register,                                             Address offset: 0x24 */
434   __IO uint32_t AHBRSTR;     /*!< RCC AHB peripherals reset register,                                     Address offset: 0x28 */
435   __IO uint32_t APBRSTR1;    /*!< RCC APB peripherals reset register 1,                                   Address offset: 0x2C */
436   __IO uint32_t APBRSTR2;    /*!< RCC APB peripherals reset register 2,                                   Address offset: 0x30 */
437   __IO uint32_t IOPENR;      /*!< RCC IO port enable register,                                            Address offset: 0x34 */
438   __IO uint32_t AHBENR;      /*!< RCC AHB peripherals clock enable register,                              Address offset: 0x38 */
439   __IO uint32_t APBENR1;     /*!< RCC APB peripherals clock enable register1,                             Address offset: 0x3C */
440   __IO uint32_t APBENR2;     /*!< RCC APB peripherals clock enable register2,                             Address offset: 0x40 */
441   __IO uint32_t IOPSMENR;    /*!< RCC IO port clocks enable in sleep mode register,                       Address offset: 0x44 */
442   __IO uint32_t AHBSMENR;    /*!< RCC AHB peripheral clocks enable in sleep mode register,                Address offset: 0x48 */
443   __IO uint32_t APBSMENR1;   /*!< RCC APB peripheral clocks enable in sleep mode register1,               Address offset: 0x4C */
444   __IO uint32_t APBSMENR2;   /*!< RCC APB peripheral clocks enable in sleep mode register2,               Address offset: 0x50 */
445   __IO uint32_t CCIPR;       /*!< RCC Peripherals Independent Clocks Configuration Register,              Address offset: 0x54 */
446   __IO uint32_t RESERVED2;   /*!< Reserved,                                                               Address offset: 0x58 */
447   __IO uint32_t BDCR;        /*!< RCC Backup Domain Control Register,                                     Address offset: 0x5C */
448   __IO uint32_t CSR;         /*!< RCC Unregulated Domain Clock Control and Status Register,               Address offset: 0x60 */
449 } RCC_TypeDef;
450 
451 /**
452   * @brief Real-Time Clock
453   */
454 typedef struct
455 {
456   __IO uint32_t TR;          /*!< RTC time register,                                         Address offset: 0x00 */
457   __IO uint32_t DR;          /*!< RTC date register,                                         Address offset: 0x04 */
458   __IO uint32_t SSR;         /*!< RTC sub second register,                                   Address offset: 0x08 */
459   __IO uint32_t ICSR;        /*!< RTC initialization control and status register,            Address offset: 0x0C */
460   __IO uint32_t PRER;        /*!< RTC prescaler register,                                    Address offset: 0x10 */
461   __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
462   __IO uint32_t CR;          /*!< RTC control register,                                      Address offset: 0x18 */
463        uint32_t RESERVED0;   /*!< Reserved                                                   Address offset: 0x1C */
464        uint32_t RESERVED1;   /*!< Reserved                                                   Address offset: 0x20 */
465   __IO uint32_t WPR;         /*!< RTC write protection register,                             Address offset: 0x24 */
466   __IO uint32_t CALR;        /*!< RTC calibration register,                                  Address offset: 0x28 */
467   __IO uint32_t SHIFTR;      /*!< RTC shift control register,                                Address offset: 0x2C */
468   __IO uint32_t TSTR;        /*!< RTC time stamp time register,                              Address offset: 0x30 */
469   __IO uint32_t TSDR;        /*!< RTC time stamp date register,                              Address offset: 0x34 */
470   __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
471        uint32_t RESERVED2;   /*!< Reserved                                                   Address offset: 0x1C */
472   __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                                      Address offset: 0x40 */
473   __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
474   __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                                      Address offset: 0x48 */
475   __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                           Address offset: 0x4C */
476   __IO uint32_t SR;          /*!< RTC Status register,                                       Address offset: 0x50 */
477   __IO uint32_t MISR;        /*!< RTC Masked Interrupt Status register,                      Address offset: 0x54 */
478        uint32_t RESERVED3;   /*!< Reserved                                                   Address offset: 0x58 */
479   __IO uint32_t SCR;         /*!< RTC Status Clear register,                                 Address offset: 0x5C */
480   __IO uint32_t OR;          /*!< RTC option register,                                       Address offset: 0x60 */
481 } RTC_TypeDef;
482 
483 /**
484   * @brief Tamper and backup registers
485   */
486 typedef struct
487 {
488   __IO uint32_t CR1;            /*!< TAMP configuration register 1,                             Address offset: 0x00 */
489   __IO uint32_t CR2;            /*!< TAMP configuration register 2,                             Address offset: 0x04 */
490        uint32_t RESERVED0;      /*!< Reserved                                                   Address offset: 0x08 */
491   __IO uint32_t FLTCR;          /*!< Reserved                                                   Address offset: 0x0C */
492        uint32_t RESERVED1[7];   /*!< Reserved                                                   Address offset: 0x10 -- 0x28 */
493   __IO uint32_t IER;            /*!< TAMP Interrupt enable register,                            Address offset: 0x2C */
494   __IO uint32_t SR;             /*!< TAMP Status register,                                      Address offset: 0x30 */
495   __IO uint32_t MISR;           /*!< TAMP Masked Interrupt Status register,                     Address offset: 0x34 */
496        uint32_t RESERVED2;      /*!< Reserved                                                   Address offset: 0x38 */
497   __IO uint32_t SCR;            /*!< TAMP Status clear register,                                Address offset: 0x3C */
498        uint32_t RESERVED3[48];  /*!< Reserved                                                   Address offset: 0x54 -- 0xFC */
499   __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                                    Address offset: 0x100 */
500   __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                                    Address offset: 0x104 */
501   __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                                    Address offset: 0x108 */
502   __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                                    Address offset: 0x10C */
503   __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                                    Address offset: 0x110 */
504 } TAMP_TypeDef;
505 
506   /**
507   * @brief Serial Peripheral Interface
508   */
509 typedef struct
510 {
511   __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
512   __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
513   __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
514   __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
515   __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
516   __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
517   __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
518   __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
519   __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
520 } SPI_TypeDef;
521 
522 /**
523   * @brief System configuration controller
524   */
525 typedef struct
526 {
527   __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                   Address offset: 0x00 */
528        uint32_t RESERVED0[5];   /*!< Reserved,                                                   0x04 --0x14 */
529   __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                   Address offset: 0x18 */
530        uint32_t RESERVED1[25];  /*!< Reserved                                                           0x1C */
531   __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register,             Address offset: 0x80 */
532 } SYSCFG_TypeDef;
533 
534 /**
535   * @brief TIM
536   */
537 typedef struct
538 {
539   __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
540   __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
541   __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
542   __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
543   __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
544   __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
545   __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
546   __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
547   __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
548   __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
549   __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
550   __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
551   __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
552   __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
553   __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
554   __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
555   __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
556   __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
557   __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
558   __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
559   __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */
560   __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
561   __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
562   __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
563   __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */
564   __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */
565   __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
566 } TIM_TypeDef;
567 
568 /**
569   * @brief Universal Synchronous Asynchronous Receiver Transmitter
570   */
571 typedef struct
572 {
573   __IO uint32_t CR1;         /*!< USART Control register 1,                 Address offset: 0x00  */
574   __IO uint32_t CR2;         /*!< USART Control register 2,                 Address offset: 0x04  */
575   __IO uint32_t CR3;         /*!< USART Control register 3,                 Address offset: 0x08  */
576   __IO uint32_t BRR;         /*!< USART Baud rate register,                 Address offset: 0x0C  */
577   __IO uint32_t GTPR;        /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
578   __IO uint32_t RTOR;        /*!< USART Receiver Time Out register,         Address offset: 0x14  */
579   __IO uint32_t RQR;         /*!< USART Request register,                   Address offset: 0x18  */
580   __IO uint32_t ISR;         /*!< USART Interrupt and status register,      Address offset: 0x1C  */
581   __IO uint32_t ICR;         /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
582   __IO uint32_t RDR;         /*!< USART Receive Data register,              Address offset: 0x24  */
583   __IO uint32_t TDR;         /*!< USART Transmit Data register,             Address offset: 0x28  */
584   __IO uint32_t PRESC;       /*!< USART Prescaler register,                 Address offset: 0x2C  */
585 } USART_TypeDef;
586 
587 /**
588   * @brief VREFBUF
589   */
590 typedef struct
591 {
592   __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
593   __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
594 } VREFBUF_TypeDef;
595 
596 /**
597   * @brief Window WATCHDOG
598   */
599 typedef struct
600 {
601   __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
602   __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
603   __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
604 } WWDG_TypeDef;
605 
606 
607 /**
608   * @brief UCPD
609   */
610 typedef struct
611 {
612   __IO uint32_t CFG1;          /*!< UCPD configuration register 1,             Address offset: 0x00 */
613   __IO uint32_t CFG2;          /*!< UCPD configuration register 2,             Address offset: 0x04 */
614   __IO uint32_t RESERVED0;     /*!< UCPD reserved register,                    Address offset: 0x08 */
615   __IO uint32_t CR;            /*!< UCPD control register,                     Address offset: 0x0C */
616   __IO uint32_t IMR;           /*!< UCPD interrupt mask register,              Address offset: 0x10 */
617   __IO uint32_t SR;            /*!< UCPD status register,                      Address offset: 0x14 */
618   __IO uint32_t ICR;           /*!< UCPD interrupt flag clear register         Address offset: 0x18 */
619   __IO uint32_t TX_ORDSET;     /*!< UCPD Tx ordered set type register,         Address offset: 0x1C */
620   __IO uint32_t TX_PAYSZ;      /*!< UCPD Tx payload size register,             Address offset: 0x20 */
621   __IO uint32_t TXDR;          /*!< UCPD Tx data register,                     Address offset: 0x24 */
622   __IO uint32_t RX_ORDSET;     /*!< UCPD Rx ordered set type register,         Address offset: 0x28 */
623   __IO uint32_t RX_PAYSZ;      /*!< UCPD Rx payload size register,             Address offset: 0x2C */
624   __IO uint32_t RXDR;          /*!< UCPD Rx data register,                     Address offset: 0x30 */
625   __IO uint32_t RX_ORDEXT1;    /*!< UCPD Rx ordered set extension 1 register,  Address offset: 0x34 */
626   __IO uint32_t RX_ORDEXT2;    /*!< UCPD Rx ordered set extension 2 register,  Address offset: 0x38 */
627 
628 } UCPD_TypeDef;
629 /**
630   * @}
631   */
632 
633 /** @addtogroup Peripheral_memory_map
634   * @{
635   */
636 #define FLASH_BASE            (0x08000000UL)  /*!< FLASH base address */
637 #define SRAM_BASE             (0x20000000UL)  /*!< SRAM base address */
638 #define PERIPH_BASE           (0x40000000UL)  /*!< Peripheral base address */
639 #define IOPORT_BASE           (0x50000000UL)  /*!< IOPORT base address */
640 #define SRAM_SIZE_MAX         (0x00008000UL)  /*!< maximum SRAM size (up to 32 KBytes) */
641 
642 #define FLASH_SIZE            (((*((uint32_t *)FLASHSIZE_BASE)) & (0x00FFU)) << 10U)
643 
644 /*!< Peripheral memory map */
645 #define APBPERIPH_BASE        (PERIPH_BASE)
646 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
647 
648 /*!< APB peripherals */
649 
650 #define TIM2_BASE             (APBPERIPH_BASE + 0UL)
651 #define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
652 #define TIM6_BASE             (APBPERIPH_BASE + 0x00001000UL)
653 #define TIM7_BASE             (APBPERIPH_BASE + 0x00001400UL)
654 #define TIM14_BASE            (APBPERIPH_BASE + 0x00002000UL)
655 #define RTC_BASE              (APBPERIPH_BASE + 0x00002800UL)
656 #define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00UL)
657 #define IWDG_BASE             (APBPERIPH_BASE + 0x00003000UL)
658 #define SPI2_BASE             (APBPERIPH_BASE + 0x00003800UL)
659 #define USART2_BASE           (APBPERIPH_BASE + 0x00004400UL)
660 #define USART3_BASE           (APBPERIPH_BASE + 0x00004800UL)
661 #define USART4_BASE           (APBPERIPH_BASE + 0x00004C00UL)
662 #define I2C1_BASE             (APBPERIPH_BASE + 0x00005400UL)
663 #define I2C2_BASE             (APBPERIPH_BASE + 0x00005800UL)
664 #define PWR_BASE              (APBPERIPH_BASE + 0x00007000UL)
665 #define DAC1_BASE             (APBPERIPH_BASE + 0x00007400UL)
666 #define DAC_BASE              (APBPERIPH_BASE + 0x00007400UL) /* Kept for legacy purpose */
667 #define CEC_BASE              (APBPERIPH_BASE + 0x00007800UL)
668 #define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00UL)
669 #define LPUART1_BASE          (APBPERIPH_BASE + 0x00008000UL)
670 #define LPTIM2_BASE           (APBPERIPH_BASE + 0x00009400UL)
671 #define UCPD1_BASE            (APBPERIPH_BASE + 0x0000A000UL)
672 #define UCPD2_BASE            (APBPERIPH_BASE + 0x0000A400UL)
673 #define TAMP_BASE             (APBPERIPH_BASE + 0x0000B000UL)
674 #define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000UL)
675 #define VREFBUF_BASE          (APBPERIPH_BASE + 0x00010030UL)
676 #define COMP1_BASE            (SYSCFG_BASE + 0x0200UL)
677 #define COMP2_BASE            (SYSCFG_BASE + 0x0204UL)
678 #define ADC1_BASE             (APBPERIPH_BASE + 0x00012400UL)
679 #define ADC1_COMMON_BASE      (APBPERIPH_BASE + 0x00012708UL)
680 #define ADC_BASE              (ADC1_COMMON_BASE) /* Kept for legacy purpose */
681 #define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00UL)
682 #define SPI1_BASE             (APBPERIPH_BASE + 0x00013000UL)
683 #define USART1_BASE           (APBPERIPH_BASE + 0x00013800UL)
684 #define TIM15_BASE            (APBPERIPH_BASE + 0x00014000UL)
685 #define TIM16_BASE            (APBPERIPH_BASE + 0x00014400UL)
686 #define TIM17_BASE            (APBPERIPH_BASE + 0x00014800UL)
687 #define DBG_BASE              (APBPERIPH_BASE + 0x00015800UL)
688 
689 
690 /*!< AHB peripherals */
691 #define DMA1_BASE             (AHBPERIPH_BASE)
692 #define DMAMUX1_BASE          (AHBPERIPH_BASE + 0x00000800UL)
693 #define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)
694 #define EXTI_BASE             (AHBPERIPH_BASE + 0x00001800UL)
695 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL)
696 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)
697 
698 
699 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008UL)
700 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CUL)
701 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030UL)
702 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044UL)
703 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058UL)
704 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CUL)
705 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080UL)
706 
707 #define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
708 #define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
709 #define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
710 #define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
711 #define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
712 #define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
713 #define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
714 
715 #define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
716 #define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
717 #define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
718 #define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
719 
720 #define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
721 #define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
722 
723 /*!< IOPORT */
724 #define GPIOA_BASE            (IOPORT_BASE + 0x00000000UL)
725 #define GPIOB_BASE            (IOPORT_BASE + 0x00000400UL)
726 #define GPIOC_BASE            (IOPORT_BASE + 0x00000800UL)
727 #define GPIOD_BASE            (IOPORT_BASE + 0x00000C00UL)
728 #define GPIOF_BASE            (IOPORT_BASE + 0x00001400UL)
729 
730 /*!< Device Electronic Signature */
731 #define PACKAGE_BASE          (0x1FFF7500UL)        /*!< Package data register base address     */
732 #define UID_BASE              (0x1FFF7590UL)        /*!< Unique device ID register base address */
733 #define FLASHSIZE_BASE        (0x1FFF75E0UL)        /*!< Flash size data register base address  */
734 
735 /**
736   * @}
737   */
738 
739 /** @addtogroup Peripheral_declaration
740   * @{
741   */
742 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
743 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
744 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
745 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
746 #define TIM14               ((TIM_TypeDef *) TIM14_BASE)
747 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
748 #define TAMP                ((TAMP_TypeDef *) TAMP_BASE)
749 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
750 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
751 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
752 #define USART2              ((USART_TypeDef *) USART2_BASE)
753 #define USART3              ((USART_TypeDef *) USART3_BASE)
754 #define USART4              ((USART_TypeDef *) USART4_BASE)
755 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
756 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
757 #define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
758 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
759 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
760 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
761 #define DAC1                ((DAC_TypeDef *) DAC1_BASE)
762 #define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
763 #define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
764 #define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
765 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
766 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
767 #define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
768 #define COMP1               ((COMP_TypeDef *) COMP1_BASE)
769 #define COMP2               ((COMP_TypeDef *) COMP2_BASE)
770 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP1_BASE)
771 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
772 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
773 #define USART1              ((USART_TypeDef *) USART1_BASE)
774 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
775 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
776 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
777 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
778 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
779 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
780 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
781 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
782 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
783 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
784 #define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
785 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
786 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
787 #define ADC                 (ADC1_COMMON) /* Kept for legacy purpose */
788 
789 
790 #define UCPD1               ((UCPD_TypeDef *) UCPD1_BASE)
791 #define UCPD2               ((UCPD_TypeDef *) UCPD2_BASE)
792 
793 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
794 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
795 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
796 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
797 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
798 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
799 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
800 #define DMAMUX1                ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
801 #define DMAMUX1_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
802 #define DMAMUX1_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
803 #define DMAMUX1_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
804 #define DMAMUX1_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
805 #define DMAMUX1_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
806 #define DMAMUX1_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
807 #define DMAMUX1_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
808 
809 #define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
810 #define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
811 #define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
812 #define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
813 
814 #define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
815 #define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
816 
817 #define DBG              ((DBG_TypeDef *) DBG_BASE)
818 
819 /**
820   * @}
821   */
822 
823 /** @addtogroup Exported_constants
824   * @{
825   */
826 
827   /** @addtogroup Hardware_Constant_Definition
828     * @{
829     */
830 #define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
831 
832   /**
833     * @}
834     */
835 
836   /** @addtogroup Peripheral_Registers_Bits_Definition
837   * @{
838   */
839 
840 /******************************************************************************/
841 /*                         Peripheral Registers Bits Definition               */
842 /******************************************************************************/
843 
844 /******************************************************************************/
845 /*                                                                            */
846 /*                      Analog to Digital Converter (ADC)                     */
847 /*                                                                            */
848 /******************************************************************************/
849 /********************  Bit definition for ADC_ISR register  *******************/
850 #define ADC_ISR_ADRDY_Pos              (0U)
851 #define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
852 #define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
853 #define ADC_ISR_EOSMP_Pos              (1U)
854 #define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
855 #define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
856 #define ADC_ISR_EOC_Pos                (2U)
857 #define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
858 #define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
859 #define ADC_ISR_EOS_Pos                (3U)
860 #define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
861 #define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
862 #define ADC_ISR_OVR_Pos                (4U)
863 #define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
864 #define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
865 #define ADC_ISR_AWD1_Pos               (7U)
866 #define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
867 #define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
868 #define ADC_ISR_AWD2_Pos               (8U)
869 #define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
870 #define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
871 #define ADC_ISR_AWD3_Pos               (9U)
872 #define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
873 #define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
874 #define ADC_ISR_EOCAL_Pos              (11U)
875 #define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
876 #define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
877 #define ADC_ISR_CCRDY_Pos              (13U)
878 #define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
879 #define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
880 
881 /* Legacy defines */
882 #define ADC_ISR_EOSEQ           (ADC_ISR_EOS)
883 
884 /********************  Bit definition for ADC_IER register  *******************/
885 #define ADC_IER_ADRDYIE_Pos            (0U)
886 #define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
887 #define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
888 #define ADC_IER_EOSMPIE_Pos            (1U)
889 #define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
890 #define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
891 #define ADC_IER_EOCIE_Pos              (2U)
892 #define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
893 #define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
894 #define ADC_IER_EOSIE_Pos              (3U)
895 #define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
896 #define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
897 #define ADC_IER_OVRIE_Pos              (4U)
898 #define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
899 #define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
900 #define ADC_IER_AWD1IE_Pos             (7U)
901 #define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
902 #define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
903 #define ADC_IER_AWD2IE_Pos             (8U)
904 #define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
905 #define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
906 #define ADC_IER_AWD3IE_Pos             (9U)
907 #define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
908 #define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
909 #define ADC_IER_EOCALIE_Pos            (11U)
910 #define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
911 #define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
912 #define ADC_IER_CCRDYIE_Pos            (13U)
913 #define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
914 #define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
915 
916 /* Legacy defines */
917 #define ADC_IER_EOSEQIE           (ADC_IER_EOSIE)
918 
919 /********************  Bit definition for ADC_CR register  ********************/
920 #define ADC_CR_ADEN_Pos                (0U)
921 #define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
922 #define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
923 #define ADC_CR_ADDIS_Pos               (1U)
924 #define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
925 #define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
926 #define ADC_CR_ADSTART_Pos             (2U)
927 #define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
928 #define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
929 #define ADC_CR_ADSTP_Pos               (4U)
930 #define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
931 #define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
932 #define ADC_CR_ADVREGEN_Pos            (28U)
933 #define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
934 #define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
935 #define ADC_CR_ADCAL_Pos               (31U)
936 #define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
937 #define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
938 
939 /********************  Bit definition for ADC_CFGR1 register  *****************/
940 #define ADC_CFGR1_DMAEN_Pos            (0U)
941 #define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
942 #define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
943 #define ADC_CFGR1_DMACFG_Pos           (1U)
944 #define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
945 #define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
946 
947 #define ADC_CFGR1_SCANDIR_Pos          (2U)
948 #define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
949 #define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
950 
951 #define ADC_CFGR1_RES_Pos              (3U)
952 #define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
953 #define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
954 #define ADC_CFGR1_RES_0                (0x1U << ADC_CFGR1_RES_Pos)             /*!< 0x00000008 */
955 #define ADC_CFGR1_RES_1                (0x2U << ADC_CFGR1_RES_Pos)             /*!< 0x00000010 */
956 
957 #define ADC_CFGR1_ALIGN_Pos            (5U)
958 #define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
959 #define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignment */
960 
961 #define ADC_CFGR1_EXTSEL_Pos           (6U)
962 #define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
963 #define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
964 #define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
965 #define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
966 #define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
967 
968 #define ADC_CFGR1_EXTEN_Pos            (10U)
969 #define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
970 #define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
971 #define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
972 #define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
973 
974 #define ADC_CFGR1_OVRMOD_Pos           (12U)
975 #define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
976 #define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
977 #define ADC_CFGR1_CONT_Pos             (13U)
978 #define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
979 #define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
980 #define ADC_CFGR1_WAIT_Pos             (14U)
981 #define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
982 #define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
983 #define ADC_CFGR1_AUTOFF_Pos           (15U)
984 #define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
985 #define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
986 #define ADC_CFGR1_DISCEN_Pos           (16U)
987 #define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
988 #define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
989 #define ADC_CFGR1_CHSELRMOD_Pos        (21U)
990 #define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
991 #define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
992 
993 #define ADC_CFGR1_AWD1SGL_Pos          (22U)
994 #define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
995 #define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
996 #define ADC_CFGR1_AWD1EN_Pos           (23U)
997 #define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
998 #define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
999 
1000 #define ADC_CFGR1_AWD1CH_Pos           (26U)
1001 #define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
1002 #define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
1003 #define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
1004 #define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
1005 #define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
1006 #define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
1007 #define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
1008 
1009 /* Legacy defines */
1010 #define ADC_CFGR1_AUTDLY          (ADC_CFGR1_WAIT)
1011 
1012 /********************  Bit definition for ADC_CFGR2 register  *****************/
1013 #define ADC_CFGR2_OVSE_Pos             (0U)
1014 #define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
1015 #define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
1016 
1017 #define ADC_CFGR2_OVSR_Pos             (2U)
1018 #define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
1019 #define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
1020 #define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
1021 #define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
1022 #define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
1023 
1024 #define ADC_CFGR2_OVSS_Pos             (5U)
1025 #define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
1026 #define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
1027 #define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
1028 #define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
1029 #define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
1030 #define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
1031 
1032 #define ADC_CFGR2_TOVS_Pos             (9U)
1033 #define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
1034 #define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
1035 
1036 #define ADC_CFGR2_LFTRIG_Pos           (29U)
1037 #define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
1038 #define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
1039 
1040 #define ADC_CFGR2_CKMODE_Pos           (30U)
1041 #define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
1042 #define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
1043 #define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
1044 #define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
1045 
1046 /********************  Bit definition for ADC_SMPR register  ******************/
1047 #define ADC_SMPR_SMP1_Pos              (0U)
1048 #define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
1049 #define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
1050 #define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
1051 #define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
1052 #define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
1053 
1054 #define ADC_SMPR_SMP2_Pos              (4U)
1055 #define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
1056 #define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
1057 #define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
1058 #define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
1059 #define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
1060 
1061 #define ADC_SMPR_SMPSEL_Pos            (8U)
1062 #define ADC_SMPR_SMPSEL_Msk            (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x07FFFF00 */
1063 #define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
1064 #define ADC_SMPR_SMPSEL0_Pos           (8U)
1065 #define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
1066 #define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
1067 #define ADC_SMPR_SMPSEL1_Pos           (9U)
1068 #define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
1069 #define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
1070 #define ADC_SMPR_SMPSEL2_Pos           (10U)
1071 #define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
1072 #define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
1073 #define ADC_SMPR_SMPSEL3_Pos           (11U)
1074 #define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
1075 #define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
1076 #define ADC_SMPR_SMPSEL4_Pos           (12U)
1077 #define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
1078 #define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
1079 #define ADC_SMPR_SMPSEL5_Pos           (13U)
1080 #define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
1081 #define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
1082 #define ADC_SMPR_SMPSEL6_Pos           (14U)
1083 #define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
1084 #define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
1085 #define ADC_SMPR_SMPSEL7_Pos           (15U)
1086 #define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
1087 #define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
1088 #define ADC_SMPR_SMPSEL8_Pos           (16U)
1089 #define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
1090 #define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
1091 #define ADC_SMPR_SMPSEL9_Pos           (17U)
1092 #define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
1093 #define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
1094 #define ADC_SMPR_SMPSEL10_Pos          (18U)
1095 #define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
1096 #define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
1097 #define ADC_SMPR_SMPSEL11_Pos          (19U)
1098 #define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
1099 #define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
1100 #define ADC_SMPR_SMPSEL12_Pos          (20U)
1101 #define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
1102 #define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
1103 #define ADC_SMPR_SMPSEL13_Pos          (21U)
1104 #define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
1105 #define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
1106 #define ADC_SMPR_SMPSEL14_Pos          (22U)
1107 #define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
1108 #define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
1109 #define ADC_SMPR_SMPSEL15_Pos          (23U)
1110 #define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
1111 #define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
1112 #define ADC_SMPR_SMPSEL16_Pos          (24U)
1113 #define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
1114 #define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
1115 #define ADC_SMPR_SMPSEL17_Pos          (25U)
1116 #define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
1117 #define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
1118 #define ADC_SMPR_SMPSEL18_Pos          (26U)
1119 #define ADC_SMPR_SMPSEL18_Msk          (0x1UL << ADC_SMPR_SMPSEL18_Pos)        /*!< 0x04000000 */
1120 #define ADC_SMPR_SMPSEL18              ADC_SMPR_SMPSEL18_Msk                   /*!< ADC channel 18 sampling time selection */
1121 
1122 /********************  Bit definition for ADC_AWD1TR register  *******************/
1123 #define ADC_AWD1TR_LT1_Pos                (0U)
1124 #define ADC_AWD1TR_LT1_Msk             (0xFFFUL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000FFF */
1125 #define ADC_AWD1TR_LT1                 ADC_AWD1TR_LT1_Msk                      /*!< ADC analog watchdog 1 threshold low */
1126 #define ADC_AWD1TR_LT1_0               (0x001UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000001 */
1127 #define ADC_AWD1TR_LT1_1               (0x002UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000002 */
1128 #define ADC_AWD1TR_LT1_2               (0x004UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000004 */
1129 #define ADC_AWD1TR_LT1_3               (0x008UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000008 */
1130 #define ADC_AWD1TR_LT1_4               (0x010UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000010 */
1131 #define ADC_AWD1TR_LT1_5               (0x020UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000020 */
1132 #define ADC_AWD1TR_LT1_6               (0x040UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000040 */
1133 #define ADC_AWD1TR_LT1_7               (0x080UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000080 */
1134 #define ADC_AWD1TR_LT1_8               (0x100UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000100 */
1135 #define ADC_AWD1TR_LT1_9               (0x200UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000200 */
1136 #define ADC_AWD1TR_LT1_10              (0x400UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000400 */
1137 #define ADC_AWD1TR_LT1_11              (0x800UL << ADC_AWD1TR_LT1_Pos)         /*!< 0x00000800 */
1138 
1139 #define ADC_AWD1TR_HT1_Pos             (16U)
1140 #define ADC_AWD1TR_HT1_Msk             (0xFFFUL << ADC_AWD1TR_HT1_Pos)         /*!< 0x0FFF0000 */
1141 #define ADC_AWD1TR_HT1                 ADC_AWD1TR_HT1_Msk                      /*!< ADC Analog watchdog 1 threshold high */
1142 #define ADC_AWD1TR_HT1_0               (0x001UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00010000 */
1143 #define ADC_AWD1TR_HT1_1               (0x002UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00020000 */
1144 #define ADC_AWD1TR_HT1_2               (0x004UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00040000 */
1145 #define ADC_AWD1TR_HT1_3               (0x008UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00080000 */
1146 #define ADC_AWD1TR_HT1_4               (0x010UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00100000 */
1147 #define ADC_AWD1TR_HT1_5               (0x020UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00200000 */
1148 #define ADC_AWD1TR_HT1_6               (0x040UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00400000 */
1149 #define ADC_AWD1TR_HT1_7               (0x080UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x00800000 */
1150 #define ADC_AWD1TR_HT1_8               (0x100UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x01000000 */
1151 #define ADC_AWD1TR_HT1_9               (0x200UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x02000000 */
1152 #define ADC_AWD1TR_HT1_10              (0x400UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x04000000 */
1153 #define ADC_AWD1TR_HT1_11              (0x800UL << ADC_AWD1TR_HT1_Pos)         /*!< 0x08000000 */
1154 
1155 /* Legacy definitions */
1156 #define ADC_TR1_LT1             ADC_AWD1TR_LT1
1157 #define ADC_TR1_LT1_0           ADC_AWD1TR_LT1_0
1158 #define ADC_TR1_LT1_1           ADC_AWD1TR_LT1_1
1159 #define ADC_TR1_LT1_2           ADC_AWD1TR_LT1_2
1160 #define ADC_TR1_LT1_3           ADC_AWD1TR_LT1_3
1161 #define ADC_TR1_LT1_4           ADC_AWD1TR_LT1_4
1162 #define ADC_TR1_LT1_5           ADC_AWD1TR_LT1_5
1163 #define ADC_TR1_LT1_6           ADC_AWD1TR_LT1_6
1164 #define ADC_TR1_LT1_7           ADC_AWD1TR_LT1_7
1165 #define ADC_TR1_LT1_8           ADC_AWD1TR_LT1_8
1166 #define ADC_TR1_LT1_9           ADC_AWD1TR_LT1_9
1167 #define ADC_TR1_LT1_10          ADC_AWD1TR_LT1_10
1168 #define ADC_TR1_LT1_11          ADC_AWD1TR_LT1_11
1169 
1170 #define ADC_TR1_HT1             ADC_AWD1TR_HT1
1171 #define ADC_TR1_HT1_0           ADC_AWD1TR_HT1_0
1172 #define ADC_TR1_HT1_1           ADC_AWD1TR_HT1_1
1173 #define ADC_TR1_HT1_2           ADC_AWD1TR_HT1_2
1174 #define ADC_TR1_HT1_3           ADC_AWD1TR_HT1_3
1175 #define ADC_TR1_HT1_4           ADC_AWD1TR_HT1_4
1176 #define ADC_TR1_HT1_5           ADC_AWD1TR_HT1_5
1177 #define ADC_TR1_HT1_6           ADC_AWD1TR_HT1_6
1178 #define ADC_TR1_HT1_7           ADC_AWD1TR_HT1_7
1179 #define ADC_TR1_HT1_8           ADC_AWD1TR_HT1_8
1180 #define ADC_TR1_HT1_9           ADC_AWD1TR_HT1_9
1181 #define ADC_TR1_HT1_10          ADC_AWD1TR_HT1_10
1182 #define ADC_TR1_HT1_11          ADC_AWD1TR_HT1_11
1183 
1184 /********************  Bit definition for ADC_AWD2TR register  *******************/
1185 #define ADC_AWD2TR_LT2_Pos             (0U)
1186 #define ADC_AWD2TR_LT2_Msk             (0xFFFUL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000FFF */
1187 #define ADC_AWD2TR_LT2                 ADC_AWD2TR_LT2_Msk                      /*!< ADC analog watchdog 2 threshold low */
1188 #define ADC_AWD2TR_LT2_0               (0x001UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000001 */
1189 #define ADC_AWD2TR_LT2_1               (0x002UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000002 */
1190 #define ADC_AWD2TR_LT2_2               (0x004UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000004 */
1191 #define ADC_AWD2TR_LT2_3               (0x008UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000008 */
1192 #define ADC_AWD2TR_LT2_4               (0x010UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000010 */
1193 #define ADC_AWD2TR_LT2_5               (0x020UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000020 */
1194 #define ADC_AWD2TR_LT2_6               (0x040UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000040 */
1195 #define ADC_AWD2TR_LT2_7               (0x080UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000080 */
1196 #define ADC_AWD2TR_LT2_8               (0x100UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000100 */
1197 #define ADC_AWD2TR_LT2_9               (0x200UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000200 */
1198 #define ADC_AWD2TR_LT2_10              (0x400UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000400 */
1199 #define ADC_AWD2TR_LT2_11              (0x800UL << ADC_AWD2TR_LT2_Pos)         /*!< 0x00000800 */
1200 
1201 #define ADC_AWD2TR_HT2_Pos             (16U)
1202 #define ADC_AWD2TR_HT2_Msk             (0xFFFUL << ADC_AWD2TR_HT2_Pos)         /*!< 0x0FFF0000 */
1203 #define ADC_AWD2TR_HT2                 ADC_AWD2TR_HT2_Msk                      /*!< ADC analog watchdog 2 threshold high */
1204 #define ADC_AWD2TR_HT2_0               (0x001UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00010000 */
1205 #define ADC_AWD2TR_HT2_1               (0x002UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00020000 */
1206 #define ADC_AWD2TR_HT2_2               (0x004UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00040000 */
1207 #define ADC_AWD2TR_HT2_3               (0x008UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00080000 */
1208 #define ADC_AWD2TR_HT2_4               (0x010UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00100000 */
1209 #define ADC_AWD2TR_HT2_5               (0x020UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00200000 */
1210 #define ADC_AWD2TR_HT2_6               (0x040UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00400000 */
1211 #define ADC_AWD2TR_HT2_7               (0x080UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x00800000 */
1212 #define ADC_AWD2TR_HT2_8               (0x100UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x01000000 */
1213 #define ADC_AWD2TR_HT2_9               (0x200UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x02000000 */
1214 #define ADC_AWD2TR_HT2_10              (0x400UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x04000000 */
1215 #define ADC_AWD2TR_HT2_11              (0x800UL << ADC_AWD2TR_HT2_Pos)         /*!< 0x08000000 */
1216 
1217 /* Legacy definitions */
1218 #define ADC_TR2_LT2             ADC_AWD2TR_LT2
1219 #define ADC_TR2_LT2_0           ADC_AWD2TR_LT2_0
1220 #define ADC_TR2_LT2_1           ADC_AWD2TR_LT2_1
1221 #define ADC_TR2_LT2_2           ADC_AWD2TR_LT2_2
1222 #define ADC_TR2_LT2_3           ADC_AWD2TR_LT2_3
1223 #define ADC_TR2_LT2_4           ADC_AWD2TR_LT2_4
1224 #define ADC_TR2_LT2_5           ADC_AWD2TR_LT2_5
1225 #define ADC_TR2_LT2_6           ADC_AWD2TR_LT2_6
1226 #define ADC_TR2_LT2_7           ADC_AWD2TR_LT2_7
1227 #define ADC_TR2_LT2_8           ADC_AWD2TR_LT2_8
1228 #define ADC_TR2_LT2_9           ADC_AWD2TR_LT2_9
1229 #define ADC_TR2_LT2_10          ADC_AWD2TR_LT2_10
1230 #define ADC_TR2_LT2_11          ADC_AWD2TR_LT2_11
1231 
1232 #define ADC_TR2_HT2             ADC_AWD2TR_HT2
1233 #define ADC_TR2_HT2_0           ADC_AWD2TR_HT2_0
1234 #define ADC_TR2_HT2_1           ADC_AWD2TR_HT2_1
1235 #define ADC_TR2_HT2_2           ADC_AWD2TR_HT2_2
1236 #define ADC_TR2_HT2_3           ADC_AWD2TR_HT2_3
1237 #define ADC_TR2_HT2_4           ADC_AWD2TR_HT2_4
1238 #define ADC_TR2_HT2_5           ADC_AWD2TR_HT2_5
1239 #define ADC_TR2_HT2_6           ADC_AWD2TR_HT2_6
1240 #define ADC_TR2_HT2_7           ADC_AWD2TR_HT2_7
1241 #define ADC_TR2_HT2_8           ADC_AWD2TR_HT2_8
1242 #define ADC_TR2_HT2_9           ADC_AWD2TR_HT2_9
1243 #define ADC_TR2_HT2_10          ADC_AWD2TR_HT2_10
1244 #define ADC_TR2_HT2_11          ADC_AWD2TR_HT2_11
1245 
1246 /********************  Bit definition for ADC_CHSELR register  ****************/
1247 #define ADC_CHSELR_CHSEL_Pos           (0U)
1248 #define ADC_CHSELR_CHSEL_Msk           (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0007FFFF */
1249 #define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
1250 #define ADC_CHSELR_CHSEL18_Pos         (18U)
1251 #define ADC_CHSELR_CHSEL18_Msk         (0x1UL << ADC_CHSELR_CHSEL18_Pos)       /*!< 0x00040000 */
1252 #define ADC_CHSELR_CHSEL18             ADC_CHSELR_CHSEL18_Msk                  /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
1253 #define ADC_CHSELR_CHSEL17_Pos         (17U)
1254 #define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
1255 #define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
1256 #define ADC_CHSELR_CHSEL16_Pos         (16U)
1257 #define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
1258 #define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
1259 #define ADC_CHSELR_CHSEL15_Pos         (15U)
1260 #define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
1261 #define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
1262 #define ADC_CHSELR_CHSEL14_Pos         (14U)
1263 #define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
1264 #define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
1265 #define ADC_CHSELR_CHSEL13_Pos         (13U)
1266 #define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
1267 #define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
1268 #define ADC_CHSELR_CHSEL12_Pos         (12U)
1269 #define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
1270 #define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
1271 #define ADC_CHSELR_CHSEL11_Pos         (11U)
1272 #define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
1273 #define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
1274 #define ADC_CHSELR_CHSEL10_Pos         (10U)
1275 #define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
1276 #define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
1277 #define ADC_CHSELR_CHSEL9_Pos          (9U)
1278 #define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
1279 #define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
1280 #define ADC_CHSELR_CHSEL8_Pos          (8U)
1281 #define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
1282 #define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
1283 #define ADC_CHSELR_CHSEL7_Pos          (7U)
1284 #define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
1285 #define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
1286 #define ADC_CHSELR_CHSEL6_Pos          (6U)
1287 #define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
1288 #define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
1289 #define ADC_CHSELR_CHSEL5_Pos          (5U)
1290 #define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
1291 #define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
1292 #define ADC_CHSELR_CHSEL4_Pos          (4U)
1293 #define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
1294 #define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
1295 #define ADC_CHSELR_CHSEL3_Pos          (3U)
1296 #define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
1297 #define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
1298 #define ADC_CHSELR_CHSEL2_Pos          (2U)
1299 #define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
1300 #define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
1301 #define ADC_CHSELR_CHSEL1_Pos          (1U)
1302 #define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
1303 #define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
1304 #define ADC_CHSELR_CHSEL0_Pos          (0U)
1305 #define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
1306 #define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
1307 
1308 #define ADC_CHSELR_SQ_ALL_Pos          (0U)
1309 #define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
1310 #define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
1311 
1312 #define ADC_CHSELR_SQ8_Pos             (28U)
1313 #define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
1314 #define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
1315 #define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
1316 #define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
1317 #define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
1318 #define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
1319 
1320 #define ADC_CHSELR_SQ7_Pos             (24U)
1321 #define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
1322 #define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
1323 #define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
1324 #define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
1325 #define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
1326 #define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
1327 
1328 #define ADC_CHSELR_SQ6_Pos             (20U)
1329 #define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
1330 #define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
1331 #define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
1332 #define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
1333 #define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
1334 #define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
1335 
1336 #define ADC_CHSELR_SQ5_Pos             (16U)
1337 #define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
1338 #define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
1339 #define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
1340 #define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
1341 #define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
1342 #define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
1343 
1344 #define ADC_CHSELR_SQ4_Pos             (12U)
1345 #define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
1346 #define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
1347 #define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
1348 #define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
1349 #define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
1350 #define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
1351 
1352 #define ADC_CHSELR_SQ3_Pos             (8U)
1353 #define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
1354 #define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
1355 #define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
1356 #define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
1357 #define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
1358 #define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
1359 
1360 #define ADC_CHSELR_SQ2_Pos             (4U)
1361 #define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
1362 #define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
1363 #define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
1364 #define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
1365 #define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
1366 #define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
1367 
1368 #define ADC_CHSELR_SQ1_Pos             (0U)
1369 #define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
1370 #define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
1371 #define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
1372 #define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
1373 #define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
1374 #define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
1375 
1376 /********************  Bit definition for ADC_AWD3TR register  *******************/
1377 #define ADC_AWD3TR_LT3_Pos             (0U)
1378 #define ADC_AWD3TR_LT3_Msk             (0xFFFUL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000FFF */
1379 #define ADC_AWD3TR_LT3                 ADC_AWD3TR_LT3_Msk                      /*!< ADC analog watchdog 3 threshold low */
1380 #define ADC_AWD3TR_LT3_0               (0x001UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000001 */
1381 #define ADC_AWD3TR_LT3_1               (0x002UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000002 */
1382 #define ADC_AWD3TR_LT3_2               (0x004UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000004 */
1383 #define ADC_AWD3TR_LT3_3               (0x008UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000008 */
1384 #define ADC_AWD3TR_LT3_4               (0x010UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000010 */
1385 #define ADC_AWD3TR_LT3_5               (0x020UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000020 */
1386 #define ADC_AWD3TR_LT3_6               (0x040UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000040 */
1387 #define ADC_AWD3TR_LT3_7               (0x080UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000080 */
1388 #define ADC_AWD3TR_LT3_8               (0x100UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000100 */
1389 #define ADC_AWD3TR_LT3_9               (0x200UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000200 */
1390 #define ADC_AWD3TR_LT3_10              (0x400UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000400 */
1391 #define ADC_AWD3TR_LT3_11              (0x800UL << ADC_AWD3TR_LT3_Pos)         /*!< 0x00000800 */
1392 
1393 #define ADC_AWD3TR_HT3_Pos             (16U)
1394 #define ADC_AWD3TR_HT3_Msk             (0xFFFUL << ADC_AWD3TR_HT3_Pos)         /*!< 0x0FFF0000 */
1395 #define ADC_AWD3TR_HT3                 ADC_AWD3TR_HT3_Msk                      /*!< ADC analog watchdog 3 threshold high */
1396 #define ADC_AWD3TR_HT3_0               (0x001UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00010000 */
1397 #define ADC_AWD3TR_HT3_1               (0x002UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00020000 */
1398 #define ADC_AWD3TR_HT3_2               (0x004UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00040000 */
1399 #define ADC_AWD3TR_HT3_3               (0x008UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00080000 */
1400 #define ADC_AWD3TR_HT3_4               (0x010UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00100000 */
1401 #define ADC_AWD3TR_HT3_5               (0x020UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00200000 */
1402 #define ADC_AWD3TR_HT3_6               (0x040UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00400000 */
1403 #define ADC_AWD3TR_HT3_7               (0x080UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x00800000 */
1404 #define ADC_AWD3TR_HT3_8               (0x100UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x01000000 */
1405 #define ADC_AWD3TR_HT3_9               (0x200UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x02000000 */
1406 #define ADC_AWD3TR_HT3_10              (0x400UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x04000000 */
1407 #define ADC_AWD3TR_HT3_11              (0x800UL << ADC_AWD3TR_HT3_Pos)         /*!< 0x08000000 */
1408 
1409 /* Legacy definitions */
1410 #define ADC_TR3_LT3             ADC_AWD3TR_LT3
1411 #define ADC_TR3_LT3_0           ADC_AWD3TR_LT3_0
1412 #define ADC_TR3_LT3_1           ADC_AWD3TR_LT3_1
1413 #define ADC_TR3_LT3_2           ADC_AWD3TR_LT3_2
1414 #define ADC_TR3_LT3_3           ADC_AWD3TR_LT3_3
1415 #define ADC_TR3_LT3_4           ADC_AWD3TR_LT3_4
1416 #define ADC_TR3_LT3_5           ADC_AWD3TR_LT3_5
1417 #define ADC_TR3_LT3_6           ADC_AWD3TR_LT3_6
1418 #define ADC_TR3_LT3_7           ADC_AWD3TR_LT3_7
1419 #define ADC_TR3_LT3_8           ADC_AWD3TR_LT3_8
1420 #define ADC_TR3_LT3_9           ADC_AWD3TR_LT3_9
1421 #define ADC_TR3_LT3_10          ADC_AWD3TR_LT3_10
1422 #define ADC_TR3_LT3_11          ADC_AWD3TR_LT3_11
1423 
1424 #define ADC_TR3_HT3             ADC_AWD3TR_HT3
1425 #define ADC_TR3_HT3_0           ADC_AWD3TR_HT3_0
1426 #define ADC_TR3_HT3_1           ADC_AWD3TR_HT3_1
1427 #define ADC_TR3_HT3_2           ADC_AWD3TR_HT3_2
1428 #define ADC_TR3_HT3_3           ADC_AWD3TR_HT3_3
1429 #define ADC_TR3_HT3_4           ADC_AWD3TR_HT3_4
1430 #define ADC_TR3_HT3_5           ADC_AWD3TR_HT3_5
1431 #define ADC_TR3_HT3_6           ADC_AWD3TR_HT3_6
1432 #define ADC_TR3_HT3_7           ADC_AWD3TR_HT3_7
1433 #define ADC_TR3_HT3_8           ADC_AWD3TR_HT3_8
1434 #define ADC_TR3_HT3_9           ADC_AWD3TR_HT3_9
1435 #define ADC_TR3_HT3_10          ADC_AWD3TR_HT3_10
1436 #define ADC_TR3_HT3_11          ADC_AWD3TR_HT3_11
1437 
1438 /********************  Bit definition for ADC_DR register  ********************/
1439 #define ADC_DR_DATA_Pos                (0U)
1440 #define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
1441 #define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
1442 #define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
1443 #define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
1444 #define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
1445 #define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
1446 #define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
1447 #define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
1448 #define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
1449 #define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
1450 #define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
1451 #define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
1452 #define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
1453 #define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
1454 #define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
1455 #define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
1456 #define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
1457 #define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
1458 
1459 /********************  Bit definition for ADC_AWD2CR register  ****************/
1460 #define ADC_AWD2CR_AWD2CH_Pos          (0U)
1461 #define ADC_AWD2CR_AWD2CH_Msk          (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0007FFFF */
1462 #define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
1463 #define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
1464 #define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
1465 #define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
1466 #define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
1467 #define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
1468 #define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
1469 #define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
1470 #define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
1471 #define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
1472 #define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
1473 #define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
1474 #define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
1475 #define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
1476 #define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
1477 #define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
1478 #define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
1479 #define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
1480 #define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
1481 #define ADC_AWD2CR_AWD2CH_18           (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00040000 */
1482 
1483 /********************  Bit definition for ADC_AWD3CR register  ****************/
1484 #define ADC_AWD3CR_AWD3CH_Pos          (0U)
1485 #define ADC_AWD3CR_AWD3CH_Msk          (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0007FFFF */
1486 #define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
1487 #define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
1488 #define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
1489 #define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
1490 #define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
1491 #define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
1492 #define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
1493 #define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
1494 #define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
1495 #define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
1496 #define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
1497 #define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
1498 #define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
1499 #define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
1500 #define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
1501 #define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
1502 #define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
1503 #define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
1504 #define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
1505 #define ADC_AWD3CR_AWD3CH_18           (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00040000 */
1506 
1507 /********************  Bit definition for ADC_CALFACT register  ***************/
1508 #define ADC_CALFACT_CALFACT_Pos        (0U)
1509 #define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
1510 #define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
1511 #define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
1512 #define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
1513 #define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
1514 #define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
1515 #define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
1516 #define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
1517 #define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
1518 
1519 /*************************  ADC Common registers  *****************************/
1520 /********************  Bit definition for ADC_CCR register  *******************/
1521 #define ADC_CCR_PRESC_Pos              (18U)
1522 #define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
1523 #define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
1524 #define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
1525 #define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
1526 #define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
1527 #define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
1528 
1529 #define ADC_CCR_VREFEN_Pos             (22U)
1530 #define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
1531 #define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
1532 #define ADC_CCR_TSEN_Pos               (23U)
1533 #define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
1534 #define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
1535 #define ADC_CCR_VBATEN_Pos             (24U)
1536 #define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
1537 #define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
1538 
1539 /* Legacy */
1540 #define ADC_CCR_LFMEN_Pos              (25U)
1541 #define ADC_CCR_LFMEN_Msk              (0x1UL << ADC_CCR_LFMEN_Pos)            /*!< 0x02000000 */
1542 #define ADC_CCR_LFMEN                  ADC_CCR_LFMEN_Msk                       /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
1543 
1544 /******************************************************************************/
1545 /*                                                                            */
1546 /*                                 HDMI-CEC (CEC)                             */
1547 /*                                                                            */
1548 /******************************************************************************/
1549 
1550 /*******************  Bit definition for CEC_CR register  *********************/
1551 #define CEC_CR_CECEN_Pos         (0U)
1552 #define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                    /*!< 0x00000001 */
1553 #define CEC_CR_CECEN             CEC_CR_CECEN_Msk                               /*!< CEC Enable                         */
1554 #define CEC_CR_TXSOM_Pos         (1U)
1555 #define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                    /*!< 0x00000002 */
1556 #define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                               /*!< CEC Tx Start Of Message            */
1557 #define CEC_CR_TXEOM_Pos         (2U)
1558 #define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                    /*!< 0x00000004 */
1559 #define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                               /*!< CEC Tx End Of Message              */
1560 
1561 /*******************  Bit definition for CEC_CFGR register  *******************/
1562 #define CEC_CFGR_SFT_Pos         (0U)
1563 #define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                    /*!< 0x00000007 */
1564 #define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                               /*!< CEC Signal Free Time               */
1565 #define CEC_CFGR_RXTOL_Pos       (3U)
1566 #define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                  /*!< 0x00000008 */
1567 #define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                             /*!< CEC Tolerance                      */
1568 #define CEC_CFGR_BRESTP_Pos      (4U)
1569 #define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                 /*!< 0x00000010 */
1570 #define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                            /*!< CEC Rx Stop                        */
1571 #define CEC_CFGR_BREGEN_Pos      (5U)
1572 #define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                 /*!< 0x00000020 */
1573 #define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                            /*!< CEC Bit Rising Error generation    */
1574 #define CEC_CFGR_LBPEGEN_Pos     (6U)
1575 #define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)                /*!< 0x00000040 */
1576 #define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                           /*!< CEC Long Bit Period Error gener.   */
1577 #define CEC_CFGR_BRDNOGEN_Pos    (7U)
1578 #define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)               /*!< 0x00000080 */
1579 #define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                          /*!< CEC Broadcast No Error generation  */
1580 #define CEC_CFGR_SFTOPT_Pos      (8U)
1581 #define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                 /*!< 0x00000100 */
1582 #define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                            /*!< CEC Signal Free Time optional      */
1583 #define CEC_CFGR_OAR_Pos         (16U)
1584 #define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                 /*!< 0x7FFF0000 */
1585 #define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                               /*!< CEC Own Address                    */
1586 #define CEC_CFGR_LSTN_Pos        (31U)
1587 #define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                   /*!< 0x80000000 */
1588 #define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                              /*!< CEC Listen mode                    */
1589 
1590 /*******************  Bit definition for CEC_TXDR register  *******************/
1591 #define CEC_TXDR_TXD_Pos         (0U)
1592 #define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                   /*!< 0x000000FF */
1593 #define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                               /*!< CEC Tx Data                        */
1594 
1595 /*******************  Bit definition for CEC_RXDR register  *******************/
1596 #define CEC_RXDR_RXD_Pos         (0U)
1597 #define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                   /*!< 0x000000FF */
1598 #define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                               /*!< CEC Rx Data                        */
1599 
1600 /*******************  Bit definition for CEC_ISR register  ********************/
1601 #define CEC_ISR_RXBR_Pos         (0U)
1602 #define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                    /*!< 0x00000001 */
1603 #define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                               /*!< CEC Rx-Byte Received                   */
1604 #define CEC_ISR_RXEND_Pos        (1U)
1605 #define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                   /*!< 0x00000002 */
1606 #define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                              /*!< CEC End Of Reception                   */
1607 #define CEC_ISR_RXOVR_Pos        (2U)
1608 #define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                   /*!< 0x00000004 */
1609 #define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                              /*!< CEC Rx-Overrun                         */
1610 #define CEC_ISR_BRE_Pos          (3U)
1611 #define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                     /*!< 0x00000008 */
1612 #define CEC_ISR_BRE              CEC_ISR_BRE_Msk                                /*!< CEC Rx Bit Rising Error                */
1613 #define CEC_ISR_SBPE_Pos         (4U)
1614 #define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                    /*!< 0x00000010 */
1615 #define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                               /*!< CEC Rx Short Bit period Error          */
1616 #define CEC_ISR_LBPE_Pos         (5U)
1617 #define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                    /*!< 0x00000020 */
1618 #define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                               /*!< CEC Rx Long Bit period Error           */
1619 #define CEC_ISR_RXACKE_Pos       (6U)
1620 #define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                  /*!< 0x00000040 */
1621 #define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                             /*!< CEC Rx Missing Acknowledge             */
1622 #define CEC_ISR_ARBLST_Pos       (7U)
1623 #define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                  /*!< 0x00000080 */
1624 #define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                             /*!< CEC Arbitration Lost                   */
1625 #define CEC_ISR_TXBR_Pos         (8U)
1626 #define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                    /*!< 0x00000100 */
1627 #define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                               /*!< CEC Tx Byte Request                    */
1628 #define CEC_ISR_TXEND_Pos        (9U)
1629 #define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                   /*!< 0x00000200 */
1630 #define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                              /*!< CEC End of Transmission                */
1631 #define CEC_ISR_TXUDR_Pos        (10U)
1632 #define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                   /*!< 0x00000400 */
1633 #define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                              /*!< CEC Tx-Buffer Underrun                 */
1634 #define CEC_ISR_TXERR_Pos        (11U)
1635 #define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                   /*!< 0x00000800 */
1636 #define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                              /*!< CEC Tx-Error                           */
1637 #define CEC_ISR_TXACKE_Pos       (12U)
1638 #define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                  /*!< 0x00001000 */
1639 #define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                             /*!< CEC Tx Missing Acknowledge             */
1640 
1641 /*******************  Bit definition for CEC_IER register  ********************/
1642 #define CEC_IER_RXBRIE_Pos       (0U)
1643 #define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                  /*!< 0x00000001 */
1644 #define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                             /*!< CEC Rx-Byte Received IT Enable         */
1645 #define CEC_IER_RXENDIE_Pos      (1U)
1646 #define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                 /*!< 0x00000002 */
1647 #define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                            /*!< CEC End Of Reception IT Enable         */
1648 #define CEC_IER_RXOVRIE_Pos      (2U)
1649 #define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                 /*!< 0x00000004 */
1650 #define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                            /*!< CEC Rx-Overrun IT Enable               */
1651 #define CEC_IER_BREIE_Pos        (3U)
1652 #define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                   /*!< 0x00000008 */
1653 #define CEC_IER_BREIE            CEC_IER_BREIE_Msk                              /*!< CEC Rx Bit Rising Error IT Enable      */
1654 #define CEC_IER_SBPEIE_Pos       (4U)
1655 #define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                  /*!< 0x00000010 */
1656 #define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                             /*!< CEC Rx Short Bit period Error IT Enable*/
1657 #define CEC_IER_LBPEIE_Pos       (5U)
1658 #define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                  /*!< 0x00000020 */
1659 #define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                             /*!< CEC Rx Long Bit period Error IT Enable */
1660 #define CEC_IER_RXACKEIE_Pos     (6U)
1661 #define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)                /*!< 0x00000040 */
1662 #define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                           /*!< CEC Rx Missing Acknowledge IT Enable   */
1663 #define CEC_IER_ARBLSTIE_Pos     (7U)
1664 #define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)                /*!< 0x00000080 */
1665 #define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                           /*!< CEC Arbitration Lost IT Enable         */
1666 #define CEC_IER_TXBRIE_Pos       (8U)
1667 #define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                  /*!< 0x00000100 */
1668 #define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                             /*!< CEC Tx Byte Request  IT Enable         */
1669 #define CEC_IER_TXENDIE_Pos      (9U)
1670 #define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                 /*!< 0x00000200 */
1671 #define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                            /*!< CEC End of Transmission IT Enable      */
1672 #define CEC_IER_TXUDRIE_Pos      (10U)
1673 #define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                 /*!< 0x00000400 */
1674 #define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                            /*!< CEC Tx-Buffer Underrun IT Enable       */
1675 #define CEC_IER_TXERRIE_Pos      (11U)
1676 #define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                 /*!< 0x00000800 */
1677 #define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                            /*!< CEC Tx-Error IT Enable                 */
1678 #define CEC_IER_TXACKEIE_Pos     (12U)
1679 #define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)                /*!< 0x00001000 */
1680 #define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                           /*!< CEC Tx Missing Acknowledge IT Enable   */
1681 
1682 /******************************************************************************/
1683 /*                                                                            */
1684 /*                          CRC calculation unit                              */
1685 /*                                                                            */
1686 /******************************************************************************/
1687 /*******************  Bit definition for CRC_DR register  *********************/
1688 #define CRC_DR_DR_Pos            (0U)
1689 #define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)                /*!< 0xFFFFFFFF */
1690 #define CRC_DR_DR                CRC_DR_DR_Msk                                  /*!< Data register bits */
1691 
1692 /*******************  Bit definition for CRC_IDR register  ********************/
1693 #define CRC_IDR_IDR_Pos          (0U)
1694 #define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)              /*!< 0xFFFFFFFF */
1695 #define CRC_IDR_IDR              CRC_IDR_IDR_Msk                                /*!< General-purpose 32-bits data register bits */
1696 
1697 /********************  Bit definition for CRC_CR register  ********************/
1698 #define CRC_CR_RESET_Pos         (0U)
1699 #define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                    /*!< 0x00000001 */
1700 #define CRC_CR_RESET             CRC_CR_RESET_Msk                               /*!< RESET the CRC computation unit bit */
1701 #define CRC_CR_POLYSIZE_Pos      (3U)
1702 #define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000018 */
1703 #define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                            /*!< Polynomial size bits */
1704 #define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
1705 #define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
1706 #define CRC_CR_REV_IN_Pos        (5U)
1707 #define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000060 */
1708 #define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                              /*!< REV_IN Reverse Input Data bits */
1709 #define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
1710 #define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
1711 #define CRC_CR_REV_OUT_Pos       (7U)
1712 #define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                  /*!< 0x00000080 */
1713 #define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                             /*!< REV_OUT Reverse Output Data bits */
1714 
1715 /*******************  Bit definition for CRC_INIT register  *******************/
1716 #define CRC_INIT_INIT_Pos        (0U)
1717 #define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)            /*!< 0xFFFFFFFF */
1718 #define CRC_INIT_INIT            CRC_INIT_INIT_Msk                              /*!< Initial CRC value bits */
1719 
1720 /*******************  Bit definition for CRC_POL register  ********************/
1721 #define CRC_POL_POL_Pos          (0U)
1722 #define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)              /*!< 0xFFFFFFFF */
1723 #define CRC_POL_POL              CRC_POL_POL_Msk                                /*!< Coefficients of the polynomial */
1724 
1725 
1726 /******************************************************************************/
1727 /*                                                                            */
1728 /*                      Digital to Analog Converter                           */
1729 /*                                                                            */
1730 /******************************************************************************/
1731 /*
1732 * @brief Specific device feature definitions
1733 */
1734 #define DAC_ADDITIONAL_TRIGGERS_SUPPORT
1735 
1736 /********************  Bit definition for DAC_CR register  ********************/
1737 #define DAC_CR_EN1_Pos              (0U)
1738 #define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
1739 #define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
1740 #define DAC_CR_TEN1_Pos             (1U)
1741 #define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
1742 #define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
1743 
1744 #define DAC_CR_TSEL1_Pos            (2U)
1745 #define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
1746 #define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
1747 #define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
1748 #define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
1749 #define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
1750 #define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
1751 
1752 #define DAC_CR_WAVE1_Pos            (6U)
1753 #define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
1754 #define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1755 #define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
1756 #define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
1757 
1758 #define DAC_CR_MAMP1_Pos            (8U)
1759 #define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
1760 #define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1761 #define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
1762 #define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
1763 #define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
1764 #define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
1765 
1766 #define DAC_CR_DMAEN1_Pos           (12U)
1767 #define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
1768 #define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
1769 #define DAC_CR_DMAUDRIE1_Pos        (13U)
1770 #define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
1771 #define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
1772 #define DAC_CR_CEN1_Pos             (14U)
1773 #define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
1774 #define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
1775 
1776 #define DAC_CR_EN2_Pos              (16U)
1777 #define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
1778 #define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
1779 #define DAC_CR_TEN2_Pos             (17U)
1780 #define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
1781 #define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
1782 
1783 #define DAC_CR_TSEL2_Pos            (18U)
1784 #define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
1785 #define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1786 #define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
1787 #define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
1788 #define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
1789 #define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                /*!< 0x00200000 */
1790 
1791 #define DAC_CR_WAVE2_Pos            (22U)
1792 #define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
1793 #define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1794 #define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
1795 #define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
1796 
1797 #define DAC_CR_MAMP2_Pos            (24U)
1798 #define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
1799 #define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1800 #define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
1801 #define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
1802 #define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
1803 #define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
1804 
1805 #define DAC_CR_DMAEN2_Pos           (28U)
1806 #define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
1807 #define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
1808 #define DAC_CR_DMAUDRIE2_Pos        (29U)
1809 #define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
1810 #define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
1811 #define DAC_CR_CEN2_Pos             (30U)
1812 #define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
1813 #define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
1814 
1815 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1816 #define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
1817 #define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
1818 #define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
1819 #define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
1820 #define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
1821 #define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
1822 
1823 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1824 #define DAC_DHR12R1_DACC1DHR_Pos    (0U)
1825 #define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
1826 #define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1827 
1828 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1829 #define DAC_DHR12L1_DACC1DHR_Pos    (4U)
1830 #define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
1831 #define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1832 
1833 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1834 #define DAC_DHR8R1_DACC1DHR_Pos     (0U)
1835 #define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
1836 #define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1837 
1838 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
1839 #define DAC_DHR12R2_DACC2DHR_Pos    (0U)
1840 #define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
1841 #define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1842 
1843 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
1844 #define DAC_DHR12L2_DACC2DHR_Pos    (4U)
1845 #define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
1846 #define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1847 
1848 /******************  Bit definition for DAC_DHR8R2 register  ******************/
1849 #define DAC_DHR8R2_DACC2DHR_Pos     (0U)
1850 #define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
1851 #define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1852 
1853 /*****************  Bit definition for DAC_DHR12RD register  ******************/
1854 #define DAC_DHR12RD_DACC1DHR_Pos    (0U)
1855 #define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
1856 #define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
1857 #define DAC_DHR12RD_DACC2DHR_Pos    (16U)
1858 #define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
1859 #define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
1860 
1861 /*****************  Bit definition for DAC_DHR12LD register  ******************/
1862 #define DAC_DHR12LD_DACC1DHR_Pos    (4U)
1863 #define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
1864 #define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
1865 #define DAC_DHR12LD_DACC2DHR_Pos    (20U)
1866 #define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
1867 #define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
1868 
1869 /******************  Bit definition for DAC_DHR8RD register  ******************/
1870 #define DAC_DHR8RD_DACC1DHR_Pos     (0U)
1871 #define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
1872 #define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
1873 #define DAC_DHR8RD_DACC2DHR_Pos     (8U)
1874 #define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
1875 #define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
1876 
1877 /*******************  Bit definition for DAC_DOR1 register  *******************/
1878 #define DAC_DOR1_DACC1DOR_Pos       (0U)
1879 #define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
1880 #define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
1881 
1882 /*******************  Bit definition for DAC_DOR2 register  *******************/
1883 #define DAC_DOR2_DACC2DOR_Pos       (0U)
1884 #define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
1885 #define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
1886 
1887 /********************  Bit definition for DAC_SR register  ********************/
1888 #define DAC_SR_DMAUDR1_Pos          (13U)
1889 #define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
1890 #define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
1891 #define DAC_SR_CAL_FLAG1_Pos        (14U)
1892 #define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
1893 #define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
1894 #define DAC_SR_BWST1_Pos            (15U)
1895 #define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
1896 #define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
1897 
1898 #define DAC_SR_DMAUDR2_Pos          (29U)
1899 #define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
1900 #define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
1901 #define DAC_SR_CAL_FLAG2_Pos        (30U)
1902 #define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
1903 #define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
1904 #define DAC_SR_BWST2_Pos            (31U)
1905 #define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
1906 #define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
1907 
1908 /*******************  Bit definition for DAC_CCR register  ********************/
1909 #define DAC_CCR_OTRIM1_Pos          (0U)
1910 #define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
1911 #define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
1912 #define DAC_CCR_OTRIM2_Pos          (16U)
1913 #define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
1914 #define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
1915 
1916 /*******************  Bit definition for DAC_MCR register  *******************/
1917 #define DAC_MCR_MODE1_Pos           (0U)
1918 #define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
1919 #define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
1920 #define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
1921 #define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
1922 #define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
1923 
1924 #define DAC_MCR_MODE2_Pos           (16U)
1925 #define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
1926 #define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
1927 #define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
1928 #define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
1929 #define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
1930 
1931 /******************  Bit definition for DAC_SHSR1 register  ******************/
1932 #define DAC_SHSR1_TSAMPLE1_Pos      (0U)
1933 #define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
1934 #define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
1935 
1936 /******************  Bit definition for DAC_SHSR2 register  ******************/
1937 #define DAC_SHSR2_TSAMPLE2_Pos      (0U)
1938 #define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
1939 #define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
1940 
1941 /******************  Bit definition for DAC_SHHR register  ******************/
1942 #define DAC_SHHR_THOLD1_Pos         (0U)
1943 #define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
1944 #define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
1945 #define DAC_SHHR_THOLD2_Pos         (16U)
1946 #define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
1947 #define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
1948 
1949 /******************  Bit definition for DAC_SHRR register  ******************/
1950 #define DAC_SHRR_TREFRESH1_Pos      (0U)
1951 #define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
1952 #define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
1953 #define DAC_SHRR_TREFRESH2_Pos      (16U)
1954 #define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
1955 #define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
1956 
1957 
1958 /******************************************************************************/
1959 /*                                                                            */
1960 /*                                 Debug MCU                                  */
1961 /*                                                                            */
1962 /******************************************************************************/
1963 
1964 /******************************************************************************/
1965 /*                                                                            */
1966 /*                           DMA Controller (DMA)                             */
1967 /*                                                                            */
1968 /******************************************************************************/
1969 
1970 /*******************  Bit definition for DMA_ISR register  ********************/
1971 #define DMA_ISR_GIF1_Pos       (0U)
1972 #define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
1973 #define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
1974 #define DMA_ISR_TCIF1_Pos      (1U)
1975 #define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
1976 #define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
1977 #define DMA_ISR_HTIF1_Pos      (2U)
1978 #define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
1979 #define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
1980 #define DMA_ISR_TEIF1_Pos      (3U)
1981 #define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
1982 #define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
1983 #define DMA_ISR_GIF2_Pos       (4U)
1984 #define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
1985 #define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
1986 #define DMA_ISR_TCIF2_Pos      (5U)
1987 #define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
1988 #define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
1989 #define DMA_ISR_HTIF2_Pos      (6U)
1990 #define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
1991 #define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
1992 #define DMA_ISR_TEIF2_Pos      (7U)
1993 #define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
1994 #define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
1995 #define DMA_ISR_GIF3_Pos       (8U)
1996 #define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
1997 #define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
1998 #define DMA_ISR_TCIF3_Pos      (9U)
1999 #define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
2000 #define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
2001 #define DMA_ISR_HTIF3_Pos      (10U)
2002 #define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
2003 #define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
2004 #define DMA_ISR_TEIF3_Pos      (11U)
2005 #define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
2006 #define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
2007 #define DMA_ISR_GIF4_Pos       (12U)
2008 #define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
2009 #define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
2010 #define DMA_ISR_TCIF4_Pos      (13U)
2011 #define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
2012 #define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
2013 #define DMA_ISR_HTIF4_Pos      (14U)
2014 #define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
2015 #define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
2016 #define DMA_ISR_TEIF4_Pos      (15U)
2017 #define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
2018 #define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
2019 #define DMA_ISR_GIF5_Pos       (16U)
2020 #define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
2021 #define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
2022 #define DMA_ISR_TCIF5_Pos      (17U)
2023 #define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
2024 #define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
2025 #define DMA_ISR_HTIF5_Pos      (18U)
2026 #define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
2027 #define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
2028 #define DMA_ISR_TEIF5_Pos      (19U)
2029 #define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
2030 #define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
2031 #define DMA_ISR_GIF6_Pos       (20U)
2032 #define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
2033 #define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
2034 #define DMA_ISR_TCIF6_Pos      (21U)
2035 #define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
2036 #define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
2037 #define DMA_ISR_HTIF6_Pos      (22U)
2038 #define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
2039 #define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
2040 #define DMA_ISR_TEIF6_Pos      (23U)
2041 #define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
2042 #define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
2043 #define DMA_ISR_GIF7_Pos       (24U)
2044 #define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
2045 #define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
2046 #define DMA_ISR_TCIF7_Pos      (25U)
2047 #define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
2048 #define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
2049 #define DMA_ISR_HTIF7_Pos      (26U)
2050 #define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
2051 #define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
2052 #define DMA_ISR_TEIF7_Pos      (27U)
2053 #define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
2054 #define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
2055 
2056 /*******************  Bit definition for DMA_IFCR register  *******************/
2057 #define DMA_IFCR_CGIF1_Pos     (0U)
2058 #define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
2059 #define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clearr */
2060 #define DMA_IFCR_CTCIF1_Pos    (1U)
2061 #define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
2062 #define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
2063 #define DMA_IFCR_CHTIF1_Pos    (2U)
2064 #define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
2065 #define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
2066 #define DMA_IFCR_CTEIF1_Pos    (3U)
2067 #define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
2068 #define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
2069 #define DMA_IFCR_CGIF2_Pos     (4U)
2070 #define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
2071 #define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
2072 #define DMA_IFCR_CTCIF2_Pos    (5U)
2073 #define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
2074 #define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
2075 #define DMA_IFCR_CHTIF2_Pos    (6U)
2076 #define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
2077 #define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
2078 #define DMA_IFCR_CTEIF2_Pos    (7U)
2079 #define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
2080 #define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
2081 #define DMA_IFCR_CGIF3_Pos     (8U)
2082 #define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
2083 #define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
2084 #define DMA_IFCR_CTCIF3_Pos    (9U)
2085 #define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
2086 #define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
2087 #define DMA_IFCR_CHTIF3_Pos    (10U)
2088 #define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
2089 #define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
2090 #define DMA_IFCR_CTEIF3_Pos    (11U)
2091 #define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
2092 #define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
2093 #define DMA_IFCR_CGIF4_Pos     (12U)
2094 #define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
2095 #define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
2096 #define DMA_IFCR_CTCIF4_Pos    (13U)
2097 #define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
2098 #define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
2099 #define DMA_IFCR_CHTIF4_Pos    (14U)
2100 #define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
2101 #define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
2102 #define DMA_IFCR_CTEIF4_Pos    (15U)
2103 #define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
2104 #define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
2105 #define DMA_IFCR_CGIF5_Pos     (16U)
2106 #define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
2107 #define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
2108 #define DMA_IFCR_CTCIF5_Pos    (17U)
2109 #define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
2110 #define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
2111 #define DMA_IFCR_CHTIF5_Pos    (18U)
2112 #define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
2113 #define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
2114 #define DMA_IFCR_CTEIF5_Pos    (19U)
2115 #define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
2116 #define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
2117 #define DMA_IFCR_CGIF6_Pos     (20U)
2118 #define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
2119 #define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
2120 #define DMA_IFCR_CTCIF6_Pos    (21U)
2121 #define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
2122 #define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
2123 #define DMA_IFCR_CHTIF6_Pos    (22U)
2124 #define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
2125 #define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
2126 #define DMA_IFCR_CTEIF6_Pos    (23U)
2127 #define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
2128 #define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
2129 #define DMA_IFCR_CGIF7_Pos     (24U)
2130 #define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
2131 #define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
2132 #define DMA_IFCR_CTCIF7_Pos    (25U)
2133 #define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
2134 #define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
2135 #define DMA_IFCR_CHTIF7_Pos    (26U)
2136 #define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
2137 #define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
2138 #define DMA_IFCR_CTEIF7_Pos    (27U)
2139 #define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
2140 #define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
2141 
2142 /*******************  Bit definition for DMA_CCR register  ********************/
2143 #define DMA_CCR_EN_Pos         (0U)
2144 #define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
2145 #define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
2146 #define DMA_CCR_TCIE_Pos       (1U)
2147 #define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
2148 #define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
2149 #define DMA_CCR_HTIE_Pos       (2U)
2150 #define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
2151 #define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
2152 #define DMA_CCR_TEIE_Pos       (3U)
2153 #define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
2154 #define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
2155 #define DMA_CCR_DIR_Pos        (4U)
2156 #define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
2157 #define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
2158 #define DMA_CCR_CIRC_Pos       (5U)
2159 #define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
2160 #define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
2161 #define DMA_CCR_PINC_Pos       (6U)
2162 #define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
2163 #define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
2164 #define DMA_CCR_MINC_Pos       (7U)
2165 #define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
2166 #define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
2167 
2168 #define DMA_CCR_PSIZE_Pos      (8U)
2169 #define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
2170 #define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
2171 #define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
2172 #define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
2173 
2174 #define DMA_CCR_MSIZE_Pos      (10U)
2175 #define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
2176 #define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
2177 #define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
2178 #define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
2179 
2180 #define DMA_CCR_PL_Pos         (12U)
2181 #define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
2182 #define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
2183 #define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
2184 #define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                        /*!< 0x00002000 */
2185 
2186 #define DMA_CCR_MEM2MEM_Pos    (14U)
2187 #define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
2188 #define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
2189 
2190 /******************  Bit definition for DMA_CNDTR register  *******************/
2191 #define DMA_CNDTR_NDT_Pos      (0U)
2192 #define DMA_CNDTR_NDT_Msk      (0xFFFFUL << DMA_CNDTR_NDT_Pos)                 /*!< 0x0000FFFF */
2193 #define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
2194 
2195 /******************  Bit definition for DMA_CPAR register  ********************/
2196 #define DMA_CPAR_PA_Pos        (0U)
2197 #define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
2198 #define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
2199 
2200 /******************  Bit definition for DMA_CMAR register  ********************/
2201 #define DMA_CMAR_MA_Pos        (0U)
2202 #define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
2203 #define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
2204 
2205 /******************************************************************************/
2206 /*                                                                            */
2207 /*                             DMAMUX Controller                              */
2208 /*                                                                            */
2209 /******************************************************************************/
2210 /********************  Bits definition for DMAMUX_CxCR register  **************/
2211 #define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
2212 #define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x3FUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x0000003F */
2213 #define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk             /*!< DMA Request ID   */
2214 #define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
2215 #define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
2216 #define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
2217 #define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
2218 #define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
2219 #define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
2220 #define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
2221 #define DMAMUX_CxCR_SOIE_Pos                   (8U)
2222 #define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos)  /*!< 0x00000100 */
2223 #define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk             /*!< Synchro overrun interrupt enable     */
2224 #define DMAMUX_CxCR_EGE_Pos                    (9U)
2225 #define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)   /*!< 0x00000200 */
2226 #define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk              /*!< Event generation interrupt enable    */
2227 #define DMAMUX_CxCR_SE_Pos                     (16U)
2228 #define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)    /*!< 0x00010000 */
2229 #define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk               /*!< Synchronization enable               */
2230 #define DMAMUX_CxCR_SPOL_Pos                   (17U)
2231 #define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00060000 */
2232 #define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk             /*!< Synchronization polarity             */
2233 #define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00020000 */
2234 #define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos)  /*!< 0x00040000 */
2235 #define DMAMUX_CxCR_NBREQ_Pos                  (19U)
2236 #define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
2237 #define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk             /*!< Number of request                    */
2238 #define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
2239 #define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
2240 #define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
2241 #define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
2242 #define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
2243 #define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
2244 #define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
2245 #define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk             /*!< Synchronization ID                   */
2246 #define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
2247 #define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
2248 #define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
2249 #define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
2250 #define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
2251 
2252 /*******************  Bits definition for DMAMUX_CSR register  **************/
2253 #define DMAMUX_CSR_SOF0_Pos                    (0U)
2254 #define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
2255 #define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
2256 #define DMAMUX_CSR_SOF1_Pos                    (1U)
2257 #define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
2258 #define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
2259 #define DMAMUX_CSR_SOF2_Pos                    (2U)
2260 #define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
2261 #define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
2262 #define DMAMUX_CSR_SOF3_Pos                    (3U)
2263 #define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
2264 #define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
2265 #define DMAMUX_CSR_SOF4_Pos                    (4U)
2266 #define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
2267 #define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
2268 #define DMAMUX_CSR_SOF5_Pos                    (5U)
2269 #define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
2270 #define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
2271 #define DMAMUX_CSR_SOF6_Pos                    (6U)
2272 #define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
2273 #define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
2274 
2275 /********************  Bits definition for DMAMUX_CFR register  **************/
2276 #define DMAMUX_CFR_CSOF0_Pos                   (0U)
2277 #define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos)  /*!< 0x00000001 */
2278 #define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk             /*!< Clear Overrun Flag 0                 */
2279 #define DMAMUX_CFR_CSOF1_Pos                   (1U)
2280 #define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos)  /*!< 0x00000002 */
2281 #define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk             /*!< Clear Overrun Flag 1                 */
2282 #define DMAMUX_CFR_CSOF2_Pos                   (2U)
2283 #define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos)  /*!< 0x00000004 */
2284 #define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk             /*!< Clear Overrun Flag 2                 */
2285 #define DMAMUX_CFR_CSOF3_Pos                   (3U)
2286 #define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos)  /*!< 0x00000008 */
2287 #define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk             /*!< Clear Overrun Flag 3                 */
2288 #define DMAMUX_CFR_CSOF4_Pos                   (4U)
2289 #define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos)  /*!< 0x00000010 */
2290 #define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk             /*!< Clear Overrun Flag 4                 */
2291 #define DMAMUX_CFR_CSOF5_Pos                   (5U)
2292 #define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos)  /*!< 0x00000020 */
2293 #define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk             /*!< Clear Overrun Flag 5                 */
2294 #define DMAMUX_CFR_CSOF6_Pos                   (6U)
2295 #define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos)  /*!< 0x00000040 */
2296 #define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk             /*!< Clear Overrun Flag 6                 */
2297 
2298 /********************  Bits definition for DMAMUX_RGxCR register  ************/
2299 #define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
2300 #define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
2301 #define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk             /*!< Signal ID                         */
2302 #define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
2303 #define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
2304 #define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
2305 #define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
2306 #define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
2307 #define DMAMUX_RGxCR_OIE_Pos                   (8U)
2308 #define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos)  /*!< 0x00000100 */
2309 #define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk             /*!< Overrun interrupt enable             */
2310 #define DMAMUX_RGxCR_GE_Pos                    (16U)
2311 #define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)   /*!< 0x00010000 */
2312 #define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk              /*!< Generation enable                    */
2313 #define DMAMUX_RGxCR_GPOL_Pos                  (17U)
2314 #define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
2315 #define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk            /*!< Generation polarity                  */
2316 #define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
2317 #define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
2318 #define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
2319 #define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
2320 #define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk             /*!< Number of request                 */
2321 #define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
2322 #define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
2323 #define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
2324 #define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
2325 #define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
2326 
2327 /********************  Bits definition for DMAMUX_RGSR register  **************/
2328 #define DMAMUX_RGSR_OF0_Pos                    (0U)
2329 #define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)   /*!< 0x00000001 */
2330 #define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk              /*!< Overrun flag 0                       */
2331 #define DMAMUX_RGSR_OF1_Pos                    (1U)
2332 #define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)   /*!< 0x00000002 */
2333 #define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk              /*!< Overrun flag 1                       */
2334 #define DMAMUX_RGSR_OF2_Pos                    (2U)
2335 #define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)   /*!< 0x00000004 */
2336 #define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk              /*!< Overrun flag 2                       */
2337 #define DMAMUX_RGSR_OF3_Pos                    (3U)
2338 #define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)   /*!< 0x00000008 */
2339 #define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk              /*!< Overrun flag 3                       */
2340 
2341 /********************  Bits definition for DMAMUX_RGCFR register  **************/
2342 #define DMAMUX_RGCFR_COF0_Pos                  (0U)
2343 #define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
2344 #define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk            /*!< Clear Overrun flag 0                 */
2345 #define DMAMUX_RGCFR_COF1_Pos                  (1U)
2346 #define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
2347 #define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk            /*!< Clear Overrun flag 1                 */
2348 #define DMAMUX_RGCFR_COF2_Pos                  (2U)
2349 #define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
2350 #define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk            /*!< Clear Overrun flag 2                 */
2351 #define DMAMUX_RGCFR_COF3_Pos                  (3U)
2352 #define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
2353 #define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk            /*!< Clear Overrun flag 3                 */
2354 
2355 /******************************************************************************/
2356 /*                                                                            */
2357 /*                    External Interrupt/Event Controller                     */
2358 /*                                                                            */
2359 /******************************************************************************/
2360 /******************  Bit definition for EXTI_RTSR1 register  ******************/
2361 #define EXTI_RTSR1_RT0_Pos           (0U)
2362 #define EXTI_RTSR1_RT0_Msk           (0x1UL << EXTI_RTSR1_RT0_Pos)             /*!< 0x00000001 */
2363 #define EXTI_RTSR1_RT0               EXTI_RTSR1_RT0_Msk                        /*!< Rising trigger configuration for input line 0 */
2364 #define EXTI_RTSR1_RT1_Pos           (1U)
2365 #define EXTI_RTSR1_RT1_Msk           (0x1UL << EXTI_RTSR1_RT1_Pos)             /*!< 0x00000002 */
2366 #define EXTI_RTSR1_RT1               EXTI_RTSR1_RT1_Msk                        /*!< Rising trigger configuration for input line 1 */
2367 #define EXTI_RTSR1_RT2_Pos           (2U)
2368 #define EXTI_RTSR1_RT2_Msk           (0x1UL << EXTI_RTSR1_RT2_Pos)             /*!< 0x00000004 */
2369 #define EXTI_RTSR1_RT2               EXTI_RTSR1_RT2_Msk                        /*!< Rising trigger configuration for input line 2 */
2370 #define EXTI_RTSR1_RT3_Pos           (3U)
2371 #define EXTI_RTSR1_RT3_Msk           (0x1UL << EXTI_RTSR1_RT3_Pos)             /*!< 0x00000008 */
2372 #define EXTI_RTSR1_RT3               EXTI_RTSR1_RT3_Msk                        /*!< Rising trigger configuration for input line 3 */
2373 #define EXTI_RTSR1_RT4_Pos           (4U)
2374 #define EXTI_RTSR1_RT4_Msk           (0x1UL << EXTI_RTSR1_RT4_Pos)             /*!< 0x00000010 */
2375 #define EXTI_RTSR1_RT4               EXTI_RTSR1_RT4_Msk                        /*!< Rising trigger configuration for input line 4 */
2376 #define EXTI_RTSR1_RT5_Pos           (5U)
2377 #define EXTI_RTSR1_RT5_Msk           (0x1UL << EXTI_RTSR1_RT5_Pos)             /*!< 0x00000020 */
2378 #define EXTI_RTSR1_RT5               EXTI_RTSR1_RT5_Msk                        /*!< Rising trigger configuration for input line 5 */
2379 #define EXTI_RTSR1_RT6_Pos           (6U)
2380 #define EXTI_RTSR1_RT6_Msk           (0x1UL << EXTI_RTSR1_RT6_Pos)             /*!< 0x00000040 */
2381 #define EXTI_RTSR1_RT6               EXTI_RTSR1_RT6_Msk                        /*!< Rising trigger configuration for input line 6 */
2382 #define EXTI_RTSR1_RT7_Pos           (7U)
2383 #define EXTI_RTSR1_RT7_Msk           (0x1UL << EXTI_RTSR1_RT7_Pos)             /*!< 0x00000080 */
2384 #define EXTI_RTSR1_RT7               EXTI_RTSR1_RT7_Msk                        /*!< Rising trigger configuration for input line 7 */
2385 #define EXTI_RTSR1_RT8_Pos           (8U)
2386 #define EXTI_RTSR1_RT8_Msk           (0x1UL << EXTI_RTSR1_RT8_Pos)             /*!< 0x00000100 */
2387 #define EXTI_RTSR1_RT8               EXTI_RTSR1_RT8_Msk                        /*!< Rising trigger configuration for input line 8 */
2388 #define EXTI_RTSR1_RT9_Pos           (9U)
2389 #define EXTI_RTSR1_RT9_Msk           (0x1UL << EXTI_RTSR1_RT9_Pos)             /*!< 0x00000200 */
2390 #define EXTI_RTSR1_RT9               EXTI_RTSR1_RT9_Msk                        /*!< Rising trigger configuration for input line 9 */
2391 #define EXTI_RTSR1_RT10_Pos          (10U)
2392 #define EXTI_RTSR1_RT10_Msk          (0x1UL << EXTI_RTSR1_RT10_Pos)            /*!< 0x00000400 */
2393 #define EXTI_RTSR1_RT10              EXTI_RTSR1_RT10_Msk                       /*!< Rising trigger configuration for input line 10 */
2394 #define EXTI_RTSR1_RT11_Pos          (11U)
2395 #define EXTI_RTSR1_RT11_Msk          (0x1UL << EXTI_RTSR1_RT11_Pos)            /*!< 0x00000800 */
2396 #define EXTI_RTSR1_RT11              EXTI_RTSR1_RT11_Msk                       /*!< Rising trigger configuration for input line 11 */
2397 #define EXTI_RTSR1_RT12_Pos          (12U)
2398 #define EXTI_RTSR1_RT12_Msk          (0x1UL << EXTI_RTSR1_RT12_Pos)            /*!< 0x00001000 */
2399 #define EXTI_RTSR1_RT12              EXTI_RTSR1_RT12_Msk                       /*!< Rising trigger configuration for input line 12 */
2400 #define EXTI_RTSR1_RT13_Pos          (13U)
2401 #define EXTI_RTSR1_RT13_Msk          (0x1UL << EXTI_RTSR1_RT13_Pos)            /*!< 0x00002000 */
2402 #define EXTI_RTSR1_RT13              EXTI_RTSR1_RT13_Msk                       /*!< Rising trigger configuration for input line 13 */
2403 #define EXTI_RTSR1_RT14_Pos          (14U)
2404 #define EXTI_RTSR1_RT14_Msk          (0x1UL << EXTI_RTSR1_RT14_Pos)            /*!< 0x00004000 */
2405 #define EXTI_RTSR1_RT14              EXTI_RTSR1_RT14_Msk                       /*!< Rising trigger configuration for input line 14 */
2406 #define EXTI_RTSR1_RT15_Pos          (15U)
2407 #define EXTI_RTSR1_RT15_Msk          (0x1UL << EXTI_RTSR1_RT15_Pos)            /*!< 0x00008000 */
2408 #define EXTI_RTSR1_RT15              EXTI_RTSR1_RT15_Msk                       /*!< Rising trigger configuration for input line 15 */
2409 #define EXTI_RTSR1_RT16_Pos          (16U)
2410 #define EXTI_RTSR1_RT16_Msk          (0x1UL << EXTI_RTSR1_RT16_Pos)            /*!< 0x00010000 */
2411 #define EXTI_RTSR1_RT16              EXTI_RTSR1_RT16_Msk                       /*!< Rising trigger configuration for input line 16 */
2412 #define EXTI_RTSR1_RT17_Pos          (17U)
2413 #define EXTI_RTSR1_RT17_Msk          (0x1UL << EXTI_RTSR1_RT17_Pos)            /*!< 0x00020000 */
2414 #define EXTI_RTSR1_RT17              EXTI_RTSR1_RT17_Msk                       /*!< Rising trigger configuration for input line 17 */
2415 #define EXTI_RTSR1_RT18_Pos          (18U)
2416 #define EXTI_RTSR1_RT18_Msk          (0x1UL << EXTI_RTSR1_RT18_Pos)            /*!< 0x00040000 */
2417 #define EXTI_RTSR1_RT18              EXTI_RTSR1_RT18_Msk                       /*!< Rising trigger configuration for input line 18 */
2418 
2419 /******************  Bit definition for EXTI_FTSR1 register  ******************/
2420 #define EXTI_FTSR1_FT0_Pos           (0U)
2421 #define EXTI_FTSR1_FT0_Msk           (0x1UL << EXTI_FTSR1_FT0_Pos)             /*!< 0x00000001 */
2422 #define EXTI_FTSR1_FT0               EXTI_FTSR1_FT0_Msk                        /*!< Falling trigger configuration for input line 0 */
2423 #define EXTI_FTSR1_FT1_Pos           (1U)
2424 #define EXTI_FTSR1_FT1_Msk           (0x1UL << EXTI_FTSR1_FT1_Pos)             /*!< 0x00000002 */
2425 #define EXTI_FTSR1_FT1               EXTI_FTSR1_FT1_Msk                        /*!< Falling trigger configuration for input line 1 */
2426 #define EXTI_FTSR1_FT2_Pos           (2U)
2427 #define EXTI_FTSR1_FT2_Msk           (0x1UL << EXTI_FTSR1_FT2_Pos)             /*!< 0x00000004 */
2428 #define EXTI_FTSR1_FT2               EXTI_FTSR1_FT2_Msk                        /*!< Falling trigger configuration for input line 2 */
2429 #define EXTI_FTSR1_FT3_Pos           (3U)
2430 #define EXTI_FTSR1_FT3_Msk           (0x1UL << EXTI_FTSR1_FT3_Pos)             /*!< 0x00000008 */
2431 #define EXTI_FTSR1_FT3               EXTI_FTSR1_FT3_Msk                        /*!< Falling trigger configuration for input line 3 */
2432 #define EXTI_FTSR1_FT4_Pos           (4U)
2433 #define EXTI_FTSR1_FT4_Msk           (0x1UL << EXTI_FTSR1_FT4_Pos)             /*!< 0x00000010 */
2434 #define EXTI_FTSR1_FT4               EXTI_FTSR1_FT4_Msk                        /*!< Falling trigger configuration for input line 4 */
2435 #define EXTI_FTSR1_FT5_Pos           (5U)
2436 #define EXTI_FTSR1_FT5_Msk           (0x1UL << EXTI_FTSR1_FT5_Pos)             /*!< 0x00000020 */
2437 #define EXTI_FTSR1_FT5               EXTI_FTSR1_FT5_Msk                        /*!< Falling trigger configuration for input line 5 */
2438 #define EXTI_FTSR1_FT6_Pos           (6U)
2439 #define EXTI_FTSR1_FT6_Msk           (0x1UL << EXTI_FTSR1_FT6_Pos)             /*!< 0x00000040 */
2440 #define EXTI_FTSR1_FT6               EXTI_FTSR1_FT6_Msk                        /*!< Falling trigger configuration for input line 6 */
2441 #define EXTI_FTSR1_FT7_Pos           (7U)
2442 #define EXTI_FTSR1_FT7_Msk           (0x1UL << EXTI_FTSR1_FT7_Pos)             /*!< 0x00000080 */
2443 #define EXTI_FTSR1_FT7               EXTI_FTSR1_FT7_Msk                        /*!< Falling trigger configuration for input line 7 */
2444 #define EXTI_FTSR1_FT8_Pos           (8U)
2445 #define EXTI_FTSR1_FT8_Msk           (0x1UL << EXTI_FTSR1_FT8_Pos)             /*!< 0x00000100 */
2446 #define EXTI_FTSR1_FT8               EXTI_FTSR1_FT8_Msk                        /*!< Falling trigger configuration for input line 8 */
2447 #define EXTI_FTSR1_FT9_Pos           (9U)
2448 #define EXTI_FTSR1_FT9_Msk           (0x1UL << EXTI_FTSR1_FT9_Pos)             /*!< 0x00000200 */
2449 #define EXTI_FTSR1_FT9               EXTI_FTSR1_FT9_Msk                        /*!< Falling trigger configuration for input line 9 */
2450 #define EXTI_FTSR1_FT10_Pos          (10U)
2451 #define EXTI_FTSR1_FT10_Msk          (0x1UL << EXTI_FTSR1_FT10_Pos)            /*!< 0x00000400 */
2452 #define EXTI_FTSR1_FT10              EXTI_FTSR1_FT10_Msk                       /*!< Falling trigger configuration for input line 10 */
2453 #define EXTI_FTSR1_FT11_Pos          (11U)
2454 #define EXTI_FTSR1_FT11_Msk          (0x1UL << EXTI_FTSR1_FT11_Pos)            /*!< 0x00000800 */
2455 #define EXTI_FTSR1_FT11              EXTI_FTSR1_FT11_Msk                       /*!< Falling trigger configuration for input line 11 */
2456 #define EXTI_FTSR1_FT12_Pos          (12U)
2457 #define EXTI_FTSR1_FT12_Msk          (0x1UL << EXTI_FTSR1_FT12_Pos)            /*!< 0x00001000 */
2458 #define EXTI_FTSR1_FT12              EXTI_FTSR1_FT12_Msk                       /*!< Falling trigger configuration for input line 12 */
2459 #define EXTI_FTSR1_FT13_Pos          (13U)
2460 #define EXTI_FTSR1_FT13_Msk          (0x1UL << EXTI_FTSR1_FT13_Pos)            /*!< 0x00002000 */
2461 #define EXTI_FTSR1_FT13              EXTI_FTSR1_FT13_Msk                       /*!< Falling trigger configuration for input line 13 */
2462 #define EXTI_FTSR1_FT14_Pos          (14U)
2463 #define EXTI_FTSR1_FT14_Msk          (0x1UL << EXTI_FTSR1_FT14_Pos)            /*!< 0x00004000 */
2464 #define EXTI_FTSR1_FT14              EXTI_FTSR1_FT14_Msk                       /*!< Falling trigger configuration for input line 14 */
2465 #define EXTI_FTSR1_FT15_Pos          (15U)
2466 #define EXTI_FTSR1_FT15_Msk          (0x1UL << EXTI_FTSR1_FT15_Pos)            /*!< 0x00008000 */
2467 #define EXTI_FTSR1_FT15              EXTI_FTSR1_FT15_Msk                       /*!< Falling trigger configuration for input line 15 */
2468 #define EXTI_FTSR1_FT16_Pos          (16U)
2469 #define EXTI_FTSR1_FT16_Msk          (0x1UL << EXTI_FTSR1_FT16_Pos)            /*!< 0x00010000 */
2470 #define EXTI_FTSR1_FT16              EXTI_FTSR1_FT16_Msk                       /*!< Falling trigger configuration for input line 16 */
2471 #define EXTI_FTSR1_FT17_Pos          (17U)
2472 #define EXTI_FTSR1_FT17_Msk          (0x1UL << EXTI_FTSR1_FT17_Pos)            /*!< 0x00020000 */
2473 #define EXTI_FTSR1_FT17              EXTI_FTSR1_FT17_Msk                       /*!< Falling trigger configuration for input line 17 */
2474 #define EXTI_FTSR1_FT18_Pos          (18U)
2475 #define EXTI_FTSR1_FT18_Msk          (0x1UL << EXTI_FTSR1_FT18_Pos)            /*!< 0x00040000 */
2476 #define EXTI_FTSR1_FT18              EXTI_FTSR1_FT18_Msk                       /*!< Falling trigger configuration for input line 18 */
2477 
2478 /******************  Bit definition for EXTI_SWIER1 register  *****************/
2479 #define EXTI_SWIER1_SWI0_Pos         (0U)
2480 #define EXTI_SWIER1_SWI0_Msk         (0x1UL << EXTI_SWIER1_SWI0_Pos)           /*!< 0x00000001 */
2481 #define EXTI_SWIER1_SWI0             EXTI_SWIER1_SWI0_Msk                      /*!< Software Interrupt on line 0 */
2482 #define EXTI_SWIER1_SWI1_Pos         (1U)
2483 #define EXTI_SWIER1_SWI1_Msk         (0x1UL << EXTI_SWIER1_SWI1_Pos)           /*!< 0x00000002 */
2484 #define EXTI_SWIER1_SWI1             EXTI_SWIER1_SWI1_Msk                      /*!< Software Interrupt on line 1 */
2485 #define EXTI_SWIER1_SWI2_Pos         (2U)
2486 #define EXTI_SWIER1_SWI2_Msk         (0x1UL << EXTI_SWIER1_SWI2_Pos)           /*!< 0x00000004 */
2487 #define EXTI_SWIER1_SWI2             EXTI_SWIER1_SWI2_Msk                      /*!< Software Interrupt on line 2 */
2488 #define EXTI_SWIER1_SWI3_Pos         (3U)
2489 #define EXTI_SWIER1_SWI3_Msk         (0x1UL << EXTI_SWIER1_SWI3_Pos)           /*!< 0x00000008 */
2490 #define EXTI_SWIER1_SWI3             EXTI_SWIER1_SWI3_Msk                      /*!< Software Interrupt on line 3 */
2491 #define EXTI_SWIER1_SWI4_Pos         (4U)
2492 #define EXTI_SWIER1_SWI4_Msk         (0x1UL << EXTI_SWIER1_SWI4_Pos)           /*!< 0x00000010 */
2493 #define EXTI_SWIER1_SWI4             EXTI_SWIER1_SWI4_Msk                      /*!< Software Interrupt on line 4 */
2494 #define EXTI_SWIER1_SWI5_Pos         (5U)
2495 #define EXTI_SWIER1_SWI5_Msk         (0x1UL << EXTI_SWIER1_SWI5_Pos)           /*!< 0x00000020 */
2496 #define EXTI_SWIER1_SWI5             EXTI_SWIER1_SWI5_Msk                      /*!< Software Interrupt on line 5 */
2497 #define EXTI_SWIER1_SWI6_Pos         (6U)
2498 #define EXTI_SWIER1_SWI6_Msk         (0x1UL << EXTI_SWIER1_SWI6_Pos)           /*!< 0x00000040 */
2499 #define EXTI_SWIER1_SWI6             EXTI_SWIER1_SWI6_Msk                      /*!< Software Interrupt on line 6 */
2500 #define EXTI_SWIER1_SWI7_Pos         (7U)
2501 #define EXTI_SWIER1_SWI7_Msk         (0x1UL << EXTI_SWIER1_SWI7_Pos)           /*!< 0x00000080 */
2502 #define EXTI_SWIER1_SWI7             EXTI_SWIER1_SWI7_Msk                      /*!< Software Interrupt on line 7 */
2503 #define EXTI_SWIER1_SWI8_Pos         (8U)
2504 #define EXTI_SWIER1_SWI8_Msk         (0x1UL << EXTI_SWIER1_SWI8_Pos)           /*!< 0x00000100 */
2505 #define EXTI_SWIER1_SWI8             EXTI_SWIER1_SWI8_Msk                      /*!< Software Interrupt on line 8 */
2506 #define EXTI_SWIER1_SWI9_Pos         (9U)
2507 #define EXTI_SWIER1_SWI9_Msk         (0x1UL << EXTI_SWIER1_SWI9_Pos)           /*!< 0x00000200 */
2508 #define EXTI_SWIER1_SWI9             EXTI_SWIER1_SWI9_Msk                      /*!< Software Interrupt on line 9 */
2509 #define EXTI_SWIER1_SWI10_Pos        (10U)
2510 #define EXTI_SWIER1_SWI10_Msk        (0x1UL << EXTI_SWIER1_SWI10_Pos)          /*!< 0x00000400 */
2511 #define EXTI_SWIER1_SWI10            EXTI_SWIER1_SWI10_Msk                     /*!< Software Interrupt on line 10 */
2512 #define EXTI_SWIER1_SWI11_Pos        (11U)
2513 #define EXTI_SWIER1_SWI11_Msk        (0x1UL << EXTI_SWIER1_SWI11_Pos)          /*!< 0x00000800 */
2514 #define EXTI_SWIER1_SWI11            EXTI_SWIER1_SWI11_Msk                     /*!< Software Interrupt on line 11 */
2515 #define EXTI_SWIER1_SWI12_Pos        (12U)
2516 #define EXTI_SWIER1_SWI12_Msk        (0x1UL << EXTI_SWIER1_SWI12_Pos)          /*!< 0x00001000 */
2517 #define EXTI_SWIER1_SWI12            EXTI_SWIER1_SWI12_Msk                     /*!< Software Interrupt on line 12 */
2518 #define EXTI_SWIER1_SWI13_Pos        (13U)
2519 #define EXTI_SWIER1_SWI13_Msk        (0x1UL << EXTI_SWIER1_SWI13_Pos)          /*!< 0x00002000 */
2520 #define EXTI_SWIER1_SWI13            EXTI_SWIER1_SWI13_Msk                     /*!< Software Interrupt on line 13 */
2521 #define EXTI_SWIER1_SWI14_Pos        (14U)
2522 #define EXTI_SWIER1_SWI14_Msk        (0x1UL << EXTI_SWIER1_SWI14_Pos)          /*!< 0x00004000 */
2523 #define EXTI_SWIER1_SWI14            EXTI_SWIER1_SWI14_Msk                     /*!< Software Interrupt on line 14 */
2524 #define EXTI_SWIER1_SWI15_Pos        (15U)
2525 #define EXTI_SWIER1_SWI15_Msk        (0x1UL << EXTI_SWIER1_SWI15_Pos)          /*!< 0x00008000 */
2526 #define EXTI_SWIER1_SWI15            EXTI_SWIER1_SWI15_Msk                     /*!< Software Interrupt on line 15 */
2527 #define EXTI_SWIER1_SWI16_Pos        (16U)
2528 #define EXTI_SWIER1_SWI16_Msk        (0x1UL << EXTI_SWIER1_SWI16_Pos)          /*!< 0x00010000 */
2529 #define EXTI_SWIER1_SWI16            EXTI_SWIER1_SWI16_Msk                     /*!< Software Interrupt on line 16 */
2530 #define EXTI_SWIER1_SWI17_Pos        (17U)
2531 #define EXTI_SWIER1_SWI17_Msk        (0x1UL << EXTI_SWIER1_SWI17_Pos)          /*!< 0x00020000 */
2532 #define EXTI_SWIER1_SWI17            EXTI_SWIER1_SWI17_Msk                     /*!< Software Interrupt on line 17 */
2533 #define EXTI_SWIER1_SWI18_Pos        (18U)
2534 #define EXTI_SWIER1_SWI18_Msk        (0x1UL << EXTI_SWIER1_SWI18_Pos)          /*!< 0x00040000 */
2535 #define EXTI_SWIER1_SWI18            EXTI_SWIER1_SWI18_Msk                     /*!< Software Interrupt on line 18 */
2536 
2537 /*******************  Bit definition for EXTI_RPR1 register  ******************/
2538 #define EXTI_RPR1_RPIF0_Pos          (0U)
2539 #define EXTI_RPR1_RPIF0_Msk          (0x1UL << EXTI_RPR1_RPIF0_Pos)            /*!< 0x00000001 */
2540 #define EXTI_RPR1_RPIF0              EXTI_RPR1_RPIF0_Msk                       /*!< Rising Pending Interrupt Flag on line 0 */
2541 #define EXTI_RPR1_RPIF1_Pos          (1U)
2542 #define EXTI_RPR1_RPIF1_Msk          (0x1UL << EXTI_RPR1_RPIF1_Pos)            /*!< 0x00000002 */
2543 #define EXTI_RPR1_RPIF1              EXTI_RPR1_RPIF1_Msk                       /*!< Rising Pending Interrupt Flag on line 1 */
2544 #define EXTI_RPR1_RPIF2_Pos          (2U)
2545 #define EXTI_RPR1_RPIF2_Msk          (0x1UL << EXTI_RPR1_RPIF2_Pos)            /*!< 0x00000004 */
2546 #define EXTI_RPR1_RPIF2              EXTI_RPR1_RPIF2_Msk                       /*!< Rising Pending Interrupt Flag on line 2 */
2547 #define EXTI_RPR1_RPIF3_Pos          (3U)
2548 #define EXTI_RPR1_RPIF3_Msk          (0x1UL << EXTI_RPR1_RPIF3_Pos)            /*!< 0x00000008 */
2549 #define EXTI_RPR1_RPIF3              EXTI_RPR1_RPIF3_Msk                       /*!< Rising Pending Interrupt Flag on line 3 */
2550 #define EXTI_RPR1_RPIF4_Pos          (4U)
2551 #define EXTI_RPR1_RPIF4_Msk          (0x1UL << EXTI_RPR1_RPIF4_Pos)            /*!< 0x00000010 */
2552 #define EXTI_RPR1_RPIF4              EXTI_RPR1_RPIF4_Msk                       /*!< Rising Pending Interrupt Flag on line 4 */
2553 #define EXTI_RPR1_RPIF5_Pos          (5U)
2554 #define EXTI_RPR1_RPIF5_Msk          (0x1UL << EXTI_RPR1_RPIF5_Pos)            /*!< 0x00000020 */
2555 #define EXTI_RPR1_RPIF5              EXTI_RPR1_RPIF5_Msk                       /*!< Rising Pending Interrupt Flag on line 5 */
2556 #define EXTI_RPR1_RPIF6_Pos          (6U)
2557 #define EXTI_RPR1_RPIF6_Msk          (0x1UL << EXTI_RPR1_RPIF6_Pos)            /*!< 0x00000040 */
2558 #define EXTI_RPR1_RPIF6              EXTI_RPR1_RPIF6_Msk                       /*!< Rising Pending Interrupt Flag on line 6 */
2559 #define EXTI_RPR1_RPIF7_Pos          (7U)
2560 #define EXTI_RPR1_RPIF7_Msk          (0x1UL << EXTI_RPR1_RPIF7_Pos)            /*!< 0x00000080 */
2561 #define EXTI_RPR1_RPIF7              EXTI_RPR1_RPIF7_Msk                       /*!< Rising Pending Interrupt Flag on line 7 */
2562 #define EXTI_RPR1_RPIF8_Pos          (8U)
2563 #define EXTI_RPR1_RPIF8_Msk          (0x1UL << EXTI_RPR1_RPIF8_Pos)            /*!< 0x00000100 */
2564 #define EXTI_RPR1_RPIF8              EXTI_RPR1_RPIF8_Msk                       /*!< Rising Pending Interrupt Flag on line 8 */
2565 #define EXTI_RPR1_RPIF9_Pos          (9U)
2566 #define EXTI_RPR1_RPIF9_Msk          (0x1UL << EXTI_RPR1_RPIF9_Pos)            /*!< 0x00000200 */
2567 #define EXTI_RPR1_RPIF9              EXTI_RPR1_RPIF9_Msk                       /*!< Rising Pending Interrupt Flag on line 9 */
2568 #define EXTI_RPR1_RPIF10_Pos         (10U)
2569 #define EXTI_RPR1_RPIF10_Msk         (0x1UL << EXTI_RPR1_RPIF10_Pos)           /*!< 0x00000400 */
2570 #define EXTI_RPR1_RPIF10             EXTI_RPR1_RPIF10_Msk                      /*!< Rising Pending Interrupt Flag on line 10 */
2571 #define EXTI_RPR1_RPIF11_Pos         (11U)
2572 #define EXTI_RPR1_RPIF11_Msk         (0x1UL << EXTI_RPR1_RPIF11_Pos)           /*!< 0x00000800 */
2573 #define EXTI_RPR1_RPIF11             EXTI_RPR1_RPIF11_Msk                      /*!< Rising Pending Interrupt Flag on line 11 */
2574 #define EXTI_RPR1_RPIF12_Pos         (12U)
2575 #define EXTI_RPR1_RPIF12_Msk         (0x1UL << EXTI_RPR1_RPIF12_Pos)           /*!< 0x00001000 */
2576 #define EXTI_RPR1_RPIF12             EXTI_RPR1_RPIF12_Msk                      /*!< Rising Pending Interrupt Flag on line 12 */
2577 #define EXTI_RPR1_RPIF13_Pos         (13U)
2578 #define EXTI_RPR1_RPIF13_Msk         (0x1UL << EXTI_RPR1_RPIF13_Pos)           /*!< 0x00002000 */
2579 #define EXTI_RPR1_RPIF13             EXTI_RPR1_RPIF13_Msk                      /*!< Rising Pending Interrupt Flag on line 13 */
2580 #define EXTI_RPR1_RPIF14_Pos         (14U)
2581 #define EXTI_RPR1_RPIF14_Msk         (0x1UL << EXTI_RPR1_RPIF14_Pos)           /*!< 0x00004000 */
2582 #define EXTI_RPR1_RPIF14             EXTI_RPR1_RPIF14_Msk                      /*!< Rising Pending Interrupt Flag on line 14 */
2583 #define EXTI_RPR1_RPIF15_Pos         (15U)
2584 #define EXTI_RPR1_RPIF15_Msk         (0x1UL << EXTI_RPR1_RPIF15_Pos)           /*!< 0x00008000 */
2585 #define EXTI_RPR1_RPIF15             EXTI_RPR1_RPIF15_Msk                      /*!< Rising Pending Interrupt Flag on line 15 */
2586 #define EXTI_RPR1_RPIF16_Pos         (16U)
2587 #define EXTI_RPR1_RPIF16_Msk         (0x1UL << EXTI_RPR1_RPIF16_Pos)           /*!< 0x00010000 */
2588 #define EXTI_RPR1_RPIF16             EXTI_RPR1_RPIF16_Msk                      /*!< Rising Pending Interrupt Flag on line 16 */
2589 #define EXTI_RPR1_RPIF17_Pos         (17U)
2590 #define EXTI_RPR1_RPIF17_Msk         (0x1UL << EXTI_RPR1_RPIF17_Pos)           /*!< 0x00020000 */
2591 #define EXTI_RPR1_RPIF17             EXTI_RPR1_RPIF17_Msk                      /*!< Rising Pending Interrupt Flag on line 17 */
2592 #define EXTI_RPR1_RPIF18_Pos         (18U)
2593 #define EXTI_RPR1_RPIF18_Msk         (0x1UL << EXTI_RPR1_RPIF18_Pos)           /*!< 0x00040000 */
2594 #define EXTI_RPR1_RPIF18             EXTI_RPR1_RPIF18_Msk                      /*!< Rising Pending Interrupt Flag on line 18 */
2595 
2596 /*******************  Bit definition for EXTI_FPR1 register  ******************/
2597 #define EXTI_FPR1_FPIF0_Pos          (0U)
2598 #define EXTI_FPR1_FPIF0_Msk          (0x1UL << EXTI_FPR1_FPIF0_Pos)            /*!< 0x00000001 */
2599 #define EXTI_FPR1_FPIF0              EXTI_FPR1_FPIF0_Msk                       /*!< Falling Pending Interrupt Flag on line 0 */
2600 #define EXTI_FPR1_FPIF1_Pos          (1U)
2601 #define EXTI_FPR1_FPIF1_Msk          (0x1UL << EXTI_FPR1_FPIF1_Pos)            /*!< 0x00000002 */
2602 #define EXTI_FPR1_FPIF1              EXTI_FPR1_FPIF1_Msk                       /*!< Falling Pending Interrupt Flag on line 1 */
2603 #define EXTI_FPR1_FPIF2_Pos          (2U)
2604 #define EXTI_FPR1_FPIF2_Msk          (0x1UL << EXTI_FPR1_FPIF2_Pos)            /*!< 0x00000004 */
2605 #define EXTI_FPR1_FPIF2              EXTI_FPR1_FPIF2_Msk                       /*!< Falling Pending Interrupt Flag on line 2 */
2606 #define EXTI_FPR1_FPIF3_Pos          (3U)
2607 #define EXTI_FPR1_FPIF3_Msk          (0x1UL << EXTI_FPR1_FPIF3_Pos)            /*!< 0x00000008 */
2608 #define EXTI_FPR1_FPIF3              EXTI_FPR1_FPIF3_Msk                       /*!< Falling Pending Interrupt Flag on line 3 */
2609 #define EXTI_FPR1_FPIF4_Pos          (4U)
2610 #define EXTI_FPR1_FPIF4_Msk          (0x1UL << EXTI_FPR1_FPIF4_Pos)            /*!< 0x00000010 */
2611 #define EXTI_FPR1_FPIF4              EXTI_FPR1_FPIF4_Msk                       /*!< Falling Pending Interrupt Flag on line 4 */
2612 #define EXTI_FPR1_FPIF5_Pos          (5U)
2613 #define EXTI_FPR1_FPIF5_Msk          (0x1UL << EXTI_FPR1_FPIF5_Pos)            /*!< 0x00000020 */
2614 #define EXTI_FPR1_FPIF5              EXTI_FPR1_FPIF5_Msk                       /*!< Falling Pending Interrupt Flag on line 5 */
2615 #define EXTI_FPR1_FPIF6_Pos          (6U)
2616 #define EXTI_FPR1_FPIF6_Msk          (0x1UL << EXTI_FPR1_FPIF6_Pos)            /*!< 0x00000040 */
2617 #define EXTI_FPR1_FPIF6              EXTI_FPR1_FPIF6_Msk                       /*!< Falling Pending Interrupt Flag on line 6 */
2618 #define EXTI_FPR1_FPIF7_Pos          (7U)
2619 #define EXTI_FPR1_FPIF7_Msk          (0x1UL << EXTI_FPR1_FPIF7_Pos)            /*!< 0x00000080 */
2620 #define EXTI_FPR1_FPIF7              EXTI_FPR1_FPIF7_Msk                       /*!< Falling Pending Interrupt Flag on line 7 */
2621 #define EXTI_FPR1_FPIF8_Pos          (8U)
2622 #define EXTI_FPR1_FPIF8_Msk          (0x1UL << EXTI_FPR1_FPIF8_Pos)            /*!< 0x00000100 */
2623 #define EXTI_FPR1_FPIF8              EXTI_FPR1_FPIF8_Msk                       /*!< Falling Pending Interrupt Flag on line 8 */
2624 #define EXTI_FPR1_FPIF9_Pos          (9U)
2625 #define EXTI_FPR1_FPIF9_Msk          (0x1UL << EXTI_FPR1_FPIF9_Pos)            /*!< 0x00000200 */
2626 #define EXTI_FPR1_FPIF9              EXTI_FPR1_FPIF9_Msk                       /*!< Falling Pending Interrupt Flag on line 9 */
2627 #define EXTI_FPR1_FPIF10_Pos         (10U)
2628 #define EXTI_FPR1_FPIF10_Msk         (0x1UL << EXTI_FPR1_FPIF10_Pos)           /*!< 0x00000400 */
2629 #define EXTI_FPR1_FPIF10             EXTI_FPR1_FPIF10_Msk                      /*!< Falling Pending Interrupt Flag on line 10 */
2630 #define EXTI_FPR1_FPIF11_Pos         (11U)
2631 #define EXTI_FPR1_FPIF11_Msk         (0x1UL << EXTI_FPR1_FPIF11_Pos)           /*!< 0x00000800 */
2632 #define EXTI_FPR1_FPIF11             EXTI_FPR1_FPIF11_Msk                      /*!< Falling Pending Interrupt Flag on line 11 */
2633 #define EXTI_FPR1_FPIF12_Pos         (12U)
2634 #define EXTI_FPR1_FPIF12_Msk         (0x1UL << EXTI_FPR1_FPIF12_Pos)           /*!< 0x00001000 */
2635 #define EXTI_FPR1_FPIF12             EXTI_FPR1_FPIF12_Msk                      /*!< Falling Pending Interrupt Flag on line 12 */
2636 #define EXTI_FPR1_FPIF13_Pos         (13U)
2637 #define EXTI_FPR1_FPIF13_Msk         (0x1UL << EXTI_FPR1_FPIF13_Pos)           /*!< 0x00002000 */
2638 #define EXTI_FPR1_FPIF13             EXTI_FPR1_FPIF13_Msk                      /*!< Falling Pending Interrupt Flag on line 13 */
2639 #define EXTI_FPR1_FPIF14_Pos         (14U)
2640 #define EXTI_FPR1_FPIF14_Msk         (0x1UL << EXTI_FPR1_FPIF14_Pos)           /*!< 0x00004000 */
2641 #define EXTI_FPR1_FPIF14             EXTI_FPR1_FPIF14_Msk                      /*!< Falling Pending Interrupt Flag on line 14 */
2642 #define EXTI_FPR1_FPIF15_Pos         (15U)
2643 #define EXTI_FPR1_FPIF15_Msk         (0x1UL << EXTI_FPR1_FPIF15_Pos)           /*!< 0x00008000 */
2644 #define EXTI_FPR1_FPIF15             EXTI_FPR1_FPIF15_Msk                      /*!< Falling Pending Interrupt Flag on line 15 */
2645 #define EXTI_FPR1_FPIF16_Pos         (16U)
2646 #define EXTI_FPR1_FPIF16_Msk         (0x1UL << EXTI_FPR1_FPIF16_Pos)           /*!< 0x00010000 */
2647 #define EXTI_FPR1_FPIF16             EXTI_FPR1_FPIF16_Msk                      /*!< Falling Pending Interrupt Flag on line 16 */
2648 #define EXTI_FPR1_FPIF17_Pos         (17U)
2649 #define EXTI_FPR1_FPIF17_Msk         (0x1UL << EXTI_FPR1_FPIF17_Pos)           /*!< 0x00020000 */
2650 #define EXTI_FPR1_FPIF17             EXTI_FPR1_FPIF17_Msk                      /*!< Falling Pending Interrupt Flag on line 17 */
2651 #define EXTI_FPR1_FPIF18_Pos         (18U)
2652 #define EXTI_FPR1_FPIF18_Msk         (0x1UL << EXTI_FPR1_FPIF18_Pos)           /*!< 0x00040000 */
2653 #define EXTI_FPR1_FPIF18             EXTI_FPR1_FPIF18_Msk                      /*!< Falling Pending Interrupt Flag on line 18 */
2654 
2655 /*****************  Bit definition for EXTI_EXTICR1 register  **************/
2656 #define EXTI_EXTICR1_EXTI0_Pos       (0U)
2657 #define EXTI_EXTICR1_EXTI0_Msk       (0x7UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000007 */
2658 #define EXTI_EXTICR1_EXTI0           EXTI_EXTICR1_EXTI0_Msk                    /*!< EXTI 0 configuration */
2659 #define EXTI_EXTICR1_EXTI0_0         (0x1UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000001 */
2660 #define EXTI_EXTICR1_EXTI0_1         (0x2UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000002 */
2661 #define EXTI_EXTICR1_EXTI0_2         (0x4UL << EXTI_EXTICR1_EXTI0_Pos)         /*!< 0x00000004 */
2662 #define EXTI_EXTICR1_EXTI1_Pos       (8U)
2663 #define EXTI_EXTICR1_EXTI1_Msk       (0x7UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000700 */
2664 #define EXTI_EXTICR1_EXTI1           EXTI_EXTICR1_EXTI1_Msk                    /*!< EXTI 1 configuration */
2665 #define EXTI_EXTICR1_EXTI1_0         (0x1UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000100 */
2666 #define EXTI_EXTICR1_EXTI1_1         (0x2UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000200 */
2667 #define EXTI_EXTICR1_EXTI1_2         (0x4UL << EXTI_EXTICR1_EXTI1_Pos)         /*!< 0x00000400 */
2668 #define EXTI_EXTICR1_EXTI2_Pos       (16U)
2669 #define EXTI_EXTICR1_EXTI2_Msk       (0x7UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00070000 */
2670 #define EXTI_EXTICR1_EXTI2           EXTI_EXTICR1_EXTI2_Msk                    /*!< EXTI 2 configuration */
2671 #define EXTI_EXTICR1_EXTI2_0         (0x1UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00010000 */
2672 #define EXTI_EXTICR1_EXTI2_1         (0x2UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00020000 */
2673 #define EXTI_EXTICR1_EXTI2_2         (0x4UL << EXTI_EXTICR1_EXTI2_Pos)         /*!< 0x00040000 */
2674 #define EXTI_EXTICR1_EXTI3_Pos       (24U)
2675 #define EXTI_EXTICR1_EXTI3_Msk       (0x7UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x07000000 */
2676 #define EXTI_EXTICR1_EXTI3           EXTI_EXTICR1_EXTI3_Msk                    /*!< EXTI 3 configuration */
2677 #define EXTI_EXTICR1_EXTI3_0         (0x1UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x01000000 */
2678 #define EXTI_EXTICR1_EXTI3_1         (0x2UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x02000000 */
2679 #define EXTI_EXTICR1_EXTI3_2         (0x4UL << EXTI_EXTICR1_EXTI3_Pos)         /*!< 0x04000000 */
2680 
2681 /*****************  Bit definition for EXTI_EXTICR2 register  **************/
2682 #define EXTI_EXTICR2_EXTI4_Pos       (0U)
2683 #define EXTI_EXTICR2_EXTI4_Msk       (0x7UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000007 */
2684 #define EXTI_EXTICR2_EXTI4           EXTI_EXTICR2_EXTI4_Msk                    /*!< EXTI 4 configuration */
2685 #define EXTI_EXTICR2_EXTI4_0         (0x1UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000001 */
2686 #define EXTI_EXTICR2_EXTI4_1         (0x2UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000002 */
2687 #define EXTI_EXTICR2_EXTI4_2         (0x4UL << EXTI_EXTICR2_EXTI4_Pos)         /*!< 0x00000004 */
2688 #define EXTI_EXTICR2_EXTI5_Pos       (8U)
2689 #define EXTI_EXTICR2_EXTI5_Msk       (0x7UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000700 */
2690 #define EXTI_EXTICR2_EXTI5           EXTI_EXTICR2_EXTI5_Msk                    /*!< EXTI 5 configuration */
2691 #define EXTI_EXTICR2_EXTI5_0         (0x1UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000100 */
2692 #define EXTI_EXTICR2_EXTI5_1         (0x2UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000200 */
2693 #define EXTI_EXTICR2_EXTI5_2         (0x4UL << EXTI_EXTICR2_EXTI5_Pos)         /*!< 0x00000400 */
2694 #define EXTI_EXTICR2_EXTI6_Pos       (16U)
2695 #define EXTI_EXTICR2_EXTI6_Msk       (0x7UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00070000 */
2696 #define EXTI_EXTICR2_EXTI6           EXTI_EXTICR2_EXTI6_Msk                    /*!< EXTI 6 configuration */
2697 #define EXTI_EXTICR2_EXTI6_0         (0x1UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00010000 */
2698 #define EXTI_EXTICR2_EXTI6_1         (0x2UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00020000 */
2699 #define EXTI_EXTICR2_EXTI6_2         (0x4UL << EXTI_EXTICR2_EXTI6_Pos)         /*!< 0x00040000 */
2700 #define EXTI_EXTICR2_EXTI7_Pos       (24U)
2701 #define EXTI_EXTICR2_EXTI7_Msk       (0x7UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x07000000 */
2702 #define EXTI_EXTICR2_EXTI7           EXTI_EXTICR2_EXTI7_Msk                    /*!< EXTI 7 configuration */
2703 #define EXTI_EXTICR2_EXTI7_0         (0x1UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x01000000 */
2704 #define EXTI_EXTICR2_EXTI7_1         (0x2UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x02000000 */
2705 #define EXTI_EXTICR2_EXTI7_2         (0x4UL << EXTI_EXTICR2_EXTI7_Pos)         /*!< 0x04000000 */
2706 
2707 /*****************  Bit definition for EXTI_EXTICR3 register  **************/
2708 #define EXTI_EXTICR3_EXTI8_Pos       (0U)
2709 #define EXTI_EXTICR3_EXTI8_Msk       (0x7UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000007 */
2710 #define EXTI_EXTICR3_EXTI8           EXTI_EXTICR3_EXTI8_Msk                    /*!< EXTI 8 configuration */
2711 #define EXTI_EXTICR3_EXTI8_0         (0x1UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000001 */
2712 #define EXTI_EXTICR3_EXTI8_1         (0x2UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000002 */
2713 #define EXTI_EXTICR3_EXTI8_2         (0x4UL << EXTI_EXTICR3_EXTI8_Pos)         /*!< 0x00000004 */
2714 #define EXTI_EXTICR3_EXTI9_Pos       (8U)
2715 #define EXTI_EXTICR3_EXTI9_Msk       (0x7UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000700 */
2716 #define EXTI_EXTICR3_EXTI9           EXTI_EXTICR3_EXTI9_Msk                    /*!< EXTI 9 configuration */
2717 #define EXTI_EXTICR3_EXTI9_0         (0x1UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000100 */
2718 #define EXTI_EXTICR3_EXTI9_1         (0x2UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000200 */
2719 #define EXTI_EXTICR3_EXTI9_2         (0x4UL << EXTI_EXTICR3_EXTI9_Pos)         /*!< 0x00000400 */
2720 #define EXTI_EXTICR3_EXTI10_Pos      (16U)
2721 #define EXTI_EXTICR3_EXTI10_Msk      (0x7UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00070000 */
2722 #define EXTI_EXTICR3_EXTI10          EXTI_EXTICR3_EXTI10_Msk                   /*!< EXTI 10 configuration */
2723 #define EXTI_EXTICR3_EXTI10_0        (0x1UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00010000 */
2724 #define EXTI_EXTICR3_EXTI10_1        (0x2UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00020000 */
2725 #define EXTI_EXTICR3_EXTI10_2        (0x4UL << EXTI_EXTICR3_EXTI10_Pos)        /*!< 0x00040000 */
2726 #define EXTI_EXTICR3_EXTI11_Pos      (24U)
2727 #define EXTI_EXTICR3_EXTI11_Msk      (0x7UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x07000000 */
2728 #define EXTI_EXTICR3_EXTI11          EXTI_EXTICR3_EXTI11_Msk                   /*!< EXTI 11 configuration */
2729 #define EXTI_EXTICR3_EXTI11_0        (0x1UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x01000000 */
2730 #define EXTI_EXTICR3_EXTI11_1        (0x2UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x02000000 */
2731 #define EXTI_EXTICR3_EXTI11_2        (0x4UL << EXTI_EXTICR3_EXTI11_Pos)        /*!< 0x04000000 */
2732 
2733 /*****************  Bit definition for EXTI_EXTICR4 register  **************/
2734 #define EXTI_EXTICR4_EXTI12_Pos      (0U)
2735 #define EXTI_EXTICR4_EXTI12_Msk      (0x7UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000007 */
2736 #define EXTI_EXTICR4_EXTI12          EXTI_EXTICR4_EXTI12_Msk                   /*!< EXTI 12 configuration */
2737 #define EXTI_EXTICR4_EXTI12_0        (0x1UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000001 */
2738 #define EXTI_EXTICR4_EXTI12_1        (0x2UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000002 */
2739 #define EXTI_EXTICR4_EXTI12_2        (0x4UL << EXTI_EXTICR4_EXTI12_Pos)        /*!< 0x00000004 */
2740 #define EXTI_EXTICR4_EXTI13_Pos      (8U)
2741 #define EXTI_EXTICR4_EXTI13_Msk      (0x7UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000700 */
2742 #define EXTI_EXTICR4_EXTI13          EXTI_EXTICR4_EXTI13_Msk                   /*!< EXTI 13 configuration */
2743 #define EXTI_EXTICR4_EXTI13_0        (0x1UL << EXTI_EXTICR4_EXTI13_Pos)        /*!< 0x00000100 */
2744 #define EXTI_EXTICR4_EXTI13_1        (0x2UL << EXTI_EXTICR4_EXTI13_Pos)       /*!< 0x00000200 */
2745 #define EXTI_EXTICR4_EXTI13_2        (0x4UL << EXTI_EXTICR4_EXTI13_Pos)         /*!< 0x00000400 */
2746 #define EXTI_EXTICR4_EXTI14_Pos      (16U)
2747 #define EXTI_EXTICR4_EXTI14_Msk      (0x7UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00070000 */
2748 #define EXTI_EXTICR4_EXTI14          EXTI_EXTICR4_EXTI14_Msk                   /*!< EXTI 14 configuration */
2749 #define EXTI_EXTICR4_EXTI14_0        (0x1UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00010000 */
2750 #define EXTI_EXTICR4_EXTI14_1        (0x2UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00020000 */
2751 #define EXTI_EXTICR4_EXTI14_2        (0x4UL << EXTI_EXTICR4_EXTI14_Pos)        /*!< 0x00040000 */
2752 #define EXTI_EXTICR4_EXTI15_Pos      (24U)
2753 #define EXTI_EXTICR4_EXTI15_Msk      (0x7UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x07000000 */
2754 #define EXTI_EXTICR4_EXTI15          EXTI_EXTICR4_EXTI15_Msk                   /*!< EXTI 15 configuration */
2755 #define EXTI_EXTICR4_EXTI15_0        (0x1UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x01000000 */
2756 #define EXTI_EXTICR4_EXTI15_1        (0x2UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x02000000 */
2757 #define EXTI_EXTICR4_EXTI15_2        (0x4UL << EXTI_EXTICR4_EXTI15_Pos)        /*!< 0x04000000 */
2758 
2759 /*******************  Bit definition for EXTI_IMR1 register  ******************/
2760 #define EXTI_IMR1_IM0_Pos            (0U)
2761 #define EXTI_IMR1_IM0_Msk            (0x1UL << EXTI_IMR1_IM0_Pos)              /*!< 0x00000001 */
2762 #define EXTI_IMR1_IM0                EXTI_IMR1_IM0_Msk                         /*!< Interrupt Mask on line 0 */
2763 #define EXTI_IMR1_IM1_Pos            (1U)
2764 #define EXTI_IMR1_IM1_Msk            (0x1UL << EXTI_IMR1_IM1_Pos)              /*!< 0x00000002 */
2765 #define EXTI_IMR1_IM1                EXTI_IMR1_IM1_Msk                         /*!< Interrupt Mask on line 1 */
2766 #define EXTI_IMR1_IM2_Pos            (2U)
2767 #define EXTI_IMR1_IM2_Msk            (0x1UL << EXTI_IMR1_IM2_Pos)              /*!< 0x00000004 */
2768 #define EXTI_IMR1_IM2                EXTI_IMR1_IM2_Msk                         /*!< Interrupt Mask on line 2 */
2769 #define EXTI_IMR1_IM3_Pos            (3U)
2770 #define EXTI_IMR1_IM3_Msk            (0x1UL << EXTI_IMR1_IM3_Pos)              /*!< 0x00000008 */
2771 #define EXTI_IMR1_IM3                EXTI_IMR1_IM3_Msk                         /*!< Interrupt Mask on line 3 */
2772 #define EXTI_IMR1_IM4_Pos            (4U)
2773 #define EXTI_IMR1_IM4_Msk            (0x1UL << EXTI_IMR1_IM4_Pos)              /*!< 0x00000010 */
2774 #define EXTI_IMR1_IM4                EXTI_IMR1_IM4_Msk                         /*!< Interrupt Mask on line 4 */
2775 #define EXTI_IMR1_IM5_Pos            (5U)
2776 #define EXTI_IMR1_IM5_Msk            (0x1UL << EXTI_IMR1_IM5_Pos)              /*!< 0x00000020 */
2777 #define EXTI_IMR1_IM5                EXTI_IMR1_IM5_Msk                         /*!< Interrupt Mask on line 5 */
2778 #define EXTI_IMR1_IM6_Pos            (6U)
2779 #define EXTI_IMR1_IM6_Msk            (0x1UL << EXTI_IMR1_IM6_Pos)              /*!< 0x00000040 */
2780 #define EXTI_IMR1_IM6                EXTI_IMR1_IM6_Msk                         /*!< Interrupt Mask on line 6 */
2781 #define EXTI_IMR1_IM7_Pos            (7U)
2782 #define EXTI_IMR1_IM7_Msk            (0x1UL << EXTI_IMR1_IM7_Pos)              /*!< 0x00000080 */
2783 #define EXTI_IMR1_IM7                EXTI_IMR1_IM7_Msk                         /*!< Interrupt Mask on line 7 */
2784 #define EXTI_IMR1_IM8_Pos            (8U)
2785 #define EXTI_IMR1_IM8_Msk            (0x1UL << EXTI_IMR1_IM8_Pos)              /*!< 0x00000100 */
2786 #define EXTI_IMR1_IM8                EXTI_IMR1_IM8_Msk                         /*!< Interrupt Mask on line 8 */
2787 #define EXTI_IMR1_IM9_Pos            (9U)
2788 #define EXTI_IMR1_IM9_Msk            (0x1UL << EXTI_IMR1_IM9_Pos)              /*!< 0x00000200 */
2789 #define EXTI_IMR1_IM9                EXTI_IMR1_IM9_Msk                         /*!< Interrupt Mask on line 9 */
2790 #define EXTI_IMR1_IM10_Pos           (10U)
2791 #define EXTI_IMR1_IM10_Msk           (0x1UL << EXTI_IMR1_IM10_Pos)             /*!< 0x00000400 */
2792 #define EXTI_IMR1_IM10               EXTI_IMR1_IM10_Msk                        /*!< Interrupt Mask on line 10 */
2793 #define EXTI_IMR1_IM11_Pos           (11U)
2794 #define EXTI_IMR1_IM11_Msk           (0x1UL << EXTI_IMR1_IM11_Pos)             /*!< 0x00000800 */
2795 #define EXTI_IMR1_IM11               EXTI_IMR1_IM11_Msk                        /*!< Interrupt Mask on line 11 */
2796 #define EXTI_IMR1_IM12_Pos           (12U)
2797 #define EXTI_IMR1_IM12_Msk           (0x1UL << EXTI_IMR1_IM12_Pos)             /*!< 0x00001000 */
2798 #define EXTI_IMR1_IM12               EXTI_IMR1_IM12_Msk                        /*!< Interrupt Mask on line 12 */
2799 #define EXTI_IMR1_IM13_Pos           (13U)
2800 #define EXTI_IMR1_IM13_Msk           (0x1UL << EXTI_IMR1_IM13_Pos)             /*!< 0x00002000 */
2801 #define EXTI_IMR1_IM13               EXTI_IMR1_IM13_Msk                        /*!< Interrupt Mask on line 13 */
2802 #define EXTI_IMR1_IM14_Pos           (14U)
2803 #define EXTI_IMR1_IM14_Msk           (0x1UL << EXTI_IMR1_IM14_Pos)             /*!< 0x00004000 */
2804 #define EXTI_IMR1_IM14               EXTI_IMR1_IM14_Msk                        /*!< Interrupt Mask on line 14 */
2805 #define EXTI_IMR1_IM15_Pos           (15U)
2806 #define EXTI_IMR1_IM15_Msk           (0x1UL << EXTI_IMR1_IM15_Pos)             /*!< 0x00008000 */
2807 #define EXTI_IMR1_IM15               EXTI_IMR1_IM15_Msk                        /*!< Interrupt Mask on line 15 */
2808 #define EXTI_IMR1_IM16_Pos           (16U)
2809 #define EXTI_IMR1_IM16_Msk           (0x1UL << EXTI_IMR1_IM16_Pos)             /*!< 0x00010000 */
2810 #define EXTI_IMR1_IM16               EXTI_IMR1_IM16_Msk                        /*!< Interrupt Mask on line 16 */
2811 #define EXTI_IMR1_IM17_Pos           (17U)
2812 #define EXTI_IMR1_IM17_Msk           (0x1UL << EXTI_IMR1_IM17_Pos)             /*!< 0x00020000 */
2813 #define EXTI_IMR1_IM17               EXTI_IMR1_IM17_Msk                        /*!< Interrupt Mask on line 17 */
2814 #define EXTI_IMR1_IM18_Pos           (18U)
2815 #define EXTI_IMR1_IM18_Msk           (0x1UL << EXTI_IMR1_IM18_Pos)             /*!< 0x00040000 */
2816 #define EXTI_IMR1_IM18               EXTI_IMR1_IM18_Msk                        /*!< Interrupt Mask on line 18 */
2817 #define EXTI_IMR1_IM19_Pos           (19U)
2818 #define EXTI_IMR1_IM19_Msk           (0x1UL << EXTI_IMR1_IM19_Pos)             /*!< 0x00080000 */
2819 #define EXTI_IMR1_IM19               EXTI_IMR1_IM19_Msk                        /*!< Interrupt Mask on line 19 */
2820 #define EXTI_IMR1_IM21_Pos           (21U)
2821 #define EXTI_IMR1_IM21_Msk           (0x1UL << EXTI_IMR1_IM21_Pos)             /*!< 0x00200000 */
2822 #define EXTI_IMR1_IM21               EXTI_IMR1_IM21_Msk                        /*!< Interrupt Mask on line 21 */
2823 #define EXTI_IMR1_IM23_Pos           (23U)
2824 #define EXTI_IMR1_IM23_Msk           (0x1UL << EXTI_IMR1_IM23_Pos)             /*!< 0x00800000 */
2825 #define EXTI_IMR1_IM23               EXTI_IMR1_IM23_Msk                        /*!< Interrupt Mask on line 23 */
2826 #define EXTI_IMR1_IM25_Pos           (25U)
2827 #define EXTI_IMR1_IM25_Msk           (0x1UL << EXTI_IMR1_IM25_Pos)             /*!< 0x02000000 */
2828 #define EXTI_IMR1_IM25               EXTI_IMR1_IM25_Msk                        /*!< Interrupt Mask on line 25 */
2829 #define EXTI_IMR1_IM26_Pos           (26U)
2830 #define EXTI_IMR1_IM26_Msk           (0x1UL << EXTI_IMR1_IM26_Pos)             /*!< 0x04000000 */
2831 #define EXTI_IMR1_IM26               EXTI_IMR1_IM26_Msk                        /*!< Interrupt Mask on line 26 */
2832 #define EXTI_IMR1_IM27_Pos           (27U)
2833 #define EXTI_IMR1_IM27_Msk           (0x1UL << EXTI_IMR1_IM27_Pos)             /*!< 0x08000000 */
2834 #define EXTI_IMR1_IM27               EXTI_IMR1_IM27_Msk                        /*!< Interrupt Mask on line 27 */
2835 #define EXTI_IMR1_IM28_Pos           (28U)
2836 #define EXTI_IMR1_IM28_Msk           (0x1UL << EXTI_IMR1_IM28_Pos)             /*!< 0x10000000 */
2837 #define EXTI_IMR1_IM28               EXTI_IMR1_IM28_Msk                        /*!< Interrupt Mask on line 28 */
2838 #define EXTI_IMR1_IM29_Pos           (29U)
2839 #define EXTI_IMR1_IM29_Msk           (0x1UL << EXTI_IMR1_IM29_Pos)             /*!< 0x20000000 */
2840 #define EXTI_IMR1_IM29               EXTI_IMR1_IM29_Msk                        /*!< Interrupt Mask on line 29 */
2841 #define EXTI_IMR1_IM30_Pos           (30U)
2842 #define EXTI_IMR1_IM30_Msk           (0x1UL << EXTI_IMR1_IM30_Pos)             /*!< 0x40000000 */
2843 #define EXTI_IMR1_IM30               EXTI_IMR1_IM30_Msk                        /*!< Interrupt Mask on line 30 */
2844 #define EXTI_IMR1_IM31_Pos           (31U)
2845 #define EXTI_IMR1_IM31_Msk           (0x1UL << EXTI_IMR1_IM31_Pos)              /*!< 0x80000000 */
2846 #define EXTI_IMR1_IM31               EXTI_IMR1_IM31_Msk                        /*!< Interrupt Mask on line 31 */
2847 #define EXTI_IMR1_IM_Pos             (0U)
2848 #define EXTI_IMR1_IM_Msk             (0xFEAFFFFFUL << EXTI_IMR1_IM_Pos)        /*!< 0xFEAFFFFF */
2849 #define EXTI_IMR1_IM                 EXTI_IMR1_IM_Msk                          /*!< Interrupt Mask All */
2850 
2851 /*******************  Bit definition for EXTI_IMR2 register  ******************/
2852 #define EXTI_IMR2_IM32_Pos           (0U)
2853 #define EXTI_IMR2_IM32_Msk           (0x1UL << EXTI_IMR2_IM32_Pos)             /*!< 0x00000001 */
2854 #define EXTI_IMR2_IM32               EXTI_IMR2_IM32_Msk                        /*!< Interrupt Mask on line 32 */
2855 #define EXTI_IMR2_IM33_Pos           (1U)
2856 #define EXTI_IMR2_IM33_Msk           (0x1UL << EXTI_IMR2_IM33_Pos)             /*!< 0x00000002 */
2857 #define EXTI_IMR2_IM33               EXTI_IMR2_IM33_Msk                        /*!< Interrupt Mask on line 33 */
2858 #define EXTI_IMR2_IM_Pos             (0U)
2859 #define EXTI_IMR2_IM_Msk             (0x3UL << EXTI_IMR2_IM_Pos)               /*!< 0x00000003 */
2860 #define EXTI_IMR2_IM                 EXTI_IMR2_IM_Msk                          /*!< Interrupt Mask All */
2861 
2862 /*******************  Bit definition for EXTI_EMR1 register  ******************/
2863 #define EXTI_EMR1_EM0_Pos            (0U)
2864 #define EXTI_EMR1_EM0_Msk            (0x1UL << EXTI_EMR1_EM0_Pos)              /*!< 0x00000001 */
2865 #define EXTI_EMR1_EM0                EXTI_EMR1_EM0_Msk                         /*!< Event Mask on line 0 */
2866 #define EXTI_EMR1_EM1_Pos            (1U)
2867 #define EXTI_EMR1_EM1_Msk            (0x1UL << EXTI_EMR1_EM1_Pos)              /*!< 0x00000002 */
2868 #define EXTI_EMR1_EM1                EXTI_EMR1_EM1_Msk                         /*!< Event Mask on line 1 */
2869 #define EXTI_EMR1_EM2_Pos            (2U)
2870 #define EXTI_EMR1_EM2_Msk            (0x1UL << EXTI_EMR1_EM2_Pos)              /*!< 0x00000004 */
2871 #define EXTI_EMR1_EM2                EXTI_EMR1_EM2_Msk                         /*!< Event Mask on line 2 */
2872 #define EXTI_EMR1_EM3_Pos            (3U)
2873 #define EXTI_EMR1_EM3_Msk            (0x1UL << EXTI_EMR1_EM3_Pos)              /*!< 0x00000008 */
2874 #define EXTI_EMR1_EM3                EXTI_EMR1_EM3_Msk                         /*!< Event Mask on line 3 */
2875 #define EXTI_EMR1_EM4_Pos            (4U)
2876 #define EXTI_EMR1_EM4_Msk            (0x1UL << EXTI_EMR1_EM4_Pos)              /*!< 0x00000010 */
2877 #define EXTI_EMR1_EM4                EXTI_EMR1_EM4_Msk                         /*!< Event Mask on line 4 */
2878 #define EXTI_EMR1_EM5_Pos            (5U)
2879 #define EXTI_EMR1_EM5_Msk            (0x1UL << EXTI_EMR1_EM5_Pos)              /*!< 0x00000020 */
2880 #define EXTI_EMR1_EM5                EXTI_EMR1_EM5_Msk                         /*!< Event Mask on line 5 */
2881 #define EXTI_EMR1_EM6_Pos            (6U)
2882 #define EXTI_EMR1_EM6_Msk            (0x1UL << EXTI_EMR1_EM6_Pos)              /*!< 0x00000040 */
2883 #define EXTI_EMR1_EM6                EXTI_EMR1_EM6_Msk                         /*!< Event Mask on line 6 */
2884 #define EXTI_EMR1_EM7_Pos            (7U)
2885 #define EXTI_EMR1_EM7_Msk            (0x1UL << EXTI_EMR1_EM7_Pos)              /*!< 0x00000080 */
2886 #define EXTI_EMR1_EM7                EXTI_EMR1_EM7_Msk                         /*!< Event Mask on line 7 */
2887 #define EXTI_EMR1_EM8_Pos            (8U)
2888 #define EXTI_EMR1_EM8_Msk            (0x1UL << EXTI_EMR1_EM8_Pos)              /*!< 0x00000100 */
2889 #define EXTI_EMR1_EM8                EXTI_EMR1_EM8_Msk                         /*!< Event Mask on line 8 */
2890 #define EXTI_EMR1_EM9_Pos            (9U)
2891 #define EXTI_EMR1_EM9_Msk            (0x1UL << EXTI_EMR1_EM9_Pos)              /*!< 0x00000200 */
2892 #define EXTI_EMR1_EM9                EXTI_EMR1_EM9_Msk                         /*!< Event Mask on line 9 */
2893 #define EXTI_EMR1_EM10_Pos           (10U)
2894 #define EXTI_EMR1_EM10_Msk           (0x1UL << EXTI_EMR1_EM10_Pos)             /*!< 0x00000400 */
2895 #define EXTI_EMR1_EM10               EXTI_EMR1_EM10_Msk                        /*!< Event Mask on line 10 */
2896 #define EXTI_EMR1_EM11_Pos           (11U)
2897 #define EXTI_EMR1_EM11_Msk           (0x1UL << EXTI_EMR1_EM11_Pos)             /*!< 0x00000800 */
2898 #define EXTI_EMR1_EM11               EXTI_EMR1_EM11_Msk                        /*!< Event Mask on line 11 */
2899 #define EXTI_EMR1_EM12_Pos           (12U)
2900 #define EXTI_EMR1_EM12_Msk           (0x1UL << EXTI_EMR1_EM12_Pos)             /*!< 0x00001000 */
2901 #define EXTI_EMR1_EM12               EXTI_EMR1_EM12_Msk                        /*!< Event Mask on line 12 */
2902 #define EXTI_EMR1_EM13_Pos           (13U)
2903 #define EXTI_EMR1_EM13_Msk           (0x1UL << EXTI_EMR1_EM13_Pos)             /*!< 0x00002000 */
2904 #define EXTI_EMR1_EM13               EXTI_EMR1_EM13_Msk                        /*!< Event Mask on line 13 */
2905 #define EXTI_EMR1_EM14_Pos           (14U)
2906 #define EXTI_EMR1_EM14_Msk           (0x1UL << EXTI_EMR1_EM14_Pos)             /*!< 0x00004000 */
2907 #define EXTI_EMR1_EM14               EXTI_EMR1_EM14_Msk                        /*!< Event Mask on line 14 */
2908 #define EXTI_EMR1_EM15_Pos           (15U)
2909 #define EXTI_EMR1_EM15_Msk           (0x1UL << EXTI_EMR1_EM15_Pos)             /*!< 0x00008000 */
2910 #define EXTI_EMR1_EM15               EXTI_EMR1_EM15_Msk                        /*!< Event Mask on line 15 */
2911 #define EXTI_EMR1_EM16_Pos           (16U)
2912 #define EXTI_EMR1_EM16_Msk           (0x1UL << EXTI_EMR1_EM16_Pos)             /*!< 0x00010000 */
2913 #define EXTI_EMR1_EM16               EXTI_EMR1_EM16_Msk                        /*!< Event Mask on line 16 */
2914 #define EXTI_EMR1_EM17_Pos           (17U)
2915 #define EXTI_EMR1_EM17_Msk           (0x1UL << EXTI_EMR1_EM17_Pos)             /*!< 0x00020000 */
2916 #define EXTI_EMR1_EM17               EXTI_EMR1_EM17_Msk                        /*!< Event Mask on line 17 */
2917 #define EXTI_EMR1_EM18_Pos           (18U)
2918 #define EXTI_EMR1_EM18_Msk           (0x1UL << EXTI_EMR1_EM18_Pos)             /*!< 0x00040000 */
2919 #define EXTI_EMR1_EM18               EXTI_EMR1_EM18_Msk                        /*!< Event Mask on line 18 */
2920 #define EXTI_EMR1_EM19_Pos           (19U)
2921 #define EXTI_EMR1_EM19_Msk           (0x1UL << EXTI_EMR1_EM19_Pos)             /*!< 0x00080000 */
2922 #define EXTI_EMR1_EM19               EXTI_EMR1_EM19_Msk                        /*!< Event Mask on line 19 */
2923 #define EXTI_EMR1_EM21_Pos           (21U)
2924 #define EXTI_EMR1_EM21_Msk           (0x1UL << EXTI_EMR1_EM21_Pos)             /*!< 0x00200000 */
2925 #define EXTI_EMR1_EM21               EXTI_EMR1_EM21_Msk                        /*!< Event Mask on line 21 */
2926 #define EXTI_EMR1_EM23_Pos           (23U)
2927 #define EXTI_EMR1_EM23_Msk           (0x1UL << EXTI_EMR1_EM23_Pos)             /*!< 0x00800000 */
2928 #define EXTI_EMR1_EM23               EXTI_EMR1_EM23_Msk                        /*!< Event Mask on line 23 */
2929 #define EXTI_EMR1_EM25_Pos           (25U)
2930 #define EXTI_EMR1_EM25_Msk           (0x1UL << EXTI_EMR1_EM25_Pos)             /*!< 0x02000000 */
2931 #define EXTI_EMR1_EM25               EXTI_EMR1_EM25_Msk                        /*!< Event Mask on line 25 */
2932 #define EXTI_EMR1_EM26_Pos           (26U)
2933 #define EXTI_EMR1_EM26_Msk           (0x1UL << EXTI_EMR1_EM26_Pos)             /*!< 0x04000000 */
2934 #define EXTI_EMR1_EM26               EXTI_EMR1_EM26_Msk                        /*!< Event Mask on line 26 */
2935 #define EXTI_EMR1_EM27_Pos           (27U)
2936 #define EXTI_EMR1_EM27_Msk           (0x1UL << EXTI_EMR1_EM27_Pos)             /*!< 0x08000000 */
2937 #define EXTI_EMR1_EM27               EXTI_EMR1_EM27_Msk                        /*!< Event Mask on line 27 */
2938 #define EXTI_EMR1_EM28_Pos           (28U)
2939 #define EXTI_EMR1_EM28_Msk           (0x1UL << EXTI_EMR1_EM28_Pos)             /*!< 0x10000000 */
2940 #define EXTI_EMR1_EM28               EXTI_EMR1_EM28_Msk                        /*!< Event Mask on line 28 */
2941 #define EXTI_EMR1_EM29_Pos           (29U)
2942 #define EXTI_EMR1_EM29_Msk           (0x1UL << EXTI_EMR1_EM29_Pos)             /*!< 0x20000000 */
2943 #define EXTI_EMR1_EM29               EXTI_EMR1_EM29_Msk                        /*!< Event Mask on line 29 */
2944 #define EXTI_EMR1_EM30_Pos           (30U)
2945 #define EXTI_EMR1_EM30_Msk           (0x1UL << EXTI_EMR1_EM30_Pos)             /*!< 0x40000000 */
2946 #define EXTI_EMR1_EM30               EXTI_EMR1_EM30_Msk                        /*!< Event Mask on line 30 */
2947 #define EXTI_EMR1_EM31_Pos           (31U)
2948 #define EXTI_EMR1_EM31_Msk           (0x1UL << EXTI_EMR1_EM31_Pos)             /*!< 0x80000000 */
2949 #define EXTI_EMR1_EM31               EXTI_EMR1_EM31_Msk                        /*!< Event Mask on line 31 */
2950 
2951 /*******************  Bit definition for EXTI_EMR2 register  ******************/
2952 #define EXTI_EMR2_EM32_Pos           (0U)
2953 #define EXTI_EMR2_EM32_Msk           (0x1UL << EXTI_EMR2_EM32_Pos)             /*!< 0x00000001 */
2954 #define EXTI_EMR2_EM32               EXTI_EMR2_EM32_Msk                        /*!< Event Mask on line 32 */
2955 #define EXTI_EMR2_EM33_Pos           (1U)
2956 #define EXTI_EMR2_EM33_Msk           (0x1UL << EXTI_EMR2_EM33_Pos)             /*!< 0x00000002 */
2957 #define EXTI_EMR2_EM33               EXTI_EMR2_EM33_Msk                        /*!< Event Mask on line 33 */
2958 
2959 /******************************************************************************/
2960 /*                                                                            */
2961 /*                                    FLASH                                   */
2962 /*                                                                            */
2963 /******************************************************************************/
2964 #define GPIO_NRST_CONFIG_SUPPORT         /*!< GPIO feature available only on specific devices: Configure NRST pin */
2965 #define FLASH_SECURABLE_MEMORY_SUPPORT   /*!< Flash feature available only on specific devices: allow to secure memory */
2966 #define FLASH_PCROP_SUPPORT              /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */
2967 
2968 /*******************  Bits definition for FLASH_ACR register  *****************/
2969 #define FLASH_ACR_LATENCY_Pos                  (0U)
2970 #define FLASH_ACR_LATENCY_Msk                  (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
2971 #define FLASH_ACR_LATENCY                      FLASH_ACR_LATENCY_Msk
2972 #define FLASH_ACR_LATENCY_0                    (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
2973 #define FLASH_ACR_LATENCY_1                    (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
2974 #define FLASH_ACR_LATENCY_2                    (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
2975 #define FLASH_ACR_PRFTEN_Pos                   (8U)
2976 #define FLASH_ACR_PRFTEN_Msk                   (0x1UL << FLASH_ACR_PRFTEN_Pos)  /*!< 0x00000100 */
2977 #define FLASH_ACR_PRFTEN                       FLASH_ACR_PRFTEN_Msk
2978 #define FLASH_ACR_ICEN_Pos                     (9U)
2979 #define FLASH_ACR_ICEN_Msk                     (0x1UL << FLASH_ACR_ICEN_Pos)    /*!< 0x00000200 */
2980 #define FLASH_ACR_ICEN                         FLASH_ACR_ICEN_Msk
2981 #define FLASH_ACR_ICRST_Pos                    (11U)
2982 #define FLASH_ACR_ICRST_Msk                    (0x1UL << FLASH_ACR_ICRST_Pos)   /*!< 0x00000800 */
2983 #define FLASH_ACR_ICRST                        FLASH_ACR_ICRST_Msk
2984 #define FLASH_ACR_PROGEMPTY_Pos                (16U)
2985 #define FLASH_ACR_PROGEMPTY_Msk                (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
2986 #define FLASH_ACR_PROGEMPTY                    FLASH_ACR_PROGEMPTY_Msk
2987 #define FLASH_ACR_DBG_SWEN_Pos                 (18U)
2988 #define FLASH_ACR_DBG_SWEN_Msk                 (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
2989 #define FLASH_ACR_DBG_SWEN                     FLASH_ACR_DBG_SWEN_Msk
2990 
2991 /*******************  Bits definition for FLASH_SR register  ******************/
2992 #define FLASH_SR_EOP_Pos                       (0U)
2993 #define FLASH_SR_EOP_Msk                       (0x1UL << FLASH_SR_EOP_Pos)      /*!< 0x00000001 */
2994 #define FLASH_SR_EOP                           FLASH_SR_EOP_Msk
2995 #define FLASH_SR_OPERR_Pos                     (1U)
2996 #define FLASH_SR_OPERR_Msk                     (0x1UL << FLASH_SR_OPERR_Pos)    /*!< 0x00000002 */
2997 #define FLASH_SR_OPERR                         FLASH_SR_OPERR_Msk
2998 #define FLASH_SR_PROGERR_Pos                   (3U)
2999 #define FLASH_SR_PROGERR_Msk                   (0x1UL << FLASH_SR_PROGERR_Pos)  /*!< 0x00000008 */
3000 #define FLASH_SR_PROGERR                       FLASH_SR_PROGERR_Msk
3001 #define FLASH_SR_WRPERR_Pos                    (4U)
3002 #define FLASH_SR_WRPERR_Msk                    (0x1UL << FLASH_SR_WRPERR_Pos)   /*!< 0x00000010 */
3003 #define FLASH_SR_WRPERR                        FLASH_SR_WRPERR_Msk
3004 #define FLASH_SR_PGAERR_Pos                    (5U)
3005 #define FLASH_SR_PGAERR_Msk                    (0x1UL << FLASH_SR_PGAERR_Pos)   /*!< 0x00000020 */
3006 #define FLASH_SR_PGAERR                        FLASH_SR_PGAERR_Msk
3007 #define FLASH_SR_SIZERR_Pos                    (6U)
3008 #define FLASH_SR_SIZERR_Msk                    (0x1UL << FLASH_SR_SIZERR_Pos)   /*!< 0x00000040 */
3009 #define FLASH_SR_SIZERR                        FLASH_SR_SIZERR_Msk
3010 #define FLASH_SR_PGSERR_Pos                    (7U)
3011 #define FLASH_SR_PGSERR_Msk                    (0x1UL << FLASH_SR_PGSERR_Pos)   /*!< 0x00000080 */
3012 #define FLASH_SR_PGSERR                        FLASH_SR_PGSERR_Msk
3013 #define FLASH_SR_MISERR_Pos                    (8U)
3014 #define FLASH_SR_MISERR_Msk                    (0x1UL << FLASH_SR_MISERR_Pos)   /*!< 0x00000100 */
3015 #define FLASH_SR_MISERR                        FLASH_SR_MISERR_Msk
3016 #define FLASH_SR_FASTERR_Pos                   (9U)
3017 #define FLASH_SR_FASTERR_Msk                   (0x1UL << FLASH_SR_FASTERR_Pos)  /*!< 0x00000200 */
3018 #define FLASH_SR_FASTERR                       FLASH_SR_FASTERR_Msk
3019 #define FLASH_SR_RDERR_Pos                     (14U)
3020 #define FLASH_SR_RDERR_Msk                     (0x1UL << FLASH_SR_RDERR_Pos)    /*!< 0x00004000 */
3021 #define FLASH_SR_RDERR                         FLASH_SR_RDERR_Msk
3022 #define FLASH_SR_OPTVERR_Pos                   (15U)
3023 #define FLASH_SR_OPTVERR_Msk                   (0x1UL << FLASH_SR_OPTVERR_Pos)  /*!< 0x00008000 */
3024 #define FLASH_SR_OPTVERR                       FLASH_SR_OPTVERR_Msk
3025 #define FLASH_SR_BSY1_Pos                      (16U)
3026 #define FLASH_SR_BSY1_Msk                      (0x1UL << FLASH_SR_BSY1_Pos)     /*!< 0x00010000 */
3027 #define FLASH_SR_BSY1                          FLASH_SR_BSY1_Msk
3028 #define FLASH_SR_CFGBSY_Pos                    (18U)
3029 #define FLASH_SR_CFGBSY_Msk                    (0x1UL << FLASH_SR_CFGBSY_Pos)   /*!< 0x00040000 */
3030 #define FLASH_SR_CFGBSY                        FLASH_SR_CFGBSY_Msk
3031 
3032 /*******************  Bits definition for FLASH_CR register  ******************/
3033 #define FLASH_CR_PG_Pos                        (0U)
3034 #define FLASH_CR_PG_Msk                        (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
3035 #define FLASH_CR_PG                            FLASH_CR_PG_Msk
3036 #define FLASH_CR_PER_Pos                       (1U)
3037 #define FLASH_CR_PER_Msk                       (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
3038 #define FLASH_CR_PER                           FLASH_CR_PER_Msk
3039 #define FLASH_CR_MER1_Pos                      (2U)
3040 #define FLASH_CR_MER1_Msk                      (0x1UL << FLASH_CR_MER1_Pos)       /*!< 0x00000004 */
3041 #define FLASH_CR_MER1                          FLASH_CR_MER1_Msk
3042 #define FLASH_CR_PNB_Pos                       (3U)
3043 #define FLASH_CR_PNB_Msk                       (0x3FFUL << FLASH_CR_PNB_Pos)       /*!< 0x00001FF8 */
3044 #define FLASH_CR_PNB                           FLASH_CR_PNB_Msk
3045 #define FLASH_CR_STRT_Pos                      (16U)
3046 #define FLASH_CR_STRT_Msk                      (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
3047 #define FLASH_CR_STRT                          FLASH_CR_STRT_Msk
3048 #define FLASH_CR_OPTSTRT_Pos                   (17U)
3049 #define FLASH_CR_OPTSTRT_Msk                   (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
3050 #define FLASH_CR_OPTSTRT                       FLASH_CR_OPTSTRT_Msk
3051 #define FLASH_CR_FSTPG_Pos                     (18U)
3052 #define FLASH_CR_FSTPG_Msk                     (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
3053 #define FLASH_CR_FSTPG                         FLASH_CR_FSTPG_Msk
3054 #define FLASH_CR_EOPIE_Pos                     (24U)
3055 #define FLASH_CR_EOPIE_Msk                     (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
3056 #define FLASH_CR_EOPIE                         FLASH_CR_EOPIE_Msk
3057 #define FLASH_CR_ERRIE_Pos                     (25U)
3058 #define FLASH_CR_ERRIE_Msk                     (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
3059 #define FLASH_CR_ERRIE                         FLASH_CR_ERRIE_Msk
3060 #define FLASH_CR_RDERRIE_Pos                   (26U)
3061 #define FLASH_CR_RDERRIE_Msk                   (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
3062 #define FLASH_CR_RDERRIE                       FLASH_CR_RDERRIE_Msk
3063 #define FLASH_CR_OBL_LAUNCH_Pos                (27U)
3064 #define FLASH_CR_OBL_LAUNCH_Msk                (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
3065 #define FLASH_CR_OBL_LAUNCH                    FLASH_CR_OBL_LAUNCH_Msk
3066 #define FLASH_CR_SEC_PROT_Pos                  (28U)
3067 #define FLASH_CR_SEC_PROT_Msk                  (0x1UL << FLASH_CR_SEC_PROT_Pos)   /*!< 0x10000000 */
3068 #define FLASH_CR_SEC_PROT                      FLASH_CR_SEC_PROT_Msk
3069 #define FLASH_CR_OPTLOCK_Pos                   (30U)
3070 #define FLASH_CR_OPTLOCK_Msk                   (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
3071 #define FLASH_CR_OPTLOCK                       FLASH_CR_OPTLOCK_Msk
3072 #define FLASH_CR_LOCK_Pos                      (31U)
3073 #define FLASH_CR_LOCK_Msk                      (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
3074 #define FLASH_CR_LOCK                          FLASH_CR_LOCK_Msk
3075 
3076 /*******************  Bits definition for FLASH_ECCR register  ****************/
3077 #define FLASH_ECCR_ADDR_ECC_Pos                (0U)
3078 #define FLASH_ECCR_ADDR_ECC_Msk                (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos)  /*!< 0x00003FFF */
3079 #define FLASH_ECCR_ADDR_ECC                    FLASH_ECCR_ADDR_ECC_Msk
3080 #define FLASH_ECCR_SYSF_ECC_Pos                (20U)
3081 #define FLASH_ECCR_SYSF_ECC_Msk                (0x1UL << FLASH_ECCR_SYSF_ECC_Pos)     /*!< 0x00100000 */
3082 #define FLASH_ECCR_SYSF_ECC                    FLASH_ECCR_SYSF_ECC_Msk
3083 #define FLASH_ECCR_ECCCIE_Pos                  (24U)
3084 #define FLASH_ECCR_ECCCIE_Msk                  (0x1UL << FLASH_ECCR_ECCCIE_Pos)       /*!< 0x01000000 */
3085 #define FLASH_ECCR_ECCCIE                      FLASH_ECCR_ECCCIE_Msk
3086 #define FLASH_ECCR_ECCC_Pos                    (30U)
3087 #define FLASH_ECCR_ECCC_Msk                    (0x1UL << FLASH_ECCR_ECCC_Pos)         /*!< 0x40000000 */
3088 #define FLASH_ECCR_ECCC                        FLASH_ECCR_ECCC_Msk
3089 #define FLASH_ECCR_ECCD_Pos                    (31U)
3090 #define FLASH_ECCR_ECCD_Msk                    (0x1UL << FLASH_ECCR_ECCD_Pos)         /*!< 0x80000000 */
3091 #define FLASH_ECCR_ECCD                        FLASH_ECCR_ECCD_Msk
3092 
3093 /*******************  Bits definition for FLASH_OPTR register  ****************/
3094 #define FLASH_OPTR_RDP_Pos                     (0U)
3095 #define FLASH_OPTR_RDP_Msk                     (0xFFUL << FLASH_OPTR_RDP_Pos)             /*!< 0x000000FF */
3096 #define FLASH_OPTR_RDP                         FLASH_OPTR_RDP_Msk
3097 #define FLASH_OPTR_BOR_EN_Pos                  (8U)
3098 #define FLASH_OPTR_BOR_EN_Msk                  (0x1UL << FLASH_OPTR_BOR_EN_Pos)           /*!< 0x00000100 */
3099 #define FLASH_OPTR_BOR_EN                      FLASH_OPTR_BOR_EN_Msk
3100 #define FLASH_OPTR_BORR_LEV_Pos                (9U)
3101 #define FLASH_OPTR_BORR_LEV_Msk                (0x3UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000600 */
3102 #define FLASH_OPTR_BORR_LEV                    FLASH_OPTR_BORR_LEV_Msk
3103 #define FLASH_OPTR_BORR_LEV_0                  (0x1UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000200 */
3104 #define FLASH_OPTR_BORR_LEV_1                  (0x2UL << FLASH_OPTR_BORR_LEV_Pos)         /*!< 0x00000400 */
3105 #define FLASH_OPTR_BORF_LEV_Pos                (11U)
3106 #define FLASH_OPTR_BORF_LEV_Msk                (0x3UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001800 */
3107 #define FLASH_OPTR_BORF_LEV                    FLASH_OPTR_BORF_LEV_Msk
3108 #define FLASH_OPTR_BORF_LEV_0                  (0x1UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00000800 */
3109 #define FLASH_OPTR_BORF_LEV_1                  (0x2UL << FLASH_OPTR_BORF_LEV_Pos)         /*!< 0x00001000 */
3110 #define FLASH_OPTR_nRST_STOP_Pos               (13U)
3111 #define FLASH_OPTR_nRST_STOP_Msk               (0x1UL << FLASH_OPTR_nRST_STOP_Pos)        /*!< 0x00002000 */
3112 #define FLASH_OPTR_nRST_STOP                   FLASH_OPTR_nRST_STOP_Msk
3113 #define FLASH_OPTR_nRST_STDBY_Pos              (14U)
3114 #define FLASH_OPTR_nRST_STDBY_Msk              (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)       /*!< 0x00004000 */
3115 #define FLASH_OPTR_nRST_STDBY                  FLASH_OPTR_nRST_STDBY_Msk
3116 #define FLASH_OPTR_nRST_SHDW_Pos               (15U)
3117 #define FLASH_OPTR_nRST_SHDW_Msk               (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)        /*!< 0x00008000 */
3118 #define FLASH_OPTR_nRST_SHDW                   FLASH_OPTR_nRST_SHDW_Msk
3119 #define FLASH_OPTR_IWDG_SW_Pos                 (16U)
3120 #define FLASH_OPTR_IWDG_SW_Msk                 (0x1UL << FLASH_OPTR_IWDG_SW_Pos)          /*!< 0x00010000 */
3121 #define FLASH_OPTR_IWDG_SW                     FLASH_OPTR_IWDG_SW_Msk
3122 #define FLASH_OPTR_IWDG_STOP_Pos               (17U)
3123 #define FLASH_OPTR_IWDG_STOP_Msk               (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)        /*!< 0x00020000 */
3124 #define FLASH_OPTR_IWDG_STOP                   FLASH_OPTR_IWDG_STOP_Msk
3125 #define FLASH_OPTR_IWDG_STDBY_Pos              (18U)
3126 #define FLASH_OPTR_IWDG_STDBY_Msk              (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)       /*!< 0x00040000 */
3127 #define FLASH_OPTR_IWDG_STDBY                  FLASH_OPTR_IWDG_STDBY_Msk
3128 #define FLASH_OPTR_WWDG_SW_Pos                 (19U)
3129 #define FLASH_OPTR_WWDG_SW_Msk                 (0x1UL << FLASH_OPTR_WWDG_SW_Pos)          /*!< 0x00080000 */
3130 #define FLASH_OPTR_WWDG_SW                     FLASH_OPTR_WWDG_SW_Msk
3131 #define FLASH_OPTR_RAM_PARITY_CHECK_Pos        (22U)
3132 #define FLASH_OPTR_RAM_PARITY_CHECK_Msk        (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
3133 #define FLASH_OPTR_RAM_PARITY_CHECK            FLASH_OPTR_RAM_PARITY_CHECK_Msk
3134 #define FLASH_OPTR_nBOOT_SEL_Pos               (24U)
3135 #define FLASH_OPTR_nBOOT_SEL_Msk               (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos)        /*!< 0x01000000 */
3136 #define FLASH_OPTR_nBOOT_SEL                   FLASH_OPTR_nBOOT_SEL_Msk
3137 #define FLASH_OPTR_nBOOT1_Pos                  (25U)
3138 #define FLASH_OPTR_nBOOT1_Msk                  (0x1UL << FLASH_OPTR_nBOOT1_Pos)           /*!< 0x02000000 */
3139 #define FLASH_OPTR_nBOOT1                      FLASH_OPTR_nBOOT1_Msk
3140 #define FLASH_OPTR_nBOOT0_Pos                  (26U)
3141 #define FLASH_OPTR_nBOOT0_Msk                  (0x1UL << FLASH_OPTR_nBOOT0_Pos)           /*!< 0x04000000 */
3142 #define FLASH_OPTR_nBOOT0                      FLASH_OPTR_nBOOT0_Msk
3143 #define FLASH_OPTR_NRST_MODE_Pos               (27U)
3144 #define FLASH_OPTR_NRST_MODE_Msk               (0x3UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x18000000 */
3145 #define FLASH_OPTR_NRST_MODE                   FLASH_OPTR_NRST_MODE_Msk
3146 #define FLASH_OPTR_NRST_MODE_0                 (0x1UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x08000000 */
3147 #define FLASH_OPTR_NRST_MODE_1                 (0x2UL << FLASH_OPTR_NRST_MODE_Pos)        /*!< 0x10000000 */
3148 #define FLASH_OPTR_IRHEN_Pos                   (29U)
3149 #define FLASH_OPTR_IRHEN_Msk                   (0x1UL << FLASH_OPTR_IRHEN_Pos)            /*!< 0x20000000 */
3150 #define FLASH_OPTR_IRHEN                       FLASH_OPTR_IRHEN_Msk
3151 
3152 /******************  Bits definition for FLASH_PCROP1ASR register  ************/
3153 #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos       (0U)
3154 #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk       (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)   /*!< 0x000000FF */
3155 #define FLASH_PCROP1ASR_PCROP1A_STRT           FLASH_PCROP1ASR_PCROP1A_STRT_Msk
3156 
3157 /******************  Bits definition for FLASH_PCROP1AER register  ************/
3158 #define FLASH_PCROP1AER_PCROP1A_END_Pos        (0U)
3159 #define FLASH_PCROP1AER_PCROP1A_END_Msk        (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)    /*!< 0x000000FF */
3160 #define FLASH_PCROP1AER_PCROP1A_END            FLASH_PCROP1AER_PCROP1A_END_Msk
3161 #define FLASH_PCROP1AER_PCROP_RDP_Pos          (31U)
3162 #define FLASH_PCROP1AER_PCROP_RDP_Msk          (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)       /*!< 0x80000000 */
3163 #define FLASH_PCROP1AER_PCROP_RDP              FLASH_PCROP1AER_PCROP_RDP_Msk
3164 
3165 /******************  Bits definition for FLASH_WRP1AR register  ***************/
3166 #define FLASH_WRP1AR_WRP1A_STRT_Pos            (0U)
3167 #define FLASH_WRP1AR_WRP1A_STRT_Msk            (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000003F */
3168 #define FLASH_WRP1AR_WRP1A_STRT                FLASH_WRP1AR_WRP1A_STRT_Msk
3169 #define FLASH_WRP1AR_WRP1A_END_Pos             (16U)
3170 #define FLASH_WRP1AR_WRP1A_END_Msk             (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x003F0000 */
3171 #define FLASH_WRP1AR_WRP1A_END                 FLASH_WRP1AR_WRP1A_END_Msk
3172 
3173 /******************  Bits definition for FLASH_WRP1BR register  ***************/
3174 #define FLASH_WRP1BR_WRP1B_STRT_Pos            (0U)
3175 #define FLASH_WRP1BR_WRP1B_STRT_Msk            (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000003F */
3176 #define FLASH_WRP1BR_WRP1B_STRT                FLASH_WRP1BR_WRP1B_STRT_Msk
3177 #define FLASH_WRP1BR_WRP1B_END_Pos             (16U)
3178 #define FLASH_WRP1BR_WRP1B_END_Msk             (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x003F0000 */
3179 #define FLASH_WRP1BR_WRP1B_END                 FLASH_WRP1BR_WRP1B_END_Msk
3180 
3181 /******************  Bits definition for FLASH_PCROP1BSR register  ************/
3182 #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos       (0U)
3183 #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk       (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)   /*!< 0x000000FF */
3184 #define FLASH_PCROP1BSR_PCROP1B_STRT           FLASH_PCROP1BSR_PCROP1B_STRT_Msk
3185 
3186 /******************  Bits definition for FLASH_PCROP1BER register  ************/
3187 #define FLASH_PCROP1BER_PCROP1B_END_Pos        (0U)
3188 #define FLASH_PCROP1BER_PCROP1B_END_Msk        (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)    /*!< 0x000000FF */
3189 #define FLASH_PCROP1BER_PCROP1B_END            FLASH_PCROP1BER_PCROP1B_END_Msk
3190 
3191 
3192 /******************  Bits definition for FLASH_SECR register  *****************/
3193 #define FLASH_SECR_SEC_SIZE_Pos                (0U)
3194 #define FLASH_SECR_SEC_SIZE_Msk                (0x7FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000007F */
3195 #define FLASH_SECR_SEC_SIZE                    FLASH_SECR_SEC_SIZE_Msk
3196 #define FLASH_SECR_BOOT_LOCK_Pos               (16U)
3197 #define FLASH_SECR_BOOT_LOCK_Msk               (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
3198 #define FLASH_SECR_BOOT_LOCK                   FLASH_SECR_BOOT_LOCK_Msk
3199 
3200 /******************************************************************************/
3201 /*                                                                            */
3202 /*                            General Purpose I/O                             */
3203 /*                                                                            */
3204 /******************************************************************************/
3205 /******************  Bits definition for GPIO_MODER register  *****************/
3206 #define GPIO_MODER_MODE0_Pos           (0U)
3207 #define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000003 */
3208 #define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
3209 #define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
3210 #define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
3211 #define GPIO_MODER_MODE1_Pos           (2U)
3212 #define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)          /*!< 0x0000000C */
3213 #define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
3214 #define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
3215 #define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
3216 #define GPIO_MODER_MODE2_Pos           (4U)
3217 #define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000030 */
3218 #define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
3219 #define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
3220 #define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
3221 #define GPIO_MODER_MODE3_Pos           (6U)
3222 #define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)          /*!< 0x000000C0 */
3223 #define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
3224 #define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
3225 #define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
3226 #define GPIO_MODER_MODE4_Pos           (8U)
3227 #define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000300 */
3228 #define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
3229 #define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
3230 #define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
3231 #define GPIO_MODER_MODE5_Pos           (10U)
3232 #define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000C00 */
3233 #define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
3234 #define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
3235 #define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
3236 #define GPIO_MODER_MODE6_Pos           (12U)
3237 #define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00003000 */
3238 #define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
3239 #define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
3240 #define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
3241 #define GPIO_MODER_MODE7_Pos           (14U)
3242 #define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)          /*!< 0x0000C000 */
3243 #define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
3244 #define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
3245 #define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
3246 #define GPIO_MODER_MODE8_Pos           (16U)
3247 #define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00030000 */
3248 #define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
3249 #define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
3250 #define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
3251 #define GPIO_MODER_MODE9_Pos           (18U)
3252 #define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)          /*!< 0x000C0000 */
3253 #define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
3254 #define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
3255 #define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
3256 #define GPIO_MODER_MODE10_Pos          (20U)
3257 #define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00300000 */
3258 #define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
3259 #define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
3260 #define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
3261 #define GPIO_MODER_MODE11_Pos          (22U)
3262 #define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00C00000 */
3263 #define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
3264 #define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
3265 #define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
3266 #define GPIO_MODER_MODE12_Pos          (24U)
3267 #define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)         /*!< 0x03000000 */
3268 #define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
3269 #define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
3270 #define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
3271 #define GPIO_MODER_MODE13_Pos          (26U)
3272 #define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)         /*!< 0x0C000000 */
3273 #define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
3274 #define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
3275 #define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
3276 #define GPIO_MODER_MODE14_Pos          (28U)
3277 #define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)         /*!< 0x30000000 */
3278 #define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
3279 #define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
3280 #define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
3281 #define GPIO_MODER_MODE15_Pos          (30U)
3282 #define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)         /*!< 0xC0000000 */
3283 #define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
3284 #define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
3285 #define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
3286 
3287 /******************  Bits definition for GPIO_OTYPER register  ****************/
3288 #define GPIO_OTYPER_OT0_Pos            (0U)
3289 #define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)           /*!< 0x00000001 */
3290 #define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
3291 #define GPIO_OTYPER_OT1_Pos            (1U)
3292 #define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)           /*!< 0x00000002 */
3293 #define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
3294 #define GPIO_OTYPER_OT2_Pos            (2U)
3295 #define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)           /*!< 0x00000004 */
3296 #define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
3297 #define GPIO_OTYPER_OT3_Pos            (3U)
3298 #define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)           /*!< 0x00000008 */
3299 #define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
3300 #define GPIO_OTYPER_OT4_Pos            (4U)
3301 #define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)           /*!< 0x00000010 */
3302 #define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
3303 #define GPIO_OTYPER_OT5_Pos            (5U)
3304 #define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)           /*!< 0x00000020 */
3305 #define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
3306 #define GPIO_OTYPER_OT6_Pos            (6U)
3307 #define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)           /*!< 0x00000040 */
3308 #define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
3309 #define GPIO_OTYPER_OT7_Pos            (7U)
3310 #define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)           /*!< 0x00000080 */
3311 #define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
3312 #define GPIO_OTYPER_OT8_Pos            (8U)
3313 #define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)           /*!< 0x00000100 */
3314 #define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
3315 #define GPIO_OTYPER_OT9_Pos            (9U)
3316 #define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)           /*!< 0x00000200 */
3317 #define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
3318 #define GPIO_OTYPER_OT10_Pos           (10U)
3319 #define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)          /*!< 0x00000400 */
3320 #define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
3321 #define GPIO_OTYPER_OT11_Pos           (11U)
3322 #define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)          /*!< 0x00000800 */
3323 #define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
3324 #define GPIO_OTYPER_OT12_Pos           (12U)
3325 #define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)          /*!< 0x00001000 */
3326 #define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
3327 #define GPIO_OTYPER_OT13_Pos           (13U)
3328 #define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)          /*!< 0x00002000 */
3329 #define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
3330 #define GPIO_OTYPER_OT14_Pos           (14U)
3331 #define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)          /*!< 0x00004000 */
3332 #define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
3333 #define GPIO_OTYPER_OT15_Pos           (15U)
3334 #define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)          /*!< 0x00008000 */
3335 #define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
3336 
3337 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3338 #define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
3339 #define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000003 */
3340 #define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
3341 #define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
3342 #define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
3343 #define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
3344 #define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x0000000C */
3345 #define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
3346 #define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
3347 #define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
3348 #define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
3349 #define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000030 */
3350 #define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
3351 #define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
3352 #define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
3353 #define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
3354 #define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x000000C0 */
3355 #define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
3356 #define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
3357 #define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
3358 #define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
3359 #define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000300 */
3360 #define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
3361 #define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
3362 #define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
3363 #define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
3364 #define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000C00 */
3365 #define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
3366 #define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
3367 #define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
3368 #define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
3369 #define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00003000 */
3370 #define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
3371 #define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
3372 #define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
3373 #define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
3374 #define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x0000C000 */
3375 #define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
3376 #define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
3377 #define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
3378 #define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
3379 #define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00030000 */
3380 #define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
3381 #define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
3382 #define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
3383 #define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
3384 #define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x000C0000 */
3385 #define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
3386 #define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
3387 #define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
3388 #define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
3389 #define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00300000 */
3390 #define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
3391 #define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
3392 #define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
3393 #define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
3394 #define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00C00000 */
3395 #define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
3396 #define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
3397 #define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
3398 #define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
3399 #define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x03000000 */
3400 #define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
3401 #define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
3402 #define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
3403 #define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
3404 #define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x0C000000 */
3405 #define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
3406 #define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
3407 #define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
3408 #define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
3409 #define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x30000000 */
3410 #define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
3411 #define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
3412 #define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
3413 #define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
3414 #define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0xC0000000 */
3415 #define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
3416 #define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
3417 #define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
3418 
3419 /******************  Bits definition for GPIO_PUPDR register  *****************/
3420 #define GPIO_PUPDR_PUPD0_Pos           (0U)
3421 #define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000003 */
3422 #define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
3423 #define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
3424 #define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
3425 #define GPIO_PUPDR_PUPD1_Pos           (2U)
3426 #define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x0000000C */
3427 #define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
3428 #define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
3429 #define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
3430 #define GPIO_PUPDR_PUPD2_Pos           (4U)
3431 #define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000030 */
3432 #define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
3433 #define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
3434 #define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
3435 #define GPIO_PUPDR_PUPD3_Pos           (6U)
3436 #define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x000000C0 */
3437 #define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
3438 #define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
3439 #define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
3440 #define GPIO_PUPDR_PUPD4_Pos           (8U)
3441 #define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000300 */
3442 #define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
3443 #define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
3444 #define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
3445 #define GPIO_PUPDR_PUPD5_Pos           (10U)
3446 #define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000C00 */
3447 #define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
3448 #define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
3449 #define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
3450 #define GPIO_PUPDR_PUPD6_Pos           (12U)
3451 #define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00003000 */
3452 #define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
3453 #define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
3454 #define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
3455 #define GPIO_PUPDR_PUPD7_Pos           (14U)
3456 #define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x0000C000 */
3457 #define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
3458 #define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
3459 #define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
3460 #define GPIO_PUPDR_PUPD8_Pos           (16U)
3461 #define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00030000 */
3462 #define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
3463 #define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
3464 #define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
3465 #define GPIO_PUPDR_PUPD9_Pos           (18U)
3466 #define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x000C0000 */
3467 #define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
3468 #define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
3469 #define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
3470 #define GPIO_PUPDR_PUPD10_Pos          (20U)
3471 #define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00300000 */
3472 #define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
3473 #define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
3474 #define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
3475 #define GPIO_PUPDR_PUPD11_Pos          (22U)
3476 #define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00C00000 */
3477 #define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
3478 #define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
3479 #define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
3480 #define GPIO_PUPDR_PUPD12_Pos          (24U)
3481 #define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x03000000 */
3482 #define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
3483 #define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
3484 #define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
3485 #define GPIO_PUPDR_PUPD13_Pos          (26U)
3486 #define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x0C000000 */
3487 #define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
3488 #define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
3489 #define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
3490 #define GPIO_PUPDR_PUPD14_Pos          (28U)
3491 #define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x30000000 */
3492 #define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
3493 #define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
3494 #define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
3495 #define GPIO_PUPDR_PUPD15_Pos          (30U)
3496 #define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0xC0000000 */
3497 #define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
3498 #define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
3499 #define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
3500 
3501 /******************  Bits definition for GPIO_IDR register  *******************/
3502 #define GPIO_IDR_ID0_Pos               (0U)
3503 #define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)              /*!< 0x00000001 */
3504 #define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
3505 #define GPIO_IDR_ID1_Pos               (1U)
3506 #define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)              /*!< 0x00000002 */
3507 #define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
3508 #define GPIO_IDR_ID2_Pos               (2U)
3509 #define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)              /*!< 0x00000004 */
3510 #define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
3511 #define GPIO_IDR_ID3_Pos               (3U)
3512 #define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)              /*!< 0x00000008 */
3513 #define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
3514 #define GPIO_IDR_ID4_Pos               (4U)
3515 #define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)              /*!< 0x00000010 */
3516 #define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
3517 #define GPIO_IDR_ID5_Pos               (5U)
3518 #define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)              /*!< 0x00000020 */
3519 #define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
3520 #define GPIO_IDR_ID6_Pos               (6U)
3521 #define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)              /*!< 0x00000040 */
3522 #define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
3523 #define GPIO_IDR_ID7_Pos               (7U)
3524 #define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)              /*!< 0x00000080 */
3525 #define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
3526 #define GPIO_IDR_ID8_Pos               (8U)
3527 #define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)              /*!< 0x00000100 */
3528 #define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
3529 #define GPIO_IDR_ID9_Pos               (9U)
3530 #define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)              /*!< 0x00000200 */
3531 #define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
3532 #define GPIO_IDR_ID10_Pos              (10U)
3533 #define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)             /*!< 0x00000400 */
3534 #define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
3535 #define GPIO_IDR_ID11_Pos              (11U)
3536 #define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)             /*!< 0x00000800 */
3537 #define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
3538 #define GPIO_IDR_ID12_Pos              (12U)
3539 #define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)             /*!< 0x00001000 */
3540 #define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
3541 #define GPIO_IDR_ID13_Pos              (13U)
3542 #define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)             /*!< 0x00002000 */
3543 #define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
3544 #define GPIO_IDR_ID14_Pos              (14U)
3545 #define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)             /*!< 0x00004000 */
3546 #define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
3547 #define GPIO_IDR_ID15_Pos              (15U)
3548 #define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)             /*!< 0x00008000 */
3549 #define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
3550 
3551 /******************  Bits definition for GPIO_ODR register  *******************/
3552 #define GPIO_ODR_OD0_Pos               (0U)
3553 #define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)              /*!< 0x00000001 */
3554 #define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
3555 #define GPIO_ODR_OD1_Pos               (1U)
3556 #define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)              /*!< 0x00000002 */
3557 #define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
3558 #define GPIO_ODR_OD2_Pos               (2U)
3559 #define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)              /*!< 0x00000004 */
3560 #define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
3561 #define GPIO_ODR_OD3_Pos               (3U)
3562 #define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)              /*!< 0x00000008 */
3563 #define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
3564 #define GPIO_ODR_OD4_Pos               (4U)
3565 #define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)              /*!< 0x00000010 */
3566 #define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
3567 #define GPIO_ODR_OD5_Pos               (5U)
3568 #define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)              /*!< 0x00000020 */
3569 #define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
3570 #define GPIO_ODR_OD6_Pos               (6U)
3571 #define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)              /*!< 0x00000040 */
3572 #define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
3573 #define GPIO_ODR_OD7_Pos               (7U)
3574 #define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)              /*!< 0x00000080 */
3575 #define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
3576 #define GPIO_ODR_OD8_Pos               (8U)
3577 #define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)              /*!< 0x00000100 */
3578 #define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
3579 #define GPIO_ODR_OD9_Pos               (9U)
3580 #define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)              /*!< 0x00000200 */
3581 #define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
3582 #define GPIO_ODR_OD10_Pos              (10U)
3583 #define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)             /*!< 0x00000400 */
3584 #define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
3585 #define GPIO_ODR_OD11_Pos              (11U)
3586 #define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)             /*!< 0x00000800 */
3587 #define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
3588 #define GPIO_ODR_OD12_Pos              (12U)
3589 #define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)             /*!< 0x00001000 */
3590 #define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
3591 #define GPIO_ODR_OD13_Pos              (13U)
3592 #define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)             /*!< 0x00002000 */
3593 #define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
3594 #define GPIO_ODR_OD14_Pos              (14U)
3595 #define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)             /*!< 0x00004000 */
3596 #define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
3597 #define GPIO_ODR_OD15_Pos              (15U)
3598 #define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)             /*!< 0x00008000 */
3599 #define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
3600 
3601 /******************  Bits definition for GPIO_BSRR register  ******************/
3602 #define GPIO_BSRR_BS0_Pos              (0U)
3603 #define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)             /*!< 0x00000001 */
3604 #define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
3605 #define GPIO_BSRR_BS1_Pos              (1U)
3606 #define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)             /*!< 0x00000002 */
3607 #define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
3608 #define GPIO_BSRR_BS2_Pos              (2U)
3609 #define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)             /*!< 0x00000004 */
3610 #define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
3611 #define GPIO_BSRR_BS3_Pos              (3U)
3612 #define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)             /*!< 0x00000008 */
3613 #define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
3614 #define GPIO_BSRR_BS4_Pos              (4U)
3615 #define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)             /*!< 0x00000010 */
3616 #define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
3617 #define GPIO_BSRR_BS5_Pos              (5U)
3618 #define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)             /*!< 0x00000020 */
3619 #define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
3620 #define GPIO_BSRR_BS6_Pos              (6U)
3621 #define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)             /*!< 0x00000040 */
3622 #define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
3623 #define GPIO_BSRR_BS7_Pos              (7U)
3624 #define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)             /*!< 0x00000080 */
3625 #define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
3626 #define GPIO_BSRR_BS8_Pos              (8U)
3627 #define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)             /*!< 0x00000100 */
3628 #define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
3629 #define GPIO_BSRR_BS9_Pos              (9U)
3630 #define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)             /*!< 0x00000200 */
3631 #define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
3632 #define GPIO_BSRR_BS10_Pos             (10U)
3633 #define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)            /*!< 0x00000400 */
3634 #define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
3635 #define GPIO_BSRR_BS11_Pos             (11U)
3636 #define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)            /*!< 0x00000800 */
3637 #define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
3638 #define GPIO_BSRR_BS12_Pos             (12U)
3639 #define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)            /*!< 0x00001000 */
3640 #define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
3641 #define GPIO_BSRR_BS13_Pos             (13U)
3642 #define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)            /*!< 0x00002000 */
3643 #define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
3644 #define GPIO_BSRR_BS14_Pos             (14U)
3645 #define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)            /*!< 0x00004000 */
3646 #define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
3647 #define GPIO_BSRR_BS15_Pos             (15U)
3648 #define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)            /*!< 0x00008000 */
3649 #define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
3650 #define GPIO_BSRR_BR0_Pos              (16U)
3651 #define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)             /*!< 0x00010000 */
3652 #define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
3653 #define GPIO_BSRR_BR1_Pos              (17U)
3654 #define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)             /*!< 0x00020000 */
3655 #define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
3656 #define GPIO_BSRR_BR2_Pos              (18U)
3657 #define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)             /*!< 0x00040000 */
3658 #define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
3659 #define GPIO_BSRR_BR3_Pos              (19U)
3660 #define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)             /*!< 0x00080000 */
3661 #define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
3662 #define GPIO_BSRR_BR4_Pos              (20U)
3663 #define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)             /*!< 0x00100000 */
3664 #define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
3665 #define GPIO_BSRR_BR5_Pos              (21U)
3666 #define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)             /*!< 0x00200000 */
3667 #define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
3668 #define GPIO_BSRR_BR6_Pos              (22U)
3669 #define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)             /*!< 0x00400000 */
3670 #define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
3671 #define GPIO_BSRR_BR7_Pos              (23U)
3672 #define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)             /*!< 0x00800000 */
3673 #define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
3674 #define GPIO_BSRR_BR8_Pos              (24U)
3675 #define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)             /*!< 0x01000000 */
3676 #define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
3677 #define GPIO_BSRR_BR9_Pos              (25U)
3678 #define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)             /*!< 0x02000000 */
3679 #define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
3680 #define GPIO_BSRR_BR10_Pos             (26U)
3681 #define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)            /*!< 0x04000000 */
3682 #define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
3683 #define GPIO_BSRR_BR11_Pos             (27U)
3684 #define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)            /*!< 0x08000000 */
3685 #define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
3686 #define GPIO_BSRR_BR12_Pos             (28U)
3687 #define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)            /*!< 0x10000000 */
3688 #define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
3689 #define GPIO_BSRR_BR13_Pos             (29U)
3690 #define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)            /*!< 0x20000000 */
3691 #define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
3692 #define GPIO_BSRR_BR14_Pos             (30U)
3693 #define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)            /*!< 0x40000000 */
3694 #define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
3695 #define GPIO_BSRR_BR15_Pos             (31U)
3696 #define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)            /*!< 0x80000000 */
3697 #define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
3698 
3699 /****************** Bit definition for GPIO_LCKR register *********************/
3700 #define GPIO_LCKR_LCK0_Pos             (0U)
3701 #define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)            /*!< 0x00000001 */
3702 #define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
3703 #define GPIO_LCKR_LCK1_Pos             (1U)
3704 #define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)            /*!< 0x00000002 */
3705 #define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
3706 #define GPIO_LCKR_LCK2_Pos             (2U)
3707 #define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)            /*!< 0x00000004 */
3708 #define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
3709 #define GPIO_LCKR_LCK3_Pos             (3U)
3710 #define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)            /*!< 0x00000008 */
3711 #define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
3712 #define GPIO_LCKR_LCK4_Pos             (4U)
3713 #define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)            /*!< 0x00000010 */
3714 #define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
3715 #define GPIO_LCKR_LCK5_Pos             (5U)
3716 #define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)            /*!< 0x00000020 */
3717 #define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
3718 #define GPIO_LCKR_LCK6_Pos             (6U)
3719 #define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)            /*!< 0x00000040 */
3720 #define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
3721 #define GPIO_LCKR_LCK7_Pos             (7U)
3722 #define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)            /*!< 0x00000080 */
3723 #define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
3724 #define GPIO_LCKR_LCK8_Pos             (8U)
3725 #define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)            /*!< 0x00000100 */
3726 #define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
3727 #define GPIO_LCKR_LCK9_Pos             (9U)
3728 #define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)            /*!< 0x00000200 */
3729 #define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
3730 #define GPIO_LCKR_LCK10_Pos            (10U)
3731 #define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)           /*!< 0x00000400 */
3732 #define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
3733 #define GPIO_LCKR_LCK11_Pos            (11U)
3734 #define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)           /*!< 0x00000800 */
3735 #define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
3736 #define GPIO_LCKR_LCK12_Pos            (12U)
3737 #define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)           /*!< 0x00001000 */
3738 #define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
3739 #define GPIO_LCKR_LCK13_Pos            (13U)
3740 #define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)           /*!< 0x00002000 */
3741 #define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
3742 #define GPIO_LCKR_LCK14_Pos            (14U)
3743 #define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)           /*!< 0x00004000 */
3744 #define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
3745 #define GPIO_LCKR_LCK15_Pos            (15U)
3746 #define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)           /*!< 0x00008000 */
3747 #define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
3748 #define GPIO_LCKR_LCKK_Pos             (16U)
3749 #define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)            /*!< 0x00010000 */
3750 #define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
3751 
3752 /****************** Bit definition for GPIO_AFRL register *********************/
3753 #define GPIO_AFRL_AFSEL0_Pos           (0U)
3754 #define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x0000000F */
3755 #define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
3756 #define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
3757 #define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
3758 #define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
3759 #define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
3760 #define GPIO_AFRL_AFSEL1_Pos           (4U)
3761 #define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x000000F0 */
3762 #define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
3763 #define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
3764 #define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
3765 #define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
3766 #define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
3767 #define GPIO_AFRL_AFSEL2_Pos           (8U)
3768 #define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000F00 */
3769 #define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
3770 #define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
3771 #define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
3772 #define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
3773 #define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
3774 #define GPIO_AFRL_AFSEL3_Pos           (12U)
3775 #define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x0000F000 */
3776 #define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
3777 #define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
3778 #define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
3779 #define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
3780 #define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
3781 #define GPIO_AFRL_AFSEL4_Pos           (16U)
3782 #define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x000F0000 */
3783 #define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
3784 #define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
3785 #define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
3786 #define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
3787 #define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
3788 #define GPIO_AFRL_AFSEL5_Pos           (20U)
3789 #define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00F00000 */
3790 #define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
3791 #define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
3792 #define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
3793 #define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
3794 #define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
3795 #define GPIO_AFRL_AFSEL6_Pos           (24U)
3796 #define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x0F000000 */
3797 #define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
3798 #define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
3799 #define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
3800 #define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
3801 #define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
3802 #define GPIO_AFRL_AFSEL7_Pos           (28U)
3803 #define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0xF0000000 */
3804 #define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
3805 #define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
3806 #define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
3807 #define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
3808 #define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
3809 
3810 /****************** Bit definition for GPIO_AFRH register *********************/
3811 #define GPIO_AFRH_AFSEL8_Pos           (0U)
3812 #define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x0000000F */
3813 #define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
3814 #define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
3815 #define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
3816 #define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
3817 #define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
3818 #define GPIO_AFRH_AFSEL9_Pos           (4U)
3819 #define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x000000F0 */
3820 #define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
3821 #define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
3822 #define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
3823 #define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
3824 #define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
3825 #define GPIO_AFRH_AFSEL10_Pos          (8U)
3826 #define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000F00 */
3827 #define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
3828 #define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
3829 #define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
3830 #define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
3831 #define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
3832 #define GPIO_AFRH_AFSEL11_Pos          (12U)
3833 #define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x0000F000 */
3834 #define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
3835 #define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
3836 #define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
3837 #define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
3838 #define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
3839 #define GPIO_AFRH_AFSEL12_Pos          (16U)
3840 #define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x000F0000 */
3841 #define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
3842 #define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
3843 #define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
3844 #define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
3845 #define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
3846 #define GPIO_AFRH_AFSEL13_Pos          (20U)
3847 #define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00F00000 */
3848 #define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
3849 #define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
3850 #define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
3851 #define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
3852 #define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
3853 #define GPIO_AFRH_AFSEL14_Pos          (24U)
3854 #define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x0F000000 */
3855 #define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
3856 #define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
3857 #define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
3858 #define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
3859 #define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
3860 #define GPIO_AFRH_AFSEL15_Pos          (28U)
3861 #define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0xF0000000 */
3862 #define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
3863 #define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
3864 #define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
3865 #define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
3866 #define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
3867 
3868 /******************  Bits definition for GPIO_BRR register  ******************/
3869 #define GPIO_BRR_BR0_Pos               (0U)
3870 #define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)              /*!< 0x00000001 */
3871 #define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
3872 #define GPIO_BRR_BR1_Pos               (1U)
3873 #define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)              /*!< 0x00000002 */
3874 #define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
3875 #define GPIO_BRR_BR2_Pos               (2U)
3876 #define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)              /*!< 0x00000004 */
3877 #define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
3878 #define GPIO_BRR_BR3_Pos               (3U)
3879 #define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)              /*!< 0x00000008 */
3880 #define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
3881 #define GPIO_BRR_BR4_Pos               (4U)
3882 #define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)              /*!< 0x00000010 */
3883 #define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
3884 #define GPIO_BRR_BR5_Pos               (5U)
3885 #define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)              /*!< 0x00000020 */
3886 #define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
3887 #define GPIO_BRR_BR6_Pos               (6U)
3888 #define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)              /*!< 0x00000040 */
3889 #define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
3890 #define GPIO_BRR_BR7_Pos               (7U)
3891 #define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)              /*!< 0x00000080 */
3892 #define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
3893 #define GPIO_BRR_BR8_Pos               (8U)
3894 #define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)              /*!< 0x00000100 */
3895 #define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
3896 #define GPIO_BRR_BR9_Pos               (9U)
3897 #define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)              /*!< 0x00000200 */
3898 #define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
3899 #define GPIO_BRR_BR10_Pos              (10U)
3900 #define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)             /*!< 0x00000400 */
3901 #define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
3902 #define GPIO_BRR_BR11_Pos              (11U)
3903 #define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)             /*!< 0x00000800 */
3904 #define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
3905 #define GPIO_BRR_BR12_Pos              (12U)
3906 #define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)             /*!< 0x00001000 */
3907 #define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
3908 #define GPIO_BRR_BR13_Pos              (13U)
3909 #define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)             /*!< 0x00002000 */
3910 #define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
3911 #define GPIO_BRR_BR14_Pos              (14U)
3912 #define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)             /*!< 0x00004000 */
3913 #define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
3914 #define GPIO_BRR_BR15_Pos              (15U)
3915 #define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)             /*!< 0x00008000 */
3916 #define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
3917 
3918 
3919 /******************************************************************************/
3920 /*                                                                            */
3921 /*                      Inter-integrated Circuit Interface (I2C)              */
3922 /*                                                                            */
3923 /******************************************************************************/
3924 /*******************  Bit definition for I2C_CR1 register  *******************/
3925 #define I2C_CR1_PE_Pos               (0U)
3926 #define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
3927 #define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
3928 #define I2C_CR1_TXIE_Pos             (1U)
3929 #define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
3930 #define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
3931 #define I2C_CR1_RXIE_Pos             (2U)
3932 #define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
3933 #define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
3934 #define I2C_CR1_ADDRIE_Pos           (3U)
3935 #define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
3936 #define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
3937 #define I2C_CR1_NACKIE_Pos           (4U)
3938 #define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
3939 #define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
3940 #define I2C_CR1_STOPIE_Pos           (5U)
3941 #define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
3942 #define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
3943 #define I2C_CR1_TCIE_Pos             (6U)
3944 #define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
3945 #define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
3946 #define I2C_CR1_ERRIE_Pos            (7U)
3947 #define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
3948 #define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
3949 #define I2C_CR1_DNF_Pos              (8U)
3950 #define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
3951 #define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
3952 #define I2C_CR1_ANFOFF_Pos           (12U)
3953 #define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
3954 #define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
3955 #define I2C_CR1_SWRST_Pos            (13U)
3956 #define I2C_CR1_SWRST_Msk            (0x1UL << I2C_CR1_SWRST_Pos)              /*!< 0x00002000 */
3957 #define I2C_CR1_SWRST                I2C_CR1_SWRST_Msk                         /*!< Software reset */
3958 #define I2C_CR1_TXDMAEN_Pos          (14U)
3959 #define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
3960 #define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
3961 #define I2C_CR1_RXDMAEN_Pos          (15U)
3962 #define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
3963 #define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
3964 #define I2C_CR1_SBC_Pos              (16U)
3965 #define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
3966 #define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
3967 #define I2C_CR1_NOSTRETCH_Pos        (17U)
3968 #define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
3969 #define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
3970 #define I2C_CR1_WUPEN_Pos            (18U)
3971 #define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
3972 #define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
3973 #define I2C_CR1_GCEN_Pos             (19U)
3974 #define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
3975 #define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
3976 #define I2C_CR1_SMBHEN_Pos           (20U)
3977 #define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
3978 #define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
3979 #define I2C_CR1_SMBDEN_Pos           (21U)
3980 #define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
3981 #define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
3982 #define I2C_CR1_ALERTEN_Pos          (22U)
3983 #define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
3984 #define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
3985 #define I2C_CR1_PECEN_Pos            (23U)
3986 #define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
3987 #define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
3988 
3989 /******************  Bit definition for I2C_CR2 register  ********************/
3990 #define I2C_CR2_SADD_Pos             (0U)
3991 #define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
3992 #define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
3993 #define I2C_CR2_RD_WRN_Pos           (10U)
3994 #define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
3995 #define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
3996 #define I2C_CR2_ADD10_Pos            (11U)
3997 #define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
3998 #define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
3999 #define I2C_CR2_HEAD10R_Pos          (12U)
4000 #define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
4001 #define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
4002 #define I2C_CR2_START_Pos            (13U)
4003 #define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
4004 #define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
4005 #define I2C_CR2_STOP_Pos             (14U)
4006 #define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
4007 #define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
4008 #define I2C_CR2_NACK_Pos             (15U)
4009 #define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
4010 #define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
4011 #define I2C_CR2_NBYTES_Pos           (16U)
4012 #define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
4013 #define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
4014 #define I2C_CR2_RELOAD_Pos           (24U)
4015 #define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
4016 #define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
4017 #define I2C_CR2_AUTOEND_Pos          (25U)
4018 #define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
4019 #define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
4020 #define I2C_CR2_PECBYTE_Pos          (26U)
4021 #define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
4022 #define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
4023 
4024 /*******************  Bit definition for I2C_OAR1 register  ******************/
4025 #define I2C_OAR1_OA1_Pos             (0U)
4026 #define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
4027 #define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
4028 #define I2C_OAR1_OA1MODE_Pos         (10U)
4029 #define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
4030 #define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
4031 #define I2C_OAR1_OA1EN_Pos           (15U)
4032 #define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
4033 #define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
4034 
4035 /*******************  Bit definition for I2C_OAR2 register  ******************/
4036 #define I2C_OAR2_OA2_Pos             (1U)
4037 #define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
4038 #define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
4039 #define I2C_OAR2_OA2MSK_Pos          (8U)
4040 #define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
4041 #define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
4042 #define I2C_OAR2_OA2NOMASK           (0U)                                      /*!< No mask                                        */
4043 #define I2C_OAR2_OA2MASK01_Pos       (8U)
4044 #define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
4045 #define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
4046 #define I2C_OAR2_OA2MASK02_Pos       (9U)
4047 #define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
4048 #define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
4049 #define I2C_OAR2_OA2MASK03_Pos       (8U)
4050 #define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
4051 #define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
4052 #define I2C_OAR2_OA2MASK04_Pos       (10U)
4053 #define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
4054 #define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
4055 #define I2C_OAR2_OA2MASK05_Pos       (8U)
4056 #define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
4057 #define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
4058 #define I2C_OAR2_OA2MASK06_Pos       (9U)
4059 #define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
4060 #define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
4061 #define I2C_OAR2_OA2MASK07_Pos       (8U)
4062 #define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
4063 #define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
4064 #define I2C_OAR2_OA2EN_Pos           (15U)
4065 #define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
4066 #define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
4067 
4068 /*******************  Bit definition for I2C_TIMINGR register *******************/
4069 #define I2C_TIMINGR_SCLL_Pos         (0U)
4070 #define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
4071 #define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
4072 #define I2C_TIMINGR_SCLH_Pos         (8U)
4073 #define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
4074 #define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
4075 #define I2C_TIMINGR_SDADEL_Pos       (16U)
4076 #define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
4077 #define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
4078 #define I2C_TIMINGR_SCLDEL_Pos       (20U)
4079 #define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
4080 #define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
4081 #define I2C_TIMINGR_PRESC_Pos        (28U)
4082 #define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
4083 #define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
4084 
4085 /******************* Bit definition for I2C_TIMEOUTR register *******************/
4086 #define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
4087 #define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
4088 #define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
4089 #define I2C_TIMEOUTR_TIDLE_Pos       (12U)
4090 #define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
4091 #define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
4092 #define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
4093 #define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
4094 #define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
4095 #define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
4096 #define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
4097 #define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
4098 #define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
4099 #define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
4100 #define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
4101 
4102 /******************  Bit definition for I2C_ISR register  *********************/
4103 #define I2C_ISR_TXE_Pos              (0U)
4104 #define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
4105 #define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
4106 #define I2C_ISR_TXIS_Pos             (1U)
4107 #define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
4108 #define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
4109 #define I2C_ISR_RXNE_Pos             (2U)
4110 #define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
4111 #define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
4112 #define I2C_ISR_ADDR_Pos             (3U)
4113 #define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
4114 #define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
4115 #define I2C_ISR_NACKF_Pos            (4U)
4116 #define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
4117 #define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
4118 #define I2C_ISR_STOPF_Pos            (5U)
4119 #define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
4120 #define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
4121 #define I2C_ISR_TC_Pos               (6U)
4122 #define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
4123 #define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
4124 #define I2C_ISR_TCR_Pos              (7U)
4125 #define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
4126 #define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
4127 #define I2C_ISR_BERR_Pos             (8U)
4128 #define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
4129 #define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
4130 #define I2C_ISR_ARLO_Pos             (9U)
4131 #define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
4132 #define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
4133 #define I2C_ISR_OVR_Pos              (10U)
4134 #define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
4135 #define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
4136 #define I2C_ISR_PECERR_Pos           (11U)
4137 #define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
4138 #define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
4139 #define I2C_ISR_TIMEOUT_Pos          (12U)
4140 #define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
4141 #define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
4142 #define I2C_ISR_ALERT_Pos            (13U)
4143 #define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
4144 #define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
4145 #define I2C_ISR_BUSY_Pos             (15U)
4146 #define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
4147 #define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
4148 #define I2C_ISR_DIR_Pos              (16U)
4149 #define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
4150 #define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
4151 #define I2C_ISR_ADDCODE_Pos          (17U)
4152 #define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
4153 #define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
4154 
4155 /******************  Bit definition for I2C_ICR register  *********************/
4156 #define I2C_ICR_ADDRCF_Pos           (3U)
4157 #define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
4158 #define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
4159 #define I2C_ICR_NACKCF_Pos           (4U)
4160 #define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
4161 #define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
4162 #define I2C_ICR_STOPCF_Pos           (5U)
4163 #define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
4164 #define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
4165 #define I2C_ICR_BERRCF_Pos           (8U)
4166 #define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
4167 #define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
4168 #define I2C_ICR_ARLOCF_Pos           (9U)
4169 #define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
4170 #define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
4171 #define I2C_ICR_OVRCF_Pos            (10U)
4172 #define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
4173 #define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
4174 #define I2C_ICR_PECCF_Pos            (11U)
4175 #define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
4176 #define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
4177 #define I2C_ICR_TIMOUTCF_Pos         (12U)
4178 #define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
4179 #define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
4180 #define I2C_ICR_ALERTCF_Pos          (13U)
4181 #define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
4182 #define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
4183 
4184 /******************  Bit definition for I2C_PECR register  *********************/
4185 #define I2C_PECR_PEC_Pos             (0U)
4186 #define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
4187 #define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
4188 
4189 /******************  Bit definition for I2C_RXDR register  *********************/
4190 #define I2C_RXDR_RXDATA_Pos          (0U)
4191 #define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
4192 #define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
4193 
4194 /******************  Bit definition for I2C_TXDR register  *********************/
4195 #define I2C_TXDR_TXDATA_Pos          (0U)
4196 #define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
4197 #define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
4198 
4199 
4200 /******************************************************************************/
4201 /*                                                                            */
4202 /*                        Independent WATCHDOG (IWDG)                         */
4203 /*                                                                            */
4204 /******************************************************************************/
4205 /*******************  Bit definition for IWDG_KR register  ********************/
4206 #define IWDG_KR_KEY_Pos      (0U)
4207 #define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
4208 #define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
4209 
4210 /*******************  Bit definition for IWDG_PR register  ********************/
4211 #define IWDG_PR_PR_Pos       (0U)
4212 #define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
4213 #define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
4214 #define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
4215 #define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
4216 #define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
4217 
4218 /*******************  Bit definition for IWDG_RLR register  *******************/
4219 #define IWDG_RLR_RL_Pos      (0U)
4220 #define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
4221 #define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
4222 
4223 /*******************  Bit definition for IWDG_SR register  ********************/
4224 #define IWDG_SR_PVU_Pos      (0U)
4225 #define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
4226 #define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
4227 #define IWDG_SR_RVU_Pos      (1U)
4228 #define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
4229 #define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
4230 #define IWDG_SR_WVU_Pos      (2U)
4231 #define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
4232 #define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
4233 
4234 /*******************  Bit definition for IWDG_KR register  ********************/
4235 #define IWDG_WINR_WIN_Pos    (0U)
4236 #define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
4237 #define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
4238 
4239 
4240 /******************************************************************************/
4241 /*                                                                            */
4242 /*                        Power Control                                       */
4243 /*                                                                            */
4244 /******************************************************************************/
4245 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
4246 #define PWR_BOR_SUPPORT                       /*!< PWR feature available only on specific devices: Brown-Out Reset feature         */
4247 #define PWR_SHDW_SUPPORT                      /*!< PWR feature available only on specific devices: Shutdown mode */
4248 
4249 /********************  Bit definition for PWR_CR1 register  ********************/
4250 #define PWR_CR1_LPMS_Pos          (0U)
4251 #define PWR_CR1_LPMS_Msk          (0x7UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000007 */
4252 #define PWR_CR1_LPMS              PWR_CR1_LPMS_Msk                             /*!< Low Power Mode Selection */
4253 #define PWR_CR1_LPMS_0            (0x1UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000001 */
4254 #define PWR_CR1_LPMS_1            (0x2UL << PWR_CR1_LPMS_Pos)                  /*!< 0x00000002 */
4255 #define PWR_CR1_LPMS_2            (0x4UL << PWR_CR1_LPMS_Pos)                   /*!< 0x00000004 */
4256 #define PWR_CR1_FPD_STOP_Pos      (3U)
4257 #define PWR_CR1_FPD_STOP_Msk      (0x1UL << PWR_CR1_FPD_STOP_Pos)              /*!< 0x00000008 */
4258 #define PWR_CR1_FPD_STOP          PWR_CR1_FPD_STOP_Msk                         /*!< Flash power down mode during stop */
4259 #define PWR_CR1_FPD_LPRUN_Pos     (4U)
4260 #define PWR_CR1_FPD_LPRUN_Msk     (0x1UL << PWR_CR1_FPD_LPRUN_Pos)             /*!< 0x00000010 */
4261 #define PWR_CR1_FPD_LPRUN         PWR_CR1_FPD_LPRUN_Msk                        /*!< Flash power down mode during run */
4262 #define PWR_CR1_FPD_LPSLP_Pos     (5U)
4263 #define PWR_CR1_FPD_LPSLP_Msk     (0x1UL << PWR_CR1_FPD_LPSLP_Pos)             /*!< 0x00000020 */
4264 #define PWR_CR1_FPD_LPSLP         PWR_CR1_FPD_LPSLP_Msk                        /*!< Flash power down mode during sleep */
4265 #define PWR_CR1_DBP_Pos           (8U)
4266 #define PWR_CR1_DBP_Msk           (0x1UL << PWR_CR1_DBP_Pos)                   /*!< 0x00000100 */
4267 #define PWR_CR1_DBP               PWR_CR1_DBP_Msk                              /*!< Disable Backup Domain write protection */
4268 #define PWR_CR1_VOS_Pos           (9U)
4269 #define PWR_CR1_VOS_Msk           (0x3UL << PWR_CR1_VOS_Pos)                   /*!< 0x00000600 */
4270 #define PWR_CR1_VOS               PWR_CR1_VOS_Msk                              /*!< Voltage scaling */
4271 #define PWR_CR1_VOS_0             (0x1UL << PWR_CR1_VOS_Pos)                   /*!< Voltage scaling bit 0 */
4272 #define PWR_CR1_VOS_1             (0x2UL << PWR_CR1_VOS_Pos)                   /*!< Voltage scaling bit 1 */
4273 #define PWR_CR1_LPR_Pos           (14U)
4274 #define PWR_CR1_LPR_Msk           (0x1UL << PWR_CR1_LPR_Pos)                   /*!< 0x00004000 */
4275 #define PWR_CR1_LPR               PWR_CR1_LPR_Msk                              /*!< Regulator Low-Power Run mode */
4276 
4277 /********************  Bit definition for PWR_CR2 register  ********************/
4278 #define PWR_CR2_PVDE_Pos          (0U)
4279 #define PWR_CR2_PVDE_Msk          (0x1UL << PWR_CR2_PVDE_Pos)                  /*!< 0x00000001 */
4280 #define PWR_CR2_PVDE              PWR_CR2_PVDE_Msk                             /*!< Programmable Voltage Detector Enable */
4281 #define PWR_CR2_PVDFT_Pos         (1U)
4282 #define PWR_CR2_PVDFT_Msk         (0x7UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x0000000E */
4283 #define PWR_CR2_PVDFT             PWR_CR2_PVDFT_Msk                            /*!< PVD Falling Threshold Selection bit field */
4284 #define PWR_CR2_PVDFT_0           (0x1UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000002 */
4285 #define PWR_CR2_PVDFT_1           (0x2UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000004 */
4286 #define PWR_CR2_PVDFT_2           (0x4UL << PWR_CR2_PVDFT_Pos)                 /*!< 0x00000008 */
4287 #define PWR_CR2_PVDRT_Pos         (4U)
4288 #define PWR_CR2_PVDRT_Msk         (0x7UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000070 */
4289 #define PWR_CR2_PVDRT             PWR_CR2_PVDRT_Msk                            /*!< PVD Rising Threshold Selection bit field */
4290 #define PWR_CR2_PVDRT_0           (0x1UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000010 */
4291 #define PWR_CR2_PVDRT_1           (0x2UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000020 */
4292 #define PWR_CR2_PVDRT_2           (0x4UL << PWR_CR2_PVDRT_Pos)                 /*!< 0x00000040 */
4293 
4294 /********************  Bit definition for PWR_CR3 register  ********************/
4295 #define PWR_CR3_EWUP_Pos          (0U)
4296 #define PWR_CR3_EWUP_Msk          (0x3BUL << PWR_CR3_EWUP_Pos)                 /*!< 0x0000003B */
4297 #define PWR_CR3_EWUP              PWR_CR3_EWUP_Msk                             /*!< Enable all Wake-Up Pins  */
4298 #define PWR_CR3_EWUP1_Pos         (0U)
4299 #define PWR_CR3_EWUP1_Msk         (0x1UL << PWR_CR3_EWUP1_Pos)                 /*!< 0x00000001 */
4300 #define PWR_CR3_EWUP1             PWR_CR3_EWUP1_Msk                            /*!< Enable WKUP pin 1 */
4301 #define PWR_CR3_EWUP2_Pos         (1U)
4302 #define PWR_CR3_EWUP2_Msk         (0x1UL << PWR_CR3_EWUP2_Pos)                 /*!< 0x00000002 */
4303 #define PWR_CR3_EWUP2             PWR_CR3_EWUP2_Msk                            /*!< Enable WKUP pin 2 */
4304 #define PWR_CR3_EWUP4_Pos         (3U)
4305 #define PWR_CR3_EWUP4_Msk         (0x1UL << PWR_CR3_EWUP4_Pos)                 /*!< 0x00000008 */
4306 #define PWR_CR3_EWUP4             PWR_CR3_EWUP4_Msk                            /*!< Enable WKUP pin 4 */
4307 #define PWR_CR3_EWUP5_Pos         (4U)
4308 #define PWR_CR3_EWUP5_Msk         (0x1UL << PWR_CR3_EWUP5_Pos)                 /*!< 0x00000010 */
4309 #define PWR_CR3_EWUP5             PWR_CR3_EWUP5_Msk                            /*!< Enable WKUP pin 5 */
4310 #define PWR_CR3_EWUP6_Pos         (5U)
4311 #define PWR_CR3_EWUP6_Msk         (0x1UL << PWR_CR3_EWUP6_Pos)                 /*!< 0x00000020 */
4312 #define PWR_CR3_EWUP6             PWR_CR3_EWUP6_Msk                            /*!< Enable WKUP pin 6 */
4313 #define PWR_CR3_RRS_Pos           (8U)
4314 #define PWR_CR3_RRS_Msk           (0x1UL << PWR_CR3_RRS_Pos)                   /*!< 0x00000100 */
4315 #define PWR_CR3_RRS               PWR_CR3_RRS_Msk                              /*!< RAM retention in Standby mode */
4316 #define PWR_CR3_ENB_ULP_Pos       (9U)
4317 #define PWR_CR3_ENB_ULP_Msk       (0x1UL << PWR_CR3_ENB_ULP_Pos)               /*!< 0x00000200 */
4318 #define PWR_CR3_ENB_ULP           PWR_CR3_ENB_ULP_Msk                          /*!< Enable sampling resistor bridge in the LPMU_RESET block */
4319 #define PWR_CR3_APC_Pos           (10U)
4320 #define PWR_CR3_APC_Msk           (0x1UL << PWR_CR3_APC_Pos)                   /*!< 0x00000400 */
4321 #define PWR_CR3_APC               PWR_CR3_APC_Msk                              /*!< Apply pull-up and pull-down configuration */
4322 #define PWR_CR3_EIWUL_Pos         (15U)
4323 #define PWR_CR3_EIWUL_Msk         (0x1UL << PWR_CR3_EIWUL_Pos)                 /*!< 0x00008000 */
4324 #define PWR_CR3_EIWUL             PWR_CR3_EIWUL_Msk                            /*!< Enable Internal Wake-up line */
4325 
4326 /********************  Bit definition for PWR_CR4 register  ********************/
4327 #define PWR_CR4_WP_Pos            (0U)
4328 #define PWR_CR4_WP_Msk            (0x3BUL << PWR_CR4_WP_Pos)                   /*!< 0x0000003B */
4329 #define PWR_CR4_WP                PWR_CR4_WP_Msk                               /*!< all Wake-Up Pin polarity */
4330 #define PWR_CR4_WP1_Pos           (0U)
4331 #define PWR_CR4_WP1_Msk           (0x1UL << PWR_CR4_WP1_Pos)                   /*!< 0x00000001 */
4332 #define PWR_CR4_WP1               PWR_CR4_WP1_Msk                              /*!< Wake-Up Pin 1 polarity */
4333 #define PWR_CR4_WP2_Pos           (1U)
4334 #define PWR_CR4_WP2_Msk           (0x1UL << PWR_CR4_WP2_Pos)                   /*!< 0x00000002 */
4335 #define PWR_CR4_WP2               PWR_CR4_WP2_Msk                              /*!< Wake-Up Pin 2 polarity */
4336 #define PWR_CR4_WP4_Pos           (3U)
4337 #define PWR_CR4_WP4_Msk           (0x1UL << PWR_CR4_WP4_Pos)                   /*!< 0x00000008 */
4338 #define PWR_CR4_WP4               PWR_CR4_WP4_Msk                              /*!< Wake-Up Pin 4 polarity */
4339 #define PWR_CR4_WP5_Pos           (4U)
4340 #define PWR_CR4_WP5_Msk           (0x1UL << PWR_CR4_WP5_Pos)                   /*!< 0x00000010 */
4341 #define PWR_CR4_WP5               PWR_CR4_WP5_Msk                              /*!< Wake-Up Pin 5 polarity */
4342 #define PWR_CR4_WP6_Pos           (5U)
4343 #define PWR_CR4_WP6_Msk           (0x1UL << PWR_CR4_WP6_Pos)                   /*!< 0x00000020 */
4344 #define PWR_CR4_WP6               PWR_CR4_WP6_Msk                              /*!< Wake-Up Pin 6 polarity */
4345 #define PWR_CR4_VBE_Pos           (8U)
4346 #define PWR_CR4_VBE_Msk           (0x1UL << PWR_CR4_VBE_Pos)                   /*!< 0x00000100 */
4347 #define PWR_CR4_VBE               PWR_CR4_VBE_Msk                              /*!< VBAT Battery charging Enable  */
4348 #define PWR_CR4_VBRS_Pos          (9U)
4349 #define PWR_CR4_VBRS_Msk          (0x1UL << PWR_CR4_VBRS_Pos)                  /*!< 0x00000200 */
4350 #define PWR_CR4_VBRS              PWR_CR4_VBRS_Msk                             /*!< VBAT Battery charging Resistor Selection */
4351 
4352 /********************  Bit definition for PWR_SR1 register  ********************/
4353 #define PWR_SR1_WUF_Pos           (0U)
4354 #define PWR_SR1_WUF_Msk           (0x3BUL << PWR_SR1_WUF_Pos)                  /*!< 0x0000003B */
4355 #define PWR_SR1_WUF               PWR_SR1_WUF_Msk                              /*!< Wakeup Flags  */
4356 #define PWR_SR1_WUF1_Pos          (0U)
4357 #define PWR_SR1_WUF1_Msk          (0x1UL << PWR_SR1_WUF1_Pos)                  /*!< 0x00000001 */
4358 #define PWR_SR1_WUF1              PWR_SR1_WUF1_Msk                             /*!< Wakeup Flag 1 */
4359 #define PWR_SR1_WUF2_Pos          (1U)
4360 #define PWR_SR1_WUF2_Msk          (0x1UL << PWR_SR1_WUF2_Pos)                  /*!< 0x00000002 */
4361 #define PWR_SR1_WUF2              PWR_SR1_WUF2_Msk                             /*!< Wakeup Flag 2 */
4362 #define PWR_SR1_WUF4_Pos          (3U)
4363 #define PWR_SR1_WUF4_Msk          (0x1UL << PWR_SR1_WUF4_Pos)                  /*!< 0x00000008 */
4364 #define PWR_SR1_WUF4              PWR_SR1_WUF4_Msk                             /*!< Wakeup Flag 4 */
4365 #define PWR_SR1_WUF5_Pos          (4U)
4366 #define PWR_SR1_WUF5_Msk          (0x1UL << PWR_SR1_WUF5_Pos)                  /*!< 0x00000010 */
4367 #define PWR_SR1_WUF5              PWR_SR1_WUF5_Msk                             /*!< Wakeup Flag 5 */
4368 #define PWR_SR1_WUF6_Pos          (5U)
4369 #define PWR_SR1_WUF6_Msk          (0x1UL << PWR_SR1_WUF6_Pos)                  /*!< 0x00000020 */
4370 #define PWR_SR1_WUF6              PWR_SR1_WUF6_Msk                             /*!< Wakeup Flag 6 */
4371 #define PWR_SR1_SBF_Pos           (8U)
4372 #define PWR_SR1_SBF_Msk           (0x1UL << PWR_SR1_SBF_Pos)                   /*!< 0x00000100 */
4373 #define PWR_SR1_SBF               PWR_SR1_SBF_Msk                              /*!< Standby Flag  */
4374 #define PWR_SR1_WUFI_Pos          (15U)
4375 #define PWR_SR1_WUFI_Msk          (0x1UL << PWR_SR1_WUFI_Pos)                  /*!< 0x00008000 */
4376 #define PWR_SR1_WUFI              PWR_SR1_WUFI_Msk                             /*!< Wakeup Flag Internal */
4377 
4378 /********************  Bit definition for PWR_SR2 register  ********************/
4379 #define PWR_SR2_FLASH_RDY_Pos     (7U)
4380 #define PWR_SR2_FLASH_RDY_Msk     (0x1UL << PWR_SR2_FLASH_RDY_Pos)             /*!< 0x00000080 */
4381 #define PWR_SR2_FLASH_RDY         PWR_SR2_FLASH_RDY_Msk                        /*!< Flash Ready */
4382 #define PWR_SR2_REGLPS_Pos        (8U)
4383 #define PWR_SR2_REGLPS_Msk        (0x1UL << PWR_SR2_REGLPS_Pos)                /*!< 0x00000100 */
4384 #define PWR_SR2_REGLPS            PWR_SR2_REGLPS_Msk                           /*!< Regulator Low Power started */
4385 #define PWR_SR2_REGLPF_Pos        (9U)
4386 #define PWR_SR2_REGLPF_Msk        (0x1UL << PWR_SR2_REGLPF_Pos)                /*!< 0x00000200 */
4387 #define PWR_SR2_REGLPF            PWR_SR2_REGLPF_Msk                           /*!< Regulator Low Power flag    */
4388 #define PWR_SR2_VOSF_Pos          (10U)
4389 #define PWR_SR2_VOSF_Msk          (0x1UL << PWR_SR2_VOSF_Pos)                  /*!< 0x00000400 */
4390 #define PWR_SR2_VOSF              PWR_SR2_VOSF_Msk                             /*!< Voltage Scaling Flag */
4391 #define PWR_SR2_PVDO_Pos          (11U)
4392 #define PWR_SR2_PVDO_Msk          (0x1UL << PWR_SR2_PVDO_Pos)                  /*!< 0x00000800 */
4393 #define PWR_SR2_PVDO              PWR_SR2_PVDO_Msk                             /*!< Power voltage detector output */
4394 
4395 /********************  Bit definition for PWR_SCR register  ********************/
4396 #define PWR_SCR_CWUF_Pos          (0U)
4397 #define PWR_SCR_CWUF_Msk          (0x3BUL << PWR_SCR_CWUF_Pos)                 /*!< 0x0000003B */
4398 #define PWR_SCR_CWUF              PWR_SCR_CWUF_Msk                             /*!< Clear Wake-up Flags  */
4399 #define PWR_SCR_CWUF1_Pos         (0U)
4400 #define PWR_SCR_CWUF1_Msk         (0x1UL << PWR_SCR_CWUF1_Pos)                 /*!< 0x00000001 */
4401 #define PWR_SCR_CWUF1             PWR_SCR_CWUF1_Msk                            /*!< Clear Wake-up Flag 1 */
4402 #define PWR_SCR_CWUF2_Pos         (1U)
4403 #define PWR_SCR_CWUF2_Msk         (0x1UL << PWR_SCR_CWUF2_Pos)                 /*!< 0x00000002 */
4404 #define PWR_SCR_CWUF2             PWR_SCR_CWUF2_Msk                            /*!< Clear Wake-up Flag 2 */
4405 #define PWR_SCR_CWUF4_Pos         (3U)
4406 #define PWR_SCR_CWUF4_Msk         (0x1UL << PWR_SCR_CWUF4_Pos)                 /*!< 0x00000008 */
4407 #define PWR_SCR_CWUF4             PWR_SCR_CWUF4_Msk                            /*!< Clear Wake-up Flag 4 */
4408 #define PWR_SCR_CWUF5_Pos         (4U)
4409 #define PWR_SCR_CWUF5_Msk         (0x1UL << PWR_SCR_CWUF5_Pos)                 /*!< 0x00000010 */
4410 #define PWR_SCR_CWUF5             PWR_SCR_CWUF5_Msk                            /*!< Clear Wake-up Flag 5 */
4411 #define PWR_SCR_CWUF6_Pos         (5U)
4412 #define PWR_SCR_CWUF6_Msk         (0x1UL << PWR_SCR_CWUF6_Pos)                 /*!< 0x00000020 */
4413 #define PWR_SCR_CWUF6             PWR_SCR_CWUF6_Msk                            /*!< Clear Wake-up Flag 6 */
4414 #define PWR_SCR_CSBF_Pos          (8U)
4415 #define PWR_SCR_CSBF_Msk          (0x1UL << PWR_SCR_CSBF_Pos)                  /*!< 0x00000100 */
4416 #define PWR_SCR_CSBF              PWR_SCR_CSBF_Msk                             /*!< Clear Standby Flag  */
4417 
4418 /********************  Bit definition for PWR_PUCRA register  *****************/
4419 #define PWR_PUCRA_PU0_Pos         (0U)
4420 #define PWR_PUCRA_PU0_Msk         (0x1UL << PWR_PUCRA_PU0_Pos)                 /*!< 0x00000001 */
4421 #define PWR_PUCRA_PU0             PWR_PUCRA_PU0_Msk                            /*!< Pin PA0 Pull-Up set */
4422 #define PWR_PUCRA_PU1_Pos         (1U)
4423 #define PWR_PUCRA_PU1_Msk         (0x1UL << PWR_PUCRA_PU1_Pos)                 /*!< 0x00000002 */
4424 #define PWR_PUCRA_PU1             PWR_PUCRA_PU1_Msk                            /*!< Pin PA1 Pull-Up set */
4425 #define PWR_PUCRA_PU2_Pos         (2U)
4426 #define PWR_PUCRA_PU2_Msk         (0x1UL << PWR_PUCRA_PU2_Pos)                 /*!< 0x00000004 */
4427 #define PWR_PUCRA_PU2             PWR_PUCRA_PU2_Msk                            /*!< Pin PA2 Pull-Up set */
4428 #define PWR_PUCRA_PU3_Pos         (3U)
4429 #define PWR_PUCRA_PU3_Msk         (0x1UL << PWR_PUCRA_PU3_Pos)                 /*!< 0x00000008 */
4430 #define PWR_PUCRA_PU3             PWR_PUCRA_PU3_Msk                            /*!< Pin PA3 Pull-Up set */
4431 #define PWR_PUCRA_PU4_Pos         (4U)
4432 #define PWR_PUCRA_PU4_Msk         (0x1UL << PWR_PUCRA_PU4_Pos)                 /*!< 0x00000010 */
4433 #define PWR_PUCRA_PU4             PWR_PUCRA_PU4_Msk                            /*!< Pin PA4 Pull-Up set */
4434 #define PWR_PUCRA_PU5_Pos         (5U)
4435 #define PWR_PUCRA_PU5_Msk         (0x1UL << PWR_PUCRA_PU5_Pos)                 /*!< 0x00000020 */
4436 #define PWR_PUCRA_PU5             PWR_PUCRA_PU5_Msk                            /*!< Pin PA5 Pull-Up set */
4437 #define PWR_PUCRA_PU6_Pos         (6U)
4438 #define PWR_PUCRA_PU6_Msk         (0x1UL << PWR_PUCRA_PU6_Pos)                 /*!< 0x00000040 */
4439 #define PWR_PUCRA_PU6             PWR_PUCRA_PU6_Msk                            /*!< Pin PA6 Pull-Up set */
4440 #define PWR_PUCRA_PU7_Pos         (7U)
4441 #define PWR_PUCRA_PU7_Msk         (0x1UL << PWR_PUCRA_PU7_Pos)                 /*!< 0x00000080 */
4442 #define PWR_PUCRA_PU7             PWR_PUCRA_PU7_Msk                            /*!< Pin PA7 Pull-Up set */
4443 #define PWR_PUCRA_PU8_Pos         (8U)
4444 #define PWR_PUCRA_PU8_Msk         (0x1UL << PWR_PUCRA_PU8_Pos)                 /*!< 0x00000100 */
4445 #define PWR_PUCRA_PU8             PWR_PUCRA_PU8_Msk                            /*!< Pin PA8 Pull-Up set */
4446 #define PWR_PUCRA_PU9_Pos         (9U)
4447 #define PWR_PUCRA_PU9_Msk         (0x1UL << PWR_PUCRA_PU9_Pos)                 /*!< 0x00000200 */
4448 #define PWR_PUCRA_PU9             PWR_PUCRA_PU9_Msk                            /*!< Pin PA9 Pull-Up set */
4449 #define PWR_PUCRA_PU10_Pos        (10U)
4450 #define PWR_PUCRA_PU10_Msk        (0x1UL << PWR_PUCRA_PU10_Pos)                /*!< 0x00000400 */
4451 #define PWR_PUCRA_PU10            PWR_PUCRA_PU10_Msk                           /*!< Pin PA10 Pull-Up set */
4452 #define PWR_PUCRA_PU11_Pos        (11U)
4453 #define PWR_PUCRA_PU11_Msk        (0x1UL << PWR_PUCRA_PU11_Pos)                /*!< 0x00000800 */
4454 #define PWR_PUCRA_PU11            PWR_PUCRA_PU11_Msk                           /*!< Pin PA11 Pull-Up set */
4455 #define PWR_PUCRA_PU12_Pos        (12U)
4456 #define PWR_PUCRA_PU12_Msk        (0x1UL << PWR_PUCRA_PU12_Pos)                /*!< 0x00001000 */
4457 #define PWR_PUCRA_PU12            PWR_PUCRA_PU12_Msk                           /*!< Pin PA12 Pull-Up set */
4458 #define PWR_PUCRA_PU13_Pos        (13U)
4459 #define PWR_PUCRA_PU13_Msk        (0x1UL << PWR_PUCRA_PU13_Pos)                /*!< 0x00002000 */
4460 #define PWR_PUCRA_PU13            PWR_PUCRA_PU13_Msk                           /*!< Pin PA13 Pull-Up set */
4461 #define PWR_PUCRA_PU14_Pos        (14U)
4462 #define PWR_PUCRA_PU14_Msk        (0x1UL << PWR_PUCRA_PU14_Pos)                /*!< 0x00004000 */
4463 #define PWR_PUCRA_PU14            PWR_PUCRA_PU14_Msk                           /*!< Pin PA14 Pull-Up set */
4464 #define PWR_PUCRA_PU15_Pos        (15U)
4465 #define PWR_PUCRA_PU15_Msk        (0x1UL << PWR_PUCRA_PU15_Pos)                /*!< 0x00008000 */
4466 #define PWR_PUCRA_PU15            PWR_PUCRA_PU15_Msk                           /*!< Pin PA15 Pull-Up set */
4467 
4468 /********************  Bit definition for PWR_PDCRA register  *****************/
4469 #define PWR_PDCRA_PD0_Pos         (0U)
4470 #define PWR_PDCRA_PD0_Msk         (0x1UL << PWR_PDCRA_PD0_Pos)                 /*!< 0x00000001 */
4471 #define PWR_PDCRA_PD0             PWR_PDCRA_PD0_Msk                            /*!< Pin PA0 Pull-Down set */
4472 #define PWR_PDCRA_PD1_Pos         (1U)
4473 #define PWR_PDCRA_PD1_Msk         (0x1UL << PWR_PDCRA_PD1_Pos)                 /*!< 0x00000002 */
4474 #define PWR_PDCRA_PD1             PWR_PDCRA_PD1_Msk                            /*!< Pin PA1 Pull-Down set */
4475 #define PWR_PDCRA_PD2_Pos         (2U)
4476 #define PWR_PDCRA_PD2_Msk         (0x1UL << PWR_PDCRA_PD2_Pos)                 /*!< 0x00000004 */
4477 #define PWR_PDCRA_PD2             PWR_PDCRA_PD2_Msk                            /*!< Pin PA2 Pull-Down set */
4478 #define PWR_PDCRA_PD3_Pos         (3U)
4479 #define PWR_PDCRA_PD3_Msk         (0x1UL << PWR_PDCRA_PD3_Pos)                 /*!< 0x00000008 */
4480 #define PWR_PDCRA_PD3             PWR_PDCRA_PD3_Msk                            /*!< Pin PA3 Pull-Down set */
4481 #define PWR_PDCRA_PD4_Pos         (4U)
4482 #define PWR_PDCRA_PD4_Msk         (0x1UL << PWR_PDCRA_PD4_Pos)                 /*!< 0x00000010 */
4483 #define PWR_PDCRA_PD4             PWR_PDCRA_PD4_Msk                            /*!< Pin PA4 Pull-Down set */
4484 #define PWR_PDCRA_PD5_Pos         (5U)
4485 #define PWR_PDCRA_PD5_Msk         (0x1UL << PWR_PDCRA_PD5_Pos)                 /*!< 0x00000020 */
4486 #define PWR_PDCRA_PD5             PWR_PDCRA_PD5_Msk                            /*!< Pin PA5 Pull-Down set */
4487 #define PWR_PDCRA_PD6_Pos         (6U)
4488 #define PWR_PDCRA_PD6_Msk         (0x1UL << PWR_PDCRA_PD6_Pos)                 /*!< 0x00000040 */
4489 #define PWR_PDCRA_PD6             PWR_PDCRA_PD6_Msk                            /*!< Pin PA6 Pull-Down set */
4490 #define PWR_PDCRA_PD7_Pos         (7U)
4491 #define PWR_PDCRA_PD7_Msk         (0x1UL << PWR_PDCRA_PD7_Pos)                 /*!< 0x00000080 */
4492 #define PWR_PDCRA_PD7             PWR_PDCRA_PD7_Msk                            /*!< Pin PA7 Pull-Down set */
4493 #define PWR_PDCRA_PD8_Pos         (8U)
4494 #define PWR_PDCRA_PD8_Msk         (0x1UL << PWR_PDCRA_PD8_Pos)                 /*!< 0x00000100 */
4495 #define PWR_PDCRA_PD8             PWR_PDCRA_PD8_Msk                            /*!< Pin PA8 Pull-Down set */
4496 #define PWR_PDCRA_PD9_Pos         (9U)
4497 #define PWR_PDCRA_PD9_Msk         (0x1UL << PWR_PDCRA_PD9_Pos)                 /*!< 0x00000200 */
4498 #define PWR_PDCRA_PD9             PWR_PDCRA_PD9_Msk                            /*!< Pin PA9 Pull-Down set */
4499 #define PWR_PDCRA_PD10_Pos        (10U)
4500 #define PWR_PDCRA_PD10_Msk        (0x1UL << PWR_PDCRA_PD10_Pos)                /*!< 0x00000400 */
4501 #define PWR_PDCRA_PD10            PWR_PDCRA_PD10_Msk                           /*!< Pin PA10 Pull-Down set */
4502 #define PWR_PDCRA_PD11_Pos        (11U)
4503 #define PWR_PDCRA_PD11_Msk        (0x1UL << PWR_PDCRA_PD11_Pos)                /*!< 0x00000800 */
4504 #define PWR_PDCRA_PD11            PWR_PDCRA_PD11_Msk                           /*!< Pin PA11 Pull-Down set */
4505 #define PWR_PDCRA_PD12_Pos        (12U)
4506 #define PWR_PDCRA_PD12_Msk        (0x1UL << PWR_PDCRA_PD12_Pos)                /*!< 0x00001000 */
4507 #define PWR_PDCRA_PD12            PWR_PDCRA_PD12_Msk                           /*!< Pin PA12 Pull-Down set */
4508 #define PWR_PDCRA_PD13_Pos        (13U)
4509 #define PWR_PDCRA_PD13_Msk        (0x1UL << PWR_PDCRA_PD13_Pos)                /*!< 0x00002000 */
4510 #define PWR_PDCRA_PD13            PWR_PDCRA_PD13_Msk                           /*!< Pin PA13 Pull-Down set */
4511 #define PWR_PDCRA_PD14_Pos        (14U)
4512 #define PWR_PDCRA_PD14_Msk        (0x1UL << PWR_PDCRA_PD14_Pos)                /*!< 0x00004000 */
4513 #define PWR_PDCRA_PD14            PWR_PDCRA_PD14_Msk                           /*!< Pin PA14 Pull-Down set */
4514 #define PWR_PDCRA_PD15_Pos        (15U)
4515 #define PWR_PDCRA_PD15_Msk        (0x1UL << PWR_PDCRA_PD15_Pos)                /*!< 0x00008000 */
4516 #define PWR_PDCRA_PD15            PWR_PDCRA_PD15_Msk                           /*!< Pin PA15 Pull-Down set */
4517 
4518 /********************  Bit definition for PWR_PUCRB register  *****************/
4519 #define PWR_PUCRB_PU0_Pos         (0U)
4520 #define PWR_PUCRB_PU0_Msk         (0x1UL << PWR_PUCRB_PU0_Pos)                 /*!< 0x00000001 */
4521 #define PWR_PUCRB_PU0             PWR_PUCRB_PU0_Msk                            /*!< Pin PB0 Pull-Up set */
4522 #define PWR_PUCRB_PU1_Pos         (1U)
4523 #define PWR_PUCRB_PU1_Msk         (0x1UL << PWR_PUCRB_PU1_Pos)                 /*!< 0x00000002 */
4524 #define PWR_PUCRB_PU1             PWR_PUCRB_PU1_Msk                            /*!< Pin PB1 Pull-Up set */
4525 #define PWR_PUCRB_PU2_Pos         (2U)
4526 #define PWR_PUCRB_PU2_Msk         (0x1UL << PWR_PUCRB_PU2_Pos)                 /*!< 0x00000004 */
4527 #define PWR_PUCRB_PU2             PWR_PUCRB_PU2_Msk                            /*!< Pin PB2 Pull-Up set */
4528 #define PWR_PUCRB_PU3_Pos         (3U)
4529 #define PWR_PUCRB_PU3_Msk         (0x1UL << PWR_PUCRB_PU3_Pos)                 /*!< 0x00000008 */
4530 #define PWR_PUCRB_PU3             PWR_PUCRB_PU3_Msk                            /*!< Pin PB3 Pull-Up set */
4531 #define PWR_PUCRB_PU4_Pos         (4U)
4532 #define PWR_PUCRB_PU4_Msk         (0x1UL << PWR_PUCRB_PU4_Pos)                 /*!< 0x00000010 */
4533 #define PWR_PUCRB_PU4             PWR_PUCRB_PU4_Msk                            /*!< Pin PB4 Pull-Up set */
4534 #define PWR_PUCRB_PU5_Pos         (5U)
4535 #define PWR_PUCRB_PU5_Msk         (0x1UL << PWR_PUCRB_PU5_Pos)                 /*!< 0x00000020 */
4536 #define PWR_PUCRB_PU5             PWR_PUCRB_PU5_Msk                            /*!< Pin PB5 Pull-Up set */
4537 #define PWR_PUCRB_PU6_Pos         (6U)
4538 #define PWR_PUCRB_PU6_Msk         (0x1UL << PWR_PUCRB_PU6_Pos)                 /*!< 0x00000040 */
4539 #define PWR_PUCRB_PU6             PWR_PUCRB_PU6_Msk                            /*!< Pin PB6 Pull-Up set */
4540 #define PWR_PUCRB_PU7_Pos         (7U)
4541 #define PWR_PUCRB_PU7_Msk         (0x1UL << PWR_PUCRB_PU7_Pos)                 /*!< 0x00000080 */
4542 #define PWR_PUCRB_PU7             PWR_PUCRB_PU7_Msk                            /*!< Pin PB7 Pull-Up set */
4543 #define PWR_PUCRB_PU8_Pos         (8U)
4544 #define PWR_PUCRB_PU8_Msk         (0x1UL << PWR_PUCRB_PU8_Pos)                 /*!< 0x00000100 */
4545 #define PWR_PUCRB_PU8             PWR_PUCRB_PU8_Msk                            /*!< Pin PB8 Pull-Up set */
4546 #define PWR_PUCRB_PU9_Pos         (9U)
4547 #define PWR_PUCRB_PU9_Msk         (0x1UL << PWR_PUCRB_PU9_Pos)                 /*!< 0x00000200 */
4548 #define PWR_PUCRB_PU9             PWR_PUCRB_PU9_Msk                            /*!< Pin PB9 Pull-Up set */
4549 #define PWR_PUCRB_PU10_Pos        (10U)
4550 #define PWR_PUCRB_PU10_Msk        (0x1UL << PWR_PUCRB_PU10_Pos)                /*!< 0x00000400 */
4551 #define PWR_PUCRB_PU10            PWR_PUCRB_PU10_Msk                           /*!< Pin PB10 Pull-Up set */
4552 #define PWR_PUCRB_PU11_Pos        (11U)
4553 #define PWR_PUCRB_PU11_Msk        (0x1UL << PWR_PUCRB_PU11_Pos)                /*!< 0x00000800 */
4554 #define PWR_PUCRB_PU11            PWR_PUCRB_PU11_Msk                           /*!< Pin PB11 Pull-Up set */
4555 #define PWR_PUCRB_PU12_Pos        (12U)
4556 #define PWR_PUCRB_PU12_Msk        (0x1UL << PWR_PUCRB_PU12_Pos)                /*!< 0x00001000 */
4557 #define PWR_PUCRB_PU12            PWR_PUCRB_PU12_Msk                           /*!< Pin PB12 Pull-Up set */
4558 #define PWR_PUCRB_PU13_Pos        (13U)
4559 #define PWR_PUCRB_PU13_Msk        (0x1UL << PWR_PUCRB_PU13_Pos)                /*!< 0x00002000 */
4560 #define PWR_PUCRB_PU13            PWR_PUCRB_PU13_Msk                           /*!< Pin PB13 Pull-Up set */
4561 #define PWR_PUCRB_PU14_Pos        (14U)
4562 #define PWR_PUCRB_PU14_Msk        (0x1UL << PWR_PUCRB_PU14_Pos)                /*!< 0x00004000 */
4563 #define PWR_PUCRB_PU14            PWR_PUCRB_PU14_Msk                           /*!< Pin PB14 Pull-Up set */
4564 #define PWR_PUCRB_PU15_Pos        (15U)
4565 #define PWR_PUCRB_PU15_Msk        (0x1UL << PWR_PUCRB_PU15_Pos)                /*!< 0x00008000 */
4566 #define PWR_PUCRB_PU15            PWR_PUCRB_PU15_Msk                           /*!< Pin PB15 Pull-Up set */
4567 
4568 /********************  Bit definition for PWR_PDCRB register  *****************/
4569 #define PWR_PDCRB_PD0_Pos         (0U)
4570 #define PWR_PDCRB_PD0_Msk         (0x1UL << PWR_PDCRB_PD0_Pos)                 /*!< 0x00000001 */
4571 #define PWR_PDCRB_PD0             PWR_PDCRB_PD0_Msk                            /*!< Pin PB0 Pull-Down set */
4572 #define PWR_PDCRB_PD1_Pos         (1U)
4573 #define PWR_PDCRB_PD1_Msk         (0x1UL << PWR_PDCRB_PD1_Pos)                 /*!< 0x00000002 */
4574 #define PWR_PDCRB_PD1             PWR_PDCRB_PD1_Msk                            /*!< Pin PB1 Pull-Down set */
4575 #define PWR_PDCRB_PD2_Pos         (2U)
4576 #define PWR_PDCRB_PD2_Msk         (0x1UL << PWR_PDCRB_PD2_Pos)                 /*!< 0x00000004 */
4577 #define PWR_PDCRB_PD2             PWR_PDCRB_PD2_Msk                            /*!< Pin PB2 Pull-Down set */
4578 #define PWR_PDCRB_PD3_Pos         (3U)
4579 #define PWR_PDCRB_PD3_Msk         (0x1UL << PWR_PDCRB_PD3_Pos)                 /*!< 0x00000008 */
4580 #define PWR_PDCRB_PD3             PWR_PDCRB_PD3_Msk                            /*!< Pin PB3 Pull-Down set */
4581 #define PWR_PDCRB_PD4_Pos         (4U)
4582 #define PWR_PDCRB_PD4_Msk         (0x1UL << PWR_PDCRB_PD4_Pos)                 /*!< 0x00000010 */
4583 #define PWR_PDCRB_PD4             PWR_PDCRB_PD4_Msk                            /*!< Pin PB4 Pull-Down set */
4584 #define PWR_PDCRB_PD5_Pos         (5U)
4585 #define PWR_PDCRB_PD5_Msk         (0x1UL << PWR_PDCRB_PD5_Pos)                 /*!< 0x00000020 */
4586 #define PWR_PDCRB_PD5             PWR_PDCRB_PD5_Msk                            /*!< Pin PB5 Pull-Down set */
4587 #define PWR_PDCRB_PD6_Pos         (6U)
4588 #define PWR_PDCRB_PD6_Msk         (0x1UL << PWR_PDCRB_PD6_Pos)                 /*!< 0x00000040 */
4589 #define PWR_PDCRB_PD6             PWR_PDCRB_PD6_Msk                            /*!< Pin PB6 Pull-Down set */
4590 #define PWR_PDCRB_PD7_Pos         (7U)
4591 #define PWR_PDCRB_PD7_Msk         (0x1UL << PWR_PDCRB_PD7_Pos)                 /*!< 0x00000080 */
4592 #define PWR_PDCRB_PD7             PWR_PDCRB_PD7_Msk                            /*!< Pin PB7 Pull-Down set */
4593 #define PWR_PDCRB_PD8_Pos         (8U)
4594 #define PWR_PDCRB_PD8_Msk         (0x1UL << PWR_PDCRB_PD8_Pos)                 /*!< 0x00000100 */
4595 #define PWR_PDCRB_PD8             PWR_PDCRB_PD8_Msk                            /*!< Pin PB8 Pull-Down set */
4596 #define PWR_PDCRB_PD9_Pos         (9U)
4597 #define PWR_PDCRB_PD9_Msk         (0x1UL << PWR_PDCRB_PD9_Pos)                 /*!< 0x00000200 */
4598 #define PWR_PDCRB_PD9             PWR_PDCRB_PD9_Msk                            /*!< Pin PB9 Pull-Down set */
4599 #define PWR_PDCRB_PD10_Pos        (10U)
4600 #define PWR_PDCRB_PD10_Msk        (0x1UL << PWR_PDCRB_PD10_Pos)                /*!< 0x00000400 */
4601 #define PWR_PDCRB_PD10            PWR_PDCRB_PD10_Msk                           /*!< Pin PB10 Pull-Down set */
4602 #define PWR_PDCRB_PD11_Pos        (11U)
4603 #define PWR_PDCRB_PD11_Msk        (0x1UL << PWR_PDCRB_PD11_Pos)                /*!< 0x00000800 */
4604 #define PWR_PDCRB_PD11            PWR_PDCRB_PD11_Msk                           /*!< Pin PB11 Pull-Down set */
4605 #define PWR_PDCRB_PD12_Pos        (12U)
4606 #define PWR_PDCRB_PD12_Msk        (0x1UL << PWR_PDCRB_PD12_Pos)                /*!< 0x00001000 */
4607 #define PWR_PDCRB_PD12            PWR_PDCRB_PD12_Msk                           /*!< Pin PB12 Pull-Down set */
4608 #define PWR_PDCRB_PD13_Pos        (13U)
4609 #define PWR_PDCRB_PD13_Msk        (0x1UL << PWR_PDCRB_PD13_Pos)                /*!< 0x00002000 */
4610 #define PWR_PDCRB_PD13            PWR_PDCRB_PD13_Msk                           /*!< Pin PB13 Pull-Down set */
4611 #define PWR_PDCRB_PD14_Pos        (14U)
4612 #define PWR_PDCRB_PD14_Msk        (0x1UL << PWR_PDCRB_PD14_Pos)                /*!< 0x00004000 */
4613 #define PWR_PDCRB_PD14            PWR_PDCRB_PD14_Msk                           /*!< Pin PB14 Pull-Down set */
4614 #define PWR_PDCRB_PD15_Pos        (15U)
4615 #define PWR_PDCRB_PD15_Msk        (0x1UL << PWR_PDCRB_PD15_Pos)                /*!< 0x00008000 */
4616 #define PWR_PDCRB_PD15            PWR_PDCRB_PD15_Msk                           /*!< Pin PB15 Pull-Down set */
4617 
4618 /********************  Bit definition for PWR_PUCRC register  *****************/
4619 #define PWR_PUCRC_PU0_Pos         (0U)
4620 #define PWR_PUCRC_PU0_Msk         (0x1UL << PWR_PUCRC_PU0_Pos)                 /*!< 0x00000001 */
4621 #define PWR_PUCRC_PU0             PWR_PUCRC_PU0_Msk                            /*!< Pin PC0 Pull-Up set */
4622 #define PWR_PUCRC_PU1_Pos         (1U)
4623 #define PWR_PUCRC_PU1_Msk         (0x1UL << PWR_PUCRC_PU1_Pos)                 /*!< 0x00000002 */
4624 #define PWR_PUCRC_PU1             PWR_PUCRC_PU1_Msk                            /*!< Pin PC1 Pull-Up set */
4625 #define PWR_PUCRC_PU2_Pos         (2U)
4626 #define PWR_PUCRC_PU2_Msk         (0x1UL << PWR_PUCRC_PU2_Pos)                 /*!< 0x00000004 */
4627 #define PWR_PUCRC_PU2             PWR_PUCRC_PU2_Msk                            /*!< Pin PC2 Pull-Up set */
4628 #define PWR_PUCRC_PU3_Pos         (3U)
4629 #define PWR_PUCRC_PU3_Msk         (0x1UL << PWR_PUCRC_PU3_Pos)                 /*!< 0x00000008 */
4630 #define PWR_PUCRC_PU3             PWR_PUCRC_PU3_Msk                            /*!< Pin PC3 Pull-Up set */
4631 #define PWR_PUCRC_PU4_Pos         (4U)
4632 #define PWR_PUCRC_PU4_Msk         (0x1UL << PWR_PUCRC_PU4_Pos)                 /*!< 0x00000010 */
4633 #define PWR_PUCRC_PU4             PWR_PUCRC_PU4_Msk                            /*!< Pin PC4 Pull-Up set */
4634 #define PWR_PUCRC_PU5_Pos         (5U)
4635 #define PWR_PUCRC_PU5_Msk         (0x1UL << PWR_PUCRC_PU5_Pos)                 /*!< 0x00000020 */
4636 #define PWR_PUCRC_PU5             PWR_PUCRC_PU5_Msk                            /*!< Pin PC5 Pull-Up set */
4637 #define PWR_PUCRC_PU6_Pos         (6U)
4638 #define PWR_PUCRC_PU6_Msk         (0x1UL << PWR_PUCRC_PU6_Pos)                 /*!< 0x00000040 */
4639 #define PWR_PUCRC_PU6             PWR_PUCRC_PU6_Msk                            /*!< Pin PC6 Pull-Up set */
4640 #define PWR_PUCRC_PU7_Pos         (7U)
4641 #define PWR_PUCRC_PU7_Msk         (0x1UL << PWR_PUCRC_PU7_Pos)                 /*!< 0x00000080 */
4642 #define PWR_PUCRC_PU7             PWR_PUCRC_PU7_Msk                            /*!< Pin PC7 Pull-Up set */
4643 #define PWR_PUCRC_PU8_Pos         (8U)
4644 #define PWR_PUCRC_PU8_Msk         (0x1UL << PWR_PUCRC_PU8_Pos)                 /*!< 0x00000100 */
4645 #define PWR_PUCRC_PU8             PWR_PUCRC_PU8_Msk                            /*!< Pin PC8 Pull-Up set */
4646 #define PWR_PUCRC_PU9_Pos         (9U)
4647 #define PWR_PUCRC_PU9_Msk         (0x1UL << PWR_PUCRC_PU9_Pos)                 /*!< 0x00000200 */
4648 #define PWR_PUCRC_PU9             PWR_PUCRC_PU9_Msk                            /*!< Pin PC9 Pull-Up set */
4649 #define PWR_PUCRC_PU10_Pos        (10U)
4650 #define PWR_PUCRC_PU10_Msk        (0x1UL << PWR_PUCRC_PU10_Pos)                /*!< 0x00000400 */
4651 #define PWR_PUCRC_PU10            PWR_PUCRC_PU10_Msk                           /*!< Pin PC10 Pull-Up set */
4652 #define PWR_PUCRC_PU11_Pos        (11U)
4653 #define PWR_PUCRC_PU11_Msk        (0x1UL << PWR_PUCRC_PU11_Pos)                /*!< 0x00000800 */
4654 #define PWR_PUCRC_PU11            PWR_PUCRC_PU11_Msk                           /*!< Pin PC11 Pull-Up set */
4655 #define PWR_PUCRC_PU12_Pos        (12U)
4656 #define PWR_PUCRC_PU12_Msk        (0x1UL << PWR_PUCRC_PU12_Pos)                /*!< 0x00001000 */
4657 #define PWR_PUCRC_PU12            PWR_PUCRC_PU12_Msk                           /*!< Pin PC12 Pull-Up set */
4658 #define PWR_PUCRC_PU13_Pos        (13U)
4659 #define PWR_PUCRC_PU13_Msk        (0x1UL << PWR_PUCRC_PU13_Pos)                /*!< 0x00002000 */
4660 #define PWR_PUCRC_PU13            PWR_PUCRC_PU13_Msk                           /*!< Pin PC13 Pull-Up set */
4661 #define PWR_PUCRC_PU14_Pos        (14U)
4662 #define PWR_PUCRC_PU14_Msk        (0x1UL << PWR_PUCRC_PU14_Pos)                /*!< 0x00004000 */
4663 #define PWR_PUCRC_PU14            PWR_PUCRC_PU14_Msk                           /*!< Pin PC14 Pull-Up set */
4664 #define PWR_PUCRC_PU15_Pos        (15U)
4665 #define PWR_PUCRC_PU15_Msk        (0x1UL << PWR_PUCRC_PU15_Pos)                /*!< 0x00008000 */
4666 #define PWR_PUCRC_PU15            PWR_PUCRC_PU15_Msk                           /*!< Pin PC15 Pull-Up set */
4667 
4668 /********************  Bit definition for PWR_PDCRC register  *****************/
4669 #define PWR_PDCRC_PD0_Pos         (0U)
4670 #define PWR_PDCRC_PD0_Msk         (0x1UL << PWR_PDCRC_PD0_Pos)                 /*!< 0x00000001 */
4671 #define PWR_PDCRC_PD0             PWR_PDCRC_PD0_Msk                            /*!< Pin PC0 Pull-Down set */
4672 #define PWR_PDCRC_PD1_Pos         (1U)
4673 #define PWR_PDCRC_PD1_Msk         (0x1UL << PWR_PDCRC_PD1_Pos)                 /*!< 0x00000002 */
4674 #define PWR_PDCRC_PD1             PWR_PDCRC_PD1_Msk                            /*!< Pin PC1 Pull-Down set */
4675 #define PWR_PDCRC_PD2_Pos         (2U)
4676 #define PWR_PDCRC_PD2_Msk         (0x1UL << PWR_PDCRC_PD2_Pos)                 /*!< 0x00000004 */
4677 #define PWR_PDCRC_PD2             PWR_PDCRC_PD2_Msk                            /*!< Pin PC2 Pull-Down set */
4678 #define PWR_PDCRC_PD3_Pos         (3U)
4679 #define PWR_PDCRC_PD3_Msk         (0x1UL << PWR_PDCRC_PD3_Pos)                 /*!< 0x00000008 */
4680 #define PWR_PDCRC_PD3             PWR_PDCRC_PD3_Msk                            /*!< Pin PC3 Pull-Down set */
4681 #define PWR_PDCRC_PD4_Pos         (4U)
4682 #define PWR_PDCRC_PD4_Msk         (0x1UL << PWR_PDCRC_PD4_Pos)                 /*!< 0x00000010 */
4683 #define PWR_PDCRC_PD4             PWR_PDCRC_PD4_Msk                            /*!< Pin PC4 Pull-Down set */
4684 #define PWR_PDCRC_PD5_Pos         (5U)
4685 #define PWR_PDCRC_PD5_Msk         (0x1UL << PWR_PDCRC_PD5_Pos)                 /*!< 0x00000020 */
4686 #define PWR_PDCRC_PD5             PWR_PDCRC_PD5_Msk                            /*!< Pin PC5 Pull-Down set */
4687 #define PWR_PDCRC_PD6_Pos         (6U)
4688 #define PWR_PDCRC_PD6_Msk         (0x1UL << PWR_PDCRC_PD6_Pos)                 /*!< 0x00000040 */
4689 #define PWR_PDCRC_PD6             PWR_PDCRC_PD6_Msk                            /*!< Pin PC6 Pull-Down set */
4690 #define PWR_PDCRC_PD7_Pos         (7U)
4691 #define PWR_PDCRC_PD7_Msk         (0x1UL << PWR_PDCRC_PD7_Pos)                 /*!< 0x00000080 */
4692 #define PWR_PDCRC_PD7             PWR_PDCRC_PD7_Msk                            /*!< Pin PC7 Pull-Down set */
4693 #define PWR_PDCRC_PD8_Pos         (8U)
4694 #define PWR_PDCRC_PD8_Msk         (0x1UL << PWR_PDCRC_PD8_Pos)                 /*!< 0x00000100 */
4695 #define PWR_PDCRC_PD8             PWR_PDCRC_PD8_Msk                            /*!< Pin PC8 Pull-Down set */
4696 #define PWR_PDCRC_PD9_Pos         (9U)
4697 #define PWR_PDCRC_PD9_Msk         (0x1UL << PWR_PDCRC_PD9_Pos)                 /*!< 0x00000200 */
4698 #define PWR_PDCRC_PD9             PWR_PDCRC_PD9_Msk                            /*!< Pin PC9 Pull-Down set */
4699 #define PWR_PDCRC_PD10_Pos        (10U)
4700 #define PWR_PDCRC_PD10_Msk        (0x1UL << PWR_PDCRC_PD10_Pos)                /*!< 0x00000400 */
4701 #define PWR_PDCRC_PD10            PWR_PDCRC_PD10_Msk                           /*!< Pin PC10 Pull-Down set */
4702 #define PWR_PDCRC_PD11_Pos        (11U)
4703 #define PWR_PDCRC_PD11_Msk        (0x1UL << PWR_PDCRC_PD11_Pos)                /*!< 0x00000800 */
4704 #define PWR_PDCRC_PD11            PWR_PDCRC_PD11_Msk                           /*!< Pin PC11 Pull-Down set */
4705 #define PWR_PDCRC_PD12_Pos        (12U)
4706 #define PWR_PDCRC_PD12_Msk        (0x1UL << PWR_PDCRC_PD12_Pos)                /*!< 0x00001000 */
4707 #define PWR_PDCRC_PD12            PWR_PDCRC_PD12_Msk                           /*!< Pin PC12 Pull-Down set */
4708 #define PWR_PDCRC_PD13_Pos        (13U)
4709 #define PWR_PDCRC_PD13_Msk        (0x1UL << PWR_PDCRC_PD13_Pos)                /*!< 0x00002000 */
4710 #define PWR_PDCRC_PD13            PWR_PDCRC_PD13_Msk                           /*!< Pin PC13 Pull-Down set */
4711 #define PWR_PDCRC_PD14_Pos        (14U)
4712 #define PWR_PDCRC_PD14_Msk        (0x1UL << PWR_PDCRC_PD14_Pos)                /*!< 0x00004000 */
4713 #define PWR_PDCRC_PD14            PWR_PDCRC_PD14_Msk                           /*!< Pin PC14 Pull-Down set */
4714 #define PWR_PDCRC_PD15_Pos        (15U)
4715 #define PWR_PDCRC_PD15_Msk        (0x1UL << PWR_PDCRC_PD15_Pos)                /*!< 0x00008000 */
4716 #define PWR_PDCRC_PD15            PWR_PDCRC_PD15_Msk                           /*!< Pin PC15 Pull-Down set */
4717 
4718 /********************  Bit definition for PWR_PUCRD register  *****************/
4719 #define PWR_PUCRD_PU0_Pos         (0U)
4720 #define PWR_PUCRD_PU0_Msk         (0x1UL << PWR_PUCRD_PU0_Pos)                 /*!< 0x00000001 */
4721 #define PWR_PUCRD_PU0             PWR_PUCRD_PU0_Msk                            /*!< Pin PD0 Pull-Up set */
4722 #define PWR_PUCRD_PU1_Pos         (1U)
4723 #define PWR_PUCRD_PU1_Msk         (0x1UL << PWR_PUCRD_PU1_Pos)                 /*!< 0x00000002 */
4724 #define PWR_PUCRD_PU1             PWR_PUCRD_PU1_Msk                            /*!< Pin PD1 Pull-Up set */
4725 #define PWR_PUCRD_PU2_Pos         (2U)
4726 #define PWR_PUCRD_PU2_Msk         (0x1UL << PWR_PUCRD_PU2_Pos)                 /*!< 0x00000004 */
4727 #define PWR_PUCRD_PU2             PWR_PUCRD_PU2_Msk                            /*!< Pin PD2 Pull-Up set */
4728 #define PWR_PUCRD_PU3_Pos         (3U)
4729 #define PWR_PUCRD_PU3_Msk         (0x1UL << PWR_PUCRD_PU3_Pos)                 /*!< 0x00000008 */
4730 #define PWR_PUCRD_PU3             PWR_PUCRD_PU3_Msk                            /*!< Pin PD3 Pull-Up set */
4731 #define PWR_PUCRD_PU4_Pos         (4U)
4732 #define PWR_PUCRD_PU4_Msk         (0x1UL << PWR_PUCRD_PU4_Pos)                 /*!< 0x00000010 */
4733 #define PWR_PUCRD_PU4             PWR_PUCRD_PU4_Msk                            /*!< Pin PD4 Pull-Up set */
4734 #define PWR_PUCRD_PU5_Pos         (5U)
4735 #define PWR_PUCRD_PU5_Msk         (0x1UL << PWR_PUCRD_PU5_Pos)                 /*!< 0x00000020 */
4736 #define PWR_PUCRD_PU5             PWR_PUCRD_PU5_Msk                            /*!< Pin PD5 Pull-Up set */
4737 #define PWR_PUCRD_PU6_Pos         (6U)
4738 #define PWR_PUCRD_PU6_Msk         (0x1UL << PWR_PUCRD_PU6_Pos)                 /*!< 0x00000040 */
4739 #define PWR_PUCRD_PU6             PWR_PUCRD_PU6_Msk                            /*!< Pin PD6 Pull-Up set */
4740 #define PWR_PUCRD_PU8_Pos         (8U)
4741 #define PWR_PUCRD_PU8_Msk         (0x1UL << PWR_PUCRD_PU8_Pos)                 /*!< 0x00000100 */
4742 #define PWR_PUCRD_PU8             PWR_PUCRD_PU8_Msk                            /*!< Pin PD8 Pull-Up set */
4743 #define PWR_PUCRD_PU9_Pos         (9U)
4744 #define PWR_PUCRD_PU9_Msk         (0x1UL << PWR_PUCRD_PU9_Pos)                 /*!< 0x00000200 */
4745 #define PWR_PUCRD_PU9             PWR_PUCRD_PU9_Msk                            /*!< Pin PD9 Pull-Up set */
4746 
4747 /********************  Bit definition for PWR_PDCRD register  *****************/
4748 #define PWR_PDCRD_PD0_Pos         (0U)
4749 #define PWR_PDCRD_PD0_Msk         (0x1UL << PWR_PDCRD_PD0_Pos)                 /*!< 0x00000001 */
4750 #define PWR_PDCRD_PD0             PWR_PDCRD_PD0_Msk                            /*!< Pin PD0 Pull-Down set */
4751 #define PWR_PDCRD_PD1_Pos         (1U)
4752 #define PWR_PDCRD_PD1_Msk         (0x1UL << PWR_PDCRD_PD1_Pos)                 /*!< 0x00000002 */
4753 #define PWR_PDCRD_PD1             PWR_PDCRD_PD1_Msk                            /*!< Pin PD1 Pull-Down set */
4754 #define PWR_PDCRD_PD2_Pos         (2U)
4755 #define PWR_PDCRD_PD2_Msk         (0x1UL << PWR_PDCRD_PD2_Pos)                 /*!< 0x00000004 */
4756 #define PWR_PDCRD_PD2             PWR_PDCRD_PD2_Msk                            /*!< Pin PD2 Pull-Down set */
4757 #define PWR_PDCRD_PD3_Pos         (3U)
4758 #define PWR_PDCRD_PD3_Msk         (0x1UL << PWR_PDCRD_PD3_Pos)                 /*!< 0x00000008 */
4759 #define PWR_PDCRD_PD3             PWR_PDCRD_PD3_Msk                            /*!< Pin PD3 Pull-Down set */
4760 #define PWR_PDCRD_PD4_Pos         (4U)
4761 #define PWR_PDCRD_PD4_Msk         (0x1UL << PWR_PDCRD_PD4_Pos)                 /*!< 0x00000010 */
4762 #define PWR_PDCRD_PD4             PWR_PDCRD_PD4_Msk                            /*!< Pin PD4 Pull-Down set */
4763 #define PWR_PDCRD_PD5_Pos         (5U)
4764 #define PWR_PDCRD_PD5_Msk         (0x1UL << PWR_PDCRD_PD5_Pos)                 /*!< 0x00000020 */
4765 #define PWR_PDCRD_PD5             PWR_PDCRD_PD5_Msk                            /*!< Pin PD5 Pull-Down set */
4766 #define PWR_PDCRD_PD6_Pos         (6U)
4767 #define PWR_PDCRD_PD6_Msk         (0x1UL << PWR_PDCRD_PD6_Pos)                 /*!< 0x00000040 */
4768 #define PWR_PDCRD_PD6             PWR_PDCRD_PD6_Msk                            /*!< Pin PD6 Pull-Down set */
4769 #define PWR_PDCRD_PD8_Pos         (8U)
4770 #define PWR_PDCRD_PD8_Msk         (0x1UL << PWR_PDCRD_PD8_Pos)                 /*!< 0x00000100 */
4771 #define PWR_PDCRD_PD8             PWR_PDCRD_PD8_Msk                            /*!< Pin PD8 Pull-Down set */
4772 #define PWR_PDCRD_PD9_Pos         (9U)
4773 #define PWR_PDCRD_PD9_Msk         (0x1UL << PWR_PDCRD_PD9_Pos)                 /*!< 0x00000200 */
4774 #define PWR_PDCRD_PD9             PWR_PDCRD_PD9_Msk                            /*!< Pin PD9 Pull-Down set */
4775 
4776 /********************  Bit definition for PWR_PUCRF register  *****************/
4777 #define PWR_PUCRF_PU0_Pos         (0U)
4778 #define PWR_PUCRF_PU0_Msk         (0x1UL << PWR_PUCRF_PU0_Pos)                 /*!< 0x00000001 */
4779 #define PWR_PUCRF_PU0             PWR_PUCRF_PU0_Msk                            /*!< Pin PF0 Pull-Up set */
4780 #define PWR_PUCRF_PU1_Pos         (1U)
4781 #define PWR_PUCRF_PU1_Msk         (0x1UL << PWR_PUCRF_PU1_Pos)                 /*!< 0x00000002 */
4782 #define PWR_PUCRF_PU1             PWR_PUCRF_PU1_Msk                            /*!< Pin PF1 Pull-Up set */
4783 #define PWR_PUCRF_PU2_Pos         (2U)
4784 #define PWR_PUCRF_PU2_Msk         (0x1UL << PWR_PUCRF_PU2_Pos)                 /*!< 0x00000004 */
4785 #define PWR_PUCRF_PU2             PWR_PUCRF_PU2_Msk                            /*!< Pin PF2 Pull-Up set */
4786 #define PWR_PUCRF_PU3_Pos         (3U)
4787 #define PWR_PUCRF_PU3_Msk         (0x1UL << PWR_PUCRF_PU3_Pos)                 /*!< 0x00000008 */
4788 #define PWR_PUCRF_PU3             PWR_PUCRF_PU3_Msk                            /*!< Pin PF3 Pull-Up set */
4789 #define PWR_PUCRF_PU4_Pos         (4U)
4790 #define PWR_PUCRF_PU4_Msk         (0x1UL << PWR_PUCRF_PU4_Pos)                 /*!< 0x00000010 */
4791 #define PWR_PUCRF_PU4             PWR_PUCRF_PU4_Msk                            /*!< Pin PF4 Pull-Up set */
4792 
4793 /********************  Bit definition for PWR_PDCRF register  *****************/
4794 #define PWR_PDCRF_PD0_Pos         (0U)
4795 #define PWR_PDCRF_PD0_Msk         (0x1UL << PWR_PDCRF_PD0_Pos)                 /*!< 0x00000001 */
4796 #define PWR_PDCRF_PD0             PWR_PDCRF_PD0_Msk                            /*!< Pin PF0 Pull-Down set */
4797 #define PWR_PDCRF_PD1_Pos         (1U)
4798 #define PWR_PDCRF_PD1_Msk         (0x1UL << PWR_PDCRF_PD1_Pos)                 /*!< 0x00000002 */
4799 #define PWR_PDCRF_PD1             PWR_PDCRF_PD1_Msk                            /*!< Pin PF1 Pull-Down set */
4800 #define PWR_PDCRF_PD2_Pos         (2U)
4801 #define PWR_PDCRF_PD2_Msk         (0x1UL << PWR_PDCRF_PD2_Pos)                 /*!< 0x00000004 */
4802 #define PWR_PDCRF_PD2             PWR_PDCRF_PD2_Msk                            /*!< Pin PF2 Pull-Down set */
4803 #define PWR_PDCRF_PD3_Pos         (3U)
4804 #define PWR_PDCRF_PD3_Msk         (0x1UL << PWR_PDCRF_PD3_Pos)                 /*!< 0x00000008 */
4805 #define PWR_PDCRF_PD3             PWR_PDCRF_PD3_Msk                            /*!< Pin PF3 Pull-Down set */
4806 #define PWR_PDCRF_PD4_Pos         (4U)
4807 #define PWR_PDCRF_PD4_Msk         (0x1UL << PWR_PDCRF_PD4_Pos)                 /*!< 0x00000010 */
4808 #define PWR_PDCRF_PD4             PWR_PDCRF_PD4_Msk                            /*!< Pin PF4 Pull-Down set */
4809 
4810 /******************************************************************************/
4811 /*                                                                            */
4812 /*                           Reset and Clock Control                          */
4813 /*                                                                            */
4814 /******************************************************************************/
4815 /*
4816 * @brief Specific device feature definitions  (not present on all devices in the STM32G0 series)
4817 */
4818 #define RCC_PLLQ_SUPPORT
4819 
4820 /********************  Bit definition for RCC_CR register  *****************/
4821 #define RCC_CR_HSION_Pos                 (8U)
4822 #define RCC_CR_HSION_Msk                 (0x1UL << RCC_CR_HSION_Pos)           /*!< 0x00000100 */
4823 #define RCC_CR_HSION                     RCC_CR_HSION_Msk                      /*!< Internal High Speed clock enable */
4824 #define RCC_CR_HSIKERON_Pos              (9U)
4825 #define RCC_CR_HSIKERON_Msk              (0x1UL << RCC_CR_HSIKERON_Pos)        /*!< 0x00000200 */
4826 #define RCC_CR_HSIKERON                  RCC_CR_HSIKERON_Msk                   /*!< Internal High Speed clock enable for some IPs Kernel */
4827 #define RCC_CR_HSIRDY_Pos                (10U)
4828 #define RCC_CR_HSIRDY_Msk                (0x1UL << RCC_CR_HSIRDY_Pos)          /*!< 0x00000400 */
4829 #define RCC_CR_HSIRDY                    RCC_CR_HSIRDY_Msk                     /*!< Internal High Speed clock ready flag */
4830 #define RCC_CR_HSIDIV_Pos                (11U)
4831 #define RCC_CR_HSIDIV_Msk                (0x7UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00003800 */
4832 #define RCC_CR_HSIDIV                    RCC_CR_HSIDIV_Msk                     /*!< HSIDIV[13:11] Internal High Speed clock division factor */
4833 #define RCC_CR_HSIDIV_0                  (0x1UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00000800 */
4834 #define RCC_CR_HSIDIV_1                  (0x2UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00001000 */
4835 #define RCC_CR_HSIDIV_2                  (0x4UL << RCC_CR_HSIDIV_Pos)          /*!< 0x00002000 */
4836 #define RCC_CR_HSEON_Pos                 (16U)
4837 #define RCC_CR_HSEON_Msk                 (0x1UL << RCC_CR_HSEON_Pos)           /*!< 0x00010000 */
4838 #define RCC_CR_HSEON                     RCC_CR_HSEON_Msk                      /*!< External High Speed clock enable */
4839 #define RCC_CR_HSERDY_Pos                (17U)
4840 #define RCC_CR_HSERDY_Msk                (0x1UL << RCC_CR_HSERDY_Pos)          /*!< 0x00020000 */
4841 #define RCC_CR_HSERDY                    RCC_CR_HSERDY_Msk                     /*!< External High Speed clock ready */
4842 #define RCC_CR_HSEBYP_Pos                (18U)
4843 #define RCC_CR_HSEBYP_Msk                (0x1UL << RCC_CR_HSEBYP_Pos)          /*!< 0x00040000 */
4844 #define RCC_CR_HSEBYP                    RCC_CR_HSEBYP_Msk                     /*!< External High Speed clock Bypass */
4845 #define RCC_CR_CSSON_Pos                 (19U)
4846 #define RCC_CR_CSSON_Msk                 (0x1UL << RCC_CR_CSSON_Pos)           /*!< 0x00080000 */
4847 #define RCC_CR_CSSON                     RCC_CR_CSSON_Msk                      /*!< HSE Clock Security System enable */
4848 
4849 #define RCC_CR_PLLON_Pos                 (24U)
4850 #define RCC_CR_PLLON_Msk                 (0x1UL << RCC_CR_PLLON_Pos)           /*!< 0x01000000 */
4851 #define RCC_CR_PLLON                     RCC_CR_PLLON_Msk                      /*!< System PLL clock enable */
4852 #define RCC_CR_PLLRDY_Pos                (25U)
4853 #define RCC_CR_PLLRDY_Msk                (0x1UL << RCC_CR_PLLRDY_Pos)          /*!< 0x02000000 */
4854 #define RCC_CR_PLLRDY                    RCC_CR_PLLRDY_Msk                     /*!< System PLL clock ready */
4855 
4856 /********************  Bit definition for RCC_ICSCR register  ***************/
4857 /*!< HSICAL configuration */
4858 #define RCC_ICSCR_HSICAL_Pos             (0U)
4859 #define RCC_ICSCR_HSICAL_Msk             (0xFFUL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x000000FF */
4860 #define RCC_ICSCR_HSICAL                 RCC_ICSCR_HSICAL_Msk                  /*!< HSICAL[7:0] bits */
4861 #define RCC_ICSCR_HSICAL_0               (0x01UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000001 */
4862 #define RCC_ICSCR_HSICAL_1               (0x02UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000002 */
4863 #define RCC_ICSCR_HSICAL_2               (0x04UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000004 */
4864 #define RCC_ICSCR_HSICAL_3               (0x08UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000008 */
4865 #define RCC_ICSCR_HSICAL_4               (0x10UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000010 */
4866 #define RCC_ICSCR_HSICAL_5               (0x20UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000020 */
4867 #define RCC_ICSCR_HSICAL_6               (0x40UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000040 */
4868 #define RCC_ICSCR_HSICAL_7               (0x80UL << RCC_ICSCR_HSICAL_Pos)      /*!< 0x00000080 */
4869 
4870 /*!< HSITRIM configuration */
4871 #define RCC_ICSCR_HSITRIM_Pos            (8U)
4872 #define RCC_ICSCR_HSITRIM_Msk            (0x7FUL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00007F00 */
4873 #define RCC_ICSCR_HSITRIM                RCC_ICSCR_HSITRIM_Msk                 /*!< HSITRIM[14:8] bits */
4874 #define RCC_ICSCR_HSITRIM_0              (0x01UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000100 */
4875 #define RCC_ICSCR_HSITRIM_1              (0x02UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000200 */
4876 #define RCC_ICSCR_HSITRIM_2              (0x04UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000400 */
4877 #define RCC_ICSCR_HSITRIM_3              (0x08UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00000800 */
4878 #define RCC_ICSCR_HSITRIM_4              (0x10UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00001000 */
4879 #define RCC_ICSCR_HSITRIM_5              (0x20UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00002000 */
4880 #define RCC_ICSCR_HSITRIM_6              (0x40UL << RCC_ICSCR_HSITRIM_Pos)     /*!< 0x00004000 */
4881 
4882 /********************  Bit definition for RCC_CFGR register  ***************/
4883 /*!< SW configuration */
4884 #define RCC_CFGR_SW_Pos                (0U)
4885 #define RCC_CFGR_SW_Msk                (0x7UL << RCC_CFGR_SW_Pos)              /*!< 0x00000007 */
4886 #define RCC_CFGR_SW                    RCC_CFGR_SW_Msk                         /*!< SW[2:0] bits (System clock Switch) */
4887 #define RCC_CFGR_SW_0                  (0x1UL << RCC_CFGR_SW_Pos)              /*!< 0x00000001 */
4888 #define RCC_CFGR_SW_1                  (0x2UL << RCC_CFGR_SW_Pos)              /*!< 0x00000002 */
4889 #define RCC_CFGR_SW_2                  (0x4UL << RCC_CFGR_SW_Pos)              /*!< 0x00000004 */
4890 
4891 /*!< SWS configuration */
4892 #define RCC_CFGR_SWS_Pos               (3U)
4893 #define RCC_CFGR_SWS_Msk               (0x7UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000038 */
4894 #define RCC_CFGR_SWS                   RCC_CFGR_SWS_Msk                        /*!< SWS[2:0] bits (System Clock Switch Status) */
4895 #define RCC_CFGR_SWS_0                 (0x1UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000008 */
4896 #define RCC_CFGR_SWS_1                 (0x2UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000010 */
4897 #define RCC_CFGR_SWS_2                 (0x4UL << RCC_CFGR_SWS_Pos)             /*!< 0x00000020 */
4898 
4899 /*!< HPRE configuration */
4900 #define RCC_CFGR_HPRE_Pos              (8U)
4901 #define RCC_CFGR_HPRE_Msk              (0xFUL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000F00 */
4902 #define RCC_CFGR_HPRE                  RCC_CFGR_HPRE_Msk                       /*!< HPRE[3:0] bits (AHB prescaler) */
4903 #define RCC_CFGR_HPRE_0                (0x1UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000100 */
4904 #define RCC_CFGR_HPRE_1                (0x2UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000200 */
4905 #define RCC_CFGR_HPRE_2                (0x4UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000400 */
4906 #define RCC_CFGR_HPRE_3                (0x8UL << RCC_CFGR_HPRE_Pos)            /*!< 0x00000800 */
4907 
4908 /*!< PPRE configuration */
4909 #define RCC_CFGR_PPRE_Pos              (12U)
4910 #define RCC_CFGR_PPRE_Msk              (0x7UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00007000 */
4911 #define RCC_CFGR_PPRE                  RCC_CFGR_PPRE_Msk                       /*!< PRE1[2:0] bits (APB prescaler) */
4912 #define RCC_CFGR_PPRE_0                (0x1UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00001000 */
4913 #define RCC_CFGR_PPRE_1                (0x2UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00002000 */
4914 #define RCC_CFGR_PPRE_2                (0x4UL << RCC_CFGR_PPRE_Pos)            /*!< 0x00004000 */
4915 
4916 
4917 /*!< MCOSEL configuration */
4918 #define RCC_CFGR_MCOSEL_Pos            (24U)
4919 #define RCC_CFGR_MCOSEL_Msk            (0x7UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x07000000 */
4920 #define RCC_CFGR_MCOSEL                RCC_CFGR_MCOSEL_Msk                     /*!< MCOSEL [2:0] bits (Clock output selection) */
4921 #define RCC_CFGR_MCOSEL_0              (0x1UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x01000000 */
4922 #define RCC_CFGR_MCOSEL_1              (0x2UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x02000000 */
4923 #define RCC_CFGR_MCOSEL_2              (0x4UL << RCC_CFGR_MCOSEL_Pos)          /*!< 0x04000000 */
4924 
4925 /*!< MCO Prescaler configuration */
4926 #define RCC_CFGR_MCOPRE_Pos            (28U)
4927 #define RCC_CFGR_MCOPRE_Msk            (0x7UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x70000000 */
4928 #define RCC_CFGR_MCOPRE                RCC_CFGR_MCOPRE_Msk                     /*!< MCO prescaler [2:0] */
4929 #define RCC_CFGR_MCOPRE_0              (0x1UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x10000000 */
4930 #define RCC_CFGR_MCOPRE_1              (0x2UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x20000000 */
4931 #define RCC_CFGR_MCOPRE_2              (0x4UL << RCC_CFGR_MCOPRE_Pos)          /*!< 0x40000000 */
4932 
4933 /********************  Bit definition for RCC_PLLCFGR register  ***************/
4934 #define RCC_PLLCFGR_PLLSRC_Pos           (0U)
4935 #define RCC_PLLCFGR_PLLSRC_Msk           (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000003 */
4936 #define RCC_PLLCFGR_PLLSRC               RCC_PLLCFGR_PLLSRC_Msk
4937 #define RCC_PLLCFGR_PLLSRC_0             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000001 */
4938 #define RCC_PLLCFGR_PLLSRC_1             (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)     /*!< 0x00000002 */
4939 
4940 #define RCC_PLLCFGR_PLLSRC_NONE          (0x00000000UL)                        /*!< No clock sent to PLL      */
4941 #define RCC_PLLCFGR_PLLSRC_HSI_Pos       (1U)
4942 #define RCC_PLLCFGR_PLLSRC_HSI_Msk       (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
4943 #define RCC_PLLCFGR_PLLSRC_HSI           RCC_PLLCFGR_PLLSRC_HSI_Msk            /*!< HSI source clock selected */
4944 #define RCC_PLLCFGR_PLLSRC_HSE_Pos       (0U)
4945 #define RCC_PLLCFGR_PLLSRC_HSE_Msk       (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
4946 #define RCC_PLLCFGR_PLLSRC_HSE           RCC_PLLCFGR_PLLSRC_HSE_Msk            /*!< HSE source clock selected */
4947 
4948 #define RCC_PLLCFGR_PLLM_Pos             (4U)
4949 #define RCC_PLLCFGR_PLLM_Msk             (0x7UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000070 */
4950 #define RCC_PLLCFGR_PLLM                 RCC_PLLCFGR_PLLM_Msk
4951 #define RCC_PLLCFGR_PLLM_0               (0x1UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000010 */
4952 #define RCC_PLLCFGR_PLLM_1               (0x2UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000020 */
4953 #define RCC_PLLCFGR_PLLM_2               (0x4UL << RCC_PLLCFGR_PLLM_Pos)       /*!< 0x00000040 */
4954 
4955 #define RCC_PLLCFGR_PLLN_Pos             (8U)
4956 #define RCC_PLLCFGR_PLLN_Msk             (0x7FUL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00007F00 */
4957 #define RCC_PLLCFGR_PLLN                 RCC_PLLCFGR_PLLN_Msk
4958 #define RCC_PLLCFGR_PLLN_0               (0x01UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000100 */
4959 #define RCC_PLLCFGR_PLLN_1               (0x02UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000200 */
4960 #define RCC_PLLCFGR_PLLN_2               (0x04UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000400 */
4961 #define RCC_PLLCFGR_PLLN_3               (0x08UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00000800 */
4962 #define RCC_PLLCFGR_PLLN_4               (0x10UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00001000 */
4963 #define RCC_PLLCFGR_PLLN_5               (0x20UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00002000 */
4964 #define RCC_PLLCFGR_PLLN_6               (0x40UL << RCC_PLLCFGR_PLLN_Pos)      /*!< 0x00004000 */
4965 
4966 #define RCC_PLLCFGR_PLLPEN_Pos           (16U)
4967 #define RCC_PLLCFGR_PLLPEN_Msk           (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)     /*!< 0x00010000 */
4968 #define RCC_PLLCFGR_PLLPEN               RCC_PLLCFGR_PLLPEN_Msk
4969 
4970 #define RCC_PLLCFGR_PLLP_Pos              (17U)
4971 #define RCC_PLLCFGR_PLLP_Msk              (0x1FUL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x003E0000 */
4972 #define RCC_PLLCFGR_PLLP                  RCC_PLLCFGR_PLLP_Msk
4973 #define RCC_PLLCFGR_PLLP_0                (0x01UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00020000 */
4974 #define RCC_PLLCFGR_PLLP_1                (0x02UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00040000 */
4975 #define RCC_PLLCFGR_PLLP_2                (0x04UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00080000 */
4976 #define RCC_PLLCFGR_PLLP_3                (0x08UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00100000 */
4977 #define RCC_PLLCFGR_PLLP_4                (0x10UL << RCC_PLLCFGR_PLLP_Pos)     /*!< 0x00200000 */
4978 
4979 #define RCC_PLLCFGR_PLLQEN_Pos           (24U)
4980 #define RCC_PLLCFGR_PLLQEN_Msk           (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)     /*!< 0x01000000 */
4981 #define RCC_PLLCFGR_PLLQEN               RCC_PLLCFGR_PLLQEN_Msk
4982 
4983 #define RCC_PLLCFGR_PLLQ_Pos             (25U)
4984 #define RCC_PLLCFGR_PLLQ_Msk             (0x7UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x0E000000 */
4985 #define RCC_PLLCFGR_PLLQ                 RCC_PLLCFGR_PLLQ_Msk
4986 #define RCC_PLLCFGR_PLLQ_0               (0x1UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x02000000 */
4987 #define RCC_PLLCFGR_PLLQ_1               (0x2UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x04000000 */
4988 #define RCC_PLLCFGR_PLLQ_2               (0x4UL << RCC_PLLCFGR_PLLQ_Pos)       /*!< 0x08000000 */
4989 
4990 #define RCC_PLLCFGR_PLLREN_Pos           (28U)
4991 #define RCC_PLLCFGR_PLLREN_Msk           (0x1UL << RCC_PLLCFGR_PLLREN_Pos)     /*!< 0x10000000 */
4992 #define RCC_PLLCFGR_PLLREN               RCC_PLLCFGR_PLLREN_Msk
4993 
4994 #define RCC_PLLCFGR_PLLR_Pos             (29U)
4995 #define RCC_PLLCFGR_PLLR_Msk             (0x7UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0xE0000000 */
4996 #define RCC_PLLCFGR_PLLR                 RCC_PLLCFGR_PLLR_Msk
4997 #define RCC_PLLCFGR_PLLR_0               (0x1UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x20000000 */
4998 #define RCC_PLLCFGR_PLLR_1               (0x2UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x40000000 */
4999 #define RCC_PLLCFGR_PLLR_2               (0x4UL << RCC_PLLCFGR_PLLR_Pos)       /*!< 0x80000000 */
5000 
5001 /********************  Bit definition for RCC_CIER register  ******************/
5002 #define RCC_CIER_LSIRDYIE_Pos            (0U)
5003 #define RCC_CIER_LSIRDYIE_Msk            (0x1UL << RCC_CIER_LSIRDYIE_Pos)      /*!< 0x00000001 */
5004 #define RCC_CIER_LSIRDYIE                RCC_CIER_LSIRDYIE_Msk
5005 #define RCC_CIER_LSERDYIE_Pos            (1U)
5006 #define RCC_CIER_LSERDYIE_Msk            (0x1UL << RCC_CIER_LSERDYIE_Pos)      /*!< 0x00000002 */
5007 #define RCC_CIER_LSERDYIE                RCC_CIER_LSERDYIE_Msk
5008 #define RCC_CIER_HSIRDYIE_Pos            (3U)
5009 #define RCC_CIER_HSIRDYIE_Msk            (0x1UL << RCC_CIER_HSIRDYIE_Pos)      /*!< 0x00000008 */
5010 #define RCC_CIER_HSIRDYIE                RCC_CIER_HSIRDYIE_Msk
5011 #define RCC_CIER_HSERDYIE_Pos            (4U)
5012 #define RCC_CIER_HSERDYIE_Msk            (0x1UL << RCC_CIER_HSERDYIE_Pos)      /*!< 0x00000010 */
5013 #define RCC_CIER_HSERDYIE                RCC_CIER_HSERDYIE_Msk
5014 #define RCC_CIER_PLLRDYIE_Pos            (5U)
5015 #define RCC_CIER_PLLRDYIE_Msk            (0x1UL << RCC_CIER_PLLRDYIE_Pos)      /*!< 0x00000020 */
5016 #define RCC_CIER_PLLRDYIE                RCC_CIER_PLLRDYIE_Msk
5017 
5018 /********************  Bit definition for RCC_CIFR register  ******************/
5019 #define RCC_CIFR_LSIRDYF_Pos             (0U)
5020 #define RCC_CIFR_LSIRDYF_Msk             (0x1UL << RCC_CIFR_LSIRDYF_Pos)       /*!< 0x00000001 */
5021 #define RCC_CIFR_LSIRDYF                 RCC_CIFR_LSIRDYF_Msk
5022 #define RCC_CIFR_LSERDYF_Pos             (1U)
5023 #define RCC_CIFR_LSERDYF_Msk             (0x1UL << RCC_CIFR_LSERDYF_Pos)       /*!< 0x00000002 */
5024 #define RCC_CIFR_LSERDYF                 RCC_CIFR_LSERDYF_Msk
5025 #define RCC_CIFR_HSIRDYF_Pos             (3U)
5026 #define RCC_CIFR_HSIRDYF_Msk             (0x1UL << RCC_CIFR_HSIRDYF_Pos)       /*!< 0x00000008 */
5027 #define RCC_CIFR_HSIRDYF                 RCC_CIFR_HSIRDYF_Msk
5028 #define RCC_CIFR_HSERDYF_Pos             (4U)
5029 #define RCC_CIFR_HSERDYF_Msk             (0x1UL << RCC_CIFR_HSERDYF_Pos)       /*!< 0x00000010 */
5030 #define RCC_CIFR_HSERDYF                 RCC_CIFR_HSERDYF_Msk
5031 #define RCC_CIFR_PLLRDYF_Pos             (5U)
5032 #define RCC_CIFR_PLLRDYF_Msk             (0x1UL << RCC_CIFR_PLLRDYF_Pos)       /*!< 0x00000020 */
5033 #define RCC_CIFR_PLLRDYF                 RCC_CIFR_PLLRDYF_Msk
5034 #define RCC_CIFR_CSSF_Pos                (8U)
5035 #define RCC_CIFR_CSSF_Msk                (0x1UL << RCC_CIFR_CSSF_Pos)          /*!< 0x00000100 */
5036 #define RCC_CIFR_CSSF                    RCC_CIFR_CSSF_Msk
5037 #define RCC_CIFR_LSECSSF_Pos             (9U)
5038 #define RCC_CIFR_LSECSSF_Msk             (0x1UL << RCC_CIFR_LSECSSF_Pos)       /*!< 0x00000200 */
5039 #define RCC_CIFR_LSECSSF                 RCC_CIFR_LSECSSF_Msk
5040 
5041 /********************  Bit definition for RCC_CICR register  ******************/
5042 #define RCC_CICR_LSIRDYC_Pos             (0U)
5043 #define RCC_CICR_LSIRDYC_Msk             (0x1UL << RCC_CICR_LSIRDYC_Pos)       /*!< 0x00000001 */
5044 #define RCC_CICR_LSIRDYC                 RCC_CICR_LSIRDYC_Msk
5045 #define RCC_CICR_LSERDYC_Pos             (1U)
5046 #define RCC_CICR_LSERDYC_Msk             (0x1UL << RCC_CICR_LSERDYC_Pos)       /*!< 0x00000002 */
5047 #define RCC_CICR_LSERDYC                 RCC_CICR_LSERDYC_Msk
5048 #define RCC_CICR_HSIRDYC_Pos             (3U)
5049 #define RCC_CICR_HSIRDYC_Msk             (0x1UL << RCC_CICR_HSIRDYC_Pos)       /*!< 0x00000008 */
5050 #define RCC_CICR_HSIRDYC                 RCC_CICR_HSIRDYC_Msk
5051 #define RCC_CICR_HSERDYC_Pos             (4U)
5052 #define RCC_CICR_HSERDYC_Msk             (0x1UL << RCC_CICR_HSERDYC_Pos)       /*!< 0x00000010 */
5053 #define RCC_CICR_HSERDYC                 RCC_CICR_HSERDYC_Msk
5054 #define RCC_CICR_PLLRDYC_Pos             (5U)
5055 #define RCC_CICR_PLLRDYC_Msk             (0x1UL << RCC_CICR_PLLRDYC_Pos)       /*!< 0x00000020 */
5056 #define RCC_CICR_PLLRDYC                 RCC_CICR_PLLRDYC_Msk
5057 #define RCC_CICR_CSSC_Pos                (8U)
5058 #define RCC_CICR_CSSC_Msk                (0x1UL << RCC_CICR_CSSC_Pos)          /*!< 0x00000100 */
5059 #define RCC_CICR_CSSC                    RCC_CICR_CSSC_Msk
5060 #define RCC_CICR_LSECSSC_Pos             (9U)
5061 #define RCC_CICR_LSECSSC_Msk             (0x1UL << RCC_CICR_LSECSSC_Pos)       /*!< 0x00000200 */
5062 #define RCC_CICR_LSECSSC                 RCC_CICR_LSECSSC_Msk
5063 
5064 /********************  Bit definition for RCC_IOPRSTR register  ****************/
5065 #define RCC_IOPRSTR_GPIOARST_Pos         (0U)
5066 #define RCC_IOPRSTR_GPIOARST_Msk         (0x1UL << RCC_IOPRSTR_GPIOARST_Pos)   /*!< 0x00000001 */
5067 #define RCC_IOPRSTR_GPIOARST             RCC_IOPRSTR_GPIOARST_Msk
5068 #define RCC_IOPRSTR_GPIOBRST_Pos         (1U)
5069 #define RCC_IOPRSTR_GPIOBRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos)   /*!< 0x00000002 */
5070 #define RCC_IOPRSTR_GPIOBRST             RCC_IOPRSTR_GPIOBRST_Msk
5071 #define RCC_IOPRSTR_GPIOCRST_Pos         (2U)
5072 #define RCC_IOPRSTR_GPIOCRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos)   /*!< 0x00000004 */
5073 #define RCC_IOPRSTR_GPIOCRST             RCC_IOPRSTR_GPIOCRST_Msk
5074 #define RCC_IOPRSTR_GPIODRST_Pos         (3U)
5075 #define RCC_IOPRSTR_GPIODRST_Msk         (0x1UL << RCC_IOPRSTR_GPIODRST_Pos)   /*!< 0x00000008 */
5076 #define RCC_IOPRSTR_GPIODRST             RCC_IOPRSTR_GPIODRST_Msk
5077 #define RCC_IOPRSTR_GPIOFRST_Pos         (5U)
5078 #define RCC_IOPRSTR_GPIOFRST_Msk         (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos)   /*!< 0x00000020 */
5079 #define RCC_IOPRSTR_GPIOFRST             RCC_IOPRSTR_GPIOFRST_Msk
5080 
5081 /********************  Bit definition for RCC_AHBRSTR register  ***************/
5082 #define RCC_AHBRSTR_DMA1RST_Pos          (0U)
5083 #define RCC_AHBRSTR_DMA1RST_Msk          (0x1UL << RCC_AHBRSTR_DMA1RST_Pos)    /*!< 0x00000001 */
5084 #define RCC_AHBRSTR_DMA1RST              RCC_AHBRSTR_DMA1RST_Msk
5085 #define RCC_AHBRSTR_FLASHRST_Pos         (8U)
5086 #define RCC_AHBRSTR_FLASHRST_Msk         (0x1UL << RCC_AHBRSTR_FLASHRST_Pos)   /*!< 0x00000100 */
5087 #define RCC_AHBRSTR_FLASHRST             RCC_AHBRSTR_FLASHRST_Msk
5088 #define RCC_AHBRSTR_CRCRST_Pos           (12U)
5089 #define RCC_AHBRSTR_CRCRST_Msk           (0x1UL << RCC_AHBRSTR_CRCRST_Pos)     /*!< 0x00001000 */
5090 #define RCC_AHBRSTR_CRCRST               RCC_AHBRSTR_CRCRST_Msk
5091 
5092 /********************  Bit definition for RCC_APBRSTR1 register  **************/
5093 #define RCC_APBRSTR1_TIM2RST_Pos         (0U)
5094 #define RCC_APBRSTR1_TIM2RST_Msk         (0x1UL << RCC_APBRSTR1_TIM2RST_Pos)   /*!< 0x00000001 */
5095 #define RCC_APBRSTR1_TIM2RST             RCC_APBRSTR1_TIM2RST_Msk
5096 #define RCC_APBRSTR1_TIM3RST_Pos         (1U)
5097 #define RCC_APBRSTR1_TIM3RST_Msk         (0x1UL << RCC_APBRSTR1_TIM3RST_Pos)   /*!< 0x00000002 */
5098 #define RCC_APBRSTR1_TIM3RST             RCC_APBRSTR1_TIM3RST_Msk
5099 #define RCC_APBRSTR1_TIM6RST_Pos         (4U)
5100 #define RCC_APBRSTR1_TIM6RST_Msk         (0x1UL << RCC_APBRSTR1_TIM6RST_Pos)   /*!< 0x00000010 */
5101 #define RCC_APBRSTR1_TIM6RST             RCC_APBRSTR1_TIM6RST_Msk
5102 #define RCC_APBRSTR1_TIM7RST_Pos         (5U)
5103 #define RCC_APBRSTR1_TIM7RST_Msk         (0x1UL << RCC_APBRSTR1_TIM7RST_Pos)   /*!< 0x00000020 */
5104 #define RCC_APBRSTR1_TIM7RST             RCC_APBRSTR1_TIM7RST_Msk
5105 #define RCC_APBRSTR1_SPI2RST_Pos         (14U)
5106 #define RCC_APBRSTR1_SPI2RST_Msk         (0x1UL << RCC_APBRSTR1_SPI2RST_Pos)   /*!< 0x00004000 */
5107 #define RCC_APBRSTR1_SPI2RST             RCC_APBRSTR1_SPI2RST_Msk
5108 #define RCC_APBRSTR1_USART2RST_Pos       (17U)
5109 #define RCC_APBRSTR1_USART2RST_Msk       (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
5110 #define RCC_APBRSTR1_USART2RST           RCC_APBRSTR1_USART2RST_Msk
5111 #define RCC_APBRSTR1_USART3RST_Pos       (18U)
5112 #define RCC_APBRSTR1_USART3RST_Msk       (0x1UL << RCC_APBRSTR1_USART3RST_Pos) /*!< 0x00040000 */
5113 #define RCC_APBRSTR1_USART3RST           RCC_APBRSTR1_USART3RST_Msk
5114 #define RCC_APBRSTR1_USART4RST_Pos       (19U)
5115 #define RCC_APBRSTR1_USART4RST_Msk       (0x1UL << RCC_APBRSTR1_USART4RST_Pos) /*!< 0x00080000 */
5116 #define RCC_APBRSTR1_USART4RST           RCC_APBRSTR1_USART4RST_Msk
5117 #define RCC_APBRSTR1_LPUART1RST_Pos      (20U)
5118 #define RCC_APBRSTR1_LPUART1RST_Msk      (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos) /*!< 0x00100000 */
5119 #define RCC_APBRSTR1_LPUART1RST          RCC_APBRSTR1_LPUART1RST_Msk
5120 #define RCC_APBRSTR1_I2C1RST_Pos         (21U)
5121 #define RCC_APBRSTR1_I2C1RST_Msk         (0x1UL << RCC_APBRSTR1_I2C1RST_Pos)    /*!< 0x00200000 */
5122 #define RCC_APBRSTR1_I2C1RST             RCC_APBRSTR1_I2C1RST_Msk
5123 #define RCC_APBRSTR1_I2C2RST_Pos         (22U)
5124 #define RCC_APBRSTR1_I2C2RST_Msk         (0x1UL << RCC_APBRSTR1_I2C2RST_Pos)    /*!< 0x00400000 */
5125 #define RCC_APBRSTR1_I2C2RST             RCC_APBRSTR1_I2C2RST_Msk
5126 #define RCC_APBRSTR1_CECRST_Pos          (24U)
5127 #define RCC_APBRSTR1_CECRST_Msk          (0x1UL << RCC_APBRSTR1_CECRST_Pos)     /*!< 0x01000000 */
5128 #define RCC_APBRSTR1_CECRST              RCC_APBRSTR1_CECRST_Msk
5129 #define RCC_APBRSTR1_UCPD1RST_Pos        (25U)
5130 #define RCC_APBRSTR1_UCPD1RST_Msk        (0x1UL << RCC_APBRSTR1_UCPD1RST_Pos)   /*!< 0x02000000 */
5131 #define RCC_APBRSTR1_UCPD1RST            RCC_APBRSTR1_UCPD1RST_Msk
5132 #define RCC_APBRSTR1_UCPD2RST_Pos        (26U)
5133 #define RCC_APBRSTR1_UCPD2RST_Msk        (0x1UL << RCC_APBRSTR1_UCPD2RST_Pos)   /*!< 0x04000000 */
5134 #define RCC_APBRSTR1_UCPD2RST            RCC_APBRSTR1_UCPD2RST_Msk
5135 #define RCC_APBRSTR1_DBGRST_Pos          (27U)
5136 #define RCC_APBRSTR1_DBGRST_Msk          (0x1UL << RCC_APBRSTR1_DBGRST_Pos)     /*!< 0x08000000 */
5137 #define RCC_APBRSTR1_DBGRST              RCC_APBRSTR1_DBGRST_Msk
5138 #define RCC_APBRSTR1_PWRRST_Pos          (28U)
5139 #define RCC_APBRSTR1_PWRRST_Msk          (0x1UL << RCC_APBRSTR1_PWRRST_Pos)     /*!< 0x10000000 */
5140 #define RCC_APBRSTR1_PWRRST              RCC_APBRSTR1_PWRRST_Msk
5141 #define RCC_APBRSTR1_DAC1RST_Pos         (29U)
5142 #define RCC_APBRSTR1_DAC1RST_Msk         (0x1UL << RCC_APBRSTR1_DAC1RST_Pos)    /*!< 0x20000000 */
5143 #define RCC_APBRSTR1_DAC1RST             RCC_APBRSTR1_DAC1RST_Msk
5144 #define RCC_APBRSTR1_LPTIM2RST_Pos       (30U)
5145 #define RCC_APBRSTR1_LPTIM2RST_Msk       (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos)  /*!< 0x40000000 */
5146 #define RCC_APBRSTR1_LPTIM2RST           RCC_APBRSTR1_LPTIM2RST_Msk
5147 #define RCC_APBRSTR1_LPTIM1RST_Pos       (31U)
5148 #define RCC_APBRSTR1_LPTIM1RST_Msk       (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos)  /*!< 0x80000000 */
5149 #define RCC_APBRSTR1_LPTIM1RST           RCC_APBRSTR1_LPTIM1RST_Msk
5150 
5151 /********************  Bit definition for RCC_APBRSTR2 register  **************/
5152 #define RCC_APBRSTR2_SYSCFGRST_Pos       (0U)
5153 #define RCC_APBRSTR2_SYSCFGRST_Msk       (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos)  /*!< 0x00000001 */
5154 #define RCC_APBRSTR2_SYSCFGRST           RCC_APBRSTR2_SYSCFGRST_Msk
5155 #define RCC_APBRSTR2_TIM1RST_Pos         (11U)
5156 #define RCC_APBRSTR2_TIM1RST_Msk         (0x1UL << RCC_APBRSTR2_TIM1RST_Pos)    /*!< 0x00000800 */
5157 #define RCC_APBRSTR2_TIM1RST             RCC_APBRSTR2_TIM1RST_Msk
5158 #define RCC_APBRSTR2_SPI1RST_Pos         (12U)
5159 #define RCC_APBRSTR2_SPI1RST_Msk         (0x1UL << RCC_APBRSTR2_SPI1RST_Pos)    /*!< 0x00001000 */
5160 #define RCC_APBRSTR2_SPI1RST             RCC_APBRSTR2_SPI1RST_Msk
5161 #define RCC_APBRSTR2_USART1RST_Pos       (14U)
5162 #define RCC_APBRSTR2_USART1RST_Msk       (0x1UL << RCC_APBRSTR2_USART1RST_Pos)  /*!< 0x00004000 */
5163 #define RCC_APBRSTR2_USART1RST           RCC_APBRSTR2_USART1RST_Msk
5164 #define RCC_APBRSTR2_TIM14RST_Pos        (15U)
5165 #define RCC_APBRSTR2_TIM14RST_Msk        (0x1UL << RCC_APBRSTR2_TIM14RST_Pos)   /*!< 0x00008000 */
5166 #define RCC_APBRSTR2_TIM14RST            RCC_APBRSTR2_TIM14RST_Msk
5167 #define RCC_APBRSTR2_TIM15RST_Pos        (16U)
5168 #define RCC_APBRSTR2_TIM15RST_Msk        (0x1UL << RCC_APBRSTR2_TIM15RST_Pos)   /*!< 0x00010000 */
5169 #define RCC_APBRSTR2_TIM15RST            RCC_APBRSTR2_TIM15RST_Msk
5170 #define RCC_APBRSTR2_TIM16RST_Pos        (17U)
5171 #define RCC_APBRSTR2_TIM16RST_Msk        (0x1UL << RCC_APBRSTR2_TIM16RST_Pos)   /*!< 0x00020000 */
5172 #define RCC_APBRSTR2_TIM16RST            RCC_APBRSTR2_TIM16RST_Msk
5173 #define RCC_APBRSTR2_TIM17RST_Pos        (18U)
5174 #define RCC_APBRSTR2_TIM17RST_Msk        (0x1UL << RCC_APBRSTR2_TIM17RST_Pos)   /*!< 0x00040000 */
5175 #define RCC_APBRSTR2_TIM17RST            RCC_APBRSTR2_TIM17RST_Msk
5176 #define RCC_APBRSTR2_ADCRST_Pos          (20U)
5177 #define RCC_APBRSTR2_ADCRST_Msk          (0x1UL << RCC_APBRSTR2_ADCRST_Pos)     /*!< 0x00100000 */
5178 #define RCC_APBRSTR2_ADCRST              RCC_APBRSTR2_ADCRST_Msk
5179 
5180 /********************  Bit definition for RCC_IOPENR register  ****************/
5181 #define RCC_IOPENR_GPIOAEN_Pos           (0U)
5182 #define RCC_IOPENR_GPIOAEN_Msk           (0x1UL << RCC_IOPENR_GPIOAEN_Pos)      /*!< 0x00000001 */
5183 #define RCC_IOPENR_GPIOAEN               RCC_IOPENR_GPIOAEN_Msk
5184 #define RCC_IOPENR_GPIOBEN_Pos           (1U)
5185 #define RCC_IOPENR_GPIOBEN_Msk           (0x1UL << RCC_IOPENR_GPIOBEN_Pos)      /*!< 0x00000002 */
5186 #define RCC_IOPENR_GPIOBEN               RCC_IOPENR_GPIOBEN_Msk
5187 #define RCC_IOPENR_GPIOCEN_Pos           (2U)
5188 #define RCC_IOPENR_GPIOCEN_Msk           (0x1UL << RCC_IOPENR_GPIOCEN_Pos)      /*!< 0x00000004 */
5189 #define RCC_IOPENR_GPIOCEN               RCC_IOPENR_GPIOCEN_Msk
5190 #define RCC_IOPENR_GPIODEN_Pos           (3U)
5191 #define RCC_IOPENR_GPIODEN_Msk           (0x1UL << RCC_IOPENR_GPIODEN_Pos)      /*!< 0x00000008 */
5192 #define RCC_IOPENR_GPIODEN               RCC_IOPENR_GPIODEN_Msk
5193 #define RCC_IOPENR_GPIOFEN_Pos           (5U)
5194 #define RCC_IOPENR_GPIOFEN_Msk           (0x1UL << RCC_IOPENR_GPIOFEN_Pos)      /*!< 0x00000020 */
5195 #define RCC_IOPENR_GPIOFEN               RCC_IOPENR_GPIOFEN_Msk
5196 
5197 /********************  Bit definition for RCC_AHBENR register  ****************/
5198 #define RCC_AHBENR_DMA1EN_Pos            (0U)
5199 #define RCC_AHBENR_DMA1EN_Msk            (0x1UL << RCC_AHBENR_DMA1EN_Pos)       /*!< 0x00000001 */
5200 #define RCC_AHBENR_DMA1EN                RCC_AHBENR_DMA1EN_Msk
5201 #define RCC_AHBENR_FLASHEN_Pos           (8U)
5202 #define RCC_AHBENR_FLASHEN_Msk           (0x1UL << RCC_AHBENR_FLASHEN_Pos)      /*!< 0x00000100 */
5203 #define RCC_AHBENR_FLASHEN               RCC_AHBENR_FLASHEN_Msk
5204 #define RCC_AHBENR_CRCEN_Pos             (12U)
5205 #define RCC_AHBENR_CRCEN_Msk             (0x1UL << RCC_AHBENR_CRCEN_Pos)        /*!< 0x00001000 */
5206 #define RCC_AHBENR_CRCEN                 RCC_AHBENR_CRCEN_Msk
5207 
5208 /********************  Bit definition for RCC_APBENR1 register  ***************/
5209 #define RCC_APBENR1_TIM2EN_Pos           (0U)
5210 #define RCC_APBENR1_TIM2EN_Msk           (0x1UL << RCC_APBENR1_TIM2EN_Pos)      /*!< 0x00000001 */
5211 #define RCC_APBENR1_TIM2EN               RCC_APBENR1_TIM2EN_Msk
5212 #define RCC_APBENR1_TIM3EN_Pos           (1U)
5213 #define RCC_APBENR1_TIM3EN_Msk           (0x1UL << RCC_APBENR1_TIM3EN_Pos)      /*!< 0x00000002 */
5214 #define RCC_APBENR1_TIM3EN               RCC_APBENR1_TIM3EN_Msk
5215 #define RCC_APBENR1_TIM6EN_Pos           (4U)
5216 #define RCC_APBENR1_TIM6EN_Msk           (0x1UL << RCC_APBENR1_TIM6EN_Pos)      /*!< 0x00000010 */
5217 #define RCC_APBENR1_TIM6EN               RCC_APBENR1_TIM6EN_Msk
5218 #define RCC_APBENR1_TIM7EN_Pos           (5U)
5219 #define RCC_APBENR1_TIM7EN_Msk           (0x1UL << RCC_APBENR1_TIM7EN_Pos)      /*!< 0x00000020 */
5220 #define RCC_APBENR1_TIM7EN               RCC_APBENR1_TIM7EN_Msk
5221 #define RCC_APBENR1_RTCAPBEN_Pos         (10U)
5222 #define RCC_APBENR1_RTCAPBEN_Msk         (0x1UL << RCC_APBENR1_RTCAPBEN_Pos)    /*!< 0x00000400 */
5223 #define RCC_APBENR1_RTCAPBEN             RCC_APBENR1_RTCAPBEN_Msk
5224 #define RCC_APBENR1_WWDGEN_Pos           (11U)
5225 #define RCC_APBENR1_WWDGEN_Msk           (0x1UL << RCC_APBENR1_WWDGEN_Pos)      /*!< 0x00000800 */
5226 #define RCC_APBENR1_WWDGEN               RCC_APBENR1_WWDGEN_Msk
5227 #define RCC_APBENR1_SPI2EN_Pos           (14U)
5228 #define RCC_APBENR1_SPI2EN_Msk           (0x1UL << RCC_APBENR1_SPI2EN_Pos)      /*!< 0x00004000 */
5229 #define RCC_APBENR1_SPI2EN               RCC_APBENR1_SPI2EN_Msk
5230 #define RCC_APBENR1_USART2EN_Pos         (17U)
5231 #define RCC_APBENR1_USART2EN_Msk         (0x1UL << RCC_APBENR1_USART2EN_Pos)    /*!< 0x00020000 */
5232 #define RCC_APBENR1_USART2EN             RCC_APBENR1_USART2EN_Msk
5233 #define RCC_APBENR1_USART3EN_Pos         (18U)
5234 #define RCC_APBENR1_USART3EN_Msk         (0x1UL << RCC_APBENR1_USART3EN_Pos)    /*!< 0x00040000 */
5235 #define RCC_APBENR1_USART3EN             RCC_APBENR1_USART3EN_Msk
5236 #define RCC_APBENR1_USART4EN_Pos         (19U)
5237 #define RCC_APBENR1_USART4EN_Msk         (0x1UL << RCC_APBENR1_USART4EN_Pos)    /*!< 0x00080000 */
5238 #define RCC_APBENR1_USART4EN             RCC_APBENR1_USART4EN_Msk
5239 #define RCC_APBENR1_LPUART1EN_Pos        (20U)
5240 #define RCC_APBENR1_LPUART1EN_Msk        (0x1UL << RCC_APBENR1_LPUART1EN_Pos)   /*!< 0x00100000 */
5241 #define RCC_APBENR1_LPUART1EN            RCC_APBENR1_LPUART1EN_Msk
5242 #define RCC_APBENR1_I2C1EN_Pos           (21U)
5243 #define RCC_APBENR1_I2C1EN_Msk           (0x1UL << RCC_APBENR1_I2C1EN_Pos)      /*!< 0x00200000 */
5244 #define RCC_APBENR1_I2C1EN               RCC_APBENR1_I2C1EN_Msk
5245 #define RCC_APBENR1_I2C2EN_Pos           (22U)
5246 #define RCC_APBENR1_I2C2EN_Msk           (0x1UL << RCC_APBENR1_I2C2EN_Pos)      /*!< 0x00400000 */
5247 #define RCC_APBENR1_I2C2EN               RCC_APBENR1_I2C2EN_Msk
5248 #define RCC_APBENR1_CECEN_Pos            (24U)
5249 #define RCC_APBENR1_CECEN_Msk            (0x1UL << RCC_APBENR1_CECEN_Pos)       /*!< 0x01000000 */
5250 #define RCC_APBENR1_CECEN                RCC_APBENR1_CECEN_Msk
5251 #define RCC_APBENR1_UCPD1EN_Pos          (25U)
5252 #define RCC_APBENR1_UCPD1EN_Msk          (0x1UL << RCC_APBENR1_UCPD1EN_Pos)     /*!< 0x02000000 */
5253 #define RCC_APBENR1_UCPD1EN              RCC_APBENR1_UCPD1EN_Msk
5254 #define RCC_APBENR1_UCPD2EN_Pos          (26U)
5255 #define RCC_APBENR1_UCPD2EN_Msk          (0x1UL << RCC_APBENR1_UCPD2EN_Pos)     /*!< 0x04000000 */
5256 #define RCC_APBENR1_UCPD2EN              RCC_APBENR1_UCPD2EN_Msk
5257 #define RCC_APBENR1_DBGEN_Pos            (27U)
5258 #define RCC_APBENR1_DBGEN_Msk            (0x1UL << RCC_APBENR1_DBGEN_Pos)       /*!< 0x08000000 */
5259 #define RCC_APBENR1_DBGEN                RCC_APBENR1_DBGEN_Msk
5260 #define RCC_APBENR1_PWREN_Pos            (28U)
5261 #define RCC_APBENR1_PWREN_Msk            (0x1UL << RCC_APBENR1_PWREN_Pos)       /*!< 0x10000000 */
5262 #define RCC_APBENR1_PWREN                RCC_APBENR1_PWREN_Msk
5263 #define RCC_APBENR1_DAC1EN_Pos           (29U)
5264 #define RCC_APBENR1_DAC1EN_Msk           (0x1UL << RCC_APBENR1_DAC1EN_Pos)      /*!< 0x20000000 */
5265 #define RCC_APBENR1_DAC1EN               RCC_APBENR1_DAC1EN_Msk
5266 #define RCC_APBENR1_LPTIM2EN_Pos         (30U)
5267 #define RCC_APBENR1_LPTIM2EN_Msk         (0x1UL << RCC_APBENR1_LPTIM2EN_Pos)    /*!< 0x40000000 */
5268 #define RCC_APBENR1_LPTIM2EN             RCC_APBENR1_LPTIM2EN_Msk
5269 #define RCC_APBENR1_LPTIM1EN_Pos         (31U)
5270 #define RCC_APBENR1_LPTIM1EN_Msk         (0x1UL << RCC_APBENR1_LPTIM1EN_Pos)    /*!< 0x80000000 */
5271 #define RCC_APBENR1_LPTIM1EN             RCC_APBENR1_LPTIM1EN_Msk
5272 
5273 /********************  Bit definition for RCC_APBENR2 register  **************/
5274 #define RCC_APBENR2_SYSCFGEN_Pos         (0U)
5275 #define RCC_APBENR2_SYSCFGEN_Msk         (0x1UL << RCC_APBENR2_SYSCFGEN_Pos)    /*!< 0x00000001 */
5276 #define RCC_APBENR2_SYSCFGEN             RCC_APBENR2_SYSCFGEN_Msk
5277 #define RCC_APBENR2_TIM1EN_Pos           (11U)
5278 #define RCC_APBENR2_TIM1EN_Msk           (0x1UL << RCC_APBENR2_TIM1EN_Pos)      /*!< 0x00000800 */
5279 #define RCC_APBENR2_TIM1EN               RCC_APBENR2_TIM1EN_Msk
5280 #define RCC_APBENR2_SPI1EN_Pos           (12U)
5281 #define RCC_APBENR2_SPI1EN_Msk           (0x1UL << RCC_APBENR2_SPI1EN_Pos)      /*!< 0x00001000 */
5282 #define RCC_APBENR2_SPI1EN               RCC_APBENR2_SPI1EN_Msk
5283 #define RCC_APBENR2_USART1EN_Pos         (14U)
5284 #define RCC_APBENR2_USART1EN_Msk         (0x1UL << RCC_APBENR2_USART1EN_Pos)    /*!< 0x00004000 */
5285 #define RCC_APBENR2_USART1EN             RCC_APBENR2_USART1EN_Msk
5286 #define RCC_APBENR2_TIM14EN_Pos          (15U)
5287 #define RCC_APBENR2_TIM14EN_Msk          (0x1UL << RCC_APBENR2_TIM14EN_Pos)     /*!< 0x00008000 */
5288 #define RCC_APBENR2_TIM14EN              RCC_APBENR2_TIM14EN_Msk
5289 #define RCC_APBENR2_TIM15EN_Pos          (16U)
5290 #define RCC_APBENR2_TIM15EN_Msk          (0x1UL << RCC_APBENR2_TIM15EN_Pos)     /*!< 0x00010000 */
5291 #define RCC_APBENR2_TIM15EN              RCC_APBENR2_TIM15EN_Msk
5292 #define RCC_APBENR2_TIM16EN_Pos          (17U)
5293 #define RCC_APBENR2_TIM16EN_Msk          (0x1UL << RCC_APBENR2_TIM16EN_Pos)     /*!< 0x00020000 */
5294 #define RCC_APBENR2_TIM16EN              RCC_APBENR2_TIM16EN_Msk
5295 #define RCC_APBENR2_TIM17EN_Pos          (18U)
5296 #define RCC_APBENR2_TIM17EN_Msk          (0x1UL << RCC_APBENR2_TIM17EN_Pos)     /*!< 0x00040000 */
5297 #define RCC_APBENR2_TIM17EN              RCC_APBENR2_TIM17EN_Msk
5298 #define RCC_APBENR2_ADCEN_Pos            (20U)
5299 #define RCC_APBENR2_ADCEN_Msk            (0x1UL << RCC_APBENR2_ADCEN_Pos)       /*!< 0x00100000 */
5300 #define RCC_APBENR2_ADCEN                RCC_APBENR2_ADCEN_Msk
5301 
5302 /********************  Bit definition for RCC_IOPSMENR register  *************/
5303 #define RCC_IOPSMENR_GPIOASMEN_Pos       (0U)
5304 #define RCC_IOPSMENR_GPIOASMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos)  /*!< 0x00000001 */
5305 #define RCC_IOPSMENR_GPIOASMEN           RCC_IOPSMENR_GPIOASMEN_Msk
5306 #define RCC_IOPSMENR_GPIOBSMEN_Pos       (1U)
5307 #define RCC_IOPSMENR_GPIOBSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos)  /*!< 0x00000002 */
5308 #define RCC_IOPSMENR_GPIOBSMEN           RCC_IOPSMENR_GPIOBSMEN_Msk
5309 #define RCC_IOPSMENR_GPIOCSMEN_Pos       (2U)
5310 #define RCC_IOPSMENR_GPIOCSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos)  /*!< 0x00000004 */
5311 #define RCC_IOPSMENR_GPIOCSMEN           RCC_IOPSMENR_GPIOCSMEN_Msk
5312 #define RCC_IOPSMENR_GPIODSMEN_Pos       (3U)
5313 #define RCC_IOPSMENR_GPIODSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos)  /*!< 0x00000008 */
5314 #define RCC_IOPSMENR_GPIODSMEN           RCC_IOPSMENR_GPIODSMEN_Msk
5315 #define RCC_IOPSMENR_GPIOFSMEN_Pos       (5U)
5316 #define RCC_IOPSMENR_GPIOFSMEN_Msk       (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos)  /*!< 0x00000020 */
5317 #define RCC_IOPSMENR_GPIOFSMEN           RCC_IOPSMENR_GPIOFSMEN_Msk
5318 
5319 /********************  Bit definition for RCC_AHBSMENR register  *************/
5320 #define RCC_AHBSMENR_DMA1SMEN_Pos        (0U)
5321 #define RCC_AHBSMENR_DMA1SMEN_Msk        (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos)   /*!< 0x00000001 */
5322 #define RCC_AHBSMENR_DMA1SMEN            RCC_AHBSMENR_DMA1SMEN_Msk
5323 #define RCC_AHBSMENR_FLASHSMEN_Pos       (8U)
5324 #define RCC_AHBSMENR_FLASHSMEN_Msk       (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos)  /*!< 0x00000100 */
5325 #define RCC_AHBSMENR_FLASHSMEN           RCC_AHBSMENR_FLASHSMEN_Msk
5326 #define RCC_AHBSMENR_SRAMSMEN_Pos        (9U)
5327 #define RCC_AHBSMENR_SRAMSMEN_Msk        (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos)   /*!< 0x00000200 */
5328 #define RCC_AHBSMENR_SRAMSMEN            RCC_AHBSMENR_SRAMSMEN_Msk
5329 #define RCC_AHBSMENR_CRCSMEN_Pos         (12U)
5330 #define RCC_AHBSMENR_CRCSMEN_Msk         (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos)    /*!< 0x00001000 */
5331 #define RCC_AHBSMENR_CRCSMEN             RCC_AHBSMENR_CRCSMEN_Msk
5332 
5333 /********************  Bit definition for RCC_APBSMENR1 register  *************/
5334 #define RCC_APBSMENR1_TIM2SMEN_Pos       (0U)
5335 #define RCC_APBSMENR1_TIM2SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos)  /*!< 0x00000001 */
5336 #define RCC_APBSMENR1_TIM2SMEN           RCC_APBSMENR1_TIM2SMEN_Msk
5337 #define RCC_APBSMENR1_TIM3SMEN_Pos       (1U)
5338 #define RCC_APBSMENR1_TIM3SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos)  /*!< 0x00000002 */
5339 #define RCC_APBSMENR1_TIM3SMEN           RCC_APBSMENR1_TIM3SMEN_Msk
5340 #define RCC_APBSMENR1_TIM6SMEN_Pos       (4U)
5341 #define RCC_APBSMENR1_TIM6SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM6SMEN_Pos)  /*!< 0x00000010 */
5342 #define RCC_APBSMENR1_TIM6SMEN           RCC_APBSMENR1_TIM6SMEN_Msk
5343 #define RCC_APBSMENR1_TIM7SMEN_Pos       (5U)
5344 #define RCC_APBSMENR1_TIM7SMEN_Msk       (0x1UL << RCC_APBSMENR1_TIM7SMEN_Pos)  /*!< 0x00000020 */
5345 #define RCC_APBSMENR1_TIM7SMEN           RCC_APBSMENR1_TIM7SMEN_Msk
5346 #define RCC_APBSMENR1_RTCAPBSMEN_Pos     (10U)
5347 #define RCC_APBSMENR1_RTCAPBSMEN_Msk     (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
5348 #define RCC_APBSMENR1_RTCAPBSMEN         RCC_APBSMENR1_RTCAPBSMEN_Msk
5349 #define RCC_APBSMENR1_WWDGSMEN_Pos       (11U)
5350 #define RCC_APBSMENR1_WWDGSMEN_Msk       (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos)   /*!< 0x00000800 */
5351 #define RCC_APBSMENR1_WWDGSMEN           RCC_APBSMENR1_WWDGSMEN_Msk
5352 #define RCC_APBSMENR1_SPI2SMEN_Pos       (14U)
5353 #define RCC_APBSMENR1_SPI2SMEN_Msk       (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos)   /*!< 0x00004000 */
5354 #define RCC_APBSMENR1_SPI2SMEN           RCC_APBSMENR1_SPI2SMEN_Msk
5355 #define RCC_APBSMENR1_USART2SMEN_Pos     (17U)
5356 #define RCC_APBSMENR1_USART2SMEN_Msk     (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
5357 #define RCC_APBSMENR1_USART2SMEN         RCC_APBSMENR1_USART2SMEN_Msk
5358 #define RCC_APBSMENR1_USART3SMEN_Pos     (18U)
5359 #define RCC_APBSMENR1_USART3SMEN_Msk     (0x1UL << RCC_APBSMENR1_USART3SMEN_Pos) /*!< 0x00040000 */
5360 #define RCC_APBSMENR1_USART3SMEN         RCC_APBSMENR1_USART3SMEN_Msk
5361 #define RCC_APBSMENR1_USART4SMEN_Pos     (19U)
5362 #define RCC_APBSMENR1_USART4SMEN_Msk     (0x1UL << RCC_APBSMENR1_USART4SMEN_Pos) /*!< 0x00080000 */
5363 #define RCC_APBSMENR1_USART4SMEN         RCC_APBSMENR1_USART4SMEN_Msk
5364 #define RCC_APBSMENR1_LPUART1SMEN_Pos    (20U)
5365 #define RCC_APBSMENR1_LPUART1SMEN_Msk    (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos) /*!< 0x00100000 */
5366 #define RCC_APBSMENR1_LPUART1SMEN        RCC_APBSMENR1_LPUART1SMEN_Msk
5367 #define RCC_APBSMENR1_I2C1SMEN_Pos       (21U)
5368 #define RCC_APBSMENR1_I2C1SMEN_Msk       (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos)   /*!< 0x00200000 */
5369 #define RCC_APBSMENR1_I2C1SMEN           RCC_APBSMENR1_I2C1SMEN_Msk
5370 #define RCC_APBSMENR1_I2C2SMEN_Pos       (22U)
5371 #define RCC_APBSMENR1_I2C2SMEN_Msk       (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos)   /*!< 0x00400000 */
5372 #define RCC_APBSMENR1_I2C2SMEN           RCC_APBSMENR1_I2C2SMEN_Msk
5373 #define RCC_APBSMENR1_CECSMEN_Pos        (24U)
5374 #define RCC_APBSMENR1_CECSMEN_Msk        (0x1UL << RCC_APBSMENR1_CECSMEN_Pos)    /*!< 0x01000000 */
5375 #define RCC_APBSMENR1_CECSMEN            RCC_APBSMENR1_CECSMEN_Msk
5376 #define RCC_APBSMENR1_UCPD1SMEN_Pos      (25U)
5377 #define RCC_APBSMENR1_UCPD1SMEN_Msk      (0x1UL << RCC_APBSMENR1_UCPD1SMEN_Pos)  /*!< 0x02000000 */
5378 #define RCC_APBSMENR1_UCPD1SMEN          RCC_APBSMENR1_UCPD1SMEN_Msk
5379 #define RCC_APBSMENR1_UCPD2SMEN_Pos      (26U)
5380 #define RCC_APBSMENR1_UCPD2SMEN_Msk      (0x1UL << RCC_APBSMENR1_UCPD2SMEN_Pos)  /*!< 0x04000000 */
5381 #define RCC_APBSMENR1_UCPD2SMEN          RCC_APBSMENR1_UCPD2SMEN_Msk
5382 #define RCC_APBSMENR1_DBGSMEN_Pos        (27U)
5383 #define RCC_APBSMENR1_DBGSMEN_Msk        (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos)    /*!< 0x08000000 */
5384 #define RCC_APBSMENR1_DBGSMEN            RCC_APBSMENR1_DBGSMEN_Msk
5385 #define RCC_APBSMENR1_PWRSMEN_Pos        (28U)
5386 #define RCC_APBSMENR1_PWRSMEN_Msk        (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos)    /*!< 0x10000000 */
5387 #define RCC_APBSMENR1_PWRSMEN            RCC_APBSMENR1_PWRSMEN_Msk
5388 #define RCC_APBSMENR1_DAC1SMEN_Pos       (29U)
5389 #define RCC_APBSMENR1_DAC1SMEN_Msk       (0x1UL << RCC_APBSMENR1_DAC1SMEN_Pos)   /*!< 0x20000000 */
5390 #define RCC_APBSMENR1_DAC1SMEN           RCC_APBSMENR1_DAC1SMEN_Msk
5391 #define RCC_APBSMENR1_LPTIM2SMEN_Pos     (30U)
5392 #define RCC_APBSMENR1_LPTIM2SMEN_Msk     (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
5393 #define RCC_APBSMENR1_LPTIM2SMEN         RCC_APBSMENR1_LPTIM2SMEN_Msk
5394 #define RCC_APBSMENR1_LPTIM1SMEN_Pos     (31U)
5395 #define RCC_APBSMENR1_LPTIM1SMEN_Msk     (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
5396 #define RCC_APBSMENR1_LPTIM1SMEN         RCC_APBSMENR1_LPTIM1SMEN_Msk
5397 
5398 /********************  Bit definition for RCC_APBSMENR2 register  *************/
5399 #define RCC_APBSMENR2_SYSCFGSMEN_Pos     (0U)
5400 #define RCC_APBSMENR2_SYSCFGSMEN_Msk     (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
5401 #define RCC_APBSMENR2_SYSCFGSMEN         RCC_APBSMENR2_SYSCFGSMEN_Msk
5402 #define RCC_APBSMENR2_TIM1SMEN_Pos       (11U)
5403 #define RCC_APBSMENR2_TIM1SMEN_Msk       (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos)  /*!< 0x00000800 */
5404 #define RCC_APBSMENR2_TIM1SMEN           RCC_APBSMENR2_TIM1SMEN_Msk
5405 #define RCC_APBSMENR2_SPI1SMEN_Pos       (12U)
5406 #define RCC_APBSMENR2_SPI1SMEN_Msk       (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos)  /*!< 0x00001000 */
5407 #define RCC_APBSMENR2_SPI1SMEN           RCC_APBSMENR2_SPI1SMEN_Msk
5408 #define RCC_APBSMENR2_USART1SMEN_Pos     (14U)
5409 #define RCC_APBSMENR2_USART1SMEN_Msk     (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
5410 #define RCC_APBSMENR2_USART1SMEN         RCC_APBSMENR2_USART1SMEN_Msk
5411 #define RCC_APBSMENR2_TIM14SMEN_Pos      (15U)
5412 #define RCC_APBSMENR2_TIM14SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
5413 #define RCC_APBSMENR2_TIM14SMEN          RCC_APBSMENR2_TIM14SMEN_Msk
5414 #define RCC_APBSMENR2_TIM15SMEN_Pos      (16U)
5415 #define RCC_APBSMENR2_TIM15SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM15SMEN_Pos) /*!< 0x00010000 */
5416 #define RCC_APBSMENR2_TIM15SMEN          RCC_APBSMENR2_TIM15SMEN_Msk
5417 #define RCC_APBSMENR2_TIM16SMEN_Pos      (17U)
5418 #define RCC_APBSMENR2_TIM16SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
5419 #define RCC_APBSMENR2_TIM16SMEN          RCC_APBSMENR2_TIM16SMEN_Msk
5420 #define RCC_APBSMENR2_TIM17SMEN_Pos      (18U)
5421 #define RCC_APBSMENR2_TIM17SMEN_Msk      (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
5422 #define RCC_APBSMENR2_TIM17SMEN          RCC_APBSMENR2_TIM17SMEN_Msk
5423 #define RCC_APBSMENR2_ADCSMEN_Pos        (20U)
5424 #define RCC_APBSMENR2_ADCSMEN_Msk        (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos)   /*!< 0x00100000 */
5425 #define RCC_APBSMENR2_ADCSMEN            RCC_APBSMENR2_ADCSMEN_Msk
5426 
5427 /********************  Bit definition for RCC_CCIPR register  ******************/
5428 #define RCC_CCIPR_USART1SEL_Pos          (0U)
5429 #define RCC_CCIPR_USART1SEL_Msk          (0x3UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000003 */
5430 #define RCC_CCIPR_USART1SEL              RCC_CCIPR_USART1SEL_Msk
5431 #define RCC_CCIPR_USART1SEL_0            (0x1UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000001 */
5432 #define RCC_CCIPR_USART1SEL_1            (0x2UL << RCC_CCIPR_USART1SEL_Pos)     /*!< 0x00000002 */
5433 
5434 #define RCC_CCIPR_USART2SEL_Pos          (2U)
5435 #define RCC_CCIPR_USART2SEL_Msk          (0x3UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x0000000C */
5436 #define RCC_CCIPR_USART2SEL              RCC_CCIPR_USART2SEL_Msk
5437 #define RCC_CCIPR_USART2SEL_0            (0x1UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000004 */
5438 #define RCC_CCIPR_USART2SEL_1            (0x2UL << RCC_CCIPR_USART2SEL_Pos)     /*!< 0x00000008 */
5439 
5440 #define RCC_CCIPR_CECSEL_Pos             (6U)
5441 #define RCC_CCIPR_CECSEL_Msk             (0x1UL << RCC_CCIPR_CECSEL_Pos)        /*!< 0x00000040 */
5442 #define RCC_CCIPR_CECSEL                 RCC_CCIPR_CECSEL_Msk
5443 
5444 #define RCC_CCIPR_LPUART1SEL_Pos         (10U)
5445 #define RCC_CCIPR_LPUART1SEL_Msk         (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000C00 */
5446 #define RCC_CCIPR_LPUART1SEL             RCC_CCIPR_LPUART1SEL_Msk
5447 #define RCC_CCIPR_LPUART1SEL_0           (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000400 */
5448 #define RCC_CCIPR_LPUART1SEL_1           (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)    /*!< 0x00000800 */
5449 
5450 #define RCC_CCIPR_I2C1SEL_Pos            (12U)
5451 #define RCC_CCIPR_I2C1SEL_Msk            (0x3UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00003000 */
5452 #define RCC_CCIPR_I2C1SEL                RCC_CCIPR_I2C1SEL_Msk
5453 #define RCC_CCIPR_I2C1SEL_0              (0x1UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00001000 */
5454 #define RCC_CCIPR_I2C1SEL_1              (0x2UL << RCC_CCIPR_I2C1SEL_Pos)       /*!< 0x00002000 */
5455 
5456 #define RCC_CCIPR_I2S1SEL_Pos            (14U)
5457 #define RCC_CCIPR_I2S1SEL_Msk            (0x3UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x0000C000 */
5458 #define RCC_CCIPR_I2S1SEL                RCC_CCIPR_I2S1SEL_Msk
5459 #define RCC_CCIPR_I2S1SEL_0              (0x1UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00004000 */
5460 #define RCC_CCIPR_I2S1SEL_1              (0x2UL << RCC_CCIPR_I2S1SEL_Pos)       /*!< 0x00008000 */
5461 
5462 #define RCC_CCIPR_LPTIM1SEL_Pos          (18U)
5463 #define RCC_CCIPR_LPTIM1SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x000C0000 */
5464 #define RCC_CCIPR_LPTIM1SEL              RCC_CCIPR_LPTIM1SEL_Msk
5465 #define RCC_CCIPR_LPTIM1SEL_0            (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00040000 */
5466 #define RCC_CCIPR_LPTIM1SEL_1            (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)     /*!< 0x00080000 */
5467 
5468 #define RCC_CCIPR_LPTIM2SEL_Pos          (20U)
5469 #define RCC_CCIPR_LPTIM2SEL_Msk          (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00300000 */
5470 #define RCC_CCIPR_LPTIM2SEL              RCC_CCIPR_LPTIM2SEL_Msk
5471 #define RCC_CCIPR_LPTIM2SEL_0            (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00100000 */
5472 #define RCC_CCIPR_LPTIM2SEL_1            (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos)     /*!< 0x00200000 */
5473 
5474 #define RCC_CCIPR_TIM1SEL_Pos            (22U)
5475 #define RCC_CCIPR_TIM1SEL_Msk            (0x1UL << RCC_CCIPR_TIM1SEL_Pos)       /*!< 0x00400000 */
5476 #define RCC_CCIPR_TIM1SEL                RCC_CCIPR_TIM1SEL_Msk
5477 
5478 #define RCC_CCIPR_TIM15SEL_Pos           (24U)
5479 #define RCC_CCIPR_TIM15SEL_Msk           (0x1UL << RCC_CCIPR_TIM15SEL_Pos)      /*!< 0x01000000 */
5480 #define RCC_CCIPR_TIM15SEL               RCC_CCIPR_TIM15SEL_Msk
5481 
5482 
5483 #define RCC_CCIPR_ADCSEL_Pos             (30U)
5484 #define RCC_CCIPR_ADCSEL_Msk             (0x3UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0xC0000000 */
5485 #define RCC_CCIPR_ADCSEL                 RCC_CCIPR_ADCSEL_Msk
5486 #define RCC_CCIPR_ADCSEL_0               (0x1UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x40000000 */
5487 #define RCC_CCIPR_ADCSEL_1               (0x2UL << RCC_CCIPR_ADCSEL_Pos)        /*!< 0x80000000 */
5488 
5489 /********************  Bit definition for RCC_BDCR register  ******************/
5490 #define RCC_BDCR_LSEON_Pos               (0U)
5491 #define RCC_BDCR_LSEON_Msk               (0x1UL << RCC_BDCR_LSEON_Pos)          /*!< 0x00000001 */
5492 #define RCC_BDCR_LSEON                   RCC_BDCR_LSEON_Msk
5493 #define RCC_BDCR_LSERDY_Pos              (1U)
5494 #define RCC_BDCR_LSERDY_Msk              (0x1UL << RCC_BDCR_LSERDY_Pos)         /*!< 0x00000002 */
5495 #define RCC_BDCR_LSERDY                  RCC_BDCR_LSERDY_Msk
5496 #define RCC_BDCR_LSEBYP_Pos              (2U)
5497 #define RCC_BDCR_LSEBYP_Msk              (0x1UL << RCC_BDCR_LSEBYP_Pos)         /*!< 0x00000004 */
5498 #define RCC_BDCR_LSEBYP                  RCC_BDCR_LSEBYP_Msk
5499 
5500 #define RCC_BDCR_LSEDRV_Pos              (3U)
5501 #define RCC_BDCR_LSEDRV_Msk              (0x3UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000018 */
5502 #define RCC_BDCR_LSEDRV                  RCC_BDCR_LSEDRV_Msk
5503 #define RCC_BDCR_LSEDRV_0                (0x1UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000008 */
5504 #define RCC_BDCR_LSEDRV_1                (0x2UL << RCC_BDCR_LSEDRV_Pos)         /*!< 0x00000010 */
5505 
5506 #define RCC_BDCR_LSECSSON_Pos            (5U)
5507 #define RCC_BDCR_LSECSSON_Msk            (0x1UL << RCC_BDCR_LSECSSON_Pos)       /*!< 0x00000020 */
5508 #define RCC_BDCR_LSECSSON                RCC_BDCR_LSECSSON_Msk
5509 #define RCC_BDCR_LSECSSD_Pos             (6U)
5510 #define RCC_BDCR_LSECSSD_Msk             (0x1UL << RCC_BDCR_LSECSSD_Pos)        /*!< 0x00000040 */
5511 #define RCC_BDCR_LSECSSD                 RCC_BDCR_LSECSSD_Msk
5512 
5513 #define RCC_BDCR_RTCSEL_Pos              (8U)
5514 #define RCC_BDCR_RTCSEL_Msk              (0x3UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000300 */
5515 #define RCC_BDCR_RTCSEL                  RCC_BDCR_RTCSEL_Msk
5516 #define RCC_BDCR_RTCSEL_0                (0x1UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000100 */
5517 #define RCC_BDCR_RTCSEL_1                (0x2UL << RCC_BDCR_RTCSEL_Pos)         /*!< 0x00000200 */
5518 
5519 #define RCC_BDCR_RTCEN_Pos               (15U)
5520 #define RCC_BDCR_RTCEN_Msk               (0x1UL << RCC_BDCR_RTCEN_Pos)          /*!< 0x00008000 */
5521 #define RCC_BDCR_RTCEN                   RCC_BDCR_RTCEN_Msk
5522 #define RCC_BDCR_BDRST_Pos               (16U)
5523 #define RCC_BDCR_BDRST_Msk               (0x1UL << RCC_BDCR_BDRST_Pos)          /*!< 0x00010000 */
5524 #define RCC_BDCR_BDRST                   RCC_BDCR_BDRST_Msk
5525 
5526 #define RCC_BDCR_LSCOEN_Pos              (24U)
5527 #define RCC_BDCR_LSCOEN_Msk              (0x1UL << RCC_BDCR_LSCOEN_Pos)         /*!< 0x01000000 */
5528 #define RCC_BDCR_LSCOEN                  RCC_BDCR_LSCOEN_Msk
5529 #define RCC_BDCR_LSCOSEL_Pos             (25U)
5530 #define RCC_BDCR_LSCOSEL_Msk             (0x1UL << RCC_BDCR_LSCOSEL_Pos)        /*!< 0x02000000 */
5531 #define RCC_BDCR_LSCOSEL                 RCC_BDCR_LSCOSEL_Msk
5532 
5533 /********************  Bit definition for RCC_CSR register  *******************/
5534 #define RCC_CSR_LSION_Pos                (0U)
5535 #define RCC_CSR_LSION_Msk                (0x1UL << RCC_CSR_LSION_Pos)           /*!< 0x00000001 */
5536 #define RCC_CSR_LSION                    RCC_CSR_LSION_Msk
5537 #define RCC_CSR_LSIRDY_Pos               (1U)
5538 #define RCC_CSR_LSIRDY_Msk               (0x1UL << RCC_CSR_LSIRDY_Pos)          /*!< 0x00000002 */
5539 #define RCC_CSR_LSIRDY                   RCC_CSR_LSIRDY_Msk
5540 
5541 #define RCC_CSR_RMVF_Pos                 (23U)
5542 #define RCC_CSR_RMVF_Msk                 (0x1UL << RCC_CSR_RMVF_Pos)            /*!< 0x00800000 */
5543 #define RCC_CSR_RMVF                     RCC_CSR_RMVF_Msk
5544 #define RCC_CSR_OBLRSTF_Pos              (25U)
5545 #define RCC_CSR_OBLRSTF_Msk              (0x1UL << RCC_CSR_OBLRSTF_Pos)         /*!< 0x02000000 */
5546 #define RCC_CSR_OBLRSTF                  RCC_CSR_OBLRSTF_Msk
5547 #define RCC_CSR_PINRSTF_Pos              (26U)
5548 #define RCC_CSR_PINRSTF_Msk              (0x1UL << RCC_CSR_PINRSTF_Pos)         /*!< 0x04000000 */
5549 #define RCC_CSR_PINRSTF                  RCC_CSR_PINRSTF_Msk
5550 #define RCC_CSR_PWRRSTF_Pos              (27U)
5551 #define RCC_CSR_PWRRSTF_Msk              (0x1UL << RCC_CSR_PWRRSTF_Pos)         /*!< 0x08000000 */
5552 #define RCC_CSR_PWRRSTF                  RCC_CSR_PWRRSTF_Msk
5553 #define RCC_CSR_SFTRSTF_Pos              (28U)
5554 #define RCC_CSR_SFTRSTF_Msk              (0x1UL << RCC_CSR_SFTRSTF_Pos)         /*!< 0x10000000 */
5555 #define RCC_CSR_SFTRSTF                  RCC_CSR_SFTRSTF_Msk
5556 #define RCC_CSR_IWDGRSTF_Pos             (29U)
5557 #define RCC_CSR_IWDGRSTF_Msk             (0x1UL << RCC_CSR_IWDGRSTF_Pos)        /*!< 0x20000000 */
5558 #define RCC_CSR_IWDGRSTF                 RCC_CSR_IWDGRSTF_Msk
5559 #define RCC_CSR_WWDGRSTF_Pos             (30U)
5560 #define RCC_CSR_WWDGRSTF_Msk             (0x1UL << RCC_CSR_WWDGRSTF_Pos)        /*!< 0x40000000 */
5561 #define RCC_CSR_WWDGRSTF                 RCC_CSR_WWDGRSTF_Msk
5562 #define RCC_CSR_LPWRRSTF_Pos             (31U)
5563 #define RCC_CSR_LPWRRSTF_Msk             (0x1UL << RCC_CSR_LPWRRSTF_Pos)        /*!< 0x80000000 */
5564 #define RCC_CSR_LPWRRSTF                 RCC_CSR_LPWRRSTF_Msk
5565 
5566 /******************************************************************************/
5567 /*                                                                            */
5568 /*                           Real-Time Clock (RTC)                            */
5569 /*                                                                            */
5570 /******************************************************************************/
5571 /*
5572 * @brief Specific device feature definitions
5573 */
5574 #define RTC_WAKEUP_SUPPORT
5575 #define RTC_BACKUP_SUPPORT
5576 
5577 /********************  Bits definition for RTC_TR register  *******************/
5578 #define RTC_TR_PM_Pos                (22U)
5579 #define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                   /*!< 0x00400000 */
5580 #define RTC_TR_PM                    RTC_TR_PM_Msk
5581 #define RTC_TR_HT_Pos                (20U)
5582 #define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                   /*!< 0x00300000 */
5583 #define RTC_TR_HT                    RTC_TR_HT_Msk
5584 #define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                   /*!< 0x00100000 */
5585 #define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                   /*!< 0x00200000 */
5586 #define RTC_TR_HU_Pos                (16U)
5587 #define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                   /*!< 0x000F0000 */
5588 #define RTC_TR_HU                    RTC_TR_HU_Msk
5589 #define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                   /*!< 0x00010000 */
5590 #define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                   /*!< 0x00020000 */
5591 #define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                   /*!< 0x00040000 */
5592 #define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                   /*!< 0x00080000 */
5593 #define RTC_TR_MNT_Pos               (12U)
5594 #define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                  /*!< 0x00007000 */
5595 #define RTC_TR_MNT                   RTC_TR_MNT_Msk
5596 #define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                  /*!< 0x00001000 */
5597 #define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                  /*!< 0x00002000 */
5598 #define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                  /*!< 0x00004000 */
5599 #define RTC_TR_MNU_Pos               (8U)
5600 #define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                  /*!< 0x00000F00 */
5601 #define RTC_TR_MNU                   RTC_TR_MNU_Msk
5602 #define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                  /*!< 0x00000100 */
5603 #define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                  /*!< 0x00000200 */
5604 #define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                  /*!< 0x00000400 */
5605 #define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                  /*!< 0x00000800 */
5606 #define RTC_TR_ST_Pos                (4U)
5607 #define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                   /*!< 0x00000070 */
5608 #define RTC_TR_ST                    RTC_TR_ST_Msk
5609 #define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                   /*!< 0x00000010 */
5610 #define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                   /*!< 0x00000020 */
5611 #define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                   /*!< 0x00000040 */
5612 #define RTC_TR_SU_Pos                (0U)
5613 #define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                   /*!< 0x0000000F */
5614 #define RTC_TR_SU                    RTC_TR_SU_Msk
5615 #define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                   /*!< 0x00000001 */
5616 #define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                   /*!< 0x00000002 */
5617 #define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                   /*!< 0x00000004 */
5618 #define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                   /*!< 0x00000008 */
5619 
5620 /********************  Bits definition for RTC_DR register  *******************/
5621 #define RTC_DR_YT_Pos                (20U)
5622 #define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                   /*!< 0x00F00000 */
5623 #define RTC_DR_YT                    RTC_DR_YT_Msk
5624 #define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                   /*!< 0x00100000 */
5625 #define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                   /*!< 0x00200000 */
5626 #define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                   /*!< 0x00400000 */
5627 #define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                   /*!< 0x00800000 */
5628 #define RTC_DR_YU_Pos                (16U)
5629 #define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                   /*!< 0x000F0000 */
5630 #define RTC_DR_YU                    RTC_DR_YU_Msk
5631 #define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                   /*!< 0x00010000 */
5632 #define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                   /*!< 0x00020000 */
5633 #define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                   /*!< 0x00040000 */
5634 #define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                   /*!< 0x00080000 */
5635 #define RTC_DR_WDU_Pos               (13U)
5636 #define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                  /*!< 0x0000E000 */
5637 #define RTC_DR_WDU                   RTC_DR_WDU_Msk
5638 #define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                  /*!< 0x00002000 */
5639 #define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                  /*!< 0x00004000 */
5640 #define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                  /*!< 0x00008000 */
5641 #define RTC_DR_MT_Pos                (12U)
5642 #define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                   /*!< 0x00001000 */
5643 #define RTC_DR_MT                    RTC_DR_MT_Msk
5644 #define RTC_DR_MU_Pos                (8U)
5645 #define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                   /*!< 0x00000F00 */
5646 #define RTC_DR_MU                    RTC_DR_MU_Msk
5647 #define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                   /*!< 0x00000100 */
5648 #define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                   /*!< 0x00000200 */
5649 #define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                   /*!< 0x00000400 */
5650 #define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                   /*!< 0x00000800 */
5651 #define RTC_DR_DT_Pos                (4U)
5652 #define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                   /*!< 0x00000030 */
5653 #define RTC_DR_DT                    RTC_DR_DT_Msk
5654 #define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                   /*!< 0x00000010 */
5655 #define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                   /*!< 0x00000020 */
5656 #define RTC_DR_DU_Pos                (0U)
5657 #define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                   /*!< 0x0000000F */
5658 #define RTC_DR_DU                    RTC_DR_DU_Msk
5659 #define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                   /*!< 0x00000001 */
5660 #define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                   /*!< 0x00000002 */
5661 #define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                   /*!< 0x00000004 */
5662 #define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                   /*!< 0x00000008 */
5663 
5664 /********************  Bits definition for RTC_SSR register  ******************/
5665 #define RTC_SSR_SS_Pos               (0U)
5666 #define RTC_SSR_SS_Msk               (0xFFFFUL << RTC_SSR_SS_Pos)               /*!< 0x0000FFFF */
5667 #define RTC_SSR_SS                   RTC_SSR_SS_Msk
5668 
5669 /********************  Bits definition for RTC_ICSR register  ******************/
5670 #define RTC_ICSR_RECALPF_Pos         (16U)
5671 #define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)            /*!< 0x00010000 */
5672 #define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
5673 #define RTC_ICSR_INIT_Pos            (7U)
5674 #define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)               /*!< 0x00000080 */
5675 #define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
5676 #define RTC_ICSR_INITF_Pos           (6U)
5677 #define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)              /*!< 0x00000040 */
5678 #define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
5679 #define RTC_ICSR_RSF_Pos             (5U)
5680 #define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)                /*!< 0x00000020 */
5681 #define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
5682 #define RTC_ICSR_INITS_Pos           (4U)
5683 #define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)              /*!< 0x00000010 */
5684 #define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
5685 #define RTC_ICSR_SHPF_Pos            (3U)
5686 #define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)               /*!< 0x00000008 */
5687 #define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
5688 #define RTC_ICSR_WUTWF_Pos           (2U)
5689 #define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)              /*!< 0x00000004 */
5690 #define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk                         /*!< Wakeup timer write flag > */
5691 #define RTC_ICSR_ALRBWF_Pos          (1U)
5692 #define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)             /*!< 0x00000002 */
5693 #define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk
5694 #define RTC_ICSR_ALRAWF_Pos          (0U)
5695 #define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)             /*!< 0x00000001 */
5696 #define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk
5697 
5698 /********************  Bits definition for RTC_PRER register  *****************/
5699 #define RTC_PRER_PREDIV_A_Pos        (16U)
5700 #define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)          /*!< 0x007F0000 */
5701 #define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
5702 #define RTC_PRER_PREDIV_S_Pos        (0U)
5703 #define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)        /*!< 0x00007FFF */
5704 #define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
5705 
5706 /********************  Bits definition for RTC_WUTR register  *****************/
5707 #define RTC_WUTR_WUT_Pos             (0U)
5708 #define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
5709 #define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk                          /*!< Wakeup auto-reload value bits > */
5710 
5711 /********************  Bits definition for RTC_CR register  *******************/
5712 #define RTC_CR_OUT2EN_Pos            (31U)
5713 #define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
5714 #define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!< RTC_OUT2 output enable */
5715 #define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
5716 #define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
5717 #define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!< TAMPALARM output type  */
5718 #define RTC_CR_TAMPALRM_PU_Pos       (29U)
5719 #define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
5720 #define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!< TAMPALARM output pull-up config */
5721 #define RTC_CR_TAMPOE_Pos            (26U)
5722 #define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
5723 #define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!< Tamper detection output enable on TAMPALARM  */
5724 #define RTC_CR_TAMPTS_Pos            (25U)
5725 #define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
5726 #define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!< Activate timestamp on tamper detection event  */
5727 #define RTC_CR_ITSE_Pos              (24U)
5728 #define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
5729 #define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!< Timestamp on internal event enable  */
5730 #define RTC_CR_COE_Pos               (23U)
5731 #define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
5732 #define RTC_CR_COE                   RTC_CR_COE_Msk
5733 #define RTC_CR_OSEL_Pos              (21U)
5734 #define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                 /*!< 0x00600000 */
5735 #define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
5736 #define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                 /*!< 0x00200000 */
5737 #define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                 /*!< 0x00400000 */
5738 #define RTC_CR_POL_Pos               (20U)
5739 #define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                  /*!< 0x00100000 */
5740 #define RTC_CR_POL                   RTC_CR_POL_Msk
5741 #define RTC_CR_COSEL_Pos             (19U)
5742 #define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
5743 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
5744 #define RTC_CR_BKP_Pos               (18U)
5745 #define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
5746 #define RTC_CR_BKP                   RTC_CR_BKP_Msk
5747 #define RTC_CR_SUB1H_Pos             (17U)
5748 #define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
5749 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
5750 #define RTC_CR_ADD1H_Pos             (16U)
5751 #define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)                /*!< 0x00010000 */
5752 #define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
5753 #define RTC_CR_TSIE_Pos              (15U)
5754 #define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
5755 #define RTC_CR_TSIE                  RTC_CR_TSIE_Msk                           /*!< Timestamp interrupt enable > */
5756 #define RTC_CR_WUTIE_Pos             (14U)
5757 #define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
5758 #define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk                          /*!< Wakeup timer interrupt enable > */
5759 #define RTC_CR_ALRBIE_Pos            (13U)
5760 #define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
5761 #define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
5762 #define RTC_CR_ALRAIE_Pos            (12U)
5763 #define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
5764 #define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
5765 #define RTC_CR_TSE_Pos               (11U)
5766 #define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
5767 #define RTC_CR_TSE                   RTC_CR_TSE_Msk                            /*!< timestamp enable > */
5768 #define RTC_CR_WUTE_Pos              (10U)
5769 #define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
5770 #define RTC_CR_WUTE                  RTC_CR_WUTE_Msk                           /*!< Wakeup timer enable > */
5771 #define RTC_CR_ALRBE_Pos             (9U)
5772 #define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
5773 #define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
5774 #define RTC_CR_ALRAE_Pos             (8U)
5775 #define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)                /*!< 0x00000100 */
5776 #define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
5777 #define RTC_CR_FMT_Pos               (6U)
5778 #define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                  /*!< 0x00000040 */
5779 #define RTC_CR_FMT                   RTC_CR_FMT_Msk
5780 #define RTC_CR_BYPSHAD_Pos           (5U)
5781 #define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)              /*!< 0x00000020 */
5782 #define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
5783 #define RTC_CR_REFCKON_Pos           (4U)
5784 #define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)              /*!< 0x00000010 */
5785 #define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
5786 #define RTC_CR_TSEDGE_Pos            (3U)
5787 #define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
5788 #define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk                         /*!< Timestamp event active edge > */
5789 #define RTC_CR_WUCKSEL_Pos           (0U)
5790 #define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
5791 #define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk                        /*!< Wakeup clock selection > */
5792 #define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
5793 #define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
5794 #define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
5795 
5796 /********************  Bits definition for RTC_WPR register  ******************/
5797 #define RTC_WPR_KEY_Pos              (0U)
5798 #define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)                /*!< 0x000000FF */
5799 #define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
5800 
5801 /********************  Bits definition for RTC_CALR register  *****************/
5802 #define RTC_CALR_CALP_Pos            (15U)
5803 #define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)               /*!< 0x00008000 */
5804 #define RTC_CALR_CALP                RTC_CALR_CALP_Msk
5805 #define RTC_CALR_CALW8_Pos           (14U)
5806 #define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)              /*!< 0x00004000 */
5807 #define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
5808 #define RTC_CALR_CALW16_Pos          (13U)
5809 #define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)             /*!< 0x00002000 */
5810 #define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
5811 #define RTC_CALR_CALM_Pos            (0U)
5812 #define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)             /*!< 0x000001FF */
5813 #define RTC_CALR_CALM                RTC_CALR_CALM_Msk
5814 #define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)             /*!< 0x00000001 */
5815 #define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)             /*!< 0x00000002 */
5816 #define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)             /*!< 0x00000004 */
5817 #define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)             /*!< 0x00000008 */
5818 #define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)             /*!< 0x00000010 */
5819 #define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)             /*!< 0x00000020 */
5820 #define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)             /*!< 0x00000040 */
5821 #define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)             /*!< 0x00000080 */
5822 #define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)             /*!< 0x00000100 */
5823 
5824 /********************  Bits definition for RTC_SHIFTR register  ***************/
5825 #define RTC_SHIFTR_SUBFS_Pos         (0U)
5826 #define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)         /*!< 0x00007FFF */
5827 #define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
5828 #define RTC_SHIFTR_ADD1S_Pos         (31U)
5829 #define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)            /*!< 0x80000000 */
5830 #define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
5831 
5832 /********************  Bits definition for RTC_TSTR register  *****************/
5833 #define RTC_TSTR_PM_Pos              (22U)
5834 #define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
5835 #define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           /*!< AM-PM notation > */
5836 #define RTC_TSTR_HT_Pos              (20U)
5837 #define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
5838 #define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
5839 #define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
5840 #define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
5841 #define RTC_TSTR_HU_Pos              (16U)
5842 #define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
5843 #define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
5844 #define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
5845 #define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
5846 #define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
5847 #define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
5848 #define RTC_TSTR_MNT_Pos             (12U)
5849 #define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
5850 #define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
5851 #define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
5852 #define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
5853 #define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)                /*!< 0x00004000 */
5854 #define RTC_TSTR_MNU_Pos             (8U)
5855 #define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)                /*!< 0x00000F00 */
5856 #define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
5857 #define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000100 */
5858 #define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000200 */
5859 #define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000400 */
5860 #define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)                /*!< 0x00000800 */
5861 #define RTC_TSTR_ST_Pos              (4U)
5862 #define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000070 */
5863 #define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
5864 #define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000010 */
5865 #define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000020 */
5866 #define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                 /*!< 0x00000040 */
5867 #define RTC_TSTR_SU_Pos              (0U)
5868 #define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                 /*!< 0x0000000F */
5869 #define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
5870 #define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000001 */
5871 #define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000002 */
5872 #define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000004 */
5873 #define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                 /*!< 0x00000008 */
5874 
5875 /********************  Bits definition for RTC_TSDR register  *****************/
5876 #define RTC_TSDR_WDU_Pos             (13U)
5877 #define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
5878 #define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          /*!< Week day units > */
5879 #define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
5880 #define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
5881 #define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
5882 #define RTC_TSDR_MT_Pos              (12U)
5883 #define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
5884 #define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
5885 #define RTC_TSDR_MU_Pos              (8U)
5886 #define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
5887 #define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
5888 #define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
5889 #define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
5890 #define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
5891 #define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
5892 #define RTC_TSDR_DT_Pos              (4U)
5893 #define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
5894 #define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
5895 #define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
5896 #define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
5897 #define RTC_TSDR_DU_Pos              (0U)
5898 #define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
5899 #define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
5900 #define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
5901 #define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
5902 #define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
5903 #define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
5904 
5905 /********************  Bits definition for RTC_TSSSR register  ****************/
5906 #define RTC_TSSSR_SS_Pos             (0U)
5907 #define RTC_TSSSR_SS_Msk             (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
5908 #define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          /*!< Sub second value > */
5909 
5910 /********************  Bits definition for RTC_ALRMAR register  ***************/
5911 #define RTC_ALRMAR_MSK4_Pos          (31U)
5912 #define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
5913 #define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
5914 #define RTC_ALRMAR_WDSEL_Pos         (30U)
5915 #define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
5916 #define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
5917 #define RTC_ALRMAR_DT_Pos            (28U)
5918 #define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
5919 #define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
5920 #define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
5921 #define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
5922 #define RTC_ALRMAR_DU_Pos            (24U)
5923 #define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
5924 #define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
5925 #define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
5926 #define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
5927 #define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
5928 #define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
5929 #define RTC_ALRMAR_MSK3_Pos          (23U)
5930 #define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
5931 #define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
5932 #define RTC_ALRMAR_PM_Pos            (22U)
5933 #define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
5934 #define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
5935 #define RTC_ALRMAR_HT_Pos            (20U)
5936 #define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
5937 #define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
5938 #define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
5939 #define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
5940 #define RTC_ALRMAR_HU_Pos            (16U)
5941 #define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
5942 #define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
5943 #define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
5944 #define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
5945 #define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
5946 #define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
5947 #define RTC_ALRMAR_MSK2_Pos          (15U)
5948 #define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
5949 #define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
5950 #define RTC_ALRMAR_MNT_Pos           (12U)
5951 #define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
5952 #define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
5953 #define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
5954 #define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
5955 #define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
5956 #define RTC_ALRMAR_MNU_Pos           (8U)
5957 #define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
5958 #define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
5959 #define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
5960 #define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
5961 #define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
5962 #define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
5963 #define RTC_ALRMAR_MSK1_Pos          (7U)
5964 #define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
5965 #define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
5966 #define RTC_ALRMAR_ST_Pos            (4U)
5967 #define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
5968 #define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
5969 #define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
5970 #define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
5971 #define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
5972 #define RTC_ALRMAR_SU_Pos            (0U)
5973 #define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
5974 #define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
5975 #define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
5976 #define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
5977 #define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
5978 #define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
5979 
5980 /********************  Bits definition for RTC_ALRMASSR register  *************/
5981 #define RTC_ALRMASSR_MASKSS_Pos      (24U)
5982 #define RTC_ALRMASSR_MASKSS_Msk      (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
5983 #define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
5984 #define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
5985 #define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
5986 #define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
5987 #define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
5988 #define RTC_ALRMASSR_SS_Pos          (0U)
5989 #define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
5990 #define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
5991 
5992 /********************  Bits definition for RTC_ALRMBR register  ***************/
5993 #define RTC_ALRMBR_MSK4_Pos          (31U)
5994 #define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
5995 #define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
5996 #define RTC_ALRMBR_WDSEL_Pos         (30U)
5997 #define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
5998 #define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
5999 #define RTC_ALRMBR_DT_Pos            (28U)
6000 #define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
6001 #define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
6002 #define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
6003 #define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
6004 #define RTC_ALRMBR_DU_Pos            (24U)
6005 #define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
6006 #define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
6007 #define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
6008 #define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
6009 #define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
6010 #define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
6011 #define RTC_ALRMBR_MSK3_Pos          (23U)
6012 #define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
6013 #define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
6014 #define RTC_ALRMBR_PM_Pos            (22U)
6015 #define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
6016 #define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
6017 #define RTC_ALRMBR_HT_Pos            (20U)
6018 #define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
6019 #define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
6020 #define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
6021 #define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
6022 #define RTC_ALRMBR_HU_Pos            (16U)
6023 #define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
6024 #define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
6025 #define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
6026 #define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
6027 #define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
6028 #define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
6029 #define RTC_ALRMBR_MSK2_Pos          (15U)
6030 #define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
6031 #define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
6032 #define RTC_ALRMBR_MNT_Pos           (12U)
6033 #define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
6034 #define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
6035 #define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
6036 #define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
6037 #define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
6038 #define RTC_ALRMBR_MNU_Pos           (8U)
6039 #define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
6040 #define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
6041 #define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
6042 #define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
6043 #define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
6044 #define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
6045 #define RTC_ALRMBR_MSK1_Pos          (7U)
6046 #define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
6047 #define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
6048 #define RTC_ALRMBR_ST_Pos            (4U)
6049 #define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
6050 #define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
6051 #define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
6052 #define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
6053 #define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
6054 #define RTC_ALRMBR_SU_Pos            (0U)
6055 #define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
6056 #define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
6057 #define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
6058 #define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
6059 #define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
6060 #define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
6061 
6062 /********************  Bits definition for RTC_ALRMASSR register  *************/
6063 #define RTC_ALRMBSSR_MASKSS_Pos      (24U)
6064 #define RTC_ALRMBSSR_MASKSS_Msk      (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
6065 #define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
6066 #define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
6067 #define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
6068 #define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
6069 #define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
6070 #define RTC_ALRMBSSR_SS_Pos          (0U)
6071 #define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
6072 #define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
6073 
6074 /********************  Bits definition for RTC_SR register  *******************/
6075 #define RTC_SR_ITSF_Pos              (5U)
6076 #define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
6077 #define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
6078 #define RTC_SR_TSOVF_Pos             (4U)
6079 #define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
6080 #define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk                          /*!< Timestamp overflow flag > */
6081 #define RTC_SR_TSF_Pos               (3U)
6082 #define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
6083 #define RTC_SR_TSF                   RTC_SR_TSF_Msk                            /*!< Timestamp flag > */
6084 #define RTC_SR_WUTF_Pos              (2U)
6085 #define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
6086 #define RTC_SR_WUTF                  RTC_SR_WUTF_Msk                           /*!< Wakeup timer flag > */
6087 #define RTC_SR_ALRBF_Pos             (1U)
6088 #define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
6089 #define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
6090 #define RTC_SR_ALRAF_Pos             (0U)
6091 #define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
6092 #define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
6093 
6094 /********************  Bits definition for RTC_MISR register  *****************/
6095 #define RTC_MISR_ITSMF_Pos           (5U)
6096 #define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
6097 #define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
6098 #define RTC_MISR_TSOVMF_Pos          (4U)
6099 #define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
6100 #define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk                       /*!< Timestamp overflow masked flag > */
6101 #define RTC_MISR_TSMF_Pos            (3U)
6102 #define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
6103 #define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk                         /*!< Timestamp masked flag > */
6104 #define RTC_MISR_WUTMF_Pos           (2U)
6105 #define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
6106 #define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk                        /*!< Wakeup timer masked flag > */
6107 #define RTC_MISR_ALRBMF_Pos          (1U)
6108 #define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
6109 #define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
6110 #define RTC_MISR_ALRAMF_Pos          (0U)
6111 #define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
6112 #define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
6113 
6114 /********************  Bits definition for RTC_SCR register  ******************/
6115 #define RTC_SCR_CITSF_Pos            (5U)
6116 #define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
6117 #define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
6118 #define RTC_SCR_CTSOVF_Pos           (4U)
6119 #define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
6120 #define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk                        /*!< Clear timestamp overflow flag > */
6121 #define RTC_SCR_CTSF_Pos             (3U)
6122 #define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
6123 #define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk                          /*!< Clear timestamp flag > */
6124 #define RTC_SCR_CWUTF_Pos            (2U)
6125 #define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
6126 #define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk                         /*!< Clear wakeup timer flag > */
6127 #define RTC_SCR_CALRBF_Pos           (1U)
6128 #define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
6129 #define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
6130 #define RTC_SCR_CALRAF_Pos           (0U)
6131 #define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
6132 #define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
6133 
6134 /******************************************************************************/
6135 /*                                                                            */
6136 /*                     Tamper and backup register (TAMP)                      */
6137 /*                                                                            */
6138 /******************************************************************************/
6139 /********************  Bits definition for TAMP_CR1 register  *****************/
6140 #define TAMP_CR1_TAMP1E_Pos          (0U)
6141 #define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)             /*!< 0x00000001 */
6142 #define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
6143 #define TAMP_CR1_TAMP2E_Pos          (1U)
6144 #define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)             /*!< 0x00000002 */
6145 #define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
6146 #define TAMP_CR1_ITAMP3E_Pos         (18U)
6147 #define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)            /*!< 0x00040000 */
6148 #define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
6149 #define TAMP_CR1_ITAMP4E_Pos         (19U)
6150 #define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)            /*!< 0x00080000 */
6151 #define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk
6152 #define TAMP_CR1_ITAMP5E_Pos         (20U)
6153 #define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)            /*!< 0x00100000 */
6154 #define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
6155 #define TAMP_CR1_ITAMP6E_Pos         (21U)
6156 #define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)            /*!< 0x00200000 */
6157 #define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
6158 
6159 /********************  Bits definition for TAMP_CR2 register  *****************/
6160 #define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
6161 #define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)       /*!< 0x00000001 */
6162 #define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
6163 #define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
6164 #define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)       /*!< 0x00000002 */
6165 #define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
6166 #define TAMP_CR2_TAMP1MSK_Pos        (16U)
6167 #define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)           /*!< 0x00010000 */
6168 #define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
6169 #define TAMP_CR2_TAMP2MSK_Pos        (17U)
6170 #define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)           /*!< 0x00020000 */
6171 #define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
6172 #define TAMP_CR2_TAMP1TRG_Pos        (24U)
6173 #define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)           /*!< 0x01000000 */
6174 #define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
6175 #define TAMP_CR2_TAMP2TRG_Pos        (25U)
6176 #define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)           /*!< 0x02000000 */
6177 #define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
6178 
6179 /********************  Bits definition for TAMP_FLTCR register  ***************/
6180 #define TAMP_FLTCR_TAMPFREQ_0        0x00000001U
6181 #define TAMP_FLTCR_TAMPFREQ_1        0x00000002U
6182 #define TAMP_FLTCR_TAMPFREQ_2        0x00000004U
6183 #define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
6184 #define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */
6185 #define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
6186 #define TAMP_FLTCR_TAMPFLT_0         0x00000008U
6187 #define TAMP_FLTCR_TAMPFLT_1         0x00000010U
6188 #define TAMP_FLTCR_TAMPFLT_Pos       (3U)
6189 #define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */
6190 #define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
6191 #define TAMP_FLTCR_TAMPPRCH_0        0x00000020U
6192 #define TAMP_FLTCR_TAMPPRCH_1        0x00000040U
6193 #define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
6194 #define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */
6195 #define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
6196 #define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
6197 #define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */
6198 #define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
6199 
6200 /********************  Bits definition for TAMP_IER register  *****************/
6201 #define TAMP_IER_TAMP1IE_Pos         (0U)
6202 #define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)            /*!< 0x00000001 */
6203 #define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
6204 #define TAMP_IER_TAMP2IE_Pos         (1U)
6205 #define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)            /*!< 0x00000002 */
6206 #define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
6207 #define TAMP_IER_ITAMP3IE_Pos        (18U)
6208 #define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)           /*!< 0x00040000 */
6209 #define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
6210 #define TAMP_IER_ITAMP4IE_Pos        (19U)
6211 #define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)           /*!< 0x00080000 */
6212 #define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk
6213 #define TAMP_IER_ITAMP5IE_Pos        (20U)
6214 #define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)           /*!< 0x00100000 */
6215 #define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
6216 #define TAMP_IER_ITAMP6IE_Pos        (21U)
6217 #define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)           /*!< 0x00200000 */
6218 #define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
6219 
6220 /********************  Bits definition for TAMP_SR register  ******************/
6221 #define TAMP_SR_TAMP1F_Pos           (0U)
6222 #define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)              /*!< 0x00000001 */
6223 #define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
6224 #define TAMP_SR_TAMP2F_Pos           (1U)
6225 #define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)              /*!< 0x00000002 */
6226 #define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
6227 #define TAMP_SR_ITAMP3F_Pos          (18U)
6228 #define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)             /*!< 0x00040000 */
6229 #define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
6230 #define TAMP_SR_ITAMP4F_Pos          (19U)
6231 #define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)             /*!< 0x00080000 */
6232 #define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk
6233 #define TAMP_SR_ITAMP5F_Pos          (20U)
6234 #define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)             /*!< 0x00100000 */
6235 #define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
6236 #define TAMP_SR_ITAMP6F_Pos          (21U)
6237 #define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)             /*!< 0x00200000 */
6238 #define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
6239 
6240 /********************  Bits definition for TAMP_MISR register  ****************/
6241 #define TAMP_MISR_TAMP1MF_Pos        (0U)
6242 #define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */
6243 #define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
6244 #define TAMP_MISR_TAMP2MF_Pos        (1U)
6245 #define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */
6246 #define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
6247 #define TAMP_MISR_ITAMP3MF_Pos       (18U)
6248 #define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)          /*!< 0x00040000 */
6249 #define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
6250 #define TAMP_MISR_ITAMP4MF_Pos       (19U)
6251 #define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)          /*!< 0x00080000 */
6252 #define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk
6253 #define TAMP_MISR_ITAMP5MF_Pos       (20U)
6254 #define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)          /*!< 0x00100000 */
6255 #define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
6256 #define TAMP_MISR_ITAMP6MF_Pos       (21U)
6257 #define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)          /*!< 0x00200000 */
6258 #define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
6259 
6260 /********************  Bits definition for TAMP_SCR register  *****************/
6261 #define TAMP_SCR_CTAMP1F_Pos         (0U)
6262 #define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */
6263 #define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
6264 #define TAMP_SCR_CTAMP2F_Pos         (1U)
6265 #define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */
6266 #define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
6267 #define TAMP_SCR_CITAMP3F_Pos        (18U)
6268 #define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)           /*!< 0x00040000 */
6269 #define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
6270 #define TAMP_SCR_CITAMP4F_Pos        (19U)
6271 #define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)           /*!< 0x00080000 */
6272 #define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk
6273 #define TAMP_SCR_CITAMP5F_Pos        (20U)
6274 #define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)           /*!< 0x00100000 */
6275 #define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
6276 #define TAMP_SCR_CITAMP6F_Pos        (21U)
6277 #define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)           /*!< 0x00200000 */
6278 #define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
6279 
6280 /********************  Bits definition for TAMP_BKP0R register  ***************/
6281 #define TAMP_BKP0R_Pos               (0U)
6282 #define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */
6283 #define TAMP_BKP0R                   TAMP_BKP0R_Msk
6284 
6285 /********************  Bits definition for TAMP_BKP1R register  ***************/
6286 #define TAMP_BKP1R_Pos               (0U)
6287 #define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */
6288 #define TAMP_BKP1R                   TAMP_BKP1R_Msk
6289 
6290 /********************  Bits definition for TAMP_BKP2R register  ***************/
6291 #define TAMP_BKP2R_Pos               (0U)
6292 #define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */
6293 #define TAMP_BKP2R                   TAMP_BKP2R_Msk
6294 
6295 /********************  Bits definition for TAMP_BKP3R register  ***************/
6296 #define TAMP_BKP3R_Pos               (0U)
6297 #define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */
6298 #define TAMP_BKP3R                   TAMP_BKP3R_Msk
6299 
6300 /********************  Bits definition for TAMP_BKP4R register  ***************/
6301 #define TAMP_BKP4R_Pos               (0U)
6302 #define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */
6303 #define TAMP_BKP4R                   TAMP_BKP4R_Msk
6304 
6305 /******************************************************************************/
6306 /*                                                                            */
6307 /*                        Serial Peripheral Interface (SPI)                   */
6308 /*                                                                            */
6309 /******************************************************************************/
6310 /*
6311  * @brief Specific device feature definitions (not present on all devices in the STM32G0 series)
6312  */
6313 #define SPI_I2S_SUPPORT                       /*!< I2S support */
6314 
6315 /*******************  Bit definition for SPI_CR1 register  ********************/
6316 #define SPI_CR1_CPHA_Pos            (0U)
6317 #define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
6318 #define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
6319 #define SPI_CR1_CPOL_Pos            (1U)
6320 #define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
6321 #define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
6322 #define SPI_CR1_MSTR_Pos            (2U)
6323 #define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
6324 #define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
6325 
6326 #define SPI_CR1_BR_Pos              (3U)
6327 #define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
6328 #define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
6329 #define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
6330 #define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
6331 #define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
6332 
6333 #define SPI_CR1_SPE_Pos             (6U)
6334 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
6335 #define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
6336 #define SPI_CR1_LSBFIRST_Pos        (7U)
6337 #define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
6338 #define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
6339 #define SPI_CR1_SSI_Pos             (8U)
6340 #define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
6341 #define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
6342 #define SPI_CR1_SSM_Pos             (9U)
6343 #define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
6344 #define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
6345 #define SPI_CR1_RXONLY_Pos          (10U)
6346 #define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
6347 #define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
6348 #define SPI_CR1_CRCL_Pos            (11U)
6349 #define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
6350 #define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
6351 #define SPI_CR1_CRCNEXT_Pos         (12U)
6352 #define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
6353 #define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
6354 #define SPI_CR1_CRCEN_Pos           (13U)
6355 #define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
6356 #define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
6357 #define SPI_CR1_BIDIOE_Pos          (14U)
6358 #define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
6359 #define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
6360 #define SPI_CR1_BIDIMODE_Pos        (15U)
6361 #define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
6362 #define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
6363 
6364 /*******************  Bit definition for SPI_CR2 register  ********************/
6365 #define SPI_CR2_RXDMAEN_Pos         (0U)
6366 #define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
6367 #define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
6368 #define SPI_CR2_TXDMAEN_Pos         (1U)
6369 #define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
6370 #define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
6371 #define SPI_CR2_SSOE_Pos            (2U)
6372 #define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
6373 #define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
6374 #define SPI_CR2_NSSP_Pos            (3U)
6375 #define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
6376 #define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
6377 #define SPI_CR2_FRF_Pos             (4U)
6378 #define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
6379 #define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
6380 #define SPI_CR2_ERRIE_Pos           (5U)
6381 #define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
6382 #define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
6383 #define SPI_CR2_RXNEIE_Pos          (6U)
6384 #define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
6385 #define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
6386 #define SPI_CR2_TXEIE_Pos           (7U)
6387 #define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
6388 #define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
6389 #define SPI_CR2_DS_Pos              (8U)
6390 #define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
6391 #define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
6392 #define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
6393 #define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
6394 #define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
6395 #define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
6396 #define SPI_CR2_FRXTH_Pos           (12U)
6397 #define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
6398 #define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
6399 #define SPI_CR2_LDMARX_Pos          (13U)
6400 #define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
6401 #define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
6402 #define SPI_CR2_LDMATX_Pos          (14U)
6403 #define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
6404 #define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
6405 
6406 /********************  Bit definition for SPI_SR register  ********************/
6407 #define SPI_SR_RXNE_Pos             (0U)
6408 #define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
6409 #define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
6410 #define SPI_SR_TXE_Pos              (1U)
6411 #define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
6412 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
6413 #define SPI_SR_CHSIDE_Pos           (2U)
6414 #define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
6415 #define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
6416 #define SPI_SR_UDR_Pos              (3U)
6417 #define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
6418 #define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
6419 #define SPI_SR_CRCERR_Pos           (4U)
6420 #define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
6421 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
6422 #define SPI_SR_MODF_Pos             (5U)
6423 #define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
6424 #define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
6425 #define SPI_SR_OVR_Pos              (6U)
6426 #define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
6427 #define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
6428 #define SPI_SR_BSY_Pos              (7U)
6429 #define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
6430 #define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
6431 #define SPI_SR_FRE_Pos              (8U)
6432 #define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
6433 #define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
6434 #define SPI_SR_FRLVL_Pos            (9U)
6435 #define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
6436 #define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
6437 #define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
6438 #define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
6439 #define SPI_SR_FTLVL_Pos            (11U)
6440 #define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
6441 #define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
6442 #define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
6443 #define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
6444 
6445 /********************  Bit definition for SPI_DR register  ********************/
6446 #define SPI_DR_DR_Pos               (0U)
6447 #define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
6448 #define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
6449 
6450 /*******************  Bit definition for SPI_CRCPR register  ******************/
6451 #define SPI_CRCPR_CRCPOLY_Pos       (0U)
6452 #define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
6453 #define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
6454 
6455 /******************  Bit definition for SPI_RXCRCR register  ******************/
6456 #define SPI_RXCRCR_RXCRC_Pos        (0U)
6457 #define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
6458 #define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
6459 
6460 /******************  Bit definition for SPI_TXCRCR register  ******************/
6461 #define SPI_TXCRCR_TXCRC_Pos        (0U)
6462 #define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
6463 #define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
6464 
6465 /******************  Bit definition for SPI_I2SCFGR register  *****************/
6466 #define SPI_I2SCFGR_CHLEN_Pos       (0U)
6467 #define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
6468 #define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
6469 #define SPI_I2SCFGR_DATLEN_Pos      (1U)
6470 #define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
6471 #define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
6472 #define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
6473 #define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
6474 #define SPI_I2SCFGR_CKPOL_Pos       (3U)
6475 #define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
6476 #define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
6477 #define SPI_I2SCFGR_I2SSTD_Pos      (4U)
6478 #define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
6479 #define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
6480 #define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
6481 #define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
6482 #define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
6483 #define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
6484 #define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
6485 #define SPI_I2SCFGR_I2SCFG_Pos      (8U)
6486 #define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
6487 #define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
6488 #define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
6489 #define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
6490 #define SPI_I2SCFGR_I2SE_Pos        (10U)
6491 #define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
6492 #define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
6493 #define SPI_I2SCFGR_I2SMOD_Pos      (11U)
6494 #define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
6495 #define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
6496 #define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
6497 #define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
6498 #define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
6499 
6500 /******************  Bit definition for SPI_I2SPR register  *******************/
6501 #define SPI_I2SPR_I2SDIV_Pos        (0U)
6502 #define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
6503 #define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
6504 #define SPI_I2SPR_ODD_Pos           (8U)
6505 #define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
6506 #define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
6507 #define SPI_I2SPR_MCKOE_Pos         (9U)
6508 #define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
6509 #define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
6510 
6511 /******************************************************************************/
6512 /*                                                                            */
6513 /*                                 SYSCFG                                     */
6514 /*                                                                            */
6515 /******************************************************************************/
6516 /*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
6517 #define SYSCFG_CFGR1_MEM_MODE_Pos             (0U)
6518 #define SYSCFG_CFGR1_MEM_MODE_Msk             (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
6519 #define SYSCFG_CFGR1_MEM_MODE                 SYSCFG_CFGR1_MEM_MODE_Msk            /*!< SYSCFG_Memory Remap Config */
6520 #define SYSCFG_CFGR1_MEM_MODE_0               (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
6521 #define SYSCFG_CFGR1_MEM_MODE_1               (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
6522 #define SYSCFG_CFGR1_PA11_RMP_Pos             (3U)
6523 #define SYSCFG_CFGR1_PA11_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
6524 #define SYSCFG_CFGR1_PA11_RMP                 SYSCFG_CFGR1_PA11_RMP_Msk            /*!< PA11 Remap */
6525 #define SYSCFG_CFGR1_PA12_RMP_Pos             (4U)
6526 #define SYSCFG_CFGR1_PA12_RMP_Msk             (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
6527 #define SYSCFG_CFGR1_PA12_RMP                 SYSCFG_CFGR1_PA12_RMP_Msk            /*!< PA12 Remap */
6528 #define SYSCFG_CFGR1_IR_POL_Pos               (5U)
6529 #define SYSCFG_CFGR1_IR_POL_Msk               (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
6530 #define SYSCFG_CFGR1_IR_POL                   SYSCFG_CFGR1_IR_POL_Msk            /*!< IROut Polarity Selection */
6531 #define SYSCFG_CFGR1_IR_MOD_Pos               (6U)
6532 #define SYSCFG_CFGR1_IR_MOD_Msk               (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
6533 #define SYSCFG_CFGR1_IR_MOD                   SYSCFG_CFGR1_IR_MOD_Msk            /*!< IRDA Modulation Envelope signal source selection */
6534 #define SYSCFG_CFGR1_IR_MOD_0                 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
6535 #define SYSCFG_CFGR1_IR_MOD_1                 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
6536 #define SYSCFG_CFGR1_BOOSTEN_Pos              (8U)
6537 #define SYSCFG_CFGR1_BOOSTEN_Msk              (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
6538 #define SYSCFG_CFGR1_BOOSTEN                  SYSCFG_CFGR1_BOOSTEN_Msk            /*!< I/O analog switch voltage booster enable */
6539 #define SYSCFG_CFGR1_UCPD1_STROBE_Pos         (9U)
6540 #define SYSCFG_CFGR1_UCPD1_STROBE_Msk         (0x1UL << SYSCFG_CFGR1_UCPD1_STROBE_Pos) /*!< 0x00000200 */
6541 #define SYSCFG_CFGR1_UCPD1_STROBE             SYSCFG_CFGR1_UCPD1_STROBE_Msk            /*!< Strobe signal bit for UCPD1 */
6542 #define SYSCFG_CFGR1_UCPD2_STROBE_Pos         (10U)
6543 #define SYSCFG_CFGR1_UCPD2_STROBE_Msk         (0x1UL << SYSCFG_CFGR1_UCPD2_STROBE_Pos) /*!< 0x00000400 */
6544 #define SYSCFG_CFGR1_UCPD2_STROBE             SYSCFG_CFGR1_UCPD2_STROBE_Msk            /*!< Strobe signal bit for UCPD2 */
6545 #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos          (16U)
6546 #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)  /*!< 0x00010000 */
6547 #define SYSCFG_CFGR1_I2C_PB6_FMP              SYSCFG_CFGR1_I2C_PB6_FMP_Msk             /*!< I2C PB6 Fast mode plus */
6548 #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos          (17U)
6549 #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)  /*!< 0x00020000 */
6550 #define SYSCFG_CFGR1_I2C_PB7_FMP              SYSCFG_CFGR1_I2C_PB7_FMP_Msk             /*!< I2C PB7 Fast mode plus */
6551 #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos          (18U)
6552 #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)  /*!< 0x00040000 */
6553 #define SYSCFG_CFGR1_I2C_PB8_FMP              SYSCFG_CFGR1_I2C_PB8_FMP_Msk             /*!< I2C PB8 Fast mode plus */
6554 #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos          (19U)
6555 #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)  /*!< 0x00080000 */
6556 #define SYSCFG_CFGR1_I2C_PB9_FMP              SYSCFG_CFGR1_I2C_PB9_FMP_Msk             /*!< I2C PB9 Fast mode plus */
6557 #define SYSCFG_CFGR1_I2C1_FMP_Pos             (20U)
6558 #define SYSCFG_CFGR1_I2C1_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)     /*!< 0x00100000 */
6559 #define SYSCFG_CFGR1_I2C1_FMP                 SYSCFG_CFGR1_I2C1_FMP_Msk                /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7  */
6560 #define SYSCFG_CFGR1_I2C2_FMP_Pos             (21U)
6561 #define SYSCFG_CFGR1_I2C2_FMP_Msk             (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)     /*!< 0x00200000 */
6562 #define SYSCFG_CFGR1_I2C2_FMP                 SYSCFG_CFGR1_I2C2_FMP_Msk                /*!< Enable I2C2 Fast mode plus  */
6563 #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos          (22U)
6564 #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk          (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos)  /*!< 0x00400000 */
6565 #define SYSCFG_CFGR1_I2C_PA9_FMP              SYSCFG_CFGR1_I2C_PA9_FMP_Msk             /*!< Enable Fast Mode Plus on PA9  */
6566 #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos         (23U)
6567 #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk         (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
6568 #define SYSCFG_CFGR1_I2C_PA10_FMP             SYSCFG_CFGR1_I2C_PA10_FMP_Msk            /*!< Enable Fast Mode Plus on PA10 */
6569 
6570 /******************  Bit definition for SYSCFG_CFGR2 register  ****************/
6571 #define SYSCFG_CFGR2_CLL_Pos                  (0U)
6572 #define SYSCFG_CFGR2_CLL_Msk                  (0x1UL << SYSCFG_CFGR2_CLL_Pos)   /*!< 0x00000001 */
6573 #define SYSCFG_CFGR2_CLL                      SYSCFG_CFGR2_CLL_Msk              /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
6574 #define SYSCFG_CFGR2_SPL_Pos                  (1U)
6575 #define SYSCFG_CFGR2_SPL_Msk                  (0x1UL << SYSCFG_CFGR2_SPL_Pos)   /*!< 0x00000002 */
6576 #define SYSCFG_CFGR2_SPL                      SYSCFG_CFGR2_SPL_Msk              /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
6577 #define SYSCFG_CFGR2_PVDL_Pos                 (2U)
6578 #define SYSCFG_CFGR2_PVDL_Msk                 (0x1UL << SYSCFG_CFGR2_PVDL_Pos)  /*!< 0x00000004 */
6579 #define SYSCFG_CFGR2_PVDL                     SYSCFG_CFGR2_PVDL_Msk             /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
6580 #define SYSCFG_CFGR2_ECCL_Pos                 (3U)
6581 #define SYSCFG_CFGR2_ECCL_Msk                 (0x1UL << SYSCFG_CFGR2_ECCL_Pos)  /*!< 0x00000008 */
6582 #define SYSCFG_CFGR2_ECCL                     SYSCFG_CFGR2_ECCL_Msk             /*!< ECCL */
6583 #define SYSCFG_CFGR2_SPF_Pos                  (8U)
6584 #define SYSCFG_CFGR2_SPF_Msk                  (0x1UL << SYSCFG_CFGR2_SPF_Pos)   /*!< 0x00000100 */
6585 #define SYSCFG_CFGR2_SPF                      SYSCFG_CFGR2_SPF_Msk              /*!< SRAM Parity error flag */
6586 #define SYSCFG_CFGR2_SRAM_PE                  SYSCFG_CFGR2_SPF                  /*!< SRAM Parity error flag (define maintained for legacy purpose) */
6587 
6588 /*****************  Bit definition for SYSCFG_ITLINEx ISR Wrapper register  ****************/
6589 #define SYSCFG_ITLINE0_SR_EWDG_Pos            (0U)
6590 #define SYSCFG_ITLINE0_SR_EWDG_Msk            (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
6591 #define SYSCFG_ITLINE0_SR_EWDG                SYSCFG_ITLINE0_SR_EWDG_Msk       /*!< EWDG interrupt */
6592 #define SYSCFG_ITLINE1_SR_PVDOUT_Pos          (0U)
6593 #define SYSCFG_ITLINE1_SR_PVDOUT_Msk          (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
6594 #define SYSCFG_ITLINE1_SR_PVDOUT              SYSCFG_ITLINE1_SR_PVDOUT_Msk     /*!< Power voltage detection -> exti[16] Interrupt */
6595 #define SYSCFG_ITLINE2_SR_TAMPER_Pos          (0U)
6596 #define SYSCFG_ITLINE2_SR_TAMPER_Msk          (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
6597 #define SYSCFG_ITLINE2_SR_TAMPER              SYSCFG_ITLINE2_SR_TAMPER_Msk     /*!< TAMPER -> exti[21] interrupt */
6598 #define SYSCFG_ITLINE2_SR_RTC_Pos             (1U)
6599 #define SYSCFG_ITLINE2_SR_RTC_Msk             (0x1UL << SYSCFG_ITLINE2_SR_RTC_Pos) /*!< 0x00000002 */
6600 #define SYSCFG_ITLINE2_SR_RTC                 SYSCFG_ITLINE2_SR_RTC_Msk /*!< RTC -> exti[19] interrupt .... */
6601 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos       (0U)
6602 #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk       (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
6603 #define SYSCFG_ITLINE3_SR_FLASH_ECC           SYSCFG_ITLINE3_SR_FLASH_ECC_Msk  /*!< Flash ITF ECC interrupt */
6604 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos       (1U)
6605 #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk       (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
6606 #define SYSCFG_ITLINE3_SR_FLASH_ITF           SYSCFG_ITLINE3_SR_FLASH_ITF_Msk  /*!< FLASH ITF interrupt */
6607 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos        (0U)
6608 #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk        (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
6609 #define SYSCFG_ITLINE4_SR_CLK_CTRL            SYSCFG_ITLINE4_SR_CLK_CTRL_Msk   /*!< RCC interrupt */
6610 #define SYSCFG_ITLINE5_SR_EXTI0_Pos           (0U)
6611 #define SYSCFG_ITLINE5_SR_EXTI0_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
6612 #define SYSCFG_ITLINE5_SR_EXTI0               SYSCFG_ITLINE5_SR_EXTI0_Msk      /*!< External Interrupt 0 */
6613 #define SYSCFG_ITLINE5_SR_EXTI1_Pos           (1U)
6614 #define SYSCFG_ITLINE5_SR_EXTI1_Msk           (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
6615 #define SYSCFG_ITLINE5_SR_EXTI1               SYSCFG_ITLINE5_SR_EXTI1_Msk      /*!< External Interrupt 1 */
6616 #define SYSCFG_ITLINE6_SR_EXTI2_Pos           (0U)
6617 #define SYSCFG_ITLINE6_SR_EXTI2_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
6618 #define SYSCFG_ITLINE6_SR_EXTI2               SYSCFG_ITLINE6_SR_EXTI2_Msk      /*!< External Interrupt 2 */
6619 #define SYSCFG_ITLINE6_SR_EXTI3_Pos           (1U)
6620 #define SYSCFG_ITLINE6_SR_EXTI3_Msk           (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
6621 #define SYSCFG_ITLINE6_SR_EXTI3               SYSCFG_ITLINE6_SR_EXTI3_Msk      /*!< External Interrupt 3 */
6622 #define SYSCFG_ITLINE7_SR_EXTI4_Pos           (0U)
6623 #define SYSCFG_ITLINE7_SR_EXTI4_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
6624 #define SYSCFG_ITLINE7_SR_EXTI4               SYSCFG_ITLINE7_SR_EXTI4_Msk      /*!< External Interrupt 4 */
6625 #define SYSCFG_ITLINE7_SR_EXTI5_Pos           (1U)
6626 #define SYSCFG_ITLINE7_SR_EXTI5_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
6627 #define SYSCFG_ITLINE7_SR_EXTI5               SYSCFG_ITLINE7_SR_EXTI5_Msk      /*!< External Interrupt 5 */
6628 #define SYSCFG_ITLINE7_SR_EXTI6_Pos           (2U)
6629 #define SYSCFG_ITLINE7_SR_EXTI6_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
6630 #define SYSCFG_ITLINE7_SR_EXTI6               SYSCFG_ITLINE7_SR_EXTI6_Msk      /*!< External Interrupt 6 */
6631 #define SYSCFG_ITLINE7_SR_EXTI7_Pos           (3U)
6632 #define SYSCFG_ITLINE7_SR_EXTI7_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
6633 #define SYSCFG_ITLINE7_SR_EXTI7               SYSCFG_ITLINE7_SR_EXTI7_Msk      /*!< External Interrupt 7 */
6634 #define SYSCFG_ITLINE7_SR_EXTI8_Pos           (4U)
6635 #define SYSCFG_ITLINE7_SR_EXTI8_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
6636 #define SYSCFG_ITLINE7_SR_EXTI8               SYSCFG_ITLINE7_SR_EXTI8_Msk      /*!< External Interrupt 8 */
6637 #define SYSCFG_ITLINE7_SR_EXTI9_Pos           (5U)
6638 #define SYSCFG_ITLINE7_SR_EXTI9_Msk           (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
6639 #define SYSCFG_ITLINE7_SR_EXTI9               SYSCFG_ITLINE7_SR_EXTI9_Msk      /*!< External Interrupt 9 */
6640 #define SYSCFG_ITLINE7_SR_EXTI10_Pos          (6U)
6641 #define SYSCFG_ITLINE7_SR_EXTI10_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
6642 #define SYSCFG_ITLINE7_SR_EXTI10              SYSCFG_ITLINE7_SR_EXTI10_Msk     /*!< External Interrupt 10 */
6643 #define SYSCFG_ITLINE7_SR_EXTI11_Pos          (7U)
6644 #define SYSCFG_ITLINE7_SR_EXTI11_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
6645 #define SYSCFG_ITLINE7_SR_EXTI11              SYSCFG_ITLINE7_SR_EXTI11_Msk     /*!< External Interrupt 11 */
6646 #define SYSCFG_ITLINE7_SR_EXTI12_Pos          (8U)
6647 #define SYSCFG_ITLINE7_SR_EXTI12_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
6648 #define SYSCFG_ITLINE7_SR_EXTI12              SYSCFG_ITLINE7_SR_EXTI12_Msk     /*!< External Interrupt 12 */
6649 #define SYSCFG_ITLINE7_SR_EXTI13_Pos          (9U)
6650 #define SYSCFG_ITLINE7_SR_EXTI13_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
6651 #define SYSCFG_ITLINE7_SR_EXTI13              SYSCFG_ITLINE7_SR_EXTI13_Msk     /*!< External Interrupt 13 */
6652 #define SYSCFG_ITLINE7_SR_EXTI14_Pos          (10U)
6653 #define SYSCFG_ITLINE7_SR_EXTI14_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
6654 #define SYSCFG_ITLINE7_SR_EXTI14              SYSCFG_ITLINE7_SR_EXTI14_Msk     /*!< External Interrupt 14 */
6655 #define SYSCFG_ITLINE7_SR_EXTI15_Pos          (11U)
6656 #define SYSCFG_ITLINE7_SR_EXTI15_Msk          (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
6657 #define SYSCFG_ITLINE7_SR_EXTI15              SYSCFG_ITLINE7_SR_EXTI15_Msk     /*!< External Interrupt 15 */
6658 #define SYSCFG_ITLINE8_SR_UCPD1_Pos           (0U)
6659 #define SYSCFG_ITLINE8_SR_UCPD1_Msk           (0x1UL << SYSCFG_ITLINE8_SR_UCPD1_Pos) /*!< 0x00000001 */
6660 #define SYSCFG_ITLINE8_SR_UCPD1               SYSCFG_ITLINE8_SR_UCPD1_Msk       /*!< UCPD1 -> exti[32] Interrupt */
6661 #define SYSCFG_ITLINE8_SR_UCPD2_Pos           (1U)
6662 #define SYSCFG_ITLINE8_SR_UCPD2_Msk           (0x1UL << SYSCFG_ITLINE8_SR_UCPD2_Pos) /*!< 0x00000002 */
6663 #define SYSCFG_ITLINE8_SR_UCPD2               SYSCFG_ITLINE8_SR_UCPD2_Msk       /*!< UCPD2 -> exti[33] Interrupt */
6664 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos        (0U)
6665 #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk        (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
6666 #define SYSCFG_ITLINE9_SR_DMA1_CH1            SYSCFG_ITLINE9_SR_DMA1_CH1_Msk   /*!< DMA1 Channel 1 Interrupt */
6667 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos       (0U)
6668 #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
6669 #define SYSCFG_ITLINE10_SR_DMA1_CH2           SYSCFG_ITLINE10_SR_DMA1_CH2_Msk  /*!< DMA1 Channel 2 Interrupt */
6670 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos       (1U)
6671 #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk       (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
6672 #define SYSCFG_ITLINE10_SR_DMA1_CH3           SYSCFG_ITLINE10_SR_DMA1_CH3_Msk  /*!< DMA2 Channel 3 Interrupt */
6673 #define SYSCFG_ITLINE11_SR_DMAMUX1_Pos        (0U)
6674 #define SYSCFG_ITLINE11_SR_DMAMUX1_Msk        (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
6675 #define SYSCFG_ITLINE11_SR_DMAMUX1            SYSCFG_ITLINE11_SR_DMAMUX1_Msk    /*!< DMAMUX Interrupt */
6676 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos       (1U)
6677 #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
6678 #define SYSCFG_ITLINE11_SR_DMA1_CH4           SYSCFG_ITLINE11_SR_DMA1_CH4_Msk  /*!< DMA1 Channel 4 Interrupt */
6679 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos       (2U)
6680 #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
6681 #define SYSCFG_ITLINE11_SR_DMA1_CH5           SYSCFG_ITLINE11_SR_DMA1_CH5_Msk  /*!< DMA1 Channel 5 Interrupt */
6682 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Pos       (3U)
6683 #define SYSCFG_ITLINE11_SR_DMA1_CH6_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH6_Pos) /*!< 0x00000008 */
6684 #define SYSCFG_ITLINE11_SR_DMA1_CH6           SYSCFG_ITLINE11_SR_DMA1_CH6_Msk  /*!< DMA1 Channel 6 Interrupt */
6685 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Pos       (4U)
6686 #define SYSCFG_ITLINE11_SR_DMA1_CH7_Msk       (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH7_Pos) /*!< 0x00000010 */
6687 #define SYSCFG_ITLINE11_SR_DMA1_CH7           SYSCFG_ITLINE11_SR_DMA1_CH7_Msk  /*!< DMA1 Channel 7 Interrupt */
6688 #define SYSCFG_ITLINE12_SR_ADC_Pos            (0U)
6689 #define SYSCFG_ITLINE12_SR_ADC_Msk            (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
6690 #define SYSCFG_ITLINE12_SR_ADC                SYSCFG_ITLINE12_SR_ADC_Msk       /*!< ADC Interrupt */
6691 #define SYSCFG_ITLINE12_SR_COMP1_Pos          (1U)
6692 #define SYSCFG_ITLINE12_SR_COMP1_Msk          (0x1UL << SYSCFG_ITLINE12_SR_COMP1_Pos) /*!< 0x00000002 */
6693 #define SYSCFG_ITLINE12_SR_COMP1              SYSCFG_ITLINE12_SR_COMP1_Msk     /*!< COMP1 Interrupt -> exti[17] */
6694 #define SYSCFG_ITLINE12_SR_COMP2_Pos          (2U)
6695 #define SYSCFG_ITLINE12_SR_COMP2_Msk          (0x1UL << SYSCFG_ITLINE12_SR_COMP2_Pos) /*!< 0x00000004 */
6696 #define SYSCFG_ITLINE12_SR_COMP2              SYSCFG_ITLINE12_SR_COMP2_Msk     /*!< COMP2 Interrupt -> exti[18] */
6697 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos       (0U)
6698 #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
6699 #define SYSCFG_ITLINE13_SR_TIM1_CCU           SYSCFG_ITLINE13_SR_TIM1_CCU_Msk  /*!< TIM1 CCU Interrupt */
6700 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos       (1U)
6701 #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
6702 #define SYSCFG_ITLINE13_SR_TIM1_TRG           SYSCFG_ITLINE13_SR_TIM1_TRG_Msk  /*!< TIM1 TRG Interrupt */
6703 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos       (2U)
6704 #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
6705 #define SYSCFG_ITLINE13_SR_TIM1_UPD           SYSCFG_ITLINE13_SR_TIM1_UPD_Msk  /*!< TIM1 UPD Interrupt */
6706 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos       (3U)
6707 #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk       (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
6708 #define SYSCFG_ITLINE13_SR_TIM1_BRK           SYSCFG_ITLINE13_SR_TIM1_BRK_Msk  /*!< TIM1 BRK Interrupt */
6709 #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos        (0U)
6710 #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk        (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
6711 #define SYSCFG_ITLINE14_SR_TIM1_CC            SYSCFG_ITLINE14_SR_TIM1_CC_Msk   /*!< TIM1 CC Interrupt */
6712 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos       (0U)
6713 #define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk       (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
6714 #define SYSCFG_ITLINE15_SR_TIM2_GLB           SYSCFG_ITLINE15_SR_TIM2_GLB_Msk  /*!< TIM2 GLB Interrupt */
6715 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos       (0U)
6716 #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk       (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
6717 #define SYSCFG_ITLINE16_SR_TIM3_GLB           SYSCFG_ITLINE16_SR_TIM3_GLB_Msk  /*!< TIM3 GLB Interrupt */
6718 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Pos       (0U)
6719 #define SYSCFG_ITLINE17_SR_TIM6_GLB_Msk       (0x1UL << SYSCFG_ITLINE17_SR_TIM6_GLB_Pos) /*!< 0x00000001 */
6720 #define SYSCFG_ITLINE17_SR_TIM6_GLB           SYSCFG_ITLINE17_SR_TIM6_GLB_Msk  /*!< TIM6 GLB Interrupt */
6721 #define SYSCFG_ITLINE17_SR_DAC_Pos            (1U)
6722 #define SYSCFG_ITLINE17_SR_DAC_Msk            (0x1UL << SYSCFG_ITLINE17_SR_DAC_Pos) /*!< 0x00000002 */
6723 #define SYSCFG_ITLINE17_SR_DAC                SYSCFG_ITLINE17_SR_DAC_Msk       /*!< DAC Interrupt */
6724 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos     (2U)
6725 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk     (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */
6726 #define SYSCFG_ITLINE17_SR_LPTIM1_GLB         SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */
6727 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Pos       (0U)
6728 #define SYSCFG_ITLINE18_SR_TIM7_GLB_Msk       (0x1UL << SYSCFG_ITLINE18_SR_TIM7_GLB_Pos) /*!< 0x00000001 */
6729 #define SYSCFG_ITLINE18_SR_TIM7_GLB           SYSCFG_ITLINE18_SR_TIM7_GLB_Msk  /*!< TIM7 GLB Interrupt */
6730 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos     (1U)
6731 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk     (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */
6732 #define SYSCFG_ITLINE18_SR_LPTIM2_GLB         SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */
6733 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos      (0U)
6734 #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk      (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
6735 #define SYSCFG_ITLINE19_SR_TIM14_GLB          SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
6736 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Pos      (0U)
6737 #define SYSCFG_ITLINE20_SR_TIM15_GLB_Msk      (0x1UL << SYSCFG_ITLINE20_SR_TIM15_GLB_Pos) /*!< 0x00000001 */
6738 #define SYSCFG_ITLINE20_SR_TIM15_GLB          SYSCFG_ITLINE20_SR_TIM15_GLB_Msk /*!< TIM15 GLB Interrupt */
6739 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos      (0U)
6740 #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk      (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
6741 #define SYSCFG_ITLINE21_SR_TIM16_GLB          SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
6742 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos      (0U)
6743 #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk      (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
6744 #define SYSCFG_ITLINE22_SR_TIM17_GLB          SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
6745 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos       (0U)
6746 #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk       (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
6747 #define SYSCFG_ITLINE23_SR_I2C1_GLB           SYSCFG_ITLINE23_SR_I2C1_GLB_Msk  /*!< I2C1 GLB Interrupt -> exti[23] */
6748 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos       (0U)
6749 #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk       (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
6750 #define SYSCFG_ITLINE24_SR_I2C2_GLB           SYSCFG_ITLINE24_SR_I2C2_GLB_Msk  /*!< I2C2 GLB Interrupt  -> exti[22]*/
6751 #define SYSCFG_ITLINE25_SR_SPI1_Pos           (0U)
6752 #define SYSCFG_ITLINE25_SR_SPI1_Msk           (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
6753 #define SYSCFG_ITLINE25_SR_SPI1               SYSCFG_ITLINE25_SR_SPI1_Msk      /*!< SPI1 Interrupt */
6754 #define SYSCFG_ITLINE26_SR_SPI2_Pos           (0U)
6755 #define SYSCFG_ITLINE26_SR_SPI2_Msk           (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
6756 #define SYSCFG_ITLINE26_SR_SPI2               SYSCFG_ITLINE26_SR_SPI2_Msk      /*!< SPI2  Interrupt */
6757 #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos     (0U)
6758 #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk     (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
6759 #define SYSCFG_ITLINE27_SR_USART1_GLB         SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
6760 #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos     (0U)
6761 #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk     (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
6762 #define SYSCFG_ITLINE28_SR_USART2_GLB         SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
6763 #define SYSCFG_ITLINE29_SR_USART3_GLB_Pos     (0U)
6764 #define SYSCFG_ITLINE29_SR_USART3_GLB_Msk     (0x1UL << SYSCFG_ITLINE29_SR_USART3_GLB_Pos) /*!< 0x00000001 */
6765 #define SYSCFG_ITLINE29_SR_USART3_GLB         SYSCFG_ITLINE29_SR_USART3_GLB_Msk /*!< USART3 GLB Interrupt */
6766 #define SYSCFG_ITLINE29_SR_USART4_GLB_Pos     (1U)
6767 #define SYSCFG_ITLINE29_SR_USART4_GLB_Msk     (0x1UL << SYSCFG_ITLINE29_SR_USART4_GLB_Pos) /*!< 0x00000002 */
6768 #define SYSCFG_ITLINE29_SR_USART4_GLB         SYSCFG_ITLINE29_SR_USART4_GLB_Msk /*!< USART4 GLB Interrupt */
6769 #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos    (2U)
6770 #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk    (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */
6771 #define SYSCFG_ITLINE29_SR_LPUART1_GLB        SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */
6772 #define SYSCFG_ITLINE30_SR_CEC_Pos            (0U)
6773 #define SYSCFG_ITLINE30_SR_CEC_Msk            (0x1UL << SYSCFG_ITLINE30_SR_CEC_Pos) /*!< 0x00000001 */
6774 #define SYSCFG_ITLINE30_SR_CEC                SYSCFG_ITLINE30_SR_CEC_Msk       /*!< CEC Interrupt-> exti[27] */
6775 
6776 /******************************************************************************/
6777 /*                                                                            */
6778 /*                                    TIM                                     */
6779 /*                                                                            */
6780 /******************************************************************************/
6781 /*******************  Bit definition for TIM_CR1 register  ********************/
6782 #define TIM_CR1_CEN_Pos           (0U)
6783 #define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
6784 #define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
6785 #define TIM_CR1_UDIS_Pos          (1U)
6786 #define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
6787 #define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
6788 #define TIM_CR1_URS_Pos           (2U)
6789 #define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
6790 #define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
6791 #define TIM_CR1_OPM_Pos           (3U)
6792 #define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
6793 #define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
6794 #define TIM_CR1_DIR_Pos           (4U)
6795 #define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
6796 #define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
6797 
6798 #define TIM_CR1_CMS_Pos           (5U)
6799 #define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
6800 #define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
6801 #define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
6802 #define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
6803 
6804 #define TIM_CR1_ARPE_Pos          (7U)
6805 #define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
6806 #define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
6807 
6808 #define TIM_CR1_CKD_Pos           (8U)
6809 #define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
6810 #define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
6811 #define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
6812 #define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
6813 
6814 #define TIM_CR1_UIFREMAP_Pos      (11U)
6815 #define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
6816 #define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
6817 
6818 /*******************  Bit definition for TIM_CR2 register  ********************/
6819 #define TIM_CR2_CCPC_Pos          (0U)
6820 #define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
6821 #define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
6822 #define TIM_CR2_CCUS_Pos          (2U)
6823 #define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
6824 #define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
6825 #define TIM_CR2_CCDS_Pos          (3U)
6826 #define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
6827 #define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
6828 
6829 #define TIM_CR2_MMS_Pos           (4U)
6830 #define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
6831 #define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
6832 #define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
6833 #define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
6834 #define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
6835 
6836 #define TIM_CR2_TI1S_Pos          (7U)
6837 #define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
6838 #define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
6839 #define TIM_CR2_OIS1_Pos          (8U)
6840 #define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
6841 #define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
6842 #define TIM_CR2_OIS1N_Pos         (9U)
6843 #define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
6844 #define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
6845 #define TIM_CR2_OIS2_Pos          (10U)
6846 #define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
6847 #define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
6848 #define TIM_CR2_OIS2N_Pos         (11U)
6849 #define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
6850 #define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
6851 #define TIM_CR2_OIS3_Pos          (12U)
6852 #define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
6853 #define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
6854 #define TIM_CR2_OIS3N_Pos         (13U)
6855 #define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
6856 #define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
6857 #define TIM_CR2_OIS4_Pos          (14U)
6858 #define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
6859 #define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
6860 #define TIM_CR2_OIS5_Pos          (16U)
6861 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
6862 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
6863 #define TIM_CR2_OIS6_Pos          (18U)
6864 #define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
6865 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
6866 
6867 #define TIM_CR2_MMS2_Pos          (20U)
6868 #define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
6869 #define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
6870 #define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
6871 #define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
6872 #define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
6873 #define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
6874 
6875 /*******************  Bit definition for TIM_SMCR register  *******************/
6876 #define TIM_SMCR_SMS_Pos          (0U)
6877 #define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
6878 #define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
6879 #define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
6880 #define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
6881 #define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
6882 #define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
6883 
6884 #define TIM_SMCR_OCCS_Pos         (3U)
6885 #define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
6886 #define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
6887 
6888 #define TIM_SMCR_TS_Pos           (4U)
6889 #define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
6890 #define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
6891 #define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
6892 #define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
6893 #define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
6894 #define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
6895 #define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
6896 
6897 #define TIM_SMCR_MSM_Pos          (7U)
6898 #define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
6899 #define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
6900 
6901 #define TIM_SMCR_ETF_Pos          (8U)
6902 #define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
6903 #define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
6904 #define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
6905 #define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
6906 #define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
6907 #define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
6908 
6909 #define TIM_SMCR_ETPS_Pos         (12U)
6910 #define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
6911 #define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
6912 #define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
6913 #define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
6914 
6915 #define TIM_SMCR_ECE_Pos          (14U)
6916 #define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
6917 #define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
6918 #define TIM_SMCR_ETP_Pos          (15U)
6919 #define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
6920 #define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
6921 
6922 /*******************  Bit definition for TIM_DIER register  *******************/
6923 #define TIM_DIER_UIE_Pos          (0U)
6924 #define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
6925 #define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
6926 #define TIM_DIER_CC1IE_Pos        (1U)
6927 #define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
6928 #define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
6929 #define TIM_DIER_CC2IE_Pos        (2U)
6930 #define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
6931 #define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
6932 #define TIM_DIER_CC3IE_Pos        (3U)
6933 #define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
6934 #define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
6935 #define TIM_DIER_CC4IE_Pos        (4U)
6936 #define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
6937 #define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
6938 #define TIM_DIER_COMIE_Pos        (5U)
6939 #define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
6940 #define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
6941 #define TIM_DIER_TIE_Pos          (6U)
6942 #define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
6943 #define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
6944 #define TIM_DIER_BIE_Pos          (7U)
6945 #define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
6946 #define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
6947 #define TIM_DIER_UDE_Pos          (8U)
6948 #define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
6949 #define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
6950 #define TIM_DIER_CC1DE_Pos        (9U)
6951 #define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
6952 #define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
6953 #define TIM_DIER_CC2DE_Pos        (10U)
6954 #define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
6955 #define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
6956 #define TIM_DIER_CC3DE_Pos        (11U)
6957 #define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
6958 #define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
6959 #define TIM_DIER_CC4DE_Pos        (12U)
6960 #define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
6961 #define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
6962 #define TIM_DIER_COMDE_Pos        (13U)
6963 #define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
6964 #define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
6965 #define TIM_DIER_TDE_Pos          (14U)
6966 #define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
6967 #define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
6968 
6969 /********************  Bit definition for TIM_SR register  ********************/
6970 #define TIM_SR_UIF_Pos            (0U)
6971 #define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
6972 #define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
6973 #define TIM_SR_CC1IF_Pos          (1U)
6974 #define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
6975 #define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
6976 #define TIM_SR_CC2IF_Pos          (2U)
6977 #define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
6978 #define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
6979 #define TIM_SR_CC3IF_Pos          (3U)
6980 #define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
6981 #define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
6982 #define TIM_SR_CC4IF_Pos          (4U)
6983 #define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
6984 #define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
6985 #define TIM_SR_COMIF_Pos          (5U)
6986 #define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
6987 #define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
6988 #define TIM_SR_TIF_Pos            (6U)
6989 #define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
6990 #define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
6991 #define TIM_SR_BIF_Pos            (7U)
6992 #define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
6993 #define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
6994 #define TIM_SR_B2IF_Pos           (8U)
6995 #define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
6996 #define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
6997 #define TIM_SR_CC1OF_Pos          (9U)
6998 #define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
6999 #define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
7000 #define TIM_SR_CC2OF_Pos          (10U)
7001 #define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
7002 #define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
7003 #define TIM_SR_CC3OF_Pos          (11U)
7004 #define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
7005 #define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
7006 #define TIM_SR_CC4OF_Pos          (12U)
7007 #define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
7008 #define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
7009 #define TIM_SR_SBIF_Pos           (13U)
7010 #define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
7011 #define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
7012 #define TIM_SR_CC5IF_Pos          (16U)
7013 #define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
7014 #define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
7015 #define TIM_SR_CC6IF_Pos          (17U)
7016 #define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
7017 #define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
7018 
7019 
7020 /*******************  Bit definition for TIM_EGR register  ********************/
7021 #define TIM_EGR_UG_Pos            (0U)
7022 #define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
7023 #define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
7024 #define TIM_EGR_CC1G_Pos          (1U)
7025 #define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
7026 #define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
7027 #define TIM_EGR_CC2G_Pos          (2U)
7028 #define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
7029 #define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
7030 #define TIM_EGR_CC3G_Pos          (3U)
7031 #define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
7032 #define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
7033 #define TIM_EGR_CC4G_Pos          (4U)
7034 #define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
7035 #define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
7036 #define TIM_EGR_COMG_Pos          (5U)
7037 #define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
7038 #define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
7039 #define TIM_EGR_TG_Pos            (6U)
7040 #define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
7041 #define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
7042 #define TIM_EGR_BG_Pos            (7U)
7043 #define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
7044 #define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
7045 #define TIM_EGR_B2G_Pos           (8U)
7046 #define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
7047 #define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
7048 
7049 
7050 /******************  Bit definition for TIM_CCMR1 register  *******************/
7051 #define TIM_CCMR1_CC1S_Pos        (0U)
7052 #define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
7053 #define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
7054 #define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
7055 #define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
7056 
7057 #define TIM_CCMR1_OC1FE_Pos       (2U)
7058 #define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
7059 #define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
7060 #define TIM_CCMR1_OC1PE_Pos       (3U)
7061 #define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
7062 #define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
7063 
7064 #define TIM_CCMR1_OC1M_Pos        (4U)
7065 #define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
7066 #define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
7067 #define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
7068 #define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
7069 #define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
7070 #define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
7071 
7072 #define TIM_CCMR1_OC1CE_Pos       (7U)
7073 #define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
7074 #define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
7075 
7076 #define TIM_CCMR1_CC2S_Pos        (8U)
7077 #define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
7078 #define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
7079 #define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
7080 #define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
7081 
7082 #define TIM_CCMR1_OC2FE_Pos       (10U)
7083 #define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
7084 #define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
7085 #define TIM_CCMR1_OC2PE_Pos       (11U)
7086 #define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
7087 #define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
7088 
7089 #define TIM_CCMR1_OC2M_Pos        (12U)
7090 #define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
7091 #define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
7092 #define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
7093 #define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
7094 #define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
7095 #define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
7096 
7097 #define TIM_CCMR1_OC2CE_Pos       (15U)
7098 #define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
7099 #define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
7100 
7101 /*----------------------------------------------------------------------------*/
7102 #define TIM_CCMR1_IC1PSC_Pos      (2U)
7103 #define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
7104 #define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
7105 #define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
7106 #define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
7107 
7108 #define TIM_CCMR1_IC1F_Pos        (4U)
7109 #define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
7110 #define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
7111 #define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
7112 #define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
7113 #define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
7114 #define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
7115 
7116 #define TIM_CCMR1_IC2PSC_Pos      (10U)
7117 #define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
7118 #define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
7119 #define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
7120 #define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
7121 
7122 #define TIM_CCMR1_IC2F_Pos        (12U)
7123 #define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
7124 #define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
7125 #define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
7126 #define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
7127 #define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
7128 #define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
7129 
7130 /******************  Bit definition for TIM_CCMR2 register  *******************/
7131 #define TIM_CCMR2_CC3S_Pos        (0U)
7132 #define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
7133 #define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
7134 #define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
7135 #define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
7136 
7137 #define TIM_CCMR2_OC3FE_Pos       (2U)
7138 #define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
7139 #define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
7140 #define TIM_CCMR2_OC3PE_Pos       (3U)
7141 #define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
7142 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
7143 
7144 #define TIM_CCMR2_OC3M_Pos        (4U)
7145 #define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
7146 #define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
7147 #define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
7148 #define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
7149 #define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
7150 #define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
7151 
7152 #define TIM_CCMR2_OC3CE_Pos       (7U)
7153 #define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
7154 #define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
7155 
7156 #define TIM_CCMR2_CC4S_Pos        (8U)
7157 #define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
7158 #define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
7159 #define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
7160 #define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
7161 
7162 #define TIM_CCMR2_OC4FE_Pos       (10U)
7163 #define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
7164 #define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
7165 #define TIM_CCMR2_OC4PE_Pos       (11U)
7166 #define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
7167 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
7168 
7169 #define TIM_CCMR2_OC4M_Pos        (12U)
7170 #define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
7171 #define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
7172 #define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
7173 #define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
7174 #define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
7175 #define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
7176 
7177 #define TIM_CCMR2_OC4CE_Pos       (15U)
7178 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
7179 #define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
7180 
7181 /*----------------------------------------------------------------------------*/
7182 #define TIM_CCMR2_IC3PSC_Pos      (2U)
7183 #define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
7184 #define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
7185 #define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
7186 #define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
7187 
7188 #define TIM_CCMR2_IC3F_Pos        (4U)
7189 #define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
7190 #define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
7191 #define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
7192 #define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
7193 #define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
7194 #define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
7195 
7196 #define TIM_CCMR2_IC4PSC_Pos      (10U)
7197 #define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
7198 #define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
7199 #define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
7200 #define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
7201 
7202 #define TIM_CCMR2_IC4F_Pos        (12U)
7203 #define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
7204 #define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
7205 #define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
7206 #define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
7207 #define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
7208 #define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
7209 
7210 /******************  Bit definition for TIM_CCMR3 register  *******************/
7211 #define TIM_CCMR3_OC5FE_Pos       (2U)
7212 #define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
7213 #define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
7214 #define TIM_CCMR3_OC5PE_Pos       (3U)
7215 #define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
7216 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
7217 
7218 #define TIM_CCMR3_OC5M_Pos        (4U)
7219 #define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
7220 #define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
7221 #define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
7222 #define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
7223 #define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
7224 #define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
7225 
7226 #define TIM_CCMR3_OC5CE_Pos       (7U)
7227 #define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
7228 #define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
7229 
7230 #define TIM_CCMR3_OC6FE_Pos       (10U)
7231 #define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
7232 #define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
7233 #define TIM_CCMR3_OC6PE_Pos       (11U)
7234 #define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
7235 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
7236 
7237 #define TIM_CCMR3_OC6M_Pos        (12U)
7238 #define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
7239 #define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
7240 #define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
7241 #define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
7242 #define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
7243 #define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
7244 
7245 #define TIM_CCMR3_OC6CE_Pos       (15U)
7246 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
7247 #define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
7248 
7249 /*******************  Bit definition for TIM_CCER register  *******************/
7250 #define TIM_CCER_CC1E_Pos         (0U)
7251 #define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
7252 #define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
7253 #define TIM_CCER_CC1P_Pos         (1U)
7254 #define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
7255 #define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
7256 #define TIM_CCER_CC1NE_Pos        (2U)
7257 #define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
7258 #define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
7259 #define TIM_CCER_CC1NP_Pos        (3U)
7260 #define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
7261 #define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
7262 #define TIM_CCER_CC2E_Pos         (4U)
7263 #define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
7264 #define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
7265 #define TIM_CCER_CC2P_Pos         (5U)
7266 #define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
7267 #define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
7268 #define TIM_CCER_CC2NE_Pos        (6U)
7269 #define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
7270 #define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
7271 #define TIM_CCER_CC2NP_Pos        (7U)
7272 #define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
7273 #define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
7274 #define TIM_CCER_CC3E_Pos         (8U)
7275 #define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
7276 #define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
7277 #define TIM_CCER_CC3P_Pos         (9U)
7278 #define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
7279 #define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
7280 #define TIM_CCER_CC3NE_Pos        (10U)
7281 #define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
7282 #define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
7283 #define TIM_CCER_CC3NP_Pos        (11U)
7284 #define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
7285 #define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
7286 #define TIM_CCER_CC4E_Pos         (12U)
7287 #define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
7288 #define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
7289 #define TIM_CCER_CC4P_Pos         (13U)
7290 #define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
7291 #define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
7292 #define TIM_CCER_CC4NP_Pos        (15U)
7293 #define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
7294 #define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
7295 #define TIM_CCER_CC5E_Pos         (16U)
7296 #define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
7297 #define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
7298 #define TIM_CCER_CC5P_Pos         (17U)
7299 #define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
7300 #define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
7301 #define TIM_CCER_CC6E_Pos         (20U)
7302 #define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
7303 #define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
7304 #define TIM_CCER_CC6P_Pos         (21U)
7305 #define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
7306 #define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
7307 
7308 /*******************  Bit definition for TIM_CNT register  ********************/
7309 #define TIM_CNT_CNT_Pos           (0U)
7310 #define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
7311 #define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
7312 #define TIM_CNT_UIFCPY_Pos        (31U)
7313 #define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
7314 #define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
7315 
7316 /*******************  Bit definition for TIM_PSC register  ********************/
7317 #define TIM_PSC_PSC_Pos           (0U)
7318 #define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
7319 #define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
7320 
7321 /*******************  Bit definition for TIM_ARR register  ********************/
7322 #define TIM_ARR_ARR_Pos           (0U)
7323 #define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
7324 #define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
7325 
7326 /*******************  Bit definition for TIM_RCR register  ********************/
7327 #define TIM_RCR_REP_Pos           (0U)
7328 #define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
7329 #define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
7330 
7331 /*******************  Bit definition for TIM_CCR1 register  *******************/
7332 #define TIM_CCR1_CCR1_Pos         (0U)
7333 #define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
7334 #define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
7335 
7336 /*******************  Bit definition for TIM_CCR2 register  *******************/
7337 #define TIM_CCR2_CCR2_Pos         (0U)
7338 #define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
7339 #define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
7340 
7341 /*******************  Bit definition for TIM_CCR3 register  *******************/
7342 #define TIM_CCR3_CCR3_Pos         (0U)
7343 #define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
7344 #define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
7345 
7346 /*******************  Bit definition for TIM_CCR4 register  *******************/
7347 #define TIM_CCR4_CCR4_Pos         (0U)
7348 #define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
7349 #define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
7350 
7351 /*******************  Bit definition for TIM_CCR5 register  *******************/
7352 #define TIM_CCR5_CCR5_Pos         (0U)
7353 #define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
7354 #define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
7355 #define TIM_CCR5_GC5C1_Pos        (29U)
7356 #define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
7357 #define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
7358 #define TIM_CCR5_GC5C2_Pos        (30U)
7359 #define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
7360 #define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
7361 #define TIM_CCR5_GC5C3_Pos        (31U)
7362 #define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
7363 #define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
7364 
7365 /*******************  Bit definition for TIM_CCR6 register  *******************/
7366 #define TIM_CCR6_CCR6_Pos         (0U)
7367 #define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
7368 #define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
7369 
7370 /*******************  Bit definition for TIM_BDTR register  *******************/
7371 #define TIM_BDTR_DTG_Pos          (0U)
7372 #define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
7373 #define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7374 #define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
7375 #define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
7376 #define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
7377 #define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
7378 #define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
7379 #define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
7380 #define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
7381 #define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
7382 
7383 #define TIM_BDTR_LOCK_Pos         (8U)
7384 #define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
7385 #define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
7386 #define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
7387 #define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
7388 
7389 #define TIM_BDTR_OSSI_Pos         (10U)
7390 #define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
7391 #define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
7392 #define TIM_BDTR_OSSR_Pos         (11U)
7393 #define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
7394 #define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
7395 #define TIM_BDTR_BKE_Pos          (12U)
7396 #define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
7397 #define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
7398 #define TIM_BDTR_BKP_Pos          (13U)
7399 #define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
7400 #define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
7401 #define TIM_BDTR_AOE_Pos          (14U)
7402 #define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
7403 #define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
7404 #define TIM_BDTR_MOE_Pos          (15U)
7405 #define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
7406 #define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
7407 
7408 #define TIM_BDTR_BKF_Pos          (16U)
7409 #define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
7410 #define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
7411 #define TIM_BDTR_BK2F_Pos         (20U)
7412 #define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
7413 #define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
7414 
7415 #define TIM_BDTR_BK2E_Pos         (24U)
7416 #define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
7417 #define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
7418 #define TIM_BDTR_BK2P_Pos         (25U)
7419 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
7420 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
7421 
7422 #define TIM_BDTR_BKDSRM_Pos       (26U)
7423 #define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
7424 #define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
7425 #define TIM_BDTR_BK2DSRM_Pos      (27U)
7426 #define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
7427 #define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
7428 
7429 #define TIM_BDTR_BKBID_Pos        (28U)
7430 #define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
7431 #define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
7432 #define TIM_BDTR_BK2BID_Pos       (29U)
7433 #define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
7434 #define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
7435 
7436 /*******************  Bit definition for TIM_DCR register  ********************/
7437 #define TIM_DCR_DBA_Pos           (0U)
7438 #define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
7439 #define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
7440 #define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
7441 #define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
7442 #define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
7443 #define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
7444 #define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
7445 
7446 #define TIM_DCR_DBL_Pos           (8U)
7447 #define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
7448 #define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
7449 #define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
7450 #define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
7451 #define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
7452 #define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
7453 #define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
7454 
7455 /*******************  Bit definition for TIM_DMAR register  *******************/
7456 #define TIM_DMAR_DMAB_Pos         (0U)
7457 #define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
7458 #define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
7459 
7460 /*******************  Bit definition for TIM1_OR1 register  *******************/
7461 #define TIM1_OR1_OCREF_CLR_Pos     (0U)
7462 #define TIM1_OR1_OCREF_CLR_Msk     (0x1UL << TIM1_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
7463 #define TIM1_OR1_OCREF_CLR         TIM1_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
7464 
7465 /*******************  Bit definition for TIM1_AF1 register  *******************/
7466 #define TIM1_AF1_BKINE_Pos        (0U)
7467 #define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
7468 #define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7469 #define TIM1_AF1_BKCMP1E_Pos      (1U)
7470 #define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7471 #define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7472 #define TIM1_AF1_BKCMP2E_Pos      (2U)
7473 #define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7474 #define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7475 #define TIM1_AF1_BKINP_Pos        (9U)
7476 #define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
7477 #define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7478 #define TIM1_AF1_BKCMP1P_Pos      (10U)
7479 #define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7480 #define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7481 #define TIM1_AF1_BKCMP2P_Pos      (11U)
7482 #define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7483 #define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7484 
7485 #define TIM1_AF1_ETRSEL_Pos       (14U)
7486 #define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7487 #define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
7488 #define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7489 #define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7490 #define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7491 #define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7492 
7493 /*******************  Bit definition for TIM1_AF2 register  *******************/
7494 #define TIM1_AF2_BK2INE_Pos       (0U)
7495 #define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
7496 #define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
7497 #define TIM1_AF2_BK2CMP1E_Pos     (1U)
7498 #define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
7499 #define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
7500 #define TIM1_AF2_BK2CMP2E_Pos     (2U)
7501 #define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
7502 #define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
7503 #define TIM1_AF2_BK2INP_Pos       (9U)
7504 #define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
7505 #define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
7506 #define TIM1_AF2_BK2CMP1P_Pos     (10U)
7507 #define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
7508 #define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
7509 #define TIM1_AF2_BK2CMP2P_Pos     (11U)
7510 #define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
7511 #define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
7512 
7513 /*******************  Bit definition for TIM2_OR1 register  *******************/
7514 #define TIM2_OR1_OCREF_CLR_Pos     (0U)
7515 #define TIM2_OR1_OCREF_CLR_Msk     (0x1UL << TIM2_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
7516 #define TIM2_OR1_OCREF_CLR         TIM2_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
7517 
7518 /*******************  Bit definition for TIM2_AF1 register  *******************/
7519 #define TIM2_AF1_ETRSEL_Pos       (14U)
7520 #define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7521 #define TIM2_AF1_ETRSEL           TIM2_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM2 ETR source selection) */
7522 #define TIM2_AF1_ETRSEL_0         (0x1UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7523 #define TIM2_AF1_ETRSEL_1         (0x2UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7524 #define TIM2_AF1_ETRSEL_2         (0x4UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7525 #define TIM2_AF1_ETRSEL_3         (0x8UL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7526 
7527 /*******************  Bit definition for TIM3_OR1 register  *******************/
7528 #define TIM3_OR1_OCREF_CLR_Pos     (0U)
7529 #define TIM3_OR1_OCREF_CLR_Msk     (0x1UL << TIM3_OR1_OCREF_CLR_Pos)           /*!< 0x00000001 */
7530 #define TIM3_OR1_OCREF_CLR         TIM3_OR1_OCREF_CLR_Msk                      /*!<OCREF clear input selection */
7531 
7532 /*******************  Bit definition for TIM3_AF1 register  *******************/
7533 #define TIM3_AF1_ETRSEL_Pos       (14U)
7534 #define TIM3_AF1_ETRSEL_Msk       (0xFUL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
7535 #define TIM3_AF1_ETRSEL           TIM3_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
7536 #define TIM3_AF1_ETRSEL_0         (0x1UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
7537 #define TIM3_AF1_ETRSEL_1         (0x2UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
7538 #define TIM3_AF1_ETRSEL_2         (0x4UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
7539 #define TIM3_AF1_ETRSEL_3         (0x8UL << TIM3_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
7540 
7541 /*******************  Bit definition for TIM14_AF1 register  *******************/
7542 #define TIM14_AF1_ETRSEL_Pos      (14U)
7543 #define TIM14_AF1_ETRSEL_Msk      (0xFUL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x0003C000 */
7544 #define TIM14_AF1_ETRSEL          TIM14_AF1_ETRSEL_Msk                         /*!<ETRSEL[3:0] bits (TIM14 ETR source selection) */
7545 #define TIM14_AF1_ETRSEL_0        (0x1UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00004000 */
7546 #define TIM14_AF1_ETRSEL_1        (0x2UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00008000 */
7547 #define TIM14_AF1_ETRSEL_2        (0x4UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00010000 */
7548 #define TIM14_AF1_ETRSEL_3        (0x8UL << TIM14_AF1_ETRSEL_Pos)              /*!< 0x00020000 */
7549 
7550 /*******************  Bit definition for TIM15_AF1 register  ******************/
7551 #define TIM15_AF1_BKINE_Pos      (0U)
7552 #define TIM15_AF1_BKINE_Msk      (0x1UL << TIM15_AF1_BKINE_Pos)                /*!< 0x00000001 */
7553 #define TIM15_AF1_BKINE          TIM15_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7554 #define TIM15_AF1_BKCMP1E_Pos    (1U)
7555 #define TIM15_AF1_BKCMP1E_Msk    (0x1UL << TIM15_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7556 #define TIM15_AF1_BKCMP1E        TIM15_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7557 #define TIM15_AF1_BKCMP2E_Pos    (2U)
7558 #define TIM15_AF1_BKCMP2E_Msk    (0x1UL << TIM15_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7559 #define TIM15_AF1_BKCMP2E        TIM15_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7560 #define TIM15_AF1_BKINP_Pos      (9U)
7561 #define TIM15_AF1_BKINP_Msk      (0x1UL << TIM15_AF1_BKINP_Pos)                /*!< 0x00000200 */
7562 #define TIM15_AF1_BKINP          TIM15_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7563 #define TIM15_AF1_BKCMP1P_Pos    (10U)
7564 #define TIM15_AF1_BKCMP1P_Msk    (0x1UL << TIM15_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7565 #define TIM15_AF1_BKCMP1P        TIM15_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7566 #define TIM15_AF1_BKCMP2P_Pos    (11U)
7567 #define TIM15_AF1_BKCMP2P_Msk    (0x1UL << TIM15_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7568 #define TIM15_AF1_BKCMP2P        TIM15_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7569 
7570 /*******************  Bit definition for TIM16_AF1 register  ******************/
7571 #define TIM16_AF1_BKINE_Pos      (0U)
7572 #define TIM16_AF1_BKINE_Msk      (0x1UL << TIM16_AF1_BKINE_Pos)                /*!< 0x00000001 */
7573 #define TIM16_AF1_BKINE          TIM16_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7574 #define TIM16_AF1_BKCMP1E_Pos    (1U)
7575 #define TIM16_AF1_BKCMP1E_Msk    (0x1UL << TIM16_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7576 #define TIM16_AF1_BKCMP1E        TIM16_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7577 #define TIM16_AF1_BKCMP2E_Pos    (2U)
7578 #define TIM16_AF1_BKCMP2E_Msk    (0x1UL << TIM16_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7579 #define TIM16_AF1_BKCMP2E        TIM16_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7580 #define TIM16_AF1_BKINP_Pos      (9U)
7581 #define TIM16_AF1_BKINP_Msk      (0x1UL << TIM16_AF1_BKINP_Pos)                /*!< 0x00000200 */
7582 #define TIM16_AF1_BKINP          TIM16_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7583 #define TIM16_AF1_BKCMP1P_Pos    (10U)
7584 #define TIM16_AF1_BKCMP1P_Msk    (0x1UL << TIM16_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7585 #define TIM16_AF1_BKCMP1P        TIM16_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7586 #define TIM16_AF1_BKCMP2P_Pos    (11U)
7587 #define TIM16_AF1_BKCMP2P_Msk    (0x1UL << TIM16_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7588 #define TIM16_AF1_BKCMP2P        TIM16_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7589 
7590 /*******************  Bit definition for TIM17_AF1 register  ******************/
7591 #define TIM17_AF1_BKINE_Pos      (0U)
7592 #define TIM17_AF1_BKINE_Msk      (0x1UL << TIM17_AF1_BKINE_Pos)                /*!< 0x00000001 */
7593 #define TIM17_AF1_BKINE          TIM17_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
7594 #define TIM17_AF1_BKCMP1E_Pos    (1U)
7595 #define TIM17_AF1_BKCMP1E_Msk    (0x1UL << TIM17_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
7596 #define TIM17_AF1_BKCMP1E        TIM17_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
7597 #define TIM17_AF1_BKCMP2E_Pos    (2U)
7598 #define TIM17_AF1_BKCMP2E_Msk    (0x1UL << TIM17_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
7599 #define TIM17_AF1_BKCMP2E        TIM17_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
7600 #define TIM17_AF1_BKINP_Pos      (9U)
7601 #define TIM17_AF1_BKINP_Msk      (0x1UL << TIM17_AF1_BKINP_Pos)                /*!< 0x00000200 */
7602 #define TIM17_AF1_BKINP          TIM17_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
7603 #define TIM17_AF1_BKCMP1P_Pos    (10U)
7604 #define TIM17_AF1_BKCMP1P_Msk    (0x1UL << TIM17_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
7605 #define TIM17_AF1_BKCMP1P        TIM17_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
7606 #define TIM17_AF1_BKCMP2P_Pos    (11U)
7607 #define TIM17_AF1_BKCMP2P_Msk    (0x1UL << TIM17_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
7608 #define TIM17_AF1_BKCMP2P        TIM17_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
7609 
7610 /*******************  Bit definition for TIM_TISEL register  *********************/
7611 #define TIM_TISEL_TI1SEL_Pos      (0U)
7612 #define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
7613 #define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
7614 #define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
7615 #define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
7616 #define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
7617 #define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
7618 
7619 #define TIM_TISEL_TI2SEL_Pos      (8U)
7620 #define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
7621 #define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
7622 #define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
7623 #define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
7624 #define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
7625 #define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */
7626 
7627 #define TIM_TISEL_TI3SEL_Pos      (16U)
7628 #define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
7629 #define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
7630 #define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00010000 */
7631 #define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00020000 */
7632 #define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00040000 */
7633 #define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x00080000 */
7634 
7635 #define TIM_TISEL_TI4SEL_Pos      (24U)
7636 #define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
7637 #define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
7638 #define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x01000000 */
7639 #define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x02000000 */
7640 #define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x04000000 */
7641 #define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x08000000 */
7642 
7643 /******************************************************************************/
7644 /*                                                                            */
7645 /*                         Low Power Timer (LPTIM)                            */
7646 /*                                                                            */
7647 /******************************************************************************/
7648 /******************  Bit definition for LPTIM_ISR register  *******************/
7649 #define LPTIM_ISR_CMPM_Pos          (0U)
7650 #define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
7651 #define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
7652 #define LPTIM_ISR_ARRM_Pos          (1U)
7653 #define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
7654 #define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
7655 #define LPTIM_ISR_EXTTRIG_Pos       (2U)
7656 #define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
7657 #define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
7658 #define LPTIM_ISR_CMPOK_Pos         (3U)
7659 #define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
7660 #define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
7661 #define LPTIM_ISR_ARROK_Pos         (4U)
7662 #define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
7663 #define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
7664 #define LPTIM_ISR_UP_Pos            (5U)
7665 #define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
7666 #define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
7667 #define LPTIM_ISR_DOWN_Pos          (6U)
7668 #define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
7669 #define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
7670 
7671 /******************  Bit definition for LPTIM_ICR register  *******************/
7672 #define LPTIM_ICR_CMPMCF_Pos        (0U)
7673 #define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
7674 #define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
7675 #define LPTIM_ICR_ARRMCF_Pos        (1U)
7676 #define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
7677 #define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
7678 #define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
7679 #define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
7680 #define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
7681 #define LPTIM_ICR_CMPOKCF_Pos       (3U)
7682 #define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
7683 #define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
7684 #define LPTIM_ICR_ARROKCF_Pos       (4U)
7685 #define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
7686 #define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
7687 #define LPTIM_ICR_UPCF_Pos          (5U)
7688 #define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
7689 #define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
7690 #define LPTIM_ICR_DOWNCF_Pos        (6U)
7691 #define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
7692 #define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
7693 
7694 /******************  Bit definition for LPTIM_IER register ********************/
7695 #define LPTIM_IER_CMPMIE_Pos        (0U)
7696 #define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
7697 #define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
7698 #define LPTIM_IER_ARRMIE_Pos        (1U)
7699 #define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
7700 #define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
7701 #define LPTIM_IER_EXTTRIGIE_Pos     (2U)
7702 #define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
7703 #define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
7704 #define LPTIM_IER_CMPOKIE_Pos       (3U)
7705 #define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
7706 #define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
7707 #define LPTIM_IER_ARROKIE_Pos       (4U)
7708 #define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
7709 #define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
7710 #define LPTIM_IER_UPIE_Pos          (5U)
7711 #define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
7712 #define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
7713 #define LPTIM_IER_DOWNIE_Pos        (6U)
7714 #define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
7715 #define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
7716 
7717 /******************  Bit definition for LPTIM_CFGR register *******************/
7718 #define LPTIM_CFGR_CKSEL_Pos        (0U)
7719 #define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
7720 #define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
7721 
7722 #define LPTIM_CFGR_CKPOL_Pos        (1U)
7723 #define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
7724 #define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
7725 #define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
7726 #define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
7727 
7728 #define LPTIM_CFGR_CKFLT_Pos        (3U)
7729 #define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
7730 #define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
7731 #define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
7732 #define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
7733 
7734 #define LPTIM_CFGR_TRGFLT_Pos       (6U)
7735 #define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
7736 #define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
7737 #define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
7738 #define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
7739 
7740 #define LPTIM_CFGR_PRESC_Pos        (9U)
7741 #define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
7742 #define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
7743 #define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
7744 #define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
7745 #define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
7746 
7747 #define LPTIM_CFGR_TRIGSEL_Pos      (13U)
7748 #define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
7749 #define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
7750 #define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
7751 #define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
7752 #define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
7753 
7754 #define LPTIM_CFGR_TRIGEN_Pos       (17U)
7755 #define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
7756 #define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
7757 #define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
7758 #define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
7759 
7760 #define LPTIM_CFGR_TIMOUT_Pos       (19U)
7761 #define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
7762 #define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timeout enable */
7763 #define LPTIM_CFGR_WAVE_Pos         (20U)
7764 #define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
7765 #define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
7766 #define LPTIM_CFGR_WAVPOL_Pos       (21U)
7767 #define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
7768 #define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
7769 #define LPTIM_CFGR_PRELOAD_Pos      (22U)
7770 #define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
7771 #define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
7772 #define LPTIM_CFGR_COUNTMODE_Pos    (23U)
7773 #define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
7774 #define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
7775 #define LPTIM_CFGR_ENC_Pos          (24U)
7776 #define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
7777 #define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
7778 
7779 /******************  Bit definition for LPTIM_CR register  ********************/
7780 #define LPTIM_CR_ENABLE_Pos         (0U)
7781 #define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
7782 #define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
7783 #define LPTIM_CR_SNGSTRT_Pos        (1U)
7784 #define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
7785 #define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
7786 #define LPTIM_CR_CNTSTRT_Pos        (2U)
7787 #define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
7788 #define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
7789 #define LPTIM_CR_COUNTRST_Pos       (3U)
7790 #define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
7791 #define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
7792 #define LPTIM_CR_RSTARE_Pos         (4U)
7793 #define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
7794 #define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
7795 
7796 /******************  Bit definition for LPTIM_CMP register  *******************/
7797 #define LPTIM_CMP_CMP_Pos           (0U)
7798 #define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
7799 #define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
7800 
7801 /******************  Bit definition for LPTIM_ARR register  *******************/
7802 #define LPTIM_ARR_ARR_Pos           (0U)
7803 #define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
7804 #define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
7805 
7806 /******************  Bit definition for LPTIM_CNT register  *******************/
7807 #define LPTIM_CNT_CNT_Pos           (0U)
7808 #define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
7809 #define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
7810 
7811 /******************  Bit definition for LPTIM_CFGR2 register  *******************/
7812 #define LPTIM_CFGR2_IN1SEL_Pos      (0U)
7813 #define LPTIM_CFGR2_IN1SEL_Msk      (0xFUL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x0000000F */
7814 #define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< CFGR2[3:0] bits (INPUT1 selection) */
7815 #define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000001 */
7816 #define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000002 */
7817 #define LPTIM_CFGR2_IN1SEL_2        (0x4UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000004 */
7818 #define LPTIM_CFGR2_IN1SEL_3        (0x8UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000008 */
7819 
7820 #define LPTIM_CFGR2_IN2SEL_Pos      (4U)
7821 #define LPTIM_CFGR2_IN2SEL_Msk      (0xFUL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x000000F0 */
7822 #define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< CFGR2[7:4] bits (INPUT2 selection) */
7823 #define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000010 */
7824 #define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000020 */
7825 #define LPTIM_CFGR2_IN2SEL_2        (0x4UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000040 */
7826 #define LPTIM_CFGR2_IN2SEL_3        (0x8UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000080 */
7827 
7828 /******************************************************************************/
7829 /*                                                                            */
7830 /*                      Analog Comparators (COMP)                             */
7831 /*                                                                            */
7832 /******************************************************************************/
7833 /**********************  Bit definition for COMP_CSR register  ****************/
7834 #define COMP_CSR_EN_Pos            (0U)
7835 #define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
7836 #define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
7837 
7838 #define COMP_CSR_INMSEL_Pos        (4U)
7839 #define COMP_CSR_INMSEL_Msk        (0xFUL << COMP_CSR_INMSEL_Pos)              /*!< 0x000000F0 */
7840 #define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
7841 #define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
7842 #define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
7843 #define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
7844 #define COMP_CSR_INMSEL_3          (0x8UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000080 */
7845 
7846 #define COMP_CSR_INPSEL_Pos        (8U)
7847 #define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000300 */
7848 #define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator plus minus selection */
7849 #define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
7850 #define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000200 */
7851 
7852 #define COMP_CSR_WINMODE_Pos       (11U)
7853 #define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000800 */
7854 #define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
7855 #define COMP_CSR_WINOUT_Pos        (14U)
7856 #define COMP_CSR_WINOUT_Msk        (0x1UL << COMP_CSR_WINOUT_Pos)              /*!< 0x00004000 */
7857 #define COMP_CSR_WINOUT            COMP_CSR_WINOUT_Msk                         /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
7858 
7859 #define COMP_CSR_POLARITY_Pos      (15U)
7860 #define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
7861 #define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
7862 
7863 #define COMP_CSR_HYST_Pos          (16U)
7864 #define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
7865 #define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator input hysteresis */
7866 #define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
7867 #define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
7868 
7869 #define COMP_CSR_PWRMODE_Pos       (18U)
7870 #define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x000C0000 */
7871 #define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
7872 #define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00040000 */
7873 #define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00080000 */
7874 
7875 #define COMP_CSR_BLANKING_Pos      (20U)
7876 #define COMP_CSR_BLANKING_Msk      (0x1FUL << COMP_CSR_BLANKING_Pos)           /*!< 0x01F00000 */
7877 #define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
7878 #define COMP_CSR_BLANKING_0        (0x01UL << COMP_CSR_BLANKING_Pos)           /*!< 0x00100000 */
7879 #define COMP_CSR_BLANKING_1        (0x02UL << COMP_CSR_BLANKING_Pos)           /*!< 0x00200000 */
7880 #define COMP_CSR_BLANKING_2        (0x04UL << COMP_CSR_BLANKING_Pos)           /*!< 0x00400000 */
7881 #define COMP_CSR_BLANKING_3        (0x08UL << COMP_CSR_BLANKING_Pos)           /*!< 0x00800000 */
7882 #define COMP_CSR_BLANKING_4        (0x10UL << COMP_CSR_BLANKING_Pos)           /*!< 0x01000000 */
7883 
7884 #define COMP_CSR_VALUE_Pos         (30U)
7885 #define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
7886 #define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
7887 
7888 #define COMP_CSR_LOCK_Pos          (31U)
7889 #define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
7890 #define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
7891 
7892 /******************************************************************************/
7893 /*                                                                            */
7894 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
7895 /*                                                                            */
7896 /******************************************************************************/
7897 /******************  Bit definition for USART_CR1 register  *******************/
7898 #define USART_CR1_UE_Pos             (0U)
7899 #define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
7900 #define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
7901 #define USART_CR1_UESM_Pos           (1U)
7902 #define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
7903 #define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
7904 #define USART_CR1_RE_Pos             (2U)
7905 #define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
7906 #define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
7907 #define USART_CR1_TE_Pos             (3U)
7908 #define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
7909 #define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
7910 #define USART_CR1_IDLEIE_Pos         (4U)
7911 #define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
7912 #define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
7913 #define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
7914 #define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
7915 #define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
7916 #define USART_CR1_TCIE_Pos           (6U)
7917 #define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
7918 #define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
7919 #define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
7920 #define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
7921 #define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
7922 #define USART_CR1_PEIE_Pos           (8U)
7923 #define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
7924 #define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
7925 #define USART_CR1_PS_Pos             (9U)
7926 #define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
7927 #define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
7928 #define USART_CR1_PCE_Pos            (10U)
7929 #define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
7930 #define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
7931 #define USART_CR1_WAKE_Pos           (11U)
7932 #define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
7933 #define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
7934 #define USART_CR1_M_Pos              (12U)
7935 #define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
7936 #define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
7937 #define USART_CR1_M0_Pos             (12U)
7938 #define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
7939 #define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
7940 #define USART_CR1_MME_Pos            (13U)
7941 #define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
7942 #define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
7943 #define USART_CR1_CMIE_Pos           (14U)
7944 #define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
7945 #define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
7946 #define USART_CR1_OVER8_Pos          (15U)
7947 #define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
7948 #define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
7949 #define USART_CR1_DEDT_Pos           (16U)
7950 #define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
7951 #define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
7952 #define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
7953 #define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
7954 #define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
7955 #define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
7956 #define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
7957 #define USART_CR1_DEAT_Pos           (21U)
7958 #define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
7959 #define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
7960 #define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
7961 #define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
7962 #define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
7963 #define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
7964 #define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
7965 #define USART_CR1_RTOIE_Pos          (26U)
7966 #define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
7967 #define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
7968 #define USART_CR1_EOBIE_Pos          (27U)
7969 #define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
7970 #define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
7971 #define USART_CR1_M1_Pos             (28U)
7972 #define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
7973 #define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
7974 #define USART_CR1_FIFOEN_Pos         (29U)
7975 #define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
7976 #define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
7977 #define USART_CR1_TXFEIE_Pos         (30U)
7978 #define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
7979 #define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
7980 #define USART_CR1_RXFFIE_Pos         (31U)
7981 #define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
7982 #define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
7983 
7984 /******************  Bit definition for USART_CR2 register  *******************/
7985 #define USART_CR2_SLVEN_Pos          (0U)
7986 #define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
7987 #define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
7988 #define USART_CR2_DIS_NSS_Pos        (3U)
7989 #define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
7990 #define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
7991 #define USART_CR2_ADDM7_Pos          (4U)
7992 #define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
7993 #define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
7994 #define USART_CR2_LBDL_Pos           (5U)
7995 #define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
7996 #define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
7997 #define USART_CR2_LBDIE_Pos          (6U)
7998 #define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
7999 #define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
8000 #define USART_CR2_LBCL_Pos           (8U)
8001 #define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
8002 #define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
8003 #define USART_CR2_CPHA_Pos           (9U)
8004 #define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
8005 #define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
8006 #define USART_CR2_CPOL_Pos           (10U)
8007 #define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
8008 #define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
8009 #define USART_CR2_CLKEN_Pos          (11U)
8010 #define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
8011 #define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
8012 #define USART_CR2_STOP_Pos           (12U)
8013 #define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
8014 #define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
8015 #define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
8016 #define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
8017 #define USART_CR2_LINEN_Pos          (14U)
8018 #define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
8019 #define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
8020 #define USART_CR2_SWAP_Pos           (15U)
8021 #define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
8022 #define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
8023 #define USART_CR2_RXINV_Pos          (16U)
8024 #define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
8025 #define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
8026 #define USART_CR2_TXINV_Pos          (17U)
8027 #define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
8028 #define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
8029 #define USART_CR2_DATAINV_Pos        (18U)
8030 #define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
8031 #define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
8032 #define USART_CR2_MSBFIRST_Pos       (19U)
8033 #define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
8034 #define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
8035 #define USART_CR2_ABREN_Pos          (20U)
8036 #define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
8037 #define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
8038 #define USART_CR2_ABRMODE_Pos        (21U)
8039 #define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
8040 #define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
8041 #define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
8042 #define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
8043 #define USART_CR2_RTOEN_Pos          (23U)
8044 #define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
8045 #define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
8046 #define USART_CR2_ADD_Pos            (24U)
8047 #define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
8048 #define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
8049 
8050 /******************  Bit definition for USART_CR3 register  *******************/
8051 #define USART_CR3_EIE_Pos            (0U)
8052 #define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
8053 #define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
8054 #define USART_CR3_IREN_Pos           (1U)
8055 #define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
8056 #define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
8057 #define USART_CR3_IRLP_Pos           (2U)
8058 #define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
8059 #define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
8060 #define USART_CR3_HDSEL_Pos          (3U)
8061 #define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
8062 #define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
8063 #define USART_CR3_NACK_Pos           (4U)
8064 #define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
8065 #define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
8066 #define USART_CR3_SCEN_Pos           (5U)
8067 #define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
8068 #define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
8069 #define USART_CR3_DMAR_Pos           (6U)
8070 #define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
8071 #define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
8072 #define USART_CR3_DMAT_Pos           (7U)
8073 #define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
8074 #define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
8075 #define USART_CR3_RTSE_Pos           (8U)
8076 #define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
8077 #define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
8078 #define USART_CR3_CTSE_Pos           (9U)
8079 #define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
8080 #define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
8081 #define USART_CR3_CTSIE_Pos          (10U)
8082 #define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
8083 #define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
8084 #define USART_CR3_ONEBIT_Pos         (11U)
8085 #define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
8086 #define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
8087 #define USART_CR3_OVRDIS_Pos         (12U)
8088 #define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
8089 #define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
8090 #define USART_CR3_DDRE_Pos           (13U)
8091 #define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
8092 #define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
8093 #define USART_CR3_DEM_Pos            (14U)
8094 #define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
8095 #define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
8096 #define USART_CR3_DEP_Pos            (15U)
8097 #define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
8098 #define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
8099 #define USART_CR3_SCARCNT_Pos        (17U)
8100 #define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
8101 #define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
8102 #define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
8103 #define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
8104 #define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
8105 #define USART_CR3_WUS_Pos            (20U)
8106 #define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
8107 #define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
8108 #define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
8109 #define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
8110 #define USART_CR3_WUFIE_Pos          (22U)
8111 #define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
8112 #define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
8113 #define USART_CR3_TXFTIE_Pos         (23U)
8114 #define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
8115 #define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
8116 #define USART_CR3_TCBGTIE_Pos        (24U)
8117 #define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
8118 #define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
8119 #define USART_CR3_RXFTCFG_Pos        (25U)
8120 #define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
8121 #define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
8122 #define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
8123 #define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
8124 #define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
8125 #define USART_CR3_RXFTIE_Pos         (28U)
8126 #define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
8127 #define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
8128 #define USART_CR3_TXFTCFG_Pos        (29U)
8129 #define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
8130 #define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
8131 #define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
8132 #define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
8133 #define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
8134 
8135 /******************  Bit definition for USART_BRR register  *******************/
8136 #define USART_BRR_LPUART_Pos         (0U)
8137 #define USART_BRR_LPUART_Msk         (0xFFFFFUL << USART_BRR_LPUART_Pos)       /*!< 0x000FFFFF */
8138 #define USART_BRR_LPUART             USART_BRR_LPUART_Msk                      /*!< LPUART Baud rate register [19:0] */
8139 #define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
8140 
8141 /******************  Bit definition for USART_GTPR register  ******************/
8142 #define USART_GTPR_PSC_Pos           (0U)
8143 #define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
8144 #define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
8145 #define USART_GTPR_GT_Pos            (8U)
8146 #define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
8147 #define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
8148 
8149 /*******************  Bit definition for USART_RTOR register  *****************/
8150 #define USART_RTOR_RTO_Pos           (0U)
8151 #define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
8152 #define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
8153 #define USART_RTOR_BLEN_Pos          (24U)
8154 #define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
8155 #define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
8156 
8157 /*******************  Bit definition for USART_RQR register  ******************/
8158 #define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
8159 #define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
8160 #define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
8161 #define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
8162 #define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
8163 
8164 /*******************  Bit definition for USART_ISR register  ******************/
8165 #define USART_ISR_PE_Pos             (0U)
8166 #define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
8167 #define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
8168 #define USART_ISR_FE_Pos             (1U)
8169 #define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
8170 #define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
8171 #define USART_ISR_NE_Pos             (2U)
8172 #define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
8173 #define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
8174 #define USART_ISR_ORE_Pos            (3U)
8175 #define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
8176 #define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
8177 #define USART_ISR_IDLE_Pos           (4U)
8178 #define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
8179 #define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
8180 #define USART_ISR_RXNE_RXFNE_Pos     (5U)
8181 #define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)       /*!< 0x00000020 */
8182 #define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                  /*!< Read Data Register Not Empty/RXFIFO Not Empty */
8183 #define USART_ISR_TC_Pos             (6U)
8184 #define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
8185 #define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
8186 #define USART_ISR_TXE_TXFNF_Pos      (7U)
8187 #define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)        /*!< 0x00000080 */
8188 #define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                   /*!< Transmit Data Register Empty/TXFIFO Not Full */
8189 #define USART_ISR_LBDF_Pos           (8U)
8190 #define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
8191 #define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
8192 #define USART_ISR_CTSIF_Pos          (9U)
8193 #define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
8194 #define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
8195 #define USART_ISR_CTS_Pos            (10U)
8196 #define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
8197 #define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
8198 #define USART_ISR_RTOF_Pos           (11U)
8199 #define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
8200 #define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
8201 #define USART_ISR_EOBF_Pos           (12U)
8202 #define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
8203 #define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
8204 #define USART_ISR_UDR_Pos            (13U)
8205 #define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
8206 #define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
8207 #define USART_ISR_ABRE_Pos           (14U)
8208 #define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
8209 #define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
8210 #define USART_ISR_ABRF_Pos           (15U)
8211 #define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
8212 #define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
8213 #define USART_ISR_BUSY_Pos           (16U)
8214 #define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
8215 #define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
8216 #define USART_ISR_CMF_Pos            (17U)
8217 #define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
8218 #define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
8219 #define USART_ISR_SBKF_Pos           (18U)
8220 #define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
8221 #define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
8222 #define USART_ISR_RWU_Pos            (19U)
8223 #define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
8224 #define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
8225 #define USART_ISR_WUF_Pos            (20U)
8226 #define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
8227 #define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
8228 #define USART_ISR_TEACK_Pos          (21U)
8229 #define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
8230 #define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
8231 #define USART_ISR_REACK_Pos          (22U)
8232 #define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
8233 #define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
8234 #define USART_ISR_TXFE_Pos           (23U)
8235 #define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
8236 #define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
8237 #define USART_ISR_RXFF_Pos           (24U)
8238 #define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
8239 #define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
8240 #define USART_ISR_TCBGT_Pos          (25U)
8241 #define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
8242 #define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
8243 #define USART_ISR_RXFT_Pos           (26U)
8244 #define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
8245 #define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
8246 #define USART_ISR_TXFT_Pos           (27U)
8247 #define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
8248 #define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
8249 
8250 /*******************  Bit definition for USART_ICR register  ******************/
8251 #define USART_ICR_PECF_Pos           (0U)
8252 #define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
8253 #define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
8254 #define USART_ICR_FECF_Pos           (1U)
8255 #define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
8256 #define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
8257 #define USART_ICR_NECF_Pos           (2U)
8258 #define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
8259 #define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
8260 #define USART_ICR_ORECF_Pos          (3U)
8261 #define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
8262 #define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
8263 #define USART_ICR_IDLECF_Pos         (4U)
8264 #define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
8265 #define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
8266 #define USART_ICR_TXFECF_Pos         (5U)
8267 #define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
8268 #define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
8269 #define USART_ICR_TCCF_Pos           (6U)
8270 #define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
8271 #define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
8272 #define USART_ICR_TCBGTCF_Pos        (7U)
8273 #define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
8274 #define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
8275 #define USART_ICR_LBDCF_Pos          (8U)
8276 #define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
8277 #define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
8278 #define USART_ICR_CTSCF_Pos          (9U)
8279 #define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
8280 #define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
8281 #define USART_ICR_RTOCF_Pos          (11U)
8282 #define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
8283 #define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
8284 #define USART_ICR_EOBCF_Pos          (12U)
8285 #define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
8286 #define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
8287 #define USART_ICR_UDRCF_Pos          (13U)
8288 #define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
8289 #define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
8290 #define USART_ICR_CMCF_Pos           (17U)
8291 #define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
8292 #define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
8293 #define USART_ICR_WUCF_Pos           (20U)
8294 #define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
8295 #define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
8296 
8297 /*******************  Bit definition for USART_RDR register  ******************/
8298 #define USART_RDR_RDR_Pos             (0U)
8299 #define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
8300 #define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
8301 
8302 /*******************  Bit definition for USART_TDR register  ******************/
8303 #define USART_TDR_TDR_Pos             (0U)
8304 #define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
8305 #define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
8306 
8307 /*******************  Bit definition for USART_PRESC register  ****************/
8308 #define USART_PRESC_PRESCALER_Pos    (0U)
8309 #define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
8310 #define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
8311 #define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
8312 #define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
8313 #define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
8314 #define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
8315 
8316 /******************************************************************************/
8317 /*                                                                            */
8318 /*                                 VREFBUF                                    */
8319 /*                                                                            */
8320 /******************************************************************************/
8321 /*******************  Bit definition for VREFBUF_CSR register  ****************/
8322 #define VREFBUF_CSR_ENVR_Pos    (0U)
8323 #define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
8324 #define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
8325 #define VREFBUF_CSR_HIZ_Pos     (1U)
8326 #define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
8327 #define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
8328 #define VREFBUF_CSR_VRS_Pos     (2U)
8329 #define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
8330 #define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference scale         */
8331 #define VREFBUF_CSR_VRR_Pos     (3U)
8332 #define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
8333 #define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference buffer ready  */
8334 
8335 /*******************  Bit definition for VREFBUF_CCR register  ******************/
8336 #define VREFBUF_CCR_TRIM_Pos    (0U)
8337 #define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
8338 #define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
8339 
8340 /******************************************************************************/
8341 /*                                                                            */
8342 /*                            Window WATCHDOG                                 */
8343 /*                                                                            */
8344 /******************************************************************************/
8345 /*******************  Bit definition for WWDG_CR register  ********************/
8346 #define WWDG_CR_T_Pos           (0U)
8347 #define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
8348 #define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
8349 #define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
8350 #define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
8351 #define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
8352 #define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
8353 #define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
8354 #define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
8355 #define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
8356 
8357 #define WWDG_CR_WDGA_Pos        (7U)
8358 #define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
8359 #define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
8360 
8361 /*******************  Bit definition for WWDG_CFR register  *******************/
8362 #define WWDG_CFR_W_Pos          (0U)
8363 #define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
8364 #define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
8365 #define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
8366 #define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
8367 #define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
8368 #define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
8369 #define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
8370 #define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
8371 #define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
8372 
8373 #define WWDG_CFR_WDGTB_Pos      (11U)
8374 #define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
8375 #define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
8376 #define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
8377 #define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
8378 #define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
8379 
8380 #define WWDG_CFR_EWI_Pos        (9U)
8381 #define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
8382 #define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
8383 
8384 /*******************  Bit definition for WWDG_SR register  ********************/
8385 #define WWDG_SR_EWIF_Pos        (0U)
8386 #define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
8387 #define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
8388 
8389 /******************************************************************************/
8390 /*                                                                            */
8391 /*                                Debug MCU                                   */
8392 /*                                                                            */
8393 /******************************************************************************/
8394 /********************  Bit definition for DBG_IDCODE register  *************/
8395 #define DBG_IDCODE_DEV_ID_Pos                          (0U)
8396 #define DBG_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBG_IDCODE_DEV_ID_Pos)  /*!< 0x00000FFF */
8397 #define DBG_IDCODE_DEV_ID                              DBG_IDCODE_DEV_ID_Msk
8398 #define DBG_IDCODE_REV_ID_Pos                          (16U)
8399 #define DBG_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
8400 #define DBG_IDCODE_REV_ID                              DBG_IDCODE_REV_ID_Msk
8401 
8402 /********************  Bit definition for DBG_CR register  *****************/
8403 #define DBG_CR_DBG_STOP_Pos                            (1U)
8404 #define DBG_CR_DBG_STOP_Msk                            (0x1UL << DBG_CR_DBG_STOP_Pos)      /*!< 0x00000002 */
8405 #define DBG_CR_DBG_STOP                                DBG_CR_DBG_STOP_Msk
8406 #define DBG_CR_DBG_STANDBY_Pos                         (2U)
8407 #define DBG_CR_DBG_STANDBY_Msk                         (0x1UL << DBG_CR_DBG_STANDBY_Pos)   /*!< 0x00000004 */
8408 #define DBG_CR_DBG_STANDBY                             DBG_CR_DBG_STANDBY_Msk
8409 
8410 
8411 /********************  Bit definition for DBG_APB_FZ1 register  ***********/
8412 #define DBG_APB_FZ1_DBG_TIM2_STOP_Pos                  (0U)
8413 #define DBG_APB_FZ1_DBG_TIM2_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
8414 #define DBG_APB_FZ1_DBG_TIM2_STOP                      DBG_APB_FZ1_DBG_TIM2_STOP_Msk
8415 #define DBG_APB_FZ1_DBG_TIM3_STOP_Pos                  (1U)
8416 #define DBG_APB_FZ1_DBG_TIM3_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
8417 #define DBG_APB_FZ1_DBG_TIM3_STOP                      DBG_APB_FZ1_DBG_TIM3_STOP_Msk
8418 #define DBG_APB_FZ1_DBG_TIM6_STOP_Pos                  (4U)
8419 #define DBG_APB_FZ1_DBG_TIM6_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
8420 #define DBG_APB_FZ1_DBG_TIM6_STOP                      DBG_APB_FZ1_DBG_TIM6_STOP_Msk
8421 #define DBG_APB_FZ1_DBG_TIM7_STOP_Pos                  (5U)
8422 #define DBG_APB_FZ1_DBG_TIM7_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
8423 #define DBG_APB_FZ1_DBG_TIM7_STOP                      DBG_APB_FZ1_DBG_TIM7_STOP_Msk
8424 #define DBG_APB_FZ1_DBG_RTC_STOP_Pos                   (10U)
8425 #define DBG_APB_FZ1_DBG_RTC_STOP_Msk                   (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos)  /*!< 0x00000400 */
8426 #define DBG_APB_FZ1_DBG_RTC_STOP                       DBG_APB_FZ1_DBG_RTC_STOP_Msk
8427 #define DBG_APB_FZ1_DBG_WWDG_STOP_Pos                  (11U)
8428 #define DBG_APB_FZ1_DBG_WWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
8429 #define DBG_APB_FZ1_DBG_WWDG_STOP                      DBG_APB_FZ1_DBG_WWDG_STOP_Msk
8430 #define DBG_APB_FZ1_DBG_IWDG_STOP_Pos                  (12U)
8431 #define DBG_APB_FZ1_DBG_IWDG_STOP_Msk                  (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
8432 #define DBG_APB_FZ1_DBG_IWDG_STOP                      DBG_APB_FZ1_DBG_IWDG_STOP_Msk
8433 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos    (21U)
8434 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk    (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
8435 #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP        DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
8436 #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos                (30U)
8437 #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk                (0x1UL << DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
8438 #define DBG_APB_FZ1_DBG_LPTIM2_STOP                    DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk
8439 #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos                (31U)
8440 #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk                (0x1UL << DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
8441 #define DBG_APB_FZ1_DBG_LPTIM1_STOP                    DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk
8442 
8443 /********************  Bit definition for DBG_APB_FZ2 register  ************/
8444 #define DBG_APB_FZ2_DBG_TIM1_STOP_Pos                  (11U)
8445 #define DBG_APB_FZ2_DBG_TIM1_STOP_Msk                  (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos)  /*!< 0x00000800 */
8446 #define DBG_APB_FZ2_DBG_TIM1_STOP                      DBG_APB_FZ2_DBG_TIM1_STOP_Msk
8447 #define DBG_APB_FZ2_DBG_TIM14_STOP_Pos                 (15U)
8448 #define DBG_APB_FZ2_DBG_TIM14_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
8449 #define DBG_APB_FZ2_DBG_TIM14_STOP                     DBG_APB_FZ2_DBG_TIM14_STOP_Msk
8450 #define DBG_APB_FZ2_DBG_TIM15_STOP_Pos                 (16U)
8451 #define DBG_APB_FZ2_DBG_TIM15_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
8452 #define DBG_APB_FZ2_DBG_TIM15_STOP                     DBG_APB_FZ2_DBG_TIM15_STOP_Msk
8453 #define DBG_APB_FZ2_DBG_TIM16_STOP_Pos                 (17U)
8454 #define DBG_APB_FZ2_DBG_TIM16_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
8455 #define DBG_APB_FZ2_DBG_TIM16_STOP                     DBG_APB_FZ2_DBG_TIM16_STOP_Msk
8456 #define DBG_APB_FZ2_DBG_TIM17_STOP_Pos                 (18U)
8457 #define DBG_APB_FZ2_DBG_TIM17_STOP_Msk                 (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
8458 #define DBG_APB_FZ2_DBG_TIM17_STOP                     DBG_APB_FZ2_DBG_TIM17_STOP_Msk
8459 
8460 /******************************************************************************/
8461 /*                                                                            */
8462 /*                                    UCPD                                   */
8463 /*                                                                            */
8464 /******************************************************************************/
8465 /********************  Bits definition for UCPD_CFG1 register  *******************/
8466 #define UCPD_CFG1_HBITCLKDIV_Pos            (0U)
8467 #define UCPD_CFG1_HBITCLKDIV_Msk            (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x0000003F */
8468 #define UCPD_CFG1_HBITCLKDIV                UCPD_CFG1_HBITCLKDIV_Msk              /*!< Number of cycles (minus 1) for a half bit clock */
8469 #define UCPD_CFG1_HBITCLKDIV_0              (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000001 */
8470 #define UCPD_CFG1_HBITCLKDIV_1              (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000002 */
8471 #define UCPD_CFG1_HBITCLKDIV_2              (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000004 */
8472 #define UCPD_CFG1_HBITCLKDIV_3              (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000008 */
8473 #define UCPD_CFG1_HBITCLKDIV_4              (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000010 */
8474 #define UCPD_CFG1_HBITCLKDIV_5              (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos)  /*!< 0x00000020 */
8475 #define UCPD_CFG1_IFRGAP_Pos                (6U)
8476 #define UCPD_CFG1_IFRGAP_Msk                (0x1FUL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x000007C0 */
8477 #define UCPD_CFG1_IFRGAP                    UCPD_CFG1_IFRGAP_Msk                  /*!< Clock divider value to generates Interframe gap */
8478 #define UCPD_CFG1_IFRGAP_0                  (0x01UL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x00000040 */
8479 #define UCPD_CFG1_IFRGAP_1                  (0x02UL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x00000080 */
8480 #define UCPD_CFG1_IFRGAP_2                  (0x04UL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x00000100 */
8481 #define UCPD_CFG1_IFRGAP_3                  (0x08UL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x00000200 */
8482 #define UCPD_CFG1_IFRGAP_4                  (0x10UL << UCPD_CFG1_IFRGAP_Pos)      /*!< 0x00000400 */
8483 #define UCPD_CFG1_TRANSWIN_Pos              (11U)
8484 #define UCPD_CFG1_TRANSWIN_Msk              (0x1FUL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x0000F800 */
8485 #define UCPD_CFG1_TRANSWIN                  UCPD_CFG1_TRANSWIN_Msk                /*!< Number of cycles (minus 1) of the half bit clock */
8486 #define UCPD_CFG1_TRANSWIN_0                (0x01UL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x00000800 */
8487 #define UCPD_CFG1_TRANSWIN_1                (0x02UL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x00001000 */
8488 #define UCPD_CFG1_TRANSWIN_2                (0x04UL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x00002000 */
8489 #define UCPD_CFG1_TRANSWIN_3                (0x08UL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x00004000 */
8490 #define UCPD_CFG1_TRANSWIN_4                (0x10UL << UCPD_CFG1_TRANSWIN_Pos)    /*!< 0x00008000 */
8491 #define UCPD_CFG1_PSC_UCPDCLK_Pos           (17U)
8492 #define UCPD_CFG1_PSC_UCPDCLK_Msk           (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos)  /*!< 0x000E0000 */
8493 #define UCPD_CFG1_PSC_UCPDCLK               UCPD_CFG1_PSC_UCPDCLK_Msk             /*!< Prescaler for UCPDCLK */
8494 #define UCPD_CFG1_PSC_UCPDCLK_0             (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos)  /*!< 0x00020000 */
8495 #define UCPD_CFG1_PSC_UCPDCLK_1             (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos)  /*!< 0x00040000 */
8496 #define UCPD_CFG1_PSC_UCPDCLK_2             (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos)  /*!< 0x00080000 */
8497 #define UCPD_CFG1_RXORDSETEN_Pos            (20U)
8498 #define UCPD_CFG1_RXORDSETEN_Msk            (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */
8499 #define UCPD_CFG1_RXORDSETEN                UCPD_CFG1_RXORDSETEN_Msk              /*!< Receiver ordered set detection enable */
8500 #define UCPD_CFG1_RXORDSETEN_0              (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */
8501 #define UCPD_CFG1_RXORDSETEN_1              (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */
8502 #define UCPD_CFG1_RXORDSETEN_2              (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */
8503 #define UCPD_CFG1_RXORDSETEN_3              (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */
8504 #define UCPD_CFG1_RXORDSETEN_4              (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */
8505 #define UCPD_CFG1_RXORDSETEN_5              (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */
8506 #define UCPD_CFG1_RXORDSETEN_6              (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */
8507 #define UCPD_CFG1_RXORDSETEN_7              (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */
8508 #define UCPD_CFG1_RXORDSETEN_8              (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */
8509 #define UCPD_CFG1_TXDMAEN_Pos               (29U)
8510 #define UCPD_CFG1_TXDMAEN_Msk               (0x1UL << UCPD_CFG1_TXDMAEN_Pos)      /*!< 0x20000000 */
8511 #define UCPD_CFG1_TXDMAEN                   UCPD_CFG1_TXDMAEN_Msk                 /*!< DMA transmission requests enable   */
8512 #define UCPD_CFG1_RXDMAEN_Pos               (30U)
8513 #define UCPD_CFG1_RXDMAEN_Msk               (0x1UL << UCPD_CFG1_RXDMAEN_Pos)      /*!< 0x40000000 */
8514 #define UCPD_CFG1_RXDMAEN                   UCPD_CFG1_RXDMAEN_Msk                 /*!< DMA reception requests enable   */
8515 #define UCPD_CFG1_UCPDEN_Pos                (31U)
8516 #define UCPD_CFG1_UCPDEN_Msk                (0x1UL << UCPD_CFG1_UCPDEN_Pos)       /*!< 0x80000000 */
8517 #define UCPD_CFG1_UCPDEN                    UCPD_CFG1_UCPDEN_Msk                  /*!< USB Power Delivery Block Enable */
8518 
8519 /********************  Bits definition for UCPD_CFG2 register  *******************/
8520 #define UCPD_CFG2_RXFILTDIS_Pos             (0U)
8521 #define UCPD_CFG2_RXFILTDIS_Msk             (0x1UL << UCPD_CFG2_RXFILTDIS_Pos)    /*!< 0x00000001 */
8522 #define UCPD_CFG2_RXFILTDIS                 UCPD_CFG2_RXFILTDIS_Msk               /*!< Enables an Rx pre-filter for the BMC decoder */
8523 #define UCPD_CFG2_RXFILT2N3_Pos             (1U)
8524 #define UCPD_CFG2_RXFILT2N3_Msk             (0x1UL << UCPD_CFG2_RXFILT2N3_Pos)    /*!< 0x00000002 */
8525 #define UCPD_CFG2_RXFILT2N3                 UCPD_CFG2_RXFILT2N3_Msk               /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
8526 #define UCPD_CFG2_FORCECLK_Pos              (2U)
8527 #define UCPD_CFG2_FORCECLK_Msk              (0x1UL << UCPD_CFG2_FORCECLK_Pos)     /*!< 0x00000004 */
8528 #define UCPD_CFG2_FORCECLK                  UCPD_CFG2_FORCECLK_Msk                /*!< Controls forcing of the clock request UCPDCLK_REQ */
8529 #define UCPD_CFG2_WUPEN_Pos                 (3U)
8530 #define UCPD_CFG2_WUPEN_Msk                 (0x1UL << UCPD_CFG2_WUPEN_Pos)        /*!< 0x00000008 */
8531 #define UCPD_CFG2_WUPEN                     UCPD_CFG2_WUPEN_Msk                   /*!< Wakeup from STOP enable */
8532 
8533 /********************  Bits definition for UCPD_CR register  ********************/
8534 #define UCPD_CR_TXMODE_Pos                  (0U)
8535 #define UCPD_CR_TXMODE_Msk                  (0x3UL << UCPD_CR_TXMODE_Pos)         /*!< 0x00000003 */
8536 #define UCPD_CR_TXMODE                      UCPD_CR_TXMODE_Msk                    /*!< Type of Tx packet  */
8537 #define UCPD_CR_TXMODE_0                    (0x1UL << UCPD_CR_TXMODE_Pos)         /*!< 0x00000001 */
8538 #define UCPD_CR_TXMODE_1                    (0x2UL << UCPD_CR_TXMODE_Pos)         /*!< 0x00000002 */
8539 #define UCPD_CR_TXSEND_Pos                  (2U)
8540 #define UCPD_CR_TXSEND_Msk                  (0x1UL << UCPD_CR_TXSEND_Pos)         /*!< 0x00000004 */
8541 #define UCPD_CR_TXSEND                      UCPD_CR_TXSEND_Msk                    /*!< Type of Tx packet  */
8542 #define UCPD_CR_TXHRST_Pos                  (3U)
8543 #define UCPD_CR_TXHRST_Msk                  (0x1UL << UCPD_CR_TXHRST_Pos)         /*!< 0x00000008 */
8544 #define UCPD_CR_TXHRST                      UCPD_CR_TXHRST_Msk                    /*!< Command to send a Tx Hard Reset  */
8545 #define UCPD_CR_RXMODE_Pos                  (4U)
8546 #define UCPD_CR_RXMODE_Msk                  (0x1UL << UCPD_CR_RXMODE_Pos)         /*!< 0x00000010 */
8547 #define UCPD_CR_RXMODE                      UCPD_CR_RXMODE_Msk                    /*!< Receiver mode  */
8548 #define UCPD_CR_PHYRXEN_Pos                 (5U)
8549 #define UCPD_CR_PHYRXEN_Msk                 (0x1UL << UCPD_CR_PHYRXEN_Pos)        /*!< 0x00000020 */
8550 #define UCPD_CR_PHYRXEN                     UCPD_CR_PHYRXEN_Msk                   /*!< Controls enable of USB Power Delivery receiver  */
8551 #define UCPD_CR_PHYCCSEL_Pos                (6U)
8552 #define UCPD_CR_PHYCCSEL_Msk                (0x1UL << UCPD_CR_PHYCCSEL_Pos)       /*!< 0x00000040 */
8553 #define UCPD_CR_PHYCCSEL                    UCPD_CR_PHYCCSEL_Msk                  /*!<  */
8554 #define UCPD_CR_ANASUBMODE_Pos              (7U)
8555 #define UCPD_CR_ANASUBMODE_Msk              (0x3UL << UCPD_CR_ANASUBMODE_Pos)     /*!< 0x00000180 */
8556 #define UCPD_CR_ANASUBMODE                  UCPD_CR_ANASUBMODE_Msk                /*!< Analog PHY sub-mode   */
8557 #define UCPD_CR_ANASUBMODE_0                (0x1UL << UCPD_CR_ANASUBMODE_Pos)     /*!< 0x00000080 */
8558 #define UCPD_CR_ANASUBMODE_1                (0x2UL << UCPD_CR_ANASUBMODE_Pos)     /*!< 0x00000100 */
8559 #define UCPD_CR_ANAMODE_Pos                 (9U)
8560 #define UCPD_CR_ANAMODE_Msk                 (0x1UL << UCPD_CR_ANAMODE_Pos)        /*!< 0x00000200 */
8561 #define UCPD_CR_ANAMODE                     UCPD_CR_ANAMODE_Msk                   /*!< Analog PHY working mode   */
8562 #define UCPD_CR_CCENABLE_Pos                (10U)
8563 #define UCPD_CR_CCENABLE_Msk                (0x3UL << UCPD_CR_CCENABLE_Pos)       /*!< 0x00000C00 */
8564 #define UCPD_CR_CCENABLE                    UCPD_CR_CCENABLE_Msk                  /*!<  */
8565 #define UCPD_CR_CCENABLE_0                  (0x1UL << UCPD_CR_CCENABLE_Pos)       /*!< 0x00000400 */
8566 #define UCPD_CR_CCENABLE_1                  (0x2UL << UCPD_CR_CCENABLE_Pos)       /*!< 0x00000800 */
8567 #define UCPD_CR_FRSRXEN_Pos                 (16U)
8568 #define UCPD_CR_FRSRXEN_Msk                 (0x1UL << UCPD_CR_FRSRXEN_Pos)        /*!< 0x00010000 */
8569 #define UCPD_CR_FRSRXEN                     UCPD_CR_FRSRXEN_Msk                   /*!< Enable FRS request detection function */
8570 #define UCPD_CR_FRSTX_Pos                   (17U)
8571 #define UCPD_CR_FRSTX_Msk                   (0x1UL << UCPD_CR_FRSTX_Pos)          /*!< 0x00020000 */
8572 #define UCPD_CR_FRSTX                       UCPD_CR_FRSTX_Msk                     /*!< Signal Fast Role Swap request */
8573 #define UCPD_CR_RDCH_Pos                    (18U)
8574 #define UCPD_CR_RDCH_Msk                    (0x1UL << UCPD_CR_RDCH_Pos)           /*!< 0x00040000 */
8575 #define UCPD_CR_RDCH                        UCPD_CR_RDCH_Msk                      /*!<  */
8576 #define UCPD_CR_CC1TCDIS_Pos                (20U)
8577 #define UCPD_CR_CC1TCDIS_Msk                (0x1UL << UCPD_CR_CC1TCDIS_Pos)       /*!< 0x00100000 */
8578 #define UCPD_CR_CC1TCDIS                    UCPD_CR_CC1TCDIS_Msk                  /*!< The bit allows the Type-C detector for CC0 to be disabled. */
8579 #define UCPD_CR_CC2TCDIS_Pos                (21U)
8580 #define UCPD_CR_CC2TCDIS_Msk                (0x1UL << UCPD_CR_CC2TCDIS_Pos)       /*!< 0x00200000 */
8581 #define UCPD_CR_CC2TCDIS                    UCPD_CR_CC2TCDIS_Msk                  /*!< The bit allows the Type-C detector for CC2 to be disabled. */
8582 
8583 /********************  Bits definition for UCPD_IMR register  *******************/
8584 #define UCPD_IMR_TXISIE_Pos                 (0U)
8585 #define UCPD_IMR_TXISIE_Msk                 (0x1UL << UCPD_IMR_TXISIE_Pos)        /*!< 0x00000001 */
8586 #define UCPD_IMR_TXISIE                     UCPD_IMR_TXISIE_Msk                   /*!< Enable TXIS interrupt  */
8587 #define UCPD_IMR_TXMSGDISCIE_Pos            (1U)
8588 #define UCPD_IMR_TXMSGDISCIE_Msk            (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos)   /*!< 0x00000002 */
8589 #define UCPD_IMR_TXMSGDISCIE                UCPD_IMR_TXMSGDISCIE_Msk              /*!< Enable TXMSGDISC interrupt  */
8590 #define UCPD_IMR_TXMSGSENTIE_Pos            (2U)
8591 #define UCPD_IMR_TXMSGSENTIE_Msk            (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos)   /*!< 0x00000004 */
8592 #define UCPD_IMR_TXMSGSENTIE                UCPD_IMR_TXMSGSENTIE_Msk              /*!< Enable TXMSGSENT interrupt  */
8593 #define UCPD_IMR_TXMSGABTIE_Pos             (3U)
8594 #define UCPD_IMR_TXMSGABTIE_Msk             (0x1UL << UCPD_IMR_TXMSGABTIE_Pos)    /*!< 0x00000008 */
8595 #define UCPD_IMR_TXMSGABTIE                 UCPD_IMR_TXMSGABTIE_Msk               /*!< Enable TXMSGABT interrupt  */
8596 #define UCPD_IMR_HRSTDISCIE_Pos             (4U)
8597 #define UCPD_IMR_HRSTDISCIE_Msk             (0x1UL << UCPD_IMR_HRSTDISCIE_Pos)    /*!< 0x00000010 */
8598 #define UCPD_IMR_HRSTDISCIE                 UCPD_IMR_HRSTDISCIE_Msk               /*!< Enable HRSTDISC interrupt  */
8599 #define UCPD_IMR_HRSTSENTIE_Pos             (5U)
8600 #define UCPD_IMR_HRSTSENTIE_Msk             (0x1UL << UCPD_IMR_HRSTSENTIE_Pos)    /*!< 0x00000020 */
8601 #define UCPD_IMR_HRSTSENTIE                 UCPD_IMR_HRSTSENTIE_Msk               /*!< Enable HRSTSENT interrupt  */
8602 #define UCPD_IMR_TXUNDIE_Pos                (6U)
8603 #define UCPD_IMR_TXUNDIE_Msk                (0x1UL << UCPD_IMR_TXUNDIE_Pos)       /*!< 0x00000040 */
8604 #define UCPD_IMR_TXUNDIE                    UCPD_IMR_TXUNDIE_Msk                  /*!< Enable TXUND interrupt  */
8605 #define UCPD_IMR_RXNEIE_Pos                 (8U)
8606 #define UCPD_IMR_RXNEIE_Msk                 (0x1UL << UCPD_IMR_RXNEIE_Pos)        /*!< 0x00000100 */
8607 #define UCPD_IMR_RXNEIE                     UCPD_IMR_RXNEIE_Msk                   /*!< Enable RXNE interrupt  */
8608 #define UCPD_IMR_RXORDDETIE_Pos             (9U)
8609 #define UCPD_IMR_RXORDDETIE_Msk             (0x1UL << UCPD_IMR_RXORDDETIE_Pos)    /*!< 0x00000200 */
8610 #define UCPD_IMR_RXORDDETIE                 UCPD_IMR_RXORDDETIE_Msk               /*!< Enable RXORDDET interrupt  */
8611 #define UCPD_IMR_RXHRSTDETIE_Pos            (10U)
8612 #define UCPD_IMR_RXHRSTDETIE_Msk            (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos)   /*!< 0x00000400 */
8613 #define UCPD_IMR_RXHRSTDETIE                UCPD_IMR_RXHRSTDETIE_Msk              /*!< Enable RXHRSTDET interrupt  */
8614 #define UCPD_IMR_RXOVRIE_Pos                (11U)
8615 #define UCPD_IMR_RXOVRIE_Msk                (0x1UL << UCPD_IMR_RXOVRIE_Pos)       /*!< 0x00000800 */
8616 #define UCPD_IMR_RXOVRIE                    UCPD_IMR_RXOVRIE_Msk                  /*!< Enable RXOVR interrupt  */
8617 #define UCPD_IMR_RXMSGENDIE_Pos             (12U)
8618 #define UCPD_IMR_RXMSGENDIE_Msk             (0x1UL << UCPD_IMR_RXMSGENDIE_Pos)    /*!< 0x00001000 */
8619 #define UCPD_IMR_RXMSGENDIE                 UCPD_IMR_RXMSGENDIE_Msk               /*!< Enable RXMSGEND interrupt  */
8620 #define UCPD_IMR_TYPECEVT1IE_Pos            (14U)
8621 #define UCPD_IMR_TYPECEVT1IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos)   /*!< 0x00004000 */
8622 #define UCPD_IMR_TYPECEVT1IE                UCPD_IMR_TYPECEVT1IE_Msk              /*!< Enable TYPECEVT1IE interrupt  */
8623 #define UCPD_IMR_TYPECEVT2IE_Pos            (15U)
8624 #define UCPD_IMR_TYPECEVT2IE_Msk            (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos)   /*!< 0x00008000 */
8625 #define UCPD_IMR_TYPECEVT2IE                UCPD_IMR_TYPECEVT2IE_Msk              /*!< Enable TYPECEVT2IE interrupt  */
8626 #define UCPD_IMR_FRSEVTIE_Pos               (20U)
8627 #define UCPD_IMR_FRSEVTIE_Msk               (0x1UL << UCPD_IMR_FRSEVTIE_Pos)      /*!< 0x00100000 */
8628 #define UCPD_IMR_FRSEVTIE                   UCPD_IMR_FRSEVTIE_Msk                 /*!< Fast Role Swap interrupt  */
8629 
8630 /********************  Bits definition for UCPD_SR register  ********************/
8631 #define UCPD_SR_TXIS_Pos                    (0U)
8632 #define UCPD_SR_TXIS_Msk                    (0x1UL << UCPD_SR_TXIS_Pos)           /*!< 0x00000001 */
8633 #define UCPD_SR_TXIS                        UCPD_SR_TXIS_Msk                      /*!< Transmit interrupt status  */
8634 #define UCPD_SR_TXMSGDISC_Pos               (1U)
8635 #define UCPD_SR_TXMSGDISC_Msk               (0x1UL << UCPD_SR_TXMSGDISC_Pos)      /*!< 0x00000002 */
8636 #define UCPD_SR_TXMSGDISC                   UCPD_SR_TXMSGDISC_Msk                 /*!< Transmit message discarded interrupt  */
8637 #define UCPD_SR_TXMSGSENT_Pos               (2U)
8638 #define UCPD_SR_TXMSGSENT_Msk               (0x1UL << UCPD_SR_TXMSGSENT_Pos)      /*!< 0x00000004 */
8639 #define UCPD_SR_TXMSGSENT                   UCPD_SR_TXMSGSENT_Msk                 /*!< Transmit message sent interrupt  */
8640 #define UCPD_SR_TXMSGABT_Pos                (3U)
8641 #define UCPD_SR_TXMSGABT_Msk                (0x1UL << UCPD_SR_TXMSGABT_Pos)       /*!< 0x00000008 */
8642 #define UCPD_SR_TXMSGABT                    UCPD_SR_TXMSGABT_Msk                  /*!< Transmit message abort interrupt  */
8643 #define UCPD_SR_HRSTDISC_Pos                (4U)
8644 #define UCPD_SR_HRSTDISC_Msk                (0x1UL << UCPD_SR_HRSTDISC_Pos)       /*!< 0x00000010 */
8645 #define UCPD_SR_HRSTDISC                    UCPD_SR_HRSTDISC_Msk                  /*!< HRST discarded interrupt  */
8646 #define UCPD_SR_HRSTSENT_Pos                (5U)
8647 #define UCPD_SR_HRSTSENT_Msk                (0x1UL << UCPD_SR_HRSTSENT_Pos)       /*!< 0x00000020 */
8648 #define UCPD_SR_HRSTSENT                    UCPD_SR_HRSTSENT_Msk                  /*!< HRST sent interrupt  */
8649 #define UCPD_SR_TXUND_Pos                   (6U)
8650 #define UCPD_SR_TXUND_Msk                   (0x1UL << UCPD_SR_TXUND_Pos)          /*!< 0x00000040 */
8651 #define UCPD_SR_TXUND                       UCPD_SR_TXUND_Msk                     /*!< Tx data underrun condition interrupt  */
8652 #define UCPD_SR_RXNE_Pos                    (8U)
8653 #define UCPD_SR_RXNE_Msk                    (0x1UL << UCPD_SR_RXNE_Pos)           /*!< 0x00000100 */
8654 #define UCPD_SR_RXNE                        UCPD_SR_RXNE_Msk                      /*!< Receive data register not empty interrupt  */
8655 #define UCPD_SR_RXORDDET_Pos                (9U)
8656 #define UCPD_SR_RXORDDET_Msk                (0x1UL << UCPD_SR_RXORDDET_Pos)       /*!< 0x00000200 */
8657 #define UCPD_SR_RXORDDET                    UCPD_SR_RXORDDET_Msk                  /*!< Rx ordered set (4 K-codes) detected interrupt  */
8658 #define UCPD_SR_RXHRSTDET_Pos               (10U)
8659 #define UCPD_SR_RXHRSTDET_Msk               (0x1UL << UCPD_SR_RXHRSTDET_Pos)      /*!< 0x00000400 */
8660 #define UCPD_SR_RXHRSTDET                   UCPD_SR_RXHRSTDET_Msk                 /*!< Rx Hard Reset detect interrupt  */
8661 #define UCPD_SR_RXOVR_Pos                   (11U)
8662 #define UCPD_SR_RXOVR_Msk                   (0x1UL << UCPD_SR_RXOVR_Pos)          /*!< 0x00000800 */
8663 #define UCPD_SR_RXOVR                       UCPD_SR_RXOVR_Msk                     /*!< Rx data overflow interrupt  */
8664 #define UCPD_SR_RXMSGEND_Pos                (12U)
8665 #define UCPD_SR_RXMSGEND_Msk                (0x1UL << UCPD_SR_RXMSGEND_Pos)       /*!< 0x00001000 */
8666 #define UCPD_SR_RXMSGEND                    UCPD_SR_RXMSGEND_Msk                  /*!< Rx message received  */
8667 #define UCPD_SR_RXERR_Pos                   (13U)
8668 #define UCPD_SR_RXERR_Msk                   (0x1UL << UCPD_SR_RXERR_Pos)          /*!< 0x00002000 */
8669 #define UCPD_SR_RXERR                       UCPD_SR_RXERR_Msk                     /*!< RX Error */
8670 #define UCPD_SR_TYPECEVT1_Pos               (14U)
8671 #define UCPD_SR_TYPECEVT1_Msk               (0x1UL << UCPD_SR_TYPECEVT1_Pos)      /*!< 0x00004000 */
8672 #define UCPD_SR_TYPECEVT1                   UCPD_SR_TYPECEVT1_Msk                 /*!< Type C voltage level event on CC1  */
8673 #define UCPD_SR_TYPECEVT2_Pos               (15U)
8674 #define UCPD_SR_TYPECEVT2_Msk               (0x1UL << UCPD_SR_TYPECEVT2_Pos)      /*!< 0x00008000 */
8675 #define UCPD_SR_TYPECEVT2                   UCPD_SR_TYPECEVT2_Msk                 /*!< Type C voltage level event on CC2  */
8676 #define UCPD_SR_TYPEC_VSTATE_CC1_Pos        (16U)
8677 #define UCPD_SR_TYPEC_VSTATE_CC1_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */
8678 #define UCPD_SR_TYPEC_VSTATE_CC1            UCPD_SR_TYPEC_VSTATE_CC1_Msk            /*!< Status of DC level on CC1 pin  */
8679 #define UCPD_SR_TYPEC_VSTATE_CC1_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */
8680 #define UCPD_SR_TYPEC_VSTATE_CC1_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */
8681 #define UCPD_SR_TYPEC_VSTATE_CC2_Pos        (18U)
8682 #define UCPD_SR_TYPEC_VSTATE_CC2_Msk        (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */
8683 #define UCPD_SR_TYPEC_VSTATE_CC2            UCPD_SR_TYPEC_VSTATE_CC2_Msk            /*!<Status of DC level on CC2 pin  */
8684 #define UCPD_SR_TYPEC_VSTATE_CC2_0          (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00040000 */
8685 #define UCPD_SR_TYPEC_VSTATE_CC2_1          (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x00080000 */
8686 #define UCPD_SR_FRSEVT_Pos                  (20U)
8687 #define UCPD_SR_FRSEVT_Msk                  (0x1UL << UCPD_SR_FRSEVT_Pos)         /*!< 0x00100000 */
8688 #define UCPD_SR_FRSEVT                      UCPD_SR_FRSEVT_Msk                    /*!< Fast Role Swap detection event  */
8689 
8690 /********************  Bits definition for UCPD_ICR register  *******************/
8691 #define UCPD_ICR_TXMSGDISCCF_Pos            (1U)
8692 #define UCPD_ICR_TXMSGDISCCF_Msk            (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos)   /*!< 0x00000002 */
8693 #define UCPD_ICR_TXMSGDISCCF                UCPD_ICR_TXMSGDISCCF_Msk              /*!< Tx message discarded flag (TXMSGDISC) clear  */
8694 #define UCPD_ICR_TXMSGSENTCF_Pos            (2U)
8695 #define UCPD_ICR_TXMSGSENTCF_Msk            (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos)   /*!< 0x00000004 */
8696 #define UCPD_ICR_TXMSGSENTCF                UCPD_ICR_TXMSGSENTCF_Msk              /*!< Tx message sent flag (TXMSGSENT) clear  */
8697 #define UCPD_ICR_TXMSGABTCF_Pos             (3U)
8698 #define UCPD_ICR_TXMSGABTCF_Msk             (0x1UL << UCPD_ICR_TXMSGABTCF_Pos)    /*!< 0x00000008 */
8699 #define UCPD_ICR_TXMSGABTCF                 UCPD_ICR_TXMSGABTCF_Msk               /*!< Tx message abort flag (TXMSGABT) clear  */
8700 #define UCPD_ICR_HRSTDISCCF_Pos             (4U)
8701 #define UCPD_ICR_HRSTDISCCF_Msk             (0x1UL << UCPD_ICR_HRSTDISCCF_Pos)    /*!< 0x00000010 */
8702 #define UCPD_ICR_HRSTDISCCF                 UCPD_ICR_HRSTDISCCF_Msk               /*!< Hard reset discarded flag (HRSTDISC) clear  */
8703 #define UCPD_ICR_HRSTSENTCF_Pos             (5U)
8704 #define UCPD_ICR_HRSTSENTCF_Msk             (0x1UL << UCPD_ICR_HRSTSENTCF_Pos)    /*!< 0x00000020 */
8705 #define UCPD_ICR_HRSTSENTCF                 UCPD_ICR_HRSTSENTCF_Msk               /*!< Hard reset sent flag (HRSTSENT) clear  */
8706 #define UCPD_ICR_TXUNDCF_Pos                (6U)
8707 #define UCPD_ICR_TXUNDCF_Msk                (0x1UL << UCPD_ICR_TXUNDCF_Pos)       /*!< 0x00000040 */
8708 #define UCPD_ICR_TXUNDCF                    UCPD_ICR_TXUNDCF_Msk                  /*!< Tx underflow flag (TXUND) clear  */
8709 #define UCPD_ICR_RXORDDETCF_Pos             (9U)
8710 #define UCPD_ICR_RXORDDETCF_Msk             (0x1UL << UCPD_ICR_RXORDDETCF_Pos)    /*!< 0x00000200 */
8711 #define UCPD_ICR_RXORDDETCF                 UCPD_ICR_RXORDDETCF_Msk               /*!< Rx ordered set detect flag (RXORDDET) clear  */
8712 #define UCPD_ICR_RXHRSTDETCF_Pos            (10U)
8713 #define UCPD_ICR_RXHRSTDETCF_Msk            (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos)   /*!< 0x00000400 */
8714 #define UCPD_ICR_RXHRSTDETCF                UCPD_ICR_RXHRSTDETCF_Msk              /*!< Rx Hard Reset detected flag (RXHRSTDET) clear  */
8715 #define UCPD_ICR_RXOVRCF_Pos                (11U)
8716 #define UCPD_ICR_RXOVRCF_Msk                (0x1UL << UCPD_ICR_RXOVRCF_Pos)       /*!< 0x00000800 */
8717 #define UCPD_ICR_RXOVRCF                    UCPD_ICR_RXOVRCF_Msk                  /*!< Rx overflow flag (RXOVR) clear  */
8718 #define UCPD_ICR_RXMSGENDCF_Pos             (12U)
8719 #define UCPD_ICR_RXMSGENDCF_Msk             (0x1UL << UCPD_ICR_RXMSGENDCF_Pos)    /*!< 0x00001000 */
8720 #define UCPD_ICR_RXMSGENDCF                 UCPD_ICR_RXMSGENDCF_Msk               /*!< Rx message received flag (RXMSGEND) clear  */
8721 #define UCPD_ICR_TYPECEVT1CF_Pos            (14U)
8722 #define UCPD_ICR_TYPECEVT1CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos)   /*!< 0x00004000 */
8723 #define UCPD_ICR_TYPECEVT1CF                UCPD_ICR_TYPECEVT1CF_Msk              /*!< TypeC event (CC1) flag (TYPECEVT1) clear  */
8724 #define UCPD_ICR_TYPECEVT2CF_Pos            (15U)
8725 #define UCPD_ICR_TYPECEVT2CF_Msk            (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos)   /*!< 0x00008000 */
8726 #define UCPD_ICR_TYPECEVT2CF                UCPD_ICR_TYPECEVT2CF_Msk              /*!< TypeC event (CC2) flag (TYPECEVT2) clear  */
8727 #define UCPD_ICR_FRSEVTCF_Pos               (20U)
8728 #define UCPD_ICR_FRSEVTCF_Msk               (0x1UL << UCPD_ICR_FRSEVTCF_Pos)      /*!< 0x00100000 */
8729 #define UCPD_ICR_FRSEVTCF                   UCPD_ICR_FRSEVTCF_Msk                 /*!< Fast Role Swap event flag clear  */
8730 
8731 /********************  Bits definition for UCPD_TXORDSET register  **************/
8732 #define UCPD_TX_ORDSET_TXORDSET_Pos         (0U)
8733 #define UCPD_TX_ORDSET_TXORDSET_Msk         (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos) /*!< 0x000FFFFF */
8734 #define UCPD_TX_ORDSET_TXORDSET             UCPD_TX_ORDSET_TXORDSET_Msk                /*!< Tx Ordered Set */
8735 
8736 /********************  Bits definition for UCPD_TXPAYSZ register  ****************/
8737 #define UCPD_TX_PAYSZ_TXPAYSZ_Pos           (0U)
8738 #define UCPD_TX_PAYSZ_TXPAYSZ_Msk           (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos) /*!< 0x000003FF */
8739 #define UCPD_TX_PAYSZ_TXPAYSZ               UCPD_TX_PAYSZ_TXPAYSZ_Msk              /*!< Tx payload size in bytes  */
8740 
8741 /********************  Bits definition for UCPD_TXDR register  *******************/
8742 #define UCPD_TXDR_TXDATA_Pos                (0U)
8743 #define UCPD_TXDR_TXDATA_Msk                 (0xFFUL << UCPD_TXDR_TXDATA_Pos)      /*!< 0x000000FF */
8744 #define UCPD_TXDR_TXDATA                    UCPD_TXDR_TXDATA_Msk                   /*!< Tx Data Register */
8745 
8746 /********************  Bits definition for UCPD_RXORDSET register  **************/
8747 #define UCPD_RX_ORDSET_RXORDSET_Pos         (0U)
8748 #define UCPD_RX_ORDSET_RXORDSET_Msk         (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000007 */
8749 #define UCPD_RX_ORDSET_RXORDSET             UCPD_RX_ORDSET_RXORDSET_Msk             /*!< Rx Ordered Set Code detected  */
8750 #define UCPD_RX_ORDSET_RXORDSET_0           (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000001 */
8751 #define UCPD_RX_ORDSET_RXORDSET_1           (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000002 */
8752 #define UCPD_RX_ORDSET_RXORDSET_2           (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos)  /*!< 0x00000004 */
8753 #define UCPD_RX_ORDSET_RXSOP3OF4_Pos        (3U)
8754 #define UCPD_RX_ORDSET_RXSOP3OF4_Msk        (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos) /*!< 0x00000008 */
8755 #define UCPD_RX_ORDSET_RXSOP3OF4            UCPD_RX_ORDSET_RXSOP3OF4_Msk            /*!< Rx Ordered Set Debug indication */
8756 #define UCPD_RX_ORDSET_RXSOPKINVALID_Pos    (4U)
8757 #define UCPD_RX_ORDSET_RXSOPKINVALID_Msk    (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos) /*!< 0x00000070 */
8758 #define UCPD_RX_ORDSET_RXSOPKINVALID        UCPD_RX_ORDSET_RXSOPKINVALID_Msk            /*!< Rx Ordered Set corrupted K-Codes (Debug) */
8759 
8760 /********************  Bits definition for UCPD_RXPAYSZ register  ****************/
8761 #define UCPD_RX_PAYSZ_RXPAYSZ_Pos           (0U)
8762 #define UCPD_RX_PAYSZ_RXPAYSZ_Msk           (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos) /*!< 0x000003FF */
8763 #define UCPD_RX_PAYSZ_RXPAYSZ               UCPD_RX_PAYSZ_RXPAYSZ_Msk              /*!< Rx payload size in bytes  */
8764 
8765 /********************  Bits definition for UCPD_RXDR register  *******************/
8766 #define UCPD_RXDR_RXDATA_Pos                (0U)
8767 #define UCPD_RXDR_RXDATA_Msk                (0xFFUL << UCPD_RXDR_RXDATA_Pos)      /*!< 0x000000FF */
8768 #define UCPD_RXDR_RXDATA                    UCPD_RXDR_RXDATA_Msk                  /*!< 8-bit receive data  */
8769 
8770 /********************  Bits definition for UCPD_RXORDEXT1 register  **************/
8771 #define UCPD_RX_ORDEXT1_RXSOPX1_Pos         (0U)
8772 #define UCPD_RX_ORDEXT1_RXSOPX1_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos) /*!< 0x000FFFFF */
8773 #define UCPD_RX_ORDEXT1_RXSOPX1             UCPD_RX_ORDEXT1_RXSOPX1_Msk                /*!< RX Ordered Set Extension Register 1 */
8774 
8775 /********************  Bits definition for UCPD_RXORDEXT2 register  **************/
8776 #define UCPD_RX_ORDEXT2_RXSOPX2_Pos         (0U)
8777 #define UCPD_RX_ORDEXT2_RXSOPX2_Msk         (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos) /*!< 0x000FFFFF */
8778 #define UCPD_RX_ORDEXT2_RXSOPX2             UCPD_RX_ORDEXT2_RXSOPX2_Msk                /*!< RX Ordered Set Extension Register 1 */
8779 
8780 
8781 /** @addtogroup Exported_macros
8782   * @{
8783   */
8784 
8785 /******************************* ADC Instances ********************************/
8786 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
8787 
8788 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
8789 
8790 
8791 /****************************** CEC Instances *********************************/
8792 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
8793 
8794 /******************************** COMP Instances ******************************/
8795 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
8796                                         ((INSTANCE) == COMP2))
8797 
8798 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
8799 
8800 /******************** COMP Instances with window mode capability **************/
8801 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
8802                                                ((INSTANCE) == COMP2))
8803 
8804 /******************************* CRC Instances ********************************/
8805 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8806 
8807 /******************************* DAC Instances ********************************/
8808 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
8809 
8810 /******************************** DMA Instances *******************************/
8811 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
8812                                        ((INSTANCE) == DMA1_Channel2) || \
8813                                        ((INSTANCE) == DMA1_Channel3) || \
8814                                        ((INSTANCE) == DMA1_Channel4) || \
8815                                        ((INSTANCE) == DMA1_Channel5) || \
8816                                        ((INSTANCE) == DMA1_Channel6) || \
8817                                        ((INSTANCE) == DMA1_Channel7))
8818 
8819 /******************************** DMAMUX Instances ****************************/
8820 #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
8821 
8822 #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
8823                                                       ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
8824                                                       ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
8825                                                       ((INSTANCE) == DMAMUX1_RequestGenerator3))
8826 
8827 /******************************* GPIO Instances *******************************/
8828 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8829                                         ((INSTANCE) == GPIOB) || \
8830                                         ((INSTANCE) == GPIOC) || \
8831                                         ((INSTANCE) == GPIOD) || \
8832                                         ((INSTANCE) == GPIOF))
8833 /******************************* GPIO AF Instances ****************************/
8834 #define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
8835 
8836 /**************************** GPIO Lock Instances *****************************/
8837 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8838                                          ((INSTANCE) == GPIOB) || \
8839                                          ((INSTANCE) == GPIOC))
8840 
8841 /******************************** I2C Instances *******************************/
8842 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8843                                        ((INSTANCE) == I2C2))
8844 
8845 
8846 /****************************** RTC Instances *********************************/
8847 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
8848 
8849 /****************************** SMBUS Instances *******************************/
8850 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
8851 
8852 /****************************** WAKEUP_FROMSTOP Instances *******************************/
8853 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
8854 
8855 /******************************** SPI Instances *******************************/
8856 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8857                                        ((INSTANCE) == SPI2))
8858 
8859 /******************************** SPI Instances *******************************/
8860 #define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI1)
8861 
8862 /****************** LPTIM Instances : All supported instances *****************/
8863 #define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
8864                                          ((INSTANCE) == LPTIM2))
8865 
8866 /****************** LPTIM Instances : All supported instances *****************/
8867 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
8868 
8869 /****************** TIM Instances : All supported instances *******************/
8870 #define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
8871                                          ((INSTANCE) == TIM2)   || \
8872                                          ((INSTANCE) == TIM3)   || \
8873                                          ((INSTANCE) == TIM6)   || \
8874                                          ((INSTANCE) == TIM7)   || \
8875                                          ((INSTANCE) == TIM14)  || \
8876                                          ((INSTANCE) == TIM15)  || \
8877                                          ((INSTANCE) == TIM16)  || \
8878                                          ((INSTANCE) == TIM17))
8879 
8880 /****************** TIM Instances : supporting 32 bits counter ****************/
8881 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
8882 
8883 /****************** TIM Instances : supporting the break function *************/
8884 #define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
8885                                             ((INSTANCE) == TIM15)   || \
8886                                             ((INSTANCE) == TIM16)   || \
8887                                             ((INSTANCE) == TIM17))
8888 
8889 /************** TIM Instances : supporting Break source selection *************/
8890 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8891                                                ((INSTANCE) == TIM15)  || \
8892                                                ((INSTANCE) == TIM16)  || \
8893                                                ((INSTANCE) == TIM17))
8894 
8895 /****************** TIM Instances : supporting 2 break inputs *****************/
8896 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
8897 
8898 /************* TIM Instances : at least 1 capture/compare channel *************/
8899 #define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8900                                          ((INSTANCE) == TIM2)   || \
8901                                          ((INSTANCE) == TIM3)   || \
8902                                          ((INSTANCE) == TIM14)  || \
8903                                          ((INSTANCE) == TIM15)  || \
8904                                          ((INSTANCE) == TIM16)  || \
8905                                          ((INSTANCE) == TIM17))
8906 
8907 /************ TIM Instances : at least 2 capture/compare channels *************/
8908 #define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8909                                          ((INSTANCE) == TIM2)   || \
8910                                          ((INSTANCE) == TIM3)   || \
8911                                          ((INSTANCE) == TIM15))
8912 
8913 /************ TIM Instances : at least 3 capture/compare channels *************/
8914 #define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8915                                          ((INSTANCE) == TIM2)   || \
8916                                          ((INSTANCE) == TIM3))
8917 
8918 /************ TIM Instances : at least 4 capture/compare channels *************/
8919 #define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8920                                          ((INSTANCE) == TIM2)   || \
8921                                          ((INSTANCE) == TIM3))
8922 
8923 /****************** TIM Instances : at least 5 capture/compare channels *******/
8924 #define IS_TIM_CC5_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
8925 
8926 /****************** TIM Instances : at least 6 capture/compare channels *******/
8927 #define IS_TIM_CC6_INSTANCE(INSTANCE)   ((INSTANCE) == TIM1)
8928 
8929 /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
8930 #define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
8931                                             ((INSTANCE) == TIM15)  || \
8932                                             ((INSTANCE) == TIM16)  || \
8933                                             ((INSTANCE) == TIM17))
8934 
8935 /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
8936 #define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
8937                                             ((INSTANCE) == TIM2)   || \
8938                                             ((INSTANCE) == TIM3)   || \
8939                                             ((INSTANCE) == TIM6)   || \
8940                                             ((INSTANCE) == TIM7)   || \
8941                                             ((INSTANCE) == TIM15)  || \
8942                                             ((INSTANCE) == TIM16)  || \
8943                                             ((INSTANCE) == TIM17))
8944 
8945 /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
8946 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
8947                                             ((INSTANCE) == TIM2)   || \
8948                                             ((INSTANCE) == TIM3)   || \
8949                                             ((INSTANCE) == TIM14)  || \
8950                                             ((INSTANCE) == TIM15)  || \
8951                                             ((INSTANCE) == TIM16)  || \
8952                                             ((INSTANCE) == TIM17))
8953 
8954 /******************** TIM Instances : DMA burst feature ***********************/
8955 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
8956                                             ((INSTANCE) == TIM2)   || \
8957                                             ((INSTANCE) == TIM3)   || \
8958                                             ((INSTANCE) == TIM15)  || \
8959                                             ((INSTANCE) == TIM16)  || \
8960                                             ((INSTANCE) == TIM17))
8961 
8962 /******************* TIM Instances : output(s) available **********************/
8963 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8964     ((((INSTANCE) == TIM1) &&                  \
8965      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8966       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8967       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8968       ((CHANNEL) == TIM_CHANNEL_4) ||          \
8969       ((CHANNEL) == TIM_CHANNEL_5) ||          \
8970       ((CHANNEL) == TIM_CHANNEL_6)))           \
8971      ||                                        \
8972      (((INSTANCE) == TIM2) &&                  \
8973      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8974       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8975       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8976       ((CHANNEL) == TIM_CHANNEL_4)))           \
8977      ||                                        \
8978      (((INSTANCE) == TIM3) &&                  \
8979      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8980       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8981       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8982       ((CHANNEL) == TIM_CHANNEL_4)))           \
8983      ||                                        \
8984      (((INSTANCE) == TIM14) &&                 \
8985      (((CHANNEL) == TIM_CHANNEL_1)))           \
8986      ||                                        \
8987      (((INSTANCE) == TIM15) &&                 \
8988      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8989       ((CHANNEL) == TIM_CHANNEL_2)))           \
8990      ||                                        \
8991      (((INSTANCE) == TIM16) &&                 \
8992      (((CHANNEL) == TIM_CHANNEL_1)))           \
8993      ||                                        \
8994      (((INSTANCE) == TIM17) &&                 \
8995       (((CHANNEL) == TIM_CHANNEL_1))))
8996 
8997 /****************** TIM Instances : supporting complementary output(s) ********/
8998 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8999    ((((INSTANCE) == TIM1) &&                    \
9000      (((CHANNEL) == TIM_CHANNEL_1) ||           \
9001       ((CHANNEL) == TIM_CHANNEL_2) ||           \
9002       ((CHANNEL) == TIM_CHANNEL_3)))            \
9003     ||                                          \
9004     (((INSTANCE) == TIM15) &&                   \
9005      ((CHANNEL) == TIM_CHANNEL_1))              \
9006     ||                                          \
9007     (((INSTANCE) == TIM16) &&                   \
9008      ((CHANNEL) == TIM_CHANNEL_1))              \
9009     ||                                          \
9010     (((INSTANCE) == TIM17) &&                   \
9011      ((CHANNEL) == TIM_CHANNEL_1)))
9012 
9013 /****************** TIM Instances : supporting clock division *****************/
9014 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
9015                                                     ((INSTANCE) == TIM2)    || \
9016                                                     ((INSTANCE) == TIM3)    || \
9017                                                     ((INSTANCE) == TIM14)   || \
9018                                                     ((INSTANCE) == TIM15)   || \
9019                                                     ((INSTANCE) == TIM16)   || \
9020                                                     ((INSTANCE) == TIM17))
9021 
9022 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
9023 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9024                                                         ((INSTANCE) == TIM2) || \
9025                                                         ((INSTANCE) == TIM3))
9026 
9027 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
9028 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9029                                                         ((INSTANCE) == TIM2) || \
9030                                                         ((INSTANCE) == TIM3))
9031 
9032 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
9033 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
9034                                                         ((INSTANCE) == TIM2) || \
9035                                                         ((INSTANCE) == TIM3) || \
9036                                                         ((INSTANCE) == TIM15))
9037 
9038 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
9039 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
9040                                                         ((INSTANCE) == TIM2) || \
9041                                                         ((INSTANCE) == TIM3) || \
9042                                                         ((INSTANCE) == TIM15))
9043 
9044 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
9045 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
9046 
9047 /****************** TIM Instances : supporting commutation event generation ***/
9048 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
9049                                                      ((INSTANCE) == TIM15)  || \
9050                                                      ((INSTANCE) == TIM16)  || \
9051                                                      ((INSTANCE) == TIM17))
9052 
9053 /****************** TIM Instances : supporting counting mode selection ********/
9054 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
9055                                                         ((INSTANCE) == TIM2) || \
9056                                                         ((INSTANCE) == TIM3))
9057 
9058 /****************** TIM Instances : supporting encoder interface **************/
9059 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
9060                                                       ((INSTANCE) == TIM2)  || \
9061                                                       ((INSTANCE) == TIM3))
9062 
9063 /****************** TIM Instances : supporting Hall sensor interface **********/
9064 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
9065                                                          ((INSTANCE) == TIM2)   || \
9066                                                          ((INSTANCE) == TIM3))
9067 
9068 /**************** TIM Instances : external trigger input available ************/
9069 #define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
9070                                             ((INSTANCE) == TIM2)  || \
9071                                             ((INSTANCE) == TIM3))
9072 
9073 /************* TIM Instances : supporting ETR source selection ***************/
9074 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
9075                                              ((INSTANCE) == TIM2)  || \
9076                                              ((INSTANCE) == TIM3))
9077 
9078 /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
9079 #define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
9080                                             ((INSTANCE) == TIM2)  || \
9081                                             ((INSTANCE) == TIM3)  || \
9082                                             ((INSTANCE) == TIM6)  || \
9083                                             ((INSTANCE) == TIM7)  || \
9084                                             ((INSTANCE) == TIM15))
9085 
9086 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
9087 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
9088                                             ((INSTANCE) == TIM2)  || \
9089                                             ((INSTANCE) == TIM3)  || \
9090                                             ((INSTANCE) == TIM15))
9091 
9092 /****************** TIM Instances : supporting OCxREF clear *******************/
9093 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
9094                                                        ((INSTANCE) == TIM2) || \
9095                                                        ((INSTANCE) == TIM3))
9096 
9097 /****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
9098 #define IS_TIM_OCCS_INSTANCE(INSTANCE)                (((INSTANCE) == TIM1)  || \
9099                                                        ((INSTANCE) == TIM2)  || \
9100                                                        ((INSTANCE) == TIM3))
9101 
9102 /****************** TIM Instances : remapping capability **********************/
9103 #define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
9104                                             ((INSTANCE) == TIM2)  || \
9105                                             ((INSTANCE) == TIM3))
9106 
9107 /****************** TIM Instances : supporting repetition counter *************/
9108 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
9109                                                        ((INSTANCE) == TIM15) || \
9110                                                        ((INSTANCE) == TIM16) || \
9111                                                        ((INSTANCE) == TIM17))
9112 
9113 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
9114 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
9115 
9116 /******************* TIM Instances : Timer input XOR function *****************/
9117 #define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
9118                                             ((INSTANCE) == TIM2)   || \
9119                                             ((INSTANCE) == TIM3)   || \
9120                                             ((INSTANCE) == TIM15))
9121 
9122 /******************* TIM Instances : Timer input selection ********************/
9123 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
9124                                          ((INSTANCE) == TIM2)   || \
9125                                          ((INSTANCE) == TIM3)   || \
9126                                          ((INSTANCE) == TIM14)  || \
9127                                          ((INSTANCE) == TIM15)  || \
9128                                          ((INSTANCE) == TIM16)  || \
9129                                          ((INSTANCE) == TIM17))
9130 
9131 /************ TIM Instances : Advanced timers  ********************************/
9132 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
9133 
9134 /******************** UART Instances : Asynchronous mode **********************/
9135 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9136                                     ((INSTANCE) == USART2) || \
9137                                     ((INSTANCE) == USART3) || \
9138                                     ((INSTANCE) == USART4))
9139 
9140 /******************** USART Instances : Synchronous mode **********************/
9141 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9142                                      ((INSTANCE) == USART2) || \
9143                                      ((INSTANCE) == USART3) || \
9144                                      ((INSTANCE) == USART4))
9145 
9146 /****************** UART Instances : Hardware Flow control ********************/
9147 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9148                                            ((INSTANCE) == USART2) || \
9149                                            ((INSTANCE) == USART3) || \
9150                                            ((INSTANCE) == USART4) || \
9151                                            ((INSTANCE) == LPUART1))
9152 
9153 
9154 /********************* USART Instances : Smard card mode ***********************/
9155 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9156                                          ((INSTANCE) == USART2))
9157 
9158 /****************** UART Instances : Auto Baud Rate detection ****************/
9159 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9160                                                             ((INSTANCE) == USART2))
9161 
9162 /******************** UART Instances : Half-Duplex mode **********************/
9163 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9164                                                  ((INSTANCE) == USART2) || \
9165                                                  ((INSTANCE) == USART3) || \
9166                                                  ((INSTANCE) == USART4) || \
9167                                                  ((INSTANCE) == LPUART1))
9168 
9169 /******************** UART Instances : LIN mode **********************/
9170 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9171                                           ((INSTANCE) == USART2))
9172 
9173 /******************** UART Instances : Wake-up from Stop mode **********************/
9174 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9175                                                       ((INSTANCE) == USART2) || \
9176                                                       ((INSTANCE) == LPUART1))
9177 
9178 /****************** UART Instances : Driver Enable *****************/
9179 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
9180                                                       ((INSTANCE) == USART2) || \
9181                                                       ((INSTANCE) == USART3) || \
9182                                                       ((INSTANCE) == USART4) || \
9183                                                       ((INSTANCE) == LPUART1))
9184 
9185 
9186 /****************** UART Instances : SPI Slave selection mode ***************/
9187 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9188                                               ((INSTANCE) == USART2) || \
9189                                               ((INSTANCE) == USART3) || \
9190                                               ((INSTANCE) == USART4))
9191 
9192 
9193 /****************** UART Instances : Driver Enable *****************/
9194 #define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
9195                                              ((INSTANCE) == USART2) || \
9196                                              ((INSTANCE) == LPUART1))
9197 
9198 /*********************** UART Instances : IRDA mode ***************************/
9199 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9200                                     ((INSTANCE) == USART2))
9201 
9202 /******************** LPUART Instance *****************************************/
9203 #define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
9204 
9205 /****************************** IWDG Instances ********************************/
9206 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
9207 
9208 /****************************** WWDG Instances ********************************/
9209 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
9210 
9211 /****************************** UCPD Instances ********************************/
9212 #define IS_UCPD_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == UCPD1) || \
9213                                          ((INSTANCE) == UCPD2))
9214 
9215 /******************************************************************************/
9216 /*  For a painless codes migration between the STM32G0xx device product       */
9217 /*  lines, the aliases defined below are put in place to overcome the         */
9218 /*  differences in the interrupt handlers and IRQn definitions.               */
9219 /*  No need to update developed interrupt code when moving across             */
9220 /*  product lines within the same STM32G0 Family                              */
9221 /******************************************************************************/
9222 /* Aliases for IRQn_Type */
9223 #define SVC_IRQn              SVCall_IRQn
9224 
9225 /**
9226   * @}
9227   */
9228 
9229  /**
9230   * @}
9231   */
9232 
9233 /**
9234   * @}
9235   */
9236 
9237 #ifdef __cplusplus
9238 }
9239 #endif /* __cplusplus */
9240 
9241 #endif /* STM32G071xx_H */
9242 
9243 /**
9244   * @}
9245   */
9246 
9247   /**
9248   * @}
9249   */
9250