1 /** 2 ****************************************************************************** 3 * @file stm32g0xx_ll_usb.h 4 * @author MCD Application Team 5 * @brief Header file of USB Low Layer HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G0xx_LL_USB_H 21 #define STM32G0xx_LL_USB_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif /* __cplusplus */ 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g0xx_hal_def.h" 29 30 #if defined (USB_DRD_FS) 31 /** @addtogroup STM32G0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup USB_LL 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 41 /** 42 * @brief USB Mode definition 43 */ 44 45 46 typedef enum 47 { 48 USB_DEVICE_MODE = 0, 49 USB_HOST_MODE = 1 50 } USB_DRD_ModeTypeDef; 51 52 /** 53 * @brief URB States definition 54 */ 55 typedef enum 56 { 57 URB_IDLE = 0, 58 URB_DONE, 59 URB_NOTREADY, 60 URB_NYET, 61 URB_ERROR, 62 URB_STALL 63 } USB_DRD_URBStateTypeDef; 64 65 /** 66 * @brief Host channel States definition 67 */ 68 typedef enum 69 { 70 HC_IDLE = 0, 71 HC_XFRC, 72 HC_HALTED, 73 HC_ACK, 74 HC_NAK, 75 HC_NYET, 76 HC_STALL, 77 HC_XACTERR, 78 HC_BBLERR, 79 HC_DATATGLERR 80 } USB_DRD_HCStateTypeDef; 81 82 83 /** 84 * @brief USB Instance Initialization Structure definition 85 */ 86 typedef struct 87 { 88 uint32_t dev_endpoints; /*!< Device Endpoints number. 89 This parameter depends on the used USB core. 90 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 91 92 uint32_t Host_channels; /*!< Host Channels number. 93 This parameter Depends on the used USB core. 94 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 95 96 uint32_t speed; /*!< USB Core speed. 97 This parameter can be any value of @ref PCD_Speed/HCD_Speed 98 (HCD_SPEED_xxx, HCD_SPEED_xxx) */ 99 100 uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */ 101 102 uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ 103 104 uint32_t phy_itface; /*!< Select the used PHY interface. 105 This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ 106 107 uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ 108 109 uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ 110 111 uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */ 112 113 uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */ 114 115 uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ 116 117 uint32_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ 118 119 uint32_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ 120 } USB_DRD_CfgTypeDef; 121 122 typedef struct 123 { 124 uint8_t num; /*!< Endpoint number 125 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 126 127 uint8_t is_in; /*!< Endpoint direction 128 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 129 130 uint8_t is_stall; /*!< Endpoint stall condition 131 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 132 133 uint8_t type; /*!< Endpoint type 134 This parameter can be any value of @ref USB_LL_EP_Type */ 135 136 uint16_t pmaadress; /*!< PMA Address 137 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 138 139 uint16_t pmaaddr0; /*!< PMA Address0 140 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 141 142 uint16_t pmaaddr1; /*!< PMA Address1 143 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 144 145 uint8_t doublebuffer; /*!< Double buffer enable 146 This parameter can be 0 or 1 */ 147 148 uint8_t data_pid_start; /*!< Initial data PID 149 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 150 151 uint16_t tx_fifo_num; /*!< Transmission FIFO number 152 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 153 154 uint32_t maxpacket; /*!< Endpoint Max packet size 155 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 156 157 uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ 158 159 uint32_t xfer_len; /*!< Current transfer length */ 160 161 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ 162 163 uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ 164 165 uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ 166 } USB_DRD_EPTypeDef; 167 168 typedef struct 169 { 170 uint8_t dev_addr; /*!< USB device address. 171 This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ 172 173 uint8_t phy_ch_num; /*!< Host channel number. 174 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 175 176 uint8_t ep_num; /*!< Endpoint number. 177 This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ 178 179 uint8_t ch_dir; /*!< channel direction 180 This parameter store the physical channel direction IN/OUT/BIDIR */ 181 182 uint8_t speed; /*!< USB Host Channel speed. 183 This parameter can be any value of @ref HCD_Device_Speed: 184 (HCD_DEVICE_SPEED_xxx) */ 185 186 uint8_t ep_type; /*!< Endpoint Type. 187 This parameter can be any value of @ref USB_LL_EP_Type */ 188 189 uint16_t max_packet; /*!< Endpoint Max packet size. 190 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ 191 192 uint8_t data_pid; /*!< Initial data PID. 193 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 194 195 uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ 196 197 uint32_t xfer_len; /*!< Current transfer length. */ 198 199 uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ 200 201 uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ 202 203 uint8_t toggle_in; /*!< IN transfer current toggle flag. 204 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 205 206 uint8_t toggle_out; /*!< OUT transfer current toggle flag 207 This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ 208 209 uint32_t ErrCnt; /*!< Host channel error count. */ 210 211 uint16_t pmaadress; /*!< PMA Address 212 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 213 214 uint16_t pmaaddr0; /*!< PMA Address0 215 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 216 217 uint16_t pmaaddr1; /*!< PMA Address1 218 This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ 219 220 uint8_t doublebuffer; /*!< Double buffer enable 221 This parameter can be 0 or 1 */ 222 223 USB_DRD_URBStateTypeDef urb_state; /*!< URB state. 224 This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 225 226 USB_DRD_HCStateTypeDef state; /*!< Host Channel state. 227 This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ 228 } USB_DRD_HCTypeDef; 229 230 231 232 /* Exported constants --------------------------------------------------------*/ 233 234 /** @defgroup PCD_Exported_Constants PCD Exported Constants 235 * @{ 236 */ 237 238 239 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS 240 * @{ 241 */ 242 #define EP_MPS_64 0U 243 #define EP_MPS_32 1U 244 #define EP_MPS_16 2U 245 #define EP_MPS_8 3U 246 /** 247 * @} 248 */ 249 250 /** @defgroup USB_LL_EP_Type USB Low Layer EP Type 251 * @{ 252 */ 253 #define EP_TYPE_CTRL 0U 254 #define EP_TYPE_ISOC 1U 255 #define EP_TYPE_BULK 2U 256 #define EP_TYPE_INTR 3U 257 #define EP_TYPE_MSK 3U 258 /** 259 * @} 260 */ 261 262 /** @defgroup USB_LL Device Speed 263 * @{ 264 */ 265 #define USBD_FS_SPEED 2U 266 #define USBH_FSLS_SPEED 1U 267 /** 268 * @} 269 */ 270 271 #define BTABLE_ADDRESS 0x000U 272 273 #define EP_ADDR_MSK 0x7U 274 275 #ifndef USE_USB_DOUBLE_BUFFER 276 #define USE_USB_DOUBLE_BUFFER 1U 277 #endif /* USE_USB_DOUBLE_BUFFER */ 278 279 /*!< USB Speed */ 280 #define USB_DRD_SPEED_FS 1U 281 #define USB_DRD_SPEED_LS 2U 282 #define USB_DRD_SPEED_LSFS 3U 283 284 /*!< PID */ 285 #define HC_PID_DATA0 0U 286 #define HC_PID_DATA2 1U 287 #define HC_PID_DATA1 2U 288 #define HC_PID_SETUP 3U 289 290 /*!< Channel Direction */ 291 #define CH_IN_DIR 1U 292 #define CH_OUT_DIR 0U 293 294 /*!< Number of used channels in the Application */ 295 #ifndef USB_DRD_USED_CHANNELS 296 #define USB_DRD_USED_CHANNELS 8U 297 #endif /* USB_DRD_USED_CHANNELS */ 298 299 /** 300 * used for USB_HC_DoubleBuffer API 301 */ 302 #define USB_DRD_BULK_DBUFF_ENBALE 1U 303 #define USB_DRD_BULK_DBUFF_DISABLE 2U 304 #define USB_DRD_ISOC_DBUFF_ENBALE 3U 305 #define USB_DRD_ISOC_DBUFF_DISABLE 4U 306 307 /* First available address in PMA */ 308 #define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) 309 #define PMA_END_ADDR USB_DRD_PMA_SIZE 310 311 /* Exported macro ------------------------------------------------------------*/ 312 /** 313 * @} 314 */ 315 /******************** Bit definition for USB_COUNTn_RX register *************/ 316 #define USB_CNTRX_NBLK_MSK (0x1FU << 26) 317 #define USB_CNTRX_BLSIZE (0x1U << 31) 318 319 320 /*Set Channel/Endpoint to the USB Register */ 321 #define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ 322 (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) 323 324 /*Get Channel/Endpoint from the USB Register */ 325 #define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) 326 327 328 /** 329 * @brief free buffer used from the application realizing it to the line 330 * toggles bit SW_BUF in the double buffered endpoint register 331 * @param USBx USB device. 332 * @param bEpChNum, bDir 333 * @retval None 334 */ 335 #define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ 336 do { \ 337 if ((bDir) == 0U) \ 338 { \ 339 /* OUT double buffered endpoint */ \ 340 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 341 } \ 342 else if ((bDir) == 1U) \ 343 { \ 344 /* IN double buffered endpoint */ \ 345 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 346 } \ 347 } while(0) 348 349 350 /** 351 * @brief Set the Setup bit in the corresponding channel, when a Setup 352 transaction is needed. 353 * @param USBx USB device. 354 * @param bEpChNum 355 * @retval None 356 */ 357 #define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ 358 do { \ 359 uint32_t _wRegVal; \ 360 \ 361 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ 362 \ 363 /*Set Setup bit*/ \ 364 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ 365 } while(0) 366 367 368 /** 369 * @brief Clears bit ERR_RX in the Channel register 370 * @param USBx USB peripheral instance register address. 371 * @param bChNum Endpoint Number. 372 * @retval None 373 */ 374 #define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ 375 do { \ 376 uint32_t _wRegVal; \ 377 \ 378 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 379 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ 380 (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ 381 \ 382 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 383 } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ 384 385 386 /** 387 * @brief Clears bit ERR_TX in the Channel register 388 * @param USBx USB peripheral instance register address. 389 * @param bChNum Endpoint Number. 390 * @retval None 391 */ 392 #define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ 393 do { \ 394 uint32_t _wRegVal; \ 395 \ 396 _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ 397 _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ 398 (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ 399 \ 400 USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ 401 } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ 402 403 404 /** 405 * @brief sets the status for tx transfer (bits STAT_TX[1:0]). 406 * @param USBx USB peripheral instance register address. 407 * @param bEpChNum Endpoint Number. 408 * @param wState new state 409 * @retval None 410 */ 411 #define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ 412 do { \ 413 uint32_t _wRegVal; \ 414 \ 415 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ 416 /* toggle first bit ? */ \ 417 if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ 418 { \ 419 _wRegVal ^= USB_CHEP_TX_DTOG1; \ 420 } \ 421 /* toggle second bit ? */ \ 422 if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ 423 { \ 424 _wRegVal ^= USB_CHEP_TX_DTOG2; \ 425 } \ 426 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ 427 } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ 428 429 430 /** 431 * @brief sets the status for rx transfer (bits STAT_TX[1:0]) 432 * @param USBx USB peripheral instance register address. 433 * @param bEpChNum Endpoint Number. 434 * @param wState new state 435 * @retval None 436 */ 437 #define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ 438 do { \ 439 uint32_t _wRegVal; \ 440 \ 441 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ 442 /* toggle first bit ? */ \ 443 if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ 444 { \ 445 _wRegVal ^= USB_CHEP_RX_DTOG1; \ 446 } \ 447 /* toggle second bit ? */ \ 448 if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ 449 { \ 450 _wRegVal ^= USB_CHEP_RX_DTOG2; \ 451 } \ 452 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 453 } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ 454 455 456 /** 457 * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] 458 * /STAT_RX[1:0]) 459 * @param USBx USB peripheral instance register address. 460 * @param bEpChNum Endpoint Number. 461 * @retval status 462 */ 463 #define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ 464 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) 465 466 #define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ 467 ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) 468 469 470 /** 471 * @brief set EP_KIND bit. 472 * @param USBx USB peripheral instance register address. 473 * @param bEpChNum Endpoint Number. 474 * @retval None 475 */ 476 #define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ 477 do { \ 478 uint32_t _wRegVal; \ 479 \ 480 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 481 \ 482 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ 483 } while(0) /* USB_DRD_SET_CHEP_KIND */ 484 485 486 /** 487 * @brief clear EP_KIND bit. 488 * @param USBx USB peripheral instance register address. 489 * @param bEpChNum Endpoint Number. 490 * @retval None 491 */ 492 #define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ 493 do { \ 494 uint32_t _wRegVal; \ 495 \ 496 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ 497 \ 498 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 499 } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ 500 501 502 /** 503 * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. 504 * @param USBx USB peripheral instance register address. 505 * @param bEpChNum Endpoint Number. 506 * @retval None 507 */ 508 #define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ 509 do { \ 510 uint32_t _wRegVal; \ 511 \ 512 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ 513 \ 514 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ 515 } while(0) /* USB_CLEAR_RX_CHEP_CTR */ 516 517 #define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ 518 do { \ 519 uint32_t _wRegVal; \ 520 \ 521 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ 522 \ 523 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ 524 } while(0) /* USB_CLEAR_TX_CHEP_CTR */ 525 526 527 /** 528 * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. 529 * @param USBx USB peripheral instance register address. 530 * @param bEpChNum Endpoint Number. 531 * @retval None 532 */ 533 #define USB_DRD_RX_DTOG(USBx, bEpChNum) \ 534 do { \ 535 uint32_t _wEPVal; \ 536 \ 537 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 538 \ 539 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ 540 } while(0) /* USB_DRD_RX_DTOG */ 541 542 #define USB_DRD_TX_DTOG(USBx, bEpChNum) \ 543 do { \ 544 uint32_t _wEPVal; \ 545 \ 546 _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ 547 \ 548 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ 549 } while(0) /* USB_TX_DTOG */ 550 551 552 /** 553 * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. 554 * @param USBx USB peripheral instance register address. 555 * @param bEpChNum Endpoint Number. 556 * @retval None 557 */ 558 #define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ 559 do { \ 560 uint32_t _wRegVal; \ 561 \ 562 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 563 \ 564 if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ 565 { \ 566 USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ 567 } \ 568 } while(0) /* USB_DRD_CLEAR_RX_DTOG */ 569 570 #define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ 571 do { \ 572 uint32_t _wRegVal; \ 573 \ 574 _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ 575 \ 576 if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ 577 { \ 578 USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ 579 } \ 580 } while(0) /* USB_DRD_CLEAR_TX_DTOG */ 581 582 583 /** 584 * @brief Sets address in an endpoint register. 585 * @param USBx USB peripheral instance register address. 586 * @param bEpChNum Endpoint Number. 587 * @param bAddr Address. 588 * @retval None 589 */ 590 #define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ 591 do { \ 592 uint32_t _wRegVal; \ 593 \ 594 /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ 595 _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ 596 \ 597 /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ 598 USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ 599 } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ 600 601 602 /* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ 603 /* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor 604 * The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) 605 * TXBD [Reserve |Countx| Address_Tx] 606 * RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ 607 608 /* Set TX Buffer Descriptor Address Field */ 609 #define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ 610 do { \ 611 /* Reset old Address */ \ 612 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ 613 \ 614 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 615 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 616 } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ 617 618 /* Set RX Buffer Descriptor Address Field */ 619 #define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ 620 do { \ 621 /* Reset old Address */ \ 622 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ 623 \ 624 /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ 625 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ 626 } while(0) /* USB_SET_CHEP_RX_ADDRESS */ 627 628 629 /** 630 * @brief Sets counter of rx buffer with no. of blocks. 631 * @param pdwReg Register pointer 632 * @param wCount Counter. 633 * @param wNBlocks no. of Blocks. 634 * @retval None 635 */ 636 #define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ 637 do { \ 638 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 639 (wNBlocks) =((uint32_t)(wCount) >> 5U); \ 640 if (((uint32_t)(wCount) % 32U) == 0U) \ 641 { \ 642 (wNBlocks)--; \ 643 } \ 644 \ 645 (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ 646 } while(0) /* USB_DRD_CALC_BLK32 */ 647 648 #define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ 649 do { \ 650 /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ 651 (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ 652 if (((wCount) & 0x1U) != 0U) \ 653 { \ 654 (wNBlocks)++; \ 655 } \ 656 (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ 657 } while(0) /* USB_DRD_CALC_BLK2 */ 658 659 #define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ 660 do { \ 661 uint32_t wNBlocks; \ 662 \ 663 (pdwReg) &= USB_PMA_RXBD_COUNTMSK; \ 664 \ 665 if ((wCount) > 62U) \ 666 { \ 667 USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ 668 } \ 669 else \ 670 { \ 671 if ((wCount) == 0U) \ 672 { \ 673 (pdwReg) &= (uint32_t)~USB_CNTRX_NBLK_MSK; \ 674 (pdwReg) |= USB_CNTRX_BLSIZE; \ 675 } \ 676 else \ 677 { \ 678 USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ 679 } \ 680 } \ 681 } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ 682 683 684 /** 685 * @brief sets counter for the tx/rx buffer. 686 * @param USBx USB peripheral instance register address. 687 * @param bEpChNum Endpoint Number. 688 * @param wCount Counter value. 689 * @retval None 690 */ 691 #define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ 692 do { \ 693 /* Reset old TX_Count value */ \ 694 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ 695 \ 696 /* Set the wCount in the dedicated EP_TXBuffer */ \ 697 (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 698 } while(0) 699 700 #define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ 701 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) 702 703 #define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ 704 USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) 705 706 /** 707 * @brief gets counter of the tx buffer. 708 * @param USBx USB peripheral instance register address. 709 * @param bEpChNum Endpoint Number. 710 * @retval Counter value 711 */ 712 #define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >>16U) 713 #define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >>16U) 714 715 #define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT 716 #define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT 717 718 #define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT 719 #define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT 720 /** 721 * @brief Sets buffer 0/1 address in a double buffer endpoint. 722 * @param USBx USB peripheral instance register address. 723 * @param bEpChNum Endpoint Number. 724 * @param wBuf0Addr buffer 0 address. 725 * @retval Counter value 726 */ 727 #define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ 728 USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) 729 730 #define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ 731 USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) 732 733 734 /** 735 * @brief Sets addresses in a double buffer endpoint. 736 * @param USBx USB peripheral instance register address. 737 * @param bEpChNum Endpoint Number. 738 * @param wBuf0Addr: buffer 0 address. 739 * @param wBuf1Addr = buffer 1 address. 740 * @retval None 741 */ 742 #define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ 743 do { \ 744 USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ 745 USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ 746 } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ 747 748 749 /** 750 * @brief Gets buffer 0/1 address of a double buffer endpoint. 751 * @param USBx USB peripheral instance register address. 752 * @param bEpChNum Endpoint Number. 753 * @param bDir endpoint dir EP_DBUF_OUT = OUT 754 * EP_DBUF_IN = IN 755 * @param wCount: Counter value 756 * @retval None 757 */ 758 #define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ 759 do { \ 760 if ((bDir) == 0U) \ 761 { \ 762 /* OUT endpoint */ \ 763 USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ 764 } \ 765 else \ 766 { \ 767 if ((bDir) == 1U) \ 768 { \ 769 /* IN endpoint */ \ 770 USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ 771 } \ 772 } \ 773 } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ 774 775 #define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ 776 do { \ 777 if ((bDir) == 0U) \ 778 { \ 779 /* OUT endpoint */ \ 780 USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ 781 } \ 782 else \ 783 { \ 784 if ((bDir) == 1U) \ 785 { \ 786 /* IN endpoint */ \ 787 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ 788 (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ 789 } \ 790 } \ 791 } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ 792 793 #define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ 794 do { \ 795 USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 796 USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ 797 } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ 798 799 /** 800 * @brief Gets buffer 0/1 rx/tx counter for double buffering. 801 * @param USBx USB peripheral instance register address. 802 * @param bEpChNum Endpoint Number. 803 * @retval None 804 */ 805 #define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) 806 #define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) 807 /** 808 * @} 809 */ 810 811 /* Exported macro ------------------------------------------------------------*/ 812 /** 813 * @} 814 */ 815 816 /* Exported functions --------------------------------------------------------*/ 817 /** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions 818 * @{ 819 */ 820 821 822 HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 823 HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 824 HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); 825 HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); 826 HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); 827 828 #if defined (HAL_PCD_MODULE_ENABLED) 829 HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 830 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 831 HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 832 HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 833 HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 834 HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); 835 #endif /* defined (HAL_PCD_MODULE_ENABLED) */ 836 837 HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); 838 HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); 839 HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); 840 HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); 841 uint32_t USB_ReadInterrupts(USB_DRD_TypeDef *USBx); 842 843 HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); 844 HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); 845 HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 846 HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); 847 HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); 848 849 uint32_t USB_GetHostSpeed(USB_DRD_TypeDef *USBx); 850 uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef *USBx); 851 HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); 852 HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); 853 HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, 854 uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); 855 856 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 857 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); 858 859 void USB_WritePMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, 860 uint16_t wPMABufAddr, uint16_t wNBytes); 861 862 void USB_ReadPMA(USB_DRD_TypeDef *USBx, uint8_t *pbUsrBuf, 863 uint16_t wPMABufAddr, uint16_t wNBytes); 864 865 /** 866 * @} 867 */ 868 869 /** 870 * @} 871 */ 872 873 /** 874 * @} 875 */ 876 877 /** 878 * @} 879 */ 880 #endif /* defined (USB_DRD_FS) */ 881 882 #ifdef __cplusplus 883 } 884 #endif /* __cplusplus */ 885 886 887 #endif /* STM32G0xx_LL_USB_H */ 888
