1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2017 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef __STM32F7xx_LL_UTILS_H
33 #define __STM32F7xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f7xx.h"
41
42 /** @addtogroup STM32F7xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Flash size data register base address
68 */
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
70
71 /**
72 * @brief Package data register base address
73 */
74 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
75
76 /**
77 * @}
78 */
79
80 /* Private macros ------------------------------------------------------------*/
81 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
82 * @{
83 */
84 /**
85 * @}
86 */
87 /* Exported types ------------------------------------------------------------*/
88 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
89 * @{
90 */
91 /**
92 * @brief UTILS PLL structure definition
93 */
94 typedef struct
95 {
96 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
97 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
98
99 This feature can be modified afterwards using unitary function
100 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
101
102 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
103 This parameter must be a number between Min_Data = 50 and Max_Data = 432
104
105 This feature can be modified afterwards using unitary function
106 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
107
108 uint32_t PLLP; /*!< Division for the main system clock.
109 This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
110
111 This feature can be modified afterwards using unitary function
112 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
113 } LL_UTILS_PLLInitTypeDef;
114
115 /**
116 * @brief UTILS System, AHB and APB buses clock configuration structure definition
117 */
118 typedef struct
119 {
120 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
121 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
122
123 This feature can be modified afterwards using unitary function
124 @ref LL_RCC_SetAHBPrescaler(). */
125
126 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
127 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
128
129 This feature can be modified afterwards using unitary function
130 @ref LL_RCC_SetAPB1Prescaler(). */
131
132 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
133 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
134
135 This feature can be modified afterwards using unitary function
136 @ref LL_RCC_SetAPB2Prescaler(). */
137
138 } LL_UTILS_ClkInitTypeDef;
139
140 /**
141 * @}
142 */
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
146 * @{
147 */
148
149 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
150 * @{
151 */
152 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
153 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
154 /**
155 * @}
156 */
157
158 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
159 * @{
160 */
161 #define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */
162 #define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */
163 #define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */
164 #define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */
165 #define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */
166 #define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */
167 #define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */
168 /**
169 * @}
170 */
171
172 /**
173 * @}
174 */
175
176 /* Exported macro ------------------------------------------------------------*/
177
178 /* Exported functions --------------------------------------------------------*/
179 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
180 * @{
181 */
182
183 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
184 * @{
185 */
186
187 /**
188 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
189 * @retval UID[31:0]
190 */
LL_GetUID_Word0(void)191 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
192 {
193 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
194 }
195
196 /**
197 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
198 * @retval UID[63:32]
199 */
LL_GetUID_Word1(void)200 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
201 {
202 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
203 }
204
205 /**
206 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
207 * @retval UID[95:64]
208 */
LL_GetUID_Word2(void)209 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
210 {
211 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
212 }
213
214 /**
215 * @brief Get Flash memory size
216 * @note This bitfield indicates the size of the device Flash memory expressed in
217 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
218 * @retval FLASH_SIZE[15:0]: Flash memory size
219 */
LL_GetFlashSize(void)220 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
221 {
222 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
223 }
224
225 /**
226 * @brief Get Package type
227 * @retval Returned value can be one of the following values:
228 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
229 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*)
230 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*)
231 * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*)
232 *
233 * (*) value not defined in all devices.
234 */
LL_GetPackageType(void)235 __STATIC_INLINE uint32_t LL_GetPackageType(void)
236 {
237 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
238 }
239
240 /**
241 * @}
242 */
243
244 /** @defgroup UTILS_LL_EF_DELAY DELAY
245 * @{
246 */
247
248 /**
249 * @brief This function configures the Cortex-M SysTick source of the time base.
250 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
251 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
252 * configuration by calling this function, for a delay use rather osDelay RTOS service.
253 * @param Ticks Number of ticks
254 * @retval None
255 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)256 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
257 {
258 /* Configure the SysTick to have interrupt in 1ms time base */
259 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
260 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
261 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
262 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
263 }
264
265 void LL_Init1msTick(uint32_t HCLKFrequency);
266 void LL_mDelay(uint32_t Delay);
267
268 /**
269 * @}
270 */
271
272 /** @defgroup UTILS_EF_SYSTEM SYSTEM
273 * @{
274 */
275
276 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
277 ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
278 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
279 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
280 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
281 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
282
283 /**
284 * @}
285 */
286
287 /**
288 * @}
289 */
290
291 /**
292 * @}
293 */
294
295 /**
296 * @}
297 */
298
299 #ifdef __cplusplus
300 }
301 #endif
302
303 #endif /* __STM32F7xx_LL_UTILS_H */
304
305
