1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef __STM32F4xx_LL_PWR_H
20 #define __STM32F4xx_LL_PWR_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32f4xx.h"
28
29 /** @addtogroup STM32F4xx_LL_Driver
30 * @{
31 */
32
33 #if defined(PWR)
34
35 /** @defgroup PWR_LL PWR
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /* Exported types ------------------------------------------------------------*/
44 /* Exported constants --------------------------------------------------------*/
45 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
46 * @{
47 */
48
49 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
50 * @brief Flags defines which can be used with LL_PWR_WriteReg function
51 * @{
52 */
53 #define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
54 #define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
55 /**
56 * @}
57 */
58
59 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
60 * @brief Flags defines which can be used with LL_PWR_ReadReg function
61 * @{
62 */
63 #define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
64 #define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
65 #define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
66 #define LL_PWR_CSR_VOS PWR_CSR_VOSRDY /*!< Voltage scaling select flag */
67 #if defined(PWR_CSR_EWUP)
68 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin */
69 #elif defined(PWR_CSR_EWUP1)
70 #define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
71 #endif /* PWR_CSR_EWUP */
72 #if defined(PWR_CSR_EWUP2)
73 #define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
74 #endif /* PWR_CSR_EWUP2 */
75 #if defined(PWR_CSR_EWUP3)
76 #define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
77 #endif /* PWR_CSR_EWUP3 */
78 /**
79 * @}
80 */
81
82 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
83 * @{
84 */
85 #if defined(PWR_CR_VOS_0)
86 #define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
87 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
88 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
89 #else
90 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
91 #define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
92 #endif /* PWR_CR_VOS_0 */
93 /**
94 * @}
95 */
96
97 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
98 * @{
99 */
100 #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
101 #define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
102 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
103 #define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
104 #define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
105 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
106 #if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
107 #define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
108 #define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS) /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
109 #endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
110 #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
111 /**
112 * @}
113 */
114
115 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
116 * @{
117 */
118 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
119 #define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
120 /**
121 * @}
122 */
123
124 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
125 * @{
126 */
127 #define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
128 #define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
129 #define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
130 #define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
131 #define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
132 #define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
133 #define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
134 #define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
135 /**
136 * @}
137 */
138 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
139 * @{
140 */
141 #if defined(PWR_CSR_EWUP)
142 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin : PA0 */
143 #endif /* PWR_CSR_EWUP */
144 #if defined(PWR_CSR_EWUP1)
145 #define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
146 #endif /* PWR_CSR_EWUP1 */
147 #if defined(PWR_CSR_EWUP2)
148 #define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC0 or PC13 according to device */
149 #endif /* PWR_CSR_EWUP2 */
150 #if defined(PWR_CSR_EWUP3)
151 #define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PC1 */
152 #endif /* PWR_CSR_EWUP3 */
153 /**
154 * @}
155 */
156
157 /**
158 * @}
159 */
160
161
162 /* Exported macro ------------------------------------------------------------*/
163 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
164 * @{
165 */
166
167 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
168 * @{
169 */
170
171 /**
172 * @brief Write a value in PWR register
173 * @param __REG__ Register to be written
174 * @param __VALUE__ Value to be written in the register
175 * @retval None
176 */
177 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
178
179 /**
180 * @brief Read a value in PWR register
181 * @param __REG__ Register to be read
182 * @retval Register value
183 */
184 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
185 /**
186 * @}
187 */
188
189 /**
190 * @}
191 */
192
193 /* Exported functions --------------------------------------------------------*/
194 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
195 * @{
196 */
197
198 /** @defgroup PWR_LL_EF_Configuration Configuration
199 * @{
200 */
201 #if defined(PWR_CR_FISSR)
202 /**
203 * @brief Enable FLASH interface STOP while system Run is ON
204 * @rmtoll CR FISSR LL_PWR_EnableFLASHInterfaceSTOP
205 * @note This mode is enabled only with STOP low power mode.
206 * @retval None
207 */
LL_PWR_EnableFLASHInterfaceSTOP(void)208 __STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
209 {
210 SET_BIT(PWR->CR, PWR_CR_FISSR);
211 }
212
213 /**
214 * @brief Disable FLASH Interface STOP while system Run is ON
215 * @rmtoll CR FISSR LL_PWR_DisableFLASHInterfaceSTOP
216 * @retval None
217 */
LL_PWR_DisableFLASHInterfaceSTOP(void)218 __STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
219 {
220 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
221 }
222
223 /**
224 * @brief Check if FLASH Interface STOP while system Run feature is enabled
225 * @rmtoll CR FISSR LL_PWR_IsEnabledFLASHInterfaceSTOP
226 * @retval State of bit (1 or 0).
227 */
LL_PWR_IsEnabledFLASHInterfaceSTOP(void)228 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
229 {
230 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
231 }
232 #endif /* PWR_CR_FISSR */
233
234 #if defined(PWR_CR_FMSSR)
235 /**
236 * @brief Enable FLASH Memory STOP while system Run is ON
237 * @rmtoll CR FMSSR LL_PWR_EnableFLASHMemorySTOP
238 * @note This mode is enabled only with STOP low power mode.
239 * @retval None
240 */
LL_PWR_EnableFLASHMemorySTOP(void)241 __STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
242 {
243 SET_BIT(PWR->CR, PWR_CR_FMSSR);
244 }
245
246 /**
247 * @brief Disable FLASH Memory STOP while system Run is ON
248 * @rmtoll CR FMSSR LL_PWR_DisableFLASHMemorySTOP
249 * @retval None
250 */
LL_PWR_DisableFLASHMemorySTOP(void)251 __STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
252 {
253 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
254 }
255
256 /**
257 * @brief Check if FLASH Memory STOP while system Run feature is enabled
258 * @rmtoll CR FMSSR LL_PWR_IsEnabledFLASHMemorySTOP
259 * @retval State of bit (1 or 0).
260 */
LL_PWR_IsEnabledFLASHMemorySTOP(void)261 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
262 {
263 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
264 }
265 #endif /* PWR_CR_FMSSR */
266 #if defined(PWR_CR_UDEN)
267 /**
268 * @brief Enable Under Drive Mode
269 * @rmtoll CR UDEN LL_PWR_EnableUnderDriveMode
270 * @note This mode is enabled only with STOP low power mode.
271 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
272 * mode is only available when the main Regulator or the low power Regulator
273 * is in low voltage mode.
274 * @note If the Under-drive mode was enabled, it is automatically disabled after
275 * exiting Stop mode.
276 * When the voltage Regulator operates in Under-drive mode, an additional
277 * startup delay is induced when waking up from Stop mode.
278 * @retval None
279 */
LL_PWR_EnableUnderDriveMode(void)280 __STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
281 {
282 SET_BIT(PWR->CR, PWR_CR_UDEN);
283 }
284
285 /**
286 * @brief Disable Under Drive Mode
287 * @rmtoll CR UDEN LL_PWR_DisableUnderDriveMode
288 * @retval None
289 */
LL_PWR_DisableUnderDriveMode(void)290 __STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
291 {
292 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
293 }
294
295 /**
296 * @brief Check if Under Drive Mode is enabled
297 * @rmtoll CR UDEN LL_PWR_IsEnabledUnderDriveMode
298 * @retval State of bit (1 or 0).
299 */
LL_PWR_IsEnabledUnderDriveMode(void)300 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
301 {
302 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
303 }
304 #endif /* PWR_CR_UDEN */
305
306 #if defined(PWR_CR_ODSWEN)
307 /**
308 * @brief Enable Over drive switching
309 * @rmtoll CR ODSWEN LL_PWR_EnableOverDriveSwitching
310 * @retval None
311 */
LL_PWR_EnableOverDriveSwitching(void)312 __STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
313 {
314 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
315 }
316
317 /**
318 * @brief Disable Over drive switching
319 * @rmtoll CR ODSWEN LL_PWR_DisableOverDriveSwitching
320 * @retval None
321 */
LL_PWR_DisableOverDriveSwitching(void)322 __STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
323 {
324 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
325 }
326
327 /**
328 * @brief Check if Over drive switching is enabled
329 * @rmtoll CR ODSWEN LL_PWR_IsEnabledOverDriveSwitching
330 * @retval State of bit (1 or 0).
331 */
LL_PWR_IsEnabledOverDriveSwitching(void)332 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
333 {
334 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
335 }
336 #endif /* PWR_CR_ODSWEN */
337 #if defined(PWR_CR_ODEN)
338 /**
339 * @brief Enable Over drive Mode
340 * @rmtoll CR ODEN LL_PWR_EnableOverDriveMode
341 * @retval None
342 */
LL_PWR_EnableOverDriveMode(void)343 __STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
344 {
345 SET_BIT(PWR->CR, PWR_CR_ODEN);
346 }
347
348 /**
349 * @brief Disable Over drive Mode
350 * @rmtoll CR ODEN LL_PWR_DisableOverDriveMode
351 * @retval None
352 */
LL_PWR_DisableOverDriveMode(void)353 __STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
354 {
355 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
356 }
357
358 /**
359 * @brief Check if Over drive switching is enabled
360 * @rmtoll CR ODEN LL_PWR_IsEnabledOverDriveMode
361 * @retval State of bit (1 or 0).
362 */
LL_PWR_IsEnabledOverDriveMode(void)363 __STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
364 {
365 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
366 }
367 #endif /* PWR_CR_ODEN */
368 #if defined(PWR_CR_MRUDS)
369 /**
370 * @brief Enable Main Regulator in deepsleep under-drive Mode
371 * @rmtoll CR MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode
372 * @retval None
373 */
LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)374 __STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
375 {
376 SET_BIT(PWR->CR, PWR_CR_MRUDS);
377 }
378
379 /**
380 * @brief Disable Main Regulator in deepsleep under-drive Mode
381 * @rmtoll CR MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode
382 * @retval None
383 */
LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)384 __STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
385 {
386 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
387 }
388
389 /**
390 * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled
391 * @rmtoll CR MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
392 * @retval State of bit (1 or 0).
393 */
LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)394 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
395 {
396 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
397 }
398 #endif /* PWR_CR_MRUDS */
399
400 #if defined(PWR_CR_LPUDS)
401 /**
402 * @brief Enable Low Power Regulator in deepsleep under-drive Mode
403 * @rmtoll CR LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
404 * @retval None
405 */
LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)406 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
407 {
408 SET_BIT(PWR->CR, PWR_CR_LPUDS);
409 }
410
411 /**
412 * @brief Disable Low Power Regulator in deepsleep under-drive Mode
413 * @rmtoll CR LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
414 * @retval None
415 */
LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)416 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
417 {
418 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
419 }
420
421 /**
422 * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled
423 * @rmtoll CR LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
424 * @retval State of bit (1 or 0).
425 */
LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)426 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
427 {
428 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
429 }
430 #endif /* PWR_CR_LPUDS */
431
432 #if defined(PWR_CR_MRLVDS)
433 /**
434 * @brief Enable Main Regulator low voltage Mode
435 * @rmtoll CR MRLVDS LL_PWR_EnableMainRegulatorLowVoltageMode
436 * @retval None
437 */
LL_PWR_EnableMainRegulatorLowVoltageMode(void)438 __STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
439 {
440 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
441 }
442
443 /**
444 * @brief Disable Main Regulator low voltage Mode
445 * @rmtoll CR MRLVDS LL_PWR_DisableMainRegulatorLowVoltageMode
446 * @retval None
447 */
LL_PWR_DisableMainRegulatorLowVoltageMode(void)448 __STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
449 {
450 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
451 }
452
453 /**
454 * @brief Check if Main Regulator low voltage Mode is enabled
455 * @rmtoll CR MRLVDS LL_PWR_IsEnabledMainRegulatorLowVoltageMode
456 * @retval State of bit (1 or 0).
457 */
LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)458 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
459 {
460 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
461 }
462 #endif /* PWR_CR_MRLVDS */
463
464 #if defined(PWR_CR_LPLVDS)
465 /**
466 * @brief Enable Low Power Regulator low voltage Mode
467 * @rmtoll CR LPLVDS LL_PWR_EnableLowPowerRegulatorLowVoltageMode
468 * @retval None
469 */
LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)470 __STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
471 {
472 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
473 }
474
475 /**
476 * @brief Disable Low Power Regulator low voltage Mode
477 * @rmtoll CR LPLVDS LL_PWR_DisableLowPowerRegulatorLowVoltageMode
478 * @retval None
479 */
LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)480 __STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
481 {
482 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
483 }
484
485 /**
486 * @brief Check if Low Power Regulator low voltage Mode is enabled
487 * @rmtoll CR LPLVDS LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
488 * @retval State of bit (1 or 0).
489 */
LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)490 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
491 {
492 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
493 }
494 #endif /* PWR_CR_LPLVDS */
495 /**
496 * @brief Set the main internal Regulator output voltage
497 * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling
498 * @param VoltageScaling This parameter can be one of the following values:
499 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
500 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
501 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
502 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
503 * @retval None
504 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)505 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
506 {
507 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
508 }
509
510 /**
511 * @brief Get the main internal Regulator output voltage
512 * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling
513 * @retval Returned value can be one of the following values:
514 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
515 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
516 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
517 * (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
518 */
LL_PWR_GetRegulVoltageScaling(void)519 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
520 {
521 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
522 }
523 /**
524 * @brief Enable the Flash Power Down in Stop Mode
525 * @rmtoll CR FPDS LL_PWR_EnableFlashPowerDown
526 * @retval None
527 */
LL_PWR_EnableFlashPowerDown(void)528 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
529 {
530 SET_BIT(PWR->CR, PWR_CR_FPDS);
531 }
532
533 /**
534 * @brief Disable the Flash Power Down in Stop Mode
535 * @rmtoll CR FPDS LL_PWR_DisableFlashPowerDown
536 * @retval None
537 */
LL_PWR_DisableFlashPowerDown(void)538 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
539 {
540 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
541 }
542
543 /**
544 * @brief Check if the Flash Power Down in Stop Mode is enabled
545 * @rmtoll CR FPDS LL_PWR_IsEnabledFlashPowerDown
546 * @retval State of bit (1 or 0).
547 */
LL_PWR_IsEnabledFlashPowerDown(void)548 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
549 {
550 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
551 }
552
553 /**
554 * @brief Enable access to the backup domain
555 * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
556 * @retval None
557 */
LL_PWR_EnableBkUpAccess(void)558 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
559 {
560 SET_BIT(PWR->CR, PWR_CR_DBP);
561 }
562
563 /**
564 * @brief Disable access to the backup domain
565 * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
566 * @retval None
567 */
LL_PWR_DisableBkUpAccess(void)568 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
569 {
570 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
571 }
572
573 /**
574 * @brief Check if the backup domain is enabled
575 * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
576 * @retval State of bit (1 or 0).
577 */
LL_PWR_IsEnabledBkUpAccess(void)578 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
579 {
580 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
581 }
582 /**
583 * @brief Enable the backup Regulator
584 * @rmtoll CSR BRE LL_PWR_EnableBkUpRegulator
585 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
586 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
587 * @retval None
588 */
LL_PWR_EnableBkUpRegulator(void)589 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
590 {
591 SET_BIT(PWR->CSR, PWR_CSR_BRE);
592 }
593
594 /**
595 * @brief Disable the backup Regulator
596 * @rmtoll CSR BRE LL_PWR_DisableBkUpRegulator
597 * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
598 * The LL_PWR_EnableBkUpAccess() must be called before using this API.
599 * @retval None
600 */
LL_PWR_DisableBkUpRegulator(void)601 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
602 {
603 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
604 }
605
606 /**
607 * @brief Check if the backup Regulator is enabled
608 * @rmtoll CSR BRE LL_PWR_IsEnabledBkUpRegulator
609 * @retval State of bit (1 or 0).
610 */
LL_PWR_IsEnabledBkUpRegulator(void)611 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
612 {
613 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
614 }
615
616 /**
617 * @brief Set voltage Regulator mode during deep sleep mode
618 * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
619 * @param RegulMode This parameter can be one of the following values:
620 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
621 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
622 * @retval None
623 */
LL_PWR_SetRegulModeDS(uint32_t RegulMode)624 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
625 {
626 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
627 }
628
629 /**
630 * @brief Get voltage Regulator mode during deep sleep mode
631 * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
632 * @retval Returned value can be one of the following values:
633 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
634 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
635 */
LL_PWR_GetRegulModeDS(void)636 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
637 {
638 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
639 }
640
641 /**
642 * @brief Set Power Down mode when CPU enters deepsleep
643 * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
644 * @rmtoll CR MRUDS LL_PWR_SetPowerMode\n
645 * @rmtoll CR LPUDS LL_PWR_SetPowerMode\n
646 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
647 * @rmtoll CR MRLVDS LL_PWR_SetPowerMode\n
648 * @rmtoll CR LPlVDS LL_PWR_SetPowerMode\n
649 * @rmtoll CR FPDS LL_PWR_SetPowerMode\n
650 * @rmtoll CR LPDS LL_PWR_SetPowerMode
651 * @param PDMode This parameter can be one of the following values:
652 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
653 * @arg @ref LL_PWR_MODE_STOP_LPREGU
654 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
655 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
656 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
657 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
658 *
659 * (*) not available on all devices
660 * @arg @ref LL_PWR_MODE_STANDBY
661 * @retval None
662 */
LL_PWR_SetPowerMode(uint32_t PDMode)663 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
664 {
665 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
666 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
667 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
668 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
669 #else
670 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
671 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
672 }
673
674 /**
675 * @brief Get Power Down mode when CPU enters deepsleep
676 * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
677 * @rmtoll CR MRUDS LL_PWR_GetPowerMode\n
678 * @rmtoll CR LPUDS LL_PWR_GetPowerMode\n
679 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
680 * @rmtoll CR MRLVDS LL_PWR_GetPowerMode\n
681 * @rmtoll CR LPLVDS LL_PWR_GetPowerMode\n
682 * @rmtoll CR FPDS LL_PWR_GetPowerMode\n
683 * @rmtoll CR LPDS LL_PWR_GetPowerMode
684 * @retval Returned value can be one of the following values:
685 * @arg @ref LL_PWR_MODE_STOP_MAINREGU
686 * @arg @ref LL_PWR_MODE_STOP_LPREGU
687 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
688 * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
689 * @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
690 * @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
691 *
692 * (*) not available on all devices
693 * @arg @ref LL_PWR_MODE_STANDBY
694 */
LL_PWR_GetPowerMode(void)695 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
696 {
697 #if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
698 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
699 #elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
700 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
701 #else
702 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
703 #endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
704 }
705
706 /**
707 * @brief Configure the voltage threshold detected by the Power Voltage Detector
708 * @rmtoll CR PLS LL_PWR_SetPVDLevel
709 * @param PVDLevel This parameter can be one of the following values:
710 * @arg @ref LL_PWR_PVDLEVEL_0
711 * @arg @ref LL_PWR_PVDLEVEL_1
712 * @arg @ref LL_PWR_PVDLEVEL_2
713 * @arg @ref LL_PWR_PVDLEVEL_3
714 * @arg @ref LL_PWR_PVDLEVEL_4
715 * @arg @ref LL_PWR_PVDLEVEL_5
716 * @arg @ref LL_PWR_PVDLEVEL_6
717 * @arg @ref LL_PWR_PVDLEVEL_7
718 * @retval None
719 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)720 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
721 {
722 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
723 }
724
725 /**
726 * @brief Get the voltage threshold detection
727 * @rmtoll CR PLS LL_PWR_GetPVDLevel
728 * @retval Returned value can be one of the following values:
729 * @arg @ref LL_PWR_PVDLEVEL_0
730 * @arg @ref LL_PWR_PVDLEVEL_1
731 * @arg @ref LL_PWR_PVDLEVEL_2
732 * @arg @ref LL_PWR_PVDLEVEL_3
733 * @arg @ref LL_PWR_PVDLEVEL_4
734 * @arg @ref LL_PWR_PVDLEVEL_5
735 * @arg @ref LL_PWR_PVDLEVEL_6
736 * @arg @ref LL_PWR_PVDLEVEL_7
737 */
LL_PWR_GetPVDLevel(void)738 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
739 {
740 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
741 }
742
743 /**
744 * @brief Enable Power Voltage Detector
745 * @rmtoll CR PVDE LL_PWR_EnablePVD
746 * @retval None
747 */
LL_PWR_EnablePVD(void)748 __STATIC_INLINE void LL_PWR_EnablePVD(void)
749 {
750 SET_BIT(PWR->CR, PWR_CR_PVDE);
751 }
752
753 /**
754 * @brief Disable Power Voltage Detector
755 * @rmtoll CR PVDE LL_PWR_DisablePVD
756 * @retval None
757 */
LL_PWR_DisablePVD(void)758 __STATIC_INLINE void LL_PWR_DisablePVD(void)
759 {
760 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
761 }
762
763 /**
764 * @brief Check if Power Voltage Detector is enabled
765 * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
766 * @retval State of bit (1 or 0).
767 */
LL_PWR_IsEnabledPVD(void)768 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
769 {
770 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
771 }
772
773 /**
774 * @brief Enable the WakeUp PINx functionality
775 * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin\n
776 * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
777 * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
778 * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
779 * @param WakeUpPin This parameter can be one of the following values:
780 * @arg @ref LL_PWR_WAKEUP_PIN1
781 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
782 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
783 *
784 * (*) not available on all devices
785 * @retval None
786 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)787 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
788 {
789 SET_BIT(PWR->CSR, WakeUpPin);
790 }
791
792 /**
793 * @brief Disable the WakeUp PINx functionality
794 * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin\n
795 * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
796 * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
797 * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
798 * @param WakeUpPin This parameter can be one of the following values:
799 * @arg @ref LL_PWR_WAKEUP_PIN1
800 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
801 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
802 *
803 * (*) not available on all devices
804 * @retval None
805 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)806 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
807 {
808 CLEAR_BIT(PWR->CSR, WakeUpPin);
809 }
810
811 /**
812 * @brief Check if the WakeUp PINx functionality is enabled
813 * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin\n
814 * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
815 * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
816 * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
817 * @param WakeUpPin This parameter can be one of the following values:
818 * @arg @ref LL_PWR_WAKEUP_PIN1
819 * @arg @ref LL_PWR_WAKEUP_PIN2 (*)
820 * @arg @ref LL_PWR_WAKEUP_PIN3 (*)
821 *
822 * (*) not available on all devices
823 * @retval State of bit (1 or 0).
824 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)825 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
826 {
827 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
828 }
829
830
831 /**
832 * @}
833 */
834
835 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
836 * @{
837 */
838
839 /**
840 * @brief Get Wake-up Flag
841 * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
842 * @retval State of bit (1 or 0).
843 */
LL_PWR_IsActiveFlag_WU(void)844 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
845 {
846 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
847 }
848
849 /**
850 * @brief Get Standby Flag
851 * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
852 * @retval State of bit (1 or 0).
853 */
LL_PWR_IsActiveFlag_SB(void)854 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
855 {
856 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
857 }
858
859 /**
860 * @brief Get Backup Regulator ready Flag
861 * @rmtoll CSR BRR LL_PWR_IsActiveFlag_BRR
862 * @retval State of bit (1 or 0).
863 */
LL_PWR_IsActiveFlag_BRR(void)864 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
865 {
866 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
867 }
868 /**
869 * @brief Indicate whether VDD voltage is below the selected PVD threshold
870 * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
871 * @retval State of bit (1 or 0).
872 */
LL_PWR_IsActiveFlag_PVDO(void)873 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
874 {
875 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
876 }
877
878 /**
879 * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
880 * @rmtoll CSR VOS LL_PWR_IsActiveFlag_VOS
881 * @retval State of bit (1 or 0).
882 */
LL_PWR_IsActiveFlag_VOS(void)883 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
884 {
885 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
886 }
887 #if defined(PWR_CR_ODEN)
888 /**
889 * @brief Indicate whether the Over-Drive mode is ready or not
890 * @rmtoll CSR ODRDY LL_PWR_IsActiveFlag_OD
891 * @retval State of bit (1 or 0).
892 */
LL_PWR_IsActiveFlag_OD(void)893 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
894 {
895 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
896 }
897 #endif /* PWR_CR_ODEN */
898
899 #if defined(PWR_CR_ODSWEN)
900 /**
901 * @brief Indicate whether the Over-Drive mode switching is ready or not
902 * @rmtoll CSR ODSWRDY LL_PWR_IsActiveFlag_ODSW
903 * @retval State of bit (1 or 0).
904 */
LL_PWR_IsActiveFlag_ODSW(void)905 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
906 {
907 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
908 }
909 #endif /* PWR_CR_ODSWEN */
910
911 #if defined(PWR_CR_UDEN)
912 /**
913 * @brief Indicate whether the Under-Drive mode is ready or not
914 * @rmtoll CSR UDRDY LL_PWR_IsActiveFlag_UD
915 * @retval State of bit (1 or 0).
916 */
LL_PWR_IsActiveFlag_UD(void)917 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
918 {
919 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
920 }
921 #endif /* PWR_CR_UDEN */
922 /**
923 * @brief Clear Standby Flag
924 * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
925 * @retval None
926 */
LL_PWR_ClearFlag_SB(void)927 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
928 {
929 SET_BIT(PWR->CR, PWR_CR_CSBF);
930 }
931
932 /**
933 * @brief Clear Wake-up Flags
934 * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
935 * @retval None
936 */
LL_PWR_ClearFlag_WU(void)937 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
938 {
939 SET_BIT(PWR->CR, PWR_CR_CWUF);
940 }
941 #if defined(PWR_CSR_UDRDY)
942 /**
943 * @brief Clear Under-Drive ready Flag
944 * @rmtoll CSR UDRDY LL_PWR_ClearFlag_UD
945 * @retval None
946 */
LL_PWR_ClearFlag_UD(void)947 __STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
948 {
949 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
950 }
951 #endif /* PWR_CSR_UDRDY */
952
953 /**
954 * @}
955 */
956
957 #if defined(USE_FULL_LL_DRIVER)
958 /** @defgroup PWR_LL_EF_Init De-initialization function
959 * @{
960 */
961 ErrorStatus LL_PWR_DeInit(void);
962 /**
963 * @}
964 */
965 #endif /* USE_FULL_LL_DRIVER */
966
967 /**
968 * @}
969 */
970
971 /**
972 * @}
973 */
974
975 #endif /* defined(PWR) */
976
977 /**
978 * @}
979 */
980
981 #ifdef __cplusplus
982 }
983 #endif
984
985 #endif /* __STM32F4xx_LL_PWR_H */
986
