1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F4xx_HAL_DFSDM_H 21 #define __STM32F4xx_HAL_DFSDM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DFSDM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief HAL DFSDM Channel states definition 46 */ 47 typedef enum 48 { 49 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 50 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 51 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 52 }HAL_DFSDM_Channel_StateTypeDef; 53 54 /** 55 * @brief DFSDM channel output clock structure definition 56 */ 57 typedef struct 58 { 59 FunctionalState Activation; /*!< Output clock enable/disable */ 60 uint32_t Selection; /*!< Output clock is system clock or audio clock. 61 This parameter can be a value of @ref DFSDM_Channel_OutputClock */ 62 uint32_t Divider; /*!< Output clock divider. 63 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 64 }DFSDM_Channel_OutputClockTypeDef; 65 66 /** 67 * @brief DFSDM channel input structure definition 68 */ 69 typedef struct 70 { 71 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. 72 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 73 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 74 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 75 uint32_t Pins; /*!< Input pins are taken from same or following channel. 76 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 77 }DFSDM_Channel_InputTypeDef; 78 79 /** 80 * @brief DFSDM channel serial interface structure definition 81 */ 82 typedef struct 83 { 84 uint32_t Type; /*!< SPI or Manchester modes. 85 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 86 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 87 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 88 }DFSDM_Channel_SerialInterfaceTypeDef; 89 90 /** 91 * @brief DFSDM channel analog watchdog structure definition 92 */ 93 typedef struct 94 { 95 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 96 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 97 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 98 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 99 }DFSDM_Channel_AwdTypeDef; 100 101 /** 102 * @brief DFSDM channel init structure definition 103 */ 104 typedef struct 105 { 106 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 107 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 108 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 109 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 110 int32_t Offset; /*!< DFSDM channel offset. 111 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 112 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 113 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 114 }DFSDM_Channel_InitTypeDef; 115 116 /** 117 * @brief DFSDM channel handle structure definition 118 */ 119 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 120 typedef struct __DFSDM_Channel_HandleTypeDef 121 #else 122 typedef struct 123 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 124 { 125 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 126 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 127 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 128 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 129 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 130 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 131 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 132 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 133 #endif 134 }DFSDM_Channel_HandleTypeDef; 135 136 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 137 /** 138 * @brief DFSDM channel callback ID enumeration definition 139 */ 140 typedef enum 141 { 142 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 143 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 144 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 145 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 146 }HAL_DFSDM_Channel_CallbackIDTypeDef; 147 148 /** 149 * @brief DFSDM channel callback pointer definition 150 */ 151 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 152 #endif 153 /** 154 * @brief HAL DFSDM Filter states definition 155 */ 156 typedef enum 157 { 158 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 159 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 160 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 161 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 162 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 163 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 164 }HAL_DFSDM_Filter_StateTypeDef; 165 166 /** 167 * @brief DFSDM filter regular conversion parameters structure definition 168 */ 169 typedef struct 170 { 171 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 172 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 173 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 174 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 175 }DFSDM_Filter_RegularParamTypeDef; 176 177 /** 178 * @brief DFSDM filter injected conversion parameters structure definition 179 */ 180 typedef struct 181 { 182 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 183 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 184 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 185 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 186 uint32_t ExtTrigger; /*!< External trigger. 187 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 188 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 189 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 190 }DFSDM_Filter_InjectedParamTypeDef; 191 192 /** 193 * @brief DFSDM filter parameters structure definition 194 */ 195 typedef struct 196 { 197 uint32_t SincOrder; /*!< Sinc filter order. 198 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 199 uint32_t Oversampling; /*!< Filter oversampling ratio. 200 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 201 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 202 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 203 }DFSDM_Filter_FilterParamTypeDef; 204 205 /** 206 * @brief DFSDM filter init structure definition 207 */ 208 typedef struct 209 { 210 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 211 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 212 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 213 }DFSDM_Filter_InitTypeDef; 214 215 /** 216 * @brief DFSDM filter handle structure definition 217 */ 218 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 219 typedef struct __DFSDM_Filter_HandleTypeDef 220 #else 221 typedef struct 222 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 223 { 224 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 225 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 226 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 227 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 228 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 229 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 230 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 231 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 232 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 233 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 234 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 235 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 236 uint32_t ErrorCode; /*!< DFSDM filter error code */ 237 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 238 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 239 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 240 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 241 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 242 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 243 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 244 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 245 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 246 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 247 #endif 248 }DFSDM_Filter_HandleTypeDef; 249 250 /** 251 * @brief DFSDM filter analog watchdog parameters structure definition 252 */ 253 typedef struct 254 { 255 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 256 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 257 uint32_t Channel; /*!< Analog watchdog channel selection. 258 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 259 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 260 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 261 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 262 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 263 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 264 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 265 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 266 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 267 }DFSDM_Filter_AwdParamTypeDef; 268 269 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 270 /** 271 * @brief DFSDM filter callback ID enumeration definition 272 */ 273 typedef enum 274 { 275 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 276 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 277 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 278 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 279 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 280 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 281 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 282 }HAL_DFSDM_Filter_CallbackIDTypeDef; 283 284 /** 285 * @brief DFSDM filter callback pointer definition 286 */ 287 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 288 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 289 #endif 290 291 /** 292 * @} 293 */ 294 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 295 /** 296 * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices 297 */ 298 typedef struct 299 { 300 uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin. 301 This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/ 302 uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin. 303 This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/ 304 uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout. 305 This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/ 306 uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout. 307 This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/ 308 uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2. 309 This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION 310 @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 311 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */ 312 uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4. 313 This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION 314 @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 315 @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 316 @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 317 @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ 318 uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1. 319 This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */ 320 uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2. 321 This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */ 322 }DFSDM_MultiChannelConfigTypeDef; 323 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ 324 /** 325 * @} 326 */ 327 328 /* End of exported types -----------------------------------------------------*/ 329 330 /* Exported constants --------------------------------------------------------*/ 331 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 332 * @{ 333 */ 334 335 /** @defgroup DFSDM_Channel_OutputClock DFSDM channel output clock selection 336 * @{ 337 */ 338 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */ 339 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ 340 /** 341 * @} 342 */ 343 344 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 345 * @{ 346 */ 347 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 348 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 349 /** 350 * @} 351 */ 352 353 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 354 * @{ 355 */ 356 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 357 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 358 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 359 /** 360 * @} 361 */ 362 363 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 364 * @{ 365 */ 366 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 367 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 368 /** 369 * @} 370 */ 371 372 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 373 * @{ 374 */ 375 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 376 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 377 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 378 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 379 /** 380 * @} 381 */ 382 383 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 384 * @{ 385 */ 386 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 387 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 388 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 389 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 390 /** 391 * @} 392 */ 393 394 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 395 * @{ 396 */ 397 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 398 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 399 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 400 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 401 /** 402 * @} 403 */ 404 405 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 406 * @{ 407 */ 408 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 409 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 410 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 411 /** 412 * @} 413 */ 414 415 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 416 * @{ 417 */ 418 #if defined(STM32F413xx) || defined(STM32F423xx) 419 /* Trigger for stm32f413xx and STM32f423xx devices */ 420 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */ 421 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */ 422 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */ 423 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ 424 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */ 425 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ 426 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */ 427 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */ 428 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/ 429 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */ 430 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */ 431 #else 432 /* Trigger for stm32f412xx devices */ 433 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/ 434 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/ 435 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/ 436 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/ 437 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/ 438 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ 439 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ 440 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/ 441 #endif 442 /** 443 * @} 444 */ 445 446 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 447 * @{ 448 */ 449 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 450 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 451 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 452 /** 453 * @} 454 */ 455 456 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 457 * @{ 458 */ 459 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 460 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 461 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 462 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 463 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 464 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 465 /** 466 * @} 467 */ 468 469 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 470 * @{ 471 */ 472 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 473 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 474 /** 475 * @} 476 */ 477 478 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 479 * @{ 480 */ 481 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 482 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 483 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 484 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 485 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 486 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 487 #endif 488 /** 489 * @} 490 */ 491 492 /** @defgroup DFSDM_BreakSignals DFSDM break signals 493 * @{ 494 */ 495 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 496 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 497 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 498 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 499 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 500 /** 501 * @} 502 */ 503 504 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 505 * @{ 506 */ 507 /* DFSDM Channels ------------------------------------------------------------*/ 508 /* The DFSDM channels are defined as follows: 509 - in 16-bit LSB the channel mask is set 510 - in 16-bit MSB the channel number is set 511 e.g. for channel 3 definition: 512 - the channel mask is 0x00000008 (bit 3 is set) 513 - the channel number 3 is 0x00030000 514 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */ 515 #define DFSDM_CHANNEL_0 0x00000001U 516 #define DFSDM_CHANNEL_1 0x00010002U 517 #define DFSDM_CHANNEL_2 0x00020004U 518 #define DFSDM_CHANNEL_3 0x00030008U 519 #define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */ 520 #define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */ 521 #define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */ 522 #define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */ 523 /** 524 * @} 525 */ 526 527 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 528 * @{ 529 */ 530 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 531 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 537 * @{ 538 */ 539 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 540 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 541 /** 542 * @} 543 */ 544 545 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 546 /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection 547 * @{ 548 */ 549 #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U 550 #define DFSDM1_CKOUT_DFSDM1 0x00000000U 551 /** 552 * @} 553 */ 554 555 /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection 556 * @{ 557 */ 558 #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U 559 #define DFSDM2_CKOUT_DFSDM2 0x00000000U 560 /** 561 * @} 562 */ 563 564 /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection 565 * @{ 566 */ 567 #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U 568 #define DFSDM1_CKIN_PAD 0x00000000U 569 /** 570 * @} 571 */ 572 573 /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection 574 * @{ 575 */ 576 #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U 577 #define DFSDM2_CKIN_PAD 0x00000000U 578 /** 579 * @} 580 */ 581 582 /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution 583 * @{ 584 */ 585 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */ 586 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */ 587 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */ 588 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */ 589 /** 590 * @} 591 */ 592 593 /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution 594 * @{ 595 */ 596 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ 597 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ 598 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ 599 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ 600 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */ 601 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */ 602 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */ 603 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */ 604 /** 605 * @} 606 */ 607 608 /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution 609 * @{ 610 */ 611 #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U 612 #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL 613 #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U 614 #define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL 615 /** 616 * @} 617 */ 618 619 /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution 620 * @{ 621 */ 622 #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U 623 #define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL 624 #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U 625 #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL 626 #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U 627 #define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL 628 #define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U 629 #define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL 630 /** 631 * @} 632 */ 633 634 /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable 635 * @{ 636 */ 637 #define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN 638 #define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN 639 /** 640 * @} 641 */ 642 643 /** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection 644 * @{ 645 */ 646 #define HAL_DFSDM2_CKIN_PAD 0x00040000U 647 #define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG 648 #define HAL_DFSDM1_CKIN_PAD 0x00000000U 649 #define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG 650 /** 651 * @} 652 */ 653 654 /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection 655 * @{ 656 */ 657 #define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U 658 #define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL 659 #define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U 660 #define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL 661 /** 662 * @} 663 */ 664 665 /** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0 666 * @{ 667 */ 668 #define HAL_DATAIN0_DFSDM2_PAD 0x10000000U 669 #define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL 670 #define HAL_DATAIN0_DFSDM1_PAD 0x00000000U 671 #define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL 672 /** 673 * @} 674 */ 675 676 /** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2 677 * @{ 678 */ 679 #define HAL_DATAIN2_DFSDM2_PAD 0x10000000U 680 #define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL 681 #define HAL_DATAIN2_DFSDM1_PAD 0x00000000U 682 #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL 683 /** 684 * @} 685 */ 686 687 /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 688 * @{ 689 */ 690 #define HAL_DATAIN4_DFSDM2_PAD 0x00000000U 691 #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL 692 /** 693 * @} 694 */ 695 696 /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 697 * @{ 698 */ 699 #define HAL_DATAIN6_DFSDM2_PAD 0x00000000U 700 #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL 701 /** 702 * @} 703 */ 704 705 /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN 706 * @{ 707 */ 708 #define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U 709 #define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL 710 #define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U 711 #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL 712 /** 713 * @} 714 */ 715 716 /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN 717 * @{ 718 */ 719 #define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U 720 #define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL 721 #define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U 722 #define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL 723 #define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U 724 #define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL 725 #define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U 726 #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL 727 /** 728 * @} 729 */ 730 731 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/ 732 /** 733 * @} 734 */ 735 /* End of exported constants -------------------------------------------------*/ 736 737 /* Exported macros -----------------------------------------------------------*/ 738 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 739 * @{ 740 */ 741 742 /** @brief Reset DFSDM channel handle state. 743 * @param __HANDLE__ DFSDM channel handle. 744 * @retval None 745 */ 746 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 747 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 748 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 749 (__HANDLE__)->MspInitCallback = NULL; \ 750 (__HANDLE__)->MspDeInitCallback = NULL; \ 751 } while(0) 752 #else 753 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 754 #endif 755 756 /** @brief Reset DFSDM filter handle state. 757 * @param __HANDLE__ DFSDM filter handle. 758 * @retval None 759 */ 760 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 761 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 762 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 763 (__HANDLE__)->MspInitCallback = NULL; \ 764 (__HANDLE__)->MspDeInitCallback = NULL; \ 765 } while(0) 766 #else 767 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 768 #endif 769 770 /** 771 * @} 772 */ 773 /* End of exported macros ----------------------------------------------------*/ 774 775 /* Exported functions --------------------------------------------------------*/ 776 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 777 * @{ 778 */ 779 780 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 781 * @{ 782 */ 783 /* Channel initialization and de-initialization functions *********************/ 784 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 785 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 786 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 787 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 788 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 789 /* Channel callbacks register/unregister functions ****************************/ 790 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 791 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 792 pDFSDM_Channel_CallbackTypeDef pCallback); 793 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 794 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 795 #endif 796 /** 797 * @} 798 */ 799 800 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 801 * @{ 802 */ 803 /* Channel operation functions ************************************************/ 804 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 805 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 806 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 807 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 808 809 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 810 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 811 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 812 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 813 814 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 815 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 816 817 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 818 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 819 820 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 821 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 822 /** 823 * @} 824 */ 825 826 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 827 * @{ 828 */ 829 /* Channel state function *****************************************************/ 830 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 831 /** 832 * @} 833 */ 834 835 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 836 * @{ 837 */ 838 /* Filter initialization and de-initialization functions *********************/ 839 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 840 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 841 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 842 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 843 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 844 /* Filter callbacks register/unregister functions ****************************/ 845 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 846 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 847 pDFSDM_Filter_CallbackTypeDef pCallback); 848 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 849 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 850 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 851 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 852 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 853 #endif 854 /** 855 * @} 856 */ 857 858 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 859 * @{ 860 */ 861 /* Filter control functions *********************/ 862 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 863 uint32_t Channel, 864 uint32_t ContinuousMode); 865 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 866 uint32_t Channel); 867 /** 868 * @} 869 */ 870 871 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 872 * @{ 873 */ 874 /* Filter operation functions *********************/ 875 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 876 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 877 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 878 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 879 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 880 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 881 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 882 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 883 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 884 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 885 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 886 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 887 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 888 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 889 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 890 DFSDM_Filter_AwdParamTypeDef* awdParam); 891 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 892 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 893 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 894 895 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 896 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 897 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 898 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 899 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 900 901 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 902 903 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 904 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 905 906 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 907 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 908 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 909 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 910 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 911 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 912 /** 913 * @} 914 */ 915 916 /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 917 * @{ 918 */ 919 /* Filter state functions *****************************************************/ 920 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 921 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 922 /** 923 * @} 924 */ 925 /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions 926 * @{ 927 */ 928 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 929 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct); 930 void HAL_DFSDM_BitstreamClock_Start(void); 931 void HAL_DFSDM_BitstreamClock_Stop(void); 932 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY); 933 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY); 934 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source); 935 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source); 936 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source); 937 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source); 938 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source); 939 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source); 940 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); 941 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ 942 /** 943 * @} 944 */ 945 /** 946 * @} 947 */ 948 /* End of exported functions -------------------------------------------------*/ 949 950 /* Private macros ------------------------------------------------------------*/ 951 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 952 * @{ 953 */ 954 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 955 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 956 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 957 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 958 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 959 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 960 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 961 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 962 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 963 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 964 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 965 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 966 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 967 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 968 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 969 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 970 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 971 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 972 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 973 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 974 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 975 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 976 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 977 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 978 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 979 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 980 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 981 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 982 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 983 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 984 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 985 #if defined (STM32F413xx) || defined (STM32F423xx) 986 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 987 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 988 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 989 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ 990 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \ 991 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 992 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \ 993 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 994 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 995 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 996 #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \ 997 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) 998 #else 999 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 1000 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 1001 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 1002 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ 1003 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 1004 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 1005 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 1006 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 1007 #endif 1008 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 1009 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 1010 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 1011 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 1012 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 1013 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 1014 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 1015 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 1016 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 1017 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 1018 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 1019 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 1020 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 1021 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 1022 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU) 1023 #if defined(DFSDM2_Channel0) 1024 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 1025 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 1026 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 1027 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 1028 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 1029 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 1030 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 1031 ((CHANNEL) == DFSDM_CHANNEL_7)) 1032 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 1033 #else 1034 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 1035 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 1036 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 1037 ((CHANNEL) == DFSDM_CHANNEL_3)) 1038 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 1039 #endif 1040 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 1041 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 1042 #if defined(DFSDM2_Channel0) 1043 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ 1044 ((INSTANCE) == DFSDM1_Channel1) || \ 1045 ((INSTANCE) == DFSDM1_Channel2) || \ 1046 ((INSTANCE) == DFSDM1_Channel3)) 1047 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ 1048 ((INSTANCE) == DFSDM1_Filter1)) 1049 #endif /* DFSDM2_Channel0 */ 1050 1051 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 1052 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \ 1053 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \ 1054 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \ 1055 ((SELECTION) == HAL_DFSDM1_CKIN_DM)) 1056 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \ 1057 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \ 1058 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \ 1059 ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) 1060 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \ 1061 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \ 1062 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \ 1063 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1)) 1064 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \ 1065 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \ 1066 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \ 1067 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3)) 1068 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \ 1069 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5)) 1070 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \ 1071 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7)) 1072 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \ 1073 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \ 1074 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \ 1075 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \ 1076 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \ 1077 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \ 1078 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \ 1079 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \ 1080 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \ 1081 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \ 1082 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \ 1083 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1)) 1084 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \ 1085 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1)) 1086 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \ 1087 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) 1088 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \ 1089 ((CLKIN) == DFSDM1_CKIN_PAD)) 1090 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \ 1091 ((CLKIN) == DFSDM2_CKIN_PAD)) 1092 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \ 1093 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \ 1094 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \ 1095 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \ 1096 ((CLK) <= 0x30U)) 1097 1098 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \ 1099 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \ 1100 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \ 1101 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \ 1102 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \ 1103 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \ 1104 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \ 1105 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \ 1106 ((CLK) <= 0x1E000U)) 1107 1108 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \ 1109 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \ 1110 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \ 1111 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \ 1112 ((DISTRIBUTION) <= 0xCU)) 1113 1114 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \ 1115 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \ 1116 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \ 1117 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \ 1118 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \ 1119 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \ 1120 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \ 1121 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \ 1122 ((DISTRIBUTION) <= 0x1D00U)) 1123 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */ 1124 /** 1125 * @} 1126 */ 1127 /* End of private macros -----------------------------------------------------*/ 1128 1129 /** 1130 * @} 1131 */ 1132 1133 /** 1134 * @} 1135 */ 1136 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 1137 #ifdef __cplusplus 1138 } 1139 #endif 1140 1141 #endif /* __STM32F4xx_HAL_DFSDM_H */ 1142
