1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_dac_ex.c
4 * @author MCD Application Team
5 * @brief DACEx HAL module driver.
6 * This file provides firmware functions to manage the extended
7 * functionalities of the DAC peripheral.
8 *
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2016 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### How to use this driver #####
24 ==============================================================================
25 [..]
26 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
27 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
28 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
29 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
30 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
31
32 @endverbatim
33 ******************************************************************************
34 */
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "stm32f3xx_hal.h"
38
39 /** @addtogroup STM32F3xx_HAL_Driver
40 * @{
41 */
42
43 #ifdef HAL_DAC_MODULE_ENABLED
44
45 /** @defgroup DACEx DACEx
46 * @brief DAC HAL module driver
47 * @{
48 */
49
50 /* Private typedef -----------------------------------------------------------*/
51 /* Private define ------------------------------------------------------------*/
52 /* Private macro -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54 /* Private function prototypes -----------------------------------------------*/
55 /** @defgroup DACEx_Private_Functions DACEx Private Functions
56 * @{
57 */
58 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
59 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
60 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
61
62 #if defined(STM32F303xE) || defined(STM32F398xx) || \
63 defined(STM32F303xC) || defined(STM32F358xx) || \
64 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
65 defined(STM32F373xC) || defined(STM32F378xx)
66 /* DAC channel 2 is available on top of DAC channel 1U */
67 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
68 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
69 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
70 #endif /* STM32F303xE || STM32F398xx || */
71 /* STM32F303xC || STM32F358xx || */
72 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
73 /* STM32F373xC || STM32F378xx */
74 /**
75 * @}
76 */
77
78 /* Exported functions ---------------------------------------------------------*/
79 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
80 * @{
81 */
82
83 /** @defgroup DACEx_Exported_Functions_Group3 DACEx Peripheral Control functions
84 * @brief Peripheral Control functions
85 *
86 @verbatim
87 ==============================================================================
88 ##### Peripheral Control functions #####
89 ==============================================================================
90 [..] This section provides functions allowing to:
91 (+) Set the specified data holding register value for DAC channel.
92 (+) Set the specified data holding register value for dual DAC channel
93 (when DAC channel 2 is present in DAC 1U)
94
95 @endverbatim
96 * @{
97 */
98
99 /**
100 * @brief Set the specified data holding register value for DAC channel.
101 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
102 * the configuration information for the specified DAC.
103 * @param Channel The selected DAC channel.
104 * @param Alignment Specifies the data alignment for DAC channel.
105 * This parameter can be one of the following values:
106 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
107 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
108 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
109 * @param Data Data to be loaded in the selected data holding register.
110 * @retval HAL status
111 */
HAL_DAC_SetValue(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Alignment,uint32_t Data)112 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
113 {
114 __IO uint32_t tmp = 0U;
115
116 /* Check the parameters */
117 assert_param(IS_DAC_CHANNEL(Channel));
118 assert_param(IS_DAC_ALIGN(Alignment));
119 assert_param(IS_DAC_DATA(Data));
120
121 tmp = (uint32_t) (hdac->Instance);
122
123 /* DAC 1 has 1 or 2 channels - no DAC2 */
124 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
125
126 if(Channel == DAC_CHANNEL_1)
127 {
128 tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
129 }
130 #if defined(STM32F303xE) || defined(STM32F398xx) || \
131 defined(STM32F303xC) || defined(STM32F358xx) || \
132 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
133 defined(STM32F373xC) || defined(STM32F378xx)
134 else /* channel = DAC_CHANNEL_2 */
135 {
136 tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
137 }
138 #endif /* STM32F303xE || STM32F398xx || */
139 /* STM32F303xC || STM32F358xx || */
140 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
141 /* STM32F373xC || STM32F378xx */
142
143 /* Set the DAC channel1 selected data holding register */
144 *(__IO uint32_t *) tmp = Data;
145
146 /* Return function status */
147 return HAL_OK;
148 }
149
150 #if defined(STM32F303xE) || defined(STM32F398xx) || \
151 defined(STM32F303xC) || defined(STM32F358xx) || \
152 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
153 defined(STM32F373xC) || defined(STM32F378xx)
154 /* DAC channel 2 is present in DAC 1U */
155 /**
156 * @brief Set the specified data holding register value for dual DAC channel.
157 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
158 * the configuration information for the specified DAC.
159 * @param Alignment Specifies the data alignment for dual channel DAC.
160 * This parameter can be one of the following values:
161 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
162 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
163 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
164 * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
165 * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
166 * @note In dual mode, a unique register access is required to write in both
167 * DAC channels at the same time.
168 * @retval HAL status
169 */
HAL_DACEx_DualSetValue(DAC_HandleTypeDef * hdac,uint32_t Alignment,uint32_t Data1,uint32_t Data2)170 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
171 {
172 uint32_t data = 0U, tmp = 0U;
173
174 /* Check the parameters */
175 assert_param(IS_DAC_ALIGN(Alignment));
176 assert_param(IS_DAC_DATA(Data1));
177 assert_param(IS_DAC_DATA(Data2));
178
179 /* Calculate and set dual DAC data holding register value */
180 if (Alignment == DAC_ALIGN_8B_R)
181 {
182 data = ((uint32_t)Data2 << 8U) | Data1;
183 }
184 else
185 {
186 data = ((uint32_t)Data2 << 16U) | Data1;
187 }
188
189 tmp = (uint32_t) (hdac->Instance);
190 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
191
192 /* Set the dual DAC selected data holding register */
193 *(__IO uint32_t *)tmp = data;
194
195 /* Return function status */
196 return HAL_OK;
197 }
198 #endif /* STM32F303xE || STM32F398xx || */
199 /* STM32F303xC || STM32F358xx || */
200 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
201 /* STM32F373xC || STM32F378xx */
202
203 /**
204 * @}
205 */
206
207 /** @defgroup DACEx_Exported_Functions_Group2 DACEx Input and Output operation functions
208 * @brief IO operation functions
209 *
210 @verbatim
211 ==============================================================================
212 ##### IO operation functions #####
213 ==============================================================================
214 [..] This section provides functions allowing to:
215 (+) Start conversion.
216 (+) Start conversion and enable DMA transfer.
217 (+) Get result of conversion.
218 (+) Handle DAC IRQ's.
219 (+) Generate triangular-wave
220 (+) Generate noise-wave
221 (+) Callback functions for DAC1 Channel2 (when supported)
222 @endverbatim
223 * @{
224 */
225
226 #if defined(STM32F303xE) || defined(STM32F398xx) || \
227 defined(STM32F303xC) || defined(STM32F358xx) || \
228 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
229 defined(STM32F373xC) || defined(STM32F378xx)
230
231 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
232 /**
233 * @brief Enables DAC and starts conversion of channel.
234 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
235 * the configuration information for the specified DAC.
236 * @param Channel The selected DAC channel.
237 * This parameter can be one of the following values:
238 * @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
239 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
240 * @retval HAL status
241 */
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)242 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
243 {
244 /* Check the parameters */
245 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
246
247 /* Process locked */
248 __HAL_LOCK(hdac);
249
250 /* Change DAC state */
251 hdac->State = HAL_DAC_STATE_BUSY;
252
253 /* Enable the Peripheral */
254 __HAL_DAC_ENABLE(hdac, Channel);
255
256 if(Channel == DAC_CHANNEL_1)
257 {
258 /* Check if software trigger enabled */
259 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
260 {
261 /* Enable the selected DAC software conversion */
262 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
263 }
264 }
265 else
266 {
267 /* Check if software trigger enabled */
268 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
269 {
270 /* Enable the selected DAC software conversion */
271 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
272 }
273 }
274
275 /* Change DAC state */
276 hdac->State = HAL_DAC_STATE_READY;
277
278 /* Process unlocked */
279 __HAL_UNLOCK(hdac);
280
281 /* Return function status */
282 return HAL_OK;
283 }
284 #endif /* STM32F303xE || STM32F398xx || */
285 /* STM32F303xC || STM32F358xx || */
286 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
287 /* STM32F373xC || STM32F378xx */
288
289 #if defined(STM32F302xE) || \
290 defined(STM32F302xC) || \
291 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
292 /* DAC 1 has 1 channels 1U */
293 /**
294 * @brief Enables DAC and starts conversion of channel.
295 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
296 * the configuration information for the specified DAC.
297 * @param Channel The selected DAC channel.
298 * This parameter can be one of the following values:
299 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
300 * @retval HAL status
301 */
302
HAL_DAC_Start(DAC_HandleTypeDef * hdac,uint32_t Channel)303 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
304 {
305 /* Check the parameters */
306 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
307
308 /* Process locked */
309 __HAL_LOCK(hdac);
310
311 /* Change DAC state */
312 hdac->State = HAL_DAC_STATE_BUSY;
313
314 /* Enable the Peripheral */
315 __HAL_DAC_ENABLE(hdac, Channel);
316
317 /* Check if software trigger enabled */
318 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
319 {
320 /* Enable the selected DAC software conversion */
321 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
322 }
323
324 /* Change DAC state */
325 hdac->State = HAL_DAC_STATE_READY;
326
327 /* Process unlocked */
328 __HAL_UNLOCK(hdac);
329
330 /* Return function status */
331 return HAL_OK;
332 }
333 #endif /* STM32F302xE || */
334 /* STM32F302xC || */
335 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
336
337 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
338 #if defined(STM32F303xE) || defined(STM32F398xx) || \
339 defined(STM32F303xC) || defined(STM32F358xx) || \
340 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
341 defined(STM32F373xC) || defined(STM32F378xx)
342 /* DAC 1 has 2 channels 1U & 2U */
343 /**
344 * @brief Enables DAC and starts conversion of channel.
345 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
346 * the configuration information for the specified DAC.
347 * @param Channel The selected DAC channel.
348 * This parameter can be one of the following values:
349 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
350 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
351 * @param pData The destination peripheral Buffer address.
352 * @param Length The length of data to be transferred from memory to DAC peripheral
353 * @param Alignment Specifies the data alignment for DAC channel.
354 * This parameter can be one of the following values:
355 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
356 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
357 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
358 * @retval HAL status
359 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t * pData,uint32_t Length,uint32_t Alignment)360 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
361 {
362 uint32_t tmpreg = 0U;
363
364 /* Check the parameters */
365 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
366 assert_param(IS_DAC_ALIGN(Alignment));
367
368 /* Process locked */
369 __HAL_LOCK(hdac);
370
371 /* Change DAC state */
372 hdac->State = HAL_DAC_STATE_BUSY;
373
374 if(Channel == DAC_CHANNEL_1)
375 {
376 /* Set the DMA transfer complete callback for channel1 */
377 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
378
379 /* Set the DMA half transfer complete callback for channel1 */
380 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
381
382 /* Set the DMA error callback for channel1 */
383 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
384
385 /* Enable the selected DAC channel1 DMA request */
386 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
387
388 /* Case of use of channel 1U */
389 switch(Alignment)
390 {
391 case DAC_ALIGN_12B_R:
392 /* Get DHR12R1 address */
393 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
394 break;
395 case DAC_ALIGN_12B_L:
396 /* Get DHR12L1 address */
397 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
398 break;
399 case DAC_ALIGN_8B_R:
400 /* Get DHR8R1 address */
401 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
402 break;
403 default:
404 break;
405 }
406 }
407 else
408 {
409 /* Set the DMA transfer complete callback for channel2 */
410 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
411
412 /* Set the DMA half transfer complete callback for channel2 */
413 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
414
415 /* Set the DMA error callback for channel2 */
416 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
417
418 /* Enable the selected DAC channel2 DMA request */
419 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
420
421 /* Case of use of channel 2U */
422 switch(Alignment)
423 {
424 case DAC_ALIGN_12B_R:
425 /* Get DHR12R2 address */
426 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
427 break;
428 case DAC_ALIGN_12B_L:
429 /* Get DHR12L2 address */
430 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
431 break;
432 case DAC_ALIGN_8B_R:
433 /* Get DHR8R2 address */
434 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
435 break;
436 default:
437 break;
438 }
439 }
440
441 /* Enable the DMA Channel */
442 if(Channel == DAC_CHANNEL_1)
443 {
444 /* Enable the DAC DMA underrun interrupt */
445 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
446
447 /* Enable the DMA Channel */
448 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
449 }
450 else
451 {
452 /* Enable the DAC DMA underrun interrupt */
453 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
454
455 /* Enable the DMA Channel */
456 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
457 }
458
459 /* Process Unlocked */
460 __HAL_UNLOCK(hdac);
461
462 /* Enable the Peripheral */
463 __HAL_DAC_ENABLE(hdac, Channel);
464
465 /* Return function status */
466 return HAL_OK;
467 }
468 #endif /* STM32F303xE || STM32F398xx || */
469 /* STM32F303xC || STM32F358xx || */
470 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
471 /* STM32F373xC || STM32F378xx */
472
473 #if defined(STM32F302xE) || \
474 defined(STM32F302xC) || \
475 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
476 /* DAC 1 has 1 channel (channel 1U) */
477 /**
478 * @brief Enables DAC and starts conversion of channel.
479 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
480 * the configuration information for the specified DAC.
481 * @param Channel The selected DAC channel.
482 * This parameter can be one of the following values:
483 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
484 * @param pData The destination peripheral Buffer address.
485 * @param Length The length of data to be transferred from memory to DAC peripheral
486 * @param Alignment Specifies the data alignment for DAC channel.
487 * This parameter can be one of the following values:
488 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
489 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
490 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
491 * @retval HAL status
492 */
HAL_DAC_Start_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t * pData,uint32_t Length,uint32_t Alignment)493 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
494 {
495 uint32_t tmpreg = 0U;
496
497 /* Check the parameters */
498 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
499 assert_param(IS_DAC_ALIGN(Alignment));
500
501 /* Process locked */
502 __HAL_LOCK(hdac);
503
504 /* Change DAC state */
505 hdac->State = HAL_DAC_STATE_BUSY;
506
507 /* Set the DMA transfer complete callback for channel1 */
508 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
509
510 /* Set the DMA half transfer complete callback for channel1 */
511 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
512
513 /* Set the DMA error callback for channel1 */
514 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
515
516 /* Enable the selected DAC channel1 DMA request */
517 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
518
519 /* Case of use of channel 1U */
520 switch(Alignment)
521 {
522 case DAC_ALIGN_12B_R:
523 /* Get DHR12R1 address */
524 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
525 break;
526 case DAC_ALIGN_12B_L:
527 /* Get DHR12L1 address */
528 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
529 break;
530 case DAC_ALIGN_8B_R:
531 /* Get DHR8R1 address */
532 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
533 break;
534 default:
535 break;
536 }
537
538 /* Enable the DMA Channel */
539 /* Enable the DAC DMA underrun interrupt */
540 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
541
542 /* Enable the DMA Channel */
543 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
544
545 /* Process Unlocked */
546 __HAL_UNLOCK(hdac);
547
548 /* Enable the Peripheral */
549 __HAL_DAC_ENABLE(hdac, Channel);
550
551 /* Return function status */
552 return HAL_OK;
553 }
554 #endif /* STM32F302xE || */
555 /* STM32F302xC || */
556 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
557
558 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
559 #if defined(STM32F303xE) || defined(STM32F398xx) || \
560 defined(STM32F303xC) || defined(STM32F358xx) || \
561 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
562 defined(STM32F373xC) || defined(STM32F378xx)
563 /* DAC 1 has 2 channels 1U & 2U */
564 /**
565 * @brief Returns the last data output value of the selected DAC channel.
566 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
567 * the configuration information for the specified DAC.
568 * @param Channel The selected DAC channel.
569 * This parameter can be one of the following values:
570 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
571 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
572 * @retval The selected DAC channel data output value.
573 */
HAL_DAC_GetValue(DAC_HandleTypeDef * hdac,uint32_t Channel)574 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
575 {
576 /* Check the parameters */
577 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
578
579 /* Returns the DAC channel data output register value */
580 if(Channel == DAC_CHANNEL_1)
581 {
582 return hdac->Instance->DOR1;
583 }
584 else /* channel = DAC_CHANNEL_2 */
585 {
586 return hdac->Instance->DOR2;
587 }
588 }
589 #endif /* STM32F303xE || STM32F398xx || */
590 /* STM32F303xC || STM32F358xx || */
591 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
592 /* STM32F373xC || STM32F378xx */
593
594 #if defined(STM32F302xE) || \
595 defined(STM32F302xC) || \
596 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
597 /* DAC 1 has 1 channel (channel 1U) */
598 /**
599 * @brief Returns the last data output value of the selected DAC channel.
600 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
601 * the configuration information for the specified DAC.
602 * @param channel The selected DAC channel.
603 * This parameter can be one of the following values:
604 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
605 * @retval The selected DAC channel data output value.
606 */
HAL_DAC_GetValue(DAC_HandleTypeDef * hdac,uint32_t Channel)607 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
608 {
609 /* Check the parameters */
610 assert_param(IS_DAC_CHANNEL_INSTANCE(hdac->Instance, Channel));
611
612 /* Returns the DAC channel data output register value */
613 return hdac->Instance->DOR1;
614 }
615 #endif /* STM32F302xE || */
616 /* STM32F302xC || */
617 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
618
619 /**
620 * @brief Return the last data output value of the selected DAC channel.
621 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
622 * the configuration information for the specified DAC.
623 * @retval The selected DAC channel data output value.
624 */
HAL_DACEx_DualGetValue(DAC_HandleTypeDef * hdac)625 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
626 {
627 uint32_t tmp = 0U;
628
629 tmp |= hdac->Instance->DOR1;
630
631 #if defined(STM32F303xE) || defined(STM32F398xx) || \
632 defined(STM32F303xC) || defined(STM32F358xx) || \
633 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
634 defined(STM32F373xC) || defined(STM32F378xx)
635 /* DAC channel 2 is present in DAC 1U */
636 tmp |= hdac->Instance->DOR2 << 16U;
637 #endif /* STM32F303xE || STM32F398xx || */
638 /* STM32F303xC || STM32F358xx || */
639 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
640 /* STM32F373xC || STM32F378xx */
641
642 /* Returns the DAC channel data output register value */
643 return tmp;
644 }
645
646 #if defined(STM32F303xE) || defined(STM32F398xx) || \
647 defined(STM32F303xC) || defined(STM32F358xx) || \
648 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
649 defined(STM32F373xC) || defined(STM32F378xx)
650 /* DAC channel 2 is available on top of DAC channel 1U */
651 /**
652 * @brief Handles DAC interrupt request
653 * This function uses the interruption of DMA
654 * underrun.
655 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
656 * the configuration information for the specified DAC.
657 * @retval None
658 */
HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef * hdac)659 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
660 {
661 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
662 {
663 /* Check underrun flag of DAC channel 1U */
664 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
665 {
666 /* Change DAC state to error state */
667 hdac->State = HAL_DAC_STATE_ERROR;
668
669 /* Set DAC error code to chanel1 DMA underrun error */
670 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
671
672 /* Clear the underrun flag */
673 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
674
675 /* Disable the selected DAC channel1 DMA request */
676 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
677
678 /* Error callback */
679 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
680 hdac->DMAUnderrunCallbackCh1(hdac);
681 #else
682 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
683 #endif
684 }
685 }
686
687 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
688 {
689 /* Check underrun flag of DAC channel 2 */
690 if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
691 {
692 /* Change DAC state to error state */
693 hdac->State = HAL_DAC_STATE_ERROR;
694
695 /* Set DAC error code to channel2 DMA underrun error */
696 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
697
698 /* Clear the underrun flag */
699 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
700
701 /* Disable the selected DAC channel1 DMA request */
702 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
703
704 /* Error callback */
705 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
706 hdac->DMAUnderrunCallbackCh2(hdac);
707 #else
708 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
709 #endif
710 }
711 }
712 }
713 #endif /* STM32F303xE || STM32F398xx || */
714 /* STM32F303xC || STM32F358xx || */
715 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
716 /* STM32F373xC || STM32F378xx */
717
718 #if defined(STM32F302xE) || \
719 defined(STM32F302xC) || \
720 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
721 /* DAC channel 2 is NOT available. Only DAC channel 1 is available */
722 /**
723 * @brief Handles DAC interrupt request
724 * This function uses the interruption of DMA
725 * underrun.
726 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
727 * the configuration information for the specified DAC.
728 * @retval None
729 */
HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef * hdac)730 void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
731 {
732 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
733 {
734 /* Check underrun flag of DAC channel 1U */
735 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
736 {
737 /* Change DAC state to error state */
738 hdac->State = HAL_DAC_STATE_ERROR;
739
740 /* Set DAC error code to chanel1 DMA underrun error */
741 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
742
743 /* Clear the underrun flag */
744 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
745
746 /* Disable the selected DAC channel1 DMA request */
747 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
748
749 /* Error callback */
750 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
751 }
752 }
753 }
754 #endif /* STM32F302xE || */
755 /* STM32F302xC || */
756 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
757
758 /**
759 * @brief Configures the selected DAC channel.
760 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
761 * the configuration information for the specified DAC.
762 * @param sConfig DAC configuration structure.
763 * @param Channel The selected DAC channel.
764 * This parameter can be one of the following values:
765 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
766 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
767 * @arg DAC_CHANNEL_1: DAC2 Channel1 selected
768 * @retval HAL status
769 */
770
HAL_DAC_ConfigChannel(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)771 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
772 {
773 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
774
775 /* Check the DAC parameters */
776 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
777
778 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
779 if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
780 {
781 /* Output Buffer (BOFF1) control */
782 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
783 }
784 else /* DAC1 channel 2U & DAC2 channel 1U */
785 {
786 /* Output Switch (OUTEN) control */
787 assert_param(IS_DAC_OUTPUT_SWITCH_STATE(sConfig->DAC_OutputSwitch));
788 }
789 #else
790 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
791 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
792 assert_param(IS_DAC_CHANNEL(Channel));
793
794 /* Process locked */
795 __HAL_LOCK(hdac);
796
797 /* Change DAC state */
798 hdac->State = HAL_DAC_STATE_BUSY;
799
800 /* Get the DAC CR value */
801 tmpreg1 = hdac->Instance->CR;
802
803 /* Clear BOFFx-OUTENx, TENx, TSELx, WAVEx and MAMPx bits */
804
805 /* Configure for the selected DAC channel: buffer output or switch output, trigger */
806 /* Set TSELx and TENx bits according to DAC_Trigger value */
807 /* Set BOFFx bit according to DAC_OutputBuffer value OR */
808 /* Set OUTEN bit according to DAC_OutputSwitch value */
809 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
810 if ((hdac->Instance == DAC1) && (Channel == DAC_CHANNEL_1))
811 {
812 /* Output Buffer (BOFF1) control */
813 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
814 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
815 }
816 else /* DAC1 channel 2U & DAC2 channel 1U */
817 {
818 /* Output Switch (OUTEN) control */
819 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_OUTEN1)) << Channel);
820 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputSwitch);
821 }
822 #else
823 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
824 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
825 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
826
827 /* Calculate CR register value depending on DAC_Channel */
828 tmpreg1 |= tmpreg2 << Channel;
829 /* Write to DAC CR */
830 hdac->Instance->CR = tmpreg1;
831
832 /* Disable wave generation */
833 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
834
835 /* Change DAC state */
836 hdac->State = HAL_DAC_STATE_READY;
837
838 /* Process unlocked */
839 __HAL_UNLOCK(hdac);
840
841 /* Return function status */
842 return HAL_OK;
843 }
844
845 /**
846 * @brief Enables or disables the selected DAC channel wave generation.
847 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
848 * the configuration information for the specified DAC.
849 * @param Channel The selected DAC channel.
850 * This parameter can be one of the following values:
851 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
852 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
853 * @param Amplitude Select max triangle amplitude.
854 * This parameter can be one of the following values:
855 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
856 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
857 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
858 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
859 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
860 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
861 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
862 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
863 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
864 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
865 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
866 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
867 * @note Wave generation is not available in DAC2.
868 * @retval HAL status
869 */
HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)870 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
871 {
872 /* Check the parameters */
873 assert_param(IS_DAC_CHANNEL(Channel));
874 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
875
876 /* Process locked */
877 __HAL_LOCK(hdac);
878
879 /* Change DAC state */
880 hdac->State = HAL_DAC_STATE_BUSY;
881
882 /* Enable the selected wave generation for the selected DAC channel */
883 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
884
885 /* Change DAC state */
886 hdac->State = HAL_DAC_STATE_READY;
887
888 /* Process unlocked */
889 __HAL_UNLOCK(hdac);
890
891 /* Return function status */
892 return HAL_OK;
893 }
894
895 /**
896 * @brief Enables or disables the selected DAC channel wave generation.
897 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
898 * the configuration information for the specified DAC.
899 * @param Channel The selected DAC channel.
900 * This parameter can be one of the following values:
901 * @arg DAC_CHANNEL_1: DAC1 Channel1 selected
902 * @arg DAC_CHANNEL_2: DAC1 Channel2 selected
903 * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
904 * This parameter can be one of the following values:
905 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
906 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
907 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
908 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
909 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
910 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
911 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
912 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
913 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
914 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
915 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
916 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
917 * @retval HAL status
918 */
HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)919 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
920 {
921 /* Check the parameters */
922 assert_param(IS_DAC_CHANNEL(Channel));
923 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
924
925 /* Process locked */
926 __HAL_LOCK(hdac);
927
928 /* Change DAC state */
929 hdac->State = HAL_DAC_STATE_BUSY;
930
931 /* Enable the selected wave generation for the selected DAC channel */
932 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
933
934 /* Change DAC state */
935 hdac->State = HAL_DAC_STATE_READY;
936
937 /* Process unlocked */
938 __HAL_UNLOCK(hdac);
939
940 /* Return function status */
941 return HAL_OK;
942 }
943
944 #if defined(STM32F303xE) || defined(STM32F398xx) || \
945 defined(STM32F303xC) || defined(STM32F358xx) || \
946 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
947 defined(STM32F373xC) || defined(STM32F378xx)
948 /* DAC channel 2 is available on top of DAC channel 1U */
949 /**
950 * @brief Conversion complete callback in non blocking mode for Channel2
951 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
952 * the configuration information for the specified DAC.
953 * @retval None
954 */
HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef * hdac)955 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
956 {
957 /* Prevent unused argument(s) compilation warning */
958 UNUSED(hdac);
959
960 /* NOTE : This function Should not be modified, when the callback is needed,
961 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
962 */
963 }
964
965 /**
966 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
967 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
968 * the configuration information for the specified DAC.
969 * @retval None
970 */
HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef * hdac)971 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
972 {
973 /* Prevent unused argument(s) compilation warning */
974 UNUSED(hdac);
975
976 /* NOTE : This function Should not be modified, when the callback is needed,
977 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
978 */
979 }
980
981 /**
982 * @brief Error DAC callback for Channel2.
983 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
984 * the configuration information for the specified DAC.
985 * @retval None
986 */
HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef * hdac)987 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
988 {
989 /* Prevent unused argument(s) compilation warning */
990 UNUSED(hdac);
991
992 /* NOTE : This function Should not be modified, when the callback is needed,
993 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
994 */
995 }
996
997 /**
998 * @brief DMA underrun DAC callback for channel2.
999 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1000 * the configuration information for the specified DAC.
1001 * @retval None
1002 */
HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef * hdac)1003 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
1004 {
1005 /* Prevent unused argument(s) compilation warning */
1006 UNUSED(hdac);
1007
1008 /* NOTE : This function Should not be modified, when the callback is needed,
1009 the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
1010 */
1011 }
1012 #endif /* STM32F303xE || STM32F398xx || */
1013 /* STM32F303xC || STM32F358xx || */
1014 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1015 /* STM32F373xC || STM32F378xx */
1016 /**
1017 * @}
1018 */
1019
1020 /**
1021 * @}
1022 */
1023
1024 /** @addtogroup DACEx_Private_Functions
1025 * @{
1026 */
1027
1028 /**
1029 * @brief DMA conversion complete callback.
1030 * @param hdma pointer to DMA handle.
1031 * @retval None
1032 */
DAC_DMAConvCpltCh1(DMA_HandleTypeDef * hdma)1033 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
1034 {
1035 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1036
1037 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1038 hdac->ConvCpltCallbackCh1(hdac);
1039 #else
1040 HAL_DAC_ConvCpltCallbackCh1(hdac);
1041 #endif
1042
1043 hdac->State= HAL_DAC_STATE_READY;
1044 }
1045
1046 /**
1047 * @brief DMA half transfer complete callback.
1048 * @param hdma pointer to DMA handle.
1049 * @retval None
1050 */
DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef * hdma)1051 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
1052 {
1053 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1054
1055 /* Conversion complete callback */
1056 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1057 hdac->ConvHalfCpltCallbackCh1(hdac);
1058 #else
1059 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
1060 #endif
1061 }
1062
1063 /**
1064 * @brief DMA error callback
1065 * @param hdma pointer to DMA handle.
1066 * @retval None
1067 */
DAC_DMAErrorCh1(DMA_HandleTypeDef * hdma)1068 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
1069 {
1070 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1071
1072 /* Set DAC error code to DMA error */
1073 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1074
1075 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1076 hdac->ErrorCallbackCh1(hdac);
1077 #else
1078 HAL_DAC_ErrorCallbackCh1(hdac);
1079 #endif
1080
1081 hdac->State= HAL_DAC_STATE_READY;
1082 }
1083
1084 #if defined(STM32F303xE) || defined(STM32F398xx) || \
1085 defined(STM32F303xC) || defined(STM32F358xx) || \
1086 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1087 defined(STM32F373xC) || defined(STM32F378xx)
1088 /* DAC channel 2 is available on top of DAC channel 1U */
1089 /**
1090 * @brief DMA conversion complete callback.
1091 * @param hdma pointer to DMA handle.
1092 * @retval None
1093 */
DAC_DMAConvCpltCh2(DMA_HandleTypeDef * hdma)1094 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
1095 {
1096 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1097
1098 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1099 hdac->ConvCpltCallbackCh2(hdac);
1100 #else
1101 HAL_DACEx_ConvCpltCallbackCh2(hdac);
1102 #endif
1103
1104 hdac->State= HAL_DAC_STATE_READY;
1105 }
1106
1107 /**
1108 * @brief DMA half transfer complete callback.
1109 * @param hdma pointer to DMA handle.
1110 * @retval None
1111 */
DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef * hdma)1112 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
1113 {
1114 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1115
1116 /* Conversion complete callback */
1117 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1118 hdac->ConvHalfCpltCallbackCh2(hdac);
1119 #else
1120 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
1121 #endif
1122 }
1123
1124 /**
1125 * @brief DMA error callback
1126 * @param hdma pointer to DMA handle.
1127 * @retval None
1128 */
DAC_DMAErrorCh2(DMA_HandleTypeDef * hdma)1129 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
1130 {
1131 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1132
1133 /* Set DAC error code to DMA error */
1134 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1135
1136 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1137 hdac->ErrorCallbackCh2(hdac);
1138 #else
1139 HAL_DACEx_ErrorCallbackCh2(hdac);
1140 #endif
1141
1142 hdac->State= HAL_DAC_STATE_READY;
1143 }
1144 #endif /* STM32F303xE || STM32F398xx || */
1145 /* STM32F303xC || STM32F358xx || */
1146 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1147 /* STM32F373xC || STM32F378xx */
1148
1149 /**
1150 * @}
1151 */
1152
1153 /**
1154 * @}
1155 */
1156
1157 #endif /* HAL_DAC_MODULE_ENABLED */
1158 /**
1159 * @}
1160 */
1161
1162
