1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_hrtim.h 4 * @author MCD Application Team 5 * @brief Header file of HRTIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F3xx_HAL_HRTIM_H 21 #define STM32F3xx_HAL_HRTIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f3xx_hal_def.h" 29 30 #if defined(HRTIM1) 31 /** @addtogroup STM32F3xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HRTIM HRTIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants 41 * @{ 42 */ 43 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer 44 * @{ 45 */ 46 #define MAX_HRTIM_TIMER 6U 47 /** 48 * @} 49 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types 55 * @{ 56 */ 57 58 /** 59 * @brief HRTIM Configuration Structure definition - Time base related parameters 60 */ 61 typedef struct 62 { 63 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. 64 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ 65 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. 66 The HRTIM instance can be configured to act as a slave (waiting for a trigger 67 to be synchronized) or a master (generating a synchronization signal) or both. 68 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ 69 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when 70 the HRTIM instance is configured as a slave). 71 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */ 72 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs 73 (significant only when the HRTIM instance is configured as a master). 74 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */ 75 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization 76 outputs (significant only when the HRTIM instance is configured as a master). 77 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */ 78 } HRTIM_InitTypeDef; 79 80 /** 81 * @brief HAL State structures definition 82 */ 83 typedef enum 84 { 85 HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 86 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 87 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 88 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ 89 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */ 90 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 91 HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */ 92 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 93 } HAL_HRTIM_StateTypeDef; 94 95 /** 96 * @brief HRTIM Timer Structure definition 97 */ 98 typedef struct 99 { 100 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1. 101 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 102 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 103 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2. 104 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 105 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 106 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */ 107 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */ 108 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */ 109 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */ 110 uint32_t DMASize; /*!< Size of the DMA transfer */ 111 } HRTIM_TimerParamTypeDef; 112 113 /** 114 * @brief HRTIM Handle Structure definition 115 */ 116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 117 typedef struct __HRTIM_HandleTypeDef 118 #else 119 typedef struct 120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 121 { 122 HRTIM_TypeDef * Instance; /*!< Register base address */ 123 124 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ 125 126 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */ 127 128 HAL_LockTypeDef Lock; /*!< Locking object */ 129 130 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ 131 132 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ 133 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ 134 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ 135 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ 136 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ 137 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ 138 139 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 140 void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ 141 void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */ 142 void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */ 143 void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */ 144 void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */ 145 void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */ 146 void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DLL Ready interrupt callback function pointer */ 147 void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */ 148 void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */ 149 void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */ 150 151 void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */ 152 void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */ 153 void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */ 154 void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */ 155 void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */ 156 void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */ 157 void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */ 158 void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */ 159 void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */ 160 void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */ 161 void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */ 162 void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */ 163 void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */ 164 void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */ 165 void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */ 166 167 void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 168 void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 169 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 170 } HRTIM_HandleTypeDef; 171 172 /** 173 * @brief Simple output compare mode configuration definition 174 */ 175 typedef struct 176 { 177 uint32_t Period; /*!< Specifies the timer period. 178 The period value must be above 3 periods of the fHRTIM clock. 179 Maximum value is = 0xFFDFU */ 180 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period. 181 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 182 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. 183 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */ 184 uint32_t Mode; /*!< Specifies the counter operating mode. 185 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */ 186 } HRTIM_TimeBaseCfgTypeDef; 187 188 /** 189 * @brief Simple output compare mode configuration definition 190 */ 191 typedef struct 192 { 193 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive). 194 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */ 195 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 196 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 197 uint32_t Polarity; /*!< Specifies the output polarity. 198 This parameter can be any value of @ref HRTIM_Output_Polarity */ 199 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 200 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 201 } HRTIM_SimpleOCChannelCfgTypeDef; 202 203 /** 204 * @brief Simple PWM output mode configuration definition 205 */ 206 typedef struct 207 { 208 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 209 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 210 uint32_t Polarity; /*!< Specifies the output polarity. 211 This parameter can be any value of @ref HRTIM_Output_Polarity */ 212 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 213 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 214 } HRTIM_SimplePWMChannelCfgTypeDef; 215 216 /** 217 * @brief Simple capture mode configuration definition 218 */ 219 typedef struct 220 { 221 uint32_t Event; /*!< Specifies the external event triggering the capture. 222 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 223 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 224 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 225 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 226 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 227 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 228 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 229 } HRTIM_SimpleCaptureChannelCfgTypeDef; 230 231 /** 232 * @brief Simple One Pulse mode configuration definition 233 */ 234 typedef struct 235 { 236 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 237 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 238 uint32_t OutputPolarity; /*!< Specifies the output polarity. 239 This parameter can be any value of @ref HRTIM_Output_Polarity */ 240 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 241 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 242 uint32_t Event; /*!< Specifies the external event triggering the pulse generation. 243 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 244 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 245 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 246 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 247 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */ 248 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 249 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 250 } HRTIM_SimpleOnePulseChannelCfgTypeDef; 251 252 /** 253 * @brief Timer configuration definition 254 */ 255 typedef struct 256 { 257 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master. 258 Specifies which interrupts requests must enabled for the timer. 259 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable 260 or @ref HRTIM_Timing_Unit_Interrupt_Enable */ 261 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master. 262 Specifies which DMA requests must be enabled for the timer. 263 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable 264 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */ 265 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master. 266 Specifies the address of the source address of the DMA transfer */ 267 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master. 268 Specifies the address of the destination address of the DMA transfer */ 269 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. 270 Specifies the size of the DMA transfer */ 271 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. 272 Specifies whether or not half mode is enabled 273 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ 274 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. 275 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 276 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */ 277 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master. 278 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 279 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */ 280 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master. 281 Indicates whether or not the a DAC synchronization event is generated. 282 This parameter can be any value of @ref HRTIM_DAC_Synchronization */ 283 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master. 284 Specifies whether or not register preload is enabled. 285 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */ 286 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master. 287 Specifies how the update occurs with respect to a burst DMA transaction or 288 update enable inputs (Slave timers only). 289 This parameter can be any value of @ref HRTIM_Update_Gating */ 290 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master. 291 Specifies how the timer behaves during a burst mode operation. 292 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */ 293 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master. 294 Specifies whether or not registers update is triggered by the repetition event. 295 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */ 296 uint32_t PushPull; /*!< Relevant for Timer A to Timer E. 297 Specifies whether or not the push-pull mode is enabled. 298 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */ 299 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E. 300 Specifies which fault channels are enabled for the timer. 301 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */ 302 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E. 303 Specifies whether or not fault enabling status is write protected. 304 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */ 305 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E. 306 Specifies whether or not dead-time insertion is enabled for the timer. 307 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */ 308 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E. 309 Specifies the delayed protection mode. 310 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */ 311 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E. 312 Specifies source(s) triggering the timer registers update. 313 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */ 314 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E. 315 Specifies source(s) triggering the timer counter reset. 316 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */ 317 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E. 318 Specifies whether or not registers update is triggered when the timer counter is reset. 319 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */ 320 } HRTIM_TimerCfgTypeDef; 321 322 /** 323 * @brief Compare unit configuration definition 324 */ 325 typedef struct 326 { 327 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit. 328 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. 329 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */ 330 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4. 331 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */ 332 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected. 333 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */ 334 } HRTIM_CompareCfgTypeDef; 335 336 /** 337 * @brief Capture unit configuration definition 338 */ 339 typedef struct 340 { 341 uint32_t Trigger; /*!< Specifies source(s) triggering the capture. 342 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ 343 } HRTIM_CaptureCfgTypeDef; 344 345 /** 346 * @brief Output configuration definition 347 */ 348 typedef struct 349 { 350 uint32_t Polarity; /*!< Specifies the output polarity. 351 This parameter can be any value of @ref HRTIM_Output_Polarity */ 352 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. 353 This parameter can be a combination of @ref HRTIM_Output_Set_Source */ 354 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. 355 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ 356 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. 357 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ 358 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 359 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 360 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. 361 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ 362 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled 363 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ 364 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. 365 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ 366 } HRTIM_OutputCfgTypeDef; 367 368 /** 369 * @brief External event filtering in timing units configuration definition 370 */ 371 typedef struct 372 { 373 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit. 374 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */ 375 uint32_t Latch; /*!< Specifies whether or not the signal is latched. 376 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */ 377 } HRTIM_TimerEventFilteringCfgTypeDef; 378 379 /** 380 * @brief Dead time feature configuration definition 381 */ 382 typedef struct 383 { 384 uint32_t Prescaler; /*!< Specifies the dead-time prescaler. 385 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */ 386 uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge. 387 This parameter can be a number between 0x0 and 0x1FFU */ 388 uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. 389 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */ 390 uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected. 391 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */ 392 uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected. 393 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */ 394 uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge. 395 This parameter can be a number between 0x0 and 0x1FFU */ 396 uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. 397 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */ 398 uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected. 399 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */ 400 uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected. 401 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */ 402 } HRTIM_DeadTimeCfgTypeDef; 403 404 /** 405 * @brief Chopper mode configuration definition 406 */ 407 typedef struct 408 { 409 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. 410 This parameter can be a value of @ref HRTIM_Chopper_Frequency */ 411 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. 412 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */ 413 uint32_t StartPulse; /*!< Specifies the Timer pulse width value. 414 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */ 415 } HRTIM_ChopperModeCfgTypeDef; 416 417 /** 418 * @brief External event channel configuration definition 419 */ 420 typedef struct 421 { 422 uint32_t Source; /*!< Identifies the source of the external event. 423 This parameter can be a value of @ref HRTIM_External_Event_Sources */ 424 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 425 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 426 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event. 427 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 428 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 429 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 430 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. 431 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */ 432 } HRTIM_EventCfgTypeDef; 433 434 /** 435 * @brief Fault channel configuration definition 436 */ 437 typedef struct 438 { 439 uint32_t Source; /*!< Identifies the source of the fault. 440 This parameter can be a value of @ref HRTIM_Fault_Sources */ 441 uint32_t Polarity; /*!< Specifies the polarity of the fault event. 442 This parameter can be a value of @ref HRTIM_Fault_Polarity */ 443 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. 444 This parameter can be a value of @ref HRTIM_Fault_Filter */ 445 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. 446 This parameter can be a value of @ref HRTIM_Fault_Lock */ 447 } HRTIM_FaultCfgTypeDef; 448 449 /** 450 * @brief Burst mode configuration definition 451 */ 452 typedef struct 453 { 454 uint32_t Mode; /*!< Specifies the burst mode operating mode. 455 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */ 456 uint32_t ClockSource; /*!< Specifies the burst mode clock source. 457 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */ 458 uint32_t Prescaler; /*!< Specifies the burst mode prescaler. 459 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */ 460 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER). 461 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */ 462 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation. 463 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */ 464 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state. 465 This parameter can be a number between 0x0 and 0xFFFF */ 466 uint32_t Period; /*!< Specifies burst mode repetition period. 467 This parameter can be a number between 0x1 and 0xFFFF */ 468 } HRTIM_BurstModeCfgTypeDef; 469 470 /** 471 * @brief ADC trigger configuration definition 472 */ 473 typedef struct 474 { 475 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source. 476 This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */ 477 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion. 478 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */ 479 } HRTIM_ADCTriggerCfgTypeDef; 480 481 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 482 /** 483 * @brief HAL HRTIM Callback ID enumeration definition 484 */ 485 typedef enum { 486 HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ 487 HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ 488 HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ 489 HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */ 490 HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */ 491 HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */ 492 HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID = 0x06U, /*!< DLL Ready interrupt callback ID */ 493 HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */ 494 HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */ 495 HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */ 496 497 HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */ 498 HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */ 499 HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */ 500 HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */ 501 HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */ 502 HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */ 503 HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */ 504 HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */ 505 HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */ 506 HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */ 507 HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */ 508 HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */ 509 HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */ 510 HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */ 511 HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */ 512 513 HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ 514 HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ 515 }HAL_HRTIM_CallbackIDTypeDef; 516 517 /** 518 * @brief HAL HRTIM Callback function pointer definitions 519 */ 520 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */ 521 522 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */ 523 uint32_t TimerIdx); 524 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 525 526 /** 527 * @} 528 */ 529 530 /* Exported constants --------------------------------------------------------*/ 531 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants 532 * @{ 533 */ 534 535 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index 536 * @{ 537 * @brief Constants defining the timer indexes 538 */ 539 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */ 540 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */ 541 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */ 542 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */ 543 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */ 544 #define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */ 545 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */ 546 /** 547 * @} 548 */ 549 550 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier 551 * @{ 552 * @brief Constants defining timer identifiers 553 */ 554 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */ 555 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ 556 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ 557 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ 558 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ 559 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ 560 /** 561 * @} 562 */ 563 564 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit 565 * @{ 566 * @brief Constants defining compare unit identifiers 567 */ 568 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */ 569 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ 570 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ 571 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ 572 /** 573 * @} 574 */ 575 576 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit 577 * @{ 578 * @brief Constants defining capture unit identifiers 579 */ 580 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */ 581 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */ 582 /** 583 * @} 584 */ 585 586 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output 587 * @{ 588 * @brief Constants defining timer output identifiers 589 */ 590 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */ 591 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */ 592 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */ 593 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */ 594 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */ 595 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */ 596 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */ 597 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */ 598 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */ 599 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */ 600 /** 601 * @} 602 */ 603 604 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger 605 * @{ 606 * @brief Constants defining ADC triggers identifiers 607 */ 608 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */ 609 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */ 610 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */ 611 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ 612 613 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ 614 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ 615 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ 616 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ 617 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) 618 /** 619 * @} 620 */ 621 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels 622 * @{ 623 * @brief Constants defining external event channel identifiers 624 */ 625 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ 626 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ 627 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ 628 #define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ 629 #define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ 630 #define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ 631 #define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ 632 #define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ 633 #define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ 634 #define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ 635 #define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */ 636 /** 637 * @} 638 */ 639 640 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel 641 * @{ 642 * @brief Constants defining fault channel identifiers 643 */ 644 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */ 645 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */ 646 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */ 647 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */ 648 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */ 649 /** 650 * @} 651 */ 652 653 654 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio 655 * @{ 656 * @brief Constants defining timer high-resolution clock prescaler ratio. 657 */ 658 #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ 659 #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ 660 #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ 661 #define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ 662 #define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ 663 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 664 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 665 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode 671 * @{ 672 * @brief Constants defining timer counter operating mode. 673 */ 674 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 675 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */ 676 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 677 /** 678 * @} 679 */ 680 681 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable 682 * @{ 683 * @brief Constants defining half mode enabling status. 684 */ 685 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */ 686 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */ 687 /** 688 * @} 689 */ 690 691 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event 692 * @{ 693 * @brief Constants defining the timer behavior following the synchronization event 694 */ 695 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 696 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ 697 /** 698 * @} 699 */ 700 701 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event 702 * @{ 703 * @brief Constants defining the timer behavior following the synchronization event 704 */ 705 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 706 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ 707 /** 708 * @} 709 */ 710 711 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization 712 * @{ 713 * @brief Constants defining on which output the DAC synchronization event is sent 714 */ 715 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */ 716 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 717 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 718 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable 724 * @{ 725 * @brief Constants defining whether a write access into a preloadable 726 * register is done into the active or the preload register. 727 */ 728 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */ 729 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ 730 /** 731 * @} 732 */ 733 734 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating 735 * @{ 736 * @brief Constants defining how the update occurs relatively to the burst DMA 737 * transaction and the external update request on update enable inputs 1 to 3. 738 */ 739 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 740 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 741 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 742 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */ 743 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */ 744 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */ 745 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */ 746 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */ 747 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */ 748 /** 749 * @} 750 */ 751 752 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode 753 * @{ 754 * @brief Constants defining how the timer behaves during a burst 755 mode operation. 756 */ 757 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */ 758 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 759 /** 760 * @} 761 */ 762 763 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update 764 * @{ 765 * @brief Constants defining whether registers are updated when the timer 766 * repetition period is completed (either due to roll-over or 767 * reset events) 768 */ 769 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */ 770 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ 771 /** 772 * @} 773 */ 774 775 776 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode 777 * @{ 778 * @brief Constants defining whether or not the push-pull mode is enabled for 779 * a timer. 780 */ 781 #define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */ 782 #define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ 783 /** 784 * @} 785 */ 786 787 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling 788 * @{ 789 * @brief Constants defining whether a fault channel is enabled for a timer 790 */ 791 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ 792 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ 793 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ 794 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ 795 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ 796 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ 797 /** 798 * @} 799 */ 800 801 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock 802 * @{ 803 * @brief Constants defining whether or not fault enabling bits are write 804 * protected for a timer 805 */ 806 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */ 807 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */ 808 /** 809 * @} 810 */ 811 812 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion 813 * @{ 814 * @brief Constants defining whether or not fault the dead time insertion 815 * feature is enabled for a timer 816 */ 817 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */ 818 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */ 819 /** 820 * @} 821 */ 822 823 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode 824 * @{ 825 * @brief Constants defining all possible delayed protection modes 826 * for a timer. Also define the source and outputs on which the delayed 827 * protection schemes are applied 828 */ 829 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 830 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */ 831 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */ 832 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */ 833 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */ 834 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */ 835 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */ 836 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ 837 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ 838 839 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 840 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ 841 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ 842 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ 843 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ 844 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ 845 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ 846 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ 847 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ 848 /** 849 * @} 850 */ 851 852 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger 853 * @{ 854 * @brief Constants defining whether the registers update is done synchronously 855 * with any other timer or master update 856 */ 857 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */ 858 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ 859 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ 860 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ 861 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ 862 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ 863 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ 864 /** 865 * @} 866 */ 867 868 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger 869 * @{ 870 * @brief Constants defining the events that can be selected to trigger the reset 871 * of the timer counter 872 */ 873 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */ 874 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ 875 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ 876 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ 877 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ 878 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ 879 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ 880 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ 881 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ 882 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */ 883 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */ 884 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */ 885 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */ 886 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */ 887 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */ 888 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */ 889 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */ 890 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */ 891 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */ 892 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 893 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 894 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 895 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 896 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 897 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 898 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 899 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 900 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 901 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 902 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 903 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 904 /** 905 * @} 906 */ 907 908 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update 909 * @{ 910 * @brief Constants defining whether the register are updated upon Timerx 911 * counter reset or roll-over to 0 after reaching the period value 912 * in continuous mode 913 */ 914 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ 915 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ 916 /** 917 * @} 918 */ 919 920 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode 921 * @{ 922 * @brief Constants defining whether the compare register is behaving in 923 * regular mode (compare match issued as soon as counter equal compare), 924 * or in auto-delayed mode 925 */ 926 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */ 927 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 928 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 929 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 930 /** 931 * @} 932 */ 933 934 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode 935 * @{ 936 * @brief Constants defining the behavior of the output signal when the timer 937 operates in basic output compare mode 938 */ 939 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */ 940 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */ 941 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ 942 943 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ 944 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ 945 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ 946 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) 947 /** 948 * @} 949 */ 950 951 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity 952 * @{ 953 * @brief Constants defining the polarity of a timer output 954 */ 955 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ 956 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 957 /** 958 * @} 959 */ 960 961 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source 962 * @{ 963 * @brief Constants defining the events that can be selected to configure the 964 * set crossbar of a timer output 965 */ 966 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ 967 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ 968 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ 969 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ 970 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ 971 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ 972 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ 973 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ 974 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ 975 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ 976 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ 977 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ 978 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 979 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 980 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 981 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 982 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 983 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 984 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 985 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 986 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 987 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ 988 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ 989 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ 990 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ 991 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ 992 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ 993 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ 994 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ 995 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ 996 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ 997 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source 1003 * @{ 1004 * @brief Constants defining the events that can be selected to configure the 1005 * reset crossbar of a timer output 1006 */ 1007 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ 1008 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ 1009 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ 1010 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ 1011 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ 1012 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ 1013 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ 1014 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ 1015 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ 1016 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ 1017 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ 1018 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ 1019 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1020 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1021 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1022 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1023 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1024 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1025 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1026 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1027 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1028 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ 1029 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ 1030 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ 1031 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ 1032 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ 1033 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ 1034 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ 1035 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ 1036 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ 1037 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ 1038 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ 1039 /** 1040 * @} 1041 */ 1042 1043 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode 1044 * @{ 1045 * @brief Constants defining whether or not the timer output transition to its 1046 IDLE state when burst mode is entered 1047 */ 1048 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ 1049 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level 1055 * @{ 1056 * @brief Constants defining the output level when output is in IDLE state 1057 */ 1058 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 1059 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 1060 /** 1061 * @} 1062 */ 1063 1064 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level 1065 * @{ 1066 * @brief Constants defining the output level when output is in FAULT state 1067 */ 1068 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ 1069 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 1070 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 1071 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 1072 /** 1073 * @} 1074 */ 1075 1076 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable 1077 * @{ 1078 * @brief Constants defining whether or not chopper mode is enabled for a timer 1079 output 1080 */ 1081 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 1082 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 1083 /** 1084 * @} 1085 */ 1086 1087 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed 1088 * @{ 1089 * @brief Constants defining the idle mode entry is delayed by forcing a 1090 dead-time insertion before switching the outputs to their idle state 1091 */ 1092 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 1093 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */ 1094 /** 1095 * @} 1096 */ 1097 1098 1099 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger 1100 * @{ 1101 * @brief Constants defining the events that can be selected to trigger the 1102 * capture of the timing unit counter 1103 */ 1104 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ 1105 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ 1106 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ 1107 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ 1108 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ 1109 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ 1110 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ 1111 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ 1112 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ 1113 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ 1114 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ 1115 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ 1116 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ 1117 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ 1118 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */ 1119 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */ 1120 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ 1121 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ 1122 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */ 1123 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */ 1124 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ 1125 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ 1126 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */ 1127 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */ 1128 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ 1129 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ 1130 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */ 1131 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */ 1132 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ 1133 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ 1134 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */ 1135 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */ 1136 /** 1137 * @} 1138 */ 1139 1140 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter 1141 * @{ 1142 * @brief Constants defining the event filtering applied to external events 1143 * by a timer 1144 */ 1145 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) 1146 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ 1147 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ 1148 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ 1149 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ 1150 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1151 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1152 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1153 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1154 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1155 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1156 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1157 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1158 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ 1159 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ 1160 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 1161 /** 1162 * @} 1163 */ 1164 1165 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch 1166 * @{ 1167 * @brief Constants defining whether or not the external event is 1168 * memorized (latched) and generated as soon as the blanking period 1169 * is completed or the window ends 1170 */ 1171 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */ 1172 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio 1178 * @{ 1179 * @brief Constants defining division ratio between the timer clock frequency 1180 * (fHRTIM) and the dead-time generator clock (fDTG) 1181 */ 1182 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ 1183 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ 1184 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ 1185 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 1186 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ 1187 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ 1188 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ 1189 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ 1190 /** 1191 * @} 1192 */ 1193 1194 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign 1195 * @{ 1196 * @brief Constants defining whether the dead-time is positive or negative 1197 * (overlapping signal) on rising edge 1198 */ 1199 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */ 1200 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */ 1201 /** 1202 * @} 1203 */ 1204 1205 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock 1206 * @{ 1207 * @brief Constants defining whether or not the dead-time (rising sign and 1208 * value) is write protected 1209 */ 1210 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */ 1211 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */ 1212 /** 1213 * @} 1214 */ 1215 1216 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock 1217 * @{ 1218 * @brief Constants defining whether or not the dead-time rising sign is write 1219 * protected 1220 */ 1221 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */ 1222 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */ 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign 1228 * @{ 1229 * @brief Constants defining whether the dead-time is positive or negative 1230 * (overlapping signal) on falling edge 1231 */ 1232 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */ 1233 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */ 1234 /** 1235 * @} 1236 */ 1237 1238 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock 1239 * @{ 1240 * @brief Constants defining whether or not the dead-time (falling sign and 1241 * value) is write protected 1242 */ 1243 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */ 1244 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */ 1245 /** 1246 * @} 1247 */ 1248 1249 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock 1250 * @{ 1251 * @brief Constants defining whether or not the dead-time falling sign is write 1252 * protected 1253 */ 1254 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */ 1255 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */ 1256 /** 1257 * @} 1258 */ 1259 1260 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency 1261 * @{ 1262 * @brief Constants defining the frequency of the generated high frequency carrier 1263 */ 1264 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */ 1265 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 1266 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 1267 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 1268 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 1269 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 1270 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 1271 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 1272 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 1273 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 1274 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 1275 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 1276 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 1277 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 1278 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 1279 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 1280 /** 1281 * @} 1282 */ 1283 1284 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle 1285 * @{ 1286 * @brief Constants defining the duty cycle of the generated high frequency carrier 1287 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 1288 */ 1289 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ 1290 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ 1291 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ 1292 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ 1293 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */ 1294 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */ 1295 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */ 1296 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */ 1297 /** 1298 * @} 1299 */ 1300 1301 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width 1302 * @{ 1303 * @brief Constants defining the pulse width of the first pulse of the generated 1304 * high frequency carrier 1305 */ 1306 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ 1307 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 1308 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 1309 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 1310 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 1311 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 1312 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 1313 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 1314 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 1315 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 1316 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 1317 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 1318 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 1319 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 1320 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 1321 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 1322 /** 1323 * @} 1324 */ 1325 1326 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options 1327 * @{ 1328 * @brief Constants defining the options for synchronizing multiple HRTIM 1329 * instances, as a master unit (generating a synchronization signal) 1330 * or as a slave (waiting for a trigger to be synchronized) 1331 */ 1332 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */ 1333 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/ 1334 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */ 1335 /** 1336 * @} 1337 */ 1338 1339 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source 1340 * @{ 1341 * @brief Constants defining defining the synchronization input source 1342 */ 1343 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ 1344 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ 1345 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 1346 /** 1347 * @} 1348 */ 1349 1350 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source 1351 * @{ 1352 * @brief Constants defining the source and event to be sent on the 1353 * synchronization outputs 1354 */ 1355 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 1356 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 1357 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 1358 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 1359 /** 1360 * @} 1361 */ 1362 1363 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity 1364 * @{ 1365 * @brief Constants defining the routing and conditioning of the synchronization output event 1366 */ 1367 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ 1368 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 1369 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 1370 /** 1371 * @} 1372 */ 1373 1374 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources 1375 * @{ 1376 * @brief Constants defining available sources associated to external events 1377 */ 1378 #define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */ 1379 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */ 1380 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */ 1381 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */ 1382 /** 1383 * @} 1384 */ 1385 1386 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity 1387 * @{ 1388 * @brief Constants defining the polarity of an external event 1389 */ 1390 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */ 1391 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 1392 /** 1393 * @} 1394 */ 1395 1396 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity 1397 * @{ 1398 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) 1399 * of an external event 1400 */ 1401 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */ 1402 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 1403 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 1404 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 1405 /** 1406 * @} 1407 */ 1408 1409 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode 1410 * @{ 1411 * @brief Constants defining whether or not an external event is programmed in 1412 fast mode 1413 */ 1414 #define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 1415 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 1416 /** 1417 * @} 1418 */ 1419 1420 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter 1421 * @{ 1422 * @brief Constants defining the frequency used to sample an external event 6 1423 * input and the length (N) of the digital filter applied 1424 */ 1425 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1426 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1427 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1428 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1429 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */ 1430 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */ 1431 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */ 1432 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */ 1433 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */ 1434 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */ 1435 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */ 1436 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */ 1437 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */ 1438 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */ 1439 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */ 1440 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */ 1441 /** 1442 * @} 1443 */ 1444 1445 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler 1446 * @{ 1447 * @brief Constants defining division ratio between the timer clock frequency 1448 * fHRTIM) and the external event signal sampling clock (fEEVS) 1449 * used by the digital filters 1450 */ 1451 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */ 1452 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */ 1453 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */ 1454 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */ 1455 /** 1456 * @} 1457 */ 1458 1459 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources 1460 * @{ 1461 * @brief Constants defining whether a fault is triggered by any external 1462 * or internal fault source 1463 */ 1464 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ 1465 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 1466 /** 1467 * @} 1468 */ 1469 1470 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity 1471 * @{ 1472 * @brief Constants defining the polarity of a fault event 1473 */ 1474 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ 1475 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 1476 /** 1477 * @} 1478 */ 1479 1480 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter 1481 * @{ 1482 * @ brief Constants defining the frequency used to sample the fault input and 1483 * the length (N) of the digital filter applied 1484 */ 1485 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1486 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1487 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1488 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1489 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */ 1490 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */ 1491 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */ 1492 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */ 1493 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */ 1494 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */ 1495 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */ 1496 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */ 1497 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */ 1498 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */ 1499 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */ 1500 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */ 1501 /** 1502 * @} 1503 */ 1504 1505 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock 1506 * @{ 1507 * @brief Constants defining whether or not the fault programming bits are 1508 write protected 1509 */ 1510 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ 1511 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ 1512 /** 1513 * @} 1514 */ 1515 1516 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler 1517 * @{ 1518 * @brief Constants defining the division ratio between the timer clock 1519 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used 1520 * by the digital filters. 1521 */ 1522 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */ 1523 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */ 1524 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */ 1525 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */ 1526 /** 1527 * @} 1528 */ 1529 1530 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode 1531 * @{ 1532 * @brief Constants defining if the burst mode is entered once or if it is 1533 * continuously operating 1534 */ 1535 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ 1536 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 1537 /** 1538 * @} 1539 */ 1540 1541 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source 1542 * @{ 1543 * @brief Constants defining the clock source for the burst mode counter 1544 */ 1545 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 1546 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 1547 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 1548 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 1549 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 1550 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 1551 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 1552 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 1553 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 1554 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 1555 /** 1556 * @} 1557 */ 1558 1559 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler 1560 * @{ 1561 * @brief Constants defining the prescaling ratio of the fHRTIM clock 1562 * for the burst mode controller 1563 */ 1564 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */ 1565 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */ 1566 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */ 1567 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */ 1568 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */ 1569 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */ 1570 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */ 1571 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */ 1572 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */ 1573 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */ 1574 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */ 1575 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/ 1576 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */ 1577 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */ 1578 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */ 1579 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */ 1580 /** 1581 * @} 1582 */ 1583 1584 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable 1585 * @{ 1586 * @brief Constants defining whether or not burst mode registers preload 1587 mechanism is enabled, i.e. a write access into a preloadable register 1588 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register 1589 */ 1590 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */ 1591 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ 1592 /** 1593 * @} 1594 */ 1595 1596 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger 1597 * @{ 1598 * @brief Constants defining the events that can be used to trig the burst 1599 * mode operation 1600 */ 1601 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ 1602 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ 1603 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ 1604 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ 1605 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */ 1606 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */ 1607 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */ 1608 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ 1609 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ 1610 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ 1611 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ 1612 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ 1613 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ 1614 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ 1615 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ 1616 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ 1617 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ 1618 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ 1619 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */ 1620 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ 1621 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ 1622 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */ 1623 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ 1624 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */ 1625 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ 1626 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ 1627 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ 1628 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ 1629 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ 1630 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */ 1631 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/ 1632 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ 1633 /** 1634 * @} 1635 */ 1636 1637 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source 1638 * @{ 1639 * @brief constants defining the source triggering the update of the 1640 HRTIM_ADCxR register (transfer from preload to active register). 1641 */ 1642 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ 1643 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ 1644 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ 1645 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ 1646 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ 1647 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ 1648 /** 1649 * @} 1650 */ 1651 1652 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event 1653 * @{ 1654 * @brief constants defining the events triggering ADC conversion. 1655 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 1656 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 1657 */ 1658 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ 1659 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ 1660 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ 1661 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ 1662 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */ 1663 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ 1664 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */ 1665 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */ 1666 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */ 1667 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */ 1668 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */ 1669 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */ 1670 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */ 1671 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */ 1672 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ 1673 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ 1674 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */ 1675 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */ 1676 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */ 1677 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ 1678 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ 1679 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */ 1680 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */ 1681 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */ 1682 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ 1683 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */ 1684 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */ 1685 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */ 1686 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ 1687 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */ 1688 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */ 1689 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */ 1690 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ 1691 1692 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */ 1693 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */ 1694 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */ 1695 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */ 1696 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */ 1697 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ 1698 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */ 1699 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */ 1700 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */ 1701 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */ 1702 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */ 1703 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */ 1704 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */ 1705 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */ 1706 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ 1707 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */ 1708 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */ 1709 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */ 1710 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ 1711 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */ 1712 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */ 1713 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */ 1714 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ 1715 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ 1716 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */ 1717 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */ 1718 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */ 1719 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ 1720 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ 1721 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */ 1722 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ 1723 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ 1724 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ 1725 1726 /** 1727 * @} 1728 */ 1729 1730 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate 1731 * @{ 1732 * @brief Constants defining the DLL calibration periods (in micro seconds) 1733 */ 1734 #define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */ 1735 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.300 ms) */ 1736 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.910 ms) */ 1737 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.114 ms) */ 1738 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.014 ms) */ 1739 /** 1740 * @} 1741 */ 1742 1743 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update 1744 * @{ 1745 * @brief Constants defining the registers that can be written during a burst 1746 * DMA operation 1747 */ 1748 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 1749 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ 1750 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ 1751 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ 1752 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ 1753 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ 1754 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ 1755 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ 1756 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ 1757 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ 1758 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ 1759 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ 1760 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 1761 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 1762 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 1763 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 1764 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 1765 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 1766 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 1767 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 1768 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 1769 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 1770 /** 1771 * @} 1772 */ 1773 1774 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control 1775 * @{ 1776 * @brief Constants used to enable or disable the burst mode controller 1777 */ 1778 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ 1779 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ 1780 /** 1781 * @} 1782 */ 1783 1784 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control 1785 * @{ 1786 * @brief Constants used to enable or disable a fault channel 1787 */ 1788 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ 1789 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ 1790 /** 1791 * @} 1792 */ 1793 1794 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update 1795 * @{ 1796 * @brief Constants used to force timer registers update 1797 */ 1798 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */ 1799 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */ 1800 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */ 1801 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */ 1802 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */ 1803 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */ 1804 /** 1805 * @} 1806 */ 1807 1808 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset 1809 * @{ 1810 * @brief Constants used to force timer counter reset 1811 */ 1812 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */ 1813 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */ 1814 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */ 1815 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */ 1816 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */ 1817 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */ 1818 /** 1819 * @} 1820 */ 1821 1822 /** @defgroup HRTIM_Output_Level HRTIM Output Level 1823 * @{ 1824 * @brief Constants defining the level of a timer output 1825 */ 1826 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */ 1827 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ 1828 1829 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ 1830 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ 1831 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) 1832 /** 1833 * @} 1834 */ 1835 1836 /** @defgroup HRTIM_Output_State HRTIM Output State 1837 * @{ 1838 * @brief Constants defining the state of a timer output 1839 */ 1840 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or 1841 inactive level as programmed in the crossbar unit */ 1842 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the 1843 outputs are disabled by software or during a burst mode operation */ 1844 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on 1845 FAULTx inputs */ 1846 /** 1847 * @} 1848 */ 1849 1850 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status 1851 * @{ 1852 * @brief Constants defining the operating state of the burst mode controller 1853 */ 1854 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ 1855 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ 1856 /** 1857 * @} 1858 */ 1859 1860 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status 1861 * @{ 1862 * @brief Constants defining on which output the signal is currently applied 1863 * in push-pull mode 1864 */ 1865 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ 1866 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 1867 /** 1868 * @} 1869 */ 1870 1871 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status 1872 * @{ 1873 * @brief Constants defining on which output the signal was applied, in 1874 * push-pull mode balanced fault mode or delayed idle mode, when the 1875 * protection was triggered 1876 */ 1877 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 1878 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 1879 /** 1880 * @} 1881 */ 1882 1883 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable 1884 * @{ 1885 */ 1886 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1887 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ 1888 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ 1889 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ 1890 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */ 1891 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */ 1892 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */ 1893 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */ 1894 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */ 1895 /** 1896 * @} 1897 */ 1898 1899 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable 1900 * @{ 1901 */ 1902 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1903 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ 1904 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ 1905 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ 1906 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */ 1907 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */ 1908 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */ 1909 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */ 1910 /** 1911 * @} 1912 */ 1913 1914 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable 1915 * @{ 1916 */ 1917 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 1918 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ 1919 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ 1920 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ 1921 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */ 1922 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */ 1923 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */ 1924 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */ 1925 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */ 1926 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */ 1927 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */ 1928 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */ 1929 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */ 1930 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */ 1931 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */ 1932 /** 1933 * @} 1934 */ 1935 1936 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag 1937 * @{ 1938 */ 1939 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ 1940 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ 1941 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ 1942 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ 1943 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ 1944 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ 1945 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */ 1946 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ 1947 /** 1948 * @} 1949 */ 1950 1951 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag 1952 * @{ 1953 */ 1954 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ 1955 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ 1956 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ 1957 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ 1958 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ 1959 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ 1960 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ 1961 /** 1962 * @} 1963 */ 1964 1965 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag 1966 * @{ 1967 */ 1968 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ 1969 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ 1970 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ 1971 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ 1972 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ 1973 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ 1974 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ 1975 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ 1976 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ 1977 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ 1978 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ 1979 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ 1980 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */ 1981 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ 1982 /** 1983 * @} 1984 */ 1985 1986 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable 1987 * @{ 1988 */ 1989 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ 1990 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ 1991 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ 1992 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ 1993 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */ 1994 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */ 1995 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */ 1996 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */ 1997 /** 1998 * @} 1999 */ 2000 2001 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable 2002 * @{ 2003 */ 2004 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ 2005 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ 2006 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ 2007 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ 2008 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */ 2009 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */ 2010 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */ 2011 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */ 2012 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */ 2013 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */ 2014 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */ 2015 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */ 2016 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */ 2017 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */ 2018 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */ 2019 /** 2020 * @} 2021 */ 2022 2023 /** 2024 * @} 2025 */ 2026 2027 /* Private macros --------------------------------------------------------*/ 2028 /** @addtogroup HRTIM_Private_Macros 2029 * @{ 2030 */ 2031 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ 2032 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ 2033 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2034 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2035 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2036 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2037 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 2038 2039 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ 2040 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2041 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2042 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2043 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2044 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 2045 2046 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) 2047 2048 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ 2049 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ 2050 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ 2051 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ 2052 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) 2053 2054 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ 2055 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ 2056 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) 2057 2058 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) 2059 2060 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ 2061 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2062 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ 2063 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ 2064 || \ 2065 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2066 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ 2067 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ 2068 || \ 2069 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2070 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ 2071 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ 2072 || \ 2073 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2074 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ 2075 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ 2076 || \ 2077 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2078 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ 2079 ((OUTPUT) == HRTIM_OUTPUT_TE2)))) 2080 2081 #define IS_HRTIM_EVENT(EVENT)\ 2082 (((EVENT) == HRTIM_EVENT_NONE)|| \ 2083 ((EVENT) == HRTIM_EVENT_1) || \ 2084 ((EVENT) == HRTIM_EVENT_2) || \ 2085 ((EVENT) == HRTIM_EVENT_3) || \ 2086 ((EVENT) == HRTIM_EVENT_4) || \ 2087 ((EVENT) == HRTIM_EVENT_5) || \ 2088 ((EVENT) == HRTIM_EVENT_6) || \ 2089 ((EVENT) == HRTIM_EVENT_7) || \ 2090 ((EVENT) == HRTIM_EVENT_8) || \ 2091 ((EVENT) == HRTIM_EVENT_9) || \ 2092 ((EVENT) == HRTIM_EVENT_10)) 2093 2094 #define IS_HRTIM_FAULT(FAULT)\ 2095 (((FAULT) == HRTIM_FAULT_1) || \ 2096 ((FAULT) == HRTIM_FAULT_2) || \ 2097 ((FAULT) == HRTIM_FAULT_3) || \ 2098 ((FAULT) == HRTIM_FAULT_4) || \ 2099 ((FAULT) == HRTIM_FAULT_5)) 2100 2101 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ 2102 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ 2103 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ 2104 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ 2105 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ 2106 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ 2107 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ 2108 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ 2109 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) 2110 2111 #define IS_HRTIM_MODE(MODE)\ 2112 (((MODE) == HRTIM_MODE_CONTINUOUS) || \ 2113 ((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2114 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2115 2116 #define IS_HRTIM_MODE_ONEPULSE(MODE)\ 2117 (((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2118 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2119 2120 2121 #define IS_HRTIM_HALFMODE(HALFMODE)\ 2122 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ 2123 ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) 2124 2125 #define IS_HRTIM_SYNCSTART(SYNCSTART)\ 2126 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ 2127 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) 2128 2129 #define IS_HRTIM_SYNCRESET(SYNCRESET)\ 2130 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ 2131 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) 2132 2133 #define IS_HRTIM_DACSYNC(DACSYNC)\ 2134 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ 2135 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ 2136 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ 2137 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) 2138 2139 #define IS_HRTIM_PRELOAD(PRELOAD)\ 2140 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ 2141 ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) 2142 2143 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ 2144 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2145 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2146 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) 2147 2148 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ 2149 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2150 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2151 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ 2152 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ 2153 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ 2154 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ 2155 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ 2156 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ 2157 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) 2158 2159 #define IS_HRTIM_TIMERBURSTMODE(MODE) \ 2160 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ 2161 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) 2162 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ 2163 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ 2164 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) 2165 2166 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ 2167 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ 2168 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) 2169 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) 2170 2171 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ 2172 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ 2173 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) 2174 2175 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ 2176 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ 2177 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ 2178 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ 2179 || \ 2180 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2181 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) 2182 2183 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ 2184 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ 2185 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ 2186 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ 2187 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ 2188 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ 2189 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ 2190 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ 2191 || \ 2192 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2193 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ 2194 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) 2195 2196 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) 2197 2198 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U) 2199 2200 2201 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ 2202 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ 2203 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) 2204 2205 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ 2206 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2207 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2208 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2209 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) 2210 2211 /* Auto delayed mode is only available for compare units 2 and 4U */ 2212 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ 2213 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ 2214 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2215 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2216 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2217 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ 2218 || \ 2219 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ 2220 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2221 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2222 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2223 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) 2224 2225 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ 2226 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ 2227 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) 2228 2229 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) 2230 2231 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ 2232 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ 2233 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ 2234 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ 2235 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ 2236 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ 2237 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ 2238 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ 2239 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ 2240 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ 2241 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ 2242 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ 2243 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ 2244 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ 2245 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ 2246 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ 2247 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ 2248 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ 2249 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ 2250 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ 2251 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ 2252 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ 2253 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ 2254 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ 2255 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ 2256 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ 2257 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ 2258 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ 2259 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ 2260 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ 2261 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ 2262 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ 2263 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) 2264 2265 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ 2266 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ 2267 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ 2268 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ 2269 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ 2270 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ 2271 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ 2272 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ 2273 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ 2274 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ 2275 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ 2276 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ 2277 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ 2278 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ 2279 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ 2280 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ 2281 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ 2282 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ 2283 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ 2284 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ 2285 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ 2286 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ 2287 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ 2288 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ 2289 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ 2290 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ 2291 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ 2292 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ 2293 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ 2294 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ 2295 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ 2296 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ 2297 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) 2298 2299 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ 2300 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ 2301 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) 2302 2303 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ 2304 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ 2305 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) 2306 2307 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ 2308 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ 2309 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ 2310 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ 2311 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) 2312 2313 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ 2314 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ 2315 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) 2316 2317 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ 2318 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ 2319 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) 2320 2321 2322 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ 2323 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ 2324 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ 2325 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ 2326 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ 2327 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ 2328 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ 2329 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ 2330 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ 2331 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ 2332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ 2333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ 2334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ 2335 || \ 2336 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2337 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2342 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2343 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2344 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2347 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2348 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2349 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2350 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2351 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2352 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2353 || \ 2354 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2355 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2356 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2357 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2358 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2359 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2360 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2361 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2362 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2363 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2364 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2365 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2366 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2367 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2368 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2369 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2370 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2371 || \ 2372 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2373 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2374 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2375 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2376 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2377 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2378 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2379 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2380 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2381 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2382 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2383 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2384 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 2385 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2386 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2387 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2388 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2389 || \ 2390 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2391 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2392 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2393 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2394 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2395 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2396 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2397 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2398 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2399 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2400 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2401 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2402 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2403 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 2404 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 2405 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 2406 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 2407 || \ 2408 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2409 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 2410 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 2411 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 2412 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 2413 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 2414 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 2415 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 2416 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 2417 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 2418 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 2419 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 2420 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 2421 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 2422 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 2423 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 2424 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) 2425 2426 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ 2427 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ 2428 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ 2429 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ 2430 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ 2431 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ 2432 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ 2433 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ 2434 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ 2435 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ 2436 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ 2437 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ 2438 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ 2439 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ 2440 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ 2441 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ 2442 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) 2443 2444 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ 2445 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ 2446 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) 2447 2448 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ 2449 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ 2450 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ 2451 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ 2452 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ 2453 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ 2454 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ 2455 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ 2456 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) 2457 2458 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ 2459 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ 2460 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) 2461 2462 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ 2463 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ 2464 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) 2465 2466 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ 2467 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ 2468 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) 2469 2470 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ 2471 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ 2472 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) 2473 2474 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ 2475 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ 2476 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) 2477 2478 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ 2479 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ 2480 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) 2481 2482 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ 2483 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ 2484 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ 2485 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ 2486 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ 2487 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ 2488 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ 2489 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ 2490 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ 2491 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ 2492 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ 2493 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ 2494 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ 2495 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ 2496 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ 2497 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ 2498 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) 2499 2500 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ 2501 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ 2502 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ 2503 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ 2504 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ 2505 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ 2506 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ 2507 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ 2508 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) 2509 2510 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ 2511 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ 2512 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ 2513 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ 2514 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ 2515 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ 2516 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ 2517 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ 2518 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ 2519 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ 2520 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ 2521 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ 2522 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ 2523 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ 2524 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ 2525 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ 2526 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) 2527 2528 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ 2529 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ 2530 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ 2531 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) 2532 2533 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ 2534 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ 2535 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ 2536 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ 2537 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) 2538 2539 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ 2540 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ 2541 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ 2542 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) 2543 2544 #define IS_HRTIM_EVENTSRC(EVENTSRC)\ 2545 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ 2546 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ 2547 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ 2548 ((EVENTSRC) == HRTIM_EVENTSRC_4)) 2549 2550 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ 2551 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ 2552 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ 2553 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ 2554 || \ 2555 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 2556 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ 2557 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) 2558 2559 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ 2560 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ 2561 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 2562 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ 2563 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) 2564 2565 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ 2566 (((((EVENT) == HRTIM_EVENT_1) || \ 2567 ((EVENT) == HRTIM_EVENT_2) || \ 2568 ((EVENT) == HRTIM_EVENT_3) || \ 2569 ((EVENT) == HRTIM_EVENT_4) || \ 2570 ((EVENT) == HRTIM_EVENT_5)) && \ 2571 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ 2572 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ 2573 || \ 2574 (((EVENT) == HRTIM_EVENT_6) || \ 2575 ((EVENT) == HRTIM_EVENT_7) || \ 2576 ((EVENT) == HRTIM_EVENT_8) || \ 2577 ((EVENT) == HRTIM_EVENT_9) || \ 2578 ((EVENT) == HRTIM_EVENT_10))) 2579 2580 2581 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ 2582 ((((EVENT) == HRTIM_EVENT_1) || \ 2583 ((EVENT) == HRTIM_EVENT_2) || \ 2584 ((EVENT) == HRTIM_EVENT_3) || \ 2585 ((EVENT) == HRTIM_EVENT_4) || \ 2586 ((EVENT) == HRTIM_EVENT_5)) \ 2587 || \ 2588 ((((EVENT) == HRTIM_EVENT_6) || \ 2589 ((EVENT) == HRTIM_EVENT_7) || \ 2590 ((EVENT) == HRTIM_EVENT_8) || \ 2591 ((EVENT) == HRTIM_EVENT_9) || \ 2592 ((EVENT) == HRTIM_EVENT_10)) && \ 2593 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ 2594 ((FILTER) == HRTIM_EVENTFILTER_1) || \ 2595 ((FILTER) == HRTIM_EVENTFILTER_2) || \ 2596 ((FILTER) == HRTIM_EVENTFILTER_3) || \ 2597 ((FILTER) == HRTIM_EVENTFILTER_4) || \ 2598 ((FILTER) == HRTIM_EVENTFILTER_5) || \ 2599 ((FILTER) == HRTIM_EVENTFILTER_6) || \ 2600 ((FILTER) == HRTIM_EVENTFILTER_7) || \ 2601 ((FILTER) == HRTIM_EVENTFILTER_8) || \ 2602 ((FILTER) == HRTIM_EVENTFILTER_9) || \ 2603 ((FILTER) == HRTIM_EVENTFILTER_10) || \ 2604 ((FILTER) == HRTIM_EVENTFILTER_11) || \ 2605 ((FILTER) == HRTIM_EVENTFILTER_12) || \ 2606 ((FILTER) == HRTIM_EVENTFILTER_13) || \ 2607 ((FILTER) == HRTIM_EVENTFILTER_14) || \ 2608 ((FILTER) == HRTIM_EVENTFILTER_15)))) 2609 2610 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ 2611 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ 2612 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ 2613 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ 2614 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) 2615 2616 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ 2617 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ 2618 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) 2619 2620 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ 2621 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ 2622 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) 2623 2624 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ 2625 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ 2626 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) 2627 2628 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ 2629 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ 2630 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ 2631 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ 2632 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ 2633 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ 2634 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ 2635 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ 2636 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ 2637 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ 2638 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ 2639 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ 2640 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ 2641 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ 2642 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ 2643 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ 2644 ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) 2645 2646 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ 2647 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ 2648 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) 2649 2650 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ 2651 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ 2652 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ 2653 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ 2654 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) 2655 2656 #define IS_HRTIM_BURSTMODE(BURSTMODE)\ 2657 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ 2658 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) 2659 2660 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ 2661 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ 2662 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ 2663 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ 2664 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ 2665 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ 2666 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ 2667 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ 2668 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ 2669 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ 2670 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) 2671 2672 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ 2673 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ 2674 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ 2675 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ 2676 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ 2677 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ 2678 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ 2679 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ 2680 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ 2681 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ 2682 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ 2683 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ 2684 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ 2685 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ 2686 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ 2687 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ 2688 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) 2689 2690 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ 2691 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ 2692 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) 2693 2694 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ 2695 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ 2696 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ 2697 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ 2698 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ 2699 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ 2700 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ 2701 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ 2702 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ 2703 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ 2704 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ 2705 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ 2706 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ 2707 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ 2708 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ 2709 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ 2710 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ 2711 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ 2712 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ 2713 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ 2714 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ 2715 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ 2716 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ 2717 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ 2718 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ 2719 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ 2720 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ 2721 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ 2722 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ 2723 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ 2724 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ 2725 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ 2726 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) 2727 2728 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ 2729 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ 2730 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ 2731 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ 2732 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ 2733 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ 2734 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) 2735 2736 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ 2737 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ 2738 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ 2739 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ 2740 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ 2741 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) 2742 2743 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ 2744 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ 2745 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2746 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2747 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2748 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 2749 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) 2750 2751 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ 2752 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ 2753 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) 2754 2755 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) 2756 2757 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U) 2758 2759 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U) 2760 2761 2762 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) 2763 2764 2765 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) 2766 2767 2768 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) 2769 2770 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U) 2771 /** 2772 * @} 2773 */ 2774 2775 /* Exported macros -----------------------------------------------------------*/ 2776 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros 2777 * @{ 2778 */ 2779 2780 /** @brief Reset HRTIM handle state 2781 * @param __HANDLE__ HRTIM handle. 2782 * @retval None 2783 */ 2784 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 2785 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ 2786 (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ 2787 (__HANDLE__)->MspInitCallback = NULL; \ 2788 (__HANDLE__)->MspDeInitCallback = NULL; \ 2789 } while(0) 2790 #else 2791 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) 2792 #endif 2793 2794 /** @brief Enables or disables the timer counter(s) 2795 * @param __HANDLE__ specifies the HRTIM Handle. 2796 * @param __TIMERS__ timers to enable/disable 2797 * This parameter can be any combinations of the following values: 2798 * @arg HRTIM_TIMERID_MASTER: Master timer identifier 2799 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier 2800 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier 2801 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier 2802 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier 2803 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier 2804 * @retval None 2805 */ 2806 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__)) 2807 2808 /* The counter of a timing unit is disabled only if all the timer outputs */ 2809 /* are disabled and no capture is configured */ 2810 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) 2811 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) 2812 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) 2813 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) 2814 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) 2815 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ 2816 do {\ 2817 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ 2818 {\ 2819 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ 2820 }\ 2821 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 2822 {\ 2823 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ 2824 {\ 2825 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ 2826 }\ 2827 }\ 2828 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 2829 {\ 2830 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ 2831 {\ 2832 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ 2833 }\ 2834 }\ 2835 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 2836 {\ 2837 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ 2838 {\ 2839 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ 2840 }\ 2841 }\ 2842 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 2843 {\ 2844 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ 2845 {\ 2846 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ 2847 }\ 2848 }\ 2849 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 2850 {\ 2851 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ 2852 {\ 2853 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ 2854 }\ 2855 }\ 2856 } while(0U) 2857 2858 2859 /** @brief Enables or disables the specified HRTIM common interrupts. 2860 * @param __HANDLE__ specifies the HRTIM Handle. 2861 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2862 * This parameter can be one of the following values: 2863 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 2864 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 2865 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable 2866 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable 2867 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable 2868 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 2869 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 2870 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 2871 * @retval None 2872 */ 2873 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__)) 2874 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__)) 2875 2876 /** @brief Enables or disables the specified HRTIM Master timer interrupts. 2877 * @param __HANDLE__ specifies the HRTIM Handle. 2878 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2879 * This parameter can be one of the following values: 2880 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2881 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2882 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2883 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2884 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2885 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2886 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2887 * @retval None 2888 */ 2889 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) 2890 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) 2891 2892 /** @brief Enables or disables the specified HRTIM Timerx interrupts. 2893 * @param __HANDLE__ specifies the HRTIM Handle. 2894 * @param __TIMER__ specified the timing unit (Timer A to E) 2895 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 2896 * This parameter can be one of the following values: 2897 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 2898 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 2899 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 2900 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 2901 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 2902 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 2903 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 2904 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 2905 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 2906 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 2907 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 2908 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 2909 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 2910 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 2911 * @retval None 2912 */ 2913 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__)) 2914 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__)) 2915 2916 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled. 2917 * @param __HANDLE__ specifies the HRTIM Handle. 2918 * @param __INTERRUPT__ specifies the interrupt source to check. 2919 * This parameter can be one of the following values: 2920 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 2921 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 2922 * @arg HRTIM_IT_FLT3: Fault 3 enable 2923 * @arg HRTIM_IT_FLT4: Fault 4 enable 2924 * @arg HRTIM_IT_FLT5: Fault 5 enable 2925 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 2926 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 2927 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 2928 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2929 */ 2930 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2931 2932 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. 2933 * @param __HANDLE__ specifies the HRTIM Handle. 2934 * @param __INTERRUPT__ specifies the interrupt source to check. 2935 * This parameter can be one of the following values: 2936 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2937 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2938 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2939 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2940 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2941 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2942 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2943 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2944 */ 2945 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2946 2947 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. 2948 * @param __HANDLE__ specifies the HRTIM Handle. 2949 * @param __TIMER__ specified the timing unit (Timer A to E) 2950 * @param __INTERRUPT__ specifies the interrupt source to check. 2951 * This parameter can be one of the following values: 2952 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 2953 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 2954 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 2955 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 2956 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 2957 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 2958 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 2959 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 2960 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 2961 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 2962 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 2963 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 2964 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 2965 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 2966 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 2967 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 2968 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 2969 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 2970 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 2971 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 2972 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 2973 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 2974 */ 2975 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 2976 2977 /** @brief Clears the specified HRTIM common pending flag. 2978 * @param __HANDLE__ specifies the HRTIM Handle. 2979 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2980 * This parameter can be one of the following values: 2981 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag 2982 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag 2983 * @arg HRTIM_IT_FLT3: Fault 3 clear flag 2984 * @arg HRTIM_IT_FLT4: Fault 4 clear flag 2985 * @arg HRTIM_IT_FLT5: Fault 5 clear flag 2986 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag 2987 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag 2988 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag 2989 * @retval None 2990 */ 2991 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 2992 2993 /** @brief Clears the specified HRTIM Master pending flag. 2994 * @param __HANDLE__ specifies the HRTIM Handle. 2995 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 2996 * This parameter can be one of the following values: 2997 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag 2998 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag 2999 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag 3000 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag 3001 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag 3002 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag 3003 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag 3004 * @retval None 3005 */ 3006 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) 3007 3008 /** @brief Clears the specified HRTIM Timerx pending flag. 3009 * @param __HANDLE__ specifies the HRTIM Handle. 3010 * @param __TIMER__ specified the timing unit (Timer A to E) 3011 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 3012 * This parameter can be one of the following values: 3013 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag 3014 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag 3015 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag 3016 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag 3017 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag 3018 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag 3019 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag 3020 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag 3021 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag 3022 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag 3023 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag 3024 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag 3025 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag 3026 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag 3027 * @retval None 3028 */ 3029 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) 3030 3031 /* DMA HANDLING */ 3032 /** @brief Enables or disables the specified HRTIM Master timer DMA requests. 3033 * @param __HANDLE__ specifies the HRTIM Handle. 3034 * @param __DMA__ specifies the DMA request to enable or disable. 3035 * This parameter can be one of the following values: 3036 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable 3037 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable 3038 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable 3039 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable 3040 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable 3041 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable 3042 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable 3043 * @retval None 3044 */ 3045 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__)) 3046 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__)) 3047 3048 /** @brief Enables or disables the specified HRTIM Timerx DMA requests. 3049 * @param __HANDLE__ specifies the HRTIM Handle. 3050 * @param __TIMER__ specified the timing unit (Timer A to E) 3051 * @param __DMA__ specifies the DMA request to enable or disable. 3052 * This parameter can be one of the following values: 3053 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable 3054 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable 3055 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable 3056 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable 3057 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable 3058 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable 3059 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable 3060 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable 3061 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable 3062 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable 3063 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable 3064 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable 3065 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable 3066 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable 3067 * @retval None 3068 */ 3069 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) 3070 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) 3071 3072 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) 3073 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) 3074 3075 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) 3076 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) 3077 3078 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) 3079 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) 3080 3081 /** @brief Sets the HRTIM timer Counter Register value on runtime 3082 * @param __HANDLE__ HRTIM Handle. 3083 * @param __TIMER__ HRTIM timer 3084 * This parameter can be one of the following values: 3085 * @arg 0x5 for master timer 3086 * @arg 0x0 to 0x4 for timers A to E 3087 * @param __COUNTER__ specifies the Counter Register new value. 3088 * @retval None 3089 */ 3090 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \ 3091 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\ 3092 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__))) 3093 3094 /** @brief Gets the HRTIM timer Counter Register value on runtime 3095 * @param __HANDLE__ HRTIM Handle. 3096 * @param __TIMER__ HRTIM timer 3097 * This parameter can be one of the following values: 3098 * @arg 0x5 for master timer 3099 * @arg 0x0 to 0x4 for timers A to E 3100 * @retval HRTIM timer Counter Register value 3101 */ 3102 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \ 3103 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\ 3104 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR)) 3105 3106 /** @brief Sets the HRTIM timer Period value on runtime 3107 * @param __HANDLE__ HRTIM Handle. 3108 * @param __TIMER__ HRTIM timer 3109 * This parameter can be one of the following values: 3110 * @arg 0x5 for master timer 3111 * @arg 0x0 to 0x4 for timers A to E 3112 * @param __PERIOD__ specifies the Period Register new value. 3113 * @retval None 3114 */ 3115 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \ 3116 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\ 3117 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__))) 3118 3119 /** @brief Gets the HRTIM timer Period Register value on runtime 3120 * @param __HANDLE__ HRTIM Handle. 3121 * @param __TIMER__ HRTIM timer 3122 * This parameter can be one of the following values: 3123 * @arg 0x5 for master timer 3124 * @arg 0x0 to 0x4 for timers A to E 3125 * @retval timer Period Register 3126 */ 3127 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \ 3128 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\ 3129 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR)) 3130 3131 /** @brief Sets the HRTIM timer clock prescaler value on runtime 3132 * @param __HANDLE__ HRTIM Handle. 3133 * @param __TIMER__ HRTIM timer 3134 * This parameter can be one of the following values: 3135 * @arg 0x5 for master timer 3136 * @arg 0x0 to 0x4 for timers A to E 3137 * @param __PRESCALER__ specifies the clock prescaler new value. 3138 * This parameter can be one of the following values: 3139 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) 3140 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) 3141 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) 3142 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) 3143 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) 3144 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) 3145 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) 3146 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) 3147 * @retval None 3148 */ 3149 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \ 3150 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\ 3151 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__)))) 3152 3153 /** @brief Gets the HRTIM timer clock prescaler value on runtime 3154 * @param __HANDLE__ HRTIM Handle. 3155 * @param __TIMER__ HRTIM timer 3156 * This parameter can be one of the following values: 3157 * @arg 0x5 for master timer 3158 * @arg 0x0 to 0x4 for timers A to E 3159 * @retval timer clock prescaler value 3160 */ 3161 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \ 3162 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\ 3163 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC)) 3164 3165 /** @brief Sets the HRTIM timer Compare Register value on runtime 3166 * @param __HANDLE__ HRTIM Handle. 3167 * @param __TIMER__ HRTIM timer 3168 * This parameter can be one of the following values: 3169 * @arg 0x0 to 0x4 for timers A to E 3170 * @param __COMPAREUNIT__ timer compare unit 3171 * This parameter can be one of the following values: 3172 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 3173 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 3174 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 3175 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 3176 * @param __COMPARE__ specifies the Compare new value. 3177 * @retval None 3178 */ 3179 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ 3180 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 3181 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ 3182 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ 3183 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ 3184 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ 3185 : \ 3186 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ 3187 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ 3188 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ 3189 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) 3190 3191 /** @brief Gets the HRTIM timer Compare Register value on runtime 3192 * @param __HANDLE__ HRTIM Handle. 3193 * @param __TIMER__ HRTIM timer 3194 * This parameter can be one of the following values: 3195 * @arg 0x0 to 0x4 for timers A to E 3196 * @param __COMPAREUNIT__ timer compare unit 3197 * This parameter can be one of the following values: 3198 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 3199 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 3200 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 3201 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 3202 * @retval Compare value 3203 */ 3204 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ 3205 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 3206 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ 3207 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ 3208 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ 3209 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ 3210 : \ 3211 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ 3212 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ 3213 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ 3214 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) 3215 3216 /** 3217 * @} 3218 */ 3219 3220 /* Exported functions --------------------------------------------------------*/ 3221 /** @addtogroup HRTIM_Exported_Functions 3222 * @{ 3223 */ 3224 3225 /** @addtogroup HRTIM_Exported_Functions_Group1 3226 * @{ 3227 */ 3228 3229 /* Initialization and Configuration functions ********************************/ 3230 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); 3231 3232 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); 3233 3234 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); 3235 3236 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); 3237 3238 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, 3239 uint32_t TimerIdx, 3240 const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); 3241 3242 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, 3243 uint32_t CalibrationRate); 3244 3245 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim, 3246 uint32_t CalibrationRate); 3247 3248 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, 3249 uint32_t Timeout); 3250 3251 /** 3252 * @} 3253 */ 3254 3255 /** @addtogroup HRTIM_Exported_Functions_Group2 3256 * @{ 3257 */ 3258 3259 /* Simple time base related functions *****************************************/ 3260 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, 3261 uint32_t TimerIdx); 3262 3263 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, 3264 uint32_t TimerIdx); 3265 3266 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, 3267 uint32_t TimerIdx); 3268 3269 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, 3270 uint32_t TimerIdx); 3271 3272 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3273 uint32_t TimerIdx, 3274 uint32_t SrcAddr, 3275 uint32_t DestAddr, 3276 uint32_t Length); 3277 3278 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3279 uint32_t TimerIdx); 3280 3281 /** 3282 * @} 3283 */ 3284 3285 /** @addtogroup HRTIM_Exported_Functions_Group3 3286 * @{ 3287 */ 3288 /* Simple output compare related functions ************************************/ 3289 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3290 uint32_t TimerIdx, 3291 uint32_t OCChannel, 3292 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); 3293 3294 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, 3295 uint32_t TimerIdx, 3296 uint32_t OCChannel); 3297 3298 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, 3299 uint32_t TimerIdx, 3300 uint32_t OCChannel); 3301 3302 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, 3303 uint32_t TimerIdx, 3304 uint32_t OCChannel); 3305 3306 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, 3307 uint32_t TimerIdx, 3308 uint32_t OCChannel); 3309 3310 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3311 uint32_t TimerIdx, 3312 uint32_t OCChannel, 3313 uint32_t SrcAddr, 3314 uint32_t DestAddr, 3315 uint32_t Length); 3316 3317 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3318 uint32_t TimerIdx, 3319 uint32_t OCChannel); 3320 3321 /** 3322 * @} 3323 */ 3324 3325 /** @addtogroup HRTIM_Exported_Functions_Group4 3326 * @{ 3327 */ 3328 /* Simple PWM output related functions ****************************************/ 3329 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3330 uint32_t TimerIdx, 3331 uint32_t PWMChannel, 3332 const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); 3333 3334 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, 3335 uint32_t TimerIdx, 3336 uint32_t PWMChannel); 3337 3338 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, 3339 uint32_t TimerIdx, 3340 uint32_t PWMChannel); 3341 3342 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, 3343 uint32_t TimerIdx, 3344 uint32_t PWMChannel); 3345 3346 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, 3347 uint32_t TimerIdx, 3348 uint32_t PWMChannel); 3349 3350 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3351 uint32_t TimerIdx, 3352 uint32_t PWMChannel, 3353 uint32_t SrcAddr, 3354 uint32_t DestAddr, 3355 uint32_t Length); 3356 3357 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3358 uint32_t TimerIdx, 3359 uint32_t PWMChannel); 3360 3361 /** 3362 * @} 3363 */ 3364 3365 /** @addtogroup HRTIM_Exported_Functions_Group5 3366 * @{ 3367 */ 3368 /* Simple capture related functions *******************************************/ 3369 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3370 uint32_t TimerIdx, 3371 uint32_t CaptureChannel, 3372 const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); 3373 3374 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, 3375 uint32_t TimerIdx, 3376 uint32_t CaptureChannel); 3377 3378 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, 3379 uint32_t TimerIdx, 3380 uint32_t CaptureChannel); 3381 3382 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, 3383 uint32_t TimerIdx, 3384 uint32_t CaptureChannel); 3385 3386 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, 3387 uint32_t TimerIdx, 3388 uint32_t CaptureChannel); 3389 3390 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3391 uint32_t TimerIdx, 3392 uint32_t CaptureChannel, 3393 uint32_t SrcAddr, 3394 uint32_t DestAddr, 3395 uint32_t Length); 3396 3397 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3398 uint32_t TimerIdx, 3399 uint32_t CaptureChannel); 3400 3401 /** 3402 * @} 3403 */ 3404 3405 /** @addtogroup HRTIM_Exported_Functions_Group6 3406 * @{ 3407 */ 3408 /* Simple one pulse related functions *****************************************/ 3409 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, 3410 uint32_t TimerIdx, 3411 uint32_t OnePulseChannel, 3412 const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); 3413 3414 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, 3415 uint32_t TimerIdx, 3416 uint32_t OnePulseChannel); 3417 3418 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, 3419 uint32_t TimerIdx, 3420 uint32_t OnePulseChannel); 3421 3422 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, 3423 uint32_t TimerIdx, 3424 uint32_t OnePulseChannel); 3425 3426 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, 3427 uint32_t TimerIdx, 3428 uint32_t OnePulseChannel); 3429 3430 /** 3431 * @} 3432 */ 3433 3434 /** @addtogroup HRTIM_Exported_Functions_Group7 3435 * @{ 3436 */ 3437 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, 3438 const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); 3439 3440 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, 3441 uint32_t Event, 3442 const HRTIM_EventCfgTypeDef* pEventCfg); 3443 3444 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 3445 uint32_t Prescaler); 3446 3447 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, 3448 uint32_t Fault, 3449 const HRTIM_FaultCfgTypeDef* pFaultCfg); 3450 3451 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 3452 uint32_t Prescaler); 3453 3454 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, 3455 uint32_t Faults, 3456 uint32_t Enable); 3457 3458 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, 3459 uint32_t ADCTrigger, 3460 const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); 3461 3462 /** 3463 * @} 3464 */ 3465 3466 /** @addtogroup HRTIM_Exported_Functions_Group8 3467 * @{ 3468 */ 3469 /* Waveform related functions *************************************************/ 3470 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, 3471 uint32_t TimerIdx, 3472 const HRTIM_TimerCfgTypeDef * pTimerCfg); 3473 3474 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, 3475 uint32_t TimerIdx, 3476 uint32_t CompareUnit, 3477 const HRTIM_CompareCfgTypeDef* pCompareCfg); 3478 3479 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, 3480 uint32_t TimerIdx, 3481 uint32_t CaptureUnit, 3482 const HRTIM_CaptureCfgTypeDef* pCaptureCfg); 3483 3484 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, 3485 uint32_t TimerIdx, 3486 uint32_t Output, 3487 const HRTIM_OutputCfgTypeDef * pOutputCfg); 3488 3489 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 3490 uint32_t TimerIdx, 3491 uint32_t Output, 3492 uint32_t OutputLevel); 3493 3494 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, 3495 uint32_t TimerIdx, 3496 uint32_t Event, 3497 const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); 3498 3499 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, 3500 uint32_t TimerIdx, 3501 const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); 3502 3503 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, 3504 uint32_t TimerIdx, 3505 const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); 3506 3507 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, 3508 uint32_t TimerIdx, 3509 uint32_t RegistersToUpdate); 3510 3511 3512 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, 3513 uint32_t Timers); 3514 3515 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, 3516 uint32_t Timers); 3517 3518 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, 3519 uint32_t Timers); 3520 3521 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, 3522 uint32_t Timers); 3523 3524 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, 3525 uint32_t Timers); 3526 3527 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, 3528 uint32_t Timers); 3529 3530 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, 3531 uint32_t OutputsToStart); 3532 3533 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, 3534 uint32_t OutputsToStop); 3535 3536 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, 3537 uint32_t Enable); 3538 3539 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim); 3540 3541 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, 3542 uint32_t TimerIdx, 3543 uint32_t CaptureUnit); 3544 3545 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, 3546 uint32_t Timers); 3547 3548 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, 3549 uint32_t Timers); 3550 3551 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, 3552 uint32_t TimerIdx, 3553 uint32_t BurstBufferAddress, 3554 uint32_t BurstBufferLength); 3555 3556 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, 3557 uint32_t Timers); 3558 3559 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, 3560 uint32_t Timers); 3561 3562 /** 3563 * @} 3564 */ 3565 3566 /** @addtogroup HRTIM_Exported_Functions_Group9 3567 * @{ 3568 */ 3569 /* HRTIM peripheral state functions */ 3570 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); 3571 3572 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, 3573 uint32_t TimerIdx, 3574 uint32_t CaptureUnit); 3575 3576 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, 3577 uint32_t TimerIdx, 3578 uint32_t Output); 3579 3580 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, 3581 uint32_t TimerIdx, 3582 uint32_t Output); 3583 3584 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, 3585 uint32_t TimerIdx, 3586 uint32_t Output); 3587 3588 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim); 3589 3590 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 3591 uint32_t TimerIdx); 3592 3593 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 3594 uint32_t TimerIdx); 3595 3596 /** 3597 * @} 3598 */ 3599 3600 /** @addtogroup HRTIM_Exported_Functions_Group10 3601 * @{ 3602 */ 3603 /* IRQ handler */ 3604 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, 3605 uint32_t TimerIdx); 3606 3607 /* HRTIM events related callback functions */ 3608 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim); 3609 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim); 3610 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim); 3611 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim); 3612 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim); 3613 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim); 3614 void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim); 3615 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim); 3616 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); 3617 3618 /* Timer events related callback functions */ 3619 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, 3620 uint32_t TimerIdx); 3621 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, 3622 uint32_t TimerIdx); 3623 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, 3624 uint32_t TimerIdx); 3625 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, 3626 uint32_t TimerIdx); 3627 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, 3628 uint32_t TimerIdx); 3629 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, 3630 uint32_t TimerIdx); 3631 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, 3632 uint32_t TimerIdx); 3633 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, 3634 uint32_t TimerIdx); 3635 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, 3636 uint32_t TimerIdx); 3637 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, 3638 uint32_t TimerIdx); 3639 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, 3640 uint32_t TimerIdx); 3641 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, 3642 uint32_t TimerIdx); 3643 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, 3644 uint32_t TimerIdx); 3645 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, 3646 uint32_t TimerIdx); 3647 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, 3648 uint32_t TimerIdx); 3649 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); 3650 3651 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 3652 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, 3653 HAL_HRTIM_CallbackIDTypeDef CallbackID, 3654 pHRTIM_CallbackTypeDef pCallback); 3655 3656 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 3657 HAL_HRTIM_CallbackIDTypeDef CallbackID); 3658 3659 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 3660 HAL_HRTIM_CallbackIDTypeDef CallbackID, 3661 pHRTIM_TIMxCallbackTypeDef pCallback); 3662 3663 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 3664 HAL_HRTIM_CallbackIDTypeDef CallbackID); 3665 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 3666 3667 /** 3668 * @} 3669 */ 3670 3671 /** 3672 * @} 3673 */ 3674 3675 /** 3676 * @} 3677 */ 3678 3679 /** 3680 * @} 3681 */ 3682 3683 #endif /* HRTIM1 */ 3684 3685 #ifdef __cplusplus 3686 } 3687 #endif 3688 3689 #endif /* STM32F3xx_HAL_HRTIM_H */ 3690
