1 /** 2 ****************************************************************************** 3 * @file stm32f2xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file in 13 * the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef __STM32F2xx_HAL_DMA_H 21 #define __STM32F2xx_HAL_DMA_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32f2xx_hal_def.h" 29 30 /** @addtogroup STM32F2xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup DMA 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @brief DMA Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief DMA Configuration Structure definition 47 */ 48 typedef struct 49 { 50 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 51 This parameter can be a value of @ref DMA_Channel_selection */ 52 53 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 54 from memory to memory or from peripheral to memory. 55 This parameter can be a value of @ref DMA_Data_transfer_direction */ 56 57 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 58 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 59 60 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 61 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 62 63 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 64 This parameter can be a value of @ref DMA_Peripheral_data_size */ 65 66 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 67 This parameter can be a value of @ref DMA_Memory_data_size */ 68 69 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 70 This parameter can be a value of @ref DMA_mode 71 @note The circular buffer mode cannot be used if the memory-to-memory 72 data transfer is configured on the selected Stream */ 73 74 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 75 This parameter can be a value of @ref DMA_Priority_level */ 76 77 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 78 This parameter can be a value of @ref DMA_FIFO_direct_mode 79 @note The Direct mode (FIFO mode disabled) cannot be used if the 80 memory-to-memory data transfer is configured on the selected stream */ 81 82 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 83 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 84 85 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 86 It specifies the amount of data to be transferred in a single non interruptible 87 transaction. 88 This parameter can be a value of @ref DMA_Memory_burst 89 @note The burst mode is possible only if the address Increment mode is enabled. */ 90 91 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 92 It specifies the amount of data to be transferred in a single non interruptible 93 transaction. 94 This parameter can be a value of @ref DMA_Peripheral_burst 95 @note The burst mode is possible only if the address Increment mode is enabled. */ 96 }DMA_InitTypeDef; 97 98 99 /** 100 * @brief HAL DMA State structures definition 101 */ 102 typedef enum 103 { 104 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 105 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 106 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 107 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 108 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 109 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ 110 }HAL_DMA_StateTypeDef; 111 112 /** 113 * @brief HAL DMA Error Code structure definition 114 */ 115 typedef enum 116 { 117 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 118 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 119 }HAL_DMA_LevelCompleteTypeDef; 120 121 /** 122 * @brief HAL DMA Error Code structure definition 123 */ 124 typedef enum 125 { 126 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 127 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 128 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 129 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 130 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 131 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 132 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 133 }HAL_DMA_CallbackIDTypeDef; 134 135 /** 136 * @brief DMA handle Structure definition 137 */ 138 typedef struct __DMA_HandleTypeDef 139 { 140 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 141 142 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 143 144 HAL_LockTypeDef Lock; /*!< DMA locking object */ 145 146 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 147 148 void *Parent; /*!< Parent object state */ 149 150 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 151 152 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 153 154 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 155 156 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 157 158 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 159 160 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 161 162 __IO uint32_t ErrorCode; /*!< DMA Error code */ 163 164 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 165 166 uint32_t StreamIndex; /*!< DMA Stream Index */ 167 168 }DMA_HandleTypeDef; 169 170 /** 171 * @} 172 */ 173 174 /* Exported constants --------------------------------------------------------*/ 175 176 /** @defgroup DMA_Exported_Constants DMA Exported Constants 177 * @brief DMA Exported constants 178 * @{ 179 */ 180 181 /** @defgroup DMA_Error_Code DMA Error Code 182 * @brief DMA Error Code 183 * @{ 184 */ 185 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 186 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 187 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ 188 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ 189 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 190 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 191 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ 192 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 193 /** 194 * @} 195 */ 196 197 /** @defgroup DMA_Channel_selection DMA Channel selection 198 * @brief DMA channel selection 199 * @{ 200 */ 201 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 202 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ 203 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ 204 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ 205 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ 206 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ 207 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ 208 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ 209 /** 210 * @} 211 */ 212 213 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 214 * @brief DMA data transfer direction 215 * @{ 216 */ 217 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 218 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 219 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 220 /** 221 * @} 222 */ 223 224 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 225 * @brief DMA peripheral incremented mode 226 * @{ 227 */ 228 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 229 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ 230 /** 231 * @} 232 */ 233 234 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 235 * @brief DMA memory incremented mode 236 * @{ 237 */ 238 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 239 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ 240 /** 241 * @} 242 */ 243 244 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 245 * @brief DMA peripheral data size 246 * @{ 247 */ 248 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 249 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 250 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 251 /** 252 * @} 253 */ 254 255 /** @defgroup DMA_Memory_data_size DMA Memory data size 256 * @brief DMA memory data size 257 * @{ 258 */ 259 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 260 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 261 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 262 /** 263 * @} 264 */ 265 266 /** @defgroup DMA_mode DMA mode 267 * @brief DMA mode 268 * @{ 269 */ 270 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 271 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 272 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup DMA_Priority_level DMA Priority level 278 * @brief DMA priority levels 279 * @{ 280 */ 281 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ 282 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 283 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 284 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 285 /** 286 * @} 287 */ 288 289 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 290 * @brief DMA FIFO direct mode 291 * @{ 292 */ 293 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 294 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 295 /** 296 * @} 297 */ 298 299 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 300 * @brief DMA FIFO level 301 * @{ 302 */ 303 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 304 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 305 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 306 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 307 /** 308 * @} 309 */ 310 311 /** @defgroup DMA_Memory_burst DMA Memory burst 312 * @brief DMA memory burst 313 * @{ 314 */ 315 #define DMA_MBURST_SINGLE 0x00000000U 316 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 317 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 318 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 319 /** 320 * @} 321 */ 322 323 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 324 * @brief DMA peripheral burst 325 * @{ 326 */ 327 #define DMA_PBURST_SINGLE 0x00000000U 328 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 329 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 330 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 331 /** 332 * @} 333 */ 334 335 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 336 * @brief DMA interrupts definition 337 * @{ 338 */ 339 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 340 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 341 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 342 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 343 #define DMA_IT_FE 0x00000080U 344 /** 345 * @} 346 */ 347 348 /** @defgroup DMA_flag_definitions DMA flag definitions 349 * @brief DMA flag definitions 350 * @{ 351 */ 352 #define DMA_FLAG_FEIF0_4 0x00000001U 353 #define DMA_FLAG_DMEIF0_4 0x00000004U 354 #define DMA_FLAG_TEIF0_4 0x00000008U 355 #define DMA_FLAG_HTIF0_4 0x00000010U 356 #define DMA_FLAG_TCIF0_4 0x00000020U 357 #define DMA_FLAG_FEIF1_5 0x00000040U 358 #define DMA_FLAG_DMEIF1_5 0x00000100U 359 #define DMA_FLAG_TEIF1_5 0x00000200U 360 #define DMA_FLAG_HTIF1_5 0x00000400U 361 #define DMA_FLAG_TCIF1_5 0x00000800U 362 #define DMA_FLAG_FEIF2_6 0x00010000U 363 #define DMA_FLAG_DMEIF2_6 0x00040000U 364 #define DMA_FLAG_TEIF2_6 0x00080000U 365 #define DMA_FLAG_HTIF2_6 0x00100000U 366 #define DMA_FLAG_TCIF2_6 0x00200000U 367 #define DMA_FLAG_FEIF3_7 0x00400000U 368 #define DMA_FLAG_DMEIF3_7 0x01000000U 369 #define DMA_FLAG_TEIF3_7 0x02000000U 370 #define DMA_FLAG_HTIF3_7 0x04000000U 371 #define DMA_FLAG_TCIF3_7 0x08000000U 372 /** 373 * @} 374 */ 375 376 /** 377 * @} 378 */ 379 380 /* Exported macro ------------------------------------------------------------*/ 381 382 /** @brief Reset DMA handle state 383 * @param __HANDLE__ specifies the DMA handle. 384 * @retval None 385 */ 386 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 387 388 /** 389 * @brief Return the current DMA Stream FIFO filled level. 390 * @param __HANDLE__ DMA handle 391 * @retval The FIFO filling state. 392 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 393 * and not empty. 394 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 395 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 396 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 397 * - DMA_FIFOStatus_Empty: when FIFO is empty 398 * - DMA_FIFOStatus_Full: when FIFO is full 399 */ 400 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 401 402 /** 403 * @brief Enable the specified DMA Stream. 404 * @param __HANDLE__ DMA handle 405 * @retval None 406 */ 407 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 408 409 /** 410 * @brief Disable the specified DMA Stream. 411 * @param __HANDLE__ DMA handle 412 * @retval None 413 */ 414 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 415 416 /* Interrupt & Flag management */ 417 418 /** 419 * @brief Return the current DMA Stream transfer complete flag. 420 * @param __HANDLE__ DMA handle 421 * @retval The specified transfer complete flag index. 422 */ 423 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 424 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 434 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 435 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 436 DMA_FLAG_TCIF3_7) 437 438 /** 439 * @brief Return the current DMA Stream half transfer complete flag. 440 * @param __HANDLE__ DMA handle 441 * @retval The specified half transfer complete flag index. 442 */ 443 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 444 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 454 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 455 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 456 DMA_FLAG_HTIF3_7) 457 458 /** 459 * @brief Return the current DMA Stream transfer error flag. 460 * @param __HANDLE__ DMA handle 461 * @retval The specified transfer error flag index. 462 */ 463 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 464 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 474 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 475 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 476 DMA_FLAG_TEIF3_7) 477 478 /** 479 * @brief Return the current DMA Stream FIFO error flag. 480 * @param __HANDLE__ DMA handle 481 * @retval The specified FIFO error flag index. 482 */ 483 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 484 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 496 DMA_FLAG_FEIF3_7) 497 498 /** 499 * @brief Return the current DMA Stream direct mode error flag. 500 * @param __HANDLE__ DMA handle 501 * @retval The specified direct mode error flag index. 502 */ 503 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 504 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 516 DMA_FLAG_DMEIF3_7) 517 518 /** 519 * @brief Get the DMA Stream pending flags. 520 * @param __HANDLE__ DMA handle 521 * @param __FLAG__ Get the specified flag. 522 * This parameter can be any combination of the following values: 523 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 524 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 525 * @arg DMA_FLAG_TEIFx: Transfer error flag. 526 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 527 * @arg DMA_FLAG_FEIFx: FIFO error flag. 528 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 529 * @retval The state of FLAG (SET or RESET). 530 */ 531 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 532 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 533 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 534 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 535 536 /** 537 * @brief Clear the DMA Stream pending flags. 538 * @param __HANDLE__ DMA handle 539 * @param __FLAG__ specifies the flag to clear. 540 * This parameter can be any combination of the following values: 541 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 542 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 543 * @arg DMA_FLAG_TEIFx: Transfer error flag. 544 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 545 * @arg DMA_FLAG_FEIFx: FIFO error flag. 546 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 547 * @retval None 548 */ 549 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 550 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 551 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 552 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 553 554 /** 555 * @brief Enable the specified DMA Stream interrupts. 556 * @param __HANDLE__ DMA handle 557 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 558 * This parameter can be any combination of the following values: 559 * @arg DMA_IT_TC: Transfer complete interrupt mask. 560 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 561 * @arg DMA_IT_TE: Transfer error interrupt mask. 562 * @arg DMA_IT_FE: FIFO error interrupt mask. 563 * @arg DMA_IT_DME: Direct mode error interrupt. 564 * @retval None 565 */ 566 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 567 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 568 569 /** 570 * @brief Disable the specified DMA Stream interrupts. 571 * @param __HANDLE__ DMA handle 572 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 573 * This parameter can be any combination of the following values: 574 * @arg DMA_IT_TC: Transfer complete interrupt mask. 575 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 576 * @arg DMA_IT_TE: Transfer error interrupt mask. 577 * @arg DMA_IT_FE: FIFO error interrupt mask. 578 * @arg DMA_IT_DME: Direct mode error interrupt. 579 * @retval None 580 */ 581 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 582 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 583 584 /** 585 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. 586 * @param __HANDLE__ DMA handle 587 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 588 * This parameter can be one of the following values: 589 * @arg DMA_IT_TC: Transfer complete interrupt mask. 590 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 591 * @arg DMA_IT_TE: Transfer error interrupt mask. 592 * @arg DMA_IT_FE: FIFO error interrupt mask. 593 * @arg DMA_IT_DME: Direct mode error interrupt. 594 * @retval The state of DMA_IT. 595 */ 596 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 597 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 598 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 599 600 /** 601 * @brief Writes the number of data units to be transferred on the DMA Stream. 602 * @param __HANDLE__ DMA handle 603 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) 604 * Number of data items depends only on the Peripheral data format. 605 * 606 * @note If Peripheral data format is Bytes: number of data units is equal 607 * to total number of bytes to be transferred. 608 * 609 * @note If Peripheral data format is Half-Word: number of data units is 610 * equal to total number of bytes to be transferred / 2. 611 * 612 * @note If Peripheral data format is Word: number of data units is equal 613 * to total number of bytes to be transferred / 4. 614 * 615 * @retval The number of remaining data units in the current DMAy Streamx transfer. 616 */ 617 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 618 619 /** 620 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 621 * @param __HANDLE__ DMA handle 622 * 623 * @retval The number of remaining data units in the current DMA Stream transfer. 624 */ 625 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 626 627 628 /* Include DMA HAL Extension module */ 629 #include "stm32f2xx_hal_dma_ex.h" 630 631 /* Exported functions --------------------------------------------------------*/ 632 633 /** @defgroup DMA_Exported_Functions DMA Exported Functions 634 * @brief DMA Exported functions 635 * @{ 636 */ 637 638 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 639 * @brief Initialization and de-initialization functions 640 * @{ 641 */ 642 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 643 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 644 /** 645 * @} 646 */ 647 648 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 649 * @brief I/O operation functions 650 * @{ 651 */ 652 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 653 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 654 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 655 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 656 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 657 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 658 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); 659 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 660 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 661 662 /** 663 * @} 664 */ 665 666 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 667 * @brief Peripheral State functions 668 * @{ 669 */ 670 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 671 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 672 /** 673 * @} 674 */ 675 /** 676 * @} 677 */ 678 /* Private Constants -------------------------------------------------------------*/ 679 /** @defgroup DMA_Private_Constants DMA Private Constants 680 * @brief DMA private defines and constants 681 * @{ 682 */ 683 /** 684 * @} 685 */ 686 687 /* Private macros ------------------------------------------------------------*/ 688 /** @defgroup DMA_Private_Macros DMA Private Macros 689 * @brief DMA private macros 690 * @{ 691 */ 692 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 693 ((CHANNEL) == DMA_CHANNEL_1) || \ 694 ((CHANNEL) == DMA_CHANNEL_2) || \ 695 ((CHANNEL) == DMA_CHANNEL_3) || \ 696 ((CHANNEL) == DMA_CHANNEL_4) || \ 697 ((CHANNEL) == DMA_CHANNEL_5) || \ 698 ((CHANNEL) == DMA_CHANNEL_6) || \ 699 ((CHANNEL) == DMA_CHANNEL_7)) 700 701 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 702 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 703 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 704 705 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 706 707 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 708 ((STATE) == DMA_PINC_DISABLE)) 709 710 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 711 ((STATE) == DMA_MINC_DISABLE)) 712 713 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 714 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 715 ((SIZE) == DMA_PDATAALIGN_WORD)) 716 717 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 718 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 719 ((SIZE) == DMA_MDATAALIGN_WORD )) 720 721 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 722 ((MODE) == DMA_CIRCULAR) || \ 723 ((MODE) == DMA_PFCTRL)) 724 725 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 726 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 727 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 728 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 729 730 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 731 ((STATE) == DMA_FIFOMODE_ENABLE)) 732 733 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 734 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 735 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 736 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 737 738 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 739 ((BURST) == DMA_MBURST_INC4) || \ 740 ((BURST) == DMA_MBURST_INC8) || \ 741 ((BURST) == DMA_MBURST_INC16)) 742 743 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 744 ((BURST) == DMA_PBURST_INC4) || \ 745 ((BURST) == DMA_PBURST_INC8) || \ 746 ((BURST) == DMA_PBURST_INC16)) 747 /** 748 * @} 749 */ 750 751 /* Private functions ---------------------------------------------------------*/ 752 /** @defgroup DMA_Private_Functions DMA Private Functions 753 * @brief DMA private functions 754 * @{ 755 */ 756 /** 757 * @} 758 */ 759 760 /** 761 * @} 762 */ 763 764 /** 765 * @} 766 */ 767 768 #ifdef __cplusplus 769 } 770 #endif 771 772 #endif /* __STM32F2xx_HAL_DMA_H */ 773 774
