1 /** 2 ****************************************************************************** 3 * @file stm32c0xx_hal_rcc.h 4 * @author MCD Application Team 5 * @brief Header file of RCC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32C0xx_HAL_RCC_H 21 #define STM32C0xx_HAL_RCC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32c0xx_hal_def.h" 29 #include "stm32c0xx_ll_rcc.h" 30 31 /** @addtogroup STM32C0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup RCC 36 * @{ 37 */ 38 39 /* Private constants ---------------------------------------------------------*/ 40 /** @addtogroup RCC_Private_Constants 41 * @{ 42 */ 43 44 /** @defgroup RCC_Timeout_Value Timeout Values 45 * @{ 46 */ 47 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT /* LSE timeout in ms */ 48 /** 49 * @} 50 */ 51 52 /* Defines used for Flags */ 53 #define RCC_CR_REG_INDEX 1U 54 #define RCC_CSR1_REG_INDEX 2U 55 #define RCC_CSR2_REG_INDEX 3U 56 57 #define RCC_FLAG_MASK 0x1FU 58 59 /* Define used for IS_RCC_CLOCKTYPE() */ 60 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1) /*!< All clocktype to configure */ 61 /** 62 * @} 63 */ 64 65 /* Private macros ------------------------------------------------------------*/ 66 /** @addtogroup RCC_Private_Macros 67 * @{ 68 */ 69 70 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 71 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 72 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 73 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 74 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 75 76 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 77 ((__HSE__) == RCC_HSE_BYPASS)) 78 79 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 80 ((__LSE__) == RCC_LSE_BYPASS)) 81 82 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 83 84 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U) 85 86 #define IS_RCC_HSIDIV(__DIV__) (((__DIV__) == RCC_HSI_DIV1) || ((__DIV__) == RCC_HSI_DIV2) || \ 87 ((__DIV__) == RCC_HSI_DIV4) || ((__DIV__) == RCC_HSI_DIV8) || \ 88 ((__DIV__) == RCC_HSI_DIV16) || ((__DIV__) == RCC_HSI_DIV32)|| \ 89 ((__DIV__) == RCC_HSI_DIV64) || ((__DIV__) == RCC_HSI_DIV128)) 90 91 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 92 93 94 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__)\ 95 & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) 96 97 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 98 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 99 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSE) || \ 100 ((__SOURCE__) == RCC_SYSCLKSOURCE_LSI)) 101 102 #define IS_RCC_SYSCLK(SYSCLK) ((SYSCLK) == RCC_SYSCLK_DIV1) 103 104 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1) || ((HCLK) == RCC_HCLK_DIV2) || \ 105 ((HCLK) == RCC_HCLK_DIV4) || ((HCLK) == RCC_HCLK_DIV8) || \ 106 ((HCLK) == RCC_HCLK_DIV16) || ((HCLK) == RCC_HCLK_DIV64) || \ 107 ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \ 108 ((HCLK) == RCC_HCLK_DIV512)) 109 110 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_APB1_DIV1) || ((__PCLK__) == RCC_APB1_DIV2) || \ 111 ((__PCLK__) == RCC_APB1_DIV4) || ((__PCLK__) == RCC_APB1_DIV8) || \ 112 ((__PCLK__) == RCC_APB1_DIV16)) 113 114 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \ 115 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 116 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 117 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 118 119 #if defined(STM32C011xx) 120 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 121 ((__MCOX__) == RCC_MCO1_PA9) || \ 122 ((__MCOX__) == RCC_MCO1_PF2) || \ 123 ((__MCOX__) == RCC_MCO2_PA8) || \ 124 ((__MCOX__) == RCC_MCO2_PA10) || \ 125 ((__MCOX__) == RCC_MCO2_PA14)) 126 #elif defined(STM32C031xx) 127 #define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1_PA8) || \ 128 ((__MCOX__) == RCC_MCO1_PA9) || \ 129 ((__MCOX__) == RCC_MCO1_PF2) || \ 130 ((__MCOX__) == RCC_MCO2_PA8) || \ 131 ((__MCOX__) == RCC_MCO2_PA10) || \ 132 ((__MCOX__) == RCC_MCO2_PA14) || \ 133 ((__MCOX__) == RCC_MCO2_PA15) || \ 134 ((__MCOX__) == RCC_MCO2_PB2)) 135 #endif 136 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 137 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 138 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 139 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 140 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 141 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 142 143 #define IS_RCC_MCO2SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO2SOURCE_NOCLOCK) || \ 144 ((__SOURCE__) == RCC_MCO2SOURCE_SYSCLK) || \ 145 ((__SOURCE__) == RCC_MCO2SOURCE_HSI) || \ 146 ((__SOURCE__) == RCC_MCO2SOURCE_HSE) || \ 147 ((__SOURCE__) == RCC_MCO2SOURCE_LSI) || \ 148 ((__SOURCE__) == RCC_MCO2SOURCE_LSE)) 149 150 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 151 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 152 ((__DIV__) == RCC_MCODIV_16)|| ((__DIV__) == RCC_MCODIV_32) || \ 153 ((__DIV__) == RCC_MCODIV_64)|| ((__DIV__) == RCC_MCODIV_128)) 154 155 #define IS_RCC_MCO2DIV(__DIV__) (((__DIV__) == RCC_MCO2DIV_1) || ((__DIV__) == RCC_MCO2DIV_2) || \ 156 ((__DIV__) == RCC_MCO2DIV_4) || ((__DIV__) == RCC_MCO2DIV_8) || \ 157 ((__DIV__) == RCC_MCO2DIV_16)|| ((__DIV__) == RCC_MCO2DIV_32) || \ 158 ((__DIV__) == RCC_MCO2DIV_64)|| ((__DIV__) == RCC_MCO2DIV_128)) 159 160 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 161 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 162 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 163 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 164 165 /** 166 * @} 167 */ 168 169 /* Exported types ------------------------------------------------------------*/ 170 /** @defgroup RCC_Exported_Types RCC Exported Types 171 * @{ 172 */ 173 174 175 /** 176 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition 177 */ 178 typedef struct 179 { 180 uint32_t OscillatorType; /*!< The oscillators to be configured. 181 This parameter can be a value of @ref RCC_Oscillator_Type */ 182 183 uint32_t HSEState; /*!< The new state of the HSE. 184 This parameter can be a value of @ref RCC_HSE_Config */ 185 186 uint32_t LSEState; /*!< The new state of the LSE. 187 This parameter can be a value of @ref RCC_LSE_Config */ 188 189 uint32_t HSIState; /*!< The new state of the HSI. 190 This parameter can be a value of @ref RCC_HSI_Config */ 191 192 uint32_t HSIDiv; /*!< The division factor of the HSI48. 193 This parameter can be a value of @ref RCC_HSI_Div */ 194 195 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 196 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ 197 198 uint32_t LSIState; /*!< The new state of the LSI. 199 This parameter can be a value of @ref RCC_LSI_Config */ 200 201 } RCC_OscInitTypeDef; 202 203 /** 204 * @brief RCC System, AHB and APB busses clock configuration structure definition 205 */ 206 typedef struct 207 { 208 uint32_t ClockType; /*!< The clock to be configured. 209 This parameter can be a combination of @ref RCC_System_Clock_Type */ 210 211 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 212 This parameter can be a value of @ref RCC_System_Clock_Source */ 213 214 uint32_t SYSCLKDivider; /*!< The system clock divider. This parameter can be 215 a value of @ref RCC_SYS_Clock_Source */ 216 217 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 218 This parameter can be a value of @ref RCC_HCLK_Clock_Source */ 219 220 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 221 This parameter can be a value of @ref RCC_APB1_Clock_Source */ 222 223 224 } RCC_ClkInitTypeDef; 225 226 /** 227 * @} 228 */ 229 230 /* Exported constants --------------------------------------------------------*/ 231 /** @defgroup RCC_Exported_Constants RCC Exported Constants 232 * @{ 233 */ 234 235 /** @defgroup RCC_Oscillator_Type Oscillator Type 236 * @{ 237 */ 238 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ 239 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */ 240 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */ 241 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ 242 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ 243 /** 244 * @} 245 */ 246 247 /** @defgroup RCC_HSE_Config HSE Config 248 * @{ 249 */ 250 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ 251 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 252 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 253 /** 254 * @} 255 */ 256 257 /** @defgroup RCC_LSE_Config LSE Config 258 * @{ 259 */ 260 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ 261 #define RCC_LSE_ON RCC_CSR1_LSEON /*!< LSE clock activation */ 262 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR1_LSEBYP | RCC_CSR1_LSEON)) /*!< External clock source for LSE clock */ 263 /** 264 * @} 265 */ 266 267 /** @defgroup RCC_HSI_Config HSI Config 268 * @{ 269 */ 270 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ 271 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 272 #define RCC_HSICALIBRATION_DEFAULT 64U /*!< Default HSI calibration trimming value */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup RCC_HSI_Div HSI Div 278 * @{ 279 */ 280 #define RCC_HSI_DIV1 0x00000000U /*!< HSI clock is not divided */ 281 #define RCC_HSI_DIV2 RCC_CR_HSIDIV_0 /*!< HSI clock is divided by 2 */ 282 #define RCC_HSI_DIV4 RCC_CR_HSIDIV_1 /*!< HSI clock is divided by 4 */ 283 #define RCC_HSI_DIV8 (RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 8 */ 284 #define RCC_HSI_DIV16 RCC_CR_HSIDIV_2 /*!< HSI clock is divided by 16 */ 285 #define RCC_HSI_DIV32 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 32 */ 286 #define RCC_HSI_DIV64 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1) /*!< HSI clock is divided by 64 */ 287 #define RCC_HSI_DIV128 (RCC_CR_HSIDIV_2|RCC_CR_HSIDIV_1|RCC_CR_HSIDIV_0) /*!< HSI clock is divided by 128 */ 288 /** 289 * @} 290 */ 291 292 293 /** @defgroup RCC_LSI_Config LSI Config 294 * @{ 295 */ 296 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ 297 #define RCC_LSI_ON RCC_CSR2_LSION /*!< LSI clock activation */ 298 /** 299 * @} 300 */ 301 302 303 /** @defgroup RCC_System_Clock_Type System Clock Type 304 * @{ 305 */ 306 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ 307 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ 308 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ 309 /** 310 * @} 311 */ 312 313 /** @defgroup RCC_System_Clock_Source System Clock Source 314 * @{ 315 */ 316 #define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI selection as system clock */ 317 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ 318 #define RCC_SYSCLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection as system clock */ 319 #define RCC_SYSCLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection as system clock */ 320 /** 321 * @} 322 */ 323 324 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 325 * @{ 326 */ 327 #define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI used as system clock */ 328 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ 329 #define RCC_SYSCLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ 330 #define RCC_SYSCLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup RCC_SYS_Clock_Source RCC SYS Clock Source 336 * @{ 337 */ 338 #define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ 339 340 /** 341 * @} 342 */ 343 344 /** @defgroup RCC_HCLK_Clock_Source RCC HCLK Clock Source 345 * @{ 346 */ 347 #define RCC_HCLK_DIV1 0x00000000U /*!< HCLK not divided */ 348 #define RCC_HCLK_DIV2 RCC_CFGR_HPRE_3 /*!< HCLK divided by 2 */ 349 #define RCC_HCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 4 */ 350 #define RCC_HCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 8 */ 351 #define RCC_HCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 16 */ 352 #define RCC_HCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< HCLK divided by 64 */ 353 #define RCC_HCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 128 */ 354 #define RCC_HCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< HCLK divided by 256 */ 355 #define RCC_HCLK_DIV512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< HCLK divided by 512 */ 356 /** 357 * @} 358 */ 359 360 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source 361 * @{ 362 */ 363 #define RCC_APB1_DIV1 0x00000000U /*!< APB not divided */ 364 #define RCC_APB1_DIV2 RCC_CFGR_PPRE_2 /*!< APB divided by 2 */ 365 #define RCC_APB1_DIV4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< APB divided by 4 */ 366 #define RCC_APB1_DIV8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< APB divided by 4 */ 367 #define RCC_APB1_DIV16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< APB divided by 16 */ 368 369 /** 370 * @} 371 */ 372 373 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 374 * @{ 375 */ 376 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock configured for RTC */ 377 #define RCC_RTCCLKSOURCE_LSE RCC_CSR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 378 #define RCC_RTCCLKSOURCE_LSI RCC_CSR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 379 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_CSR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 380 /** 381 * @} 382 */ 383 384 /** @defgroup RCC_MCO_Index MCO Index 385 * @{ 386 */ 387 388 /* @cond */ 389 /* 32 28 20 16 0 390 -------------------------------- 391 | MCO | GPIO | GPIO | GPIO | 392 | Index | AF | Port | Pin | 393 -------------------------------*/ 394 395 #define RCC_MCO_GPIOPORT_POS 16U 396 #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) 397 #define RCC_MCO_GPIOAF_POS 20U 398 #define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS) 399 #define RCC_MCO_INDEX_POS 28U 400 #define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS) 401 402 #define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */ 403 #define RCC_MCO2_INDEX (0x1UL << RCC_MCO_INDEX_POS) /*!< MCO2 index */ 404 /* @endcond */ 405 406 #define RCC_MCO1_PA8 (RCC_MCO1_INDEX |\ 407 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 408 #define RCC_MCO1_PA9 (RCC_MCO1_INDEX |\ 409 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_9) 410 #define RCC_MCO1_PF2 (RCC_MCO1_INDEX |\ 411 (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOF) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 412 #define RCC_MCO1 RCC_MCO1_PA8 /*!< Alias for compatibility */ 413 414 #define RCC_MCO2_PA8 (RCC_MCO2_INDEX |\ 415 (GPIO_AF15_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8) 416 #define RCC_MCO2_PA10 (RCC_MCO2_INDEX |\ 417 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10) 418 #define RCC_MCO2_PA14 (RCC_MCO2_INDEX |\ 419 (GPIO_AF11_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_14) 420 #if defined(STM32C031xx) 421 #define RCC_MCO2_PA15 (RCC_MCO2_INDEX |\ 422 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_15) 423 #define RCC_MCO2_PB2 (RCC_MCO2_INDEX |\ 424 (GPIO_AF3_MCO2 << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOB) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_2) 425 #endif 426 #define RCC_MCO2 RCC_MCO2_PA10 /*!< Alias for compatibility */ 427 428 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 1 MCO*/ 429 /** 430 * @} 431 */ 432 433 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 434 * @{ 435 */ 436 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ 437 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 438 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 439 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 440 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 441 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 442 /** 443 * @} 444 */ 445 446 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source 447 * @{ 448 */ 449 #define RCC_MCO2SOURCE_NOCLOCK 0x00000000U /*!< MCO2 output disabled, no clock on MCO2 */ 450 #define RCC_MCO2SOURCE_SYSCLK RCC_CFGR_MCO2SEL_0 /*!< SYSCLK selection as MCO2 source */ 451 #define RCC_MCO2SOURCE_HSI (RCC_CFGR_MCO2SEL_0| RCC_CFGR_MCO2SEL_1) /*!< HSI selection as MCO2 source */ 452 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2SEL_2 /*!< HSE selection as MCO2 source */ 453 #define RCC_MCO2SOURCE_LSI (RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSI selection as MCO2 source */ 454 #define RCC_MCO2SOURCE_LSE (RCC_CFGR_MCO2SEL_0|RCC_CFGR_MCO2SEL_1|RCC_CFGR_MCO2SEL_2) /*!< LSE selection as MCO2 source */ 455 /** 456 * @} 457 */ 458 /** @defgroup RCC_MCO1_Clock_Prescaler MCO1 Clock Prescaler 459 * @{ 460 */ 461 #define RCC_MCODIV_1 0x00000000U /*!< MCO not divided */ 462 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */ 463 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */ 464 #define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */ 465 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */ 466 #define RCC_MCODIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 32 */ 467 #define RCC_MCODIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO divided by 64 */ 468 #define RCC_MCODIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 128 */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup RCC_MCO2_Clock_Prescaler MCO2 Clock Prescaler 474 * @{ 475 */ 476 #define RCC_MCO2DIV_1 0x00000000U /*!< MCO not divided */ 477 #define RCC_MCO2DIV_2 RCC_CFGR_MCO2PRE_0 /*!< MCO divided by 2 */ 478 #define RCC_MCO2DIV_4 RCC_CFGR_MCO2PRE_1 /*!< MCO divided by 4 */ 479 #define RCC_MCO2DIV_8 (RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 8 */ 480 #define RCC_MCO2DIV_16 RCC_CFGR_MCO2PRE_2 /*!< MCO divided by 16 */ 481 #define RCC_MCO2DIV_32 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 32 */ 482 #define RCC_MCO2DIV_64 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1) /*!< MCO divided by 64 */ 483 #define RCC_MCO2DIV_128 (RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_0) /*!< MCO divided by 128 */ 484 /** 485 * @} 486 */ 487 488 /** @defgroup RCC_Interrupt Interrupts 489 * @{ 490 */ 491 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 492 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 493 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ 494 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 495 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */ 496 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 497 /** 498 * @} 499 */ 500 501 /** @defgroup RCC_Flag Flags 502 * Elements values convention: XXXYYYYYb 503 * - YYYYY : Flag position in the register 504 * - XXX : Register index 505 * - 001: CR register 506 * - 010: CSR1 register 507 * - 011: CSR2 register 508 * @{ 509 */ 510 /* Flags in the CR register */ 511 #define RCC_FLAG_HSIRDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ 512 #define RCC_FLAG_HSERDY ((RCC_CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ 513 514 /* Flags in the CSR1 register */ 515 #define RCC_FLAG_LSERDY ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSERDY_Pos) /*!< LSE Ready flag */ 516 #define RCC_FLAG_LSECSSD ((RCC_CSR1_REG_INDEX << 5U) | RCC_CSR1_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ 517 518 /* Flags in the CSR2 register */ 519 #define RCC_FLAG_LSIRDY ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LSIRDY_Pos) /*!< LSI Ready flag */ 520 #define RCC_FLAG_OBLRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ 521 #define RCC_FLAG_PINRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PINRSTF_Pos) /*!< PIN reset flag */ 522 #define RCC_FLAG_PWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_PWRRSTF_Pos) /*!< BOR or POR/PDR reset flag */ 523 #define RCC_FLAG_SFTRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_SFTRSTF_Pos) /*!< Software Reset flag */ 524 #define RCC_FLAG_IWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ 525 #define RCC_FLAG_WWDGRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ 526 #define RCC_FLAG_LPWRRST ((RCC_CSR2_REG_INDEX << 5U) | RCC_CSR2_LPWRRSTF_Pos) /*!< Low-Power reset flag */ 527 528 /** 529 * @} 530 */ 531 532 /** @defgroup RCC_LSEDrive_Config LSE Drive Configuration 533 * @{ 534 */ 535 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ 536 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR1_LSEDRV_0 /*!< LSE medium low drive capability */ 537 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR1_LSEDRV_1 /*!< LSE medium high drive capability */ 538 #define RCC_LSEDRIVE_HIGH RCC_CSR1_LSEDRV /*!< LSE high drive capability */ 539 /** 540 * @} 541 */ 542 543 /** 544 * @} 545 */ 546 547 /* Exported macros -----------------------------------------------------------*/ 548 549 /** @defgroup RCC_Exported_Macros RCC Exported Macros 550 * @{ 551 */ 552 553 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable 554 * @brief Enable or disable the AHB peripheral clock. 555 * @note After reset, the peripheral clock (used for registers read/write access) 556 * is disabled and the application software has to enable this clock before 557 * using it. 558 * @{ 559 */ 560 561 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 562 __IO uint32_t tmpreg; \ 563 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 564 /* Delay after an RCC peripheral clock enabling */ \ 565 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN); \ 566 UNUSED(tmpreg); \ 567 } while(0U) 568 569 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 570 __IO uint32_t tmpreg; \ 571 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 572 /* Delay after an RCC peripheral clock enabling */ \ 573 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN); \ 574 UNUSED(tmpreg); \ 575 } while(0U) 576 577 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 578 __IO uint32_t tmpreg; \ 579 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 580 /* Delay after an RCC peripheral clock enabling */ \ 581 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN); \ 582 UNUSED(tmpreg); \ 583 } while(0U) 584 585 586 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) 587 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) 588 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) 589 590 /** 591 * @} 592 */ 593 594 /** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Clock Enable Disable 595 * @brief Enable or disable the IO Ports clock. 596 * @note After reset, the IO ports clock (used for registers read/write access) 597 * is disabled and the application software has to enable this clock before 598 * using it. 599 * @{ 600 */ 601 602 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 603 __IO uint32_t tmpreg; \ 604 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 605 /* Delay after an RCC peripheral clock enabling */ \ 606 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN); \ 607 UNUSED(tmpreg); \ 608 } while(0U) 609 610 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 611 __IO uint32_t tmpreg; \ 612 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 613 /* Delay after an RCC peripheral clock enabling */ \ 614 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN); \ 615 UNUSED(tmpreg); \ 616 } while(0U) 617 618 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 619 __IO uint32_t tmpreg; \ 620 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 621 /* Delay after an RCC peripheral clock enabling */ \ 622 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN); \ 623 UNUSED(tmpreg); \ 624 } while(0U) 625 #if defined (STM32C031xx) 626 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 627 __IO uint32_t tmpreg; \ 628 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 629 /* Delay after an RCC peripheral clock enabling */ \ 630 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN); \ 631 UNUSED(tmpreg); \ 632 } while(0U) 633 #endif 634 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 635 __IO uint32_t tmpreg; \ 636 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 637 /* Delay after an RCC peripheral clock enabling */ \ 638 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN); \ 639 UNUSED(tmpreg); \ 640 } while(0U) 641 642 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) 643 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) 644 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) 645 #if defined (STM32C031xx) 646 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) 647 #endif 648 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) 649 650 /** 651 * @} 652 */ 653 654 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 655 * @brief Enable or disable the APB1 peripheral clock. 656 * @note After reset, the peripheral clock (used for registers read/write access) 657 * is disabled and the application software has to enable this clock before 658 * using it. 659 * @{ 660 */ 661 662 663 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 664 __IO uint32_t tmpreg; \ 665 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 666 /* Delay after an RCC peripheral clock enabling */ \ 667 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \ 668 UNUSED(tmpreg); \ 669 } while(0U) 670 671 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 672 __IO uint32_t tmpreg; \ 673 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 674 /* Delay after an RCC peripheral clock enabling */ \ 675 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \ 676 UNUSED(tmpreg); \ 677 } while(0U) 678 679 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 680 __IO uint32_t tmpreg; \ 681 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 682 /* Delay after an RCC peripheral clock enabling */ \ 683 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \ 684 UNUSED(tmpreg); \ 685 } while(0U) 686 687 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 688 __IO uint32_t tmpreg; \ 689 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 690 /* Delay after an RCC peripheral clock enabling */ \ 691 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \ 692 UNUSED(tmpreg); \ 693 } while(0U) 694 695 696 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 697 __IO uint32_t tmpreg; \ 698 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 699 /* Delay after an RCC peripheral clock enabling */ \ 700 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \ 701 UNUSED(tmpreg); \ 702 } while(0U) 703 704 #define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \ 705 __IO uint32_t tmpreg; \ 706 SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 707 /* Delay after an RCC peripheral clock enabling */ \ 708 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \ 709 UNUSED(tmpreg); \ 710 } while(0U) 711 712 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 713 __IO uint32_t tmpreg; \ 714 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 715 /* Delay after an RCC peripheral clock enabling */ \ 716 tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \ 717 UNUSED(tmpreg); \ 718 } while(0U) 719 720 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) 721 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) 722 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) 723 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) 724 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) 725 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) 726 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) 727 /** 728 * @} 729 */ 730 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 731 * @brief Enable or disable the APB2 peripheral clock. 732 * @note After reset, the peripheral clock (used for registers read/write access) 733 * is disabled and the application software has to enable this clock before 734 * using it. 735 * @{ 736 */ 737 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 738 __IO uint32_t tmpreg; \ 739 SET_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 740 /* Delay after an RCC peripheral clock enabling */ \ 741 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN); \ 742 UNUSED(tmpreg); \ 743 } while(0U) 744 745 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 746 __IO uint32_t tmpreg; \ 747 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 748 /* Delay after an RCC peripheral clock enabling */ \ 749 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN); \ 750 UNUSED(tmpreg); \ 751 } while(0U) 752 753 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 754 __IO uint32_t tmpreg; \ 755 SET_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 756 /* Delay after an RCC peripheral clock enabling */ \ 757 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN); \ 758 UNUSED(tmpreg); \ 759 } while(0U) 760 761 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 762 __IO uint32_t tmpreg; \ 763 SET_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 764 /* Delay after an RCC peripheral clock enabling */ \ 765 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN); \ 766 UNUSED(tmpreg); \ 767 } while(0U) 768 769 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ 770 __IO uint32_t tmpreg; \ 771 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 772 /* Delay after an RCC peripheral clock enabling */ \ 773 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN); \ 774 UNUSED(tmpreg); \ 775 } while(0U) 776 777 778 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 779 __IO uint32_t tmpreg; \ 780 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 781 /* Delay after an RCC peripheral clock enabling */ \ 782 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN); \ 783 UNUSED(tmpreg); \ 784 } while(0U) 785 786 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 787 __IO uint32_t tmpreg; \ 788 SET_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 789 /* Delay after an RCC peripheral clock enabling */ \ 790 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN); \ 791 UNUSED(tmpreg); \ 792 } while(0U) 793 794 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 795 __IO uint32_t tmpreg; \ 796 SET_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 797 /* Delay after an RCC peripheral clock enabling */ \ 798 tmpreg = READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN); \ 799 UNUSED(tmpreg); \ 800 } while(0U) 801 802 803 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) 804 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) 805 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) 806 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) 807 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) 808 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) 809 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) 810 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) 811 812 /** 813 * @} 814 */ 815 816 /** @defgroup RCC_AHB_Peripheral_Clock_Enabled_Disabled_Status AHB Peripheral Clock Enabled or Disabled Status 817 * @brief Check whether the AHB peripheral clock is enabled or not. 818 * @note After reset, the peripheral clock (used for registers read/write access) 819 * is disabled and the application software has to enable this clock before 820 * using it. 821 * @{ 822 */ 823 824 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET) 825 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) != RESET) 826 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET) 827 828 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) == RESET) 829 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_FLASHEN) == RESET) 830 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) == RESET) 831 832 /** 833 * @} 834 */ 835 836 /** @defgroup RCC_IOPORT_Clock_Enabled_Disabled_Status IOPORT Clock Enabled or Disabled Status 837 * @brief Check whether the IO Port clock is enabled or not. 838 * @note After reset, the peripheral clock (used for registers read/write access) 839 * is disabled and the application software has to enable this clock before 840 * using it. 841 * @{ 842 */ 843 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET) 844 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET) 845 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET) 846 #if defined (STM32C031xx) 847 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) != RESET) 848 #endif 849 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) != RESET) 850 851 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) == RESET) 852 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) == RESET) 853 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) == RESET) 854 #if defined (STM32C031xx) 855 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN) == RESET) 856 #endif 857 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOFEN) == RESET) 858 859 /** 860 * @} 861 */ 862 863 /** @defgroup RCC_APB1_Clock_Enabled_Disabled_Status APB1 Peripheral Clock Enabled or Disabled Status 864 * @brief Check whether the APB1 peripheral clock is enabled or not. 865 * @note After reset, the peripheral clock (used for registers read/write access) 866 * is disabled and the application software has to enable this clock before 867 * using it. 868 * @{ 869 */ 870 871 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U) 872 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U) 873 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U) 874 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U) 875 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U) 876 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U) 877 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U) 878 879 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U) 880 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U) 881 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U) 882 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U) 883 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U) 884 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U) 885 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U) 886 887 /** 888 * @} 889 */ 890 891 /** @defgroup RCC_APB2_Clock_Enabled_Disabled_Status APB2 Peripheral Clock Enabled or Disabled Status 892 * @brief Check whether the APB2 peripheral clock is enabled or not. 893 * @note After reset, the peripheral clock (used for registers read/write access) 894 * is disabled and the application software has to enable this clock before 895 * using it. 896 * @{ 897 */ 898 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) != 0U) 899 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) != 0U) 900 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) != 0U) 901 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) != 0U) 902 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) != 0U) 903 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) != 0U) 904 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) != 0U) 905 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) != 0U) 906 907 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SYSCFGEN) == 0U) 908 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM1EN) == 0U) 909 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_SPI1EN) == 0U) 910 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_USART1EN) == 0U) 911 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM14EN) == 0U) 912 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM16EN) == 0U) 913 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_TIM17EN) == 0U) 914 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR2, RCC_APBENR2_ADCEN) == 0U) 915 916 /** 917 * @} 918 */ 919 920 921 /** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset 922 * @brief Force or release AHB1 peripheral reset. 923 * @{ 924 */ 925 #define __HAL_RCC_AHB_FORCE_RESET() WRITE_REG(RCC->AHBRSTR, 0xFFFFFFFFU) 926 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 927 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 928 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 929 930 #define __HAL_RCC_AHB_RELEASE_RESET() WRITE_REG(RCC->AHBRSTR, 0x00000000U) 931 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_DMA1RST) 932 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_FLASHRST) 933 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, RCC_AHBRSTR_CRCRST) 934 935 /** 936 * @} 937 */ 938 939 /** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Force Release Reset 940 * @brief Force or release IO Port reset. 941 * @{ 942 */ 943 #define __HAL_RCC_IOP_FORCE_RESET() WRITE_REG(RCC->IOPRSTR, 0xFFFFFFFFU) 944 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 945 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 946 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 947 #if defined (STM32C031xx) 948 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 949 #endif 950 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 951 952 #define __HAL_RCC_IOP_RELEASE_RESET() WRITE_REG(RCC->IOPRSTR, 0x00000000U) 953 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOARST) 954 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOBRST) 955 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOCRST) 956 #if defined (STM32C031xx) 957 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIODRST) 958 #endif 959 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, RCC_IOPRSTR_GPIOFRST) 960 961 /** 962 * @} 963 */ 964 965 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 966 * @brief Force or release APB1 peripheral reset. 967 * @{ 968 */ 969 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APBRSTR1, 0xFFFFFFFFU) 970 971 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 972 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 973 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 974 #define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 975 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 976 977 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APBRSTR1, 0x00000000U) 978 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_TIM3RST) 979 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_USART2RST) 980 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_I2C1RST) 981 #define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_DBGRST) 982 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR1, RCC_APBRSTR1_PWRRST) 983 984 /** 985 * @} 986 */ 987 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 988 * @brief Force or release APB2 peripheral reset. 989 * @{ 990 */ 991 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APBRSTR2, 0xFFFFFFFFU) 992 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 993 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 994 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 995 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 996 #define __HAL_RCC_TIM14_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 997 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 998 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 999 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1000 1001 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APBRSTR2, 0x00000000U) 1002 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SYSCFGRST) 1003 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM1RST) 1004 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_SPI1RST) 1005 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_USART1RST) 1006 #define __HAL_RCC_TIM14_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM14RST) 1007 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM16RST) 1008 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_TIM17RST) 1009 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->APBRSTR2, RCC_APBRSTR2_ADCRST) 1010 /** 1011 * @} 1012 */ 1013 1014 /** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripherals Clock Sleep Enable Disable 1015 * @brief Enable or disable the AHB peripherals clock during Low Power (Sleep) mode. 1016 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1017 * power consumption. 1018 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1019 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1020 * @{ 1021 */ 1022 1023 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1024 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1025 #define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1026 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1027 1028 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) 1029 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) 1030 #define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) 1031 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) 1032 1033 /** 1034 * @} 1035 */ 1036 1037 /** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Clock Sleep Enable Disable 1038 * @brief Enable or disable the IOPORT clock during Low Power (Sleep) mode. 1039 * @note IOPORT clock gating in SLEEP mode can be used to further reduce 1040 * power consumption. 1041 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1042 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1043 * @{ 1044 */ 1045 1046 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1047 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1048 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1049 #if defined (STM32C031xx) 1050 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1051 #endif 1052 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1053 1054 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) 1055 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) 1056 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) 1057 #if defined (STM32C031xx) 1058 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) 1059 #endif 1060 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) 1061 /** 1062 * @} 1063 */ 1064 1065 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 1066 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 1067 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1068 * power consumption. 1069 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1070 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1071 * @{ 1072 */ 1073 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1074 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1075 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1076 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1077 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1078 #define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 1079 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1080 1081 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) 1082 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) 1083 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) 1084 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) 1085 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) 1086 #define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) 1087 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) 1088 1089 /** 1090 * @} 1091 */ 1092 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 1093 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 1094 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1095 * power consumption. 1096 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1097 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1098 * @{ 1099 */ 1100 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1101 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1102 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1103 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1104 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 1105 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1106 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 1107 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1108 1109 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) 1110 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) 1111 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) 1112 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) 1113 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) 1114 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) 1115 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) 1116 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) 1117 1118 /** 1119 * @} 1120 */ 1121 1122 1123 /** @defgroup RCC_AHB_Clock_Sleep_Enabled_Disabled_Status AHB Peripheral Clock Sleep Enabled or Disabled Status 1124 * @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not. 1125 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1126 * power consumption. 1127 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1128 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1129 * @{ 1130 */ 1131 1132 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET) 1133 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN)!= RESET) 1134 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET) 1135 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET) 1136 1137 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) == RESET) 1138 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_FLASHSMEN) == RESET) 1139 #define __HAL_RCC_SRAM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) == RESET) 1140 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) == RESET) 1141 1142 1143 /** 1144 * @} 1145 */ 1146 1147 /** @defgroup RCC_IOPORT_Clock_Sleep_Enabled_Disabled_Status IOPORT Clock Sleep Enabled or Disabled Status 1148 * @brief Check whether the IOPORT clock during Low Power (Sleep) mode is enabled or not. 1149 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1150 * power consumption. 1151 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1152 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1153 * @{ 1154 */ 1155 1156 1157 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN)!= RESET) 1158 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN)!= RESET) 1159 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN)!= RESET) 1160 #if defined (STM32C031xx) 1161 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN)!= RESET) 1162 #endif 1163 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN)!= RESET) 1164 1165 1166 1167 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) == RESET) 1168 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) == RESET) 1169 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) == RESET) 1170 #if defined (STM32C031xx) 1171 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIODSMEN) == RESET) 1172 #endif 1173 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOFSMEN) == RESET) 1174 1175 /** 1176 * @} 1177 */ 1178 1179 /** @defgroup RCC_APB1_Clock_Sleep_Enabled_Disabled_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 1180 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 1181 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1182 * power consumption. 1183 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1184 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1185 * @{ 1186 */ 1187 1188 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) != RESET) 1189 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) != RESET) 1190 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) != RESET) 1191 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) != RESET) 1192 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) != RESET) 1193 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) != RESET) 1194 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) != RESET) 1195 1196 1197 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_TIM3SMEN) == RESET) 1198 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_RTCAPBSMEN) == RESET) 1199 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_WWDGSMEN) == RESET) 1200 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_USART2SMEN) == RESET) 1201 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_I2C1SMEN) == RESET) 1202 #define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_DBGSMEN) == RESET) 1203 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR1, RCC_APBSMENR1_PWRSMEN) == RESET) 1204 1205 /** 1206 * @} 1207 */ 1208 1209 /** @defgroup RCC_APB2_Clock_Sleep_Enabled_Disabled_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 1210 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 1211 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 1212 * power consumption. 1213 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 1214 * @note By default, all peripheral clocks are enabled during SLEEP mode. 1215 * @{ 1216 */ 1217 1218 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) != RESET) 1219 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) != RESET) 1220 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) != RESET) 1221 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) != RESET) 1222 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) != RESET) 1223 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) != RESET) 1224 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) != RESET) 1225 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) != RESET) 1226 1227 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SYSCFGSMEN) == RESET) 1228 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM1SMEN) == RESET) 1229 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_SPI1SMEN) == RESET) 1230 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_USART1SMEN) == RESET) 1231 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM14SMEN) == RESET) 1232 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM16SMEN) == RESET) 1233 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_TIM17SMEN) == RESET) 1234 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APBSMENR2 , RCC_APBSMENR2_ADCSMEN) == RESET) 1235 /** 1236 * @} 1237 */ 1238 1239 1240 /** @defgroup RCC_RTC_Domain_Reset RCC RTC Domain Reset 1241 * @{ 1242 */ 1243 1244 /** @brief Macros to force or release the RTC domain reset. 1245 * @note This function resets the RTC peripheral 1246 * and the RTC clock source selection in RCC_CSR1 register. 1247 * @retval None 1248 */ 1249 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCRST) 1250 1251 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCRST) 1252 1253 /** 1254 * @} 1255 */ 1256 1257 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 1258 * @{ 1259 */ 1260 1261 /** @brief Macros to enable or disable the RTC clock. 1262 * @note These macros must be used after the RTC clock source was selected. 1263 * @retval None 1264 */ 1265 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR1, RCC_CSR1_RTCEN) 1266 1267 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR1, RCC_CSR1_RTCEN) 1268 1269 /** 1270 * @} 1271 */ 1272 1273 /** @defgroup RCC_Clock_Configuration RCC Clock Configuration 1274 * @{ 1275 */ 1276 1277 /** @brief Macros to enable the Internal High Speed oscillator (HSI). 1278 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 1279 * It is used (enabled by hardware) as system clock source after startup 1280 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 1281 * of the HSE used directly or indirectly as system clock (if the Clock 1282 * Security System CSS is enabled). 1283 * @note After enabling the HSI, the application software should wait on HSIRDY 1284 * flag to be set indicating that HSI clock is stable and can be used as 1285 * system clock source. 1286 * This parameter can be: ENABLE or DISABLE. 1287 * @retval None 1288 */ 1289 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 1290 1291 /** @brief Macros to disable the Internal High Speed oscillator (HSI). 1292 * @note HSI can not be stopped if it is used as system clock source. In this case, 1293 * you have to select another source of the system clock then stop the HSI. 1294 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 1295 * clock cycles. 1296 * @retval None 1297 */ 1298 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 1299 1300 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. 1301 * @note The calibration is used to compensate for the variations in voltage 1302 * and temperature that influence the frequency of the internal HSI RC. 1303 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value 1304 * (default is RCC_HSICALIBRATION_DEFAULT). 1305 * This parameter must be a number between 0 and 127. 1306 * @retval None 1307 */ 1308 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 1309 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) 1310 1311 /** 1312 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 1313 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 1314 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 1315 * speed because of the HSI startup time. 1316 * @note The enable of this function has not effect on the HSION bit. 1317 * This parameter can be: ENABLE or DISABLE. 1318 * @retval None 1319 */ 1320 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 1321 1322 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 1323 1324 /** @brief Macro to configure the HSISYS clock. 1325 * @param __HSIDIV__ specifies the HSI16 division factor. 1326 * This parameter can be one of the following values: 1327 * @arg @ref RCC_HSI_DIV1 HSI clock source is divided by 1 1328 * @arg @ref RCC_HSI_DIV2 HSI clock source is divided by 2 1329 * @arg @ref RCC_HSI_DIV4 HSI clock source is divided by 4 1330 * @arg @ref RCC_HSI_DIV8 HSI clock source is divided by 8 1331 * @arg @ref RCC_HSI_DIV16 HSI clock source is divided by 16 1332 * @arg @ref RCC_HSI_DIV32 HSI clock source is divided by 32 1333 * @arg @ref RCC_HSI_DIV64 HSI clock source is divided by 64 1334 * @arg @ref RCC_HSI_DIV128 HSI clock source is divided by 128 1335 */ 1336 #define __HAL_RCC_HSI_CONFIG(__HSIDIV__) \ 1337 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, (__HSIDIV__)) 1338 1339 /** @brief Macro to get the HSI divider. 1340 * @retval The HSI divider. The returned value can be one 1341 * of the following: 1342 * - RCC_CR_HSIDIV_1 HSI oscillator divided by 1 1343 * - RCC_CR_HSIDIV_2 HSI oscillator divided by 2 1344 * - RCC_CR_HSIDIV_4 HSI oscillator divided by 4 (default after reset) 1345 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 8 1346 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 16 1347 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 32 1348 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 64 1349 * - RCC_CR_HSIDIV_8 HSI oscillator divided by 128 1350 */ 1351 #define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV))) 1352 1353 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 1354 * @note After enabling the LSI, the application software should wait on 1355 * LSIRDY flag to be set indicating that LSI clock is stable and can 1356 * be used to clock the IWDG and/or the RTC. 1357 * @note LSI can not be disabled if the IWDG is running. 1358 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 1359 * clock cycles. 1360 * @retval None 1361 */ 1362 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR2, RCC_CSR2_LSION) 1363 1364 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR2, RCC_CSR2_LSION) 1365 1366 /** 1367 * @brief Macro to configure the External High Speed oscillator (HSE). 1368 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 1369 * supported by this macro. User should request a transition to HSE Off 1370 * first and then HSE On or HSE Bypass. 1371 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 1372 * software should wait on HSERDY flag to be set indicating that HSE clock 1373 * is stable and can be used to clock the PLL and/or system clock. 1374 * @note HSE state can not be changed if it is used directly or through the 1375 * PLL as system clock. In this case, you have to select another source 1376 * of the system clock then change the HSE state (ex. disable it). 1377 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 1378 * @note This function reset the CSSON bit, so if the clock security system(CSS) 1379 * was previously enabled you have to enable it again after calling this 1380 * function. 1381 * @param __STATE__ specifies the new state of the HSE. 1382 * This parameter can be one of the following values: 1383 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 1384 * 6 HSE oscillator clock cycles. 1385 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 1386 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 1387 * @retval None 1388 */ 1389 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 1390 do { \ 1391 if((__STATE__) == RCC_HSE_ON) \ 1392 { \ 1393 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1394 } \ 1395 else if((__STATE__) == RCC_HSE_BYPASS) \ 1396 { \ 1397 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1398 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 1399 } \ 1400 else \ 1401 { \ 1402 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 1403 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 1404 } \ 1405 } while(0U) 1406 1407 /** 1408 * @brief Macro to configure the External Low Speed oscillator (LSE). 1409 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 1410 * supported by this macro. User should request a transition to LSE Off 1411 * first and then LSE On or LSE Bypass. 1412 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 1413 * software should wait on LSERDY flag to be set indicating that LSE clock 1414 * is stable and can be used to clock the RTC. 1415 * @param __STATE__ specifies the new state of the LSE. 1416 * This parameter can be one of the following values: 1417 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 1418 * 6 LSE oscillator clock cycles. 1419 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 1420 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 1421 * @retval None 1422 */ 1423 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 1424 do { \ 1425 if((__STATE__) == RCC_LSE_ON) \ 1426 { \ 1427 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1428 } \ 1429 else if((__STATE__) == RCC_LSE_BYPASS) \ 1430 { \ 1431 SET_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ 1432 SET_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1433 } \ 1434 else \ 1435 { \ 1436 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEON); \ 1437 CLEAR_BIT(RCC->CSR1, RCC_CSR1_LSEBYP); \ 1438 } \ 1439 } while(0U) 1440 /** 1441 * @} 1442 */ 1443 1444 /** @addtogroup RCC_RTC_Clock_Configuration 1445 * @{ 1446 */ 1447 1448 /** @brief Macros to configure the RTC clock (RTCCLK). 1449 * @note As the RTC clock configuration bits are in the RTC domain and write 1450 * access is denied to this domain after reset, you have to enable write 1451 * access using the Power RTC Access macro before to configure 1452 * the RTC clock source (to be done once after reset). 1453 * @note Once the RTC clock is configured it cannot be changed unless the 1454 * RTC domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 1455 * a Power On Reset (POR). 1456 * 1457 * @param __RTC_CLKSOURCE__ specifies the RTC clock source. 1458 * This parameter can be one of the following values: 1459 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 1460 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1461 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1462 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1463 * 1464 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 1465 * work in STOP and STANDBY modes, and can be used as wakeup source. 1466 * However, when the HSE clock is used as RTC clock source, the RTC 1467 * cannot be used in STOP and STANDBY modes. 1468 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 1469 * RTC clock source). 1470 * @retval None 1471 */ 1472 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 1473 MODIFY_REG( RCC->CSR1, RCC_CSR1_RTCSEL, (__RTC_CLKSOURCE__)) 1474 1475 1476 /** @brief Macro to get the RTC clock source. 1477 * @retval The returned value can be one of the following: 1478 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock. 1479 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 1480 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 1481 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 1482 */ 1483 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL))) 1484 1485 /** 1486 * @} 1487 */ 1488 1489 /** @addtogroup RCC_Clock_Configuration 1490 * @{ 1491 */ 1492 1493 1494 /** 1495 * @brief Macro to configure the system clock source. 1496 * @param __SYSCLKSOURCE__ specifies the system clock source. 1497 * This parameter can be one of the following values: 1498 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. 1499 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. 1500 * @arg @ref RCC_SYSCLKSOURCE_LSI LSI oscillator is used as system clock source. 1501 * @arg @ref RCC_SYSCLKSOURCE_LSE LSE oscillator is used as system clock source. 1502 * @retval None 1503 */ 1504 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 1505 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 1506 1507 /** @brief Macro to get the clock source used as system clock. 1508 * @retval The clock source used as system clock. The returned value can be one 1509 * of the following: 1510 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock. 1511 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock. 1512 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSI LSI used as system clock source. 1513 * @arg @ref RCC_SYSCLKSOURCE_STATUS_LSE LSE used as system clock source. 1514 */ 1515 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) 1516 1517 /** 1518 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 1519 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability. 1520 * This parameter can be one of the following values: 1521 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 1522 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 1523 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 1524 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 1525 * @retval None 1526 */ 1527 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 1528 MODIFY_REG(RCC->CSR1, RCC_CSR1_LSEDRV, (uint32_t)(__LSEDRIVE__)) 1529 1530 /** @brief Macro to configure the MCO clock. 1531 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1532 * This parameter can be one of the following values: 1533 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 1534 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 1535 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 1536 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source 1537 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 1538 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 1539 * @param __MCODIV__ specifies the MCO clock prescaler. 1540 * This parameter can be one of the following values: 1541 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 1542 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 1543 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 1544 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 1545 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 1546 * @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32 1547 * @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64 1548 * @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128 1549 */ 1550 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1551 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1552 1553 1554 /** @brief Macro to configure the MCO clock. 1555 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 1556 * This parameter can be one of the following values: 1557 * @arg @ref RCC_MCO2SOURCE_NOCLOCK MCO output disabled 1558 * @arg @ref RCC_MCO2SOURCE_SYSCLK System clock selected as MCO source 1559 * @arg @ref RCC_MCO2SOURCE_HSI HSI clock selected as MCO source 1560 * @arg @ref RCC_MCO2SOURCE_HSE HSE clock selected as MCO source 1561 * @arg @ref RCC_MCO2SOURCE_LSI LSI clock selected as MCO source 1562 * @arg @ref RCC_MCO2SOURCE_LSE LSE clock selected as MCO source 1563 * @param __MCODIV__ specifies the MCO clock prescaler. 1564 * This parameter can be one of the following values: 1565 * @arg @ref RCC_MCO2DIV_1 MCO clock source is divided by 1 1566 * @arg @ref RCC_MCO2DIV_2 MCO clock source is divided by 2 1567 * @arg @ref RCC_MCO2DIV_4 MCO clock source is divided by 4 1568 * @arg @ref RCC_MCO2DIV_8 MCO clock source is divided by 8 1569 * @arg @ref RCC_MCO2DIV_16 MCO clock source is divided by 16 1570 * @arg @ref RCC_MCO2DIV_32 MCO clock source is divided by 32 1571 * @arg @ref RCC_MCO2DIV_64 MCO clock source is divided by 64 1572 * @arg @ref RCC_MCO2DIV_128 MCO clock source is divided by 128 1573 */ 1574 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 1575 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 1576 /** 1577 * @} 1578 */ 1579 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 1580 * @brief macros to manage the specified RCC Flags and interrupts. 1581 * @{ 1582 */ 1583 1584 /** @brief Enable RCC interrupt. 1585 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. 1586 * This parameter can be any combination of the following values: 1587 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1588 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1589 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1590 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1591 * @retval None 1592 */ 1593 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 1594 1595 /** @brief Disable RCC interrupt. 1596 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. 1597 * This parameter can be any combination of the following values: 1598 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1599 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1600 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1601 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1602 * @retval None 1603 */ 1604 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 1605 1606 /** @brief Clear RCC interrupt pending bits. 1607 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 1608 * This parameter can be any combination of the following values: 1609 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1610 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1611 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1612 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1613 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 1614 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 1615 * @retval None 1616 */ 1617 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 1618 1619 /** @brief Check whether the RCC interrupt has occurred or not. 1620 * @param __INTERRUPT__ specifies the RCC interrupt source to check. 1621 * This parameter can be one of the following values: 1622 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 1623 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 1624 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 1625 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 1626 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 1627 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 1628 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 1629 */ 1630 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 1631 1632 /** @brief Set RMVF bit to clear the reset flags. 1633 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PWRRST, 1634 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 1635 * @retval None 1636 */ 1637 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR2 |= RCC_CSR2_RMVF) 1638 1639 /** @brief Check whether the selected RCC flag is set or not. 1640 * @param __FLAG__ specifies the flag to check. 1641 * This parameter can be one of the following values: 1642 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 1643 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 1644 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 1645 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 1646 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 1647 * @arg @ref RCC_FLAG_PWRRST BOR or POR/PDR reset 1648 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 1649 * @arg @ref RCC_FLAG_PINRST Pin reset 1650 * @arg @ref RCC_FLAG_SFTRST Software reset 1651 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 1652 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 1653 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 1654 * @retval The new state of __FLAG__ (TRUE or FALSE). 1655 */ 1656 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == RCC_CR_REG_INDEX) ? RCC->CR : \ 1657 ((((__FLAG__) >> 5U) == RCC_CSR1_REG_INDEX) ? RCC->CSR1 : \ 1658 ((((__FLAG__) >> 5U) == RCC_CSR2_REG_INDEX) ? RCC->CSR2 : RCC->CIFR))) & \ 1659 (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 1660 ? 1U : 0U) 1661 1662 /** 1663 * @} 1664 */ 1665 1666 /** 1667 * @} 1668 */ 1669 1670 /* Include RCC HAL Extended module */ 1671 #include "stm32c0xx_hal_rcc_ex.h" 1672 1673 /* Exported functions --------------------------------------------------------*/ 1674 /** @addtogroup RCC_Exported_Functions 1675 * @{ 1676 */ 1677 1678 1679 /** @addtogroup RCC_Exported_Functions_Group1 1680 * @{ 1681 */ 1682 1683 /* Initialization and de-initialization functions ******************************/ 1684 HAL_StatusTypeDef HAL_RCC_DeInit(void); 1685 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); 1686 HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 1687 1688 /** 1689 * @} 1690 */ 1691 1692 /** @addtogroup RCC_Exported_Functions_Group2 1693 * @{ 1694 */ 1695 1696 /* Peripheral Control functions ************************************************/ 1697 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 1698 void HAL_RCC_EnableCSS(void); 1699 void HAL_RCC_EnableLSECSS(void); 1700 void HAL_RCC_DisableLSECSS(void); 1701 uint32_t HAL_RCC_GetSysClockFreq(void); 1702 uint32_t HAL_RCC_GetHCLKFreq(void); 1703 uint32_t HAL_RCC_GetPCLK1Freq(void); 1704 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 1705 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 1706 /* LSE & HSE CSS NMI IRQ handler */ 1707 void HAL_RCC_NMI_IRQHandler(void); 1708 /* User Callbacks in non blocking mode (IT mode) */ 1709 void HAL_RCC_CSSCallback(void); 1710 void HAL_RCC_LSECSSCallback(void); 1711 1712 /** 1713 * @} 1714 */ 1715 1716 /** 1717 * @} 1718 */ 1719 1720 /** 1721 * @} 1722 */ 1723 1724 /** 1725 * @} 1726 */ 1727 1728 #ifdef __cplusplus 1729 } 1730 #endif 1731 1732 #endif /* STM32C0xx_HAL_RCC_H */ 1733
