1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_spi.c
4 * @author MCD Application Team
5 * @brief SPI LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wlxx_ll_spi.h"
22 #include "stm32wlxx_ll_bus.h"
23 #include "stm32wlxx_ll_rcc.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30
31 /** @addtogroup STM32WLxx_LL_Driver
32 * @{
33 */
34
35 #if defined (SPI1) || defined (SPI2)
36
37 /** @addtogroup SPI_LL
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
46 * @{
47 */
48 /* SPI registers Masks */
49 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
54 /**
55 * @}
56 */
57
58 /* Private macros ------------------------------------------------------------*/
59 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
60 * @{
61 */
62 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
72 || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
73 || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
74 || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
75 || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
76 || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
77 || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
78 || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
79 || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
80 || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
81 || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
82 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
83
84 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
85 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
86
87 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
88 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
89
90 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
91 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
92 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
93
94 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
95 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
96 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
97 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
98 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
99 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
100 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
102
103 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
104 || ((__VALUE__) == LL_SPI_MSB_FIRST))
105
106 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
107 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
108
109 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
110
111 /**
112 * @}
113 */
114
115 /* Private function prototypes -----------------------------------------------*/
116
117 /* Exported functions --------------------------------------------------------*/
118 /** @addtogroup SPI_LL_Exported_Functions
119 * @{
120 */
121
122 /** @addtogroup SPI_LL_EF_Init
123 * @{
124 */
125
126 /**
127 * @brief De-initialize the SPI registers to their default reset values.
128 * @param SPIx SPI Instance
129 * @retval An ErrorStatus enumeration value:
130 * - SUCCESS: SPI registers are de-initialized
131 * - ERROR: SPI registers are not de-initialized
132 */
LL_SPI_DeInit(SPI_TypeDef * SPIx)133 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
134 {
135 ErrorStatus status = ERROR;
136
137 /* Check the parameters */
138 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
139
140 #if defined(SPI1)
141 if (SPIx == SPI1)
142 {
143 /* Force reset of SPI clock */
144 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
145
146 /* Release reset of SPI clock */
147 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
148
149 status = SUCCESS;
150 }
151 #endif /* SPI1 */
152 #if defined(SPI2)
153 if (SPIx == SPI2)
154 {
155 /* Force reset of SPI clock */
156 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
157
158 /* Release reset of SPI clock */
159 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
160
161 status = SUCCESS;
162 }
163 #endif /* SPI2 */
164
165 return status;
166 }
167
168 /**
169 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
170 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
171 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
172 * @param SPIx SPI Instance
173 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
174 * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
175 */
LL_SPI_Init(SPI_TypeDef * SPIx,LL_SPI_InitTypeDef * SPI_InitStruct)176 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
177 {
178 ErrorStatus status = ERROR;
179
180 /* Check the SPI Instance SPIx*/
181 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
182
183 /* Check the SPI parameters from SPI_InitStruct*/
184 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
185 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
186 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
187 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
188 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
189 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
190 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
191 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
192 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
193
194 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
195 {
196 /*---------------------------- SPIx CR1 Configuration ------------------------
197 * Configure SPIx CR1 with parameters:
198 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
199 * - Master/Slave Mode: SPI_CR1_MSTR bit
200 * - ClockPolarity: SPI_CR1_CPOL bit
201 * - ClockPhase: SPI_CR1_CPHA bit
202 * - NSS management: SPI_CR1_SSM bit
203 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
204 * - BitOrder: SPI_CR1_LSBFIRST bit
205 * - CRCCalculation: SPI_CR1_CRCEN bit
206 */
207 MODIFY_REG(SPIx->CR1,
208 SPI_CR1_CLEAR_MASK,
209 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
210 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
211 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
212 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
213
214 /*---------------------------- SPIx CR2 Configuration ------------------------
215 * Configure SPIx CR2 with parameters:
216 * - DataWidth: DS[3:0] bits
217 * - NSS management: SSOE bit
218 */
219 MODIFY_REG(SPIx->CR2,
220 SPI_CR2_DS | SPI_CR2_SSOE,
221 SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
222
223 /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */
224 if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT)
225 {
226 LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER);
227 }
228
229 /*---------------------------- SPIx CRCPR Configuration ----------------------
230 * Configure SPIx CRCPR with parameters:
231 * - CRCPoly: CRCPOLY[15:0] bits
232 */
233 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
234 {
235 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
236 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
237 }
238 status = SUCCESS;
239 }
240
241 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
242 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
243 return status;
244 }
245
246 /**
247 * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
248 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
249 * whose fields will be set to default values.
250 * @retval None
251 */
LL_SPI_StructInit(LL_SPI_InitTypeDef * SPI_InitStruct)252 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
253 {
254 /* Set SPI_InitStruct fields to default values */
255 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
256 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
257 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
258 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
259 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
260 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
261 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
262 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
263 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
264 SPI_InitStruct->CRCPoly = 7U;
265 }
266
267 /**
268 * @}
269 */
270
271 /**
272 * @}
273 */
274
275 /**
276 * @}
277 */
278
279 /** @addtogroup I2S_LL
280 * @{
281 */
282
283 /* Private types -------------------------------------------------------------*/
284 /* Private variables ---------------------------------------------------------*/
285 /* Private constants ---------------------------------------------------------*/
286 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
287 * @{
288 */
289 /* I2S registers Masks */
290 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
291 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
292 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
293
294 #define I2S_I2SPR_CLEAR_MASK 0x0002U
295 /**
296 * @}
297 */
298 /* Private macros ------------------------------------------------------------*/
299 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
300 * @{
301 */
302
303 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
304 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
305 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
306 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
307
308 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
309 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
310
311 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
312 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
313 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
314 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
315 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
316
317 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
318 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
319 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
320 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
321
322 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
323 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
324
325 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
326 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
327 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
328
329 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
330
331 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
332 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
333 /**
334 * @}
335 */
336
337 /* Private function prototypes -----------------------------------------------*/
338
339 /* Exported functions --------------------------------------------------------*/
340 /** @addtogroup I2S_LL_Exported_Functions
341 * @{
342 */
343
344 /** @addtogroup I2S_LL_EF_Init
345 * @{
346 */
347
348 /**
349 * @brief De-initialize the SPI/I2S registers to their default reset values.
350 * @param SPIx SPI Instance
351 * @retval An ErrorStatus enumeration value:
352 * - SUCCESS: SPI registers are de-initialized
353 * - ERROR: SPI registers are not de-initialized
354 */
LL_I2S_DeInit(SPI_TypeDef * SPIx)355 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
356 {
357 return LL_SPI_DeInit(SPIx);
358 }
359
360 /**
361 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
362 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
363 * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
364 * @param SPIx SPI Instance
365 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
366 * @retval An ErrorStatus enumeration value:
367 * - SUCCESS: SPI registers are Initialized
368 * - ERROR: SPI registers are not Initialized
369 */
LL_I2S_Init(SPI_TypeDef * SPIx,LL_I2S_InitTypeDef * I2S_InitStruct)370 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
371 {
372 uint32_t i2sdiv = 2U;
373 uint32_t i2sodd = 0U;
374 uint32_t packetlength = 1U;
375 uint32_t tmp;
376 LL_RCC_ClocksTypeDef rcc_clocks;
377 uint32_t sourceclock;
378 ErrorStatus status = ERROR;
379
380 /* Check the I2S parameters */
381 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
382 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
383 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
384 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
385 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
386 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
387 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
388
389 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
390 {
391 /*---------------------------- SPIx I2SCFGR Configuration --------------------
392 * Configure SPIx I2SCFGR with parameters:
393 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
394 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
395 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
396 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
397 */
398
399 /* Write to SPIx I2SCFGR */
400 MODIFY_REG(SPIx->I2SCFGR,
401 I2S_I2SCFGR_CLEAR_MASK,
402 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
403 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
404 SPI_I2SCFGR_I2SMOD);
405
406 /*---------------------------- SPIx I2SPR Configuration ----------------------
407 * Configure SPIx I2SPR with parameters:
408 * - MCLKOutput: SPI_I2SPR_MCKOE bit
409 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
410 */
411
412 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
413 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
414 */
415 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
416 {
417 /* Check the frame length (For the Prescaler computing)
418 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
419 */
420 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
421 {
422 /* Packet length is 32 bits */
423 packetlength = 2U;
424 }
425
426 /* I2S Clock source is System clock: Get System Clock frequency */
427 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
428
429 /* Get the source clock value: based on System Clock value */
430 sourceclock = rcc_clocks.SYSCLK_Frequency;
431
432 /* Compute the Real divider depending on the MCLK output state with a floating point */
433 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
434 {
435 /* MCLK output is enabled */
436 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
437 }
438 else
439 {
440 /* MCLK output is disabled */
441 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
442 }
443
444 /* Remove the floating point */
445 tmp = tmp / 10U;
446
447 /* Check the parity of the divider */
448 i2sodd = (tmp & (uint16_t)0x0001U);
449
450 /* Compute the i2sdiv prescaler */
451 i2sdiv = ((tmp - i2sodd) / 2U);
452
453 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
454 i2sodd = (i2sodd << 8U);
455 }
456
457 /* Test if the divider is 1 or 0 or greater than 0xFF */
458 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
459 {
460 /* Set the default values */
461 i2sdiv = 2U;
462 i2sodd = 0U;
463 }
464
465 /* Write to SPIx I2SPR register the computed value */
466 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
467
468 status = SUCCESS;
469 }
470 return status;
471 }
472
473 /**
474 * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
475 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
476 * whose fields will be set to default values.
477 * @retval None
478 */
LL_I2S_StructInit(LL_I2S_InitTypeDef * I2S_InitStruct)479 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
480 {
481 /*--------------- Reset I2S init structure parameters values -----------------*/
482 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
483 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
484 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
485 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
486 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
487 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
488 }
489
490 /**
491 * @brief Set linear and parity prescaler.
492 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
493 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
494 * @param SPIx SPI Instance
495 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
496 * @param PrescalerParity This parameter can be one of the following values:
497 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
498 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
499 * @retval None
500 */
LL_I2S_ConfigPrescaler(SPI_TypeDef * SPIx,uint32_t PrescalerLinear,uint32_t PrescalerParity)501 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
502 {
503 /* Check the I2S parameters */
504 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
505 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
506 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
507
508 /* Write to SPIx I2SPR */
509 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
510 }
511
512 /**
513 * @}
514 */
515
516 /**
517 * @}
518 */
519
520 /**
521 * @}
522 */
523
524 #endif /* defined (SPI1) || defined (SPI2) */
525
526 /**
527 * @}
528 */
529
530 #endif /* USE_FULL_LL_DRIVER */
531
532
