1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wlxx_ll_dma.h"
22 #include "stm32wlxx_ll_bus.h"
23 #ifdef USE_FULL_ASSERT
24 #include "stm32_assert.h"
25 #else
26 #define assert_param(expr) ((void)0U)
27 #endif /* USE_FULL_ASSERT */
28
29 /** @addtogroup STM32WLxx_LL_Driver
30 * @{
31 */
32
33 #if defined (DMA1) || defined (DMA2)
34
35 /** @defgroup DMA_LL DMA
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /* Private constants ---------------------------------------------------------*/
42 /* Private macros ------------------------------------------------------------*/
43 /** @addtogroup DMA_LL_Private_Macros
44 * @{
45 */
46 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
47 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
48 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
49
50 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
51 ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
52
53 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
54 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
55
56 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
57 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
58
59 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
60 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
61 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
62
63 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
64 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
65 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
66
67 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
68
69 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__) ((__VALUE__) <= LL_DMAMUX_MAX_REQ)
70
71 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
72 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
73 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
74 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
75
76 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
77 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
78 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
79 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
80 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
81 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
82 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
83 ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
84 (((INSTANCE) == DMA2) && \
85 (((CHANNEL) == LL_DMA_CHANNEL_1) || \
86 ((CHANNEL) == LL_DMA_CHANNEL_2) || \
87 ((CHANNEL) == LL_DMA_CHANNEL_3) || \
88 ((CHANNEL) == LL_DMA_CHANNEL_4) || \
89 ((CHANNEL) == LL_DMA_CHANNEL_5) || \
90 ((CHANNEL) == LL_DMA_CHANNEL_6) || \
91 ((CHANNEL) == LL_DMA_CHANNEL_7))))
92 /**
93 * @}
94 */
95
96 /* Private function prototypes -----------------------------------------------*/
97
98 /* Exported functions --------------------------------------------------------*/
99 /** @addtogroup DMA_LL_Exported_Functions
100 * @{
101 */
102
103 /** @addtogroup DMA_LL_EF_Init
104 * @{
105 */
106
107 /**
108 * @brief De-initialize the DMA registers to their default reset values.
109 * @param DMAx DMAx Instance
110 * @param Channel This parameter can be one of the following values:
111 * @arg @ref LL_DMA_CHANNEL_1
112 * @arg @ref LL_DMA_CHANNEL_2
113 * @arg @ref LL_DMA_CHANNEL_3
114 * @arg @ref LL_DMA_CHANNEL_4
115 * @arg @ref LL_DMA_CHANNEL_5
116 * @arg @ref LL_DMA_CHANNEL_6
117 * @arg @ref LL_DMA_CHANNEL_7
118 * @arg @ref LL_DMA_CHANNEL_ALL
119 * @retval An ErrorStatus enumeration value:
120 * - SUCCESS: DMA registers are de-initialized
121 * - ERROR: DMA registers are not de-initialized
122 */
LL_DMA_DeInit(DMA_TypeDef * DMAx,uint32_t Channel)123 ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
124 {
125 ErrorStatus status = SUCCESS;
126
127 /* Check the DMA Instance DMAx and Channel parameters*/
128 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
129
130 if (Channel == LL_DMA_CHANNEL_ALL)
131 {
132 if (DMAx == DMA1)
133 {
134 /* Force reset of DMA clock */
135 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
136
137 /* Release reset of DMA clock */
138 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
139 }
140 #if defined(DMA2)
141 else if (DMAx == DMA2)
142 {
143 /* Force reset of DMA clock */
144 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
145
146 /* Release reset of DMA clock */
147 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
148 }
149 #endif /* DMA2 */
150 else
151 {
152 status = ERROR;
153 }
154 }
155 else
156 {
157 DMA_Channel_TypeDef *tmp;
158
159 tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
160
161 /* Disable the selected DMAx_Channely */
162 CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
163
164 /* Reset DMAx_Channely control register */
165 WRITE_REG(tmp->CCR, 0U);
166
167 /* Reset DMAx_Channely remaining bytes register */
168 WRITE_REG(tmp->CNDTR, 0U);
169
170 /* Reset DMAx_Channely peripheral address register */
171 WRITE_REG(tmp->CPAR, 0U);
172
173 /* Reset DMAx_Channely memory address register */
174 WRITE_REG(tmp->CMAR, 0U);
175
176 /* Reset Request register field for DMAx Channel */
177 LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
178
179 if (Channel == LL_DMA_CHANNEL_1)
180 {
181 /* Reset interrupt pending bits for DMAx Channel1 */
182 LL_DMA_ClearFlag_GI1(DMAx);
183 }
184 else if (Channel == LL_DMA_CHANNEL_2)
185 {
186 /* Reset interrupt pending bits for DMAx Channel2 */
187 LL_DMA_ClearFlag_GI2(DMAx);
188 }
189 else if (Channel == LL_DMA_CHANNEL_3)
190 {
191 /* Reset interrupt pending bits for DMAx Channel3 */
192 LL_DMA_ClearFlag_GI3(DMAx);
193 }
194 else if (Channel == LL_DMA_CHANNEL_4)
195 {
196 /* Reset interrupt pending bits for DMAx Channel4 */
197 LL_DMA_ClearFlag_GI4(DMAx);
198 }
199 else if (Channel == LL_DMA_CHANNEL_5)
200 {
201 /* Reset interrupt pending bits for DMAx Channel5 */
202 LL_DMA_ClearFlag_GI5(DMAx);
203 }
204 else if (Channel == LL_DMA_CHANNEL_6)
205 {
206 /* Reset interrupt pending bits for DMAx Channel6 */
207 LL_DMA_ClearFlag_GI6(DMAx);
208 }
209 else if (Channel == LL_DMA_CHANNEL_7)
210 {
211 /* Reset interrupt pending bits for DMAx Channel7 */
212 LL_DMA_ClearFlag_GI7(DMAx);
213 }
214 else
215 {
216 status = ERROR;
217 }
218 }
219
220 return status;
221 }
222
223 /**
224 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
225 * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
226 * @arg @ref __LL_DMA_GET_INSTANCE
227 * @arg @ref __LL_DMA_GET_CHANNEL
228 * @param DMAx DMAx Instance
229 * @param Channel This parameter can be one of the following values:
230 * @arg @ref LL_DMA_CHANNEL_1
231 * @arg @ref LL_DMA_CHANNEL_2
232 * @arg @ref LL_DMA_CHANNEL_3
233 * @arg @ref LL_DMA_CHANNEL_4
234 * @arg @ref LL_DMA_CHANNEL_5
235 * @arg @ref LL_DMA_CHANNEL_6
236 * @arg @ref LL_DMA_CHANNEL_7
237 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
238 * @retval An ErrorStatus enumeration value:
239 * - SUCCESS: DMA registers are initialized
240 * - ERROR: Not applicable
241 */
LL_DMA_Init(DMA_TypeDef * DMAx,uint32_t Channel,LL_DMA_InitTypeDef * DMA_InitStruct)242 ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
243 {
244 /* Check the DMA Instance DMAx and Channel parameters*/
245 assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
246
247 /* Check the DMA parameters from DMA_InitStruct */
248 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
249 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
250 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
251 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
252 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
253 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
254 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
255 assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
256 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
257
258 /*---------------------------- DMAx CCR Configuration ------------------------
259 * Configure DMAx_Channely: data transfer direction, data transfer mode,
260 * peripheral and memory increment mode,
261 * data size alignment and priority level with parameters :
262 * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
263 * - Mode: DMA_CCR_CIRC bit
264 * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
265 * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
266 * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
267 * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
268 * - Priority: DMA_CCR_PL[1:0] bits
269 */
270 LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
271 DMA_InitStruct->Mode | \
272 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
273 DMA_InitStruct->MemoryOrM2MDstIncMode | \
274 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
275 DMA_InitStruct->MemoryOrM2MDstDataSize | \
276 DMA_InitStruct->Priority);
277
278 /*-------------------------- DMAx CMAR Configuration -------------------------
279 * Configure the memory or destination base address with parameter :
280 * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
281 */
282 LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
283
284 /*-------------------------- DMAx CPAR Configuration -------------------------
285 * Configure the peripheral or source base address with parameter :
286 * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
287 */
288 LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
289
290 /*--------------------------- DMAx CNDTR Configuration -----------------------
291 * Configure the peripheral base address with parameter :
292 * - NbData: DMA_CNDTR_NDT[15:0] bits
293 */
294 LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
295
296 /*--------------------------- DMAMUXx CCR Configuration ----------------------
297 * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
298 * - PeriphRequest: DMA_CxCR[7:0] bits
299 */
300 LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
301
302 return SUCCESS;
303 }
304
305 /**
306 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
307 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
308 * @retval None
309 */
LL_DMA_StructInit(LL_DMA_InitTypeDef * DMA_InitStruct)310 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
311 {
312 /* Set DMA_InitStruct fields to default values */
313 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
314 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
315 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
316 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
317 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
318 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
319 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
320 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
321 DMA_InitStruct->NbData = 0x00000000U;
322 DMA_InitStruct->PeriphRequest = LL_DMAMUX_REQ_MEM2MEM;
323 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
324 }
325
326 /**
327 * @}
328 */
329
330 /**
331 * @}
332 */
333
334 /**
335 * @}
336 */
337
338 #endif /* DMA1 || DMA2 */
339
340 /**
341 * @}
342 */
343
344 #endif /* USE_FULL_LL_DRIVER */
345
