1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18 #if defined(USE_FULL_LL_DRIVER)
19
20 /* Includes ------------------------------------------------------------------*/
21 #include "stm32wlxx_ll_adc.h"
22 #include "stm32wlxx_ll_bus.h"
23
24 #ifdef USE_FULL_ASSERT
25 #include "stm32_assert.h"
26 #else
27 #define assert_param(expr) ((void)0U)
28 #endif /* USE_FULL_ASSERT */
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC)
35
36 /** @addtogroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /** @addtogroup ADC_LL_Private_Constants
44 * @{
45 */
46
47 /* Definitions of ADC hardware constraints delays */
48 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
49 /* not timeout values: */
50 /* Timeout values for ADC operations are dependent to device clock */
51 /* configuration (system clock versus ADC clock), */
52 /* and therefore must be defined in user application. */
53 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
54 /* values definition. */
55 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
56 /* of device clock setting. */
57 /* In user application, ADC timeout values should be defined with */
58 /* temporal values, in function of device clock settings. */
59 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
60 /* - ADC clock from synchronous clock with AHB prescaler 512, */
61 /* APB prescaler 16, ADC prescaler 4. */
62 /* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
63 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
64 /* CPU clock frequency max 48MHz, HSI frequency 16MHz: ratio 4. */
65 /* Unit: CPU cycles. */
66 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
67 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
68 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
69 /* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
70 /* after the channel configuration has been changed. */
71 /* Driver timeout is approximated to 6 CPU cycles. */
72 #define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
73
74 /**
75 * @}
76 */
77
78 /* Private macros ------------------------------------------------------------*/
79
80 /** @addtogroup ADC_LL_Private_Macros
81 * @{
82 */
83
84 /* Check of parameters for configuration of ADC hierarchical scope: */
85 /* common to several ADC instances. */
86 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
87 (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
99 )
100
101 #define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \
102 (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \
103 || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \
104 )
105
106 /* Check of parameters for configuration of ADC hierarchical scope: */
107 /* ADC instance. */
108 #define IS_LL_ADC_CLOCK(__CLOCK__) \
109 (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
110 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
111 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
113 )
114
115 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
116 (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
117 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
118 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
119 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
120 )
121
122 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
123 (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
124 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
125 )
126
127 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
128 (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
129 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
130 || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
131 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
132 )
133
134 /* Check of parameters for configuration of ADC hierarchical scope: */
135 /* ADC group regular */
136 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
137 (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
144 )
145
146 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
147 (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
148 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
149 )
150
151 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
152 (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
153 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
154 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
155 )
156
157 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
158 (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
159 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
160 )
161
162 #define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
163 (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
164 || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
165 )
166
167 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
168 (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
169 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
170 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
171 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
172 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
173 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
174 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
175 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
176 )
177
178 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
179 (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
180 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
181 )
182
183 /**
184 * @}
185 */
186
187
188 /* Private function prototypes -----------------------------------------------*/
189
190 /* Exported functions --------------------------------------------------------*/
191 /** @addtogroup ADC_LL_Exported_Functions
192 * @{
193 */
194
195 /** @addtogroup ADC_LL_EF_Init
196 * @{
197 */
198
199 /**
200 * @brief De-initialize registers of all ADC instances belonging to
201 * the same ADC common instance to their default reset values.
202 * @note This function is performing a hard reset, using high level
203 * clock source RCC ADC reset.
204 * @param ADCxy_COMMON ADC common instance
205 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
206 * @retval An ErrorStatus enumeration value:
207 * - SUCCESS: ADC common registers are de-initialized
208 * - ERROR: not applicable
209 */
LL_ADC_CommonDeInit(ADC_Common_TypeDef * ADCxy_COMMON)210 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
211 {
212 /* Check the parameters */
213 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
214
215 /* Prevent unused argument(s) compilation warning if no assert_param check */
216 (void)(ADCxy_COMMON);
217
218 /* Force reset of ADC clock (core clock) */
219 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
220
221 /* Release reset of ADC clock (core clock) */
222 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
223
224 return SUCCESS;
225 }
226
227 /**
228 * @brief Initialize some features of ADC common parameters
229 * (all ADC instances belonging to the same ADC common instance)
230 * and multimode (for devices with several ADC instances available).
231 * @note The setting of ADC common parameters is conditioned to
232 * ADC instances state:
233 * All ADC instances belonging to the same ADC common instance
234 * must be disabled.
235 * @param ADCxy_COMMON ADC common instance
236 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
237 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
238 * @retval An ErrorStatus enumeration value:
239 * - SUCCESS: ADC common registers are initialized
240 * - ERROR: ADC common registers are not initialized
241 */
LL_ADC_CommonInit(ADC_Common_TypeDef * ADCxy_COMMON,LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)242 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
243 {
244 ErrorStatus status = SUCCESS;
245
246 /* Check the parameters */
247 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
248 assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
249
250 /* Note: Hardware constraint (refer to description of functions */
251 /* "LL_ADC_SetCommonXXX()": */
252 /* On this STM32 series, setting of these features is conditioned to */
253 /* ADC state: */
254 /* All ADC instances of the ADC common group must be disabled. */
255 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
256 {
257 /* Configuration of ADC hierarchical scope: */
258 /* - common to several ADC */
259 /* (all ADC instances belonging to the same ADC common instance) */
260 /* - Set ADC clock (conversion clock) */
261 LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
262 }
263 else
264 {
265 /* Initialization error: One or several ADC instances belonging to */
266 /* the same ADC common instance are not disabled. */
267 status = ERROR;
268 }
269
270 return status;
271 }
272
273 /**
274 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
275 * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
276 * whose fields will be set to default values.
277 * @retval None
278 */
LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef * pADC_CommonInitStruct)279 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
280 {
281 /* Set pADC_CommonInitStruct fields to default values */
282 /* Set fields of ADC common */
283 /* (all ADC instances belonging to the same ADC common instance) */
284 pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
285
286 }
287
288 /**
289 * @brief De-initialize registers of the selected ADC instance
290 * to their default reset values.
291 * @note To reset all ADC instances quickly (perform a hard reset),
292 * use function @ref LL_ADC_CommonDeInit().
293 * @note If this functions returns error status, it means that ADC instance
294 * is in an unknown state.
295 * In this case, perform a hard reset using high level
296 * clock source RCC ADC reset.
297 * Refer to function @ref LL_ADC_CommonDeInit().
298 * @param ADCx ADC instance
299 * @retval An ErrorStatus enumeration value:
300 * - SUCCESS: ADC registers are de-initialized
301 * - ERROR: ADC registers are not de-initialized
302 */
LL_ADC_DeInit(ADC_TypeDef * ADCx)303 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
304 {
305 ErrorStatus status = SUCCESS;
306
307 __IO uint32_t timeout_cpu_cycles = 0UL;
308
309 /* Check the parameters */
310 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
311
312 /* Disable ADC instance if not already disabled. */
313 if (LL_ADC_IsEnabled(ADCx) == 1UL)
314 {
315 /* Set ADC group regular trigger source to SW start to ensure to not */
316 /* have an external trigger event occurring during the conversion stop */
317 /* ADC disable process. */
318 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
319
320 /* Stop potential ADC conversion on going on ADC group regular. */
321 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
322 {
323 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
324 {
325 LL_ADC_REG_StopConversion(ADCx);
326 }
327 }
328
329 /* Wait for ADC conversions are effectively stopped */
330 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
331 while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
332 {
333 timeout_cpu_cycles--;
334 if (timeout_cpu_cycles == 0UL)
335 {
336 /* Time-out error */
337 status = ERROR;
338 break;
339 }
340 }
341
342 /* Disable the ADC instance */
343 LL_ADC_Disable(ADCx);
344
345 /* Wait for ADC instance is effectively disabled */
346 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
347 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
348 {
349 timeout_cpu_cycles--;
350 if (timeout_cpu_cycles == 0UL)
351 {
352 /* Time-out error */
353 status = ERROR;
354 break;
355 }
356 }
357 }
358
359 /* Check whether ADC state is compliant with expected state */
360 if (READ_BIT(ADCx->CR,
361 (ADC_CR_ADSTP | ADC_CR_ADSTART
362 | ADC_CR_ADDIS | ADC_CR_ADEN)
363 )
364 == 0UL)
365 {
366 /* ========== Reset ADC registers ========== */
367 /* Reset register IER */
368 CLEAR_BIT(ADCx->IER,
369 (LL_ADC_IT_ADRDY
370 | LL_ADC_IT_EOC
371 | LL_ADC_IT_EOS
372 | LL_ADC_IT_OVR
373 | LL_ADC_IT_EOSMP
374 | LL_ADC_IT_AWD1
375 | LL_ADC_IT_AWD2
376 | LL_ADC_IT_AWD3
377 | LL_ADC_IT_EOCAL
378 | LL_ADC_IT_CCRDY
379 )
380 );
381
382 /* Reset register ISR */
383 SET_BIT(ADCx->ISR,
384 (LL_ADC_FLAG_ADRDY
385 | LL_ADC_FLAG_EOC
386 | LL_ADC_FLAG_EOS
387 | LL_ADC_FLAG_OVR
388 | LL_ADC_FLAG_EOSMP
389 | LL_ADC_FLAG_AWD1
390 | LL_ADC_FLAG_AWD2
391 | LL_ADC_FLAG_AWD3
392 | LL_ADC_FLAG_EOCAL
393 | LL_ADC_FLAG_CCRDY
394 )
395 );
396
397 /* Reset register CR */
398 /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
399 /* "read-set": no direct reset applicable. */
400 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
401
402 /* Reset register CFGR1 */
403 CLEAR_BIT(ADCx->CFGR1,
404 (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
405 | ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
406 | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
407 | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)
408 );
409
410 /* Reset register SMPR */
411 CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
412
413 /* Reset register AWD1TR */
414 MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, ADC_AWD1TR_HT1);
415
416 /* Reset register AWD2TR */
417 MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2, ADC_AWD2TR_HT2);
418
419 /* Reset register AWD3TR */
420 MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3, ADC_AWD3TR_HT3);
421
422 /* Reset register CHSELR */
423 CLEAR_BIT(ADCx->CHSELR,
424 (ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
425 | ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
426 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
427 | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
428 | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0)
429 );
430
431 /* Wait for ADC channel configuration ready */
432 timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
433 while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
434 {
435 timeout_cpu_cycles--;
436 if (timeout_cpu_cycles == 0UL)
437 {
438 /* Time-out error */
439 status = ERROR;
440 break;
441 }
442 }
443
444 /* Clear flag ADC channel configuration ready */
445 LL_ADC_ClearFlag_CCRDY(ADCx);
446
447 /* Reset register DR */
448 /* bits in access mode read only, no direct reset applicable */
449
450 /* Reset register CALFACT */
451 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
452
453 /* Reset register CFGR2 */
454 /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
455 /* already done above. */
456 /* Note: ADC clock reset at the end of de-initialization because select */
457 /* asynchronous clock source, corresponding to no clock by default */
458 /* on STM32WL. Refer to function "LL_RCC_SetADCClockSource()". */
459 CLEAR_BIT(ADCx->CFGR2,
460 (ADC_CFGR2_CKMODE
461 | ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR
462 | ADC_CFGR2_OVSE)
463 );
464
465 }
466 else
467 {
468 /* ADC instance is in an unknown state */
469 /* Need to performing a hard reset of ADC instance, using high level */
470 /* clock source RCC ADC reset. */
471 /* Caution: On this STM32 series, if several ADC instances are available */
472 /* on the selected device, RCC ADC reset will reset */
473 /* all ADC instances belonging to the common ADC instance. */
474 status = ERROR;
475 }
476
477 return status;
478 }
479
480 /**
481 * @brief Initialize some features of ADC instance.
482 * @note These parameters have an impact on ADC scope: ADC instance.
483 * Refer to corresponding unitary functions into
484 * @ref ADC_LL_EF_Configuration_ADC_Instance .
485 * @note The setting of these parameters by function @ref LL_ADC_Init()
486 * is conditioned to ADC state:
487 * ADC instance must be disabled.
488 * This condition is applied to all ADC features, for efficiency
489 * and compatibility over all STM32 families. However, the different
490 * features can be set under different ADC state conditions
491 * (setting possible with ADC enabled without conversion on going,
492 * ADC enabled with conversion on going, ...)
493 * Each feature can be updated afterwards with a unitary function
494 * and potentially with ADC in a different state than disabled,
495 * refer to description of each function for setting
496 * conditioned to ADC state.
497 * @note After using this function, some other features must be configured
498 * using LL unitary functions.
499 * The minimum configuration remaining to be done is:
500 * - Set ADC group regular sequencer:
501 * Depending on the sequencer mode (refer to
502 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
503 * - map channel on the selected sequencer rank.
504 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
505 * - map channel on rank corresponding to channel number.
506 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
507 * - Set ADC channel sampling time
508 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
509 * Refer to function LL_ADC_SetChannelSamplingTime();
510 * @param ADCx ADC instance
511 * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
512 * @retval An ErrorStatus enumeration value:
513 * - SUCCESS: ADC registers are initialized
514 * - ERROR: ADC registers are not initialized
515 */
LL_ADC_Init(ADC_TypeDef * ADCx,LL_ADC_InitTypeDef * pADC_InitStruct)516 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct)
517 {
518 ErrorStatus status = SUCCESS;
519
520 /* Check the parameters */
521 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
522
523 assert_param(IS_LL_ADC_CLOCK(pADC_InitStruct->Clock));
524 assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
525 assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
526 assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
527
528 /* Note: Hardware constraint (refer to description of this function): */
529 /* ADC instance must be disabled. */
530 if (LL_ADC_IsEnabled(ADCx) == 0UL)
531 {
532 /* Configuration of ADC hierarchical scope: */
533 /* - ADC instance */
534 /* - Set ADC data resolution */
535 /* - Set ADC conversion data alignment */
536 /* - Set ADC low power mode */
537 MODIFY_REG(ADCx->CFGR1,
538 ADC_CFGR1_RES
539 | ADC_CFGR1_ALIGN
540 | ADC_CFGR1_WAIT
541 | ADC_CFGR1_AUTOFF
542 ,
543 pADC_InitStruct->Resolution
544 | pADC_InitStruct->DataAlignment
545 | pADC_InitStruct->LowPowerMode
546 );
547
548 MODIFY_REG(ADCx->CFGR2,
549 ADC_CFGR2_CKMODE
550 ,
551 pADC_InitStruct->Clock
552 );
553 }
554 else
555 {
556 /* Initialization error: ADC instance is not disabled. */
557 status = ERROR;
558 }
559
560 return status;
561 }
562
563 /**
564 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
565 * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
566 * whose fields will be set to default values.
567 * @retval None
568 */
LL_ADC_StructInit(LL_ADC_InitTypeDef * pADC_InitStruct)569 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
570 {
571 /* Set pADC_InitStruct fields to default values */
572 /* Set fields of ADC instance */
573 pADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
574 pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
575 pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
576 pADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
577
578 }
579
580 /**
581 * @brief Initialize some features of ADC group regular.
582 * @note These parameters have an impact on ADC scope: ADC group regular.
583 * Refer to corresponding unitary functions into
584 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
585 * (functions with prefix "REG").
586 * @note The setting of these parameters by function @ref LL_ADC_Init()
587 * is conditioned to ADC state:
588 * ADC instance must be disabled.
589 * This condition is applied to all ADC features, for efficiency
590 * and compatibility over all STM32 families. However, the different
591 * features can be set under different ADC state conditions
592 * (setting possible with ADC enabled without conversion on going,
593 * ADC enabled with conversion on going, ...)
594 * Each feature can be updated afterwards with a unitary function
595 * and potentially with ADC in a different state than disabled,
596 * refer to description of each function for setting
597 * conditioned to ADC state.
598 * @note Before using this function, ADC group regular sequencer
599 * must be configured: refer to function
600 * @ref LL_ADC_REG_SetSequencerConfigurable().
601 * @note After using this function, other features must be configured
602 * using LL unitary functions.
603 * The minimum configuration remaining to be done is:
604 * - Set ADC group regular sequencer:
605 * Depending on the sequencer mode (refer to
606 * function @ref LL_ADC_REG_SetSequencerConfigurable() ):
607 * - map channel on the selected sequencer rank.
608 * Refer to function @ref LL_ADC_REG_SetSequencerRanks();
609 * - map channel on rank corresponding to channel number.
610 * Refer to function @ref LL_ADC_REG_SetSequencerChannels();
611 * - Set ADC channel sampling time
612 * Refer to function LL_ADC_SetSamplingTimeCommonChannels();
613 * Refer to function LL_ADC_SetChannelSamplingTime();
614 * @param ADCx ADC instance
615 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
616 * @retval An ErrorStatus enumeration value:
617 * - SUCCESS: ADC registers are initialized
618 * - ERROR: ADC registers are not initialized
619 */
LL_ADC_REG_Init(ADC_TypeDef * ADCx,LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)620 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
621 {
622 ErrorStatus status = SUCCESS;
623
624 /* Check the parameters */
625 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
626 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource));
627 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
628 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
629 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
630
631 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
632 {
633 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
634 }
635
636 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
637 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
638 )
639 {
640 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
641
642 /* ADC group regular continuous mode and discontinuous mode */
643 /* can not be enabled simultenaeously */
644 assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
645 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
646 }
647
648 /* Note: Hardware constraint (refer to description of this function): */
649 /* ADC instance must be disabled. */
650 if (LL_ADC_IsEnabled(ADCx) == 0UL)
651 {
652 /* Configuration of ADC hierarchical scope: */
653 /* - ADC group regular */
654 /* - Set ADC group regular trigger source */
655 /* - Set ADC group regular sequencer length */
656 /* - Set ADC group regular sequencer discontinuous mode */
657 /* - Set ADC group regular continuous mode */
658 /* - Set ADC group regular conversion data transfer: no transfer or */
659 /* transfer by DMA, and DMA requests mode */
660 /* - Set ADC group regular overrun behavior */
661 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
662 /* setting of trigger source to SW start. */
663 if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
664 || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
665 )
666 {
667 /* Case of sequencer mode fixed
668 or sequencer length >= 2 ranks with sequencer mode fully configurable:
669 discontinuous mode configured */
670 MODIFY_REG(ADCx->CFGR1,
671 ADC_CFGR1_EXTSEL
672 | ADC_CFGR1_EXTEN
673 | ADC_CFGR1_DISCEN
674 | ADC_CFGR1_CONT
675 | ADC_CFGR1_DMAEN
676 | ADC_CFGR1_DMACFG
677 | ADC_CFGR1_OVRMOD
678 ,
679 pADC_RegInitStruct->TriggerSource
680 | pADC_RegInitStruct->SequencerDiscont
681 | pADC_RegInitStruct->ContinuousMode
682 | pADC_RegInitStruct->DMATransfer
683 | pADC_RegInitStruct->Overrun
684 );
685 }
686 else
687 {
688 /* Case of sequencer mode fully configurable
689 and sequencer length 1 rank (sequencer disabled):
690 discontinuous mode discarded (fixed to disable) */
691 MODIFY_REG(ADCx->CFGR1,
692 ADC_CFGR1_EXTSEL
693 | ADC_CFGR1_EXTEN
694 | ADC_CFGR1_DISCEN
695 | ADC_CFGR1_CONT
696 | ADC_CFGR1_DMAEN
697 | ADC_CFGR1_DMACFG
698 | ADC_CFGR1_OVRMOD
699 ,
700 pADC_RegInitStruct->TriggerSource
701 | LL_ADC_REG_SEQ_DISCONT_DISABLE
702 | pADC_RegInitStruct->ContinuousMode
703 | pADC_RegInitStruct->DMATransfer
704 | pADC_RegInitStruct->Overrun
705 );
706 }
707
708 /* Set ADC group regular sequencer length */
709 if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
710 {
711 LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
712 }
713 }
714 else
715 {
716 /* Initialization error: ADC instance is not disabled. */
717 status = ERROR;
718 }
719 return status;
720 }
721
722 /**
723 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
724 * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
725 * whose fields will be set to default values.
726 * @retval None
727 */
LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef * pADC_RegInitStruct)728 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
729 {
730 /* Set pADC_RegInitStruct fields to default values */
731 /* Set fields of ADC group regular */
732 /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
733 /* setting of trigger source to SW start. */
734 pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
735 pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
736 pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
737 pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
738 pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
739 pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
740 }
741
742 /**
743 * @}
744 */
745
746 /**
747 * @}
748 */
749
750 /**
751 * @}
752 */
753
754 #endif /* ADC */
755
756 /**
757 * @}
758 */
759
760 #endif /* USE_FULL_LL_DRIVER */
761
