1 /**
2 ******************************************************************************
3 * @file stm32wlxx_hal_pwr_ex.c
4 * @author MCD Application Team
5 * @brief Extended PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Extended Initialization and de-initialization functions
9 * + Extended Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2020 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 */
23
24 /* Includes ------------------------------------------------------------------*/
25 #include "stm32wlxx_hal.h"
26
27 /** @addtogroup STM32WLxx_HAL_Driver
28 * @{
29 */
30
31 /** @addtogroup PWREx
32 * @{
33 */
34
35 #ifdef HAL_PWR_MODULE_ENABLED
36
37 /* Private typedef -----------------------------------------------------------*/
38 /* Private constants ---------------------------------------------------------*/
39 /** @addtogroup PWREx_Private_Constants PWR Extended Private Constants
40 * @{
41 */
42 #define PWR_PORTC_AVAILABLE_PINS (PWR_GPIO_BIT_15 | PWR_GPIO_BIT_14 | PWR_GPIO_BIT_13 | PWR_GPIO_BIT_6 | PWR_GPIO_BIT_5 | PWR_GPIO_BIT_4 | PWR_GPIO_BIT_3 | PWR_GPIO_BIT_2 | PWR_GPIO_BIT_1 | PWR_GPIO_BIT_0)
43 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_3)
44
45 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
46 * @{
47 */
48 #define PWR_FLAG_SETTING_DELAY_US 50UL /*!< Time out value for REGLPF and VOSF flags setting */
49 /**
50 * @}
51 */
52
53 /**
54 * @}
55 */
56
57 /* Private macro -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private function prototypes -----------------------------------------------*/
60 /* Exported functions --------------------------------------------------------*/
61 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
62 * @{
63 */
64
65 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
66 * @brief Extended Peripheral Control functions
67 *
68 @verbatim
69 ===============================================================================
70 ##### Extended Peripheral Initialization and de-initialization functions #####
71 ===============================================================================
72 [..]
73
74 @endverbatim
75 * @{
76 */
77
78
79 /**
80 * @brief Return Voltage Scaling Range.
81 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2)
82 */
HAL_PWREx_GetVoltageRange(void)83 uint32_t HAL_PWREx_GetVoltageRange(void)
84 {
85 return (PWR->CR1 & PWR_CR1_VOS);
86 }
87
88 /**
89 * @brief Configure the main internal regulator output voltage.
90 * @param VoltageScaling specifies the regulator output voltage to achieve
91 * a trade-off between performance and power consumption.
92 * This parameter can be one of the following values:
93 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
94 * typical output voltage at 1.2 V,
95 * system frequency up to 48 MHz.
96 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
97 * typical output voltage at 1.0 V,
98 * system frequency up to 16 MHz.
99 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
100 * a value below 16 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
101 * When moving from Range 2 to Range 1, the system frequency can be increased to
102 * a value up to 48 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
103 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
104 * cleared before returning the status. If the flag is not cleared within
105 * 50 microseconds, HAL_TIMEOUT status is reported.
106 * @retval HAL Status
107 */
HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)108 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
109 {
110 uint32_t wait_loop_index;
111
112 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
113
114 /* If Set Range 1 */
115 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
116 {
117 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
118 {
119 /* Set Range 1 */
120 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
121
122 /* Wait until VOSF is cleared */
123 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL);
124 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
125 {
126 wait_loop_index--;
127 }
128 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
129 {
130 return HAL_TIMEOUT;
131 }
132 }
133 }
134 else
135 {
136 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
137 {
138 /* Set Range 2 */
139 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
140 /* No need to wait for VOSF to be cleared for this transition */
141 }
142 }
143
144 return HAL_OK;
145 }
146
147 /****************************************************************************/
148
149 /**
150 * @brief Enable battery charging.
151 * When VDD is present, charge the external battery on VBAT through an internal resistor.
152 * @param ResistorSelection specifies the resistor impedance.
153 * This parameter can be one of the following values:
154 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
155 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
156 * @retval None
157 */
HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)158 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
159 {
160 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
161
162 /* Specify resistor selection */
163 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
164
165 /* Enable battery charging */
166 SET_BIT(PWR->CR4, PWR_CR4_VBE);
167 }
168
169 /**
170 * @brief Disable battery charging.
171 * @retval None
172 */
HAL_PWREx_DisableBatteryCharging(void)173 void HAL_PWREx_DisableBatteryCharging(void)
174 {
175 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
176 }
177
178 /****************************************************************************/
179
180 /**
181 * @brief Enable Internal Wake-up Line.
182 * @retval None
183 */
HAL_PWREx_EnableInternalWakeUpLine(void)184 void HAL_PWREx_EnableInternalWakeUpLine(void)
185 {
186 #ifdef CORE_CM0PLUS
187 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
188 #else
189 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
190 #endif
191 }
192
193 /**
194 * @brief Disable Internal Wake-up Line.
195 * @retval None
196 */
HAL_PWREx_DisableInternalWakeUpLine(void)197 void HAL_PWREx_DisableInternalWakeUpLine(void)
198 {
199 #ifdef CORE_CM0PLUS
200 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
201 #else
202 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
203 #endif
204 }
205
206 /**
207 * @brief Set radio busy trigger polarity.
208 * @param RadioBusyPolarity This parameter can be one of the following values:
209 * @arg @ref PWR_RADIO_BUSY_POLARITY_RISING
210 * @arg @ref PWR_RADIO_BUSY_POLARITY_FALLING
211 * @retval HAL Status
212 */
HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity)213 void HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity)
214 {
215 /* Check the parameters */
216 assert_param(IS_RADIO_BUSY_POLARITY(RadioBusyPolarity));
217
218 LL_PWR_SetRadioBusyPolarity(RadioBusyPolarity);
219 }
220
221 /**
222 * @brief Set radio busy trigger action: wake-up from low-power mode Standby,
223 * interruption.
224 * @note Signal polarity can be configured using function
225 * @ref HAL_PWREx_SetRadioBusyPolarity().
226 * @param RadioBusyTrigger This parameter can be one of the following values:
227 * @arg @ref PWR_RADIO_BUSY_TRIGGER_NONE
228 * @arg @ref PWR_RADIO_BUSY_TRIGGER_WU_IT
229 * @retval None
230 */
HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)231 void HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)
232 {
233 /* Check the parameters */
234 assert_param(IS_PWR_RADIO_BUSY_TRIGGER(RadioBusyTrigger));
235
236 #ifdef CORE_CM0PLUS
237 LL_C2_PWR_SetRadioBusyTrigger(RadioBusyTrigger);
238 #else
239 LL_PWR_SetRadioBusyTrigger(RadioBusyTrigger);
240 #endif
241 }
242
243 /**
244 * @brief Set radio IRQ trigger action: wake-up from low-power mode Standby,
245 * interruption.
246 * @param RadioIRQTrigger This parameter can be one of the following values:
247 * @arg @ref PWR_RADIO_IRQ_TRIGGER_NONE
248 * @arg @ref PWR_RADIO_IRQ_TRIGGER_WU_IT
249 * @retval None
250 */
HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)251 void HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)
252 {
253 /* Check the parameters */
254 assert_param(IS_RADIO_IRQ_TRIGGER(RadioIRQTrigger));
255
256 #ifdef CORE_CM0PLUS
257 LL_C2_PWR_SetRadioIRQTrigger(RadioIRQTrigger);
258 #else
259 LL_PWR_SetRadioIRQTrigger(RadioIRQTrigger);
260 #endif
261 }
262
263 #if defined(DUAL_CORE)
264 /**
265 * @brief Enable CPU2 on-Hold interrupt.
266 * @retval None
267 */
HAL_PWREx_EnableHOLDC2IT(void)268 void HAL_PWREx_EnableHOLDC2IT(void)
269 {
270 SET_BIT(PWR->CR3, PWR_CR3_EC2H);
271 }
272
273 /**
274 * @brief Disable CPU2 on-Hold interrupt.
275 * @retval None
276 */
HAL_PWREx_DisableHOLDC2IT(void)277 void HAL_PWREx_DisableHOLDC2IT(void)
278 {
279 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
280 }
281 #endif
282
283 /****************************************************************************/
284
285 /**
286 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
287 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
288 * pull-up state in Standby and Shutdown modes.
289 * @note This state is effective in Standby and Shutdown modes only if APC bit
290 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
291 * @note The configuration is lost when exiting the Shutdown mode due to the
292 * power-on reset, maintained when exiting the Standby mode.
293 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
294 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
295 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
296 * parameter at the same time are set.
297 * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
298 * to select the GPIO peripheral.
299 * @param GPIONumber Specify the I/O pins numbers.
300 * This parameter can be one of the following values:
301 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
302 * I/O pins are available) or the logical OR of several of them to set
303 * several bits for a given port in a single API call.
304 * @retval HAL Status
305 */
HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)306 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
307 {
308 HAL_StatusTypeDef status = HAL_OK;
309
310 assert_param(IS_PWR_GPIO(GPIO));
311 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
312
313 switch (GPIO)
314 {
315 case PWR_GPIO_A:
316 SET_BIT(PWR->PUCRA, GPIONumber);
317 CLEAR_BIT(PWR->PDCRA, GPIONumber);
318 break;
319 case PWR_GPIO_B:
320 SET_BIT(PWR->PUCRB, GPIONumber);
321 CLEAR_BIT(PWR->PDCRB, GPIONumber);
322 break;
323 case PWR_GPIO_C:
324 SET_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
325 CLEAR_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
326 break;
327 case PWR_GPIO_H:
328 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
329 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
330 break;
331 default:
332 status = HAL_ERROR;
333 break;
334 }
335
336 return status;
337 }
338
339 /**
340 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
341 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
342 * in pull-up state in Standby and Shutdown modes.
343 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
344 * parameter at the same time are reset.
345 * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
346 * to select the GPIO peripheral.
347 * @param GPIONumber Specify the I/O pins numbers.
348 * This parameter can be one of the following values:
349 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
350 * I/O pins are available) or the logical OR of several of them to reset
351 * several bits for a given port in a single API call.
352 * @retval HAL Status
353 */
HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)354 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
355 {
356 HAL_StatusTypeDef status = HAL_OK;
357
358 assert_param(IS_PWR_GPIO(GPIO));
359 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
360
361 switch (GPIO)
362 {
363 case PWR_GPIO_A:
364 CLEAR_BIT(PWR->PUCRA, GPIONumber);
365 break;
366 case PWR_GPIO_B:
367 CLEAR_BIT(PWR->PUCRB, GPIONumber);
368 break;
369 case PWR_GPIO_C:
370 CLEAR_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
371 break;
372 case PWR_GPIO_H:
373 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
374 break;
375 default:
376 status = HAL_ERROR;
377 break;
378 }
379
380 return status;
381 }
382
383 /**
384 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
385 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
386 * pull-down state in Standby and Shutdown modes.
387 * @note This state is effective in Standby and Shutdown modes only if APC bit
388 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
389 * @note The configuration is lost when exiting the Shutdown mode due to the
390 * power-on reset, maintained when exiting the Standby mode.
391 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
392 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
393 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
394 * parameter at the same time are set.
395 * @param GPIO Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
396 * to select the GPIO peripheral.
397 * @param GPIONumber Specify the I/O pins numbers.
398 * This parameter can be one of the following values:
399 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
400 * I/O pins are available) or the logical OR of several of them to set
401 * several bits for a given port in a single API call.
402 * @retval HAL Status
403 */
HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)404 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
405 {
406 HAL_StatusTypeDef status = HAL_OK;
407
408 assert_param(IS_PWR_GPIO(GPIO));
409 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
410
411 switch (GPIO)
412 {
413 case PWR_GPIO_A:
414 SET_BIT(PWR->PDCRA, GPIONumber);
415 CLEAR_BIT(PWR->PUCRA, GPIONumber);
416 break;
417 case PWR_GPIO_B:
418 SET_BIT(PWR->PDCRB, GPIONumber);
419 CLEAR_BIT(PWR->PUCRB, GPIONumber);
420 break;
421 case PWR_GPIO_C:
422 SET_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
423 CLEAR_BIT(PWR->PUCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
424 break;
425 case PWR_GPIO_H:
426 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
427 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
428 break;
429 default:
430 status = HAL_ERROR;
431 break;
432 }
433
434 return status;
435 }
436
437 /**
438 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
439 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
440 * in pull-down state in Standby and Shutdown modes.
441 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
442 * parameter at the same time are reset.
443 * @param GPIO Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
444 * to select the GPIO peripheral.
445 * @param GPIONumber Specify the I/O pins numbers.
446 * This parameter can be one of the following values:
447 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
448 * I/O pins are available) or the logical OR of several of them to reset
449 * several bits for a given port in a single API call.
450 * @retval HAL Status
451 */
HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)452 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
453 {
454 HAL_StatusTypeDef status = HAL_OK;
455
456 assert_param(IS_PWR_GPIO(GPIO));
457 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
458
459 switch (GPIO)
460 {
461 case PWR_GPIO_A:
462 CLEAR_BIT(PWR->PDCRA, GPIONumber);
463 break;
464 case PWR_GPIO_B:
465 CLEAR_BIT(PWR->PDCRB, GPIONumber);
466 break;
467 case PWR_GPIO_C:
468 CLEAR_BIT(PWR->PDCRC, (GPIONumber & PWR_PORTC_AVAILABLE_PINS));
469 break;
470 case PWR_GPIO_H:
471 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
472 break;
473 default:
474 status = HAL_ERROR;
475 break;
476 }
477
478 return status;
479 }
480
481 /**
482 * @brief Enable pull-up and pull-down configuration.
483 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
484 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
485 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
486 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
487 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
488 * is no conflict when setting PUy or PDy bit.
489 * @retval None
490 */
HAL_PWREx_EnablePullUpPullDownConfig(void)491 void HAL_PWREx_EnablePullUpPullDownConfig(void)
492 {
493 #ifdef CORE_CM0PLUS
494 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC);
495 #else
496 SET_BIT(PWR->CR3, PWR_CR3_APC);
497 #endif
498 }
499
500 /**
501 * @brief Disable pull-up and pull-down configuration.
502 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
503 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
504 * @retval None
505 */
HAL_PWREx_DisablePullUpPullDownConfig(void)506 void HAL_PWREx_DisablePullUpPullDownConfig(void)
507 {
508 #ifdef CORE_CM0PLUS
509 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC);
510 #else
511 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
512 #endif
513 }
514
515 /****************************************************************************/
516
517 #if defined(DUAL_CORE)
518 /**
519 * @brief Hold CPU and allocated peripherals after reset or wakeup from Stop or Standby.
520 * @param CPU Specifies the core to be held.
521 * This parameter can be one of the following values:
522 * @arg PWR_CORE_CPU2: Hold CPU2.
523 * @note Hold CPU2 with CPU1 as master by default.
524 * @retval None
525 */
HAL_PWREx_HoldCore(uint32_t CPU)526 void HAL_PWREx_HoldCore(uint32_t CPU)
527 {
528 /* Check the parameters */
529 assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU));
530
531 LL_PWR_DisableBootC2();
532 }
533
534 /**
535 * @brief Release CPU and allocated peripherals after reset or wakeup from Stop or Standby.
536 * @param CPU Specifies the core to be released.
537 * This parameter can be one of the following values:
538 * @arg PWR_CORE_CPU2: Release the CPU2 from holding.
539 * @retval None
540 */
HAL_PWREx_ReleaseCore(uint32_t CPU)541 void HAL_PWREx_ReleaseCore(uint32_t CPU)
542 {
543 /* Check the parameters */
544 assert_param(IS_PWR_CORE_HOLD_RELEASE(CPU));
545
546 LL_PWR_EnableBootC2();
547 }
548
549 /****************************************************************************/
550 #ifdef CORE_CM0PLUS
551 /**
552 * @brief Enable CPU2 wake-up from low-power mode on illegal access occurrence
553 * @note Can be configured from CPU2 only
554 * @retval None
555 */
HAL_PWREx_EnableWakeUp_ILAC(void)556 void HAL_PWREx_EnableWakeUp_ILAC(void)
557 {
558 LL_PWR_C2_EnableWakeUp_ILAC();
559 }
560
561 /**
562 * @brief Disable CPU2 wake-up from low-power mode on illegal access occurrence
563 * @note Can be configured from CPU2 only
564 * @retval None
565 */
HAL_PWREx_DisableWakeUp_ILAC(void)566 void HAL_PWREx_DisableWakeUp_ILAC(void)
567 {
568 LL_PWR_C2_DisableWakeUp_ILAC();
569 }
570
571 /**
572 * @brief Check if bit to wake-up CPU2 from low-power mode on illegal access
573 * occurrence is set
574 * @note Can be used from CPU2 only
575 * @retval State of bit (1 or 0)
576 */
HAL_PWREx_IsEnabledWakeUp_ILAC(void)577 uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void)
578 {
579 return LL_PWR_C2_IsEnabledWakeUp_ILAC();
580 }
581 #endif
582 #endif
583
584 /****************************************************************************/
585 /**
586 * @brief Enable SRAM2 content retention in Standby mode.
587 * @note When RRS bit is set, SRAM is powered by the low-power regulator in
588 * Standby mode and its content is kept.
589 * @retval None
590 */
HAL_PWREx_EnableSRAMRetention(void)591 void HAL_PWREx_EnableSRAMRetention(void)
592 {
593 LL_PWR_EnableSRAM2Retention();
594 }
595
596 /**
597 * @brief Disable SRAM2 content retention in Standby mode.
598 * @note When RRS bit is reset, SRAM is powered off in Standby mode
599 * and its content is lost.
600 * @retval None
601 */
HAL_PWREx_DisableSRAMRetention(void)602 void HAL_PWREx_DisableSRAMRetention(void)
603 {
604 LL_PWR_DisableSRAM2Retention();
605 }
606
607 /****************************************************************************/
608 /**
609 * @brief Enable Flash Power Down.
610 * @note This API allows to enable flash power down capabilities in low power
611 * run and low power sleep modes.
612 * @note This configuration is effective when both CPU have selected it.
613 * @param PowerMode this can be a combination of following values:
614 * @arg @ref PWR_FLASHPD_LPRUN
615 * @arg @ref PWR_FLASHPD_LPSLEEP
616 * @retval None
617 */
HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)618 void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
619 {
620 assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
621
622 #ifdef CORE_CM0PLUS
623 if ((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
624 {
625 /* Unlock bit FPDR */
626 WRITE_REG(PWR->C2CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE);
627 }
628
629 /* Set flash power down mode */
630 SET_BIT(PWR->C2CR1, PowerMode);
631 #else
632 if ((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
633 {
634 /* Unlock bit FPDR */
635 WRITE_REG(PWR->CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE);
636 }
637
638 /* Set flash power down mode */
639 SET_BIT(PWR->CR1, PowerMode);
640 #endif
641 }
642
643 /**
644 * @brief Disable Flash Power Down.
645 * @note This API allows to disable flash power down capabilities in low power
646 * run and low power sleep modes.
647 * @note This configuration is effective when both CPU have selected it.
648 * @param PowerMode this can be a combination of following values:
649 * @arg @ref PWR_FLASHPD_LPRUN
650 * @arg @ref PWR_FLASHPD_LPSLEEP
651 * @retval None
652 */
HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)653 void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
654 {
655 assert_param(IS_PWR_FLASH_POWERDOWN(PowerMode));
656
657 #ifdef CORE_CM0PLUS
658 /* Set flash power down mode */
659 CLEAR_BIT(PWR->C2CR1, PowerMode);
660 #else
661 /* Set flash power down mode */
662 CLEAR_BIT(PWR->CR1, PowerMode);
663 #endif
664 }
665
666 /****************************************************************************/
667 /**
668 * @brief Enable wake-up power voltage detection
669 * @note Wake-up power voltage detection status can be checked
670 * using flag @ref PWR_FLAG_WPVD.
671 * @retval None
672 */
HAL_PWREx_EnableWPVD(void)673 void HAL_PWREx_EnableWPVD(void)
674 {
675 #ifdef CORE_CM0PLUS
676 LL_C2_PWR_EnableWPVD();
677 #else
678 LL_PWR_EnableWPVD();
679 #endif
680 }
681
682 /**
683 * @brief Disable wake-up power voltage detection
684 * @retval None
685 */
HAL_PWREx_DisableWPVD(void)686 void HAL_PWREx_DisableWPVD(void)
687 {
688 #ifdef CORE_CM0PLUS
689 LL_C2_PWR_DisableWPVD();
690 #else
691 LL_PWR_DisableWPVD();
692 #endif
693 }
694
695 /**
696 * @brief Enable periodical sampling of supply voltage in Stop and Standby
697 * modes for detecting condition of PDR and BOR reset.
698 * @note Caution: When enabled, and if the supply voltage drops below
699 * the minimum operating condition between two supply voltage samples,
700 * the reset condition is missed and no reset is generated.
701 * @retval None
702 */
HAL_PWREx_EnableBORPVD_ULP(void)703 void HAL_PWREx_EnableBORPVD_ULP(void)
704 {
705 SET_BIT(PWR->CR3, PWR_CR3_ULPEN);
706 }
707
708
709 /**
710 * @brief Disable periodical sampling of supply voltage in Stop and Standby
711 * modes for detecting condition of PDR and BOR reset.
712 * @note All the other modes are not affected by this bit
713 * @retval None
714 */
HAL_PWREx_DisableBORPVD_ULP(void)715 void HAL_PWREx_DisableBORPVD_ULP(void)
716 {
717 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPEN);
718 }
719
720 /****************************************************************************/
721
722 /**
723 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
724 * @retval None
725 */
HAL_PWREx_EnablePVM3(void)726 void HAL_PWREx_EnablePVM3(void)
727 {
728 SET_BIT(PWR->CR2, PWR_PVM_3);
729 }
730
731 /**
732 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
733 * @retval None
734 */
HAL_PWREx_DisablePVM3(void)735 void HAL_PWREx_DisablePVM3(void)
736 {
737 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
738 }
739
740 /**
741 * @brief Configure the Peripheral Voltage Monitoring (PVM).
742 * @param sConfigPVM pointer to a PWR_PVMTypeDef structure that contains the
743 * PVM configuration information.
744 * @note The API configures a single PVM according to the information contained
745 * in the input structure. To configure several PVMs, the API must be singly
746 * called for each PVM used.
747 * @note Refer to the electrical characteristics of your device datasheet for
748 * more details about the voltage thresholds corresponding to each
749 * detection level and to each monitored supply.
750 * @retval HAL status
751 */
HAL_PWREx_ConfigPVM(PWR_PVMTypeDef * sConfigPVM)752 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
753 {
754 HAL_StatusTypeDef status = HAL_OK;
755
756 /* Check the parameters */
757 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
758 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
759
760 /* Configure EXTI lines if so required:
761 scan through PVMType to detect which PVMx is set and
762 configure the corresponding EXTI line accordingly. */
763 switch (sConfigPVM->PVMType)
764 {
765 case PWR_PVM_3:
766 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
767 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
768 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
769
770 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
771 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
772
773 /* Configure interrupt mode */
774 if ((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
775 {
776 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
777 }
778
779 /* Configure the edge */
780 if ((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
781 {
782 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
783 }
784
785 if ((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
786 {
787 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
788 }
789 break;
790
791 default:
792 status = HAL_ERROR;
793 break;
794
795 }
796
797 return status;
798 }
799
800 /**
801 * @brief Set monitoring of supply voltage for radio operating level
802 * (radio End Of Life), radio must be in active mode.
803 * @param RadioEOL This parameter can be one of the following values:
804 * @arg @ref PWR_RADIO_EOL_ENABLE
805 * @arg @ref PWR_RADIO_EOL_DISABLE
806 * @retval None
807 */
HAL_PWREx_SetRadioEOL(uint32_t RadioEOL)808 void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL)
809 {
810 MODIFY_REG(PWR->CR5, PWR_CR5_RFEOLEN, RadioEOL);
811 }
812
813 /****************************************************************************/
814
815 /**
816 * @brief Set SMPS operating mode.
817 * @note In case of a board without SMPS coil mounted, SMPS should not be activated.
818 * @param OperatingMode This parameter can be one of the following values:
819 * @arg @ref PWR_SMPS_BYPASS
820 * @arg @ref PWR_SMPS_STEP_DOWN
821 * @retval None
822 */
HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)823 void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
824 {
825 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, OperatingMode);
826 }
827
828 /**
829 * @brief Get SMPS effective operating mode
830 * @note SMPS operating mode can be changed by hardware, therefore
831 * requested operating mode can differ from effective low power mode.
832 * - dependency SubGhz Radio IP: can switch SMPS on for radio activity.
833 * @note In case of a board without SMPS coil mounted, SMPS should not be activated
834 * and this function is not relevant.
835 * @retval Returned value can be one of the following values:
836 * @arg @ref PWR_SMPS_BYPASS
837 * @arg @ref PWR_SMPS_STEP_DOWN
838 */
HAL_PWREx_SMPS_GetEffectiveMode(void)839 uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
840 {
841 /* Return a value corresponding to definition of literals */
842 /* PWR_SMPS_BYPASS or PWR_SMPS_STEP_DOWN. */
843 return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos));
844 }
845
846 /****************************************************************************/
847
848 /**
849 * @brief Enter Low-power Run mode
850 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
851 * @note Clock frequency must be reduced below 2 MHz.
852 * @retval None
853 */
HAL_PWREx_EnableLowPowerRunMode(void)854 void HAL_PWREx_EnableLowPowerRunMode(void)
855 {
856 /* Set Regulator parameter */
857 SET_BIT(PWR->CR1, PWR_CR1_LPR);
858 }
859
860 /**
861 * @brief Exit Low-power Run mode.
862 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
863 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
864 * returns HAL_TIMEOUT status). The system clock frequency can then be
865 * increased above 2 MHz.
866 * @retval HAL Status
867 */
HAL_PWREx_DisableLowPowerRunMode(void)868 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
869 {
870 uint32_t wait_loop_index;
871
872 /* Clear LPR bit */
873 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
874
875 /* Wait until REGLPF is reset */
876 wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL);
877 while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U))
878 {
879 wait_loop_index--;
880 }
881 if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF)))
882 {
883 return HAL_TIMEOUT;
884 }
885
886 return HAL_OK;
887 }
888
889 /****************************************************************************/
890
891 /**
892 * @brief Enter Stop 0 mode.
893 * @note In Stop 0 mode, main and low voltage regulators are ON.
894 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
895 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
896 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
897 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
898 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
899 * only to the peripheral requesting it.
900 * SRAM1, SRAM2 and register contents are preserved.
901 * The BOR is available.
902 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
903 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
904 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
905 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
906 * is higher although the startup time is reduced.
907 * @note According to system power policy, system entering in Stop mode
908 * is depending on other CPU power mode.
909 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
910 * This parameter can be one of the following values:
911 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
912 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
913 * @retval None
914 */
HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)915 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
916 {
917 /* Check the parameters */
918 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
919
920 #ifdef CORE_CM0PLUS
921 /* Stop 0 mode with Main Regulator */
922 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
923
924 #else
925 /* Stop 0 mode with Main Regulator */
926 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
927
928 #endif
929
930 /* Set SLEEPDEEP bit of Cortex System Control Register */
931 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
932
933 /* Select Stop mode entry --------------------------------------------------*/
934 if (STOPEntry == PWR_STOPENTRY_WFI)
935 {
936 /* Request Wait For Interrupt */
937 __WFI();
938 }
939 else
940 {
941 /* Request Wait For Event */
942 __SEV();
943 __WFE();
944 __WFE();
945 }
946
947 /* Reset SLEEPDEEP bit of Cortex System Control Register */
948 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
949 }
950
951 /**
952 * @brief Enter Stop 1 mode.
953 * @note In Stop 1 mode, only low power voltage regulator is ON.
954 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
955 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
956 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
957 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
958 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
959 * only to the peripheral requesting it.
960 * SRAM1, SRAM2 and register contents are preserved.
961 * The BOR is available.
962 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
963 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
964 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
965 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
966 * @note According to system power policy, system entering in Stop mode
967 * is depending on other CPU power mode.
968 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
969 * This parameter can be one of the following values:
970 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
971 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
972 * @retval None
973 */
HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)974 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
975 {
976 /* Check the parameters */
977 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
978
979 #ifdef CORE_CM0PLUS
980 /* Stop 1 mode with Low-Power Regulator */
981 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
982 #else
983 /* Stop 1 mode with Low-Power Regulator */
984 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1);
985 #endif
986
987 /* Set SLEEPDEEP bit of Cortex System Control Register */
988 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
989
990 /* Select Stop mode entry --------------------------------------------------*/
991 if (STOPEntry == PWR_STOPENTRY_WFI)
992 {
993 /* Request Wait For Interrupt */
994 __WFI();
995 }
996 else
997 {
998 /* Request Wait For Event */
999 __SEV();
1000 __WFE();
1001 __WFE();
1002 }
1003
1004 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1005 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1006 }
1007
1008
1009 /**
1010 * @brief Enter Stop 2 mode.
1011 * @note In Stop 2 mode, only low power voltage regulator is ON.
1012 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
1013 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
1014 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
1015 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
1016 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
1017 * to the peripheral requesting it.
1018 * SRAM1, SRAM2 and register contents are preserved.
1019 * The BOR is available.
1020 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
1021 * Otherwise, Stop 1 mode is entered.
1022 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
1023 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
1024 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
1025 * @note According to system power policy, system entering in Stop mode
1026 * is depending on other CPU power mode.
1027 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
1028 * This parameter can be one of the following values:
1029 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
1030 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
1031 * @retval None
1032 */
HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)1033 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
1034 {
1035 /* Check the parameter */
1036 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
1037
1038 #ifdef CORE_CM0PLUS
1039 /* Set Stop mode 2 */
1040 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2);
1041 #else
1042 /* Set Stop mode 2 */
1043 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2);
1044 #endif
1045
1046 /* Set SLEEPDEEP bit of Cortex System Control Register */
1047 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1048
1049 /* Select Stop mode entry --------------------------------------------------*/
1050 if (STOPEntry == PWR_STOPENTRY_WFI)
1051 {
1052 /* Request Wait For Interrupt */
1053 __WFI();
1054 }
1055 else
1056 {
1057 /* Request Wait For Event */
1058 __SEV();
1059 __WFE();
1060 __WFE();
1061 }
1062
1063 /* Reset SLEEPDEEP bit of Cortex System Control Register */
1064 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1065 }
1066
1067 /**
1068 * @brief Enter Shutdown mode.
1069 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
1070 * off. The voltage regulator is disabled and Vcore domain is powered off.
1071 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
1072 * The BOR is not available.
1073 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
1074 * @note According to system power policy, system entering in Shutdown mode
1075 * is depending on other CPU power mode.
1076 * @retval None
1077 */
HAL_PWREx_EnterSHUTDOWNMode(void)1078 void HAL_PWREx_EnterSHUTDOWNMode(void)
1079 {
1080 #ifdef CORE_CM0PLUS
1081 /* Set Shutdown mode */
1082 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN);
1083 #else
1084 /* Set Shutdown mode */
1085 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_SHUTDOWN);
1086 #endif
1087
1088 /* Set SLEEPDEEP bit of Cortex System Control Register */
1089 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
1090
1091 /* This option is used to ensure that store operations are completed */
1092 #if defined ( __CC_ARM)
1093 __force_stores();
1094 #endif
1095
1096 /* Request Wait For Interrupt */
1097 __WFI();
1098
1099 /* Note: After this request to enter in Shutdown mode, at wake-up, program
1100 execution depends on system low-power mode:
1101 - If system was in Shutdown mode (other CPU in Shutdown),
1102 then at wake-up program restarts at reset state
1103 - If system was in Run or Stop mode (other CPU in Run, Sleep, Stop),
1104 then at wake-up program continues from this point
1105 */
1106 }
1107
1108 /**
1109 * @brief This function handles the PWR PVD/PVMx interrupt request.
1110 * @note This API should be called under the PVD_PVM_IRQHandler().
1111 * @retval None
1112 */
HAL_PWREx_PVD_PVM_IRQHandler(void)1113 void HAL_PWREx_PVD_PVM_IRQHandler(void)
1114 {
1115 /* Check PWR exti flag */
1116 if (__HAL_PWR_PVD_EXTI_GET_FLAG() != 0UL)
1117 {
1118 /* Clear PVD exti pending bit */
1119 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
1120
1121 /* PWR PVD interrupt user callback */
1122 HAL_PWR_PVDCallback();
1123 }
1124
1125 if (__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0UL)
1126 {
1127 /* Clear PVM3 exti pending bit */
1128 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
1129
1130 /* PWR PVM3 interrupt user callback */
1131 HAL_PWREx_PVM3Callback();
1132 }
1133 }
1134
1135 /**
1136 * @brief PWR PVM3 interrupt callback
1137 * @retval None
1138 */
HAL_PWREx_PVM3Callback(void)1139 __weak void HAL_PWREx_PVM3Callback(void)
1140 {
1141 /* NOTE : This function should not be modified; when the callback is needed,
1142 HAL_PWREx_PVM3Callback() API can be implemented in the user file
1143 */
1144 }
1145
1146 /**
1147 * @}
1148 */
1149
1150 /**
1151 * @}
1152 */
1153
1154 #endif /* HAL_PWR_MODULE_ENABLED */
1155 /**
1156 * @}
1157 */
1158
1159 /**
1160 * @}
1161 */
1162
1163
