1 /**
2 ******************************************************************************
3 * @file stm32wlxx_hal_pwr.c
4 * @author MCD Application Team
5 * @brief PWR HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Power Controller (PWR) peripheral:
8 * + Initialization/de-initialization functions
9 * + Peripheral Control functions
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2020 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 */
22
23 /* Includes ------------------------------------------------------------------*/
24 #include "stm32wlxx_hal.h"
25
26 /** @addtogroup STM32WLxx_HAL_Driver
27 * @{
28 */
29
30 /** @addtogroup PWR
31 * @{
32 */
33
34 #ifdef HAL_PWR_MODULE_ENABLED
35
36 /* Private typedef -----------------------------------------------------------*/
37 /* Private define ------------------------------------------------------------*/
38 /* Private macro -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41
42 /** @addtogroup PWR_Private_Constants PWR Private Constants
43 * @{
44 */
45 /* Definitions of PWR registers reset value */
46 #define PWR_CR1_RESET_VALUE (0x00000200)
47 #define PWR_CR2_RESET_VALUE (0x00000000)
48 #define PWR_CR3_RESET_VALUE (PWR_CR3_EIWUL)
49 #define PWR_CR4_RESET_VALUE (0x00000000)
50 #define PWR_CR5_RESET_VALUE (0x00000000)
51 #define PWR_PUCRA_RESET_VALUE (0x00000000)
52 #define PWR_PDCRA_RESET_VALUE (0x00000000)
53 #define PWR_PUCRB_RESET_VALUE (0x00000000)
54 #define PWR_PDCRB_RESET_VALUE (0x00000000)
55 #define PWR_PUCRC_RESET_VALUE (0x00000000)
56 #define PWR_PDCRC_RESET_VALUE (0x00000000)
57 #define PWR_PUCRH_RESET_VALUE (0x00000000)
58 #define PWR_PDCRH_RESET_VALUE (0x00000000)
59 #if defined(DUAL_CORE)
60 #define PWR_C2CR1_RESET_VALUE (PWR_C2CR1_LPMS_2 | PWR_C2CR1_LPMS_1 | PWR_C2CR1_LPMS_0)
61 #define PWR_C2CR3_RESET_VALUE (0x00000000)
62 #endif
63 /**
64 * @}
65 */
66
67 /* Private function prototypes -----------------------------------------------*/
68 /* Exported functions --------------------------------------------------------*/
69 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
70 * @{
71 */
72
73 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
74 * @brief Initialization and de-initialization functions
75 *
76 @verbatim
77 ===============================================================================
78 ##### Initialization and de-initialization functions #####
79 ===============================================================================
80 [..]
81
82 @endverbatim
83 * @{
84 */
85
86 /**
87 * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
88 * @retval None
89 */
HAL_PWR_DeInit(void)90 void HAL_PWR_DeInit(void)
91 {
92 /* Apply reset values to all PWR registers */
93 /* Note: Update of each register required since PWR global reset is not */
94 /* available at RCC level on this STM32 series. */
95 LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
96 LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
97 LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
98 LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
99 LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
100 LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
101 LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
102 LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
103 LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
104 LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
105 LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
106 LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
107 LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
108 #ifdef CORE_CM0PLUS
109 LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
110 LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
111 #endif
112
113 /* Clear all flags */
114 #if defined(DUAL_CORE)
115 LL_PWR_WriteReg(SCR,
116 LL_PWR_SCR_CWUF
117 | LL_PWR_SCR_CWRFBUSYF
118 | LL_PWR_SCR_CWPVDF
119 | LL_PWR_SCR_CC2HF
120 );
121 #else
122 LL_PWR_WriteReg(SCR,
123 LL_PWR_SCR_CWUF
124 | LL_PWR_SCR_CWRFBUSYF
125 | LL_PWR_SCR_CWPVDF
126 );
127 #endif /* DUAL_CORE */
128
129 #ifdef CORE_CM0PLUS
130 LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C2CSSF);
131 #else
132 LL_PWR_WriteReg(EXTSCR, LL_PWR_EXTSCR_C1CSSF);
133 #endif /* CORE_CM0PLUS */
134 }
135
136
137 /**
138 * @brief Enable access to the backup domain
139 * (RTC registers, RTC backup data registers).
140 * @note After reset, the backup domain is protected against
141 * possible unwanted write accesses.
142 * @note RTCSEL that sets the RTC clock source selection is in the RTC backup domain.
143 * In order to set or modify the RTC clock, the backup domain access must be
144 * disabled.
145 * @note LSEON bit that switches on and off the LSE crystal belongs as well to the
146 * backup domain.
147 * @retval None
148 */
HAL_PWR_EnableBkUpAccess(void)149 void HAL_PWR_EnableBkUpAccess(void)
150 {
151 SET_BIT(PWR->CR1, PWR_CR1_DBP);
152 }
153
154 /**
155 * @brief Disable access to the backup domain
156 * (RTC registers, RTC backup data registers).
157 * @retval None
158 */
HAL_PWR_DisableBkUpAccess(void)159 void HAL_PWR_DisableBkUpAccess(void)
160 {
161 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
162 }
163
164 /**
165 * @}
166 */
167
168
169 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
170 * @brief Low Power modes configuration functions
171 *
172 @verbatim
173
174 ===============================================================================
175 ##### Peripheral Control functions #####
176 ===============================================================================
177
178 [..]
179 *** PVD configuration ***
180 =========================
181 [..]
182 (+) The PVD is used to monitor the VDD power supply by comparing it to a
183 threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
184 (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
185 than the PVD threshold. This event is internally connected to the EXTI
186 line16 and can generate an interrupt if enabled. This is done through
187 __HAL_PVD_EXTI_ENABLE_IT() macro.
188 (+) The PVD is stopped in Standby mode.
189
190 *** WakeUp pin configuration ***
191 ================================
192 [..]
193 (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
194 The polarity of these pins can be set to configure event detection on high
195 level (rising edge) or low level (falling edge).
196
197 *** Low Power modes configuration ***
198 =====================================
199 [..]
200 The devices feature 8 low-power modes:
201
202 (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
203
204 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
205 (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
206
207 (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
208 (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
209 (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
210
211 (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
212 (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
213
214 (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
215
216 (+) Note: system power mode depends on each sub-system (CPU1, CPU2, radio) power modes.
217 Each CPU request to enter in a low-power mode will make system enter in the equivalent low-power mode
218 if all other sub-systems are aligned.
219
220 *** Low-power run mode ***
221 ==========================
222 [..]
223 (+) Entry: (from main run mode)
224 (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
225 (+) Exit:
226 (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
227 then can the system clock frequency be increased above 2 MHz.
228
229 *** Sleep mode / Low-power sleep mode ***
230 =========================================
231 [..]
232 (+) Entry:
233 The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
234 in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
235 (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
236 (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
237 In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
238 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
239 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
240
241 (+) WFI Exit:
242 (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
243 controller (NVIC) or any wake-up event.
244
245 (+) WFE Exit:
246 (++) Any wake-up event such as an EXTI line configured in event mode.
247
248 [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
249 the MCU is in Low-power Run mode.
250
251 *** Stop 0, Stop 1 and Stop 2 modes ***
252 ===============================
253 [..]
254 (+) Entry:
255 The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
256 (++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
257 or for porting reasons HAL_PWR_EnterSTOPMode().
258
259 (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
260 (++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
261 (++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
262 (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
263 (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
264 (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
265 (+) WFI Exit:
266 (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
267 (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
268 when programmed in wakeup mode.
269 (+) WFE Exit:
270 (++) Any EXTI Line (Internal or External) configured in Event mode.
271
272 [..]
273 When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
274 depending on the LPR bit setting.
275 When exiting Stop 2 mode, the MCU is in Run mode.
276
277 *** Standby mode ***
278 ====================
279 [..] The Standby mode offers two options:
280 (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
281 SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
282 and Standby circuitry.
283 (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
284 SRAM and register contents are lost except for the RTC registers, RTC backup registers
285 and Standby circuitry.
286
287 (++) Entry:
288 (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
289 SRAM1 and register contents are lost except for registers in the Backup domain and
290 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
291 To enable this feature, the user can resort to HAL_PWREx_EnableSRAMRetention() API
292 to set RRS bit.
293 (++) Exit:
294 (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
295 external reset in NRST pin, IWDG reset.
296 [..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
297
298
299 *** Shutdown mode ***
300 ======================
301 [..]
302 In Shutdown mode,
303 voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
304 SRAM and registers contents are lost except for backup domain registers.
305 (+) Entry:
306 The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
307 (+) Exit:
308 (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
309 external reset in NRST pin.
310 [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
311
312
313 *** Auto-wakeup (AWU) from low-power mode ***
314 =============================================
315 [..]
316 The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
317 Wakeup event, a tamper event or a time-stamp event, without depending on
318 an external interrupt (Auto-wakeup mode).
319
320 (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
321
322
323 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
324 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
325
326 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
327 is necessary to configure the RTC to detect the tamper or time stamp event using the
328 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
329
330 (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
331 configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
332
333 @endverbatim
334 * @{
335 */
336
337 /**
338 * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
339 * @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
340 * configuration information.
341 * @note Refer to the electrical characteristics of your device datasheet for
342 * more details about the voltage thresholds corresponding to each
343 * detection level.
344 * @note For devices dual core: if "sConfigPVD->Mode" is set to PVD_MODE_IT,
345 * wake-up target is set to wake-up the selected CPU.
346 * @retval HAL Status
347 */
HAL_PWR_ConfigPVD(PWR_PVDTypeDef * sConfigPVD)348 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
349 {
350 /* Check the parameters */
351 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
352 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
353
354 /* Set PLS bits according to PVDLevel value */
355 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
356
357 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
358
359 /* Note: On STM32WL series, power PVD event is not available on EXTI lines */
360 /* (only interruption is available through EXTI line 16). */
361 __HAL_PWR_PVD_EXTI_DISABLE_IT();
362 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
363 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
364
365 /* Configure interrupt mode */
366 if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
367 {
368 __HAL_PWR_PVD_EXTI_ENABLE_IT();
369 }
370
371 /* Configure the edge */
372 if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
373 {
374 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
375 }
376
377 if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
378 {
379 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
380 }
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Enable the Power Voltage Detector(PVD).
387 * @retval None
388 */
HAL_PWR_EnablePVD(void)389 void HAL_PWR_EnablePVD(void)
390 {
391 /* Enable the power voltage detector */
392 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
393 }
394
395 /**
396 * @brief Disable the Power Voltage Detector(PVD).
397 * @retval None
398 */
HAL_PWR_DisablePVD(void)399 void HAL_PWR_DisablePVD(void)
400 {
401 /* Disable the power voltage detector */
402 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
403 }
404
405 /**
406 * @brief Enable the WakeUp PINx functionality.
407 * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
408 * This parameter can be one of the following legacy values which set the default polarity
409 * i.e. detection on high level (rising edge):
410 * @arg PWR_WAKEUP_PIN1 Pin wake-up the system from Standby mode.
411 * @arg PWR_WAKEUP_PIN2 Pin wake-up the system from Standby mode.
412 * @arg PWR_WAKEUP_PIN3 Pin wake-up the system from Standby mode.
413 * or one of the following value where the user can explicitly specify the enabled pin and
414 * the chosen polarity:
415 * @arg @ref PWR_WAKEUP_PIN1_HIGH or @arg @ref PWR_WAKEUP_PIN1_LOW
416 * @arg @ref PWR_WAKEUP_PIN2_HIGH or @arg @ref PWR_WAKEUP_PIN2_LOW
417 * @arg @ref PWR_WAKEUP_PIN3_HIGH or @arg @ref PWR_WAKEUP_PIN3_LOW
418 * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
419 * @retval None
420 */
HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)421 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
422 {
423 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
424
425 /* Specifies the Wake-Up pin polarity for the event detection
426 (rising or falling edge) */
427 MODIFY_REG(PWR->CR4, ((PWR_CR4_WP1 | PWR_CR4_WP2 | PWR_CR4_WP3) & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
428
429 /* Enable wake-up pin */
430 #ifdef CORE_CM0PLUS
431 SET_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinPolarity));
432 #else
433 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
434 #endif
435 }
436
437 /**
438 * @brief Disable the WakeUp PINx functionality.
439 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
440 * This parameter can be one of the following values:
441 * @arg @ref PWR_WAKEUP_PIN1 Pin wake-up the system from Standby mode.
442 * @arg @ref PWR_WAKEUP_PIN2 Pin wake-up the system from Standby mode.
443 * @arg @ref PWR_WAKEUP_PIN3 Pin wake-up the system from Standby mode.
444 * @retval None
445 */
HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)446 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
447 {
448 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
449
450 /* Disable wake-up pin */
451 #ifdef CORE_CM0PLUS
452 CLEAR_BIT(PWR->C2CR3, (PWR_C2CR3_EWUP & WakeUpPinx));
453 #else
454 CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
455 #endif
456 }
457
458 /**
459 * @brief Enter Sleep or Low-power Sleep mode.
460 * @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
461 * @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode.
462 * This parameter can be one of the following values:
463 * @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
464 * @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
465 * @note Low-power Sleep mode is entered from Low-power Run mode (low-power regulator used
466 * and clock frequency below 2 MHz) and by calling HAL_PWR_EnterSLEEPMode() with Regulator set
467 * to PWR_LOWPOWERREGULATOR_ON.
468 * Additionally, the clock frequency must be reduced below 2 MHz.
469 * @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
470 * Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
471 * @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction.
472 * This parameter can be one of the following values:
473 * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
474 * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
475 * @note When WFI entry is used, tick interrupt have to be disabled if not desired as
476 * the interrupt wake up source.
477 * @retval None
478 */
HAL_PWR_EnterSLEEPMode(uint32_t Regulator,uint8_t SLEEPEntry)479 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
480 {
481 /* Check the parameters */
482 assert_param(IS_PWR_REGULATOR(Regulator));
483 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
484
485 /* Set Regulator parameter */
486 if (Regulator == PWR_MAINREGULATOR_ON)
487 {
488 /* If in low-power run mode at this point, exit it */
489 if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF)))
490 {
491 if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
492 {
493 return ;
494 }
495 }
496 /* Regulator now in main mode. */
497 }
498 else
499 {
500 /* If in run mode, first move to low-power run mode.
501 The system clock frequency must be below 2 MHz at this point. */
502 if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF)))
503 {
504 HAL_PWREx_EnableLowPowerRunMode();
505 }
506 }
507
508 /* Clear SLEEPDEEP bit of Cortex System Control Register */
509 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
510
511 /* Select SLEEP mode entry -------------------------------------------------*/
512 if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
513 {
514 /* Request Wait For Interrupt */
515 __WFI();
516 }
517 else
518 {
519 /* Request Wait For Event */
520 __SEV();
521 __WFE();
522 __WFE();
523 }
524 }
525
526 /**
527 * @brief Enter Stop mode
528 * @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy STM32 series
529 * where only "Stop mode" is mentioned with main or low power regulator ON.
530 * It is recommended to use functions:
531 * @arg @ref HAL_PWREx_EnterSTOP0Mode
532 * @arg @ref HAL_PWREx_EnterSTOP1Mode
533 * @arg @ref HAL_PWREx_EnterSTOP2Mode
534 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
535 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
536 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
537 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
538 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
539 * only to the peripheral requesting it.
540 * SRAM1, SRAM2 and register contents are preserved.
541 * The BOR is available.
542 * The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
543 * @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
544 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
545 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
546 * @note When the voltage regulator operates in low power mode (Stop 1), an additional
547 * startup delay is incurred when waking up.
548 * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
549 * is higher although the startup time is reduced.
550 * @note According to system power policy, system entering in Stop mode
551 * is depending on other CPU power mode.
552 * @param Regulator Specifies the regulator state in Stop mode.
553 * This parameter can be one of the following values:
554 * @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
555 * @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
556 * @param STOPEntry Specifies Stop 0, Stop 1 mode is entered with WFI or WFE instruction.
557 * This parameter can be one of the following values:
558 * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
559 * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
560 * @retval None
561 */
HAL_PWR_EnterSTOPMode(uint32_t Regulator,uint8_t STOPEntry)562 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
563 {
564 /* Check the parameters */
565 assert_param(IS_PWR_REGULATOR(Regulator));
566
567 if (Regulator == PWR_LOWPOWERREGULATOR_ON)
568 {
569 HAL_PWREx_EnterSTOP1Mode(STOPEntry);
570 }
571 else
572 {
573 HAL_PWREx_EnterSTOP0Mode(STOPEntry);
574 }
575 }
576
577 /**
578 * @brief Enter Standby mode.
579 * @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
580 * off. The voltage regulator is disabled, except when SRAM2 content is preserved
581 * in which case the regulator is in low-power mode.
582 * SRAM and register contents are lost except for registers in the Backup domain and
583 * Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
584 * To enable this feature, the user can resort to HAL_PWREx_EnableSRAMRetention() API
585 * to set RRS bit.
586 * The BOR is available.
587 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
588 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
589 * Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
590 * same.
591 * These states are effective in Standby mode only if APC bit is set through
592 * HAL_PWREx_EnablePullUpPullDownConfig() API.
593 * @note According to system power policy, system entering in Standby mode
594 * is depending on other CPU power mode.
595 * @retval None
596 */
HAL_PWR_EnterSTANDBYMode(void)597 void HAL_PWR_EnterSTANDBYMode(void)
598 {
599 #ifdef CORE_CM0PLUS
600 /* Set Stand-by mode */
601 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
602 #else
603 /* Set Stand-by mode */
604 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
605 #endif
606
607 /* Set SLEEPDEEP bit of Cortex System Control Register */
608 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
609
610 /* This option is used to ensure that store operations are completed */
611 #if defined ( __CC_ARM)
612 __force_stores();
613 #endif
614
615 /* Request Wait For Interrupt */
616 __WFI();
617
618 /* Note: After this request to enter in Standby mode, at wake-up, program
619 execution depends on system low-power mode:
620 - If system was in Standby mode (other CPU in Standby or Shutdown),
621 then at wake-up program restarts at reset state
622 - If system was in Run or Stop mode (other CPU in Run, Sleep, Stop),
623 then at wake-up program continues from this point
624 */
625 }
626
627 /**
628 * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
629 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
630 * re-enters SLEEP mode when an interruption handling is over.
631 * Setting this bit is useful when the processor is expected to run only on
632 * interruptions handling.
633 * @retval None
634 */
HAL_PWR_EnableSleepOnExit(void)635 void HAL_PWR_EnableSleepOnExit(void)
636 {
637 /* Set SLEEPONEXIT bit of Cortex System Control Register */
638 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
639 }
640
641 /**
642 * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
643 * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
644 * re-enters SLEEP mode when an interruption handling is over.
645 * @retval None
646 */
HAL_PWR_DisableSleepOnExit(void)647 void HAL_PWR_DisableSleepOnExit(void)
648 {
649 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
650 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
651 }
652
653 /**
654 * @brief Enable CPU SEVONPEND bit.
655 * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
656 * WFE to wake up when an interrupt moves from inactive to pended.
657 * @retval None
658 */
HAL_PWR_EnableSEVOnPend(void)659 void HAL_PWR_EnableSEVOnPend(void)
660 {
661 /* Set SEVONPEND bit of Cortex System Control Register */
662 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
663 }
664
665 /**
666 * @brief Disable CPU SEVONPEND bit.
667 * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
668 * WFE to wake up when an interrupt moves from inactive to pended.
669 * @retval None
670 */
HAL_PWR_DisableSEVOnPend(void)671 void HAL_PWR_DisableSEVOnPend(void)
672 {
673 /* Clear SEVONPEND bit of Cortex System Control Register */
674 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
675 }
676
677 /**
678 * @brief PWR PVD interrupt callback
679 * @retval None
680 */
HAL_PWR_PVDCallback(void)681 __weak void HAL_PWR_PVDCallback(void)
682 {
683 /* NOTE : This function should not be modified; when the callback is needed,
684 the HAL_PWR_PVDCallback can be implemented in the user file
685 */
686 }
687
688 /**
689 * @}
690 */
691
692 /**
693 * @}
694 */
695
696 #endif /* HAL_PWR_MODULE_ENABLED */
697 /**
698 * @}
699 */
700
701 /**
702 * @}
703 */
704
705
