1 /**
2 ******************************************************************************
3 * @file stm32wlxx_hal_cortex.c
4 * @author MCD Application Team
5 * @brief CORTEX HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the CORTEX:
8 * + Initialization and Configuration functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2020 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### How to use this driver #####
25 ==============================================================================
26
27 [..]
28 *** How to configure Interrupts using CORTEX HAL driver ***
29 ===========================================================
30 [..]
31 This section provides functions allowing to configure the NVIC interrupts (IRQ).
32 The Cortex-M4 exceptions are managed by CMSIS functions.
33
34 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
35 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
36 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
37
38 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
39 The pending IRQ priority will be managed only by the sub priority.
40
41 -@- IRQ priority order (sorted by highest to lowest priority):
42 (+@) Lowest pre-emption priority
43 (+@) Lowest sub priority
44 (+@) Lowest hardware priority (IRQ number)
45
46 [..]
47 *** How to configure Systick using CORTEX HAL driver ***
48 ========================================================
49 [..]
50 Setup SysTick Timer for time base.
51
52 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
53 is a CMSIS function that:
54 (++) Configures the SysTick Reload register with value passed as function parameter.
55 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
56 (++) Resets the SysTick Counter register.
57 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
58 (++) Enables the SysTick Interrupt.
59 (++) Starts the SysTick Counter.
60
61 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
62 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
63 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
64 inside the stm32wlxx_hal_cortex.h file.
65
66 (+) You can change the SysTick IRQ priority by calling the
67 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
68 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
69
70 (+) To adjust the SysTick time base, use the following formula:
71
72 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
73 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
74 (++) Reload Value should not exceed 0xFFFFFF
75
76 @endverbatim
77 ******************************************************************************
78
79 The table below gives the allowed values of the pre-emption priority and subpriority according
80 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
81
82 ==========================================================================================================================
83 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
84 ==========================================================================================================================
85 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority
86 | | | 4 bits for subpriority
87 --------------------------------------------------------------------------------------------------------------------------
88 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority
89 | | | 3 bits for subpriority
90 --------------------------------------------------------------------------------------------------------------------------
91 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
92 | | | 2 bits for subpriority
93 --------------------------------------------------------------------------------------------------------------------------
94 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
95 | | | 1 bit for subpriority
96 --------------------------------------------------------------------------------------------------------------------------
97 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
98 | | | 0 bit for subpriority
99 ==========================================================================================================================
100
101 ******************************************************************************
102 */
103
104 /* Includes ------------------------------------------------------------------*/
105 #include "stm32wlxx_hal.h"
106
107 /** @addtogroup STM32WLxx_HAL_Driver
108 * @{
109 */
110
111 /** @addtogroup CORTEX
112 * @{
113 */
114
115 #ifdef HAL_CORTEX_MODULE_ENABLED
116
117 /* Private types -------------------------------------------------------------*/
118 /* Private variables ---------------------------------------------------------*/
119 /* Private constants ---------------------------------------------------------*/
120 /* Private macros ------------------------------------------------------------*/
121 /* Private functions ---------------------------------------------------------*/
122 /* Exported functions --------------------------------------------------------*/
123
124 /** @addtogroup CORTEX_Exported_Functions
125 * @{
126 */
127
128
129 /** @addtogroup CORTEX_Exported_Functions_Group1
130 * @brief Initialization and Configuration functions
131 *
132 @verbatim
133 ==============================================================================
134 ##### Initialization and Configuration functions #####
135 ==============================================================================
136 [..]
137 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
138 SysTick functionalities
139
140 @endverbatim
141 * @{
142 */
143
144 #ifdef CORE_CM0PLUS
145 /**
146 * @brief Sets the priority of an interrupt.
147 * @param IRQn External interrupt number .
148 * This parameter can be an enumerator of IRQn_Type enumeration
149 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32wlxx.h file)
150 * @param PreemptPriority The preemption priority for the IRQn channel.
151 * This parameter can be a value between 0 and 3.
152 * A lower priority value indicates a higher priority
153 * @param SubPriority the subpriority level for the IRQ channel.
154 * with stm32wlxx devices, this parameter is a dummy value and it is ignored, because
155 * no subpriority supported in Cortex M0+ based products.
156 * @retval None
157 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)158 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
159 {
160 /* Check the parameters */
161 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
162 NVIC_SetPriority(IRQn, PreemptPriority);
163 }
164 #else
165 /**
166 * @brief Set the priority grouping field (pre-emption priority and subpriority)
167 * using the required unlock sequence.
168 * @param PriorityGroup The priority grouping bits length.
169 * This parameter can be one of the following values:
170 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
171 * 4 bits for subpriority
172 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
173 * 3 bits for subpriority
174 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
175 * 2 bits for subpriority
176 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
177 * 1 bit for subpriority
178 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
179 * 0 bit for subpriority
180 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
181 * The pending IRQ priority will be managed only by the subpriority.
182 * @retval None
183 */
HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)184 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
185 {
186 /* Check the parameters */
187 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
188
189 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
190 NVIC_SetPriorityGrouping(PriorityGroup);
191 }
192
193 /**
194 * @brief Set the priority of an interrupt.
195 * @param IRQn External interrupt number.
196 * This parameter can be an enumerator of IRQn_Type enumeration
197 * (For the complete STM32 Devices IRQ Channels list, please refer
198 * to the appropriate CMSIS device file (stm32wlxxxx.h))
199 * @param PreemptPriority The pre-emption priority for the IRQn channel.
200 * This parameter can be a value between 0 and 15
201 * A lower priority value indicates a higher priority
202 * @param SubPriority the subpriority level for the IRQ channel.
203 * This parameter can be a value between 0 and 15
204 * A lower priority value indicates a higher priority.
205 * @retval None
206 */
HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority,uint32_t SubPriority)207 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
208 {
209 uint32_t prioritygroup;
210
211 /* Check the parameters */
212 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
213 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
214
215 prioritygroup = NVIC_GetPriorityGrouping();
216
217 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
218 }
219 #endif /* CORE_CM0PLUS */
220
221 /**
222 * @brief Enable a device specific interrupt in the NVIC interrupt controller.
223 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
224 * function should be called before.
225 * @param IRQn External interrupt number.
226 * This parameter can be an enumerator of IRQn_Type enumeration
227 * (For the complete STM32 Devices IRQ Channels list, please refer
228 * to the appropriate CMSIS device file (stm32wlxxxx.h))
229 * @retval None
230 */
HAL_NVIC_EnableIRQ(IRQn_Type IRQn)231 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
232 {
233 /* Check the parameters */
234 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
235
236 /* Enable interrupt */
237 NVIC_EnableIRQ(IRQn);
238 }
239
240 /**
241 * @brief Disable a device specific interrupt in the NVIC interrupt controller.
242 * @param IRQn External interrupt number.
243 * This parameter can be an enumerator of IRQn_Type enumeration
244 * (For the complete STM32 Devices IRQ Channels list, please refer
245 * to the appropriate CMSIS device file (stm32wlxxxx.h))
246 * @retval None
247 */
HAL_NVIC_DisableIRQ(IRQn_Type IRQn)248 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
249 {
250 /* Check the parameters */
251 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
252
253 /* Disable interrupt */
254 NVIC_DisableIRQ(IRQn);
255 }
256
257 /**
258 * @brief Initiate a system reset request to reset the MCU.
259 * @retval None
260 */
HAL_NVIC_SystemReset(void)261 void HAL_NVIC_SystemReset(void)
262 {
263 /* System Reset */
264 NVIC_SystemReset();
265 }
266
267 /**
268 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
269 * Counter is in free running mode to generate periodic interrupts.
270 * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
271 * @retval status: - 0 Function succeeded.
272 * - 1 Function failed.
273 */
HAL_SYSTICK_Config(uint32_t TicksNumb)274 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
275 {
276 return SysTick_Config(TicksNumb);
277 }
278 /**
279 * @}
280 */
281
282 /** @addtogroup CORTEX_Exported_Functions_Group2
283 * @brief Cortex control functions
284 *
285 @verbatim
286 ==============================================================================
287 ##### Peripheral Control functions #####
288 ==============================================================================
289 [..]
290 This subsection provides a set of functions allowing to control the CORTEX
291 (NVIC, SYSTICK, MPU) functionalities.
292
293
294 @endverbatim
295 * @{
296 */
297
298 #ifdef CORE_CM0PLUS
299 /**
300 * @brief Get the priority of an interrupt.
301 * @param IRQn External interrupt number.
302 * This parameter can be an enumerator of IRQn_Type enumeration
303 * (For the complete STM32 Devices IRQ Channels list, please refer
304 * to the appropriate CMSIS device file (stm32wlxxxx.h))
305 * @retval None
306 */
HAL_NVIC_GetPriority(IRQn_Type IRQn)307 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn)
308 {
309 /* Get priority for Cortex-M system or device specific interrupts */
310 return NVIC_GetPriority(IRQn);
311 }
312 #else
313
314 /**
315 * @brief Get the priority grouping field from the NVIC Interrupt Controller.
316 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
317 */
HAL_NVIC_GetPriorityGrouping(void)318 uint32_t HAL_NVIC_GetPriorityGrouping(void)
319 {
320 /* Get the PRIGROUP[10:8] field value */
321 return NVIC_GetPriorityGrouping();
322 }
323
324 /**
325 * @brief Get the priority of an interrupt.
326 * @param IRQn External interrupt number.
327 * This parameter can be an enumerator of IRQn_Type enumeration
328 * (For the complete STM32 Devices IRQ Channels list, please refer
329 * to the appropriate CMSIS device file (stm32wlxxxx.h))
330 * @param PriorityGroup the priority grouping bits length.
331 * This parameter can be one of the following values:
332 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
333 * 4 bits for subpriority
334 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
335 * 3 bits for subpriority
336 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
337 * 2 bits for subpriority
338 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
339 * 1 bit for subpriority
340 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
341 * 0 bit for subpriority
342 * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
343 * @param pSubPriority Pointer on the Subpriority value (starting from 0).
344 * @retval None
345 */
HAL_NVIC_GetPriority(IRQn_Type IRQn,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)346 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
347 {
348 /* Check the parameters */
349 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
350 /* Get priority for Cortex-M system or device specific interrupts */
351 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
352 }
353
354 /**
355 * @brief Get active interrupt (read the active register in NVIC and return the active bit).
356 * @param IRQn External interrupt number
357 * This parameter can be an enumerator of IRQn_Type enumeration
358 * (For the complete STM32 Devices IRQ Channels list, please refer
359 * to the appropriate CMSIS device file (stm32wlxxxx.h))
360 * @retval status: - 0 Interrupt status is not pending.
361 * - 1 Interrupt status is pending.
362 */
HAL_NVIC_GetActive(IRQn_Type IRQn)363 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
364 {
365 /* Return 1 if active else 0 */
366 return NVIC_GetActive(IRQn);
367 }
368
369 #endif /* CORE_CM0PLUS */
370
371 /**
372 * @brief Set Pending bit of an external interrupt.
373 * @param IRQn External interrupt number
374 * This parameter can be an enumerator of IRQn_Type enumeration
375 * (For the complete STM32 Devices IRQ Channels list, please refer
376 * to the appropriate CMSIS device file (stm32wlxxxx.h))
377 * @retval None
378 */
HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)379 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
380 {
381 /* Check the parameters */
382 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
383
384 /* Set interrupt pending */
385 NVIC_SetPendingIRQ(IRQn);
386 }
387
388 /**
389 * @brief Get Pending Interrupt (read the pending register in the NVIC
390 * and return the pending bit for the specified interrupt).
391 * @param IRQn External interrupt number.
392 * This parameter can be an enumerator of IRQn_Type enumeration
393 * (For the complete STM32 Devices IRQ Channels list, please refer
394 * to the appropriate CMSIS device file (stm32wlxxxx.h))
395 * @retval status: - 0 Interrupt status is not pending.
396 * - 1 Interrupt status is pending.
397 */
HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)398 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
399 {
400 /* Check the parameters */
401 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
402
403 /* Return 1 if pending else 0 */
404 return NVIC_GetPendingIRQ(IRQn);
405 }
406
407 /**
408 * @brief Clear the pending bit of an external interrupt.
409 * @param IRQn External interrupt number.
410 * This parameter can be an enumerator of IRQn_Type enumeration
411 * (For the complete STM32 Devices IRQ Channels list, please refer
412 * to the appropriate CMSIS device file (stm32wlxxxx.h))
413 * @retval None
414 */
HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)415 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
416 {
417 /* Check the parameters */
418 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
419
420 /* Clear pending interrupt */
421 NVIC_ClearPendingIRQ(IRQn);
422 }
423
424 /**
425 * @brief Configure the SysTick clock source.
426 * @param CLKSource specifies the SysTick clock source.
427 * This parameter can be one of the following values:
428 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
429 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
430 * @retval None
431 */
HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)432 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
433 {
434 /* Check the parameters */
435 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
436 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
437 {
438 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
439 }
440 else
441 {
442 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
443 }
444 }
445
446 /**
447 * @brief Handle SYSTICK interrupt request.
448 * @retval None
449 */
HAL_SYSTICK_IRQHandler(void)450 void HAL_SYSTICK_IRQHandler(void)
451 {
452 HAL_SYSTICK_Callback();
453 }
454
455 /**
456 * @brief SYSTICK callback.
457 * @retval None
458 */
HAL_SYSTICK_Callback(void)459 __weak void HAL_SYSTICK_Callback(void)
460 {
461 /* NOTE : This function should not be modified, when the callback is needed,
462 the HAL_SYSTICK_Callback could be implemented in the user file
463 */
464 }
465
466 #if (__MPU_PRESENT == 1U)
467
468 /**
469 * @brief Enable the MPU.
470 * @param MPU_Control: Specifies the control mode of the MPU during hard fault,
471 * NMI, FAULTMASK and privileged access to the default memory
472 * This parameter can be one of the following values:
473 * @arg MPU_HFNMI_PRIVDEF_NONE
474 * @arg MPU_HARDFAULT_NMI
475 * @arg MPU_PRIVILEGED_DEFAULT
476 * @arg MPU_HFNMI_PRIVDEF
477 * @retval None
478 */
HAL_MPU_Enable(uint32_t MPU_Control)479 void HAL_MPU_Enable(uint32_t MPU_Control)
480 {
481 /* Enable the MPU */
482 MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
483
484 /* Ensure MPU setting take effects */
485 __DSB();
486 __ISB();
487 }
488
489
490 /**
491 * @brief Disable the MPU.
492 * @retval None
493 */
HAL_MPU_Disable(void)494 void HAL_MPU_Disable(void)
495 {
496 /* Make sure outstanding transfers are done */
497 __DMB();
498
499 /* Disable the MPU and clear the control register*/
500 MPU->CTRL = 0;
501 }
502
503
504 /**
505 * @brief Initialize and configure the Region and the memory to be protected.
506 * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
507 * the initialization and configuration information.
508 * @retval None
509 */
HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef * MPU_Init)510 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
511 {
512 /* Check the parameters */
513 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
514 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
515
516 /* Set the Region number */
517 MPU->RNR = MPU_Init->Number;
518
519 if ((MPU_Init->Enable) != 0U)
520 {
521 /* Check the parameters */
522 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
523 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
524 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
525 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
526 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
527 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
528 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
529 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
530
531 MPU->RBAR = MPU_Init->BaseAddress;
532 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
533 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
534 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
535 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
536 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
537 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
538 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
539 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
540 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
541 }
542 else
543 {
544 MPU->RBAR = 0x00U;
545 MPU->RASR = 0x00U;
546 }
547 }
548 #endif /* __MPU_PRESENT */
549
550 /**
551 * @}
552 */
553
554 /**
555 * @}
556 */
557
558 #endif /* HAL_CORTEX_MODULE_ENABLED */
559 /**
560 * @}
561 */
562
563 /**
564 * @}
565 */
566
567
