1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL UTILS driver contains a set of generic APIs that can be
23 used by user:
24 (+) Device electronic signature
25 (+) Timing functions
26 (+) PLL configuration functions
27
28 @endverbatim
29 ******************************************************************************
30 */
31
32 /* Define to prevent recursive inclusion -------------------------------------*/
33 #ifndef __STM32WLxx_LL_UTILS_H
34 #define __STM32WLxx_LL_UTILS_H
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* Includes ------------------------------------------------------------------*/
41 #include "stm32wlxx.h"
42
43 /** @addtogroup STM32WLxx_LL_Driver
44 * @{
45 */
46
47 /** @defgroup UTILS_LL UTILS
48 * @{
49 */
50
51 /* Private types -------------------------------------------------------------*/
52 /* Private variables ---------------------------------------------------------*/
53
54 /* Private constants ---------------------------------------------------------*/
55 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
56 * @{
57 */
58
59 /* Max delay can be used in LL_mDelay */
60 #define LL_MAX_DELAY 0xFFFFFFFFU
61
62 /**
63 * @brief Unique device ID register base address
64 */
65 #define UID_BASE_ADDRESS UID_BASE
66
67 /**
68 * @brief Flash size data register base address
69 */
70 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
71
72 /**
73 * @brief Package data register base address
74 */
75 #define PACKAGE_BASE_ADDRESS PACKAGE_BASE
76
77 /**
78 * @}
79 */
80
81 /* Private macros ------------------------------------------------------------*/
82 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
83 * @{
84 */
85 /**
86 * @}
87 */
88 /* Exported types ------------------------------------------------------------*/
89 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
90 * @{
91 */
92 /**
93 * @brief UTILS PLL structure definition
94 */
95 typedef struct
96 {
97 uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
98 This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
99
100 This feature can be modified afterwards using unitary function
101 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
102
103 uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
104 This parameter must be a number between Min_Data = 6 and Max_Data = 127
105
106 This feature can be modified afterwards using unitary function
107 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
108
109 uint32_t PLLR; /*!< Division for the main system clock.
110 This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
111
112 This feature can be modified afterwards using unitary function
113 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
114 } LL_UTILS_PLLInitTypeDef;
115
116 /**
117 * @brief UTILS System, AHB and APB buses clock configuration structure definition
118 */
119 typedef struct
120 {
121 uint32_t CPU1CLKDivider; /*!< The CPU1 clock (HCLK1) divider. This clock is derived from the system clock
122 (SYSCLK).
123 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
124
125 This feature can be modified afterwards using unitary function
126 @ref LL_RCC_SetAHBPrescaler(). */
127
128 #if defined(DUAL_CORE)
129 uint32_t CPU2CLKDivider; /*!< The CPU2 clock (HCLK2) divider. This clock is derived from the system clock
130 (SYSCLK).
131 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
132
133 This feature can be modified afterwards using unitary function
134 @ref LL_C2_RCC_SetAHBPrescaler(). */
135 #endif /* DUAL_CORE */
136
137 uint32_t AHB3CLKDivider; /*!< The AHBS clock (HCLK3) divider. This clock is derived from the system clock
138 (SYSCLK).
139 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
140
141 This feature can be modified afterwards using unitary function
142 @ref LL_RCC_SetAHB3Prescaler(). */
143
144 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK1).
145 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
146
147 This feature can be modified afterwards using unitary function
148 @ref LL_RCC_SetAPB1Prescaler(). */
149
150 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK1).
151 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
152
153 This feature can be modified afterwards using unitary function
154 @ref LL_RCC_SetAPB2Prescaler(). */
155
156 } LL_UTILS_ClkInitTypeDef;
157
158 /**
159 * @}
160 */
161
162 /* Exported constants --------------------------------------------------------*/
163 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
164 * @{
165 */
166
167 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
168 * @{
169 */
170 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
171 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
172 /**
173 * @}
174 */
175
176 /** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
177 * @{
178 */
179 #define LL_UTILS_PACKAGETYPE_UFBGA73 0x00000000U /*!< UFBGA73 package type */
180 #define LL_UTILS_PACKAGETYPE_WLCSP59 0x00000002U /*!< WLSCSP59 package type */
181 #define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQPFN48 package type */
182 /**
183 * @}
184 */
185
186 /**
187 * @}
188 */
189
190 /* Exported macro ------------------------------------------------------------*/
191
192 /* Exported functions --------------------------------------------------------*/
193 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
194 * @{
195 */
196
197 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
198 * @{
199 */
200 /**
201 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
202 * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
203 */
LL_GetUID_Word0(void)204 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
205 {
206 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
207 }
208
209 /**
210 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
211 * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
212 */
LL_GetUID_Word1(void)213 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
214 {
215 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
216 }
217
218 /**
219 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
220 * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
221 */
LL_GetUID_Word2(void)222 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
223 {
224 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
225 }
226
227 /**
228 * @brief Get Flash memory size
229 * @note This bitfield indicates the size of the device Flash memory expressed in
230 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
231 * @retval FLASH_SIZE[15:0]: Flash memory size
232 */
LL_GetFlashSize(void)233 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
234 {
235 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFUL);
236 }
237
238 /**
239 * @brief Get Package type
240 * @retval Returned value can be one of the following values:
241 * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA73
242 * @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
243 * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP59
244 *
245 */
LL_GetPackageType(void)246 __STATIC_INLINE uint32_t LL_GetPackageType(void)
247 {
248 return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
249 }
250
251 /**
252 * @}
253 */
254
255 /** @defgroup UTILS_LL_EF_DELAY DELAY
256 * @{
257 */
258 #if defined(CORE_CM0PLUS)
259 /**
260 * @brief This function configures the Cortex-M SysTick source of the time base.
261 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function
262 * @ref LL_RCC_GetSystemClocksFreq (HCLK2_Frequency field))
263 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
264 * configuration by calling this function, for a delay use rather osDelay RTOS service.
265 * @param Ticks Number of ticks
266 * @retval None
267 */
268 #else
269 /**
270 * @brief This function configures the Cortex-M SysTick source of the time base.
271 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function
272 * @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
273 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
274 * configuration by calling this function, for a delay use rather osDelay RTOS service.
275 * @param Ticks Number of ticks
276 * @retval None
277 */
278 #endif /* CORE_CM0PLUS */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)279 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
280 {
281 if (Ticks > 0U)
282 {
283 /* Configure the SysTick to have interrupt in 1ms time base */
284 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
285 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
286 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
287 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
288 }
289 }
290
291 void LL_Init1msTick(uint32_t HCLKFrequency);
292
293 void LL_mDelay(uint32_t Delay);
294
295 /**
296 * @}
297 */
298
299 /** @defgroup UTILS_EF_SYSTEM SYSTEM
300 * @{
301 */
302
303 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
304 ErrorStatus LL_SetFlashLatency(uint32_t HCLK3_Frequency);
305 ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
306 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
307 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
308 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
309 ErrorStatus LL_PLL_ConfigSystemClock_HSE(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
310 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
311
312
313 /**
314 * @}
315 */
316
317 /**
318 * @}
319 */
320
321 /**
322 * @}
323 */
324
325 /**
326 * @}
327 */
328
329 #ifdef __cplusplus
330 }
331 #endif
332
333 #endif /* __STM32WLxx_LL_UTILS_H */
334
