1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WLxx_LL_RCC_H
21 #define __STM32WLxx_LL_RCC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45
46 #define HSE_CONTROL_UNLOCK_KEY 0xCAFECAFEU
47
48 /**
49 * @}
50 */
51
52 /* Private constants ---------------------------------------------------------*/
53 /* Private macros ------------------------------------------------------------*/
54 #if defined(USE_FULL_LL_DRIVER)
55 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
56 * @{
57 */
58 /**
59 * @}
60 */
61 #endif /*USE_FULL_LL_DRIVER*/
62
63 /* Exported types ------------------------------------------------------------*/
64 #if defined(USE_FULL_LL_DRIVER)
65 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
66 * @{
67 */
68
69 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
70 * @{
71 */
72
73 /**
74 * @brief RCC Clocks Frequency Structure
75 */
76 typedef struct
77 {
78 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
79 uint32_t HCLK1_Frequency; /*!< HCLK1 clock frequency */
80 #if defined(DUAL_CORE)
81 uint32_t HCLK2_Frequency; /*!< HCLK2 clock frequency */
82 #endif /* DUAL_CORE */
83 uint32_t HCLK3_Frequency; /*!< HCLK3 clock frequency */
84 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
85 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
86 } LL_RCC_ClocksTypeDef;
87
88 /**
89 * @}
90 */
91
92 /**
93 * @}
94 */
95 #endif /* USE_FULL_LL_DRIVER */
96
97 /* Exported constants --------------------------------------------------------*/
98 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
99 * @{
100 */
101
102 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
103 * @brief Defines used to adapt values of different oscillators
104 * @note These values could be modified in the user environment according to
105 * HW set-up.
106 * @{
107 */
108 #if !defined (HSE_VALUE)
109 #define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */
110 #endif /* HSE_VALUE */
111
112 #if !defined (HSI_VALUE)
113 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
114 #endif /* HSI_VALUE */
115
116 #if !defined (LSE_VALUE)
117 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
118 #endif /* LSE_VALUE */
119
120 #if !defined (LSI_VALUE)
121 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
122 #endif /* LSI_VALUE */
123
124 #if !defined (EXTERNAL_CLOCK_VALUE)
125 #define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN external oscillator in Hz */
126 #endif /* EXTERNAL_CLOCK_VALUE */
127
128 /**
129 * @}
130 */
131
132 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
133 * @brief Flags defines which can be used with LL_RCC_WriteReg function
134 * @{
135 */
136 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
137 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
138 #define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */
139 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
140 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
141 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
142 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
143 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
144 /**
145 * @}
146 */
147
148 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
149 * @brief Flags defines which can be used with LL_RCC_ReadReg function
150 * @{
151 */
152 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
153 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
154 #define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */
155 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
156 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
157 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
158 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
159 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
160 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
161 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
162 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
163 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
164 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
165 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
166 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
167 #define LL_RCC_CSR_RFILASTF RCC_CSR_RFILARSTF /*!< Radio illegal access flag */
168
169 /**
170 * @}
171 */
172
173 /** @defgroup RCC_LL_EC_IT IT Defines
174 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
175 * @{
176 */
177 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
178 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
179 #define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */
180 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
181 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
182 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
183 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
184 /**
185 * @}
186 */
187
188 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
189 * @{
190 */
191 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
192 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
193 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
194 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
195 /**
196 * @}
197 */
198
199 /** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
200 * @{
201 */
202 #define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
203 #define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
204 #define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
205 #define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
206 #define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
207 #define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
208 #define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
209 #define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
210 #define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
211 #define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
212 #define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
213 #define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
214 /**
215 * @}
216 */
217
218 /** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
219 * @{
220 */
221 #define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
222 #define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
223 #define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
224 #define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
225 /**
226 * @}
227 */
228
229
230 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
231 * @{
232 */
233 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
234 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
235 /**
236 * @}
237 */
238
239 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
240 * @{
241 */
242 #define LL_RCC_SYS_CLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */
243 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
244 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
245 #define LL_RCC_SYS_CLKSOURCE_PLL (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< PLL selection as system clock */
246 /**
247 * @}
248 */
249
250 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
251 * @{
252 */
253 #define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */
254 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
255 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
256 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< PLL used as system clock */
257 /**
258 * @}
259 */
260
261 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
262 * @{
263 */
264 #define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */
265 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
266 #define LL_RCC_SYSCLK_DIV_3 RCC_CFGR_HPRE_0 /*!< SYSCLK divided by 3 */
267 #define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
268 #define LL_RCC_SYSCLK_DIV_5 RCC_CFGR_HPRE_1 /*!< SYSCLK divided by 5 */
269 #define LL_RCC_SYSCLK_DIV_6 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 6 */
270 #define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
271 #define LL_RCC_SYSCLK_DIV_10 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 10 */
272 #define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
273 #define LL_RCC_SYSCLK_DIV_32 (RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 32 */
274 #define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
275 #define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
276 #define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
277 #define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */
278 /**
279 * @}
280 */
281
282 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
283 * @{
284 */
285 #define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK1 not divided */
286 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK1 divided by 2 */
287 #define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 4 */
288 #define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK1 divided by 8 */
289 #define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1 | RCC_CFGR_PPRE1_0) /*!< HCLK1 divided by 16 */
290 /**
291 * @}
292 */
293
294 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
295 * @{
296 */
297 #define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK1 not divided */
298 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK1 divided by 2 */
299 #define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 4 */
300 #define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK1 divided by 8 */
301 #define LL_RCC_APB2_DIV_16 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1 | RCC_CFGR_PPRE2_0) /*!< HCLK1 divided by 16 */
302 /**
303 * @}
304 */
305
306 /** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
307 * @{
308 */
309 #define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
310 #define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
311 /**
312 * @}
313 */
314
315 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
316 * @{
317 */
318 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
319 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
320 #define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
321 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
322 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE after stabilization selection as MCO1 source */
323 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLLR selection as MCO1 source */
324 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
325 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_3 /*!< LSE selection as MCO1 source */
326 #define LL_RCC_MCO1SOURCE_PLLPCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< Main PLLQ selection as MCO1 source */
327 #define LL_RCC_MCO1SOURCE_PLLQCLK (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2|RCC_CFGR_MCOSEL_3) /*!< Main PLLP selection as MCO1 source */
328 /**
329 * @}
330 */
331
332 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
333 * @{
334 */
335 #define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */
336 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
337 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
338 #define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
339 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
340 /**
341 * @}
342 */
343
344 #if defined(USE_FULL_LL_DRIVER)
345 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
346 * @{
347 */
348 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
349 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
350 /**
351 * @}
352 */
353 #endif /* USE_FULL_LL_DRIVER */
354
355 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE USARTx CLKSOURCE
356 * @{
357 */
358 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
359 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
360 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
361 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
362 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
363 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
364 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
365 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
366 /**
367 * @}
368 */
369
370 /** @defgroup RCC_LL_EC_I2S2_CLKSOURCE Peripheral I2S clock source selection
371 * @{
372 */
373 #define LL_RCC_I2S2_CLKSOURCE_PLL RCC_CCIPR_I2S2SEL_0 /*!< PLL clock used as I2S2 clock source */
374 #define LL_RCC_I2S2_CLKSOURCE_HSI RCC_CCIPR_I2S2SEL_1 /*!< HSI clock used as I2S2 clock source */
375 #define LL_RCC_I2S2_CLKSOURCE_PIN RCC_CCIPR_I2S2SEL /*!< External clock used as I2S2 clock source */
376 /**
377 * @}
378 */
379
380 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE LPUART1 CLKSOURCE
381 * @{
382 */
383 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */
384 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYCLK selected as LPUART1 clock */
385 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */
386 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock */
387 /**
388 * @}
389 */
390
391 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE I2Cx CLKSOURCE
392 * @{
393 */
394 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C1 clock */
395 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_0 >> 4)) /*!< SYSCLK selected as I2C1 clock */
396 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) | (RCC_CCIPR_I2C1SEL_1 >> 4)) /*!< HSI selected as I2C1 clock */
397 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C2 clock */
398 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_0 >> 4)) /*!< SYSCLK selected as I2C2 clock */
399 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) | (RCC_CCIPR_I2C2SEL_1 >> 4)) /*!< HSI selected as I2C2 clock */
400 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (0x00000000U >> 4)) /*!< PCLK1 selected as I2C3 clock */
401 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_0 >> 4)) /*!< SYSCLK selected as I2C3 clock */
402 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) | (RCC_CCIPR_I2C3SEL_1 >> 4)) /*!< HSI selected as I2C3 clock */
403 /**
404 * @}
405 */
406
407 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE LPTIMx CLKSOURCE
408 * @{
409 */
410 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM1 clock */
411 #define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_0 >> 16)) /*!< LSI selected as LPTIM1 clock */
412 #define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL_1 >> 16)) /*!< HSI selected as LPTIM1 clock */
413 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL | (RCC_CCIPR_LPTIM1SEL >> 16)) /*!< LSE selected as LPTIM1 clock */
414 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM2 clock */
415 #define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_0 >> 16)) /*!< LSI selected as LPTIM2 clock */
416 #define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL_1 >> 16)) /*!< HSI selected as LPTIM2 clock */
417 #define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL | (RCC_CCIPR_LPTIM2SEL >> 16)) /*!< LSE selected as LPTIM2 clock */
418 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM3SEL | (0x00000000U >> 16)) /*!< PCLK1 selected as LPTIM3 clock */
419 #define LL_RCC_LPTIM3_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_0 >> 16)) /*!< LSI selected as LPTIM3 clock */
420 #define LL_RCC_LPTIM3_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL_1 >> 16)) /*!< HSI selected as LPTIM3 clock */
421 #define LL_RCC_LPTIM3_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM3SEL | (RCC_CCIPR_LPTIM3SEL >> 16)) /*!< LSE selected as LPTIM3 clock */
422
423 /**
424 * @}
425 */
426
427 /** @defgroup RCC_LL_EC_ADC_CLKSRC ADC CLKSRC
428 * @{
429 */
430 #define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< no Clock used as ADC clock */
431 #define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR_ADCSEL_0 /*!< HSI selected as ADC clock */
432 #define LL_RCC_ADC_CLKSOURCE_PLL RCC_CCIPR_ADCSEL_1 /*!< PLL selected as ADC clock */
433 #define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /*!< SYSCLK selected as ADC clock */
434 /**
435 * @}
436 */
437
438 /** @defgroup RCC_LL_EC_RNG_CLKSRC RNG CLKSRC
439 * @{
440 */
441 #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL selected as RNG Clock */
442 #define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR_RNGSEL_0 /*!< LSI selected as RNG clock */
443 #define LL_RCC_RNG_CLKSOURCE_LSE RCC_CCIPR_RNGSEL_1 /*!< LSE selected as RNG clock */
444 #define LL_RCC_RNG_CLKSOURCE_MSI (RCC_CCIPR_RNGSEL_1 | RCC_CCIPR_RNGSEL_0) /*!< MSI selected as RNG clock */
445 /**
446 * @}
447 */
448
449 /** @defgroup RCC_LL_EC_USARTx USARTx
450 * @{
451 */
452 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */
453 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selection bits */
454
455 /**
456 * @}
457 */
458
459 /** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
460 * @{
461 */
462 #define LL_RCC_I2S2_CLKSOURCE RCC_CCIPR_I2S2SEL /*!< I2S2 Clock source selection */
463 /**
464 * @}
465 */
466
467 /** @defgroup RCC_LL_EC_LPUART1 LPUART1
468 * @{
469 */
470 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */
471 /**
472 * @}
473 */
474
475 /** @defgroup RCC_LL_EC_I2Cx I2Cx
476 * @{
477 */
478 #define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */
479 #define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL /*!< I2C2 clock source selection bits */
480 #define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */
481 /**
482 * @}
483 */
484
485 /** @defgroup RCC_LL_EC_LPTIMx LPTIMx
486 * @{
487 */
488 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */
489 #define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /*!< LPTIM2 clock source selection bits */
490 #define LL_RCC_LPTIM3_CLKSOURCE RCC_CCIPR_LPTIM3SEL /*!< LPTIM2 clock source selection bits */
491
492 /**
493 * @}
494 */
495
496 /** @defgroup RCC_LL_EC_RNG RNG
497 * @{
498 */
499 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_RNGSEL /*!< RNG clock source selection bits */
500 /**
501 * @}
502 */
503
504 /** @defgroup RCC_LL_EC_ADC ADC
505 * @{
506 */
507 #define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /*!< ADC clock source selection bits */
508 /**
509 * @}
510 */
511
512 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
513 * @{
514 */
515 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
516 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
517 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
518 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
519
520 /**
521 * @}
522 */
523
524 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
525 * @{
526 */
527 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
528 #define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
529 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
530 #define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
531 /**
532 * @}
533 */
534
535 /** @defgroup RCC_LL_EC_PLLM_DIV PLL.division factor
536 * @{
537 */
538 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
539 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 2 */
540 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 3 */
541 #define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 4 */
542 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 5 */
543 #define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)) /*!< PLL division factor by 6 */
544 #define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)) /*!< PLL division factor by 7 */
545 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM) /*!< PLL division factor by 8 */
546 /**
547 * @}
548 */
549
550 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
551 * @{
552 */
553 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
554 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
555 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
556 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
557 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
558 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
559 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
560 /**
561 * @}
562 */
563
564 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
565 * @{
566 */
567 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 2 */
568 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 3 */
569 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1) /*!< Main PLL division factor for PLLP output by 4 */
570 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 5 */
571 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 6 */
572 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 7 */
573 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2) /*!< Main PLL division factor for PLLP output by 8 */
574 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 9 */
575 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 10 */
576 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 11 */
577 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 12 */
578 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 13 */
579 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 14 */
580 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3) /*!< Main PLL division factor for PLLP output by 15 */
581 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3)/*!< Main PLL division factor for PLLP output by 16 */
582 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 17 */
583 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 18 */
584 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 19 */
585 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 20 */
586 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 21 */
587 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 22 */
588 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 23 */
589 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 24 */
590 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 25 */
591 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 26 */
592 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 27*/
593 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 28 */
594 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4) /*!< Main PLL division factor for PLLP output by 29 */
595 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 30 */
596 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 31 */
597 #define LL_RCC_PLLP_DIV_32 (RCC_PLLCFGR_PLLP_0|RCC_PLLCFGR_PLLP_1|RCC_PLLCFGR_PLLP_2|RCC_PLLCFGR_PLLP_3|RCC_PLLCFGR_PLLP_4)/*!< Main PLL division factor for PLLP output by 32 */
598 /**
599 * @}
600 */
601
602 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
603 * @{
604 */
605 #define LL_RCC_PLLQ_DIV_2 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 2 */
606 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 3 */
607 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
608 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 5 */
609 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 6 */
610 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 7 */
611 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
612 /**
613 * @}
614 */
615
616 /** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
617 * @{
618 */
619 #define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */
620 #define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSIRANGE */
621 /**
622 * @}
623 */
624
625 /** @defgroup RCC_LL_EC_LSIPRE LSI division factor
626 * @{
627 */
628 #define LL_RCC_LSI_PREDIV_1 0x00000000U /*!< LSI division factor by 1 */
629 #define LL_RCC_LSI_PREDIV_128 RCC_CSR_LSIPRE /*!< LSI division factor by 128 */
630 /**
631 * @}
632 */
633
634 /**
635 * @}
636 */
637
638 /* Exported macro ------------------------------------------------------------*/
639 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
640 * @{
641 */
642
643 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
644 * @{
645 */
646
647 /**
648 * @brief Write a value in RCC register
649 * @param __REG__ Register to be written
650 * @param __VALUE__ Value to be written in the register
651 * @retval None
652 */
653 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
654
655 /**
656 * @brief Read a value in RCC register
657 * @param __REG__ Register to be read
658 * @retval Register value
659 */
660 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
661 /**
662 * @}
663 */
664
665 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
666 * @{
667 */
668
669 /**
670 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
671 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
672 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
673 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
674 * @param __PLLM__ This parameter can be one of the following values:
675 * @arg @ref LL_RCC_PLLM_DIV_1
676 * @arg @ref LL_RCC_PLLM_DIV_2
677 * @arg @ref LL_RCC_PLLM_DIV_3
678 * @arg @ref LL_RCC_PLLM_DIV_4
679 * @arg @ref LL_RCC_PLLM_DIV_5
680 * @arg @ref LL_RCC_PLLM_DIV_6
681 * @arg @ref LL_RCC_PLLM_DIV_7
682 * @arg @ref LL_RCC_PLLM_DIV_8
683 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
684 * @param __PLLR__ This parameter can be one of the following values:
685 * @arg @ref LL_RCC_PLLR_DIV_2
686 * @arg @ref LL_RCC_PLLR_DIV_3
687 * @arg @ref LL_RCC_PLLR_DIV_4
688 * @arg @ref LL_RCC_PLLR_DIV_5
689 * @arg @ref LL_RCC_PLLR_DIV_6
690 * @arg @ref LL_RCC_PLLR_DIV_7
691 * @arg @ref LL_RCC_PLLR_DIV_8
692 * @retval PLL clock frequency (in Hz)
693 */
694 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \
695 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
696 (((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U))
697
698 /**
699 * @brief Helper macro to calculate the PLLPCLK frequency used on ADC domain
700 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
701 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
702 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
703 * @param __PLLM__ This parameter can be one of the following values:
704 * @arg @ref LL_RCC_PLLM_DIV_1
705 * @arg @ref LL_RCC_PLLM_DIV_2
706 * @arg @ref LL_RCC_PLLM_DIV_3
707 * @arg @ref LL_RCC_PLLM_DIV_4
708 * @arg @ref LL_RCC_PLLM_DIV_5
709 * @arg @ref LL_RCC_PLLM_DIV_6
710 * @arg @ref LL_RCC_PLLM_DIV_7
711 * @arg @ref LL_RCC_PLLM_DIV_8
712 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
713 * @param __PLLP__ This parameter can be one of the following values:
714 * @arg @ref LL_RCC_PLLP_DIV_2
715 * @arg @ref LL_RCC_PLLP_DIV_3
716 * @arg @ref LL_RCC_PLLP_DIV_4
717 * @arg @ref LL_RCC_PLLP_DIV_5
718 * @arg @ref LL_RCC_PLLP_DIV_6
719 * @arg @ref LL_RCC_PLLP_DIV_7
720 * @arg @ref LL_RCC_PLLP_DIV_8
721 * @arg @ref LL_RCC_PLLP_DIV_9
722 * @arg @ref LL_RCC_PLLP_DIV_10
723 * @arg @ref LL_RCC_PLLP_DIV_11
724 * @arg @ref LL_RCC_PLLP_DIV_12
725 * @arg @ref LL_RCC_PLLP_DIV_13
726 * @arg @ref LL_RCC_PLLP_DIV_14
727 * @arg @ref LL_RCC_PLLP_DIV_15
728 * @arg @ref LL_RCC_PLLP_DIV_16
729 * @arg @ref LL_RCC_PLLP_DIV_17
730 * @arg @ref LL_RCC_PLLP_DIV_18
731 * @arg @ref LL_RCC_PLLP_DIV_19
732 * @arg @ref LL_RCC_PLLP_DIV_20
733 * @arg @ref LL_RCC_PLLP_DIV_21
734 * @arg @ref LL_RCC_PLLP_DIV_22
735 * @arg @ref LL_RCC_PLLP_DIV_23
736 * @arg @ref LL_RCC_PLLP_DIV_24
737 * @arg @ref LL_RCC_PLLP_DIV_25
738 * @arg @ref LL_RCC_PLLP_DIV_26
739 * @arg @ref LL_RCC_PLLP_DIV_27
740 * @arg @ref LL_RCC_PLLP_DIV_28
741 * @arg @ref LL_RCC_PLLP_DIV_29
742 * @arg @ref LL_RCC_PLLP_DIV_30
743 * @arg @ref LL_RCC_PLLP_DIV_31
744 * @arg @ref LL_RCC_PLLP_DIV_32
745 * @retval PLL clock frequency (in Hz)
746 */
747 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \
748 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
749 (((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos) + 1U))
750
751 /**
752 * @brief Helper macro to calculate the PLLQCLK frequency used on RNG domain
753 * @note ex: @ref __LL_RCC_CALC_PLLCLK_RNG_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
754 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
755 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
756 * @param __PLLM__ This parameter can be one of the following values:
757 * @arg @ref LL_RCC_PLLM_DIV_1
758 * @arg @ref LL_RCC_PLLM_DIV_2
759 * @arg @ref LL_RCC_PLLM_DIV_3
760 * @arg @ref LL_RCC_PLLM_DIV_4
761 * @arg @ref LL_RCC_PLLM_DIV_5
762 * @arg @ref LL_RCC_PLLM_DIV_6
763 * @arg @ref LL_RCC_PLLM_DIV_7
764 * @arg @ref LL_RCC_PLLM_DIV_8
765 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
766 * @param __PLLQ__ This parameter can be one of the following values:
767 * @arg @ref LL_RCC_PLLQ_DIV_2
768 * @arg @ref LL_RCC_PLLQ_DIV_3
769 * @arg @ref LL_RCC_PLLQ_DIV_4
770 * @arg @ref LL_RCC_PLLQ_DIV_5
771 * @arg @ref LL_RCC_PLLQ_DIV_6
772 * @arg @ref LL_RCC_PLLQ_DIV_7
773 * @arg @ref LL_RCC_PLLQ_DIV_8
774 * @retval PLL clock frequency (in Hz)
775 */
776 #define __LL_RCC_CALC_PLLCLK_RNG_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \
777 ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
778 (((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U))
779
780 /**
781 * @brief Helper macro to calculate the PLLQCLK frequency used on I2S domain
782 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S2_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
783 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
784 * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
785 * @param __PLLM__ This parameter can be one of the following values:
786 * @arg @ref LL_RCC_PLLM_DIV_1
787 * @arg @ref LL_RCC_PLLM_DIV_2
788 * @arg @ref LL_RCC_PLLM_DIV_3
789 * @arg @ref LL_RCC_PLLM_DIV_4
790 * @arg @ref LL_RCC_PLLM_DIV_5
791 * @arg @ref LL_RCC_PLLM_DIV_6
792 * @arg @ref LL_RCC_PLLM_DIV_7
793 * @arg @ref LL_RCC_PLLM_DIV_8
794 * @param __PLLN__ Between Min_Data = 6 and Max_Data = 127
795 * @param __PLLQ__ This parameter can be one of the following values:
796 * @arg @ref LL_RCC_PLLQ_DIV_2
797 * @arg @ref LL_RCC_PLLQ_DIV_3
798 * @arg @ref LL_RCC_PLLQ_DIV_4
799 * @arg @ref LL_RCC_PLLQ_DIV_5
800 * @arg @ref LL_RCC_PLLQ_DIV_6
801 * @arg @ref LL_RCC_PLLQ_DIV_7
802 * @arg @ref LL_RCC_PLLQ_DIV_8
803 * @retval PLL clock frequency (in Hz)
804 */
805 #define __LL_RCC_CALC_PLLCLK_I2S2_FREQ __LL_RCC_CALC_PLLCLK_RNG_FREQ
806
807 /**
808 * @brief Helper macro to calculate the HCLK1 frequency
809 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
810 * @param __CPU1PRESCALER__ This parameter can be one of the following values:
811 * @arg @ref LL_RCC_SYSCLK_DIV_1
812 * @arg @ref LL_RCC_SYSCLK_DIV_2
813 * @arg @ref LL_RCC_SYSCLK_DIV_3
814 * @arg @ref LL_RCC_SYSCLK_DIV_4
815 * @arg @ref LL_RCC_SYSCLK_DIV_5
816 * @arg @ref LL_RCC_SYSCLK_DIV_6
817 * @arg @ref LL_RCC_SYSCLK_DIV_8
818 * @arg @ref LL_RCC_SYSCLK_DIV_10
819 * @arg @ref LL_RCC_SYSCLK_DIV_16
820 * @arg @ref LL_RCC_SYSCLK_DIV_32
821 * @arg @ref LL_RCC_SYSCLK_DIV_64
822 * @arg @ref LL_RCC_SYSCLK_DIV_128
823 * @arg @ref LL_RCC_SYSCLK_DIV_256
824 * @arg @ref LL_RCC_SYSCLK_DIV_512
825 * @retval HCLK1 clock frequency (in Hz)
826 */
827 #define __LL_RCC_CALC_HCLK1_FREQ(__SYSCLKFREQ__,__CPU1PRESCALER__) \
828 ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU1PRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
829
830 #if defined(DUAL_CORE)
831 /**
832 * @brief Helper macro to calculate the HCLK2 frequency
833 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
834 * @param __CPU2PRESCALER__ This parameter can be one of the following values:
835 * @arg @ref LL_RCC_SYSCLK_DIV_1
836 * @arg @ref LL_RCC_SYSCLK_DIV_2
837 * @arg @ref LL_RCC_SYSCLK_DIV_3
838 * @arg @ref LL_RCC_SYSCLK_DIV_4
839 * @arg @ref LL_RCC_SYSCLK_DIV_5
840 * @arg @ref LL_RCC_SYSCLK_DIV_6
841 * @arg @ref LL_RCC_SYSCLK_DIV_8
842 * @arg @ref LL_RCC_SYSCLK_DIV_10
843 * @arg @ref LL_RCC_SYSCLK_DIV_16
844 * @arg @ref LL_RCC_SYSCLK_DIV_32
845 * @arg @ref LL_RCC_SYSCLK_DIV_64
846 * @arg @ref LL_RCC_SYSCLK_DIV_128
847 * @arg @ref LL_RCC_SYSCLK_DIV_256
848 * @arg @ref LL_RCC_SYSCLK_DIV_512
849 * @retval HCLK2 clock frequency (in Hz)
850 */
851 #define __LL_RCC_CALC_HCLK2_FREQ(__SYSCLKFREQ__, __CPU2PRESCALER__) \
852 ((__SYSCLKFREQ__) / AHBPrescTable[((__CPU2PRESCALER__) & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos])
853 #endif /* DUAL_CORE */
854
855 /**
856 * @brief Helper macro to calculate the HCLK3 frequency
857 * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
858 * @param __AHB3PRESCALER__ This parameter can be one of the following values:
859 * @arg @ref LL_RCC_SYSCLK_DIV_1
860 * @arg @ref LL_RCC_SYSCLK_DIV_2
861 * @arg @ref LL_RCC_SYSCLK_DIV_3
862 * @arg @ref LL_RCC_SYSCLK_DIV_4
863 * @arg @ref LL_RCC_SYSCLK_DIV_5
864 * @arg @ref LL_RCC_SYSCLK_DIV_6
865 * @arg @ref LL_RCC_SYSCLK_DIV_8
866 * @arg @ref LL_RCC_SYSCLK_DIV_10
867 * @arg @ref LL_RCC_SYSCLK_DIV_16
868 * @arg @ref LL_RCC_SYSCLK_DIV_32
869 * @arg @ref LL_RCC_SYSCLK_DIV_64
870 * @arg @ref LL_RCC_SYSCLK_DIV_128
871 * @arg @ref LL_RCC_SYSCLK_DIV_256
872 * @arg @ref LL_RCC_SYSCLK_DIV_512
873 * @retval HCLK3 clock frequency (in Hz)
874 */
875 #define __LL_RCC_CALC_HCLK3_FREQ(__SYSCLKFREQ__, __AHB3PRESCALER__) \
876 ((__SYSCLKFREQ__) / AHBPrescTable[(((__AHB3PRESCALER__) >> 4U) & RCC_EXTCFGR_SHDHPRE) >> RCC_EXTCFGR_SHDHPRE_Pos])
877
878
879 /**
880 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
881 * @param __HCLKFREQ__ HCLK frequency
882 * @param __APB1PRESCALER__ This parameter can be one of the following values:
883 * @arg @ref LL_RCC_APB1_DIV_1
884 * @arg @ref LL_RCC_APB1_DIV_2
885 * @arg @ref LL_RCC_APB1_DIV_4
886 * @arg @ref LL_RCC_APB1_DIV_8
887 * @arg @ref LL_RCC_APB1_DIV_16
888 * @retval PCLK1 clock frequency (in Hz)
889 */
890 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \
891 ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
892
893 /**
894 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
895 * @param __HCLKFREQ__ HCLK frequency
896 * @param __APB2PRESCALER__ This parameter can be one of the following values:
897 * @arg @ref LL_RCC_APB2_DIV_1
898 * @arg @ref LL_RCC_APB2_DIV_2
899 * @arg @ref LL_RCC_APB2_DIV_4
900 * @arg @ref LL_RCC_APB2_DIV_8
901 * @arg @ref LL_RCC_APB2_DIV_16
902 * @retval PCLK2 clock frequency (in Hz)
903 */
904 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) \
905 ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
906
907 /**
908 * @brief Helper macro to calculate the MSI frequency (in Hz)
909 * @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
910 * @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
911 * __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
912 * else by LL_RCC_MSI_GetRange()
913 * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
914 * (LL_RCC_MSI_IsEnabledRangeSelect()?
915 * LL_RCC_MSI_GetRange():
916 * LL_RCC_MSI_GetRangeAfterStandby()))
917 * @param __MSISEL__ This parameter can be one of the following values:
918 * @arg @ref LL_RCC_MSIRANGESEL_STANDBY
919 * @arg @ref LL_RCC_MSIRANGESEL_RUN
920 * @param __MSIRANGE__ This parameter can be one of the following values:
921 * @arg @ref LL_RCC_MSIRANGE_0
922 * @arg @ref LL_RCC_MSIRANGE_1
923 * @arg @ref LL_RCC_MSIRANGE_2
924 * @arg @ref LL_RCC_MSIRANGE_3
925 * @arg @ref LL_RCC_MSIRANGE_4
926 * @arg @ref LL_RCC_MSIRANGE_5
927 * @arg @ref LL_RCC_MSIRANGE_6
928 * @arg @ref LL_RCC_MSIRANGE_7
929 * @arg @ref LL_RCC_MSIRANGE_8
930 * @arg @ref LL_RCC_MSIRANGE_9
931 * @arg @ref LL_RCC_MSIRANGE_10
932 * @arg @ref LL_RCC_MSIRANGE_11
933 * @arg @ref LL_RCC_MSISRANGE_4
934 * @arg @ref LL_RCC_MSISRANGE_5
935 * @arg @ref LL_RCC_MSISRANGE_6
936 * @arg @ref LL_RCC_MSISRANGE_7
937 * @retval MSI clock frequency (in Hz)
938 */
939 #define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) \
940 (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
941 (MSIRangeTable[((__MSIRANGE__) & RCC_CSR_MSISRANGE_Msk) >> RCC_CSR_MSISRANGE_Pos ]) : \
942 (MSIRangeTable[((__MSIRANGE__) & RCC_CR_MSIRANGE_Msk) >> RCC_CR_MSIRANGE_Pos]))
943
944 /**
945 * @}
946 */
947
948
949 /**
950 * @}
951 */
952
953 /* Exported functions --------------------------------------------------------*/
954 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
955 * @{
956 */
957
958 /** @defgroup RCC_LL_EF_HSE HSE
959 * @{
960 */
961
962 /**
963 * @brief Enable HSE VDDTCXO output on package pin PB0-VDDTCXO
964 * @note PB0 must be configured in analog mode prior enabling VDDTCXO supply
965 * @rmtoll CR HSEBYPPWR LL_RCC_HSE_EnableTcxo
966 * @retval None
967 */
LL_RCC_HSE_EnableTcxo(void)968 __STATIC_INLINE void LL_RCC_HSE_EnableTcxo(void)
969 {
970 SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR);
971 }
972
973 /**
974 * @brief Disable HSE VDDTCXO output on package pin PB0-VDDTCXO
975 * @rmtoll CR HSEBYPPWR LL_RCC_HSE_DisableTcxo
976 * @retval None
977 */
LL_RCC_HSE_DisableTcxo(void)978 __STATIC_INLINE void LL_RCC_HSE_DisableTcxo(void)
979 {
980 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR);
981 }
982
983 /**
984 * @brief Get HSE VDDTCXO output on package pin PB0-VDDTCXO
985 * @rmtoll CR HSEBYPPWR LL_RCC_HSE_IsEnabledTcxo
986 * @retval None
987 */
LL_RCC_HSE_IsEnabledTcxo(void)988 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledTcxo(void)
989 {
990 return ((READ_BIT(RCC->CR, RCC_CR_HSEBYPPWR) == (RCC_CR_HSEBYPPWR)) ? 1UL : 0UL);
991 }
992
993
994 /**
995 * @brief Enable HSE sysclk and pll prescaler division by 2
996 * @rmtoll CR HSEPRE LL_RCC_HSE_EnableDiv2
997 * @retval None
998 */
LL_RCC_HSE_EnableDiv2(void)999 __STATIC_INLINE void LL_RCC_HSE_EnableDiv2(void)
1000 {
1001 SET_BIT(RCC->CR, RCC_CR_HSEPRE);
1002 }
1003
1004 /**
1005 * @brief Disable HSE sysclk and pll prescaler division by 2
1006 * @rmtoll CR HSEPRE LL_RCC_HSE_DisableDiv2
1007 * @retval None
1008 */
LL_RCC_HSE_DisableDiv2(void)1009 __STATIC_INLINE void LL_RCC_HSE_DisableDiv2(void)
1010 {
1011 CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE);
1012 }
1013
1014 /**
1015 * @brief Get HSE sysclk and pll prescaler division by 2
1016 * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledDiv2
1017 * @retval None
1018 */
LL_RCC_HSE_IsEnabledDiv2(void)1019 __STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledDiv2(void)
1020 {
1021 return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL);
1022 }
1023
1024 /**
1025 * @brief Enable the Clock Security System.
1026 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1027 * @retval None
1028 */
LL_RCC_HSE_EnableCSS(void)1029 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1030 {
1031 SET_BIT(RCC->CR, RCC_CR_CSSON);
1032 }
1033
1034 /**
1035 * @brief Enable HSE crystal oscillator (HSE ON)
1036 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1037 * @retval None
1038 */
LL_RCC_HSE_Enable(void)1039 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1040 {
1041 SET_BIT(RCC->CR, RCC_CR_HSEON);
1042 }
1043
1044 /**
1045 * @brief Disable HSE crystal oscillator (HSE ON)
1046 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1047 * @retval None
1048 */
LL_RCC_HSE_Disable(void)1049 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1050 {
1051 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1052 }
1053
1054 /**
1055 * @brief Check if HSE oscillator Ready
1056 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1057 * @retval State of bit (1 or 0).
1058 */
LL_RCC_HSE_IsReady(void)1059 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1060 {
1061 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1062 }
1063
1064 /**
1065 * @}
1066 */
1067
1068 /** @defgroup RCC_LL_EF_HSI HSI
1069 * @{
1070 */
1071
1072 /**
1073 * @brief Enable HSI even in stop mode
1074 * @note HSI oscillator is forced ON even in Stop mode
1075 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
1076 * @retval None
1077 */
LL_RCC_HSI_EnableInStopMode(void)1078 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
1079 {
1080 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1081 }
1082
1083 /**
1084 * @brief Disable HSI in stop mode
1085 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
1086 * @retval None
1087 */
LL_RCC_HSI_DisableInStopMode(void)1088 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
1089 {
1090 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1091 }
1092
1093 /**
1094 * @brief Check if HSI in stop mode is ready
1095 * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
1096 * @retval State of bit (1 or 0).
1097 */
LL_RCC_HSI_IsEnabledInStopMode(void)1098 __STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
1099 {
1100 return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON)) ? 1UL : 0UL);
1101 }
1102
1103 /**
1104 * @brief Enable HSI oscillator
1105 * @rmtoll CR HSION LL_RCC_HSI_Enable
1106 * @retval None
1107 */
LL_RCC_HSI_Enable(void)1108 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1109 {
1110 SET_BIT(RCC->CR, RCC_CR_HSION);
1111 }
1112
1113 /**
1114 * @brief Disable HSI oscillator
1115 * @rmtoll CR HSION LL_RCC_HSI_Disable
1116 * @retval None
1117 */
LL_RCC_HSI_Disable(void)1118 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1119 {
1120 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1121 }
1122
1123 /**
1124 * @brief Check if HSI clock is ready
1125 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1126 * @retval State of bit (1 or 0).
1127 */
LL_RCC_HSI_IsReady(void)1128 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1129 {
1130 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1131 }
1132
1133 /**
1134 * @brief Enable HSI Automatic from stop mode
1135 * @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
1136 * @retval None
1137 */
LL_RCC_HSI_EnableAutoFromStop(void)1138 __STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
1139 {
1140 SET_BIT(RCC->CR, RCC_CR_HSIASFS);
1141 }
1142
1143 /**
1144 * @brief Disable HSI Automatic from stop mode
1145 * @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
1146 * @retval None
1147 */
LL_RCC_HSI_DisableAutoFromStop(void)1148 __STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
1149 {
1150 CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
1151 }
1152 /**
1153 * @brief Get HSI Calibration value
1154 * @note When HSITRIM is written, HSICAL is updated with the sum of
1155 * HSITRIM and the factory trim value
1156 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1157 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1158 */
LL_RCC_HSI_GetCalibration(void)1159 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1160 {
1161 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1162 }
1163
1164 /**
1165 * @brief Set HSI Calibration trimming
1166 * @note user-programmable trimming value that is added to the HSICAL
1167 * @note Default value is 64, which, when added to the HSICAL value,
1168 * should trim the HSI to 16 MHz +/- 1 %
1169 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1170 * @param Value Between Min_Data = 0 and Max_Data = 127
1171 * @retval None
1172 */
LL_RCC_HSI_SetCalibTrimming(uint32_t Value)1173 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1174 {
1175 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1176 }
1177
1178 /**
1179 * @brief Get HSI Calibration trimming
1180 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1181 * @retval Between Min_Data = 0 and Max_Data = 127
1182 */
LL_RCC_HSI_GetCalibTrimming(void)1183 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1184 {
1185 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1186 }
1187
1188 /**
1189 * @}
1190 */
1191
1192 /** @defgroup RCC_LL_EF_LSE LSE
1193 * @{
1194 */
1195
1196 /**
1197 * @brief Enable Low Speed External (LSE) crystal.
1198 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1199 * @retval None
1200 */
LL_RCC_LSE_Enable(void)1201 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1202 {
1203 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1204 }
1205
1206 /**
1207 * @brief Disable Low Speed External (LSE) crystal.
1208 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1209 * @retval None
1210 */
LL_RCC_LSE_Disable(void)1211 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1212 {
1213 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1214 }
1215
1216 /**
1217 * @brief Check if Low Speed External (LSE) crystal has been enabled or not
1218 * @rmtoll BDCR LSEON LL_RCC_LSE_IsEnabled
1219 * @retval State of bit (1 or 0).
1220 */
LL_RCC_LSE_IsEnabled(void)1221 __STATIC_INLINE uint32_t LL_RCC_LSE_IsEnabled(void)
1222 {
1223 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEON) == (RCC_BDCR_LSEON)) ? 1UL : 0UL);
1224 }
1225
1226 /**
1227 * @brief Enable external clock source (LSE bypass).
1228 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1229 * @retval None
1230 */
LL_RCC_LSE_EnableBypass(void)1231 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1232 {
1233 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1234 }
1235
1236 /**
1237 * @brief Disable external clock source (LSE bypass).
1238 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1239 * @retval None
1240 */
LL_RCC_LSE_DisableBypass(void)1241 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1242 {
1243 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1244 }
1245
1246 /**
1247 * @brief Set LSE oscillator drive capability
1248 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1249 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1250 * @param LSEDrive This parameter can be one of the following values:
1251 * @arg @ref LL_RCC_LSEDRIVE_LOW
1252 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1253 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1254 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1255 * @retval None
1256 */
LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)1257 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1258 {
1259 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1260 }
1261
1262 /**
1263 * @brief Get LSE oscillator drive capability
1264 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1265 * @retval Returned value can be one of the following values:
1266 * @arg @ref LL_RCC_LSEDRIVE_LOW
1267 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1268 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1269 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1270 */
LL_RCC_LSE_GetDriveCapability(void)1271 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1272 {
1273 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1274 }
1275
1276 /**
1277 * @brief Enable Clock security system on LSE.
1278 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1279 * @retval None
1280 */
LL_RCC_LSE_EnableCSS(void)1281 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1282 {
1283 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1284 }
1285
1286 /**
1287 * @brief Disable Clock security system on LSE.
1288 * @note Clock security system can be disabled only after a LSE
1289 * failure detection. In that case it MUST be disabled by software.
1290 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1291 * @retval None
1292 */
LL_RCC_LSE_DisableCSS(void)1293 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1294 {
1295 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1296 }
1297
1298 /**
1299 * @brief Enable LSE oscillator propagation for system clock
1300 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation
1301 * @retval None
1302 */
LL_RCC_LSE_EnablePropagation(void)1303 __STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void)
1304 {
1305 SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1306 }
1307
1308 /**
1309 * @brief Disable LSE oscillator propagation for system clock
1310 * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation
1311 * @retval None
1312 */
LL_RCC_LSE_DisablePropagation(void)1313 __STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void)
1314 {
1315 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
1316 }
1317
1318 /**
1319 * @brief Check if LSE oscillator propagation for system clock Ready
1320 * @rmtoll BDCR LSEYSRDY LL_RCC_LSE_IsPropagationReady
1321 * @retval State of bit (1 or 0).
1322 */
LL_RCC_LSE_IsPropagationReady(void)1323 __STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void)
1324 {
1325 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == (RCC_BDCR_LSESYSRDY)) ? 1UL : 0UL);
1326 }
1327
1328
1329 /**
1330 * @brief Check if LSE oscillator Ready
1331 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1332 * @retval State of bit (1 or 0).
1333 */
LL_RCC_LSE_IsReady(void)1334 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1335 {
1336 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1337 }
1338
1339 /**
1340 * @brief Check if CSS on LSE failure Detection
1341 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1342 * @retval State of bit (1 or 0).
1343 */
LL_RCC_LSE_IsCSSDetected(void)1344 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1345 {
1346 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1347 }
1348
1349 /**
1350 * @}
1351 */
1352
1353 /** @defgroup RCC_LL_EF_LSI LSI
1354 * @{
1355 */
1356
1357
1358 /**
1359 * @brief Set LSI division factor
1360 * @rmtoll CSR LSIPRE LL_RCC_LSI_SetPrediv
1361 * @param LSI_PREDIV This parameter can be one of the following values:
1362 * @arg @ref LL_RCC_LSI_PREDIV_1
1363 * @arg @ref LL_RCC_LSI_PREDIV_128
1364 * @retval None
1365 */
LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)1366 __STATIC_INLINE void LL_RCC_LSI_SetPrediv(uint32_t LSI_PREDIV)
1367 {
1368 MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, LSI_PREDIV);
1369 }
1370
1371 /**
1372 * @brief Get LSI division factor
1373 * @rmtoll CSR LSIPRE LL_RCC_LSI_GetPrediv
1374 * @retval Returned value can be one of the following values:
1375 * @arg @ref LL_RCC_LSI_PREDIV_1
1376 * @arg @ref LL_RCC_LSI_PREDIV_128
1377 */
LL_RCC_LSI_GetPrediv(void)1378 __STATIC_INLINE uint32_t LL_RCC_LSI_GetPrediv(void)
1379 {
1380 return (READ_BIT(RCC->CSR, RCC_CSR_LSIPRE));
1381 }
1382
1383
1384 /**
1385 * @brief Enable LSI Oscillator
1386 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1387 * @retval None
1388 */
LL_RCC_LSI_Enable(void)1389 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1390 {
1391 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1392 }
1393
1394 /**
1395 * @brief Disable LSI Oscillator
1396 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1397 * @retval None
1398 */
LL_RCC_LSI_Disable(void)1399 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1400 {
1401 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1402 }
1403
1404 /**
1405 * @brief Check if LSI is Ready
1406 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1407 * @retval State of bit (1 or 0).
1408 */
LL_RCC_LSI_IsReady(void)1409 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1410 {
1411 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1412 }
1413
1414 /**
1415 * @}
1416 */
1417
1418 /** @defgroup RCC_LL_EF_MSI MSI
1419 * @{
1420 */
1421
1422 /**
1423 * @brief Enable MSI oscillator
1424 * @rmtoll CR MSION LL_RCC_MSI_Enable
1425 * @retval None
1426 */
LL_RCC_MSI_Enable(void)1427 __STATIC_INLINE void LL_RCC_MSI_Enable(void)
1428 {
1429 SET_BIT(RCC->CR, RCC_CR_MSION);
1430 }
1431
1432 /**
1433 * @brief Disable MSI oscillator
1434 * @rmtoll CR MSION LL_RCC_MSI_Disable
1435 * @retval None
1436 */
LL_RCC_MSI_Disable(void)1437 __STATIC_INLINE void LL_RCC_MSI_Disable(void)
1438 {
1439 CLEAR_BIT(RCC->CR, RCC_CR_MSION);
1440 }
1441
1442 /**
1443 * @brief Check if MSI oscillator Ready
1444 * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
1445 * @retval State of bit (1 or 0).
1446 */
LL_RCC_MSI_IsReady(void)1447 __STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
1448 {
1449 return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL);
1450 }
1451
1452 /**
1453 * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
1454 * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
1455 * and ready (LSERDY set by hardware)
1456 * @note hardware protection to avoid enabling MSIPLLEN if LSE is not
1457 * ready
1458 * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
1459 * @retval None
1460 */
LL_RCC_MSI_EnablePLLMode(void)1461 __STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
1462 {
1463 SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1464 }
1465
1466 /**
1467 * @brief Disable MSI-PLL mode
1468 * @note cleared by hardware when LSE is disabled (LSEON = 0) or when
1469 * the Clock Security System on LSE detects a LSE failure
1470 * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
1471 * @retval None
1472 */
LL_RCC_MSI_DisablePLLMode(void)1473 __STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
1474 {
1475 CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
1476 }
1477
1478 /**
1479 * @brief Enable MSI clock range selection with MSIRANGE register
1480 * @note Write 0 has no effect. After a standby or a reset
1481 * MSIRGSEL is at 0 and the MSI range value is provided by
1482 * MSISRANGE
1483 * @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
1484 * @retval None
1485 */
LL_RCC_MSI_EnableRangeSelection(void)1486 __STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
1487 {
1488 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
1489 }
1490
1491 /**
1492 * @brief Check if MSI clock range is selected with MSIRANGE register
1493 * @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
1494 * @retval State of bit (1 or 0).
1495 */
LL_RCC_MSI_IsEnabledRangeSelect(void)1496 __STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
1497 {
1498 return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL);
1499 }
1500
1501 /**
1502 * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
1503 * @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
1504 * @param Range This parameter can be one of the following values:
1505 * @arg @ref LL_RCC_MSIRANGE_0
1506 * @arg @ref LL_RCC_MSIRANGE_1
1507 * @arg @ref LL_RCC_MSIRANGE_2
1508 * @arg @ref LL_RCC_MSIRANGE_3
1509 * @arg @ref LL_RCC_MSIRANGE_4
1510 * @arg @ref LL_RCC_MSIRANGE_5
1511 * @arg @ref LL_RCC_MSIRANGE_6
1512 * @arg @ref LL_RCC_MSIRANGE_7
1513 * @arg @ref LL_RCC_MSIRANGE_8
1514 * @arg @ref LL_RCC_MSIRANGE_9
1515 * @arg @ref LL_RCC_MSIRANGE_10
1516 * @arg @ref LL_RCC_MSIRANGE_11
1517 * @retval None
1518 */
LL_RCC_MSI_SetRange(uint32_t Range)1519 __STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
1520 {
1521 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
1522 }
1523
1524 /**
1525 * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
1526 * @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
1527 * @retval Returned value can be one of the following values:
1528 * @arg @ref LL_RCC_MSIRANGE_0
1529 * @arg @ref LL_RCC_MSIRANGE_1
1530 * @arg @ref LL_RCC_MSIRANGE_2
1531 * @arg @ref LL_RCC_MSIRANGE_3
1532 * @arg @ref LL_RCC_MSIRANGE_4
1533 * @arg @ref LL_RCC_MSIRANGE_5
1534 * @arg @ref LL_RCC_MSIRANGE_6
1535 * @arg @ref LL_RCC_MSIRANGE_7
1536 * @arg @ref LL_RCC_MSIRANGE_8
1537 * @arg @ref LL_RCC_MSIRANGE_9
1538 * @arg @ref LL_RCC_MSIRANGE_10
1539 * @arg @ref LL_RCC_MSIRANGE_11
1540 */
LL_RCC_MSI_GetRange(void)1541 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
1542 {
1543 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
1544 }
1545
1546 /**
1547 * @brief Configure MSI range used after standby
1548 * @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
1549 * @param Range This parameter can be one of the following values:
1550 * @arg @ref LL_RCC_MSISRANGE_4
1551 * @arg @ref LL_RCC_MSISRANGE_5
1552 * @arg @ref LL_RCC_MSISRANGE_6
1553 * @arg @ref LL_RCC_MSISRANGE_7
1554 * @retval None
1555 */
LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)1556 __STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
1557 {
1558 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
1559 }
1560
1561 /**
1562 * @brief Get MSI range used after standby
1563 * @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
1564 * @retval Returned value can be one of the following values:
1565 * @arg @ref LL_RCC_MSISRANGE_4
1566 * @arg @ref LL_RCC_MSISRANGE_5
1567 * @arg @ref LL_RCC_MSISRANGE_6
1568 * @arg @ref LL_RCC_MSISRANGE_7
1569 */
LL_RCC_MSI_GetRangeAfterStandby(void)1570 __STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
1571 {
1572 return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
1573 }
1574
1575 /**
1576 * @brief Get MSI Calibration value
1577 * @note When MSITRIM is written, MSICAL is updated with the sum of
1578 * MSITRIM and the factory trim value
1579 * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
1580 * @retval Between Min_Data = 0 and Max_Data = 255
1581 */
LL_RCC_MSI_GetCalibration(void)1582 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
1583 {
1584 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
1585 }
1586
1587 /**
1588 * @brief Set MSI Calibration trimming
1589 * @note user-programmable trimming value that is added to the MSICAL
1590 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
1591 * @param Value Between Min_Data = 0 and Max_Data = 255
1592 * @retval None
1593 */
LL_RCC_MSI_SetCalibTrimming(uint32_t Value)1594 __STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
1595 {
1596 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
1597 }
1598
1599 /**
1600 * @brief Get MSI Calibration trimming
1601 * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
1602 * @retval Between 0 and 255
1603 */
LL_RCC_MSI_GetCalibTrimming(void)1604 __STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
1605 {
1606 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
1607 }
1608
1609 /**
1610 * @}
1611 */
1612
1613 /** @defgroup RCC_LL_EF_LSCO LSCO
1614 * @{
1615 */
1616
1617 /**
1618 * @brief Enable Low speed clock
1619 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1620 * @retval None
1621 */
LL_RCC_LSCO_Enable(void)1622 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1623 {
1624 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1625 }
1626
1627 /**
1628 * @brief Disable Low speed clock
1629 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1630 * @retval None
1631 */
LL_RCC_LSCO_Disable(void)1632 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1633 {
1634 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1635 }
1636
1637 /**
1638 * @brief Configure Low speed clock selection
1639 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1640 * @param Source This parameter can be one of the following values:
1641 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1642 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1643 * @retval None
1644 */
LL_RCC_LSCO_SetSource(uint32_t Source)1645 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1646 {
1647 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1648 }
1649
1650 /**
1651 * @brief Get Low speed clock selection
1652 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1653 * @retval Returned value can be one of the following values:
1654 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1655 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1656 */
LL_RCC_LSCO_GetSource(void)1657 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1658 {
1659 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1660 }
1661
1662 /**
1663 * @}
1664 */
1665
1666 /** @defgroup RCC_LL_EF_RF RF
1667 * @{
1668 */
1669
1670 /**
1671 * @brief Enable radio reset
1672 * @rmtoll CSR RFRST LL_RCC_RF_EnableReset
1673 * @retval None
1674 */
LL_RCC_RF_EnableReset(void)1675 __STATIC_INLINE void LL_RCC_RF_EnableReset(void)
1676 {
1677 SET_BIT(RCC->CSR, RCC_CSR_RFRST);
1678 }
1679
1680 /**
1681 * @brief Disable radio reset
1682 * @rmtoll CSR RFRST LL_RCC_RF_DisableReset
1683 * @retval None
1684 */
LL_RCC_RF_DisableReset(void)1685 __STATIC_INLINE void LL_RCC_RF_DisableReset(void)
1686 {
1687 CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST);
1688 }
1689
1690 /**
1691 * @brief Get radio reset
1692 * @rmtoll CSR RFRST LL_RCC_RF_IsEnabledReset
1693 * @retval None
1694 */
LL_RCC_RF_IsEnabledReset(void)1695 __STATIC_INLINE uint32_t LL_RCC_RF_IsEnabledReset(void)
1696 {
1697 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRST) == (RCC_CSR_RFRST)) ? 1UL : 0UL);
1698 }
1699
1700 /**
1701 * @brief Check if RCC flag Radio in reset is set or not.
1702 * @rmtoll CSR RFRSTF LL_RCC_IsRFUnderReset
1703 * @retval State of bit (1 or 0).
1704 */
LL_RCC_IsRFUnderReset(void)1705 __STATIC_INLINE uint32_t LL_RCC_IsRFUnderReset(void)
1706 {
1707 return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL);
1708 }
1709
1710
1711 /**
1712 * @}
1713 */
1714
1715
1716 /** @defgroup RCC_LL_EF_System System
1717 * @{
1718 */
1719
1720 /**
1721 * @brief Configure the system clock source
1722 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1723 * @param Source This parameter can be one of the following values:
1724 * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
1725 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1726 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1727 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1728 * @retval None
1729 */
LL_RCC_SetSysClkSource(uint32_t Source)1730 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1731 {
1732 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1733 }
1734
1735 /**
1736 * @brief Get the system clock source
1737 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1738 * @retval Returned value can be one of the following values:
1739 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
1740 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1741 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1742 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1743 */
LL_RCC_GetSysClkSource(void)1744 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1745 {
1746 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1747 }
1748
1749
1750 /**
1751 * @brief Set AHB prescaler
1752 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1753 * @param Prescaler This parameter can be one of the following values:
1754 * @arg @ref LL_RCC_SYSCLK_DIV_1
1755 * @arg @ref LL_RCC_SYSCLK_DIV_2
1756 * @arg @ref LL_RCC_SYSCLK_DIV_3
1757 * @arg @ref LL_RCC_SYSCLK_DIV_4
1758 * @arg @ref LL_RCC_SYSCLK_DIV_5
1759 * @arg @ref LL_RCC_SYSCLK_DIV_6
1760 * @arg @ref LL_RCC_SYSCLK_DIV_8
1761 * @arg @ref LL_RCC_SYSCLK_DIV_10
1762 * @arg @ref LL_RCC_SYSCLK_DIV_16
1763 * @arg @ref LL_RCC_SYSCLK_DIV_32
1764 * @arg @ref LL_RCC_SYSCLK_DIV_64
1765 * @arg @ref LL_RCC_SYSCLK_DIV_128
1766 * @arg @ref LL_RCC_SYSCLK_DIV_256
1767 * @arg @ref LL_RCC_SYSCLK_DIV_512
1768 * @retval None
1769 */
LL_RCC_SetAHBPrescaler(uint32_t Prescaler)1770 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1771 {
1772 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1773 }
1774
1775 #if defined(DUAL_CORE)
1776 /**
1777 * @brief Set CPU2 AHB prescaler
1778 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_SetAHBPrescaler
1779 * @param Prescaler This parameter can be one of the following values:
1780 * @arg @ref LL_RCC_SYSCLK_DIV_1
1781 * @arg @ref LL_RCC_SYSCLK_DIV_2
1782 * @arg @ref LL_RCC_SYSCLK_DIV_3
1783 * @arg @ref LL_RCC_SYSCLK_DIV_4
1784 * @arg @ref LL_RCC_SYSCLK_DIV_5
1785 * @arg @ref LL_RCC_SYSCLK_DIV_6
1786 * @arg @ref LL_RCC_SYSCLK_DIV_8
1787 * @arg @ref LL_RCC_SYSCLK_DIV_10
1788 * @arg @ref LL_RCC_SYSCLK_DIV_16
1789 * @arg @ref LL_RCC_SYSCLK_DIV_32
1790 * @arg @ref LL_RCC_SYSCLK_DIV_64
1791 * @arg @ref LL_RCC_SYSCLK_DIV_128
1792 * @arg @ref LL_RCC_SYSCLK_DIV_256
1793 * @arg @ref LL_RCC_SYSCLK_DIV_512
1794 * @retval None
1795 */
LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)1796 __STATIC_INLINE void LL_C2_RCC_SetAHBPrescaler(uint32_t Prescaler)
1797 {
1798 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE, Prescaler);
1799 }
1800 #endif /* DUAL_CORE */
1801
1802 /**
1803 * @brief Set AHB3 prescaler
1804 * @rmtoll EXTCFGR SHDHPRE LL_RCC_SetAHB3Prescaler
1805 * @param Prescaler This parameter can be one of the following values:
1806 * @arg @ref LL_RCC_SYSCLK_DIV_1
1807 * @arg @ref LL_RCC_SYSCLK_DIV_2
1808 * @arg @ref LL_RCC_SYSCLK_DIV_3
1809 * @arg @ref LL_RCC_SYSCLK_DIV_4
1810 * @arg @ref LL_RCC_SYSCLK_DIV_5
1811 * @arg @ref LL_RCC_SYSCLK_DIV_6
1812 * @arg @ref LL_RCC_SYSCLK_DIV_8
1813 * @arg @ref LL_RCC_SYSCLK_DIV_10
1814 * @arg @ref LL_RCC_SYSCLK_DIV_16
1815 * @arg @ref LL_RCC_SYSCLK_DIV_32
1816 * @arg @ref LL_RCC_SYSCLK_DIV_64
1817 * @arg @ref LL_RCC_SYSCLK_DIV_128
1818 * @arg @ref LL_RCC_SYSCLK_DIV_256
1819 * @arg @ref LL_RCC_SYSCLK_DIV_512
1820 * @retval None
1821 */
LL_RCC_SetAHB3Prescaler(uint32_t Prescaler)1822 __STATIC_INLINE void LL_RCC_SetAHB3Prescaler(uint32_t Prescaler)
1823 {
1824 MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4);
1825 }
1826
1827 /**
1828 * @brief Set APB1 prescaler
1829 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1830 * @param Prescaler This parameter can be one of the following values:
1831 * @arg @ref LL_RCC_APB1_DIV_1
1832 * @arg @ref LL_RCC_APB1_DIV_2
1833 * @arg @ref LL_RCC_APB1_DIV_4
1834 * @arg @ref LL_RCC_APB1_DIV_8
1835 * @arg @ref LL_RCC_APB1_DIV_16
1836 * @retval None
1837 */
LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)1838 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1839 {
1840 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1841 }
1842
1843 /**
1844 * @brief Set APB2 prescaler
1845 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1846 * @param Prescaler This parameter can be one of the following values:
1847 * @arg @ref LL_RCC_APB2_DIV_1
1848 * @arg @ref LL_RCC_APB2_DIV_2
1849 * @arg @ref LL_RCC_APB2_DIV_4
1850 * @arg @ref LL_RCC_APB2_DIV_8
1851 * @arg @ref LL_RCC_APB2_DIV_16
1852 * @retval None
1853 */
LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)1854 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1855 {
1856 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1857 }
1858
1859 /**
1860 * @brief Get AHB prescaler
1861 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1862 * @retval Returned value can be one of the following values:
1863 * @arg @ref LL_RCC_SYSCLK_DIV_1
1864 * @arg @ref LL_RCC_SYSCLK_DIV_2
1865 * @arg @ref LL_RCC_SYSCLK_DIV_3
1866 * @arg @ref LL_RCC_SYSCLK_DIV_4
1867 * @arg @ref LL_RCC_SYSCLK_DIV_5
1868 * @arg @ref LL_RCC_SYSCLK_DIV_6
1869 * @arg @ref LL_RCC_SYSCLK_DIV_8
1870 * @arg @ref LL_RCC_SYSCLK_DIV_10
1871 * @arg @ref LL_RCC_SYSCLK_DIV_16
1872 * @arg @ref LL_RCC_SYSCLK_DIV_32
1873 * @arg @ref LL_RCC_SYSCLK_DIV_64
1874 * @arg @ref LL_RCC_SYSCLK_DIV_128
1875 * @arg @ref LL_RCC_SYSCLK_DIV_256
1876 * @arg @ref LL_RCC_SYSCLK_DIV_512
1877 */
LL_RCC_GetAHBPrescaler(void)1878 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1879 {
1880 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1881 }
1882
1883 #if defined(DUAL_CORE)
1884 /**
1885 * @brief Get C2 AHB prescaler
1886 * @rmtoll EXTCFGR C2HPRE LL_C2_RCC_GetAHBPrescaler
1887 * @retval Returned value can be one of the following values:
1888 * @arg @ref LL_RCC_SYSCLK_DIV_1
1889 * @arg @ref LL_RCC_SYSCLK_DIV_2
1890 * @arg @ref LL_RCC_SYSCLK_DIV_3
1891 * @arg @ref LL_RCC_SYSCLK_DIV_4
1892 * @arg @ref LL_RCC_SYSCLK_DIV_5
1893 * @arg @ref LL_RCC_SYSCLK_DIV_6
1894 * @arg @ref LL_RCC_SYSCLK_DIV_8
1895 * @arg @ref LL_RCC_SYSCLK_DIV_10
1896 * @arg @ref LL_RCC_SYSCLK_DIV_16
1897 * @arg @ref LL_RCC_SYSCLK_DIV_32
1898 * @arg @ref LL_RCC_SYSCLK_DIV_64
1899 * @arg @ref LL_RCC_SYSCLK_DIV_128
1900 * @arg @ref LL_RCC_SYSCLK_DIV_256
1901 * @arg @ref LL_RCC_SYSCLK_DIV_512
1902 */
LL_C2_RCC_GetAHBPrescaler(void)1903 __STATIC_INLINE uint32_t LL_C2_RCC_GetAHBPrescaler(void)
1904 {
1905 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPRE));
1906 }
1907 #endif /* DUAL_CORE */
1908
1909 /**
1910 * @brief Get AHB3 prescaler
1911 * @rmtoll EXTCFGR SHDHPRE LL_RCC_GetAHB3Prescaler
1912 * @retval Returned value can be one of the following values:
1913 * @arg @ref LL_RCC_SYSCLK_DIV_1
1914 * @arg @ref LL_RCC_SYSCLK_DIV_2
1915 * @arg @ref LL_RCC_SYSCLK_DIV_3
1916 * @arg @ref LL_RCC_SYSCLK_DIV_4
1917 * @arg @ref LL_RCC_SYSCLK_DIV_5
1918 * @arg @ref LL_RCC_SYSCLK_DIV_6
1919 * @arg @ref LL_RCC_SYSCLK_DIV_8
1920 * @arg @ref LL_RCC_SYSCLK_DIV_10
1921 * @arg @ref LL_RCC_SYSCLK_DIV_16
1922 * @arg @ref LL_RCC_SYSCLK_DIV_32
1923 * @arg @ref LL_RCC_SYSCLK_DIV_64
1924 * @arg @ref LL_RCC_SYSCLK_DIV_128
1925 * @arg @ref LL_RCC_SYSCLK_DIV_256
1926 * @arg @ref LL_RCC_SYSCLK_DIV_512
1927 */
LL_RCC_GetAHB3Prescaler(void)1928 __STATIC_INLINE uint32_t LL_RCC_GetAHB3Prescaler(void)
1929 {
1930 return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4);
1931 }
1932
1933 /**
1934 * @brief Get APB1 prescaler
1935 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1936 * @retval Returned value can be one of the following values:
1937 * @arg @ref LL_RCC_APB1_DIV_1
1938 * @arg @ref LL_RCC_APB1_DIV_2
1939 * @arg @ref LL_RCC_APB1_DIV_4
1940 * @arg @ref LL_RCC_APB1_DIV_8
1941 * @arg @ref LL_RCC_APB1_DIV_16
1942 */
LL_RCC_GetAPB1Prescaler(void)1943 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1944 {
1945 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1946 }
1947
1948 /**
1949 * @brief Get APB2 prescaler
1950 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1951 * @retval Returned value can be one of the following values:
1952 * @arg @ref LL_RCC_APB2_DIV_1
1953 * @arg @ref LL_RCC_APB2_DIV_2
1954 * @arg @ref LL_RCC_APB2_DIV_4
1955 * @arg @ref LL_RCC_APB2_DIV_8
1956 * @arg @ref LL_RCC_APB2_DIV_16
1957 */
LL_RCC_GetAPB2Prescaler(void)1958 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1959 {
1960 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1961 }
1962
1963 /**
1964 * @brief Set Clock After Wake-Up From Stop mode
1965 * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
1966 * @param Clock This parameter can be one of the following values:
1967 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1968 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1969 * @retval None
1970 */
LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)1971 __STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
1972 {
1973 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
1974 }
1975
1976 /**
1977 * @brief Get Clock After Wake-Up From Stop mode
1978 * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
1979 * @retval Returned value can be one of the following values:
1980 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
1981 * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
1982 */
LL_RCC_GetClkAfterWakeFromStop(void)1983 __STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
1984 {
1985 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
1986 }
1987
1988 /**
1989 * @}
1990 */
1991
1992
1993 /** @defgroup RCC_LL_EF_MCO MCO
1994 * @{
1995 */
1996
1997 /**
1998 * @brief Configure MCOx
1999 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
2000 * CFGR MCOPRE LL_RCC_ConfigMCO
2001 * @param MCOxSource This parameter can be one of the following values:
2002 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
2003 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
2004 * @arg @ref LL_RCC_MCO1SOURCE_MSI
2005 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2006 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2007 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2008 * @arg @ref LL_RCC_MCO1SOURCE_LSI
2009 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2010 * @arg @ref LL_RCC_MCO1SOURCE_PLLQCLK
2011 * @arg @ref LL_RCC_MCO1SOURCE_PLLPCLK
2012 * @param MCOxPrescaler This parameter can be one of the following values:
2013 * @arg @ref LL_RCC_MCO1_DIV_1
2014 * @arg @ref LL_RCC_MCO1_DIV_2
2015 * @arg @ref LL_RCC_MCO1_DIV_4
2016 * @arg @ref LL_RCC_MCO1_DIV_8
2017 * @arg @ref LL_RCC_MCO1_DIV_16
2018 * @retval None
2019 */
LL_RCC_ConfigMCO(uint32_t MCOxSource,uint32_t MCOxPrescaler)2020 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2021 {
2022 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
2023 }
2024
2025 /**
2026 * @}
2027 */
2028
2029 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2030 * @{
2031 */
2032
2033 /**
2034 * @brief Configure USARTx clock source
2035 * @rmtoll CCIPR USART1SEL LL_RCC_SetUSARTClockSource
2036 * @param USARTxSource This parameter can be one of the following values:
2037 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2038 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2039 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2040 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2041 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2042 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2043 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2044 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2045 * @retval None
2046 */
LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)2047 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2048 {
2049 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU));
2050 }
2051
2052 /**
2053 * @brief Configure I2Sx clock source
2054 * @rmtoll CCIPR I2S2SEL LL_RCC_SetI2SClockSource
2055 * @param I2SxSource This parameter can be one of the following values:
2056 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2057 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2058 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2059 * @retval None
2060 */
LL_RCC_SetI2SClockSource(uint32_t I2SxSource)2061 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
2062 {
2063 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource);
2064 }
2065
2066 /**
2067 * @brief Configure LPUARTx clock source
2068 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2069 * @param LPUARTxSource This parameter can be one of the following values:
2070 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2071 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2072 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2073 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2074 * @retval None
2075 */
LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)2076 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
2077 {
2078 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
2079 }
2080
2081 /**
2082 * @brief Configure I2Cx clock source
2083 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
2084 * @param I2CxSource This parameter can be one of the following values:
2085 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2086 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2087 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2088 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2089 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2090 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2091 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2092 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2093 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2094 * @retval None
2095 */
LL_RCC_SetI2CClockSource(uint32_t I2CxSource)2096 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2097 {
2098 MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U));
2099 }
2100
2101 /**
2102 * @brief Configure LPTIMx clock source
2103 * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
2104 * @param LPTIMxSource This parameter can be one of the following values:
2105 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2106 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2107 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2108 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2109 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2110 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2111 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2112 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2113 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1
2114 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
2115 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI
2116 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
2117 * @retval None
2118 */
LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)2119 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2120 {
2121 MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16));
2122 }
2123
2124 /**
2125 * @brief Configure RNG clock source
2126 * @rmtoll CCIPR RNGSEL LL_RCC_SetRNGClockSource
2127 * @param RNGxSource This parameter can be one of the following values:
2128 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2129 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2130 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2131 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
2132 * @retval None
2133 */
LL_RCC_SetRNGClockSource(uint32_t RNGxSource)2134 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2135 {
2136 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource);
2137 }
2138
2139
2140 /**
2141 * @brief Configure ADC clock source
2142 * @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
2143 * @param ADCxSource This parameter can be one of the following values:
2144 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2145 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2146 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2147 * @retval None
2148 */
LL_RCC_SetADCClockSource(uint32_t ADCxSource)2149 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
2150 {
2151 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
2152 }
2153
2154 /**
2155 * @brief Get USARTx clock source
2156 * @rmtoll CCIPR USART1SEL LL_RCC_GetUSARTClockSource
2157 * @param USARTx This parameter can be one of the following values:
2158 * @arg @ref LL_RCC_USART1_CLKSOURCE
2159 * @retval Returned value can be one of the following values:
2160 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2161 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2162 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2163 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2164 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2165 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2166 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2167 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2168 */
LL_RCC_GetUSARTClockSource(uint32_t USARTx)2169 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2170 {
2171 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16));
2172 }
2173
2174 /**
2175 * @brief Get I2Sx clock source
2176 * @rmtoll CCIPR I2S2SEL LL_RCC_GetI2SClockSource
2177 * @param I2Sx This parameter can be one of the following values:
2178 * @arg @ref LL_RCC_I2S2_CLKSOURCE
2179 * @retval Returned value can be one of the following values:
2180 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL
2181 * @arg @ref LL_RCC_I2S2_CLKSOURCE_HSI
2182 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN
2183 */
LL_RCC_GetI2SClockSource(uint32_t I2Sx)2184 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2185 {
2186 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
2187 }
2188
2189 /**
2190 * @brief Get LPUARTx clock source
2191 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
2192 * @param LPUARTx This parameter can be one of the following values:
2193 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
2194 * @retval Returned value can be one of the following values:
2195 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
2196 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
2197 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2198 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2199 */
LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)2200 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
2201 {
2202 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
2203 }
2204
2205 /**
2206 * @brief Get I2Cx clock source
2207 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
2208 * @param I2Cx This parameter can be one of the following values:
2209 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2210 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2211 * @retval Returned value can be one of the following values:
2212 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2213 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2214 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2215 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2216 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2217 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2218 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2219 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2220 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2221 */
LL_RCC_GetI2CClockSource(uint32_t I2Cx)2222 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2223 {
2224 return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) | (I2Cx << 4));
2225 }
2226
2227 /**
2228 * @brief Get LPTIMx clock source
2229 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
2230 * @param LPTIMx This parameter can be one of the following values:
2231 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2232 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
2233 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
2234 * @retval Returned value can be one of the following values:
2235 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2236 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2237 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2238 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2239 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
2240 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2241 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
2242 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2243 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_PCLK1
2244 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSI
2245 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_HSI
2246 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE_LSE
2247
2248 */
LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)2249 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2250 {
2251 return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16) | LPTIMx);
2252 }
2253
2254 /**
2255 * @brief Get RNGx clock source
2256 * @rmtoll CCIPR RNGSEL LL_RCC_GetRNGClockSource
2257 * @param RNGx This parameter can be one of the following values:
2258 * @arg @ref LL_RCC_RNG_CLKSOURCE
2259 * @retval Returned value can be one of the following values:
2260 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2261 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
2262 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
2263 * @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
2264 */
LL_RCC_GetRNGClockSource(uint32_t RNGx)2265 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2266 {
2267 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
2268 }
2269
2270 /**
2271 * @brief Get ADCx clock source
2272 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
2273 * @param ADCx This parameter can be one of the following values:
2274 * @arg @ref LL_RCC_ADC_CLKSOURCE
2275 * @retval Returned value can be one of the following values:
2276 * @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
2277 * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI
2278 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL
2279 * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
2280 */
LL_RCC_GetADCClockSource(uint32_t ADCx)2281 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2282 {
2283 return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
2284 }
2285
2286 /**
2287 * @}
2288 */
2289
2290 /** @defgroup RCC_LL_EF_RTC RTC
2291 * @{
2292 */
2293
2294 /**
2295 * @brief Set RTC Clock Source
2296 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2297 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2298 * set). The BDRST bit can be used to reset them.
2299 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2300 * @param Source This parameter can be one of the following values:
2301 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2302 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2303 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2304 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2305 * @retval None
2306 */
LL_RCC_SetRTCClockSource(uint32_t Source)2307 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2308 {
2309 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2310 }
2311
2312 /**
2313 * @brief Get RTC Clock Source
2314 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2315 * @retval Returned value can be one of the following values:
2316 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2317 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2318 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2319 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2320 */
LL_RCC_GetRTCClockSource(void)2321 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2322 {
2323 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2324 }
2325
2326 /**
2327 * @brief Enable RTC
2328 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2329 * @retval None
2330 */
LL_RCC_EnableRTC(void)2331 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2332 {
2333 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2334 }
2335
2336 /**
2337 * @brief Disable RTC
2338 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2339 * @retval None
2340 */
LL_RCC_DisableRTC(void)2341 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2342 {
2343 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2344 }
2345
2346 /**
2347 * @brief Check if RTC has been enabled or not
2348 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2349 * @retval State of bit (1 or 0).
2350 */
LL_RCC_IsEnabledRTC(void)2351 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2352 {
2353 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2354 }
2355
2356 /**
2357 * @brief Force the Backup domain reset
2358 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2359 * @retval None
2360 */
LL_RCC_ForceBackupDomainReset(void)2361 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2362 {
2363 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2364 }
2365
2366 /**
2367 * @brief Release the Backup domain reset
2368 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2369 * @retval None
2370 */
LL_RCC_ReleaseBackupDomainReset(void)2371 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2372 {
2373 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2374 }
2375
2376 /**
2377 * @}
2378 */
2379
2380
2381 /** @defgroup RCC_LL_EF_PLL PLL
2382 * @{
2383 */
2384
2385 /**
2386 * @brief Enable PLL
2387 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2388 * @retval None
2389 */
LL_RCC_PLL_Enable(void)2390 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2391 {
2392 SET_BIT(RCC->CR, RCC_CR_PLLON);
2393 }
2394
2395 /**
2396 * @brief Disable PLL
2397 * @note Cannot be disabled if the PLL clock is used as the system clock
2398 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2399 * @retval None
2400 */
LL_RCC_PLL_Disable(void)2401 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2402 {
2403 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2404 }
2405
2406 /**
2407 * @brief Check if PLL Ready
2408 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2409 * @retval State of bit (1 or 0).
2410 */
LL_RCC_PLL_IsReady(void)2411 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2412 {
2413 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2414 }
2415
2416 /**
2417 * @brief Configure PLL used for SYSCLK Domain
2418 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2419 * @note PLLN/PLLR can be written only when PLL is disabled
2420 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2421 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2422 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2423 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2424 * @param Source This parameter can be one of the following values:
2425 * @arg @ref LL_RCC_PLLSOURCE_NONE
2426 * @arg @ref LL_RCC_PLLSOURCE_MSI
2427 * @arg @ref LL_RCC_PLLSOURCE_HSI
2428 * @arg @ref LL_RCC_PLLSOURCE_HSE
2429 * @param PLLM This parameter can be one of the following values:
2430 * @arg @ref LL_RCC_PLLM_DIV_1
2431 * @arg @ref LL_RCC_PLLM_DIV_2
2432 * @arg @ref LL_RCC_PLLM_DIV_3
2433 * @arg @ref LL_RCC_PLLM_DIV_4
2434 * @arg @ref LL_RCC_PLLM_DIV_5
2435 * @arg @ref LL_RCC_PLLM_DIV_6
2436 * @arg @ref LL_RCC_PLLM_DIV_7
2437 * @arg @ref LL_RCC_PLLM_DIV_8
2438 * @param PLLN Between 6 and 127
2439 * @param PLLR This parameter can be one of the following values:
2440 * @arg @ref LL_RCC_PLLR_DIV_2
2441 * @arg @ref LL_RCC_PLLR_DIV_3
2442 * @arg @ref LL_RCC_PLLR_DIV_4
2443 * @arg @ref LL_RCC_PLLR_DIV_5
2444 * @arg @ref LL_RCC_PLLR_DIV_6
2445 * @arg @ref LL_RCC_PLLR_DIV_7
2446 * @arg @ref LL_RCC_PLLR_DIV_8
2447 * @retval None
2448 */
LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLR)2449 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2450 {
2451 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2452 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2453 }
2454
2455 /**
2456 * @brief Configure PLL used for ADC domain clock
2457 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2458 * @note PLLN/PLLP can be written only when PLL is disabled
2459 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2460 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2461 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2462 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_ADC
2463 * @param Source This parameter can be one of the following values:
2464 * @arg @ref LL_RCC_PLLSOURCE_NONE
2465 * @arg @ref LL_RCC_PLLSOURCE_MSI
2466 * @arg @ref LL_RCC_PLLSOURCE_HSI
2467 * @arg @ref LL_RCC_PLLSOURCE_HSE
2468 * @param PLLM This parameter can be one of the following values:
2469 * @arg @ref LL_RCC_PLLM_DIV_1
2470 * @arg @ref LL_RCC_PLLM_DIV_2
2471 * @arg @ref LL_RCC_PLLM_DIV_3
2472 * @arg @ref LL_RCC_PLLM_DIV_4
2473 * @arg @ref LL_RCC_PLLM_DIV_5
2474 * @arg @ref LL_RCC_PLLM_DIV_6
2475 * @arg @ref LL_RCC_PLLM_DIV_7
2476 * @arg @ref LL_RCC_PLLM_DIV_8
2477 * @param PLLN Between 6 and 127
2478 * @param PLLP This parameter can be one of the following values:
2479 * @arg @ref LL_RCC_PLLP_DIV_2
2480 * @arg @ref LL_RCC_PLLP_DIV_3
2481 * @arg @ref LL_RCC_PLLP_DIV_4
2482 * @arg @ref LL_RCC_PLLP_DIV_5
2483 * @arg @ref LL_RCC_PLLP_DIV_6
2484 * @arg @ref LL_RCC_PLLP_DIV_7
2485 * @arg @ref LL_RCC_PLLP_DIV_8
2486 * @arg @ref LL_RCC_PLLP_DIV_9
2487 * @arg @ref LL_RCC_PLLP_DIV_10
2488 * @arg @ref LL_RCC_PLLP_DIV_11
2489 * @arg @ref LL_RCC_PLLP_DIV_12
2490 * @arg @ref LL_RCC_PLLP_DIV_13
2491 * @arg @ref LL_RCC_PLLP_DIV_14
2492 * @arg @ref LL_RCC_PLLP_DIV_15
2493 * @arg @ref LL_RCC_PLLP_DIV_16
2494 * @arg @ref LL_RCC_PLLP_DIV_17
2495 * @arg @ref LL_RCC_PLLP_DIV_18
2496 * @arg @ref LL_RCC_PLLP_DIV_19
2497 * @arg @ref LL_RCC_PLLP_DIV_20
2498 * @arg @ref LL_RCC_PLLP_DIV_21
2499 * @arg @ref LL_RCC_PLLP_DIV_22
2500 * @arg @ref LL_RCC_PLLP_DIV_23
2501 * @arg @ref LL_RCC_PLLP_DIV_24
2502 * @arg @ref LL_RCC_PLLP_DIV_25
2503 * @arg @ref LL_RCC_PLLP_DIV_26
2504 * @arg @ref LL_RCC_PLLP_DIV_27
2505 * @arg @ref LL_RCC_PLLP_DIV_28
2506 * @arg @ref LL_RCC_PLLP_DIV_29
2507 * @arg @ref LL_RCC_PLLP_DIV_30
2508 * @arg @ref LL_RCC_PLLP_DIV_31
2509 * @arg @ref LL_RCC_PLLP_DIV_32
2510 * @retval None
2511 */
LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLP)2512 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2513 {
2514 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
2515 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2516 }
2517
2518 /**
2519 * @brief Configure PLL used for RNG domain clock
2520 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2521 * @note PLLN/PLLQ can be written only when PLL is disabled
2522 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_RNG\n
2523 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_RNG\n
2524 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_RNG\n
2525 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_RNG
2526 * @param Source This parameter can be one of the following values:
2527 * @arg @ref LL_RCC_PLLSOURCE_NONE
2528 * @arg @ref LL_RCC_PLLSOURCE_MSI
2529 * @arg @ref LL_RCC_PLLSOURCE_HSI
2530 * @arg @ref LL_RCC_PLLSOURCE_HSE
2531 * @param PLLM This parameter can be one of the following values:
2532 * @arg @ref LL_RCC_PLLM_DIV_1
2533 * @arg @ref LL_RCC_PLLM_DIV_2
2534 * @arg @ref LL_RCC_PLLM_DIV_3
2535 * @arg @ref LL_RCC_PLLM_DIV_4
2536 * @arg @ref LL_RCC_PLLM_DIV_5
2537 * @arg @ref LL_RCC_PLLM_DIV_6
2538 * @arg @ref LL_RCC_PLLM_DIV_7
2539 * @arg @ref LL_RCC_PLLM_DIV_8
2540 * @param PLLN Between 6 and 127
2541 * @param PLLQ This parameter can be one of the following values:
2542 * @arg @ref LL_RCC_PLLQ_DIV_2
2543 * @arg @ref LL_RCC_PLLQ_DIV_3
2544 * @arg @ref LL_RCC_PLLQ_DIV_4
2545 * @arg @ref LL_RCC_PLLQ_DIV_5
2546 * @arg @ref LL_RCC_PLLQ_DIV_6
2547 * @arg @ref LL_RCC_PLLQ_DIV_7
2548 * @arg @ref LL_RCC_PLLQ_DIV_8
2549 * @retval None
2550 */
LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2551 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_RNG(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2552 {
2553 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2554 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2555 }
2556
2557 /**
2558 * @brief Configure PLL used for I2S domain clock
2559 * @note PLL Source and PLLM Divider can be written only when PLL is disabled
2560 * @note PLLN/PLLQ can be written only when PLL is disabled
2561 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
2562 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
2563 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
2564 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_I2S
2565 * @param Source This parameter can be one of the following values:
2566 * @arg @ref LL_RCC_PLLSOURCE_NONE
2567 * @arg @ref LL_RCC_PLLSOURCE_MSI
2568 * @arg @ref LL_RCC_PLLSOURCE_HSI
2569 * @arg @ref LL_RCC_PLLSOURCE_HSE
2570 * @param PLLM This parameter can be one of the following values:
2571 * @arg @ref LL_RCC_PLLM_DIV_1
2572 * @arg @ref LL_RCC_PLLM_DIV_2
2573 * @arg @ref LL_RCC_PLLM_DIV_3
2574 * @arg @ref LL_RCC_PLLM_DIV_4
2575 * @arg @ref LL_RCC_PLLM_DIV_5
2576 * @arg @ref LL_RCC_PLLM_DIV_6
2577 * @arg @ref LL_RCC_PLLM_DIV_7
2578 * @arg @ref LL_RCC_PLLM_DIV_8
2579 * @param PLLN Between 6 and 127
2580 * @param PLLQ This parameter can be one of the following values:
2581 * @arg @ref LL_RCC_PLLQ_DIV_2
2582 * @arg @ref LL_RCC_PLLQ_DIV_3
2583 * @arg @ref LL_RCC_PLLQ_DIV_4
2584 * @arg @ref LL_RCC_PLLQ_DIV_5
2585 * @arg @ref LL_RCC_PLLQ_DIV_6
2586 * @arg @ref LL_RCC_PLLQ_DIV_7
2587 * @arg @ref LL_RCC_PLLQ_DIV_8
2588 * @retval None
2589 */
LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source,uint32_t PLLM,uint32_t PLLN,uint32_t PLLQ)2590 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2591 {
2592 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2593 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2594 }
2595
2596 /**
2597 * @brief Get Main PLL multiplication factor for VCO
2598 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2599 * @retval Between 6 and 127
2600 */
LL_RCC_PLL_GetN(void)2601 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2602 {
2603 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2604 }
2605
2606 /**
2607 * @brief Get Main PLL division factor for PLLP
2608 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
2609 * @retval Returned value can be one of the following values:
2610 * @arg @ref LL_RCC_PLLP_DIV_2
2611 * @arg @ref LL_RCC_PLLP_DIV_3
2612 * @arg @ref LL_RCC_PLLP_DIV_4
2613 * @arg @ref LL_RCC_PLLP_DIV_5
2614 * @arg @ref LL_RCC_PLLP_DIV_6
2615 * @arg @ref LL_RCC_PLLP_DIV_7
2616 * @arg @ref LL_RCC_PLLP_DIV_8
2617 * @arg @ref LL_RCC_PLLP_DIV_9
2618 * @arg @ref LL_RCC_PLLP_DIV_10
2619 * @arg @ref LL_RCC_PLLP_DIV_11
2620 * @arg @ref LL_RCC_PLLP_DIV_12
2621 * @arg @ref LL_RCC_PLLP_DIV_13
2622 * @arg @ref LL_RCC_PLLP_DIV_14
2623 * @arg @ref LL_RCC_PLLP_DIV_15
2624 * @arg @ref LL_RCC_PLLP_DIV_16
2625 * @arg @ref LL_RCC_PLLP_DIV_17
2626 * @arg @ref LL_RCC_PLLP_DIV_18
2627 * @arg @ref LL_RCC_PLLP_DIV_19
2628 * @arg @ref LL_RCC_PLLP_DIV_20
2629 * @arg @ref LL_RCC_PLLP_DIV_21
2630 * @arg @ref LL_RCC_PLLP_DIV_22
2631 * @arg @ref LL_RCC_PLLP_DIV_23
2632 * @arg @ref LL_RCC_PLLP_DIV_24
2633 * @arg @ref LL_RCC_PLLP_DIV_25
2634 * @arg @ref LL_RCC_PLLP_DIV_26
2635 * @arg @ref LL_RCC_PLLP_DIV_27
2636 * @arg @ref LL_RCC_PLLP_DIV_28
2637 * @arg @ref LL_RCC_PLLP_DIV_29
2638 * @arg @ref LL_RCC_PLLP_DIV_30
2639 * @arg @ref LL_RCC_PLLP_DIV_31
2640 * @arg @ref LL_RCC_PLLP_DIV_32
2641 */
LL_RCC_PLL_GetP(void)2642 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
2643 {
2644 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
2645 }
2646
2647 /**
2648 * @brief Get Main PLL division factor for PLLQ
2649 * @note used for PLL48MCLK selected for USB, RNG (48 MHz clock)
2650 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
2651 * @retval Returned value can be one of the following values:
2652 * @arg @ref LL_RCC_PLLQ_DIV_2
2653 * @arg @ref LL_RCC_PLLQ_DIV_3
2654 * @arg @ref LL_RCC_PLLQ_DIV_4
2655 * @arg @ref LL_RCC_PLLQ_DIV_5
2656 * @arg @ref LL_RCC_PLLQ_DIV_6
2657 * @arg @ref LL_RCC_PLLQ_DIV_7
2658 * @arg @ref LL_RCC_PLLQ_DIV_8
2659 */
LL_RCC_PLL_GetQ(void)2660 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
2661 {
2662 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
2663 }
2664
2665 /**
2666 * @brief Get Main PLL division factor for PLLR
2667 * @note used for PLLCLK (system clock)
2668 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
2669 * @retval Returned value can be one of the following values:
2670 * @arg @ref LL_RCC_PLLR_DIV_2
2671 * @arg @ref LL_RCC_PLLR_DIV_3
2672 * @arg @ref LL_RCC_PLLR_DIV_4
2673 * @arg @ref LL_RCC_PLLR_DIV_5
2674 * @arg @ref LL_RCC_PLLR_DIV_6
2675 * @arg @ref LL_RCC_PLLR_DIV_7
2676 * @arg @ref LL_RCC_PLLR_DIV_8
2677 */
LL_RCC_PLL_GetR(void)2678 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
2679 {
2680 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
2681 }
2682
2683 /**
2684 * @brief Get Division factor for the main PLL and other PLL
2685 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
2686 * @retval Returned value can be one of the following values:
2687 * @arg @ref LL_RCC_PLLM_DIV_1
2688 * @arg @ref LL_RCC_PLLM_DIV_2
2689 * @arg @ref LL_RCC_PLLM_DIV_3
2690 * @arg @ref LL_RCC_PLLM_DIV_4
2691 * @arg @ref LL_RCC_PLLM_DIV_5
2692 * @arg @ref LL_RCC_PLLM_DIV_6
2693 * @arg @ref LL_RCC_PLLM_DIV_7
2694 * @arg @ref LL_RCC_PLLM_DIV_8
2695 */
LL_RCC_PLL_GetDivider(void)2696 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
2697 {
2698 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
2699 }
2700
2701 /**
2702 * @brief Enable PLL output mapped on ADC domain clock
2703 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
2704 * @retval None
2705 */
LL_RCC_PLL_EnableDomain_ADC(void)2706 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
2707 {
2708 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2709 }
2710
2711 /**
2712 * @brief Disable PLL output mapped on ADC domain clock
2713 * @note In order to save power, when the PLLCLK of the PLL is
2714 * not used, should be 0
2715 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
2716 * @retval None
2717 */
LL_RCC_PLL_DisableDomain_ADC(void)2718 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
2719 {
2720 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2721 }
2722
2723 /**
2724 * @brief Check if PLL output mapped on ADC domain clock is enabled
2725 * @rmtoll PLLCFGR RCC_PLLCFGR_PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
2726 * @retval State of bit (1 or 0).
2727 */
LL_RCC_PLL_IsEnabledDomain_ADC(void)2728 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
2729 {
2730 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
2731 }
2732
2733 /**
2734 * @brief Enable PLL output mapped on RNG domain clock
2735 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_RNG
2736 * @retval None
2737 */
LL_RCC_PLL_EnableDomain_RNG(void)2738 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_RNG(void)
2739 {
2740 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2741 }
2742
2743 /**
2744 * @brief Disable PLL output mapped on RNG domain clock
2745 * @note In order to save power, when the PLLCLK of the PLL is
2746 * not used, should be 0
2747 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_RNG
2748 * @retval None
2749 */
LL_RCC_PLL_DisableDomain_RNG(void)2750 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_RNG(void)
2751 {
2752 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2753 }
2754
2755 /**
2756 * @brief Check if PLL output mapped on RNG domain clock is enabled
2757 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_RNG
2758 * @retval State of bit (1 or 0).
2759 */
LL_RCC_PLL_IsEnabledDomain_RNG(void)2760 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_RNG(void)
2761 {
2762 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
2763 }
2764
2765 /**
2766 * @brief Enable PLL output mapped on I2S domain clock
2767 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_I2S
2768 * @retval None
2769 */
LL_RCC_PLL_EnableDomain_I2S(void)2770 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_I2S(void)
2771 {
2772 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2773 }
2774
2775 /**
2776 * @brief Disable PLL output mapped on I2S domain clock
2777 * @note In order to save power, when the PLLCLK of the PLL is
2778 * not used, should be 0
2779 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_I2S
2780 * @retval None
2781 */
LL_RCC_PLL_DisableDomain_I2S(void)2782 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_I2S(void)
2783 {
2784 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2785 }
2786
2787 /**
2788 * @brief Check if PLL output mapped on I2S domain clock is enabled
2789 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_I2S
2790 * @retval State of bit (1 or 0).
2791 */
LL_RCC_PLL_IsEnabledDomain_I2S(void)2792 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_I2S(void)
2793 {
2794 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
2795 }
2796
2797 /**
2798 * @brief Enable PLL output mapped on SYSCLK domain
2799 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
2800 * @retval None
2801 */
LL_RCC_PLL_EnableDomain_SYS(void)2802 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
2803 {
2804 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2805 }
2806
2807 /**
2808 * @brief Disable PLL output mapped on SYSCLK domain
2809 * @note Cannot be disabled if the PLL clock is used as the system clock
2810 * @note In order to save power, when the PLLCLK of the PLL is
2811 * not used, Main PLL should be 0
2812 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
2813 * @retval None
2814 */
LL_RCC_PLL_DisableDomain_SYS(void)2815 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
2816 {
2817 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2818 }
2819
2820 /**
2821 * @brief Check if PLL output mapped on SYS domain clock is enabled
2822 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
2823 * @retval State of bit (1 or 0).
2824 */
LL_RCC_PLL_IsEnabledDomain_SYS(void)2825 __STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
2826 {
2827 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
2828 }
2829
2830 /**
2831 * @brief Configure PLL clock source
2832 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
2833 * @param PLLSource This parameter can be one of the following values:
2834 * @arg @ref LL_RCC_PLLSOURCE_MSI
2835 * @arg @ref LL_RCC_PLLSOURCE_HSI
2836 * @arg @ref LL_RCC_PLLSOURCE_HSE
2837 * @retval None
2838 */
LL_RCC_PLL_SetMainSource(uint32_t PLLSource)2839 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2840 {
2841 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
2842 }
2843
2844 /**
2845 * @brief Get the oscillator used as PLL clock source.
2846 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
2847 * @retval Returned value can be one of the following values:
2848 * @arg @ref LL_RCC_PLLSOURCE_NONE
2849 * @arg @ref LL_RCC_PLLSOURCE_MSI
2850 * @arg @ref LL_RCC_PLLSOURCE_HSI
2851 * @arg @ref LL_RCC_PLLSOURCE_HSE
2852 */
LL_RCC_PLL_GetMainSource(void)2853 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2854 {
2855 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
2856 }
2857
2858 /**
2859 * @}
2860 */
2861
2862
2863
2864 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2865 * @{
2866 */
2867
2868 /**
2869 * @brief Clear LSI ready interrupt flag
2870 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2871 * @retval None
2872 */
LL_RCC_ClearFlag_LSIRDY(void)2873 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2874 {
2875 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
2876 }
2877
2878 /**
2879 * @brief Clear LSE ready interrupt flag
2880 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2881 * @retval None
2882 */
LL_RCC_ClearFlag_LSERDY(void)2883 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2884 {
2885 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2886 }
2887
2888 /**
2889 * @brief Clear MSI ready interrupt flag
2890 * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
2891 * @retval None
2892 */
LL_RCC_ClearFlag_MSIRDY(void)2893 __STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
2894 {
2895 SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
2896 }
2897
2898 /**
2899 * @brief Clear HSI ready interrupt flag
2900 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2901 * @retval None
2902 */
LL_RCC_ClearFlag_HSIRDY(void)2903 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2904 {
2905 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2906 }
2907
2908 /**
2909 * @brief Clear HSE ready interrupt flag
2910 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2911 * @retval None
2912 */
LL_RCC_ClearFlag_HSERDY(void)2913 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2914 {
2915 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2916 }
2917
2918 /**
2919 * @brief Clear PLL ready interrupt flag
2920 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2921 * @retval None
2922 */
LL_RCC_ClearFlag_PLLRDY(void)2923 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2924 {
2925 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
2926 }
2927
2928 /**
2929 * @brief Clear Clock security system interrupt flag
2930 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2931 * @retval None
2932 */
LL_RCC_ClearFlag_HSECSS(void)2933 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2934 {
2935 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
2936 }
2937
2938 /**
2939 * @brief Clear LSE Clock security system interrupt flag
2940 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
2941 * @retval None
2942 */
LL_RCC_ClearFlag_LSECSS(void)2943 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
2944 {
2945 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
2946 }
2947
2948 /**
2949 * @brief Check if LSI ready interrupt occurred or not
2950 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2951 * @retval State of bit (1 or 0).
2952 */
LL_RCC_IsActiveFlag_LSIRDY(void)2953 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2954 {
2955 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
2956
2957 }
2958
2959 /**
2960 * @brief Check if LSE ready interrupt occurred or not
2961 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2962 * @retval State of bit (1 or 0).
2963 */
LL_RCC_IsActiveFlag_LSERDY(void)2964 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2965 {
2966 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
2967 }
2968
2969 /**
2970 * @brief Check if MSI ready interrupt occurred or not
2971 * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
2972 * @retval State of bit (1 or 0).
2973 */
LL_RCC_IsActiveFlag_MSIRDY(void)2974 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
2975 {
2976 return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF)) ? 1UL : 0UL);
2977 }
2978
2979 /**
2980 * @brief Check if HSI ready interrupt occurred or not
2981 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2982 * @retval State of bit (1 or 0).
2983 */
LL_RCC_IsActiveFlag_HSIRDY(void)2984 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2985 {
2986 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
2987 }
2988
2989 /**
2990 * @brief Check if HSE ready interrupt occurred or not
2991 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2992 * @retval State of bit (1 or 0).
2993 */
LL_RCC_IsActiveFlag_HSERDY(void)2994 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2995 {
2996 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
2997 }
2998
2999 /**
3000 * @brief Check if PLL ready interrupt occurred or not
3001 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
3002 * @retval State of bit (1 or 0).
3003 */
LL_RCC_IsActiveFlag_PLLRDY(void)3004 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
3005 {
3006 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
3007
3008 }
3009
3010 /**
3011 * @brief Check if Clock security system interrupt occurred or not
3012 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
3013 * @retval State of bit (1 or 0).
3014 */
LL_RCC_IsActiveFlag_HSECSS(void)3015 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
3016 {
3017 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
3018 }
3019
3020 /**
3021 * @brief Check if LSE Clock security system interrupt occurred or not
3022 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
3023 * @retval State of bit (1 or 0).
3024 */
LL_RCC_IsActiveFlag_LSECSS(void)3025 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
3026 {
3027 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
3028 }
3029
3030 /**
3031 * @brief Check if HCLK1 prescaler flag value has been applied or not
3032 * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE
3033 * @retval State of bit (1 or 0).
3034 */
LL_RCC_IsActiveFlag_HPRE(void)3035 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void)
3036 {
3037 return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL);
3038 }
3039
3040 #if defined(DUAL_CORE)
3041 /**
3042 * @brief Check if HCLK2 prescaler flag value has been applied or not
3043 * @rmtoll EXTCFGR C2HPREF LL_RCC_IsActiveFlag_C2HPRE
3044 * @retval State of bit (1 or 0).
3045 */
LL_RCC_IsActiveFlag_C2HPRE(void)3046 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_C2HPRE(void)
3047 {
3048 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_C2HPREF) == (RCC_EXTCFGR_C2HPREF)) ? 1UL : 0UL);
3049 }
3050 #endif /* DUAL_CORE */
3051
3052 /**
3053 * @brief Check if HCLK3 prescaler flag value has been applied or not
3054 * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE
3055 * @retval State of bit (1 or 0).
3056 */
LL_RCC_IsActiveFlag_SHDHPRE(void)3057 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void)
3058 {
3059 return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL);
3060 }
3061
3062
3063 /**
3064 * @brief Check if PLCK1 prescaler flag value has been applied or not
3065 * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1
3066 * @retval State of bit (1 or 0).
3067 */
LL_RCC_IsActiveFlag_PPRE1(void)3068 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void)
3069 {
3070 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL);
3071 }
3072
3073 /**
3074 * @brief Check if PLCK2 prescaler flag value has been applied or not
3075 * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2
3076 * @retval State of bit (1 or 0).
3077 */
LL_RCC_IsActiveFlag_PPRE2(void)3078 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void)
3079 {
3080 return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL);
3081 }
3082
3083 /**
3084 * @brief Check if RCC flag Independent Watchdog reset is set or not.
3085 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
3086 * @retval State of bit (1 or 0).
3087 */
LL_RCC_IsActiveFlag_IWDGRST(void)3088 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
3089 {
3090 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
3091 }
3092
3093 /**
3094 * @brief Check if RCC flag Radio illegal access is set or not.
3095 * @rmtoll CSR RFILARSTF LL_RCC_IsActiveFlag_RFILARST
3096 * @retval State of bit (1 or 0).
3097 */
LL_RCC_IsActiveFlag_RFILARST(void)3098 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_RFILARST(void)
3099 {
3100 return ((READ_BIT(RCC->CSR, RCC_CSR_RFILARSTF) == (RCC_CSR_RFILARSTF)) ? 1UL : 0UL);
3101 }
3102
3103 /**
3104 * @brief Check if RCC flag Low Power reset is set or not.
3105 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
3106 * @retval State of bit (1 or 0).
3107 */
LL_RCC_IsActiveFlag_LPWRRST(void)3108 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
3109 {
3110 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
3111 }
3112
3113 /**
3114 * @brief Check if RCC flag Option byte reset is set or not.
3115 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
3116 * @retval State of bit (1 or 0).
3117 */
LL_RCC_IsActiveFlag_OBLRST(void)3118 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
3119 {
3120 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
3121 }
3122
3123 /**
3124 * @brief Check if RCC flag Pin reset is set or not.
3125 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
3126 * @retval State of bit (1 or 0).
3127 */
LL_RCC_IsActiveFlag_PINRST(void)3128 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
3129 {
3130 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
3131 }
3132
3133 /**
3134 * @brief Check if RCC flag Software reset is set or not.
3135 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
3136 * @retval State of bit (1 or 0).
3137 */
LL_RCC_IsActiveFlag_SFTRST(void)3138 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
3139 {
3140 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
3141 }
3142
3143 /**
3144 * @brief Check if RCC flag Window Watchdog reset is set or not.
3145 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
3146 * @retval State of bit (1 or 0).
3147 */
LL_RCC_IsActiveFlag_WWDGRST(void)3148 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
3149 {
3150 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
3151 }
3152
3153 /**
3154 * @brief Check if RCC flag BOR reset is set or not.
3155 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
3156 * @retval State of bit (1 or 0).
3157 */
LL_RCC_IsActiveFlag_BORRST(void)3158 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
3159 {
3160 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
3161 }
3162
3163 /**
3164 * @brief Set RMVF bit to clear the reset flags.
3165 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
3166 * @retval None
3167 */
LL_RCC_ClearResetFlags(void)3168 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
3169 {
3170 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
3171 }
3172
3173 /**
3174 * @}
3175 */
3176
3177 /** @defgroup RCC_LL_EF_IT_Management IT Management
3178 * @{
3179 */
3180
3181 /**
3182 * @brief Enable LSI ready interrupt
3183 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
3184 * @retval None
3185 */
LL_RCC_EnableIT_LSIRDY(void)3186 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
3187 {
3188 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3189 }
3190
3191 /**
3192 * @brief Enable LSE ready interrupt
3193 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
3194 * @retval None
3195 */
LL_RCC_EnableIT_LSERDY(void)3196 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
3197 {
3198 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3199 }
3200
3201 /**
3202 * @brief Enable MSI ready interrupt
3203 * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
3204 * @retval None
3205 */
LL_RCC_EnableIT_MSIRDY(void)3206 __STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
3207 {
3208 SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
3209 }
3210
3211 /**
3212 * @brief Enable HSI ready interrupt
3213 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
3214 * @retval None
3215 */
LL_RCC_EnableIT_HSIRDY(void)3216 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
3217 {
3218 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3219 }
3220
3221 /**
3222 * @brief Enable HSE ready interrupt
3223 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
3224 * @retval None
3225 */
LL_RCC_EnableIT_HSERDY(void)3226 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
3227 {
3228 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3229 }
3230
3231 /**
3232 * @brief Enable PLL ready interrupt
3233 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
3234 * @retval None
3235 */
LL_RCC_EnableIT_PLLRDY(void)3236 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
3237 {
3238 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3239 }
3240
3241 /**
3242 * @brief Enable LSE clock security system interrupt
3243 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
3244 * @retval None
3245 */
LL_RCC_EnableIT_LSECSS(void)3246 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
3247 {
3248 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
3249 }
3250
3251 /**
3252 * @brief Disable LSI ready interrupt
3253 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
3254 * @retval None
3255 */
LL_RCC_DisableIT_LSIRDY(void)3256 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
3257 {
3258 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
3259 }
3260
3261 /**
3262 * @brief Disable LSE ready interrupt
3263 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
3264 * @retval None
3265 */
LL_RCC_DisableIT_LSERDY(void)3266 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
3267 {
3268 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
3269 }
3270
3271 /**
3272 * @brief Disable MSI ready interrupt
3273 * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
3274 * @retval None
3275 */
LL_RCC_DisableIT_MSIRDY(void)3276 __STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
3277 {
3278 CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
3279 }
3280
3281 /**
3282 * @brief Disable HSI ready interrupt
3283 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
3284 * @retval None
3285 */
LL_RCC_DisableIT_HSIRDY(void)3286 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
3287 {
3288 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
3289 }
3290
3291 /**
3292 * @brief Disable HSE ready interrupt
3293 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
3294 * @retval None
3295 */
LL_RCC_DisableIT_HSERDY(void)3296 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
3297 {
3298 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
3299 }
3300
3301 /**
3302 * @brief Disable PLL ready interrupt
3303 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
3304 * @retval None
3305 */
LL_RCC_DisableIT_PLLRDY(void)3306 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
3307 {
3308 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
3309 }
3310
3311 /**
3312 * @brief Disable LSE clock security system interrupt
3313 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
3314 * @retval None
3315 */
LL_RCC_DisableIT_LSECSS(void)3316 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
3317 {
3318 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
3319 }
3320
3321 /**
3322 * @brief Checks if LSI ready interrupt source is enabled or disabled.
3323 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
3324 * @retval State of bit (1 or 0).
3325 */
LL_RCC_IsEnabledIT_LSIRDY(void)3326 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
3327 {
3328 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
3329 }
3330
3331 /**
3332 * @brief Checks if LSE ready interrupt source is enabled or disabled.
3333 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
3334 * @retval State of bit (1 or 0).
3335 */
LL_RCC_IsEnabledIT_LSERDY(void)3336 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
3337 {
3338 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
3339 }
3340
3341 /**
3342 * @brief Checks if MSI ready interrupt source is enabled or disabled.
3343 * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
3344 * @retval State of bit (1 or 0).
3345 */
LL_RCC_IsEnabledIT_MSIRDY(void)3346 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
3347 {
3348 return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE)) ? 1UL : 0UL);
3349 }
3350
3351 /**
3352 * @brief Checks if HSI ready interrupt source is enabled or disabled.
3353 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
3354 * @retval State of bit (1 or 0).
3355 */
LL_RCC_IsEnabledIT_HSIRDY(void)3356 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
3357 {
3358 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
3359 }
3360
3361 /**
3362 * @brief Checks if HSE ready interrupt source is enabled or disabled.
3363 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
3364 * @retval State of bit (1 or 0).
3365 */
LL_RCC_IsEnabledIT_HSERDY(void)3366 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
3367 {
3368 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
3369 }
3370
3371 /**
3372 * @brief Checks if PLL ready interrupt source is enabled or disabled.
3373 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
3374 * @retval State of bit (1 or 0).
3375 */
LL_RCC_IsEnabledIT_PLLRDY(void)3376 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
3377 {
3378 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
3379
3380 }
3381
3382 /**
3383 * @brief Checks if LSECSS interrupt source is enabled or disabled.
3384 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
3385 * @retval State of bit (1 or 0).
3386 */
LL_RCC_IsEnabledIT_LSECSS(void)3387 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
3388 {
3389 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
3390 }
3391
3392 /**
3393 * @}
3394 */
3395
3396 #if defined(USE_FULL_LL_DRIVER)
3397 /** @defgroup RCC_LL_EF_Init De-initialization function
3398 * @{
3399 */
3400 ErrorStatus LL_RCC_DeInit(void);
3401 /**
3402 * @}
3403 */
3404
3405 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
3406 * @{
3407 */
3408 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
3409 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
3410 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
3411 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
3412 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
3413 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
3414 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
3415 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
3416 uint32_t LL_RCC_GetRTCClockFreq(void);
3417 /**
3418 * @}
3419 */
3420 #endif /* USE_FULL_LL_DRIVER */
3421
3422 /**
3423 * @}
3424 */
3425
3426 /**
3427 * @}
3428 */
3429
3430 #endif /* defined(RCC) */
3431
3432 /**
3433 * @}
3434 */
3435
3436 #ifdef __cplusplus
3437 }
3438 #endif
3439
3440 #endif /* __STM32WLxx_LL_RCC_H */
3441
