1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef __STM32WLxx_LL_PWR_H
21 #define __STM32WLxx_LL_PWR_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined(PWR)
35
36 /** @defgroup PWR_LL PWR
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
45 * @{
46 */
47 #define PWR_FLASH_POWER_MODE_UNLOCK_CODE (0x0000C1B0UL)
48 /**
49 * @}
50 */
51
52 /* Private macros ------------------------------------------------------------*/
53
54 /* Exported types ------------------------------------------------------------*/
55 /* Exported constants --------------------------------------------------------*/
56 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
57 * @{
58 */
59
60 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
61 * @brief Flags defines which can be used with LL_PWR_WriteReg function
62 * @{
63 */
64 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
65 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
66 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
67 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
68 #define LL_PWR_SCR_CWPVDF PWR_SCR_CWPVDF
69 #define LL_PWR_SCR_CWRFBUSYF PWR_SCR_CWRFBUSYF
70 #define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
71 #define LL_PWR_EXTSCR_C2CSSF PWR_EXTSCR_C2CSSF
72 #define LL_PWR_EXTSCR_C1CSSF PWR_EXTSCR_C1CSSF
73 /**
74 * @}
75 */
76
77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
78 * @brief Flags defines which can be used with LL_PWR_ReadReg function
79 * @{
80 */
81 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
82 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
83 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
84 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
85 #define LL_PWR_SR1_WPVDF PWR_SR1_WPVDF
86
87 #define LL_PWR_SR2_LDORDY PWR_SR2_LDORDY
88 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
89 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
90 #define LL_PWR_SR2_RFEOL PWR_SR2_RFEOLF
91 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
92 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
93 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
94 #define LL_PWR_SR2_REGMRS PWR_SR2_REGMRS
95
96 /* SMPS flags */
97 #define LL_PWR_SR2_SMPSRDY PWR_SR2_SMPSRDY
98
99 /* Radio flags */
100 #define LL_PWR_SR1_WRFBUSY PWR_SR1_WRFBUSYF /* Radio busy flag for wake-up and interruption (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) */
101 #define LL_PWR_SR2_RFBUSYS PWR_SR2_RFBUSYS /* Radio busy signal flag (current status) */
102 #define LL_PWR_SR2_RFBUSYMS PWR_SR2_RFBUSYMS /* Radio busy masked signal flag (current status) */
103
104 /* Multicore flags */
105 #define LL_PWR_EXTSCR_C1SBF PWR_EXTSCR_C1SBF /* System Standby flag for CPU1 */
106 #define LL_PWR_EXTSCR_C1STOP2F PWR_EXTSCR_C1STOP2F /* System Stop 2 flag for CPU1 */
107 #define LL_PWR_EXTSCR_C1STOPF PWR_EXTSCR_C1STOPF /* System Stop 0 or stop 1 flag for CPU1 */
108 #define LL_PWR_EXTSCR_C1DS PWR_EXTSCR_C1DS /* CPU1 deepsleep mode */
109 #if defined(DUAL_CORE)
110 #define LL_PWR_EXTSCR_C2SBF PWR_EXTSCR_C2SBF /* System Standby flag for CPU2 */
111 #define LL_PWR_EXTSCR_C2STOP2F PWR_EXTSCR_C2STOP2F /* System Stop 2 flag for CPU2 */
112 #define LL_PWR_EXTSCR_C2STOPF PWR_EXTSCR_C2STOPF /* System Stop 0 or stop 1 flag for CPU2 */
113 #define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */
114 #define LL_PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS /* CPU2 boot request source information flag */
115 #define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */
116 #endif
117 /**
118 * @}
119 */
120
121 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
122 * @{
123 */
124 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) /* Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz. */
125 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) /* Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz. */
126 /**
127 * @}
128 */
129
130 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
131 * @{
132 */
133 #define LL_PWR_MODE_STOP0 (0x000000000UL)
134 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
135 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
136 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
137 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
138 /**
139 * @}
140 */
141
142 /** @defgroup PWR_LL_EC_FLASH_LPRUN_POWER_DOWN_MODE Flash power-down mode during low-power run mode
143 * @{
144 */
145 #define LL_PWR_FLASH_LPRUN_MODE_IDLE (0x000000000UL)
146 #define LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN (PWR_CR1_FPDR)
147 /**
148 * @}
149 */
150
151 /** @defgroup PWR_LL_EC_FLASH_SLEEP_POWER_DOWN_MODE Flash power-down mode during sleep mode
152 * @{
153 */
154 #define LL_PWR_FLASH_SLEEP_MODE_IDLE (0x000000000UL)
155 #define LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN (PWR_CR1_FPDS)
156 /**
157 * @}
158 */
159
160 /** @defgroup PWR_LL_EC_PVM Peripheral voltage monitoring
161 * @{
162 */
163 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
164 /**
165 * @}
166 */
167
168 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
169 * @{
170 */
171 #define LL_PWR_PVDLEVEL_0 (0x00000000UL) /* VPVD0 around 2.0 V */
172 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_0) /* VPVD1 around 2.2 V */
173 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_1) /* VPVD2 around 2.4 V */
174 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* VPVD3 around 2.5 V */
175 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_2) /* VPVD4 around 2.6 V */
176 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /* VPVD5 around 2.8 V */
177 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1) /* VPVD6 around 2.9 V */
178 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /* External input analog voltage (Compare internally to VREFINT) */
179 /**
180 * @}
181 */
182
183 /** @defgroup PWR_LL_EC_EOL_OPERATING_MODES Monitoring of supply voltage for radio operating level (radio End Of Life)
184 * @{
185 */
186 #define LL_PWR_RADIO_EOL_DISABLE (0x00000000UL) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) disable */
187 #define LL_PWR_RADIO_EOL_ENABLE (PWR_CR5_RFEOLEN) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) enable */
188 /**
189 * @}
190 */
191
192 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
193 * @{
194 */
195 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
196 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
197 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
198 /**
199 * @}
200 */
201
202 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
203 * @{
204 */
205 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000UL)
206 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
207 /**
208 * @}
209 */
210
211 /** @defgroup PWR_LL_EC_GPIO GPIO
212 * @{
213 */
214 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
215 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
216 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
217 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
218 /**
219 * @}
220 */
221
222 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
223 * @{
224 */
225 /* Note: LL_PWR_GPIO_BIT_x defined from port B because all pins are available */
226 /* for PWR pull-up and pull-down. */
227 #define LL_PWR_GPIO_BIT_0 (PWR_PUCRB_PB0)
228 #define LL_PWR_GPIO_BIT_1 (PWR_PUCRB_PB1)
229 #define LL_PWR_GPIO_BIT_2 (PWR_PUCRB_PB2)
230 #define LL_PWR_GPIO_BIT_3 (PWR_PUCRB_PB3)
231 #define LL_PWR_GPIO_BIT_4 (PWR_PUCRB_PB4)
232 #define LL_PWR_GPIO_BIT_5 (PWR_PUCRB_PB5)
233 #define LL_PWR_GPIO_BIT_6 (PWR_PUCRB_PB6)
234 #define LL_PWR_GPIO_BIT_7 (PWR_PUCRB_PB7)
235 #define LL_PWR_GPIO_BIT_8 (PWR_PUCRB_PB8)
236 #define LL_PWR_GPIO_BIT_9 (PWR_PUCRB_PB9)
237 #define LL_PWR_GPIO_BIT_10 (PWR_PUCRB_PB10)
238 #define LL_PWR_GPIO_BIT_11 (PWR_PUCRB_PB11)
239 #define LL_PWR_GPIO_BIT_12 (PWR_PUCRB_PB12)
240 #define LL_PWR_GPIO_BIT_13 (PWR_PUCRB_PB13)
241 #define LL_PWR_GPIO_BIT_14 (PWR_PUCRB_PB14)
242 #define LL_PWR_GPIO_BIT_15 (PWR_PUCRB_PB15)
243 /**
244 * @}
245 */
246
247 /** @defgroup PWR_LL_EC_SMPS_OPERATING_MODES SMPS step down converter operating modes
248 * @{
249 */
250 #define LL_PWR_SMPS_BYPASS (0x00000000UL) /*!< SMPS step down in bypass mode (disable). */
251 #define LL_PWR_SMPS_STEP_DOWN (PWR_CR5_SMPSEN) /*!< SMPS step down in step down mode if system low power mode is run, LP run or Stop 0. If system low power mode is Stop 1, Stop 2, Standby, Shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. Note: In case of a board without SMPS coil mounted, SMPS should not be activated. */
252 /**
253 * @}
254 */
255
256 /** @defgroup PWR_LL_EC_RADIO_BUSY_POLARITY Radio busy signal polarity
257 * @{
258 */
259 #define LL_PWR_RADIO_BUSY_POLARITY_RISING (0x00000000UL) /*!< Radio busy signal polarity to rising edge (detection on high level). */
260 #define LL_PWR_RADIO_BUSY_POLARITY_FALLING (PWR_CR4_WRFBUSYP) /*!< Radio busy signal polarity to falling edge (detection on low level). */
261 /**
262 * @}
263 */
264
265 /** @defgroup PWR_LL_EC_RADIO_BUSY_TRIGGER Radio busy trigger
266 * @{
267 */
268 #define LL_PWR_RADIO_BUSY_TRIGGER_NONE (0x00000000UL) /*!< Radio busy trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
269 #define LL_PWR_RADIO_BUSY_TRIGGER_WU_IT (PWR_CR3_EWRFBUSY) /*!< Radio busy trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
270 /**
271 * @}
272 */
273
274 /** @defgroup PWR_LL_EC_RADIO_IRQ_TRIGGER Radio IRQ trigger
275 * @{
276 */
277 #define LL_PWR_RADIO_IRQ_TRIGGER_NONE (0x00000000UL) /*!< Radio IRQ trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
278 #define LL_PWR_RADIO_IRQ_TRIGGER_WU_IT (PWR_CR3_EWRFIRQ) /*!< Radio IRQ trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
279 /**
280 * @}
281 */
282
283 /** @defgroup PWR_LL_EC_RADIO_SPI_NSS_SRC Radio Sub-GHz radio SPI NSS source
284 * @{
285 */
286 #define LL_PWR_SUBGHZSPI_NSS_SRC_SW (0x00000000UL) /*!< Sub-GHz radio SPI NSS controlled by software. Refer to function @ref LL_PWR_UnselectSUBGHZSPI_NSS(). */
287 #define LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3 (PWR_CR1_SUBGHZSPINSSSEL) /*!< Sub-GHz radio SPI NSS controlled by LPTIM3. */
288 /**
289 * @}
290 */
291
292 /**
293 * @}
294 */
295
296 /* Exported macro ------------------------------------------------------------*/
297 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
298 * @{
299 */
300
301 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
302 * @{
303 */
304
305 /**
306 * @brief Write a value in PWR register
307 * @param __REG__ Register to be written
308 * @param __VALUE__ Value to be written in the register
309 * @retval None
310 */
311 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
312
313 /**
314 * @brief Read a value in PWR register
315 * @param __REG__ Register to be read
316 * @retval Register value
317 */
318 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
319 /**
320 * @}
321 */
322
323 /**
324 * @}
325 */
326
327
328 /* Exported functions --------------------------------------------------------*/
329 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
330 * @{
331 */
332
333 /** @defgroup PWR_LL_EF_Configuration Configuration
334 * @{
335 */
336
337 /**
338 * @brief Switch from run main mode to run low-power mode.
339 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
340 * @retval None
341 */
LL_PWR_EnterLowPowerRunMode(void)342 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
343 {
344 SET_BIT(PWR->CR1, PWR_CR1_LPR);
345 }
346
347 /**
348 * @brief Switch from run main mode to low-power mode.
349 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
350 * @retval None
351 */
LL_PWR_ExitLowPowerRunMode(void)352 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
353 {
354 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
355 }
356
357 /**
358 * @brief Check if the regulator is in low-power mode
359 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
360 * @retval State of bit (1 or 0).
361 */
LL_PWR_IsEnabledLowPowerRunMode(void)362 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
363 {
364 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
365 }
366
367 /**
368 * @brief Set the main internal regulator output voltage
369 * @note A delay is required for the internal regulator to be ready
370 * after the voltage scaling has been changed.
371 * Check whether regulator reached the selected voltage level
372 * can be done using function @ref LL_PWR_IsActiveFlag_VOS().
373 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
374 * @param VoltageScaling This parameter can be one of the following values:
375 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
376 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
377 * @retval None
378 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)379 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
380 {
381 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
382 }
383
384 /**
385 * @brief Get the main internal regulator output voltage
386 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
387 * @retval Returned value can be one of the following values:
388 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
389 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
390 */
LL_PWR_GetRegulVoltageScaling(void)391 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
392 {
393 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
394 }
395
396 /**
397 * @brief Enable access to the backup domain
398 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
399 * @retval None
400 */
LL_PWR_EnableBkUpAccess(void)401 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
402 {
403 SET_BIT(PWR->CR1, PWR_CR1_DBP);
404 }
405
406 /**
407 * @brief Disable access to the backup domain
408 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
409 * @retval None
410 */
LL_PWR_DisableBkUpAccess(void)411 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
412 {
413 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
414 }
415
416 /**
417 * @brief Check if the backup domain is enabled
418 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
419 * @retval State of bit (1 or 0).
420 */
LL_PWR_IsEnabledBkUpAccess(void)421 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
422 {
423 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
424 }
425
426 /**
427 * @brief Set Low-Power mode
428 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
429 * @param LowPowerMode This parameter can be one of the following values:
430 * @arg @ref LL_PWR_MODE_STOP0
431 * @arg @ref LL_PWR_MODE_STOP1
432 * @arg @ref LL_PWR_MODE_STOP2
433 * @arg @ref LL_PWR_MODE_STANDBY
434 * @arg @ref LL_PWR_MODE_SHUTDOWN
435 * @retval None
436 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)437 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
438 {
439 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
440 }
441
442 /**
443 * @brief Get Low-Power mode
444 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
445 * @retval Returned value can be one of the following values:
446 * @arg @ref LL_PWR_MODE_STOP0
447 * @arg @ref LL_PWR_MODE_STOP1
448 * @arg @ref LL_PWR_MODE_STOP2
449 * @arg @ref LL_PWR_MODE_STANDBY
450 * @arg @ref LL_PWR_MODE_SHUTDOWN
451 */
LL_PWR_GetPowerMode(void)452 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
453 {
454 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
455 }
456
457 /**
458 * @brief Set flash power-down mode during low-power run mode
459 * @rmtoll CR1 FPDR LL_PWR_SetFlashPowerModeLPRun
460 * @param FlashLowPowerMode This parameter can be one of the following values:
461 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
462 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
463 * @retval None
464 */
LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)465 __STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
466 {
467 /* Unlock bit FPDR */
468 WRITE_REG(PWR->CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE);
469
470 /* Update bit FPDR */
471 MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
472 }
473
474 /**
475 * @brief Get flash power-down mode during low-power run mode
476 * @rmtoll CR1 FPDR LL_PWR_GetFlashPowerModeLPRun
477 * @retval Returned value can be one of the following values:
478 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
479 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
480 */
LL_PWR_GetFlashPowerModeLPRun(void)481 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeLPRun(void)
482 {
483 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDR));
484 }
485
486 /**
487 * @brief Set flash power-down mode during sleep mode
488 * @rmtoll CR1 FPDS LL_PWR_SetFlashPowerModeSleep
489 * @param FlashLowPowerMode This parameter can be one of the following values:
490 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
491 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
492 * @retval None
493 */
LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)494 __STATIC_INLINE void LL_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
495 {
496 MODIFY_REG(PWR->CR1, PWR_CR1_FPDS, FlashLowPowerMode);
497 }
498
499 /**
500 * @brief Get flash power-down mode during sleep mode
501 * @rmtoll CR1 FPDS LL_PWR_GetFlashPowerModeSleep
502 * @retval Returned value can be one of the following values:
503 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
504 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
505 */
LL_PWR_GetFlashPowerModeSleep(void)506 __STATIC_INLINE uint32_t LL_PWR_GetFlashPowerModeSleep(void)
507 {
508 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_FPDS));
509 }
510
511 /**
512 * @brief Enable the Power Voltage Monitoring on a peripheral
513 * @rmtoll CR2 PVME3 LL_PWR_EnablePVM
514 * @param PeriphVoltage This parameter can be one of the following values:
515 * @arg @ref LL_PWR_PVM_VDDA_1_62V
516 * @retval None
517 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)518 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
519 {
520 SET_BIT(PWR->CR2, PeriphVoltage);
521 }
522
523 /**
524 * @brief Disable the Power Voltage Monitoring on a peripheral
525 * @rmtoll CR2 PVME3 LL_PWR_DisablePVM
526 * @param PeriphVoltage This parameter can be one of the following values:
527 * @arg @ref LL_PWR_PVM_VDDA_1_62V
528 * @retval None
529 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)530 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
531 {
532 CLEAR_BIT(PWR->CR2, PeriphVoltage);
533 }
534
535 /**
536 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
537 * @rmtoll CR2 PVME3 LL_PWR_IsEnabledPVM
538 * @param PeriphVoltage This parameter can be one of the following values:
539 * @arg @ref LL_PWR_PVM_VDDA_1_62V
540 * @retval State of bit (1 or 0).
541 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)542 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
543 {
544 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
545 }
546
547 /**
548 * @brief Configure the voltage threshold detected by the Power Voltage Detector
549 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
550 * @param PVDLevel This parameter can be one of the following values:
551 * @arg @ref LL_PWR_PVDLEVEL_0
552 * @arg @ref LL_PWR_PVDLEVEL_1
553 * @arg @ref LL_PWR_PVDLEVEL_2
554 * @arg @ref LL_PWR_PVDLEVEL_3
555 * @arg @ref LL_PWR_PVDLEVEL_4
556 * @arg @ref LL_PWR_PVDLEVEL_5
557 * @arg @ref LL_PWR_PVDLEVEL_6
558 * @arg @ref LL_PWR_PVDLEVEL_7
559 * @retval None
560 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)561 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
562 {
563 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
564 }
565
566 /**
567 * @brief Get the voltage threshold detection
568 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
569 * @retval Returned value can be one of the following values:
570 * @arg @ref LL_PWR_PVDLEVEL_0
571 * @arg @ref LL_PWR_PVDLEVEL_1
572 * @arg @ref LL_PWR_PVDLEVEL_2
573 * @arg @ref LL_PWR_PVDLEVEL_3
574 * @arg @ref LL_PWR_PVDLEVEL_4
575 * @arg @ref LL_PWR_PVDLEVEL_5
576 * @arg @ref LL_PWR_PVDLEVEL_6
577 * @arg @ref LL_PWR_PVDLEVEL_7
578 */
LL_PWR_GetPVDLevel(void)579 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
580 {
581 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
582 }
583
584 /**
585 * @brief Enable Power Voltage Detector
586 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
587 * @retval None
588 */
LL_PWR_EnablePVD(void)589 __STATIC_INLINE void LL_PWR_EnablePVD(void)
590 {
591 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
592 }
593
594 /**
595 * @brief Disable Power Voltage Detector
596 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
597 * @retval None
598 */
LL_PWR_DisablePVD(void)599 __STATIC_INLINE void LL_PWR_DisablePVD(void)
600 {
601 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
602 }
603
604 /**
605 * @brief Check if Power Voltage Detector is enabled
606 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
607 * @retval State of bit (1 or 0).
608 */
LL_PWR_IsEnabledPVD(void)609 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
610 {
611 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
612 }
613
614 /**
615 * @brief Set monitoring of supply voltage for radio operating level
616 * (radio End Of Life), radio must be in active mode.
617 * @rmtoll CR5 RFEOLEN LL_PWR_SetRadioEOL
618 * @param RadioEOL This parameter can be one of the following values:
619 * @arg @ref LL_PWR_RADIO_EOL_DISABLE
620 * @arg @ref LL_PWR_RADIO_EOL_ENABLE
621 * @retval None
622 */
LL_PWR_SetRadioEOL(uint32_t RadioEOL)623 __STATIC_INLINE void LL_PWR_SetRadioEOL(uint32_t RadioEOL)
624 {
625 MODIFY_REG(PWR->CR5, PWR_CR5_RFEOLEN, RadioEOL);
626 }
627
628 /**
629 * @brief Get monitoring of supply voltage for radio operating level (radio End Of Life)
630 * @rmtoll CR5 RFEOLEN LL_PWR_GetRadioEOL
631 * @retval Returned value can be one of the following values:
632 * @arg @ref LL_PWR_RADIO_EOL_DISABLE
633 * @arg @ref LL_PWR_RADIO_EOL_ENABLE
634 */
LL_PWR_GetRadioEOL(void)635 __STATIC_INLINE uint32_t LL_PWR_GetRadioEOL(void)
636 {
637 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_RFEOLEN));
638 }
639
640 /**
641 * @brief Enable Internal Wake-up line
642 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
643 * @retval None
644 */
LL_PWR_EnableInternWU(void)645 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
646 {
647 SET_BIT(PWR->CR3, PWR_CR3_EIWUL);
648 }
649
650 /**
651 * @brief Disable Internal Wake-up line
652 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
653 * @retval None
654 */
LL_PWR_DisableInternWU(void)655 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
656 {
657 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
658 }
659
660 /**
661 * @brief Check if Internal Wake-up line is enabled
662 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
663 * @retval State of bit (1 or 0).
664 */
LL_PWR_IsEnabledInternWU(void)665 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
666 {
667 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL);
668 }
669
670 /**
671 * @brief Enable pull-up and pull-down configuration
672 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
673 * @retval None
674 */
LL_PWR_EnablePUPDCfg(void)675 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
676 {
677 SET_BIT(PWR->CR3, PWR_CR3_APC);
678 }
679
680 /**
681 * @brief Disable pull-up and pull-down configuration
682 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
683 * @retval None
684 */
LL_PWR_DisablePUPDCfg(void)685 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
686 {
687 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
688 }
689
690 /**
691 * @brief Check if pull-up and pull-down configuration is enabled
692 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
693 * @retval State of bit (1 or 0).
694 */
LL_PWR_IsEnabledPUPDCfg(void)695 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
696 {
697 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
698 }
699
700 /**
701 * @brief Enable SRAM2 content retention in Standby mode
702 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
703 * @retval None
704 */
LL_PWR_EnableSRAM2Retention(void)705 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
706 {
707 SET_BIT(PWR->CR3, PWR_CR3_RRS);
708 }
709
710 /**
711 * @brief Disable SRAM2 content retention in Standby mode
712 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
713 * @retval None
714 */
LL_PWR_DisableSRAM2Retention(void)715 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
716 {
717 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
718 }
719
720 /**
721 * @brief Check if SRAM2 content retention in Standby mode is enabled
722 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
723 * @retval State of bit (1 or 0).
724 */
LL_PWR_IsEnabledSRAM2Retention(void)725 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
726 {
727 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL);
728 }
729
730 /**
731 * @brief Enable wake-up power voltage detection with trigger for CPU1
732 * @note Wake-up power voltage detection status can be checked
733 * using function @ref LL_PWR_IsActiveFlag_WPVD().
734 * @rmtoll CR3 EWPVD LL_PWR_EnableWPVD
735 * @retval None
736 */
LL_PWR_EnableWPVD(void)737 __STATIC_INLINE void LL_PWR_EnableWPVD(void)
738 {
739 SET_BIT(PWR->CR3, PWR_CR3_EWPVD);
740 }
741
742 /**
743 * @brief Disable wake-up power voltage detection with trigger for CPU1
744 * @rmtoll CR3 EWPVD LL_PWR_DisableWPVD
745 * @retval None
746 */
LL_PWR_DisableWPVD(void)747 __STATIC_INLINE void LL_PWR_DisableWPVD(void)
748 {
749 CLEAR_BIT(PWR->CR3, PWR_CR3_EWPVD);
750 }
751
752 /**
753 * @brief Check if wake-up power voltage detection is enabled with trigger for CPU1
754 * @rmtoll CR3 EWPVD LL_PWR_IsEnabledWPVD
755 * @retval State of bit (1 or 0).
756 */
LL_PWR_IsEnabledWPVD(void)757 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWPVD(void)
758 {
759 return ((READ_BIT(PWR->CR3, PWR_CR3_EWPVD) == (PWR_CR3_EWPVD)) ? 1UL : 0UL);
760 }
761
762 /**
763 * @brief Enable periodical sampling of supply voltage in Stop and Standby
764 * modes for detecting condition of PDR and BOR reset.
765 * @note Caution: When enabled, and if the supply voltage drops below
766 * the minimum operating condition between two supply voltage samples,
767 * the reset condition is missed and no reset is generated.
768 * @rmtoll CR3 ULPEN LL_PWR_EnableBORPVD_ULP
769 * @retval None
770 */
LL_PWR_EnableBORPVD_ULP(void)771 __STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)
772 {
773 SET_BIT(PWR->CR3, PWR_CR3_ULPEN);
774 }
775
776 /**
777 * @brief Disable periodical sampling of supply voltage in Stop and Standby
778 * modes for detecting condition of PDR and BOR reset.
779 * @rmtoll CR3 ULPEN LL_PWR_DisableBORPVD_ULP
780 * @retval None
781 */
LL_PWR_DisableBORPVD_ULP(void)782 __STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)
783 {
784 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPEN);
785 }
786
787 /**
788 * @brief Check if periodical sampling of supply voltage in Stop and Standby
789 * modes is enabled.
790 * @rmtoll CR3 ULPEN LL_PWR_IsEnabledBORPVD_ULP
791 * @retval State of bit (1 or 0).
792 */
LL_PWR_IsEnabledBORPVD_ULP(void)793 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)
794 {
795 return ((READ_BIT(PWR->CR3, PWR_CR3_ULPEN) == (PWR_CR3_ULPEN)) ? 1UL : 0UL);
796 }
797
798 /**
799 * @brief Enable the WakeUp PINx functionality
800 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
801 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
802 * CR3 EWUP3 LL_PWR_EnableWakeUpPin
803 * @param WakeUpPin This parameter can be one of the following values:
804 * @arg @ref LL_PWR_WAKEUP_PIN1
805 * @arg @ref LL_PWR_WAKEUP_PIN2
806 * @arg @ref LL_PWR_WAKEUP_PIN3
807 * @retval None
808 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)809 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
810 {
811 SET_BIT(PWR->CR3, WakeUpPin);
812 }
813
814 /**
815 * @brief Disable the WakeUp PINx functionality
816 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
817 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
818 * CR3 EWUP3 LL_PWR_DisableWakeUpPin
819 * @param WakeUpPin This parameter can be one of the following values:
820 * @arg @ref LL_PWR_WAKEUP_PIN1
821 * @arg @ref LL_PWR_WAKEUP_PIN2
822 * @arg @ref LL_PWR_WAKEUP_PIN3
823 * @retval None
824 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)825 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
826 {
827 CLEAR_BIT(PWR->CR3, WakeUpPin);
828 }
829
830 /**
831 * @brief Check if the WakeUp PINx functionality is enabled
832 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
833 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
834 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin
835 * @param WakeUpPin This parameter can be one of the following values:
836 * @arg @ref LL_PWR_WAKEUP_PIN1
837 * @arg @ref LL_PWR_WAKEUP_PIN2
838 * @arg @ref LL_PWR_WAKEUP_PIN3
839 * @retval State of bit (1 or 0).
840 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)841 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
842 {
843 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
844 }
845
846 /**
847 * @brief Set the resistor impedance
848 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
849 * @param Resistor This parameter can be one of the following values:
850 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
851 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
852 * @retval None
853 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)854 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
855 {
856 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
857 }
858
859 /**
860 * @brief Get the resistor impedance
861 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
862 * @retval Returned value can be one of the following values:
863 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
864 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
865 */
LL_PWR_GetBattChargResistor(void)866 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
867 {
868 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
869 }
870
871 /**
872 * @brief Enable battery charging
873 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
874 * @retval None
875 */
LL_PWR_EnableBatteryCharging(void)876 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
877 {
878 SET_BIT(PWR->CR4, PWR_CR4_VBE);
879 }
880
881 /**
882 * @brief Disable battery charging
883 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
884 * @retval None
885 */
LL_PWR_DisableBatteryCharging(void)886 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
887 {
888 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
889 }
890
891 /**
892 * @brief Check if battery charging is enabled
893 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
894 * @retval State of bit (1 or 0).
895 */
LL_PWR_IsEnabledBatteryCharging(void)896 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
897 {
898 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
899 }
900
901 /**
902 * @brief Set the Wake-Up pin polarity low for the event detection
903 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
904 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
905 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow
906 * @param WakeUpPin This parameter can be one of the following values:
907 * @arg @ref LL_PWR_WAKEUP_PIN1
908 * @arg @ref LL_PWR_WAKEUP_PIN2
909 * @arg @ref LL_PWR_WAKEUP_PIN3
910 * @retval None
911 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)912 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
913 {
914 SET_BIT(PWR->CR4, WakeUpPin);
915 }
916
917 /**
918 * @brief Set the Wake-Up pin polarity high for the event detection
919 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
920 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
921 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh
922 * @param WakeUpPin This parameter can be one of the following values:
923 * @arg @ref LL_PWR_WAKEUP_PIN1
924 * @arg @ref LL_PWR_WAKEUP_PIN2
925 * @arg @ref LL_PWR_WAKEUP_PIN3
926 * @retval None
927 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)928 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
929 {
930 CLEAR_BIT(PWR->CR4, WakeUpPin);
931 }
932
933 /**
934 * @brief Get the Wake-Up pin polarity for the event detection
935 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
936 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
937 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow
938 * @param WakeUpPin This parameter can be one of the following values:
939 * @arg @ref LL_PWR_WAKEUP_PIN1
940 * @arg @ref LL_PWR_WAKEUP_PIN2
941 * @arg @ref LL_PWR_WAKEUP_PIN3
942 * @retval State of bit (1 or 0).
943 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)944 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
945 {
946 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
947 }
948
949 /**
950 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
951 * @note Some pins are not configurable for pulling in Standby and Shutdown
952 * modes. Refer to reference manual for available pins and ports.
953 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
954 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
955 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
956 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
957 * @param GPIO This parameter can be one of the following values:
958 * @arg @ref LL_PWR_GPIO_A
959 * @arg @ref LL_PWR_GPIO_B
960 * @arg @ref LL_PWR_GPIO_C
961 * @arg @ref LL_PWR_GPIO_H
962 * @param GPIONumber This parameter can be one of the following values:
963 * @arg @ref LL_PWR_GPIO_BIT_0
964 * @arg @ref LL_PWR_GPIO_BIT_1
965 * @arg @ref LL_PWR_GPIO_BIT_2
966 * @arg @ref LL_PWR_GPIO_BIT_3
967 * @arg @ref LL_PWR_GPIO_BIT_4
968 * @arg @ref LL_PWR_GPIO_BIT_5
969 * @arg @ref LL_PWR_GPIO_BIT_6
970 * @arg @ref LL_PWR_GPIO_BIT_7
971 * @arg @ref LL_PWR_GPIO_BIT_8
972 * @arg @ref LL_PWR_GPIO_BIT_9
973 * @arg @ref LL_PWR_GPIO_BIT_10
974 * @arg @ref LL_PWR_GPIO_BIT_11
975 * @arg @ref LL_PWR_GPIO_BIT_12
976 * @arg @ref LL_PWR_GPIO_BIT_13
977 * @arg @ref LL_PWR_GPIO_BIT_14
978 * @arg @ref LL_PWR_GPIO_BIT_15
979 * @retval None
980 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)981 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
982 {
983 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
984 }
985
986 /**
987 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
988 * @note Some pins are not configurable for pulling in Standby and Shutdown
989 * modes. Refer to reference manual for available pins and ports.
990 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
991 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
992 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
993 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
994 * @param GPIO This parameter can be one of the following values:
995 * @arg @ref LL_PWR_GPIO_A
996 * @arg @ref LL_PWR_GPIO_B
997 * @arg @ref LL_PWR_GPIO_C
998 * @arg @ref LL_PWR_GPIO_H
999 * @param GPIONumber This parameter can be one of the following values:
1000 * @arg @ref LL_PWR_GPIO_BIT_0
1001 * @arg @ref LL_PWR_GPIO_BIT_1
1002 * @arg @ref LL_PWR_GPIO_BIT_2
1003 * @arg @ref LL_PWR_GPIO_BIT_3
1004 * @arg @ref LL_PWR_GPIO_BIT_4
1005 * @arg @ref LL_PWR_GPIO_BIT_5
1006 * @arg @ref LL_PWR_GPIO_BIT_6
1007 * @arg @ref LL_PWR_GPIO_BIT_7
1008 * @arg @ref LL_PWR_GPIO_BIT_8
1009 * @arg @ref LL_PWR_GPIO_BIT_9
1010 * @arg @ref LL_PWR_GPIO_BIT_10
1011 * @arg @ref LL_PWR_GPIO_BIT_11
1012 * @arg @ref LL_PWR_GPIO_BIT_12
1013 * @arg @ref LL_PWR_GPIO_BIT_13
1014 * @arg @ref LL_PWR_GPIO_BIT_14
1015 * @arg @ref LL_PWR_GPIO_BIT_15
1016 * @retval None
1017 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1018 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1019 {
1020 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1021 }
1022
1023 /**
1024 * @brief Check if GPIO pull-up state is enabled
1025 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1026 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1027 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1028 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
1029 * @param GPIO This parameter can be one of the following values:
1030 * @arg @ref LL_PWR_GPIO_A
1031 * @arg @ref LL_PWR_GPIO_B
1032 * @arg @ref LL_PWR_GPIO_C
1033 * @arg @ref LL_PWR_GPIO_H
1034 * @param GPIONumber This parameter can be one of the following values:
1035 * @arg @ref LL_PWR_GPIO_BIT_0
1036 * @arg @ref LL_PWR_GPIO_BIT_1
1037 * @arg @ref LL_PWR_GPIO_BIT_2
1038 * @arg @ref LL_PWR_GPIO_BIT_3
1039 * @arg @ref LL_PWR_GPIO_BIT_4
1040 * @arg @ref LL_PWR_GPIO_BIT_5
1041 * @arg @ref LL_PWR_GPIO_BIT_6
1042 * @arg @ref LL_PWR_GPIO_BIT_7
1043 * @arg @ref LL_PWR_GPIO_BIT_8
1044 * @arg @ref LL_PWR_GPIO_BIT_9
1045 * @arg @ref LL_PWR_GPIO_BIT_10
1046 * @arg @ref LL_PWR_GPIO_BIT_11
1047 * @arg @ref LL_PWR_GPIO_BIT_12
1048 * @arg @ref LL_PWR_GPIO_BIT_13
1049 * @arg @ref LL_PWR_GPIO_BIT_14
1050 * @arg @ref LL_PWR_GPIO_BIT_15
1051 * @retval State of bit (1 or 0).
1052 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1053 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1054 {
1055 return ((READ_BIT(*((__IO uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1056 }
1057
1058 /**
1059 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1060 * @note Some pins are not configurable for pulling in Standby and Shutdown
1061 * modes. Refer to reference manual for available pins and ports.
1062 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1063 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1064 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1065 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
1066 * @param GPIO This parameter can be one of the following values:
1067 * @arg @ref LL_PWR_GPIO_A
1068 * @arg @ref LL_PWR_GPIO_B
1069 * @arg @ref LL_PWR_GPIO_C
1070 * @arg @ref LL_PWR_GPIO_H
1071 * @param GPIONumber This parameter can be one of the following values:
1072 * @arg @ref LL_PWR_GPIO_BIT_0
1073 * @arg @ref LL_PWR_GPIO_BIT_1
1074 * @arg @ref LL_PWR_GPIO_BIT_2
1075 * @arg @ref LL_PWR_GPIO_BIT_3
1076 * @arg @ref LL_PWR_GPIO_BIT_4
1077 * @arg @ref LL_PWR_GPIO_BIT_5
1078 * @arg @ref LL_PWR_GPIO_BIT_6
1079 * @arg @ref LL_PWR_GPIO_BIT_7
1080 * @arg @ref LL_PWR_GPIO_BIT_8
1081 * @arg @ref LL_PWR_GPIO_BIT_9
1082 * @arg @ref LL_PWR_GPIO_BIT_10
1083 * @arg @ref LL_PWR_GPIO_BIT_11
1084 * @arg @ref LL_PWR_GPIO_BIT_12
1085 * @arg @ref LL_PWR_GPIO_BIT_13
1086 * @arg @ref LL_PWR_GPIO_BIT_14
1087 * @arg @ref LL_PWR_GPIO_BIT_15
1088 * @retval None
1089 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1090 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1091 {
1092 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1093 }
1094
1095 /**
1096 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1097 * @note Some pins are not configurable for pulling in Standby and Shutdown
1098 * modes. Refer to reference manual for available pins and ports.
1099 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1100 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1101 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1102 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
1103 * @param GPIO This parameter can be one of the following values:
1104 * @arg @ref LL_PWR_GPIO_A
1105 * @arg @ref LL_PWR_GPIO_B
1106 * @arg @ref LL_PWR_GPIO_C
1107 * @arg @ref LL_PWR_GPIO_H
1108 * @param GPIONumber This parameter can be one of the following values:
1109 * @arg @ref LL_PWR_GPIO_BIT_0
1110 * @arg @ref LL_PWR_GPIO_BIT_1
1111 * @arg @ref LL_PWR_GPIO_BIT_2
1112 * @arg @ref LL_PWR_GPIO_BIT_3
1113 * @arg @ref LL_PWR_GPIO_BIT_4
1114 * @arg @ref LL_PWR_GPIO_BIT_5
1115 * @arg @ref LL_PWR_GPIO_BIT_6
1116 * @arg @ref LL_PWR_GPIO_BIT_7
1117 * @arg @ref LL_PWR_GPIO_BIT_8
1118 * @arg @ref LL_PWR_GPIO_BIT_9
1119 * @arg @ref LL_PWR_GPIO_BIT_10
1120 * @arg @ref LL_PWR_GPIO_BIT_11
1121 * @arg @ref LL_PWR_GPIO_BIT_12
1122 * @arg @ref LL_PWR_GPIO_BIT_13
1123 * @arg @ref LL_PWR_GPIO_BIT_14
1124 * @arg @ref LL_PWR_GPIO_BIT_15
1125 * @retval None
1126 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1127 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1128 {
1129 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1130 }
1131
1132 /**
1133 * @brief Check if GPIO pull-down state is enabled
1134 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1135 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1136 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1137 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
1138 * @param GPIO This parameter can be one of the following values:
1139 * @arg @ref LL_PWR_GPIO_A
1140 * @arg @ref LL_PWR_GPIO_B
1141 * @arg @ref LL_PWR_GPIO_C
1142 * @arg @ref LL_PWR_GPIO_H
1143 * @param GPIONumber This parameter can be one of the following values:
1144 * @arg @ref LL_PWR_GPIO_BIT_0
1145 * @arg @ref LL_PWR_GPIO_BIT_1
1146 * @arg @ref LL_PWR_GPIO_BIT_2
1147 * @arg @ref LL_PWR_GPIO_BIT_3
1148 * @arg @ref LL_PWR_GPIO_BIT_4
1149 * @arg @ref LL_PWR_GPIO_BIT_5
1150 * @arg @ref LL_PWR_GPIO_BIT_6
1151 * @arg @ref LL_PWR_GPIO_BIT_7
1152 * @arg @ref LL_PWR_GPIO_BIT_8
1153 * @arg @ref LL_PWR_GPIO_BIT_9
1154 * @arg @ref LL_PWR_GPIO_BIT_10
1155 * @arg @ref LL_PWR_GPIO_BIT_11
1156 * @arg @ref LL_PWR_GPIO_BIT_12
1157 * @arg @ref LL_PWR_GPIO_BIT_13
1158 * @arg @ref LL_PWR_GPIO_BIT_14
1159 * @arg @ref LL_PWR_GPIO_BIT_15
1160 * @retval State of bit (1 or 0).
1161 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1162 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1163 {
1164 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1165 }
1166
1167 /**
1168 * @}
1169 */
1170
1171 /** @defgroup PWR_LL_EF_Configuration_SMPS Configuration of SMPS
1172 * @{
1173 */
1174
1175 /**
1176 * @brief Set SMPS operating mode
1177 * @note In case of a board without SMPS coil mounted, SMPS should not be activated.
1178 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_SetMode
1179 * @param OperatingMode This parameter can be one of the following values:
1180 * @arg @ref LL_PWR_SMPS_BYPASS
1181 * @arg @ref LL_PWR_SMPS_STEP_DOWN
1182 * @retval None
1183 */
LL_PWR_SMPS_SetMode(uint32_t OperatingMode)1184 __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
1185 {
1186 MODIFY_REG(PWR->CR5, PWR_CR5_SMPSEN, OperatingMode);
1187 }
1188
1189 /**
1190 * @brief Get SMPS operating mode
1191 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_GetMode
1192 * @retval Returned value can be one of the following values:
1193 * @arg @ref LL_PWR_SMPS_BYPASS
1194 * @arg @ref LL_PWR_SMPS_STEP_DOWN
1195 */
LL_PWR_SMPS_GetMode(void)1196 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
1197 {
1198 return (uint32_t)(READ_BIT(PWR->CR5, PWR_CR5_SMPSEN));
1199 }
1200
1201 /**
1202 * @brief Get SMPS effective operating mode
1203 * @note SMPS operating mode can be changed by hardware, therefore
1204 * requested operating mode can differ from effective low power mode.
1205 * - dependency SubGhz Radio IP: can switch SMPS on for radio activity.
1206 * @note In case of a board without SMPS coil mounted, SMPS should not be activated
1207 * and this function is not relevant.
1208 * @rmtoll SR2 SMPSRDY LL_PWR_SMPS_GetEffectiveMode
1209 * @retval Returned value can be one of the following values:
1210 * @arg @ref LL_PWR_SMPS_BYPASS
1211 * @arg @ref LL_PWR_SMPS_STEP_DOWN
1212 */
LL_PWR_SMPS_GetEffectiveMode(void)1213 __STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
1214 {
1215 /* Return a value corresponding to definition of literals */
1216 /* LL_PWR_SMPS_BYPASS or LL_PWR_SMPS_STEP_DOWN. */
1217 return (uint32_t)(READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) << (PWR_CR5_SMPSEN_Pos - PWR_SR2_SMPSRDY_Pos));
1218 }
1219
1220 /**
1221 * @brief SMPS step down converter enable
1222 * @note This function can be used for specific usage of the SMPS,
1223 * for general usage of the SMPS the function
1224 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1225 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Enable
1226 * @retval None
1227 */
LL_PWR_SMPS_Enable(void)1228 __STATIC_INLINE void LL_PWR_SMPS_Enable(void)
1229 {
1230 SET_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1231 }
1232
1233 /**
1234 * @brief SMPS step down converter enable
1235 * @note This function can be used for specific usage of the SMPS,
1236 * for general usage of the SMPS the function
1237 * @ref LL_PWR_SMPS_SetMode() should be used instead.
1238 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_Disable
1239 * @retval None
1240 */
LL_PWR_SMPS_Disable(void)1241 __STATIC_INLINE void LL_PWR_SMPS_Disable(void)
1242 {
1243 CLEAR_BIT(PWR->CR5, PWR_CR5_SMPSEN);
1244 }
1245
1246 /**
1247 * @brief Check if the SMPS step down converter is enabled
1248 * @rmtoll CR5 SMPSEN LL_PWR_SMPS_IsEnabled
1249 * @retval State of bit (1 or 0).
1250 */
LL_PWR_SMPS_IsEnabled(void)1251 __STATIC_INLINE uint32_t LL_PWR_SMPS_IsEnabled(void)
1252 {
1253 return ((READ_BIT(PWR->CR5, PWR_CR5_SMPSEN) == (PWR_CR5_SMPSEN)) ? 1UL : 0UL);
1254 }
1255
1256 /**
1257 * @}
1258 */
1259
1260 /** @defgroup PWR_LL_EF_Configuration_Radio Configuration of radio
1261 * @{
1262 */
1263
1264 /**
1265 * @brief Set radio busy signal polarity
1266 * @rmtoll CR4 RFBUSYP LL_PWR_SetRadioBusyPolarity
1267 * @param RadioBusyPolarity This parameter can be one of the following values:
1268 * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_RISING
1269 * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_FALLING
1270 * @retval None
1271 */
LL_PWR_SetRadioBusyPolarity(uint32_t RadioBusyPolarity)1272 __STATIC_INLINE void LL_PWR_SetRadioBusyPolarity(uint32_t RadioBusyPolarity)
1273 {
1274 MODIFY_REG(PWR->CR4, PWR_CR4_WRFBUSYP, RadioBusyPolarity);
1275 }
1276
1277 /**
1278 * @brief Get radio busy signal polarity
1279 * @rmtoll CR4 RFBUSYP LL_PWR_GetRadioBusyPolarity
1280 * @retval Returned value can be one of the following values:
1281 * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_RISING
1282 * @arg @ref LL_PWR_RADIO_BUSY_POLARITY_FALLING
1283 */
LL_PWR_GetRadioBusyPolarity(void)1284 __STATIC_INLINE uint32_t LL_PWR_GetRadioBusyPolarity(void)
1285 {
1286 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_WRFBUSYP));
1287 }
1288
1289 /**
1290 * @brief Set radio busy trigger action for CPU1: wake-up from low-power mode
1291 * Standby.
1292 * @note Signal polarity can be configured using function
1293 * @ref LL_PWR_SetRadioBusyPolarity().
1294 * @rmtoll CR3 ERFBUSY LL_PWR_SetRadioBusyTrigger
1295 * @param RadioBusyTrigger This parameter can be one of the following values:
1296 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE
1297 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT
1298 * @retval None
1299 */
LL_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)1300 __STATIC_INLINE void LL_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)
1301 {
1302 MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger);
1303 }
1304
1305 /**
1306 * @brief Get radio busy trigger action for CPU1: wake-up from low-power mode
1307 * Standby.
1308 * @rmtoll CR3 ERFBUSY LL_PWR_GetRadioBusyTrigger
1309 * @retval Returned value can be one of the following values:
1310 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE
1311 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT
1312 */
LL_PWR_GetRadioBusyTrigger(void)1313 __STATIC_INLINE uint32_t LL_PWR_GetRadioBusyTrigger(void)
1314 {
1315 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFBUSY));
1316 }
1317
1318 /**
1319 * @brief Set radio IRQ trigger action for CPU1: wake-up from low-power mode
1320 * Standby.
1321 * @rmtoll CR3 ERFIRQ LL_PWR_SetRadioIRQTrigger
1322 * @param RadioIRQTrigger This parameter can be one of the following values:
1323 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE
1324 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT
1325 * @retval None
1326 */
LL_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)1327 __STATIC_INLINE void LL_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)
1328 {
1329 MODIFY_REG(PWR->CR3, PWR_CR3_EWRFIRQ, RadioIRQTrigger);
1330 }
1331
1332 /**
1333 * @brief Get radio IRQ trigger action for CPU1: wake-up from low-power mode
1334 * Standby.
1335 * @rmtoll CR3 ERFIRQ LL_PWR_GetRadioIRQTrigger
1336 * @retval Returned value can be one of the following values:
1337 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE
1338 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT
1339 */
LL_PWR_GetRadioIRQTrigger(void)1340 __STATIC_INLINE uint32_t LL_PWR_GetRadioIRQTrigger(void)
1341 {
1342 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_EWRFIRQ));
1343 }
1344
1345 /**
1346 * @brief Set sub-GHz radio SPI NSS control source
1347 * @rmtoll CR1 SUBGHZSPINSSSEL LL_PWR_SetSUBGHZSPI_NSSSource
1348 * @param RadioSPI_NSSSource This parameter can be one of the following values:
1349 * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_SW
1350 * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3
1351 * @retval None
1352 */
LL_PWR_SetSUBGHZSPI_NSSSource(uint32_t RadioSPI_NSSSource)1353 __STATIC_INLINE void LL_PWR_SetSUBGHZSPI_NSSSource(uint32_t RadioSPI_NSSSource)
1354 {
1355 MODIFY_REG(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL, RadioSPI_NSSSource);
1356 }
1357
1358 /**
1359 * @brief Get sub-GHz radio SPI NSS control source
1360 * @rmtoll CR1 SUBGHZSPINSSSEL LL_PWR_GetSUBGHZSPI_NSSSource
1361 * @retval Returned value can be one of the following values:
1362 * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_SW
1363 * @arg @ref LL_PWR_SUBGHZSPI_NSS_SRC_LPTIM3
1364 */
LL_PWR_GetSUBGHZSPI_NSSSource(void)1365 __STATIC_INLINE uint32_t LL_PWR_GetSUBGHZSPI_NSSSource(void)
1366 {
1367 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SUBGHZSPINSSSEL));
1368 }
1369
1370 /**
1371 * @brief Set sub-GHz radio SPI NSS at logical level high.
1372 * @rmtoll SUBGHZSPICR NSS LL_PWR_UnselectSUBGHZSPI_NSS
1373 * @retval None
1374 */
LL_PWR_UnselectSUBGHZSPI_NSS(void)1375 __STATIC_INLINE void LL_PWR_UnselectSUBGHZSPI_NSS(void)
1376 {
1377 SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS);
1378 }
1379
1380 /**
1381 * @brief Set sub-GHz radio SPI NSS at logical level low.
1382 * @rmtoll SUBGHZSPICR NSS LL_PWR_SelectSUBGHZSPI_NSS
1383 * @retval None
1384 */
LL_PWR_SelectSUBGHZSPI_NSS(void)1385 __STATIC_INLINE void LL_PWR_SelectSUBGHZSPI_NSS(void)
1386 {
1387 CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS);
1388 }
1389
1390 /**
1391 * @brief Check whether sub-GHz radio SPI NSS is at logical level high or low.
1392 * @rmtoll SUBGHZSPICR NSS LL_PWR_IsSUBGHZSPI_NSS_Selected
1393 * @retval State of bit (1 for SUBGHZSPI_NSS selected or 0 for SUBGHZSPI_NSS unselected).
1394 */
LL_PWR_IsSUBGHZSPI_NSS_Selected(void)1395 __STATIC_INLINE uint32_t LL_PWR_IsSUBGHZSPI_NSS_Selected(void)
1396 {
1397 return ((READ_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS) != (PWR_SUBGHZSPICR_NSS)) ? 1UL : 0UL);
1398 }
1399
1400 /**
1401 * @}
1402 */
1403
1404 #if defined(DUAL_CORE)
1405 /** @defgroup PWR_LL_EF_Configuration_Radio_CPU2 Configuration of radio for CPU2
1406 * @{
1407 */
1408
1409 /**
1410 * @brief Set radio busy trigger action for CPU2: wake-up from low-power mode,
1411 * interruption.
1412 * @note Signal polarity can be configured using function
1413 * @ref LL_PWR_SetRadioBusyPolarity().
1414 * @rmtoll C2CR3 ERFBUSY LL_C2_PWR_SetRadioBusyTrigger
1415 * @param RadioBusyTrigger This parameter can be one of the following values:
1416 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE
1417 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT
1418 * @retval None
1419 */
LL_C2_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)1420 __STATIC_INLINE void LL_C2_PWR_SetRadioBusyTrigger(uint32_t RadioBusyTrigger)
1421 {
1422 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFBUSY, RadioBusyTrigger);
1423 }
1424
1425 /**
1426 * @brief Get radio busy trigger action for CPU2: wake-up from low-power mode,
1427 * interruption.
1428 * @rmtoll C2CR3 ERFBUSY LL_C2_PWR_GetRadioBusyTrigger
1429 * @retval Returned value can be one of the following values:
1430 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_NONE
1431 * @arg @ref LL_PWR_RADIO_BUSY_TRIGGER_WU_IT
1432 */
LL_C2_PWR_GetRadioBusyTrigger(void)1433 __STATIC_INLINE uint32_t LL_C2_PWR_GetRadioBusyTrigger(void)
1434 {
1435 /* Note: Bit shift performed for literals to be generic between CPU1 and CPU2 */
1436 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFBUSY));
1437 }
1438
1439 /**
1440 * @brief Set radio IRQ trigger action for CPU2: wake-up from low-power mode,
1441 * interruption.
1442 * @rmtoll C2CR3 ERFIRQ LL_C2_PWR_SetRadioIRQTrigger
1443 * @param RadioIRQTrigger This parameter can be one of the following values:
1444 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE
1445 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT
1446 * @retval None
1447 */
LL_C2_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)1448 __STATIC_INLINE void LL_C2_PWR_SetRadioIRQTrigger(uint32_t RadioIRQTrigger)
1449 {
1450 MODIFY_REG(PWR->C2CR3, PWR_C2CR3_EWRFIRQ, RadioIRQTrigger);
1451 }
1452
1453 /**
1454 * @brief Get radio IRQ trigger action for CPU2: wake-up from low-power mode,
1455 * interruption.
1456 * @rmtoll C2CR3 ERFIRQ LL_C2_PWR_GetRadioIRQTrigger
1457 * @retval Returned value can be one of the following values:
1458 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_NONE
1459 * @arg @ref LL_PWR_RADIO_IRQ_TRIGGER_WU_IT
1460 */
LL_C2_PWR_GetRadioIRQTrigger(void)1461 __STATIC_INLINE uint32_t LL_C2_PWR_GetRadioIRQTrigger(void)
1462 {
1463 return (uint32_t)(READ_BIT(PWR->C2CR3, PWR_C2CR3_EWRFIRQ));
1464 }
1465
1466 /**
1467 * @}
1468 */
1469
1470 /** @defgroup PWR_LL_EF_Configuration_Multicore Configuration of multicore, intended to be executed by CPU1
1471 * @{
1472 */
1473
1474 /**
1475 * @brief Boot CPU2 after reset or wakeup from Stop or Standby modes.
1476 * @note CPU2 can boot from configuration of this function or from
1477 * an illegal access. For information of boot source,
1478 * refer to function @ref LL_PWR_IsActiveFlag_C2BOOTS().
1479 * @rmtoll CR4 C2BOOT LL_PWR_EnableBootC2
1480 * @retval None
1481 */
LL_PWR_EnableBootC2(void)1482 __STATIC_INLINE void LL_PWR_EnableBootC2(void)
1483 {
1484 SET_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1485 }
1486
1487 /**
1488 * @brief Do not allow CPU2 to boot after reset or wakeup from Stop or Standby
1489 * modes.
1490 * @rmtoll CR4 C2BOOT LL_PWR_DisableBootC2
1491 * @retval None
1492 */
LL_PWR_DisableBootC2(void)1493 __STATIC_INLINE void LL_PWR_DisableBootC2(void)
1494 {
1495 CLEAR_BIT(PWR->CR4, PWR_CR4_C2BOOT);
1496 }
1497
1498 /**
1499 * @brief Check if bit to boot CPU2 after reset or wakeup from Stop or Standby
1500 * modes is set
1501 * @note CPU2 can boot from configuration of this function or from
1502 * an illegal access. For information of boot source,
1503 * refer to function @ref LL_PWR_IsActiveFlag_C2BOOTS().
1504 * @rmtoll CR4 C2BOOT LL_PWR_IsEnabledBootC2
1505 * @retval State of bit (1 or 0)
1506 */
LL_PWR_IsEnabledBootC2(void)1507 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void)
1508 {
1509 return ((READ_BIT(PWR->CR4, PWR_CR4_C2BOOT) == (PWR_CR4_C2BOOT)) ? 1UL : 0UL);
1510 }
1511
1512 /**
1513 * @}
1514 */
1515
1516 /** @defgroup PWR_LL_EF_Configuration_CPU2 Configuration of CPU2, intended to be executed by CPU2
1517 * @{
1518 */
1519
1520 /**
1521 * @brief Set Low-Power mode for CPU2
1522 * @rmtoll C2CR1 LPMS LL_C2_PWR_SetPowerMode
1523 * @param LowPowerMode This parameter can be one of the following values:
1524 * @arg @ref LL_PWR_MODE_STOP0
1525 * @arg @ref LL_PWR_MODE_STOP1
1526 * @arg @ref LL_PWR_MODE_STOP2
1527 * @arg @ref LL_PWR_MODE_STANDBY
1528 * @arg @ref LL_PWR_MODE_SHUTDOWN
1529 * @retval None
1530 */
LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)1531 __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
1532 {
1533 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, LowPowerMode);
1534 }
1535
1536 /**
1537 * @brief Get Low-Power mode for CPU2
1538 * @rmtoll C2CR1 LPMS LL_C2_PWR_GetPowerMode
1539 * @retval Returned value can be one of the following values:
1540 * @arg @ref LL_PWR_MODE_STOP0
1541 * @arg @ref LL_PWR_MODE_STOP1
1542 * @arg @ref LL_PWR_MODE_STOP2
1543 * @arg @ref LL_PWR_MODE_STANDBY
1544 * @arg @ref LL_PWR_MODE_SHUTDOWN
1545 */
LL_C2_PWR_GetPowerMode(void)1546 __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
1547 {
1548 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_LPMS));
1549 }
1550
1551 /**
1552 * @brief Set flash power-down mode during low-power run mode for CPU2
1553 * @rmtoll C2CR1 FPDR LL_C2_PWR_SetFlashPowerModeLPRun
1554 * @param FlashLowPowerMode This parameter can be one of the following values:
1555 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1556 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1557 * @retval None
1558 */
LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)1559 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
1560 {
1561 /* Unlock bit FPDR */
1562 WRITE_REG(PWR->C2CR1, PWR_FLASH_POWER_MODE_UNLOCK_CODE);
1563
1564 /* Update bit FPDR */
1565 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
1566 }
1567
1568 /**
1569 * @brief Get flash power-down mode during low-power run mode for CPU2
1570 * @rmtoll C2CR1 FPDR LL_C2_PWR_GetFlashPowerModeLPRun
1571 * @retval Returned value can be one of the following values:
1572 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_IDLE
1573 * @arg @ref LL_PWR_FLASH_LPRUN_MODE_POWER_DOWN
1574 */
LL_C2_PWR_GetFlashPowerModeLPRun(void)1575 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeLPRun(void)
1576 {
1577 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDR));
1578 }
1579
1580 /**
1581 * @brief Set flash power-down mode during sleep mode for CPU2
1582 * @rmtoll C2CR1 FPDS LL_C2_PWR_SetFlashPowerModeSleep
1583 * @param FlashLowPowerMode This parameter can be one of the following values:
1584 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1585 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1586 * @retval None
1587 */
LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)1588 __STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeSleep(uint32_t FlashLowPowerMode)
1589 {
1590 MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDS, FlashLowPowerMode);
1591 }
1592
1593 /**
1594 * @brief Get flash power-down mode during sleep mode for CPU2
1595 * @rmtoll C2CR1 FPDS LL_C2_PWR_GetFlashPowerModeSleep
1596 * @retval Returned value can be one of the following values:
1597 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_IDLE
1598 * @arg @ref LL_PWR_FLASH_SLEEP_MODE_POWER_DOWN
1599 */
LL_C2_PWR_GetFlashPowerModeSleep(void)1600 __STATIC_INLINE uint32_t LL_C2_PWR_GetFlashPowerModeSleep(void)
1601 {
1602 return (uint32_t)(READ_BIT(PWR->C2CR1, PWR_C2CR1_FPDS));
1603 }
1604
1605
1606 /**
1607 * @brief Enable Internal Wake-up line for CPU2
1608 * @rmtoll C2CR3 EIWUL LL_C2_PWR_EnableInternWU
1609 * @retval None
1610 */
LL_C2_PWR_EnableInternWU(void)1611 __STATIC_INLINE void LL_C2_PWR_EnableInternWU(void)
1612 {
1613 SET_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1614 }
1615
1616 /**
1617 * @brief Disable Internal Wake-up line for CPU2
1618 * @rmtoll C2CR3 EIWUL LL_C2_PWR_DisableInternWU
1619 * @retval None
1620 */
LL_C2_PWR_DisableInternWU(void)1621 __STATIC_INLINE void LL_C2_PWR_DisableInternWU(void)
1622 {
1623 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL);
1624 }
1625
1626 /**
1627 * @brief Check if Internal Wake-up line is enabled for CPU2
1628 * @rmtoll C2CR3 EIWUL LL_C2_PWR_IsEnabledInternWU
1629 * @retval State of bit (1 or 0).
1630 */
LL_C2_PWR_IsEnabledInternWU(void)1631 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void)
1632 {
1633 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EIWUL) == (PWR_C2CR3_EIWUL)) ? 1UL : 0UL);
1634 }
1635
1636 /**
1637 * @brief Enable the WakeUp PINx functionality
1638 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n
1639 * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n
1640 * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin
1641 * @param WakeUpPin This parameter can be one of the following values:
1642 * @arg @ref LL_PWR_WAKEUP_PIN1
1643 * @arg @ref LL_PWR_WAKEUP_PIN2
1644 * @arg @ref LL_PWR_WAKEUP_PIN3
1645 * @retval None
1646 */
LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)1647 __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1648 {
1649 SET_BIT(PWR->C2CR3, WakeUpPin);
1650 }
1651
1652 /**
1653 * @brief Disable the WakeUp PINx functionality
1654 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n
1655 * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n
1656 * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin
1657 * @param WakeUpPin This parameter can be one of the following values:
1658 * @arg @ref LL_PWR_WAKEUP_PIN1
1659 * @arg @ref LL_PWR_WAKEUP_PIN2
1660 * @arg @ref LL_PWR_WAKEUP_PIN3
1661 * @retval None
1662 */
LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)1663 __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1664 {
1665 CLEAR_BIT(PWR->C2CR3, WakeUpPin);
1666 }
1667
1668 /**
1669 * @brief Check if the WakeUp PINx functionality is enabled
1670 * @rmtoll C2CR3 EWUP1 LL_C2_PWR_EnableWakeUpPin\n
1671 * C2CR3 EWUP2 LL_C2_PWR_EnableWakeUpPin\n
1672 * C2CR3 EWUP3 LL_C2_PWR_EnableWakeUpPin
1673 * @param WakeUpPin This parameter can be one of the following values:
1674 * @arg @ref LL_PWR_WAKEUP_PIN1
1675 * @arg @ref LL_PWR_WAKEUP_PIN2
1676 * @arg @ref LL_PWR_WAKEUP_PIN3
1677 * @retval None
1678 */
LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)1679 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1680 {
1681 return ((READ_BIT(PWR->C2CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1682 }
1683
1684 /**
1685 * @brief Enable pull-up and pull-down configuration for CPU2
1686 * @rmtoll C2CR3 APC LL_C2_PWR_EnablePUPDCfg
1687 * @retval None
1688 */
LL_C2_PWR_EnablePUPDCfg(void)1689 __STATIC_INLINE void LL_C2_PWR_EnablePUPDCfg(void)
1690 {
1691 SET_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1692 }
1693
1694 /**
1695 * @brief Disable pull-up and pull-down configuration for CPU2
1696 * @rmtoll C2CR3 APC LL_C2_PWR_DisablePUPDCfg
1697 * @retval None
1698 */
LL_C2_PWR_DisablePUPDCfg(void)1699 __STATIC_INLINE void LL_C2_PWR_DisablePUPDCfg(void)
1700 {
1701 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_APC);
1702 }
1703
1704 /**
1705 * @brief Check if pull-up and pull-down configuration is enabled for CPU2
1706 * @rmtoll C2CR3 APC LL_C2_PWR_IsEnabledPUPDCfg
1707 * @retval State of bit (1 or 0).
1708 */
LL_C2_PWR_IsEnabledPUPDCfg(void)1709 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledPUPDCfg(void)
1710 {
1711 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_APC) == (PWR_C2CR3_APC)) ? 1UL : 0UL);
1712 }
1713
1714 /**
1715 * @brief Enable wake-up power voltage detection with trigger for CPU2
1716 * @note Wake-up power voltage detection status can be checked
1717 * using function @ref LL_PWR_IsActiveFlag_WPVD().
1718 * @rmtoll C2CR3 EWPVD LL_C2_PWR_EnableWPVD
1719 * @retval None
1720 */
LL_C2_PWR_EnableWPVD(void)1721 __STATIC_INLINE void LL_C2_PWR_EnableWPVD(void)
1722 {
1723 SET_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD);
1724 }
1725
1726 /**
1727 * @brief Disable wake-up power voltage detection with trigger for CPU2
1728 * @rmtoll C2CR3 EWPVD LL_C2_PWR_DisableWPVD
1729 * @retval None
1730 */
LL_C2_PWR_DisableWPVD(void)1731 __STATIC_INLINE void LL_C2_PWR_DisableWPVD(void)
1732 {
1733 CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD);
1734 }
1735
1736 /**
1737 * @brief Check if wake-up power voltage detection is enabled with trigger for CPU2
1738 * @rmtoll C2CR3 EWPVD LL_C2_PWR_IsEnabledWPVD
1739 * @retval State of bit (1 or 0).
1740 */
LL_C2_PWR_IsEnabledWPVD(void)1741 __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWPVD(void)
1742 {
1743 return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EWPVD) == (PWR_C2CR3_EWPVD)) ? 1UL : 0UL);
1744 }
1745
1746 /**
1747 * @brief Enable CPU2 wake-up from low-power mode on illegal access occurrence
1748 * @note Can be configured from CPU2 only
1749 * @rmtoll SECCFGR C2EWILA LL_PWR_C2_EnableWakeUp_ILAC
1750 * @retval None
1751 */
LL_PWR_C2_EnableWakeUp_ILAC(void)1752 __STATIC_INLINE void LL_PWR_C2_EnableWakeUp_ILAC(void)
1753 {
1754 SET_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA);
1755 }
1756
1757 /**
1758 * @brief Disable CPU2 wake-up from low-power mode on illegal access occurrence
1759 * @note Can be configured from CPU2 only
1760 * @rmtoll SECCFGR C2EWILA LL_PWR_C2_DisableWakeUp_ILAC
1761 * @retval None
1762 */
LL_PWR_C2_DisableWakeUp_ILAC(void)1763 __STATIC_INLINE void LL_PWR_C2_DisableWakeUp_ILAC(void)
1764 {
1765 CLEAR_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA);
1766 }
1767
1768 /**
1769 * @brief Check if bit to wake-up CPU2 from low-power mode on illegal access
1770 * occurrence is set
1771 * @note Can be used from CPU2 only
1772 * @rmtoll SECCFGR C2EWILA LL_PWR_C2_IsEnabledWakeUp_ILAC
1773 * @retval State of bit (1 or 0)
1774 */
LL_PWR_C2_IsEnabledWakeUp_ILAC(void)1775 __STATIC_INLINE uint32_t LL_PWR_C2_IsEnabledWakeUp_ILAC(void)
1776 {
1777 return ((READ_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA) == (PWR_SECCFGR_C2EWILA)) ? 1UL : 0UL);
1778 }
1779 #endif
1780
1781 /**
1782 * @}
1783 */
1784
1785 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1786 * @{
1787 */
1788
1789 /**
1790 * @brief Get Internal Wake-up line Flag
1791 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1792 * @retval State of bit (1 or 0).
1793 */
LL_PWR_IsActiveFlag_InternWU(void)1794 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1795 {
1796 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1797 }
1798
1799 /**
1800 * @brief Get Wake-up Flag 3
1801 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1802 * @retval State of bit (1 or 0).
1803 */
LL_PWR_IsActiveFlag_WU3(void)1804 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1805 {
1806 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Get Wake-up Flag 2
1811 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1812 * @retval State of bit (1 or 0).
1813 */
LL_PWR_IsActiveFlag_WU2(void)1814 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1815 {
1816 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1817 }
1818
1819 /**
1820 * @brief Get Wake-up Flag 1
1821 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1822 * @retval State of bit (1 or 0).
1823 */
LL_PWR_IsActiveFlag_WU1(void)1824 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1825 {
1826 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1827 }
1828
1829 /**
1830 * @brief Clear Wake-up Flags
1831 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1832 * @retval None
1833 */
LL_PWR_ClearFlag_WU(void)1834 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1835 {
1836 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1837 }
1838
1839 /**
1840 * @brief Clear Wake-up Flag 3
1841 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1842 * @retval None
1843 */
LL_PWR_ClearFlag_WU3(void)1844 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1845 {
1846 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1847 }
1848
1849 /**
1850 * @brief Clear Wake-up Flag 2
1851 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1852 * @retval None
1853 */
LL_PWR_ClearFlag_WU2(void)1854 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1855 {
1856 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1857 }
1858
1859 /**
1860 * @brief Clear Wake-up Flag 1
1861 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1862 * @retval None
1863 */
LL_PWR_ClearFlag_WU1(void)1864 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1865 {
1866 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1867 }
1868
1869 /**
1870 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1871 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1872 * @retval State of bit (1 or 0).
1873 */
LL_PWR_IsActiveFlag_PVMO3(void)1874 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1875 {
1876 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1877 }
1878
1879 /**
1880 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1881 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1882 * @retval State of bit (1 or 0).
1883 */
LL_PWR_IsActiveFlag_PVDO(void)1884 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1885 {
1886 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1887 }
1888
1889 /**
1890 * @brief Indicate whether supply voltage is below radio operating level.
1891 * @rmtoll SR2 RFEOLF LL_PWR_IsActiveFlag_RFEOL
1892 * @retval State of bit (1 or 0).
1893 */
LL_PWR_IsActiveFlag_RFEOL(void)1894 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFEOL(void)
1895 {
1896 return ((READ_BIT(PWR->SR2, PWR_SR2_RFEOLF) == (PWR_SR2_RFEOLF)) ? 1UL : 0UL);
1897 }
1898
1899 /**
1900 * @brief Indicate whether the regulator reached the selected voltage level
1901 * @note Regulator voltage level is selected using function
1902 * @ref LL_PWR_SetRegulVoltageScaling().
1903 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1904 * @retval State of bit (1 or 0).
1905 */
LL_PWR_IsActiveFlag_VOS(void)1906 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1907 {
1908 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1909 }
1910
1911 /**
1912 * @brief Get wake-up power voltage detection flag
1913 * @rmtoll SR1 WPVD LL_PWR_IsActiveFlag_WPVD
1914 * @retval State of bit (1 or 0).
1915 */
LL_PWR_IsActiveFlag_WPVD(void)1916 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WPVD(void)
1917 {
1918 return ((READ_BIT(PWR->SR1, PWR_SR1_WPVDF) == (PWR_SR1_WPVDF)) ? 1UL : 0UL);
1919 }
1920
1921 /**
1922 * @brief Clear wake-up power voltage detection flag
1923 * @rmtoll SCR CWPVD LL_PWR_ClearFlag_WPVD
1924 * @retval None
1925 */
LL_PWR_ClearFlag_WPVD(void)1926 __STATIC_INLINE void LL_PWR_ClearFlag_WPVD(void)
1927 {
1928 WRITE_REG(PWR->SCR, PWR_SCR_CWPVDF);
1929 }
1930
1931 /**
1932 * @brief Get main LDO ready flag
1933 * @rmtoll SR2 LDORDY LL_PWR_IsActiveFlag_LDORDY
1934 * @retval State of bit (1 or 0).
1935 */
LL_PWR_IsActiveFlag_LDORDY(void)1936 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_LDORDY(void)
1937 {
1938 return ((READ_BIT(PWR->SR2, PWR_SR2_LDORDY) == (PWR_SR2_LDORDY)) ? 1UL : 0UL);
1939 }
1940
1941 /**
1942 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1943 * @note Return value "0" means the main regulator is ready and used. Return value "1" means the low-power regulator is used.
1944 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1945 * @retval State of bit (1 or 0).
1946 */
LL_PWR_IsActiveFlag_REGLPF(void)1947 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1948 {
1949 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1950 }
1951
1952 /**
1953 * @brief Indicate whether the low-power regulator is ready after a power-on
1954 * reset, Standby or Shutdown mode.
1955 * @note If the Standby mode is entered while REGLPS bit is still
1956 * cleared (i.e. backup SRAM2 disabled), the wakeup time
1957 * from Standby mode may be increased.
1958 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1959 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1960 * @retval State of bit (1 or 0).
1961 */
LL_PWR_IsActiveFlag_REGLPS(void)1962 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1963 {
1964 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1965 }
1966
1967 /**
1968 * @brief Indicate whether the main regulator is supplied from the LDO or SMPS
1969 * or directly supplied from VDD.
1970 * @note Return value "0" for main regulator supplied directly from VDD, return value "1" for main regulator supplied directly from LDO or SMPS.
1971 * @rmtoll SR2 REGMRS LL_PWR_IsActiveFlag_REGMRS
1972 * @retval State of bit (1 or 0).
1973 */
LL_PWR_IsActiveFlag_REGMRS(void)1974 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGMRS(void)
1975 {
1976 return ((READ_BIT(PWR->SR2, PWR_SR2_REGMRS) == (PWR_SR2_REGMRS)) ? 1UL : 0UL);
1977 }
1978
1979 /**
1980 * @brief Indicate whether the flash memory is ready
1981 * @rmtoll SR2 FLASHRDY LL_PWR_IsActiveFlag_FLASHRDY
1982 * @retval State of bit (1 or 0).
1983 */
LL_PWR_IsActiveFlag_FLASHRDY(void)1984 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_FLASHRDY(void)
1985 {
1986 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASHRDY) == (PWR_SR2_FLASHRDY)) ? 1UL : 0UL);
1987 }
1988
1989 /**
1990 * @}
1991 */
1992
1993 /** @defgroup PWR_LL_EF_FLAG_Management_SMPS FLAG management for SMPS
1994 * @{
1995 */
1996
1997 /**
1998 * @brief Get SMPS ready flag
1999 * @rmtoll SR1 SMPSRDY LL_PWR_IsActiveFlag_SMPSRDY
2000 * @retval State of bit (1 or 0).
2001 */
LL_PWR_IsActiveFlag_SMPSRDY(void)2002 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSRDY(void)
2003 {
2004 return ((READ_BIT(PWR->SR2, PWR_SR2_SMPSRDY) == (PWR_SR2_SMPSRDY)) ? 1UL : 0UL);
2005 }
2006
2007 /**
2008 * @}
2009 */
2010
2011 /** @defgroup PWR_LL_EF_FLAG_Management_Radio FLAG management for radio
2012 * @{
2013 */
2014
2015 /**
2016 * @brief Get radio busy flag (triggered status: wake-up event
2017 * or interruption occurred at least once. Can be cleared by software).
2018 * @note This radio busy triggered status is based on radio busy masked
2019 * signal.
2020 * To get radio busy masked signal current status, use function
2021 * @ref LL_PWR_IsActiveFlag_RFBUSYMS()
2022 * @rmtoll SR1 RFBUSYF LL_PWR_IsActiveFlag_RFBUSY
2023 * @retval State of bit (1 or 0).
2024 */
LL_PWR_IsActiveFlag_RFBUSY(void)2025 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSY(void)
2026 {
2027 return ((READ_BIT(PWR->SR1, PWR_SR1_WRFBUSYF) == (PWR_SR1_WRFBUSYF)) ? 1UL : 0UL);
2028 }
2029
2030 /**
2031 * @brief Clear radio busy flag
2032 * @rmtoll SCR CRFBUSYF LL_PWR_ClearFlag_RFBUSY
2033 * @retval None
2034 */
LL_PWR_ClearFlag_RFBUSY(void)2035 __STATIC_INLINE void LL_PWR_ClearFlag_RFBUSY(void)
2036 {
2037 WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF);
2038 }
2039
2040 /**
2041 * @brief Get radio busy signal flag (current status:
2042 * set and cleared by hardware reflecting the real time signal level).
2043 * @note The get radio busy flag triggered status, use function
2044 * @ref LL_PWR_IsActiveFlag_RFBUSY()
2045 * @rmtoll SR2 RFBUSYS LL_PWR_IsActiveFlag_RFBUSYS
2046 * @retval State of bit (1 or 0).
2047 */
LL_PWR_IsActiveFlag_RFBUSYS(void)2048 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYS(void)
2049 {
2050 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL);
2051 }
2052
2053 /**
2054 * @brief Get radio busy masked signal flag (current status:
2055 * set and cleared by hardware reflecting the real time signal level).
2056 * @note The get radio busy flag triggered status, use function
2057 * @ref LL_PWR_IsActiveFlag_RFBUSY()
2058 * @rmtoll SR2 RFBUSYMS LL_PWR_IsActiveFlag_RFBUSYMS
2059 * @retval State of bit (1 or 0).
2060 */
LL_PWR_IsActiveFlag_RFBUSYMS(void)2061 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_RFBUSYMS(void)
2062 {
2063 return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL);
2064 }
2065
2066 /**
2067 * @}
2068 */
2069
2070 /** @defgroup PWR_LL_EF_FLAG_Management_Multicore FLAG management for multicore
2071 * @{
2072 */
2073
2074 #if defined(DUAL_CORE)
2075 /**
2076 * @brief Get CPU2 hold interrupt flag
2077 * @rmtoll SR1 C2HF LL_PWR_IsActiveFlag_C2H
2078 * @retval State of bit: 0 or 1 (CPU2 wake-up request and C2BOOT disabled,
2079 * (except for illegal access wake-up),
2080 * refer to function @ref LL_PWR_EnableBootC2()).
2081 */
LL_PWR_IsActiveFlag_C2H(void)2082 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2H(void)
2083 {
2084 return ((READ_BIT(PWR->SR1, PWR_SR1_C2HF) == (PWR_SR1_C2HF)) ? 1UL : 0UL);
2085 }
2086
2087 /**
2088 * @brief Get CPU2 boot or wake-up request source information
2089 * @rmtoll SR2 C2BOOTS LL_PWR_IsActiveFlag_C2BOOTS
2090 * @retval State of bit: 0 (boot from an illegal access event)
2091 * or 1 (boot from a SW request from function @ref LL_PWR_EnableBootC2()).
2092 */
LL_PWR_IsActiveFlag_C2BOOTS(void)2093 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2BOOTS(void)
2094 {
2095 return ((READ_BIT(PWR->SR2, PWR_SR2_C2BOOTS) == (PWR_SR2_C2BOOTS)) ? 1UL : 0UL);
2096 }
2097 #endif
2098
2099 /**
2100 * @brief Get system Stop 0 or Stop 1 flag for CPU1
2101 * @rmtoll EXTSCR C1STOPF LL_PWR_IsActiveFlag_C1STOP
2102 * @retval State of bit (1 or 0).
2103 */
LL_PWR_IsActiveFlag_C1STOP(void)2104 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP(void)
2105 {
2106 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOPF) == (PWR_EXTSCR_C1STOPF)) ? 1UL : 0UL);
2107 }
2108
2109 /**
2110 * @brief Get system Stop 2 flag for CPU1
2111 * @rmtoll EXTSCR C1STOP2F LL_PWR_IsActiveFlag_C1STOP2
2112 * @retval State of bit (1 or 0).
2113 */
LL_PWR_IsActiveFlag_C1STOP2(void)2114 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1STOP2(void)
2115 {
2116 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1STOP2F) == (PWR_EXTSCR_C1STOP2F)) ? 1UL : 0UL);
2117 }
2118
2119 /**
2120 * @brief Get system Standby flag for CPU1
2121 * @rmtoll EXTSCR C1SBF LL_PWR_IsActiveFlag_C1SB
2122 * @retval State of bit (1 or 0).
2123 */
LL_PWR_IsActiveFlag_C1SB(void)2124 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1SB(void)
2125 {
2126 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1SBF) == (PWR_EXTSCR_C1SBF)) ? 1UL : 0UL);
2127 }
2128
2129 /**
2130 * @brief Get deepsleep mode for CPU1
2131 * @rmtoll EXTSCR C1DS LL_PWR_IsActiveFlag_C1DS
2132 * @retval State of bit (1 or 0).
2133 */
LL_PWR_IsActiveFlag_C1DS(void)2134 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C1DS(void)
2135 {
2136 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C1DS) == (PWR_EXTSCR_C1DS)) ? 1UL : 0UL);
2137 }
2138
2139 #if defined(DUAL_CORE)
2140 /**
2141 * @brief System Stop 0 or Stop 1 flag for CPU2
2142 * @rmtoll EXTSCR C2STOPF LL_PWR_IsActiveFlag_C2STOP
2143 * @retval State of bit (1 or 0).
2144 */
LL_PWR_IsActiveFlag_C2STOP(void)2145 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP(void)
2146 {
2147 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOPF) == (PWR_EXTSCR_C2STOPF)) ? 1UL : 0UL);
2148 }
2149
2150 /**
2151 * @brief System Stop 2 flag for CPU2
2152 * @rmtoll EXTSCR C2STOP2F LL_PWR_IsActiveFlag_C2STOP2
2153 * @retval State of bit (1 or 0).
2154 */
LL_PWR_IsActiveFlag_C2STOP2(void)2155 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2STOP2(void)
2156 {
2157 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2STOP2F) == (PWR_EXTSCR_C2STOP2F)) ? 1UL : 0UL);
2158 }
2159
2160 /**
2161 * @brief System Standby flag for CPU2
2162 * @rmtoll EXTSCR C2SBF LL_PWR_IsActiveFlag_C2SB
2163 * @retval State of bit (1 or 0).
2164 */
LL_PWR_IsActiveFlag_C2SB(void)2165 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2SB(void)
2166 {
2167 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2SBF) == (PWR_EXTSCR_C2SBF)) ? 1UL : 0UL);
2168 }
2169
2170 /**
2171 * @brief Get deepsleep mode for CPU2
2172 * @rmtoll EXTSCR C2DS LL_PWR_IsActiveFlag_C2DS
2173 * @retval State of bit (1 or 0).
2174 */
LL_PWR_IsActiveFlag_C2DS(void)2175 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2DS(void)
2176 {
2177 return ((READ_BIT(PWR->EXTSCR, PWR_EXTSCR_C2DS) == (PWR_EXTSCR_C2DS)) ? 1UL : 0UL);
2178 }
2179
2180 /**
2181 * @brief Clear CPU2 hold interrupt flag
2182 * @rmtoll SCR CC2HF LL_PWR_ClearFlag_C2H
2183 * @retval None
2184 */
LL_PWR_ClearFlag_C2H(void)2185 __STATIC_INLINE void LL_PWR_ClearFlag_C2H(void)
2186 {
2187 WRITE_REG(PWR->SCR, PWR_SCR_CC2HF);
2188 }
2189 #endif
2190
2191 /**
2192 * @brief Clear standby and stop flags for CPU1
2193 * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB
2194 * @retval None
2195 */
LL_PWR_ClearFlag_C1STOP_C1STB(void)2196 __STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void)
2197 {
2198 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF);
2199 }
2200
2201 #if defined(DUAL_CORE)
2202 /**
2203 * @brief Clear standby and stop flags for CPU2
2204 * @rmtoll EXTSCR C2CSSF LL_PWR_ClearFlag_C2STOP_C2STB
2205 * @retval None
2206 */
LL_PWR_ClearFlag_C2STOP_C2STB(void)2207 __STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void)
2208 {
2209 WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF);
2210 }
2211 #endif
2212
2213 /**
2214 * @}
2215 */
2216
2217 #if defined(DUAL_CORE)
2218 /** @defgroup PWR_LL_EF_IT_Management_Multicore PWR IT management for multicore
2219 * @{
2220 */
2221
2222 /**
2223 * @brief Enable CPU2 hold interrupt for CPU1
2224 * @rmtoll CR3 EC2H LL_PWR_EnableIT_HoldCPU2
2225 * @retval None
2226 */
LL_PWR_EnableIT_HoldCPU2(void)2227 __STATIC_INLINE void LL_PWR_EnableIT_HoldCPU2(void)
2228 {
2229 SET_BIT(PWR->CR3, PWR_CR3_EC2H);
2230 }
2231
2232 /**
2233 * @brief Disable CPU2 hold interrupt for CPU1
2234 * @rmtoll CR3 EC2H LL_PWR_DisableIT_HoldCPU2
2235 * @retval None
2236 */
LL_PWR_DisableIT_HoldCPU2(void)2237 __STATIC_INLINE void LL_PWR_DisableIT_HoldCPU2(void)
2238 {
2239 CLEAR_BIT(PWR->CR3, PWR_CR3_EC2H);
2240 }
2241
2242 /**
2243 * @brief Check if CPU2 hold interrupt is enabled for CPU2
2244 * @rmtoll CR3 EC2H LL_PWR_IsEnabledIT_HoldCPU2
2245 * @retval State of bit (1 or 0).
2246 */
LL_PWR_IsEnabledIT_HoldCPU2(void)2247 __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void)
2248 {
2249 return ((READ_BIT(PWR->CR3, PWR_CR3_EC2H) == (PWR_CR3_EC2H)) ? 1UL : 0UL);
2250 }
2251
2252 /**
2253 * @}
2254 */
2255 #endif
2256
2257 #if defined(USE_FULL_LL_DRIVER)
2258 /** @defgroup PWR_LL_EF_Init De-initialization function
2259 * @{
2260 */
2261 ErrorStatus LL_PWR_DeInit(void);
2262 /**
2263 * @}
2264 */
2265 #endif /* USE_FULL_LL_DRIVER */
2266
2267 /**
2268 * @}
2269 */
2270
2271 /**
2272 * @}
2273 */
2274
2275 #endif /* defined(PWR) */
2276
2277 /**
2278 * @}
2279 */
2280
2281 #ifdef __cplusplus
2282 }
2283 #endif
2284
2285 #endif /* __STM32WLxx_LL_PWR_H */
2286
2287
