1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_lpuart.h
4 * @author MCD Application Team
5 * @brief Header file of LPUART LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_LPUART_H
21 #define STM32WLxx_LL_LPUART_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (LPUART1)
35
36 /** @defgroup LPUART_LL LPUART
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
43 * @{
44 */
45 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
46 static const uint16_t LPUART_PRESCALER_TAB[] =
47 {
48 (uint16_t)1,
49 (uint16_t)2,
50 (uint16_t)4,
51 (uint16_t)6,
52 (uint16_t)8,
53 (uint16_t)10,
54 (uint16_t)12,
55 (uint16_t)16,
56 (uint16_t)32,
57 (uint16_t)64,
58 (uint16_t)128,
59 (uint16_t)256
60 };
61 /**
62 * @}
63 */
64
65 /* Private constants ---------------------------------------------------------*/
66 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
67 * @{
68 */
69 /* Defines used in Baud Rate related macros and corresponding register setting computation */
70 #define LPUART_LPUARTDIV_FREQ_MUL 256U
71 #define LPUART_BRR_MASK 0x000FFFFFU
72 #define LPUART_BRR_MIN_VALUE 0x00000300U
73 /**
74 * @}
75 */
76
77
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
91 * @{
92 */
93
94 /**
95 * @brief LL LPUART Init Structure definition
96 */
97 typedef struct
98 {
99 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
100 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
101
102 This feature can be modified afterwards using unitary
103 function @ref LL_LPUART_SetPrescaler().*/
104
105 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
106
107 This feature can be modified afterwards using unitary
108 function @ref LL_LPUART_SetBaudRate().*/
109
110 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
111 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
112
113 This feature can be modified afterwards using unitary
114 function @ref LL_LPUART_SetDataWidth().*/
115
116 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
117 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
118
119 This feature can be modified afterwards using unitary
120 function @ref LL_LPUART_SetStopBitsLength().*/
121
122 uint32_t Parity; /*!< Specifies the parity mode.
123 This parameter can be a value of @ref LPUART_LL_EC_PARITY.
124
125 This feature can be modified afterwards using unitary
126 function @ref LL_LPUART_SetParity().*/
127
128 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
129 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
130
131 This feature can be modified afterwards using unitary
132 function @ref LL_LPUART_SetTransferDirection().*/
133
134 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
135 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
136
137 This feature can be modified afterwards using unitary
138 function @ref LL_LPUART_SetHWFlowCtrl().*/
139
140 } LL_LPUART_InitTypeDef;
141
142 /**
143 * @}
144 */
145 #endif /* USE_FULL_LL_DRIVER */
146
147 /* Exported constants --------------------------------------------------------*/
148 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
149 * @{
150 */
151
152 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
153 * @brief Flags defines which can be used with LL_LPUART_WriteReg function
154 * @{
155 */
156 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
157 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
158 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
159 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
160 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
161 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
162 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
163 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
164 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
165 /**
166 * @}
167 */
168
169 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
170 * @brief Flags defines which can be used with LL_LPUART_ReadReg function
171 * @{
172 */
173 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
174 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
175 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
176 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
177 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
178 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
179 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
180 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
181 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
182 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
183 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
184 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
185 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
186 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
187 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
188 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
189 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
190 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
191 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
192 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
193 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
194 /**
195 * @}
196 */
197
198 /** @defgroup LPUART_LL_EC_IT IT Defines
199 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
200 * @{
201 */
202 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
203 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
204 interrupt enable */
205 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
206 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
207 not full interrupt enable */
208 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
209 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
210 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
211 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
212 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
213 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
214 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
215 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
216 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
217 /**
218 * @}
219 */
220
221 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
222 * @{
223 */
224 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
225 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
226 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
227 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
228 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
229 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
230 /**
231 * @}
232 */
233
234 /** @defgroup LPUART_LL_EC_DIRECTION Direction
235 * @{
236 */
237 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
238 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
239 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
240 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
241 /**
242 * @}
243 */
244
245 /** @defgroup LPUART_LL_EC_PARITY Parity Control
246 * @{
247 */
248 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
249 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
250 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
251 /**
252 * @}
253 */
254
255 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup
256 * @{
257 */
258 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
259 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
260 /**
261 * @}
262 */
263
264 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
265 * @{
266 */
267 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
268 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
269 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
270 /**
271 * @}
272 */
273
274 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
275 * @{
276 */
277 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
278 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
279 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
280 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
281 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
282 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
283 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
284 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
285 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
286 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
287 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
288 USART_PRESC_PRESCALER_1 |\
289 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
290 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
291 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
292 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
293 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
294 USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
295 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
296 USART_PRESC_PRESCALER_1 |\
297 USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
298 /**
299 * @}
300 */
301
302 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
303 * @{
304 */
305 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
306 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
307 /**
308 * @}
309 */
310
311 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
312 * @{
313 */
314 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
315 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
316 /**
317 * @}
318 */
319
320 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
321 * @{
322 */
323 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
324 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
325 /**
326 * @}
327 */
328
329 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
330 * @{
331 */
332 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
333 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
334 /**
335 * @}
336 */
337
338 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
339 * @{
340 */
341 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
342 in positive/direct logic. (1=H, 0=L) */
343 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
344 in negative/inverse logic. (1=L, 0=H).
345 The parity bit is also inverted. */
346 /**
347 * @}
348 */
349
350 /** @defgroup LPUART_LL_EC_BITORDER Bit Order
351 * @{
352 */
353 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
354 following the start bit */
355 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
356 following the start bit */
357 /**
358 * @}
359 */
360
361 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
362 * @{
363 */
364 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
365 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
366 /**
367 * @}
368 */
369
370 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
371 * @{
372 */
373 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
374 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
375 when there is space in the receive buffer */
376 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
377 when the nCTS input is asserted (tied to 0)*/
378 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
379 /**
380 * @}
381 */
382
383 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
384 * @{
385 */
386 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
387 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
388 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
389 /**
390 * @}
391 */
392
393 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
394 * @{
395 */
396 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
397 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
398 /**
399 * @}
400 */
401
402 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
403 * @{
404 */
405 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
406 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
407 /**
408 * @}
409 */
410
411 /**
412 * @}
413 */
414
415 /* Exported macro ------------------------------------------------------------*/
416 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
417 * @{
418 */
419
420 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
421 * @{
422 */
423
424 /**
425 * @brief Write a value in LPUART register
426 * @param __INSTANCE__ LPUART Instance
427 * @param __REG__ Register to be written
428 * @param __VALUE__ Value to be written in the register
429 * @retval None
430 */
431 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
432
433 /**
434 * @brief Read a value in LPUART register
435 * @param __INSTANCE__ LPUART Instance
436 * @param __REG__ Register to be read
437 * @retval Register value
438 */
439 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
440 /**
441 * @}
442 */
443
444 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
445 * @{
446 */
447
448 /**
449 * @brief Compute LPUARTDIV value according to Peripheral Clock and
450 * expected Baud Rate (20-bit value of LPUARTDIV is returned)
451 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
452 * @param __PRESCALER__ This parameter can be one of the following values:
453 * @arg @ref LL_LPUART_PRESCALER_DIV1
454 * @arg @ref LL_LPUART_PRESCALER_DIV2
455 * @arg @ref LL_LPUART_PRESCALER_DIV4
456 * @arg @ref LL_LPUART_PRESCALER_DIV6
457 * @arg @ref LL_LPUART_PRESCALER_DIV8
458 * @arg @ref LL_LPUART_PRESCALER_DIV10
459 * @arg @ref LL_LPUART_PRESCALER_DIV12
460 * @arg @ref LL_LPUART_PRESCALER_DIV16
461 * @arg @ref LL_LPUART_PRESCALER_DIV32
462 * @arg @ref LL_LPUART_PRESCALER_DIV64
463 * @arg @ref LL_LPUART_PRESCALER_DIV128
464 * @arg @ref LL_LPUART_PRESCALER_DIV256
465 * @param __BAUDRATE__ Baud Rate value to achieve
466 * @retval LPUARTDIV value to be used for BRR register filling
467 */
468 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
469 ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
470 * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
471
472 /**
473 * @}
474 */
475
476 /**
477 * @}
478 */
479
480 /* Exported functions --------------------------------------------------------*/
481 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
482 * @{
483 */
484
485 /** @defgroup LPUART_LL_EF_Configuration Configuration functions
486 * @{
487 */
488
489 /**
490 * @brief LPUART Enable
491 * @rmtoll CR1 UE LL_LPUART_Enable
492 * @param LPUARTx LPUART Instance
493 * @retval None
494 */
LL_LPUART_Enable(USART_TypeDef * LPUARTx)495 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
496 {
497 SET_BIT(LPUARTx->CR1, USART_CR1_UE);
498 }
499
500 /**
501 * @brief LPUART Disable
502 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
503 * and current operations are discarded. The configuration of the LPUART is kept, but all the status
504 * flags, in the LPUARTx_ISR are set to their default values.
505 * @note In order to go into low-power mode without generating errors on the line,
506 * the TE bit must be reset before and the software must wait
507 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
508 * The DMA requests are also reset when UE = 0 so the DMA channel must
509 * be disabled before resetting the UE bit.
510 * @rmtoll CR1 UE LL_LPUART_Disable
511 * @param LPUARTx LPUART Instance
512 * @retval None
513 */
LL_LPUART_Disable(USART_TypeDef * LPUARTx)514 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
515 {
516 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
517 }
518
519 /**
520 * @brief Indicate if LPUART is enabled
521 * @rmtoll CR1 UE LL_LPUART_IsEnabled
522 * @param LPUARTx LPUART Instance
523 * @retval State of bit (1 or 0).
524 */
LL_LPUART_IsEnabled(const USART_TypeDef * LPUARTx)525 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
526 {
527 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
528 }
529
530 /**
531 * @brief FIFO Mode Enable
532 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
533 * @param LPUARTx LPUART Instance
534 * @retval None
535 */
LL_LPUART_EnableFIFO(USART_TypeDef * LPUARTx)536 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
537 {
538 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
539 }
540
541 /**
542 * @brief FIFO Mode Disable
543 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
544 * @param LPUARTx LPUART Instance
545 * @retval None
546 */
LL_LPUART_DisableFIFO(USART_TypeDef * LPUARTx)547 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
548 {
549 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
550 }
551
552 /**
553 * @brief Indicate if FIFO Mode is enabled
554 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
555 * @param LPUARTx LPUART Instance
556 * @retval State of bit (1 or 0).
557 */
LL_LPUART_IsEnabledFIFO(const USART_TypeDef * LPUARTx)558 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
559 {
560 return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
561 }
562
563 /**
564 * @brief Configure TX FIFO Threshold
565 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
566 * @param LPUARTx LPUART Instance
567 * @param Threshold This parameter can be one of the following values:
568 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
569 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
570 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
571 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
572 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
573 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
574 * @retval None
575 */
LL_LPUART_SetTXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)576 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
577 {
578 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
579 }
580
581 /**
582 * @brief Return TX FIFO Threshold Configuration
583 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
584 * @param LPUARTx LPUART Instance
585 * @retval Returned value can be one of the following values:
586 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
587 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
588 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
589 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
590 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
591 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
592 */
LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef * LPUARTx)593 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
594 {
595 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
596 }
597
598 /**
599 * @brief Configure RX FIFO Threshold
600 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
601 * @param LPUARTx LPUART Instance
602 * @param Threshold This parameter can be one of the following values:
603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
604 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
605 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
606 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
607 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
608 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
609 * @retval None
610 */
LL_LPUART_SetRXFIFOThreshold(USART_TypeDef * LPUARTx,uint32_t Threshold)611 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
612 {
613 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
614 }
615
616 /**
617 * @brief Return RX FIFO Threshold Configuration
618 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
619 * @param LPUARTx LPUART Instance
620 * @retval Returned value can be one of the following values:
621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
622 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
623 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
624 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
625 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
626 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
627 */
LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef * LPUARTx)628 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
629 {
630 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
631 }
632
633 /**
634 * @brief Configure TX and RX FIFOs Threshold
635 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
636 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
637 * @param LPUARTx LPUART Instance
638 * @param TXThreshold This parameter can be one of the following values:
639 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
640 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
641 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
642 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
643 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
644 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
645 * @param RXThreshold This parameter can be one of the following values:
646 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
647 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
648 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
649 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
650 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
651 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
652 * @retval None
653 */
LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef * LPUARTx,uint32_t TXThreshold,uint32_t RXThreshold)654 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
655 {
656 ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
657 (RXThreshold << USART_CR3_RXFTCFG_Pos));
658 }
659
660 /**
661 * @brief LPUART enabled in STOP Mode
662 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
663 * LPUART clock selection is HSI or LSE in RCC.
664 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
665 * @param LPUARTx LPUART Instance
666 * @retval None
667 */
LL_LPUART_EnableInStopMode(USART_TypeDef * LPUARTx)668 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
669 {
670 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
671 }
672
673 /**
674 * @brief LPUART disabled in STOP Mode
675 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
676 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
677 * @param LPUARTx LPUART Instance
678 * @retval None
679 */
LL_LPUART_DisableInStopMode(USART_TypeDef * LPUARTx)680 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
681 {
682 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
683 }
684
685 /**
686 * @brief Indicate if LPUART is enabled in STOP Mode
687 * (able to wake up MCU from Stop mode or not)
688 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
689 * @param LPUARTx LPUART Instance
690 * @retval State of bit (1 or 0).
691 */
LL_LPUART_IsEnabledInStopMode(const USART_TypeDef * LPUARTx)692 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
693 {
694 return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
695 }
696
697 /**
698 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
699 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
700 * @param LPUARTx LPUART Instance
701 * @retval None
702 */
LL_LPUART_EnableDirectionRx(USART_TypeDef * LPUARTx)703 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
704 {
705 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
706 }
707
708 /**
709 * @brief Receiver Disable
710 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
711 * @param LPUARTx LPUART Instance
712 * @retval None
713 */
LL_LPUART_DisableDirectionRx(USART_TypeDef * LPUARTx)714 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
715 {
716 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
717 }
718
719 /**
720 * @brief Transmitter Enable
721 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
722 * @param LPUARTx LPUART Instance
723 * @retval None
724 */
LL_LPUART_EnableDirectionTx(USART_TypeDef * LPUARTx)725 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
726 {
727 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
728 }
729
730 /**
731 * @brief Transmitter Disable
732 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
733 * @param LPUARTx LPUART Instance
734 * @retval None
735 */
LL_LPUART_DisableDirectionTx(USART_TypeDef * LPUARTx)736 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
737 {
738 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
739 }
740
741 /**
742 * @brief Configure simultaneously enabled/disabled states
743 * of Transmitter and Receiver
744 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
745 * CR1 TE LL_LPUART_SetTransferDirection
746 * @param LPUARTx LPUART Instance
747 * @param TransferDirection This parameter can be one of the following values:
748 * @arg @ref LL_LPUART_DIRECTION_NONE
749 * @arg @ref LL_LPUART_DIRECTION_RX
750 * @arg @ref LL_LPUART_DIRECTION_TX
751 * @arg @ref LL_LPUART_DIRECTION_TX_RX
752 * @retval None
753 */
LL_LPUART_SetTransferDirection(USART_TypeDef * LPUARTx,uint32_t TransferDirection)754 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
755 {
756 ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
757 }
758
759 /**
760 * @brief Return enabled/disabled states of Transmitter and Receiver
761 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
762 * CR1 TE LL_LPUART_GetTransferDirection
763 * @param LPUARTx LPUART Instance
764 * @retval Returned value can be one of the following values:
765 * @arg @ref LL_LPUART_DIRECTION_NONE
766 * @arg @ref LL_LPUART_DIRECTION_RX
767 * @arg @ref LL_LPUART_DIRECTION_TX
768 * @arg @ref LL_LPUART_DIRECTION_TX_RX
769 */
LL_LPUART_GetTransferDirection(const USART_TypeDef * LPUARTx)770 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
771 {
772 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
773 }
774
775 /**
776 * @brief Configure Parity (enabled/disabled and parity mode if enabled)
777 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
778 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
779 * (depending on data width) and parity is checked on the received data.
780 * @rmtoll CR1 PS LL_LPUART_SetParity\n
781 * CR1 PCE LL_LPUART_SetParity
782 * @param LPUARTx LPUART Instance
783 * @param Parity This parameter can be one of the following values:
784 * @arg @ref LL_LPUART_PARITY_NONE
785 * @arg @ref LL_LPUART_PARITY_EVEN
786 * @arg @ref LL_LPUART_PARITY_ODD
787 * @retval None
788 */
LL_LPUART_SetParity(USART_TypeDef * LPUARTx,uint32_t Parity)789 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
790 {
791 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
792 }
793
794 /**
795 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
796 * @rmtoll CR1 PS LL_LPUART_GetParity\n
797 * CR1 PCE LL_LPUART_GetParity
798 * @param LPUARTx LPUART Instance
799 * @retval Returned value can be one of the following values:
800 * @arg @ref LL_LPUART_PARITY_NONE
801 * @arg @ref LL_LPUART_PARITY_EVEN
802 * @arg @ref LL_LPUART_PARITY_ODD
803 */
LL_LPUART_GetParity(const USART_TypeDef * LPUARTx)804 __STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
805 {
806 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
807 }
808
809 /**
810 * @brief Set Receiver Wake Up method from Mute mode.
811 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
812 * @param LPUARTx LPUART Instance
813 * @param Method This parameter can be one of the following values:
814 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
815 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
816 * @retval None
817 */
LL_LPUART_SetWakeUpMethod(USART_TypeDef * LPUARTx,uint32_t Method)818 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
819 {
820 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
821 }
822
823 /**
824 * @brief Return Receiver Wake Up method from Mute mode
825 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
826 * @param LPUARTx LPUART Instance
827 * @retval Returned value can be one of the following values:
828 * @arg @ref LL_LPUART_WAKEUP_IDLELINE
829 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
830 */
LL_LPUART_GetWakeUpMethod(const USART_TypeDef * LPUARTx)831 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
832 {
833 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
834 }
835
836 /**
837 * @brief Set Word length (nb of data bits, excluding start and stop bits)
838 * @rmtoll CR1 M LL_LPUART_SetDataWidth
839 * @param LPUARTx LPUART Instance
840 * @param DataWidth This parameter can be one of the following values:
841 * @arg @ref LL_LPUART_DATAWIDTH_7B
842 * @arg @ref LL_LPUART_DATAWIDTH_8B
843 * @arg @ref LL_LPUART_DATAWIDTH_9B
844 * @retval None
845 */
LL_LPUART_SetDataWidth(USART_TypeDef * LPUARTx,uint32_t DataWidth)846 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
847 {
848 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
849 }
850
851 /**
852 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
853 * @rmtoll CR1 M LL_LPUART_GetDataWidth
854 * @param LPUARTx LPUART Instance
855 * @retval Returned value can be one of the following values:
856 * @arg @ref LL_LPUART_DATAWIDTH_7B
857 * @arg @ref LL_LPUART_DATAWIDTH_8B
858 * @arg @ref LL_LPUART_DATAWIDTH_9B
859 */
LL_LPUART_GetDataWidth(const USART_TypeDef * LPUARTx)860 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
861 {
862 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
863 }
864
865 /**
866 * @brief Allow switch between Mute Mode and Active mode
867 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode
868 * @param LPUARTx LPUART Instance
869 * @retval None
870 */
LL_LPUART_EnableMuteMode(USART_TypeDef * LPUARTx)871 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
872 {
873 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
874 }
875
876 /**
877 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
878 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode
879 * @param LPUARTx LPUART Instance
880 * @retval None
881 */
LL_LPUART_DisableMuteMode(USART_TypeDef * LPUARTx)882 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
883 {
884 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
885 }
886
887 /**
888 * @brief Indicate if switch between Mute Mode and Active mode is allowed
889 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
890 * @param LPUARTx LPUART Instance
891 * @retval State of bit (1 or 0).
892 */
LL_LPUART_IsEnabledMuteMode(const USART_TypeDef * LPUARTx)893 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
894 {
895 return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
896 }
897
898 /**
899 * @brief Configure Clock source prescaler for baudrate generator and oversampling
900 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
901 * @param LPUARTx LPUART Instance
902 * @param PrescalerValue This parameter can be one of the following values:
903 * @arg @ref LL_LPUART_PRESCALER_DIV1
904 * @arg @ref LL_LPUART_PRESCALER_DIV2
905 * @arg @ref LL_LPUART_PRESCALER_DIV4
906 * @arg @ref LL_LPUART_PRESCALER_DIV6
907 * @arg @ref LL_LPUART_PRESCALER_DIV8
908 * @arg @ref LL_LPUART_PRESCALER_DIV10
909 * @arg @ref LL_LPUART_PRESCALER_DIV12
910 * @arg @ref LL_LPUART_PRESCALER_DIV16
911 * @arg @ref LL_LPUART_PRESCALER_DIV32
912 * @arg @ref LL_LPUART_PRESCALER_DIV64
913 * @arg @ref LL_LPUART_PRESCALER_DIV128
914 * @arg @ref LL_LPUART_PRESCALER_DIV256
915 * @retval None
916 */
LL_LPUART_SetPrescaler(USART_TypeDef * LPUARTx,uint32_t PrescalerValue)917 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
918 {
919 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
920 }
921
922 /**
923 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
924 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
925 * @param LPUARTx LPUART Instance
926 * @retval Returned value can be one of the following values:
927 * @arg @ref LL_LPUART_PRESCALER_DIV1
928 * @arg @ref LL_LPUART_PRESCALER_DIV2
929 * @arg @ref LL_LPUART_PRESCALER_DIV4
930 * @arg @ref LL_LPUART_PRESCALER_DIV6
931 * @arg @ref LL_LPUART_PRESCALER_DIV8
932 * @arg @ref LL_LPUART_PRESCALER_DIV10
933 * @arg @ref LL_LPUART_PRESCALER_DIV12
934 * @arg @ref LL_LPUART_PRESCALER_DIV16
935 * @arg @ref LL_LPUART_PRESCALER_DIV32
936 * @arg @ref LL_LPUART_PRESCALER_DIV64
937 * @arg @ref LL_LPUART_PRESCALER_DIV128
938 * @arg @ref LL_LPUART_PRESCALER_DIV256
939 */
LL_LPUART_GetPrescaler(const USART_TypeDef * LPUARTx)940 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
941 {
942 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
943 }
944
945 /**
946 * @brief Set the length of the stop bits
947 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
948 * @param LPUARTx LPUART Instance
949 * @param StopBits This parameter can be one of the following values:
950 * @arg @ref LL_LPUART_STOPBITS_1
951 * @arg @ref LL_LPUART_STOPBITS_2
952 * @retval None
953 */
LL_LPUART_SetStopBitsLength(USART_TypeDef * LPUARTx,uint32_t StopBits)954 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
955 {
956 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
957 }
958
959 /**
960 * @brief Retrieve the length of the stop bits
961 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
962 * @param LPUARTx LPUART Instance
963 * @retval Returned value can be one of the following values:
964 * @arg @ref LL_LPUART_STOPBITS_1
965 * @arg @ref LL_LPUART_STOPBITS_2
966 */
LL_LPUART_GetStopBitsLength(const USART_TypeDef * LPUARTx)967 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
968 {
969 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
970 }
971
972 /**
973 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
974 * @note Call of this function is equivalent to following function call sequence :
975 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
976 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
977 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
978 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
979 * CR1 PCE LL_LPUART_ConfigCharacter\n
980 * CR1 M LL_LPUART_ConfigCharacter\n
981 * CR2 STOP LL_LPUART_ConfigCharacter
982 * @param LPUARTx LPUART Instance
983 * @param DataWidth This parameter can be one of the following values:
984 * @arg @ref LL_LPUART_DATAWIDTH_7B
985 * @arg @ref LL_LPUART_DATAWIDTH_8B
986 * @arg @ref LL_LPUART_DATAWIDTH_9B
987 * @param Parity This parameter can be one of the following values:
988 * @arg @ref LL_LPUART_PARITY_NONE
989 * @arg @ref LL_LPUART_PARITY_EVEN
990 * @arg @ref LL_LPUART_PARITY_ODD
991 * @param StopBits This parameter can be one of the following values:
992 * @arg @ref LL_LPUART_STOPBITS_1
993 * @arg @ref LL_LPUART_STOPBITS_2
994 * @retval None
995 */
LL_LPUART_ConfigCharacter(USART_TypeDef * LPUARTx,uint32_t DataWidth,uint32_t Parity,uint32_t StopBits)996 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
997 uint32_t StopBits)
998 {
999 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
1000 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
1001 }
1002
1003 /**
1004 * @brief Configure TX/RX pins swapping setting.
1005 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
1006 * @param LPUARTx LPUART Instance
1007 * @param SwapConfig This parameter can be one of the following values:
1008 * @arg @ref LL_LPUART_TXRX_STANDARD
1009 * @arg @ref LL_LPUART_TXRX_SWAPPED
1010 * @retval None
1011 */
LL_LPUART_SetTXRXSwap(USART_TypeDef * LPUARTx,uint32_t SwapConfig)1012 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
1013 {
1014 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
1015 }
1016
1017 /**
1018 * @brief Retrieve TX/RX pins swapping configuration.
1019 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
1020 * @param LPUARTx LPUART Instance
1021 * @retval Returned value can be one of the following values:
1022 * @arg @ref LL_LPUART_TXRX_STANDARD
1023 * @arg @ref LL_LPUART_TXRX_SWAPPED
1024 */
LL_LPUART_GetTXRXSwap(const USART_TypeDef * LPUARTx)1025 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
1026 {
1027 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
1028 }
1029
1030 /**
1031 * @brief Configure RX pin active level logic
1032 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
1033 * @param LPUARTx LPUART Instance
1034 * @param PinInvMethod This parameter can be one of the following values:
1035 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1036 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1037 * @retval None
1038 */
LL_LPUART_SetRXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1039 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1040 {
1041 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
1042 }
1043
1044 /**
1045 * @brief Retrieve RX pin active level logic configuration
1046 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
1047 * @param LPUARTx LPUART Instance
1048 * @retval Returned value can be one of the following values:
1049 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
1050 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
1051 */
LL_LPUART_GetRXPinLevel(const USART_TypeDef * LPUARTx)1052 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
1053 {
1054 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
1055 }
1056
1057 /**
1058 * @brief Configure TX pin active level logic
1059 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
1060 * @param LPUARTx LPUART Instance
1061 * @param PinInvMethod This parameter can be one of the following values:
1062 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1063 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1064 * @retval None
1065 */
LL_LPUART_SetTXPinLevel(USART_TypeDef * LPUARTx,uint32_t PinInvMethod)1066 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
1067 {
1068 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
1069 }
1070
1071 /**
1072 * @brief Retrieve TX pin active level logic configuration
1073 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
1074 * @param LPUARTx LPUART Instance
1075 * @retval Returned value can be one of the following values:
1076 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
1077 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
1078 */
LL_LPUART_GetTXPinLevel(const USART_TypeDef * LPUARTx)1079 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
1080 {
1081 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
1082 }
1083
1084 /**
1085 * @brief Configure Binary data logic.
1086 *
1087 * @note Allow to define how Logical data from the data register are send/received :
1088 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
1089 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
1090 * @param LPUARTx LPUART Instance
1091 * @param DataLogic This parameter can be one of the following values:
1092 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1093 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1094 * @retval None
1095 */
LL_LPUART_SetBinaryDataLogic(USART_TypeDef * LPUARTx,uint32_t DataLogic)1096 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
1097 {
1098 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
1099 }
1100
1101 /**
1102 * @brief Retrieve Binary data configuration
1103 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
1104 * @param LPUARTx LPUART Instance
1105 * @retval Returned value can be one of the following values:
1106 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
1107 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
1108 */
LL_LPUART_GetBinaryDataLogic(const USART_TypeDef * LPUARTx)1109 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
1110 {
1111 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
1112 }
1113
1114 /**
1115 * @brief Configure transfer bit order (either Less or Most Significant Bit First)
1116 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1117 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1118 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
1119 * @param LPUARTx LPUART Instance
1120 * @param BitOrder This parameter can be one of the following values:
1121 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1122 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1123 * @retval None
1124 */
LL_LPUART_SetTransferBitOrder(USART_TypeDef * LPUARTx,uint32_t BitOrder)1125 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
1126 {
1127 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
1128 }
1129
1130 /**
1131 * @brief Return transfer bit order (either Less or Most Significant Bit First)
1132 * @note MSB First means data is transmitted/received with the MSB first, following the start bit.
1133 * LSB First means data is transmitted/received with data bit 0 first, following the start bit.
1134 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
1135 * @param LPUARTx LPUART Instance
1136 * @retval Returned value can be one of the following values:
1137 * @arg @ref LL_LPUART_BITORDER_LSBFIRST
1138 * @arg @ref LL_LPUART_BITORDER_MSBFIRST
1139 */
LL_LPUART_GetTransferBitOrder(const USART_TypeDef * LPUARTx)1140 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
1141 {
1142 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
1143 }
1144
1145 /**
1146 * @brief Set Address of the LPUART node.
1147 * @note This is used in multiprocessor communication during Mute mode or Stop mode,
1148 * for wake up with address mark detection.
1149 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
1150 * (b7-b4 should be set to 0)
1151 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
1152 * (This is used in multiprocessor communication during Mute mode or Stop mode,
1153 * for wake up with 7-bit address mark detection.
1154 * The MSB of the character sent by the transmitter should be equal to 1.
1155 * It may also be used for character detection during normal reception,
1156 * Mute mode inactive (for example, end of block detection in ModBus protocol).
1157 * In this case, the whole received character (8-bit) is compared to the ADD[7:0]
1158 * value and CMF flag is set on match)
1159 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
1160 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress
1161 * @param LPUARTx LPUART Instance
1162 * @param AddressLen This parameter can be one of the following values:
1163 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1164 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1165 * @param NodeAddress 4 or 7 bit Address of the LPUART node.
1166 * @retval None
1167 */
LL_LPUART_ConfigNodeAddress(USART_TypeDef * LPUARTx,uint32_t AddressLen,uint32_t NodeAddress)1168 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
1169 {
1170 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
1171 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
1172 }
1173
1174 /**
1175 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
1176 * @note If 4-bit Address Detection is selected in ADDM7,
1177 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
1178 * If 7-bit Address Detection is selected in ADDM7,
1179 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
1180 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
1181 * @param LPUARTx LPUART Instance
1182 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
1183 */
LL_LPUART_GetNodeAddress(const USART_TypeDef * LPUARTx)1184 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
1185 {
1186 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
1187 }
1188
1189 /**
1190 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
1191 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
1192 * @param LPUARTx LPUART Instance
1193 * @retval Returned value can be one of the following values:
1194 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B
1195 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B
1196 */
LL_LPUART_GetNodeAddressLen(const USART_TypeDef * LPUARTx)1197 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
1198 {
1199 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
1200 }
1201
1202 /**
1203 * @brief Enable RTS HW Flow Control
1204 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
1205 * @param LPUARTx LPUART Instance
1206 * @retval None
1207 */
LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1208 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1209 {
1210 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1211 }
1212
1213 /**
1214 * @brief Disable RTS HW Flow Control
1215 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
1216 * @param LPUARTx LPUART Instance
1217 * @retval None
1218 */
LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef * LPUARTx)1219 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1220 {
1221 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
1222 }
1223
1224 /**
1225 * @brief Enable CTS HW Flow Control
1226 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
1227 * @param LPUARTx LPUART Instance
1228 * @retval None
1229 */
LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1230 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1231 {
1232 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1233 }
1234
1235 /**
1236 * @brief Disable CTS HW Flow Control
1237 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
1238 * @param LPUARTx LPUART Instance
1239 * @retval None
1240 */
LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef * LPUARTx)1241 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
1242 {
1243 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
1244 }
1245
1246 /**
1247 * @brief Configure HW Flow Control mode (both CTS and RTS)
1248 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
1249 * CR3 CTSE LL_LPUART_SetHWFlowCtrl
1250 * @param LPUARTx LPUART Instance
1251 * @param HardwareFlowControl This parameter can be one of the following values:
1252 * @arg @ref LL_LPUART_HWCONTROL_NONE
1253 * @arg @ref LL_LPUART_HWCONTROL_RTS
1254 * @arg @ref LL_LPUART_HWCONTROL_CTS
1255 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1256 * @retval None
1257 */
LL_LPUART_SetHWFlowCtrl(USART_TypeDef * LPUARTx,uint32_t HardwareFlowControl)1258 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
1259 {
1260 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
1261 }
1262
1263 /**
1264 * @brief Return HW Flow Control configuration (both CTS and RTS)
1265 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
1266 * CR3 CTSE LL_LPUART_GetHWFlowCtrl
1267 * @param LPUARTx LPUART Instance
1268 * @retval Returned value can be one of the following values:
1269 * @arg @ref LL_LPUART_HWCONTROL_NONE
1270 * @arg @ref LL_LPUART_HWCONTROL_RTS
1271 * @arg @ref LL_LPUART_HWCONTROL_CTS
1272 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
1273 */
LL_LPUART_GetHWFlowCtrl(const USART_TypeDef * LPUARTx)1274 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
1275 {
1276 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
1277 }
1278
1279 /**
1280 * @brief Enable Overrun detection
1281 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
1282 * @param LPUARTx LPUART Instance
1283 * @retval None
1284 */
LL_LPUART_EnableOverrunDetect(USART_TypeDef * LPUARTx)1285 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
1286 {
1287 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1288 }
1289
1290 /**
1291 * @brief Disable Overrun detection
1292 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
1293 * @param LPUARTx LPUART Instance
1294 * @retval None
1295 */
LL_LPUART_DisableOverrunDetect(USART_TypeDef * LPUARTx)1296 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
1297 {
1298 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
1299 }
1300
1301 /**
1302 * @brief Indicate if Overrun detection is enabled
1303 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
1304 * @param LPUARTx LPUART Instance
1305 * @retval State of bit (1 or 0).
1306 */
LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef * LPUARTx)1307 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
1308 {
1309 return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
1310 }
1311
1312 /**
1313 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1314 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType
1315 * @param LPUARTx LPUART Instance
1316 * @param Type This parameter can be one of the following values:
1317 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1318 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1319 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1320 * @retval None
1321 */
LL_LPUART_SetWKUPType(USART_TypeDef * LPUARTx,uint32_t Type)1322 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
1323 {
1324 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
1325 }
1326
1327 /**
1328 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
1329 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType
1330 * @param LPUARTx LPUART Instance
1331 * @retval Returned value can be one of the following values:
1332 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
1333 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
1334 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE
1335 */
LL_LPUART_GetWKUPType(const USART_TypeDef * LPUARTx)1336 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
1337 {
1338 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
1339 }
1340
1341 /**
1342 * @brief Configure LPUART BRR register for achieving expected Baud Rate value.
1343 *
1344 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
1345 * according to used Peripheral Clock and expected Baud Rate values
1346 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid
1347 * (Baud rate value != 0).
1348 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
1349 * a care should be taken when generating high baud rates using high PeriphClk
1350 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
1351 * @rmtoll BRR BRR LL_LPUART_SetBaudRate
1352 * @param LPUARTx LPUART Instance
1353 * @param PeriphClk Peripheral Clock
1354 * @param PrescalerValue This parameter can be one of the following values:
1355 * @arg @ref LL_LPUART_PRESCALER_DIV1
1356 * @arg @ref LL_LPUART_PRESCALER_DIV2
1357 * @arg @ref LL_LPUART_PRESCALER_DIV4
1358 * @arg @ref LL_LPUART_PRESCALER_DIV6
1359 * @arg @ref LL_LPUART_PRESCALER_DIV8
1360 * @arg @ref LL_LPUART_PRESCALER_DIV10
1361 * @arg @ref LL_LPUART_PRESCALER_DIV12
1362 * @arg @ref LL_LPUART_PRESCALER_DIV16
1363 * @arg @ref LL_LPUART_PRESCALER_DIV32
1364 * @arg @ref LL_LPUART_PRESCALER_DIV64
1365 * @arg @ref LL_LPUART_PRESCALER_DIV128
1366 * @arg @ref LL_LPUART_PRESCALER_DIV256
1367 * @param BaudRate Baud Rate
1368 * @retval None
1369 */
LL_LPUART_SetBaudRate(USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue,uint32_t BaudRate)1370 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
1371 uint32_t BaudRate)
1372 {
1373 if (BaudRate != 0U)
1374 {
1375 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
1376 }
1377 }
1378
1379 /**
1380 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
1381 * (full BRR content), and to used Peripheral Clock values
1382 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
1383 * @rmtoll BRR BRR LL_LPUART_GetBaudRate
1384 * @param LPUARTx LPUART Instance
1385 * @param PeriphClk Peripheral Clock
1386 * @param PrescalerValue This parameter can be one of the following values:
1387 * @arg @ref LL_LPUART_PRESCALER_DIV1
1388 * @arg @ref LL_LPUART_PRESCALER_DIV2
1389 * @arg @ref LL_LPUART_PRESCALER_DIV4
1390 * @arg @ref LL_LPUART_PRESCALER_DIV6
1391 * @arg @ref LL_LPUART_PRESCALER_DIV8
1392 * @arg @ref LL_LPUART_PRESCALER_DIV10
1393 * @arg @ref LL_LPUART_PRESCALER_DIV12
1394 * @arg @ref LL_LPUART_PRESCALER_DIV16
1395 * @arg @ref LL_LPUART_PRESCALER_DIV32
1396 * @arg @ref LL_LPUART_PRESCALER_DIV64
1397 * @arg @ref LL_LPUART_PRESCALER_DIV128
1398 * @arg @ref LL_LPUART_PRESCALER_DIV256
1399 * @retval Baud Rate
1400 */
LL_LPUART_GetBaudRate(const USART_TypeDef * LPUARTx,uint32_t PeriphClk,uint32_t PrescalerValue)1401 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
1402 uint32_t PrescalerValue)
1403 {
1404 uint32_t lpuartdiv;
1405 uint32_t brrresult;
1406 uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
1407
1408 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
1409
1410 if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
1411 {
1412 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
1413 }
1414 else
1415 {
1416 brrresult = 0x0UL;
1417 }
1418
1419 return (brrresult);
1420 }
1421
1422 /**
1423 * @}
1424 */
1425
1426 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
1427 * @{
1428 */
1429
1430 /**
1431 * @brief Enable Single Wire Half-Duplex mode
1432 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
1433 * @param LPUARTx LPUART Instance
1434 * @retval None
1435 */
LL_LPUART_EnableHalfDuplex(USART_TypeDef * LPUARTx)1436 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
1437 {
1438 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1439 }
1440
1441 /**
1442 * @brief Disable Single Wire Half-Duplex mode
1443 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
1444 * @param LPUARTx LPUART Instance
1445 * @retval None
1446 */
LL_LPUART_DisableHalfDuplex(USART_TypeDef * LPUARTx)1447 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
1448 {
1449 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
1450 }
1451
1452 /**
1453 * @brief Indicate if Single Wire Half-Duplex mode is enabled
1454 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
1455 * @param LPUARTx LPUART Instance
1456 * @retval State of bit (1 or 0).
1457 */
LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef * LPUARTx)1458 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
1459 {
1460 return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
1461 }
1462
1463 /**
1464 * @}
1465 */
1466
1467 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
1468 * @{
1469 */
1470
1471 /**
1472 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1473 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
1474 * @param LPUARTx LPUART Instance
1475 * @param Time Value between Min_Data=0 and Max_Data=31
1476 * @retval None
1477 */
LL_LPUART_SetDEDeassertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1478 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1479 {
1480 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
1481 }
1482
1483 /**
1484 * @brief Return DEDT (Driver Enable De-Assertion Time)
1485 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
1486 * @param LPUARTx LPUART Instance
1487 * @retval Time value expressed on 5 bits ([4:0] bits) : c
1488 */
LL_LPUART_GetDEDeassertionTime(const USART_TypeDef * LPUARTx)1489 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
1490 {
1491 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
1492 }
1493
1494 /**
1495 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
1496 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
1497 * @param LPUARTx LPUART Instance
1498 * @param Time Value between Min_Data=0 and Max_Data=31
1499 * @retval None
1500 */
LL_LPUART_SetDEAssertionTime(USART_TypeDef * LPUARTx,uint32_t Time)1501 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
1502 {
1503 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
1504 }
1505
1506 /**
1507 * @brief Return DEAT (Driver Enable Assertion Time)
1508 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
1509 * @param LPUARTx LPUART Instance
1510 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
1511 */
LL_LPUART_GetDEAssertionTime(const USART_TypeDef * LPUARTx)1512 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
1513 {
1514 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
1515 }
1516
1517 /**
1518 * @brief Enable Driver Enable (DE) Mode
1519 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode
1520 * @param LPUARTx LPUART Instance
1521 * @retval None
1522 */
LL_LPUART_EnableDEMode(USART_TypeDef * LPUARTx)1523 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
1524 {
1525 SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
1526 }
1527
1528 /**
1529 * @brief Disable Driver Enable (DE) Mode
1530 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode
1531 * @param LPUARTx LPUART Instance
1532 * @retval None
1533 */
LL_LPUART_DisableDEMode(USART_TypeDef * LPUARTx)1534 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
1535 {
1536 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
1537 }
1538
1539 /**
1540 * @brief Indicate if Driver Enable (DE) Mode is enabled
1541 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
1542 * @param LPUARTx LPUART Instance
1543 * @retval State of bit (1 or 0).
1544 */
LL_LPUART_IsEnabledDEMode(const USART_TypeDef * LPUARTx)1545 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
1546 {
1547 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Select Driver Enable Polarity
1552 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
1553 * @param LPUARTx LPUART Instance
1554 * @param Polarity This parameter can be one of the following values:
1555 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1556 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1557 * @retval None
1558 */
LL_LPUART_SetDESignalPolarity(USART_TypeDef * LPUARTx,uint32_t Polarity)1559 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
1560 {
1561 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
1562 }
1563
1564 /**
1565 * @brief Return Driver Enable Polarity
1566 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
1567 * @param LPUARTx LPUART Instance
1568 * @retval Returned value can be one of the following values:
1569 * @arg @ref LL_LPUART_DE_POLARITY_HIGH
1570 * @arg @ref LL_LPUART_DE_POLARITY_LOW
1571 */
LL_LPUART_GetDESignalPolarity(const USART_TypeDef * LPUARTx)1572 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
1573 {
1574 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
1575 }
1576
1577 /**
1578 * @}
1579 */
1580
1581 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
1582 * @{
1583 */
1584
1585 /**
1586 * @brief Check if the LPUART Parity Error Flag is set or not
1587 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
1588 * @param LPUARTx LPUART Instance
1589 * @retval State of bit (1 or 0).
1590 */
LL_LPUART_IsActiveFlag_PE(const USART_TypeDef * LPUARTx)1591 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
1592 {
1593 return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Check if the LPUART Framing Error Flag is set or not
1598 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
1599 * @param LPUARTx LPUART Instance
1600 * @retval State of bit (1 or 0).
1601 */
LL_LPUART_IsActiveFlag_FE(const USART_TypeDef * LPUARTx)1602 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
1603 {
1604 return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief Check if the LPUART Noise error detected Flag is set or not
1609 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
1610 * @param LPUARTx LPUART Instance
1611 * @retval State of bit (1 or 0).
1612 */
LL_LPUART_IsActiveFlag_NE(const USART_TypeDef * LPUARTx)1613 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
1614 {
1615 return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
1616 }
1617
1618 /**
1619 * @brief Check if the LPUART OverRun Error Flag is set or not
1620 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
1621 * @param LPUARTx LPUART Instance
1622 * @retval State of bit (1 or 0).
1623 */
LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef * LPUARTx)1624 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
1625 {
1626 return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @brief Check if the LPUART IDLE line detected Flag is set or not
1631 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
1632 * @param LPUARTx LPUART Instance
1633 * @retval State of bit (1 or 0).
1634 */
LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef * LPUARTx)1635 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
1636 {
1637 return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
1638 }
1639
1640 /* Legacy define */
1641 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1642
1643 /**
1644 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
1645 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
1646 * @param LPUARTx LPUART Instance
1647 * @retval State of bit (1 or 0).
1648 */
LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef * LPUARTx)1649 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
1650 {
1651 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
1652 }
1653
1654 /**
1655 * @brief Check if the LPUART Transmission Complete Flag is set or not
1656 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
1657 * @param LPUARTx LPUART Instance
1658 * @retval State of bit (1 or 0).
1659 */
LL_LPUART_IsActiveFlag_TC(const USART_TypeDef * LPUARTx)1660 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
1661 {
1662 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
1663 }
1664
1665 /* Legacy define */
1666 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
1667
1668 /**
1669 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
1670 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
1671 * @param LPUARTx LPUART Instance
1672 * @retval State of bit (1 or 0).
1673 */
LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef * LPUARTx)1674 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
1675 {
1676 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
1677 }
1678
1679 /**
1680 * @brief Check if the LPUART CTS interrupt Flag is set or not
1681 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
1682 * @param LPUARTx LPUART Instance
1683 * @retval State of bit (1 or 0).
1684 */
LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef * LPUARTx)1685 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
1686 {
1687 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
1688 }
1689
1690 /**
1691 * @brief Check if the LPUART CTS Flag is set or not
1692 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
1693 * @param LPUARTx LPUART Instance
1694 * @retval State of bit (1 or 0).
1695 */
LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef * LPUARTx)1696 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
1697 {
1698 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
1699 }
1700
1701 /**
1702 * @brief Check if the LPUART Busy Flag is set or not
1703 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
1704 * @param LPUARTx LPUART Instance
1705 * @retval State of bit (1 or 0).
1706 */
LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef * LPUARTx)1707 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
1708 {
1709 return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
1710 }
1711
1712 /**
1713 * @brief Check if the LPUART Character Match Flag is set or not
1714 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
1715 * @param LPUARTx LPUART Instance
1716 * @retval State of bit (1 or 0).
1717 */
LL_LPUART_IsActiveFlag_CM(const USART_TypeDef * LPUARTx)1718 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
1719 {
1720 return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
1721 }
1722
1723 /**
1724 * @brief Check if the LPUART Send Break Flag is set or not
1725 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
1726 * @param LPUARTx LPUART Instance
1727 * @retval State of bit (1 or 0).
1728 */
LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef * LPUARTx)1729 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
1730 {
1731 return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
1732 }
1733
1734 /**
1735 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
1736 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
1737 * @param LPUARTx LPUART Instance
1738 * @retval State of bit (1 or 0).
1739 */
LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef * LPUARTx)1740 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
1741 {
1742 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
1743 }
1744
1745 /**
1746 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not
1747 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
1748 * @param LPUARTx LPUART Instance
1749 * @retval State of bit (1 or 0).
1750 */
LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef * LPUARTx)1751 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
1752 {
1753 return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
1754 }
1755
1756 /**
1757 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
1758 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
1759 * @param LPUARTx LPUART Instance
1760 * @retval State of bit (1 or 0).
1761 */
LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef * LPUARTx)1762 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
1763 {
1764 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
1765 }
1766
1767 /**
1768 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
1769 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
1770 * @param LPUARTx LPUART Instance
1771 * @retval State of bit (1 or 0).
1772 */
LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef * LPUARTx)1773 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
1774 {
1775 return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
1776 }
1777
1778 /**
1779 * @brief Check if the LPUART TX FIFO Empty Flag is set or not
1780 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
1781 * @param LPUARTx LPUART Instance
1782 * @retval State of bit (1 or 0).
1783 */
LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef * LPUARTx)1784 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
1785 {
1786 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
1787 }
1788
1789 /**
1790 * @brief Check if the LPUART RX FIFO Full Flag is set or not
1791 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
1792 * @param LPUARTx LPUART Instance
1793 * @retval State of bit (1 or 0).
1794 */
LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef * LPUARTx)1795 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
1796 {
1797 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
1798 }
1799
1800 /**
1801 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not
1802 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
1803 * @param LPUARTx LPUART Instance
1804 * @retval State of bit (1 or 0).
1805 */
LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef * LPUARTx)1806 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
1807 {
1808 return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
1809 }
1810
1811 /**
1812 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not
1813 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
1814 * @param LPUARTx LPUART Instance
1815 * @retval State of bit (1 or 0).
1816 */
LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef * LPUARTx)1817 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
1818 {
1819 return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
1820 }
1821
1822 /**
1823 * @brief Clear Parity Error Flag
1824 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
1825 * @param LPUARTx LPUART Instance
1826 * @retval None
1827 */
LL_LPUART_ClearFlag_PE(USART_TypeDef * LPUARTx)1828 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
1829 {
1830 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
1831 }
1832
1833 /**
1834 * @brief Clear Framing Error Flag
1835 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
1836 * @param LPUARTx LPUART Instance
1837 * @retval None
1838 */
LL_LPUART_ClearFlag_FE(USART_TypeDef * LPUARTx)1839 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
1840 {
1841 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
1842 }
1843
1844 /**
1845 * @brief Clear Noise detected Flag
1846 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
1847 * @param LPUARTx LPUART Instance
1848 * @retval None
1849 */
LL_LPUART_ClearFlag_NE(USART_TypeDef * LPUARTx)1850 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
1851 {
1852 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
1853 }
1854
1855 /**
1856 * @brief Clear OverRun Error Flag
1857 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
1858 * @param LPUARTx LPUART Instance
1859 * @retval None
1860 */
LL_LPUART_ClearFlag_ORE(USART_TypeDef * LPUARTx)1861 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
1862 {
1863 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
1864 }
1865
1866 /**
1867 * @brief Clear IDLE line detected Flag
1868 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
1869 * @param LPUARTx LPUART Instance
1870 * @retval None
1871 */
LL_LPUART_ClearFlag_IDLE(USART_TypeDef * LPUARTx)1872 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
1873 {
1874 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
1875 }
1876
1877 /**
1878 * @brief Clear Transmission Complete Flag
1879 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
1880 * @param LPUARTx LPUART Instance
1881 * @retval None
1882 */
LL_LPUART_ClearFlag_TC(USART_TypeDef * LPUARTx)1883 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
1884 {
1885 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
1886 }
1887
1888 /**
1889 * @brief Clear CTS Interrupt Flag
1890 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
1891 * @param LPUARTx LPUART Instance
1892 * @retval None
1893 */
LL_LPUART_ClearFlag_nCTS(USART_TypeDef * LPUARTx)1894 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
1895 {
1896 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
1897 }
1898
1899 /**
1900 * @brief Clear Character Match Flag
1901 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
1902 * @param LPUARTx LPUART Instance
1903 * @retval None
1904 */
LL_LPUART_ClearFlag_CM(USART_TypeDef * LPUARTx)1905 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
1906 {
1907 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
1908 }
1909
1910 /**
1911 * @brief Clear Wake Up from stop mode Flag
1912 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
1913 * @param LPUARTx LPUART Instance
1914 * @retval None
1915 */
LL_LPUART_ClearFlag_WKUP(USART_TypeDef * LPUARTx)1916 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
1917 {
1918 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
1919 }
1920
1921 /**
1922 * @}
1923 */
1924
1925 /** @defgroup LPUART_LL_EF_IT_Management IT_Management
1926 * @{
1927 */
1928
1929 /**
1930 * @brief Enable IDLE Interrupt
1931 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
1932 * @param LPUARTx LPUART Instance
1933 * @retval None
1934 */
LL_LPUART_EnableIT_IDLE(USART_TypeDef * LPUARTx)1935 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
1936 {
1937 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
1938 }
1939
1940 /* Legacy define */
1941 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
1942
1943 /**
1944 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
1945 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
1946 * @param LPUARTx LPUART Instance
1947 * @retval None
1948 */
LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)1949 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
1950 {
1951 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
1952 }
1953
1954 /**
1955 * @brief Enable Transmission Complete Interrupt
1956 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
1957 * @param LPUARTx LPUART Instance
1958 * @retval None
1959 */
LL_LPUART_EnableIT_TC(USART_TypeDef * LPUARTx)1960 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
1961 {
1962 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
1963 }
1964
1965 /* Legacy define */
1966 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
1967
1968 /**
1969 * @brief Enable TX Empty and TX FIFO Not Full Interrupt
1970 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
1971 * @param LPUARTx LPUART Instance
1972 * @retval None
1973 */
LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)1974 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
1975 {
1976 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
1977 }
1978
1979 /**
1980 * @brief Enable Parity Error Interrupt
1981 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
1982 * @param LPUARTx LPUART Instance
1983 * @retval None
1984 */
LL_LPUART_EnableIT_PE(USART_TypeDef * LPUARTx)1985 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
1986 {
1987 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
1988 }
1989
1990 /**
1991 * @brief Enable Character Match Interrupt
1992 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
1993 * @param LPUARTx LPUART Instance
1994 * @retval None
1995 */
LL_LPUART_EnableIT_CM(USART_TypeDef * LPUARTx)1996 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
1997 {
1998 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
1999 }
2000
2001 /**
2002 * @brief Enable TX FIFO Empty Interrupt
2003 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
2004 * @param LPUARTx LPUART Instance
2005 * @retval None
2006 */
LL_LPUART_EnableIT_TXFE(USART_TypeDef * LPUARTx)2007 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
2008 {
2009 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2010 }
2011
2012 /**
2013 * @brief Enable RX FIFO Full Interrupt
2014 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
2015 * @param LPUARTx LPUART Instance
2016 * @retval None
2017 */
LL_LPUART_EnableIT_RXFF(USART_TypeDef * LPUARTx)2018 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
2019 {
2020 ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2021 }
2022
2023 /**
2024 * @brief Enable Error Interrupt
2025 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2026 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2027 * - 0: Interrupt is inhibited
2028 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2029 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
2030 * @param LPUARTx LPUART Instance
2031 * @retval None
2032 */
LL_LPUART_EnableIT_ERROR(USART_TypeDef * LPUARTx)2033 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
2034 {
2035 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
2036 }
2037
2038 /**
2039 * @brief Enable CTS Interrupt
2040 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
2041 * @param LPUARTx LPUART Instance
2042 * @retval None
2043 */
LL_LPUART_EnableIT_CTS(USART_TypeDef * LPUARTx)2044 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
2045 {
2046 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2047 }
2048
2049 /**
2050 * @brief Enable Wake Up from Stop Mode Interrupt
2051 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
2052 * @param LPUARTx LPUART Instance
2053 * @retval None
2054 */
LL_LPUART_EnableIT_WKUP(USART_TypeDef * LPUARTx)2055 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
2056 {
2057 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2058 }
2059
2060 /**
2061 * @brief Enable TX FIFO Threshold Interrupt
2062 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
2063 * @param LPUARTx LPUART Instance
2064 * @retval None
2065 */
LL_LPUART_EnableIT_TXFT(USART_TypeDef * LPUARTx)2066 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
2067 {
2068 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2069 }
2070
2071 /**
2072 * @brief Enable RX FIFO Threshold Interrupt
2073 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
2074 * @param LPUARTx LPUART Instance
2075 * @retval None
2076 */
LL_LPUART_EnableIT_RXFT(USART_TypeDef * LPUARTx)2077 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
2078 {
2079 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2080 }
2081
2082 /**
2083 * @brief Disable IDLE Interrupt
2084 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
2085 * @param LPUARTx LPUART Instance
2086 * @retval None
2087 */
LL_LPUART_DisableIT_IDLE(USART_TypeDef * LPUARTx)2088 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
2089 {
2090 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
2091 }
2092
2093 /* Legacy define */
2094 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
2095
2096 /**
2097 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
2098 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
2099 * @param LPUARTx LPUART Instance
2100 * @retval None
2101 */
LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef * LPUARTx)2102 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
2103 {
2104 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
2105 }
2106
2107 /**
2108 * @brief Disable Transmission Complete Interrupt
2109 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
2110 * @param LPUARTx LPUART Instance
2111 * @retval None
2112 */
LL_LPUART_DisableIT_TC(USART_TypeDef * LPUARTx)2113 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
2114 {
2115 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
2116 }
2117
2118 /* Legacy define */
2119 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
2120
2121 /**
2122 * @brief Disable TX Empty and TX FIFO Not Full Interrupt
2123 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
2124 * @param LPUARTx LPUART Instance
2125 * @retval None
2126 */
LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef * LPUARTx)2127 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
2128 {
2129 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
2130 }
2131
2132 /**
2133 * @brief Disable Parity Error Interrupt
2134 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
2135 * @param LPUARTx LPUART Instance
2136 * @retval None
2137 */
LL_LPUART_DisableIT_PE(USART_TypeDef * LPUARTx)2138 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
2139 {
2140 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
2141 }
2142
2143 /**
2144 * @brief Disable Character Match Interrupt
2145 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
2146 * @param LPUARTx LPUART Instance
2147 * @retval None
2148 */
LL_LPUART_DisableIT_CM(USART_TypeDef * LPUARTx)2149 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
2150 {
2151 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
2152 }
2153
2154 /**
2155 * @brief Disable TX FIFO Empty Interrupt
2156 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
2157 * @param LPUARTx LPUART Instance
2158 * @retval None
2159 */
LL_LPUART_DisableIT_TXFE(USART_TypeDef * LPUARTx)2160 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
2161 {
2162 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
2163 }
2164
2165 /**
2166 * @brief Disable RX FIFO Full Interrupt
2167 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
2168 * @param LPUARTx LPUART Instance
2169 * @retval None
2170 */
LL_LPUART_DisableIT_RXFF(USART_TypeDef * LPUARTx)2171 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
2172 {
2173 ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
2174 }
2175
2176 /**
2177 * @brief Disable Error Interrupt
2178 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
2179 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
2180 * - 0: Interrupt is inhibited
2181 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
2182 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
2183 * @param LPUARTx LPUART Instance
2184 * @retval None
2185 */
LL_LPUART_DisableIT_ERROR(USART_TypeDef * LPUARTx)2186 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
2187 {
2188 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
2189 }
2190
2191 /**
2192 * @brief Disable CTS Interrupt
2193 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
2194 * @param LPUARTx LPUART Instance
2195 * @retval None
2196 */
LL_LPUART_DisableIT_CTS(USART_TypeDef * LPUARTx)2197 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
2198 {
2199 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
2200 }
2201
2202 /**
2203 * @brief Disable Wake Up from Stop Mode Interrupt
2204 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
2205 * @param LPUARTx LPUART Instance
2206 * @retval None
2207 */
LL_LPUART_DisableIT_WKUP(USART_TypeDef * LPUARTx)2208 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
2209 {
2210 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
2211 }
2212
2213 /**
2214 * @brief Disable TX FIFO Threshold Interrupt
2215 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
2216 * @param LPUARTx LPUART Instance
2217 * @retval None
2218 */
LL_LPUART_DisableIT_TXFT(USART_TypeDef * LPUARTx)2219 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
2220 {
2221 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
2222 }
2223
2224 /**
2225 * @brief Disable RX FIFO Threshold Interrupt
2226 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
2227 * @param LPUARTx LPUART Instance
2228 * @retval None
2229 */
LL_LPUART_DisableIT_RXFT(USART_TypeDef * LPUARTx)2230 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
2231 {
2232 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
2233 }
2234
2235 /**
2236 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
2237 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
2238 * @param LPUARTx LPUART Instance
2239 * @retval State of bit (1 or 0).
2240 */
LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef * LPUARTx)2241 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
2242 {
2243 return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
2244 }
2245
2246 /* Legacy define */
2247 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2248
2249 /**
2250 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
2251 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
2252 * @param LPUARTx LPUART Instance
2253 * @retval State of bit (1 or 0).
2254 */
LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef * LPUARTx)2255 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
2256 {
2257 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
2258 }
2259
2260 /**
2261 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
2262 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
2263 * @param LPUARTx LPUART Instance
2264 * @retval State of bit (1 or 0).
2265 */
LL_LPUART_IsEnabledIT_TC(const USART_TypeDef * LPUARTx)2266 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
2267 {
2268 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
2269 }
2270
2271 /* Legacy define */
2272 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
2273
2274 /**
2275 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
2276 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
2277 * @param LPUARTx LPUART Instance
2278 * @retval State of bit (1 or 0).
2279 */
LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef * LPUARTx)2280 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
2281 {
2282 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
2283 }
2284
2285 /**
2286 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
2287 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
2288 * @param LPUARTx LPUART Instance
2289 * @retval State of bit (1 or 0).
2290 */
LL_LPUART_IsEnabledIT_PE(const USART_TypeDef * LPUARTx)2291 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
2292 {
2293 return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
2294 }
2295
2296 /**
2297 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
2298 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
2299 * @param LPUARTx LPUART Instance
2300 * @retval State of bit (1 or 0).
2301 */
LL_LPUART_IsEnabledIT_CM(const USART_TypeDef * LPUARTx)2302 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
2303 {
2304 return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
2305 }
2306
2307 /**
2308 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
2309 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
2310 * @param LPUARTx LPUART Instance
2311 * @retval State of bit (1 or 0).
2312 */
LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef * LPUARTx)2313 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
2314 {
2315 return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
2316 }
2317
2318 /**
2319 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
2320 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
2321 * @param LPUARTx LPUART Instance
2322 * @retval State of bit (1 or 0).
2323 */
LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef * LPUARTx)2324 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
2325 {
2326 return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
2327 }
2328
2329 /**
2330 * @brief Check if the LPUART Error Interrupt is enabled or disabled.
2331 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
2332 * @param LPUARTx LPUART Instance
2333 * @retval State of bit (1 or 0).
2334 */
LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef * LPUARTx)2335 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
2336 {
2337 return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
2338 }
2339
2340 /**
2341 * @brief Check if the LPUART CTS Interrupt is enabled or disabled.
2342 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
2343 * @param LPUARTx LPUART Instance
2344 * @retval State of bit (1 or 0).
2345 */
LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef * LPUARTx)2346 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
2347 {
2348 return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
2349 }
2350
2351 /**
2352 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
2353 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
2354 * @param LPUARTx LPUART Instance
2355 * @retval State of bit (1 or 0).
2356 */
LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef * LPUARTx)2357 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
2358 {
2359 return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
2360 }
2361
2362 /**
2363 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
2364 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
2365 * @param LPUARTx LPUART Instance
2366 * @retval State of bit (1 or 0).
2367 */
LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef * LPUARTx)2368 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
2369 {
2370 return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
2371 }
2372
2373 /**
2374 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
2375 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
2376 * @param LPUARTx LPUART Instance
2377 * @retval State of bit (1 or 0).
2378 */
LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef * LPUARTx)2379 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
2380 {
2381 return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
2382 }
2383
2384 /**
2385 * @}
2386 */
2387
2388 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
2389 * @{
2390 */
2391
2392 /**
2393 * @brief Enable DMA Mode for reception
2394 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
2395 * @param LPUARTx LPUART Instance
2396 * @retval None
2397 */
LL_LPUART_EnableDMAReq_RX(USART_TypeDef * LPUARTx)2398 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
2399 {
2400 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2401 }
2402
2403 /**
2404 * @brief Disable DMA Mode for reception
2405 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
2406 * @param LPUARTx LPUART Instance
2407 * @retval None
2408 */
LL_LPUART_DisableDMAReq_RX(USART_TypeDef * LPUARTx)2409 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
2410 {
2411 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
2412 }
2413
2414 /**
2415 * @brief Check if DMA Mode is enabled for reception
2416 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
2417 * @param LPUARTx LPUART Instance
2418 * @retval State of bit (1 or 0).
2419 */
LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef * LPUARTx)2420 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
2421 {
2422 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
2423 }
2424
2425 /**
2426 * @brief Enable DMA Mode for transmission
2427 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
2428 * @param LPUARTx LPUART Instance
2429 * @retval None
2430 */
LL_LPUART_EnableDMAReq_TX(USART_TypeDef * LPUARTx)2431 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
2432 {
2433 ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2434 }
2435
2436 /**
2437 * @brief Disable DMA Mode for transmission
2438 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
2439 * @param LPUARTx LPUART Instance
2440 * @retval None
2441 */
LL_LPUART_DisableDMAReq_TX(USART_TypeDef * LPUARTx)2442 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
2443 {
2444 ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
2445 }
2446
2447 /**
2448 * @brief Check if DMA Mode is enabled for transmission
2449 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
2450 * @param LPUARTx LPUART Instance
2451 * @retval State of bit (1 or 0).
2452 */
LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef * LPUARTx)2453 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
2454 {
2455 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
2456 }
2457
2458 /**
2459 * @brief Enable DMA Disabling on Reception Error
2460 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
2461 * @param LPUARTx LPUART Instance
2462 * @retval None
2463 */
LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2464 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2465 {
2466 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2467 }
2468
2469 /**
2470 * @brief Disable DMA Disabling on Reception Error
2471 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
2472 * @param LPUARTx LPUART Instance
2473 * @retval None
2474 */
LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef * LPUARTx)2475 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
2476 {
2477 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
2478 }
2479
2480 /**
2481 * @brief Indicate if DMA Disabling on Reception Error is disabled
2482 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
2483 * @param LPUARTx LPUART Instance
2484 * @retval State of bit (1 or 0).
2485 */
LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef * LPUARTx)2486 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
2487 {
2488 return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
2489 }
2490
2491 /**
2492 * @brief Get the LPUART data register address used for DMA transfer
2493 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
2494 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
2495 * @param LPUARTx LPUART Instance
2496 * @param Direction This parameter can be one of the following values:
2497 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
2498 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
2499 * @retval Address of data register
2500 */
LL_LPUART_DMA_GetRegAddr(const USART_TypeDef * LPUARTx,uint32_t Direction)2501 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
2502 {
2503 uint32_t data_reg_addr;
2504
2505 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
2506 {
2507 /* return address of TDR register */
2508 data_reg_addr = (uint32_t) &(LPUARTx->TDR);
2509 }
2510 else
2511 {
2512 /* return address of RDR register */
2513 data_reg_addr = (uint32_t) &(LPUARTx->RDR);
2514 }
2515
2516 return data_reg_addr;
2517 }
2518
2519 /**
2520 * @}
2521 */
2522
2523 /** @defgroup LPUART_LL_EF_Data_Management Data_Management
2524 * @{
2525 */
2526
2527 /**
2528 * @brief Read Receiver Data register (Receive Data value, 8 bits)
2529 * @rmtoll RDR RDR LL_LPUART_ReceiveData8
2530 * @param LPUARTx LPUART Instance
2531 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
2532 */
LL_LPUART_ReceiveData8(const USART_TypeDef * LPUARTx)2533 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
2534 {
2535 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
2536 }
2537
2538 /**
2539 * @brief Read Receiver Data register (Receive Data value, 9 bits)
2540 * @rmtoll RDR RDR LL_LPUART_ReceiveData9
2541 * @param LPUARTx LPUART Instance
2542 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
2543 */
LL_LPUART_ReceiveData9(const USART_TypeDef * LPUARTx)2544 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
2545 {
2546 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
2547 }
2548
2549 /**
2550 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
2551 * @rmtoll TDR TDR LL_LPUART_TransmitData8
2552 * @param LPUARTx LPUART Instance
2553 * @param Value between Min_Data=0x00 and Max_Data=0xFF
2554 * @retval None
2555 */
LL_LPUART_TransmitData8(USART_TypeDef * LPUARTx,uint8_t Value)2556 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
2557 {
2558 LPUARTx->TDR = Value;
2559 }
2560
2561 /**
2562 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
2563 * @rmtoll TDR TDR LL_LPUART_TransmitData9
2564 * @param LPUARTx LPUART Instance
2565 * @param Value between Min_Data=0x00 and Max_Data=0x1FF
2566 * @retval None
2567 */
LL_LPUART_TransmitData9(USART_TypeDef * LPUARTx,uint16_t Value)2568 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
2569 {
2570 LPUARTx->TDR = Value & 0x1FFUL;
2571 }
2572
2573 /**
2574 * @}
2575 */
2576
2577 /** @defgroup LPUART_LL_EF_Execution Execution
2578 * @{
2579 */
2580
2581 /**
2582 * @brief Request Break sending
2583 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
2584 * @param LPUARTx LPUART Instance
2585 * @retval None
2586 */
LL_LPUART_RequestBreakSending(USART_TypeDef * LPUARTx)2587 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
2588 {
2589 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
2590 }
2591
2592 /**
2593 * @brief Put LPUART in mute mode and set the RWU flag
2594 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
2595 * @param LPUARTx LPUART Instance
2596 * @retval None
2597 */
LL_LPUART_RequestEnterMuteMode(USART_TypeDef * LPUARTx)2598 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
2599 {
2600 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
2601 }
2602
2603 /**
2604 * @brief Request a Receive Data and FIFO flush
2605 * @note Allows to discard the received data without reading them, and avoid an overrun
2606 * condition.
2607 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
2608 * @param LPUARTx LPUART Instance
2609 * @retval None
2610 */
LL_LPUART_RequestRxDataFlush(USART_TypeDef * LPUARTx)2611 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
2612 {
2613 SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
2614 }
2615
2616 /**
2617 * @}
2618 */
2619
2620 #if defined(USE_FULL_LL_DRIVER)
2621 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
2622 * @{
2623 */
2624 ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
2625 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
2626 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
2627 /**
2628 * @}
2629 */
2630 #endif /* USE_FULL_LL_DRIVER */
2631
2632 /**
2633 * @}
2634 */
2635
2636 /**
2637 * @}
2638 */
2639
2640 #endif /* LPUART1 */
2641
2642 /**
2643 * @}
2644 */
2645
2646 #ifdef __cplusplus
2647 }
2648 #endif
2649
2650 #endif /* STM32WLxx_LL_LPUART_H */
2651
2652
