1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL CORTEX driver contains a set of generic APIs that can be
23 used by user:
24 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
25 functions
26 (+) Low power mode configuration (SCB register of Cortex-MCU)
27 (+) MPU API to configure and enable regions
28 (+) API to access to MCU info (CPUID register)
29 (+) API to enable fault handler (SHCSR accesses)
30
31 @endverbatim
32 ******************************************************************************
33 */
34
35 /* Define to prevent recursive inclusion -------------------------------------*/
36 #ifndef __STM32WLxx_LL_CORTEX_H
37 #define __STM32WLxx_LL_CORTEX_H
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32wlxx.h"
45
46 /** @addtogroup STM32WLxx_LL_Driver
47 * @{
48 */
49
50 /** @defgroup CORTEX_LL CORTEX
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56
57 /* Private constants ---------------------------------------------------------*/
58
59 /* Private macros ------------------------------------------------------------*/
60
61 /* Exported types ------------------------------------------------------------*/
62 /* Exported constants --------------------------------------------------------*/
63 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
64 * @{
65 */
66
67 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
68 * @{
69 */
70 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
71 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
72 /**
73 * @}
74 */
75
76 #if !defined(CORE_CM0PLUS)
77 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
78 * @{
79 */
80 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
81 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
82 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
83 /**
84 * @}
85 */
86 #endif /* CORE_CM0PLUS */
87
88 #if __MPU_PRESENT
89 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
90 * @{
91 */
92 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
93 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
94 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
95 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
96 /**
97 * @}
98 */
99
100 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
101 * @{
102 */
103 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
104 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
105 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
106 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
107 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
108 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
109 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
110 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
111 /**
112 * @}
113 */
114
115 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
116 * @{
117 */
118 #if defined(CORE_CM0PLUS)
119 #else
120 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
121 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
122 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
123 #endif
124 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
125 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
126 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
127 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
128 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
129 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
130 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
131 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
132 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
133 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
134 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
135 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
136 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
137 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
138 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
139 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
140 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
141 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
142 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
143 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
144 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
145 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
146 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
147 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
148 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
149 /**
150 * @}
151 */
152
153 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
154 * @{
155 */
156 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
157 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
158 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
159 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
160 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
161 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
162 /**
163 * @}
164 */
165
166 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
167 * @{
168 */
169 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
170 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
171 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
172
173 /**
174 * @}
175 */
176
177 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
178 * @{
179 */
180 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
181 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
182 /**
183 * @}
184 */
185
186 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
187 * @{
188 */
189 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
190 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
191 /**
192 * @}
193 */
194
195 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
196 * @{
197 */
198 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
199 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
200 /**
201 * @}
202 */
203
204 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
205 * @{
206 */
207 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
208 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
209 /**
210 * @}
211 */
212 #endif /* __MPU_PRESENT */
213 /**
214 * @}
215 */
216
217 /* Exported macro ------------------------------------------------------------*/
218
219 /* Exported functions --------------------------------------------------------*/
220 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
221 * @{
222 */
223
224 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
225 * @{
226 */
227
228 /**
229 * @brief This function checks if the Systick counter flag is active or not.
230 * @note It can be used in timeout function on application side.
231 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
232 * @retval State of bit (1 or 0).
233 */
LL_SYSTICK_IsActiveCounterFlag(void)234 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
235 {
236 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
237 }
238
239 /**
240 * @brief Configures the SysTick clock source
241 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
242 * @param Source This parameter can be one of the following values:
243 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
244 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
245 * @retval None
246 */
LL_SYSTICK_SetClkSource(uint32_t Source)247 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
248 {
249 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
250 {
251 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
252 }
253 else
254 {
255 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
256 }
257 }
258
259 /**
260 * @brief Get the SysTick clock source
261 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
262 * @retval Returned value can be one of the following values:
263 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
264 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
265 */
LL_SYSTICK_GetClkSource(void)266 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
267 {
268 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
269 }
270
271 /**
272 * @brief Enable SysTick exception request
273 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
274 * @retval None
275 */
LL_SYSTICK_EnableIT(void)276 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
277 {
278 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
279 }
280
281 /**
282 * @brief Disable SysTick exception request
283 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
284 * @retval None
285 */
LL_SYSTICK_DisableIT(void)286 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
287 {
288 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
289 }
290
291 /**
292 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
293 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
294 * @retval State of bit (1 or 0).
295 */
LL_SYSTICK_IsEnabledIT(void)296 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
297 {
298 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
299 }
300
301 /**
302 * @}
303 */
304
305 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
306 * @{
307 */
308
309 /**
310 * @brief Processor uses sleep as its low power mode
311 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
312 * @retval None
313 */
LL_LPM_EnableSleep(void)314 __STATIC_INLINE void LL_LPM_EnableSleep(void)
315 {
316 /* Clear SLEEPDEEP bit of Cortex System Control Register */
317 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
318 }
319
320 /**
321 * @brief Processor uses deep sleep as its low power mode
322 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
323 * @retval None
324 */
LL_LPM_EnableDeepSleep(void)325 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
326 {
327 /* Set SLEEPDEEP bit of Cortex System Control Register */
328 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
329 }
330
331 /**
332 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
333 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
334 * empty main application.
335 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
336 * @retval None
337 */
LL_LPM_EnableSleepOnExit(void)338 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
339 {
340 /* Set SLEEPONEXIT bit of Cortex System Control Register */
341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
342 }
343
344 /**
345 * @brief Do not sleep when returning to Thread mode.
346 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
347 * @retval None
348 */
LL_LPM_DisableSleepOnExit(void)349 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
350 {
351 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
352 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
353 }
354
355 /**
356 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
357 * processor.
358 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
359 * @retval None
360 */
LL_LPM_EnableEventOnPend(void)361 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
362 {
363 /* Set SEVEONPEND bit of Cortex System Control Register */
364 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
365 }
366
367 /**
368 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
369 * excluded
370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
371 * @retval None
372 */
LL_LPM_DisableEventOnPend(void)373 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
374 {
375 /* Clear SEVEONPEND bit of Cortex System Control Register */
376 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
377 }
378
379 /**
380 * @}
381 */
382
383 #if !defined(CORE_CM0PLUS)
384 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
385 * @{
386 */
387
388 /**
389 * @brief Enable a fault in System handler control register (SHCSR)
390 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
391 * @param Fault This parameter can be a combination of the following values:
392 * @arg @ref LL_HANDLER_FAULT_USG
393 * @arg @ref LL_HANDLER_FAULT_BUS
394 * @arg @ref LL_HANDLER_FAULT_MEM
395 * @retval None
396 */
LL_HANDLER_EnableFault(uint32_t Fault)397 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
398 {
399 /* Enable the system handler fault */
400 SET_BIT(SCB->SHCSR, Fault);
401 }
402
403 /**
404 * @brief Disable a fault in System handler control register (SHCSR)
405 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
406 * @param Fault This parameter can be a combination of the following values:
407 * @arg @ref LL_HANDLER_FAULT_USG
408 * @arg @ref LL_HANDLER_FAULT_BUS
409 * @arg @ref LL_HANDLER_FAULT_MEM
410 * @retval None
411 */
LL_HANDLER_DisableFault(uint32_t Fault)412 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
413 {
414 /* Disable the system handler fault */
415 CLEAR_BIT(SCB->SHCSR, Fault);
416 }
417
418 /**
419 * @}
420 */
421
422 #endif /* CORE_CM0PLUS */
423 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
424 * @{
425 */
426
427 /**
428 * @brief Get Implementer code
429 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
430 * @retval Value should be equal to 0x41 for ARM
431 */
LL_CPUID_GetImplementer(void)432 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
433 {
434 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
435 }
436
437 /**
438 * @brief Get Variant number (The r value in the rnpn product revision identifier)
439 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
440 * @retval Value between 0 and 255 (0x0: revision 0)
441 */
LL_CPUID_GetVariant(void)442 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
443 {
444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
445 }
446
447 /**
448 * @brief Get Architecture number
449 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
450 * @retval Value should be equal to 0xF for Cortex-M4 devices
451 */
LL_CPUID_GetArchitecture(void)452 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
453 {
454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
455 }
456
457 /**
458 * @brief Get Part number
459 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
460 * @retval Value should be equal to 0xC24 for Cortex-M4
461 */
LL_CPUID_GetParNo(void)462 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
463 {
464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
465 }
466
467 /**
468 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
469 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
470 * @retval Value between 0 and 255 (0x1: patch 1)
471 */
LL_CPUID_GetRevision(void)472 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
473 {
474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
475 }
476
477 /**
478 * @}
479 */
480
481 #if __MPU_PRESENT
482 /** @defgroup CORTEX_LL_EF_MPU MPU
483 * @{
484 */
485
486 /**
487 * @brief Enable MPU with input options
488 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
489 * @param Options This parameter can be one of the following values:
490 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
491 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
492 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
493 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
494 * @retval None
495 */
LL_MPU_Enable(uint32_t Options)496 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
497 {
498 /* Enable the MPU*/
499 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
500 /* Ensure MPU settings take effects */
501 __DSB();
502 /* Sequence instruction fetches using update settings */
503 __ISB();
504 }
505
506 /**
507 * @brief Disable MPU
508 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
509 * @retval None
510 */
LL_MPU_Disable(void)511 __STATIC_INLINE void LL_MPU_Disable(void)
512 {
513 /* Make sure outstanding transfers are done */
514 __DMB();
515 /* Disable MPU*/
516 WRITE_REG(MPU->CTRL, 0U);
517 }
518
519 /**
520 * @brief Check if MPU is enabled or not
521 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
522 * @retval State of bit (1 or 0).
523 */
LL_MPU_IsEnabled(void)524 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
525 {
526 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
527 }
528
529 /**
530 * @brief Enable a MPU region
531 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
532 * @param Region This parameter can be one of the following values:
533 * @arg @ref LL_MPU_REGION_NUMBER0
534 * @arg @ref LL_MPU_REGION_NUMBER1
535 * @arg @ref LL_MPU_REGION_NUMBER2
536 * @arg @ref LL_MPU_REGION_NUMBER3
537 * @arg @ref LL_MPU_REGION_NUMBER4
538 * @arg @ref LL_MPU_REGION_NUMBER5
539 * @arg @ref LL_MPU_REGION_NUMBER6
540 * @arg @ref LL_MPU_REGION_NUMBER7
541 * @retval None
542 */
LL_MPU_EnableRegion(uint32_t Region)543 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
544 {
545 /* Set Region number */
546 WRITE_REG(MPU->RNR, Region);
547 /* Enable the MPU region */
548 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
549 }
550
551 /**
552 * @brief Configure and enable a region
553 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
554 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
555 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
556 * MPU_RASR XN LL_MPU_ConfigRegion\n
557 * MPU_RASR AP LL_MPU_ConfigRegion\n
558 * MPU_RASR S LL_MPU_ConfigRegion\n
559 * MPU_RASR C LL_MPU_ConfigRegion\n
560 * MPU_RASR B LL_MPU_ConfigRegion\n
561 * MPU_RASR SIZE LL_MPU_ConfigRegion
562 * @param Region This parameter can be one of the following values:
563 * @arg @ref LL_MPU_REGION_NUMBER0
564 * @arg @ref LL_MPU_REGION_NUMBER1
565 * @arg @ref LL_MPU_REGION_NUMBER2
566 * @arg @ref LL_MPU_REGION_NUMBER3
567 * @arg @ref LL_MPU_REGION_NUMBER4
568 * @arg @ref LL_MPU_REGION_NUMBER5
569 * @arg @ref LL_MPU_REGION_NUMBER6
570 * @arg @ref LL_MPU_REGION_NUMBER7
571 * @param Address Value of region base address
572 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
573 * @param Attributes This parameter can be a combination of the following values:
574 * @arg @ref LL_MPU_REGION_SIZE_32B (*) or @ref LL_MPU_REGION_SIZE_64B (*) or @ref LL_MPU_REGION_SIZE_128B (*)
575 * or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B or @ref LL_MPU_REGION_SIZE_1KB
576 * or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB
577 * or @ref LL_MPU_REGION_SIZE_16KB or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB
578 * or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
579 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB
580 * or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB or @ref LL_MPU_REGION_SIZE_32MB
581 * or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB
582 * or @ref LL_MPU_REGION_SIZE_512MB or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB
583 * or @ref LL_MPU_REGION_SIZE_4GB
584 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO
585 * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
586 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
587 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
588 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
589 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
590 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
591 * (*) value not defined for CM0+ core.
592 * @retval None
593 */
LL_MPU_ConfigRegion(uint32_t Region,uint32_t SubRegionDisable,uint32_t Address,uint32_t Attributes)594 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address,
595 uint32_t Attributes)
596 {
597 /* Set Region number */
598 WRITE_REG(MPU->RNR, Region);
599 /* Set base address */
600 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
601 /* Configure MPU */
602 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
603 }
604
605 /**
606 * @brief Disable a region
607 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
608 * MPU_RASR ENABLE LL_MPU_DisableRegion
609 * @param Region This parameter can be one of the following values:
610 * @arg @ref LL_MPU_REGION_NUMBER0
611 * @arg @ref LL_MPU_REGION_NUMBER1
612 * @arg @ref LL_MPU_REGION_NUMBER2
613 * @arg @ref LL_MPU_REGION_NUMBER3
614 * @arg @ref LL_MPU_REGION_NUMBER4
615 * @arg @ref LL_MPU_REGION_NUMBER5
616 * @arg @ref LL_MPU_REGION_NUMBER6
617 * @arg @ref LL_MPU_REGION_NUMBER7
618 * @retval None
619 */
LL_MPU_DisableRegion(uint32_t Region)620 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
621 {
622 /* Set Region number */
623 WRITE_REG(MPU->RNR, Region);
624 /* Disable the MPU region */
625 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
626 }
627
628 /**
629 * @}
630 */
631
632 #endif /* __MPU_PRESENT */
633 /**
634 * @}
635 */
636
637 /**
638 * @}
639 */
640
641 /**
642 * @}
643 */
644
645 #ifdef __cplusplus
646 }
647 #endif
648
649 #endif /* __STM32WLxx_LL_CORTEX_H */
650
