1 /**
2 ******************************************************************************
3 * @file stm32wlxx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32WLxx_LL_ADC_H
21 #define STM32WLxx_LL_ADC_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32wlxx.h"
29
30 /** @addtogroup STM32WLxx_LL_Driver
31 * @{
32 */
33
34 #if defined (ADC)
35
36 /** @defgroup ADC_LL ADC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
45 * @{
46 */
47
48 /* Internal mask for ADC group regular sequencer: */
49 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50 /* - sequencer rank bits position into the selected register */
51
52 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
53
54 /* Definition of ADC group regular sequencer bits information to be inserted */
55 /* into ADC group regular sequencer ranks literals definition. */
56 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
57 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
58 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
59 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
60 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
61 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
62 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
63 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
64
65
66
67 /* Internal mask for ADC group regular trigger: */
68 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
69 /* - regular trigger source */
70 /* - regular trigger edge */
71 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
72 compatibility with some ADC on other STM32 families
73 having this setting set by HW default value) */
74
75 /* Mask containing trigger source masks for each of possible */
76 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
77 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
78 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
79 ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \
80 ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \
81 ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) )
82
83 /* Mask containing trigger edge masks for each of possible */
84 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
85 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
86 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
87 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
88 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
89 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
90
91 /* Definition of ADC group regular trigger bits information. */
92 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
93 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
94
95
96
97 /* Internal mask for ADC channel: */
98 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
99 /* - channel identifier defined by number */
100 /* - channel identifier defined by bitfield */
101 /* - channel differentiation between external channels (connected to */
102 /* GPIO pins) and internal channels (connected to internal paths) */
103 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH)
104 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
105 #define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
106 ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
107 if set to mode "fully configurable", can contain channels with a restricted channel number.
108 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
109 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
110 position in register */
111 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
112 ADC_CHANNEL_ID_INTERNAL_CH_MASK)
113 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
114 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
115 >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
116
117 /* Channel differentiation between external and internal channels */
118 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
119 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
120
121 /* Definition of channels ID number information to be inserted into */
122 /* channels literals definition. */
123 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
124 #define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0)
125 #define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1)
126 #define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
127 #define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2)
128 #define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
129 #define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
130 #define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
131 #define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3)
132 #define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
133 #define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
134 #define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
135 #define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
136 #define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
137 #define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
138 #define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
139 ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
140 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4)
141 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
142 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
143
144 /* Definition of channels ID bitfield information to be inserted into */
145 /* channels literals definition. */
146 #define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
147 #define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
148 #define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
149 #define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
150 #define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
151 #define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
152 #define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
153 #define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
154 #define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
155 #define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
156 #define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
157 #define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
158 #define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
159 #define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
160 #define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
161 #define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
162 #define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
163 #define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
164
165 /* Internal mask for ADC channel sampling time: */
166 /* To select into literals LL_ADC_SAMPLINGTIME_x */
167 /* the relevant bits for: */
168 /* (concatenation of multiple bits used in register SMPR) */
169 /* - ADC channels sampling time: setting channel wise, to map each channel */
170 /* on one of the common sampling time available. */
171 /* - ADC channels common sampling time: set a sampling time into one of the */
172 /* common sampling time available. */
173 #define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
174 #define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
175 #define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
176
177 /* Internal mask for ADC analog watchdog: */
178 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
179 /* (concatenation of multiple bits used in different analog watchdogs, */
180 /* (feature of several watchdogs not available on all STM32 families)). */
181 /* - analog watchdog 1: monitored channel defined by number, */
182 /* selection of ADC group (ADC group regular). */
183 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
184 /* selection on groups. */
185
186 /* Internal register offset for ADC analog watchdog channel configuration */
187 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
188 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
189 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
190
191 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
192 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
193 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
194 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
195
196 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
197 #define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
198
199 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
200 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
201 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
202
203 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET
204 in ADC_AWD_CRX_REGOFFSET_MASK */
205
206 /* Internal register offset for ADC analog watchdog threshold configuration */
207 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
208 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
209 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
210 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
211 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET
212 in ADC_AWD_TRX_REGOFFSET_MASK */
213 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate
214 threshold high: mask of bit */
215 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate
216 threshold high: position of bit */
217 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
218 position to perform a shift of 4 ranks */
219 #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
220
221
222
223 /* ADC registers bits positions */
224 #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
225 #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
226 #define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
227 #define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
228 #define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
229 #define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
230 #define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
231 #define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
232 #define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
233 #define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
234 #define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
235 #define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
236 #define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
237 #define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
238 #define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
239 #define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
240 #define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
241 #define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
242 #define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
243 #define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
244 #define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
245 #define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
246 #define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
247 #define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
248 #define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
249
250
251 /* ADC registers bits groups */
252 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
253 | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with
254 HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
255
256
257 /* ADC internal channels related definitions */
258 /* Internal voltage reference VrefInt */
259 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference,
260 address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC),
261 Vref+ = 3.3 V (tolerance: +-10 mV). */
262 #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value
263 with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
264 /* Temperature sensor */
265 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32WL,
266 temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V
267 (tolerance: +-10 mV). */
268 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On STM32WL,
269 temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V
270 (tolerance: +-10 mV). */
271 #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor
272 has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
273 #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor
274 has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
275 #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) value
276 with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
277
278 /**
279 * @}
280 */
281
282
283 /* Private macros ------------------------------------------------------------*/
284 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
285 * @{
286 */
287
288 /**
289 * @brief Driver macro reserved for internal use: set a pointer to
290 * a register from a register basis from which an offset
291 * is applied.
292 * @param __REG__ Register basis from which the offset is applied.
293 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
294 * @retval Pointer to register address
295 */
296 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
297 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
298
299 /**
300 * @}
301 */
302
303
304 /* Exported types ------------------------------------------------------------*/
305 #if defined(USE_FULL_LL_DRIVER)
306 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
307 * @{
308 */
309
310 /**
311 * @brief Structure definition of some features of ADC common parameters
312 * and multimode
313 * (all ADC instances belonging to the same ADC common instance).
314 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
315 * is conditioned to ADC instances state (all ADC instances
316 * sharing the same ADC common instance):
317 * All ADC instances sharing the same ADC common instance must be
318 * disabled.
319 */
320 typedef struct
321 {
322 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
323 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
324 This feature can be modified afterwards using unitary function
325 @ref LL_ADC_SetCommonClock(). */
326
327 } LL_ADC_CommonInitTypeDef;
328
329 /**
330 * @brief Structure definition of some features of ADC instance.
331 * @note These parameters have an impact on ADC scope: ADC instance.
332 * Refer to corresponding unitary functions into
333 * @ref ADC_LL_EF_Configuration_ADC_Instance .
334 * @note The setting of these parameters by function @ref LL_ADC_Init()
335 * is conditioned to ADC state:
336 * ADC instance must be disabled.
337 * This condition is applied to all ADC features, for efficiency
338 * and compatibility over all STM32 families. However, the different
339 * features can be set under different ADC state conditions
340 * (setting possible with ADC enabled without conversion on going,
341 * ADC enabled with conversion on going, ...)
342 * Each feature can be updated afterwards with a unitary function
343 * and potentially with ADC in a different state than disabled,
344 * refer to description of each function for setting
345 * conditioned to ADC state.
346 */
347 typedef struct
348 {
349 uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
350 This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
351 @note On this STM32 series, this parameter has some clock ratio constraints:
352 ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
353 only if PCLK has a 50% duty clock cycle (APB prescaler configured
354 inside the RCC must be bypassed and the system clock must by 50% duty
355 cycle).
356 This feature can be modified afterwards using unitary function
357 @ref LL_ADC_SetClock().
358 For more details, refer to description of this function. */
359
360 uint32_t Resolution; /*!< Set ADC resolution.
361 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
362 This feature can be modified afterwards using unitary function
363 @ref LL_ADC_SetResolution(). */
364
365 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
366 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
367 This feature can be modified afterwards using unitary function
368 @ref LL_ADC_SetDataAlignment(). */
369
370 uint32_t LowPowerMode; /*!< Set ADC low power mode.
371 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
372 This feature can be modified afterwards using unitary function
373 @ref LL_ADC_SetLowPowerMode(). */
374
375 } LL_ADC_InitTypeDef;
376
377 /**
378 * @brief Structure definition of some features of ADC group regular.
379 * @note These parameters have an impact on ADC scope: ADC group regular.
380 * Refer to corresponding unitary functions into
381 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
382 * (functions with prefix "REG").
383 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
384 * is conditioned to ADC state:
385 * ADC instance must be disabled.
386 * This condition is applied to all ADC features, for efficiency
387 * and compatibility over all STM32 families. However, the different
388 * features can be set under different ADC state conditions
389 * (setting possible with ADC enabled without conversion on going,
390 * ADC enabled with conversion on going, ...)
391 * Each feature can be updated afterwards with a unitary function
392 * and potentially with ADC in a different state than disabled,
393 * refer to description of each function for setting
394 * conditioned to ADC state.
395 */
396 typedef struct
397 {
398 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or
399 from external peripheral (timer event, external interrupt line).
400 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
401 @note On this STM32 series, setting trigger source to external trigger also
402 set trigger polarity to rising edge(default setting for compatibility
403 with some ADC on other STM32 families having this setting set by HW
404 default value).
405 In case of need to modify trigger edge, use function
406 @ref LL_ADC_REG_SetTriggerEdge().
407 This feature can be modified afterwards using unitary function
408 @ref LL_ADC_REG_SetTriggerSource(). */
409
410 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
411 @note This parameter has an effect only if group regular sequencer is set
412 to mode "fully configurable". Refer to function
413 @ref LL_ADC_REG_SetSequencerConfigurable().
414 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
415 This feature can be modified afterwards using unitary function
416 @ref LL_ADC_REG_SetSequencerLength(). */
417
418 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
419 and scan conversions interrupted every selected number of ranks.
420 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
421 @note This parameter has an effect only if group regular sequencer is
422 enabled (depending on the sequencer mode: scan length of 2 ranks or
423 more, or several ADC channels enabled in group regular sequencer.
424 Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
425 This feature can be modified afterwards using unitary function
426 @ref LL_ADC_REG_SetSequencerDiscont(). */
427
428 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
429 conversions are performed in single mode (one conversion per trigger) or in
430 continuous mode (after the first trigger, following conversions launched
431 successively automatically).
432 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
433 Note: It is not possible to enable both ADC group regular continuous mode
434 and discontinuous mode.
435 This feature can be modified afterwards using unitary function
436 @ref LL_ADC_REG_SetContinuousMode(). */
437
438 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer
439 by DMA, and DMA requests mode.
440 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
441 This feature can be modified afterwards using unitary function
442 @ref LL_ADC_REG_SetDMATransfer(). */
443
444 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
445 data preserved or overwritten.
446 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
447 This feature can be modified afterwards using unitary function
448 @ref LL_ADC_REG_SetOverrun(). */
449
450 } LL_ADC_REG_InitTypeDef;
451
452 /**
453 * @}
454 */
455 #endif /* USE_FULL_LL_DRIVER */
456
457 /* Exported constants --------------------------------------------------------*/
458 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
459 * @{
460 */
461
462 /** @defgroup ADC_LL_EC_FLAG ADC flags
463 * @brief Flags defines which can be used with LL_ADC_ReadReg function
464 * @{
465 */
466 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
467 #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
468 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
469 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
470 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
471 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
472 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
473 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
474 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
475 #define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
476 /**
477 * @}
478 */
479
480 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
481 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
482 * @{
483 */
484 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
485 #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
486 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
487 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
488 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
489 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
490 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
491 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
492 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
493 #define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
494 /**
495 * @}
496 */
497
498 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
499 * @{
500 */
501 /* List of ADC registers intended to be used (most commonly) with */
502 /* DMA transfer. */
503 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
504 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register
505 (corresponding to register DR) to be used with ADC
506 configured in independent mode. Without DMA transfer,
507 register accessed by LL function
508 @ref LL_ADC_REG_ReadConversionData32() and other
509 functions @ref LL_ADC_REG_ReadConversionDatax() */
510 /**
511 * @}
512 */
513
514 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
515 * @{
516 */
517 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
518 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
519 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
520 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
521 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
522 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
523 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
524 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
525 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
526 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
527 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
528 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */
529 /**
530 * @}
531 */
532
533 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
534 * @{
535 */
536 /* Note: Other measurement paths to internal channels may be available */
537 /* (connections to other peripherals). */
538 /* If they are not listed below, they do not require any specific */
539 /* path enable. In this case, Access to measurement path is done */
540 /* only by selecting the corresponding ADC internal channel. */
541 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
542 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
543 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
544 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
545 /**
546 * @}
547 */
548
549 /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
550 * @{
551 */
552 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
553 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
554 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
555 #define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
556 /**
557 * @}
558 */
559
560 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
561 * @{
562 */
563 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
564 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
565 #define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */
566 #define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */
567 /**
568 * @}
569 */
570
571 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
572 * @{
573 */
574 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
575 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
576 /**
577 * @}
578 */
579
580 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
581 * @{
582 */
583 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
584 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
585 #define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
586 #define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
587 /**
588 * @}
589 */
590
591 /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
592 * @{
593 */
594 #define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
595 #define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
596 /**
597 * @}
598 */
599
600 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
601 * @{
602 */
603 #define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
604 #define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
605 /**
606 * @}
607 */
608
609 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
610 * @{
611 */
612 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
613 /**
614 * @}
615 */
616
617 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
618 * @{
619 */
620 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
621 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
622 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
623 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
624 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
625 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
626 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
627 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
628 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
629 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
630 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
631 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
632 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
633 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
634 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
635 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
636 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
637 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
638 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
639 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
640 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
641 #define LL_ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC channel 1. */
642 /**
643 * @}
644 */
645
646 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
647 * @{
648 */
649 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
650 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
651 #define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
652 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
653 #define LL_ADC_REG_TRIG_EXT_TIM2_CH4 ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
654 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
655 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
656 /**
657 * @}
658 */
659
660 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
661 * @{
662 */
663 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
664 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
665 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
666 /**
667 * @}
668 */
669
670 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
671 * @{
672 */
673 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
674 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
675 /**
676 * @}
677 */
678
679 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
680 * @{
681 */
682 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
683 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
684 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
685 /**
686 * @}
687 */
688
689 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
690 * @{
691 */
692 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
693 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
694 /**
695 * @}
696 */
697
698 /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
699 * @{
700 */
701 #define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */
702 #define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
703 /**
704 * @}
705 */
706
707 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
708 * @{
709 */
710 #define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
711 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
712 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
713 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
714 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
715 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
716 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
717 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
718 /**
719 * @}
720 */
721
722 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
723 * @{
724 */
725 #define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */
726 #define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */
727 /**
728 * @}
729 */
730
731 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
732 * @{
733 */
734 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
735 #define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
736 /**
737 * @}
738 */
739
740 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
741 * @{
742 */
743 #define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
744 #define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
745 #define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
746 #define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
747 #define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
748 #define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
749 #define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
750 #define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
751 /**
752 * @}
753 */
754
755 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
756 * @{
757 */
758 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
759 #define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
760 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
761 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
762 #define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */
763 #define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
764 #define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
765 #define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
766 /**
767 * @}
768 */
769
770 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
771 * @{
772 */
773 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
774 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
775 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
776 /**
777 * @}
778 */
779
780 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
781 * @{
782 */
783 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
784 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
785 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
786 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
787 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
788 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
789 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
790 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
791 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
792 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
793 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
794 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
795 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
796 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
797 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
798 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
799 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
800 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
801 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
802 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
803 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
804 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
805 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
806 #define LL_ADC_AWD_CH_DACCH1_REG ((LL_ADC_CHANNEL_DACCH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC channel 1, converted by group regular only */
807 /**
808 * @}
809 */
810
811 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
812 * @{
813 */
814 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */
815 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */
816 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
817 /**
818 * @}
819 */
820
821 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
822 * @{
823 */
824 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
825 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
826 /**
827 * @}
828 */
829
830 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
831 * @{
832 */
833 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
834 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
835 /**
836 * @}
837 */
838
839 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
840 * @{
841 */
842 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
843 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
844 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
845 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
846 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
847 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
848 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
849 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
850 /**
851 * @}
852 */
853
854 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
855 * @{
856 */
857 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
858 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
859 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
860 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
861 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
862 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
863 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
864 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
865 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
866 /**
867 * @}
868 */
869
870 /** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro
871 * @{
872 */
873 #define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro
874 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
875 calibration parameters. This value is coded on 16 bits
876 (to fit on signed word or double word) and corresponds
877 to an inconsistent temperature value. */
878 /**
879 * @}
880 */
881
882 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
883 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
884 * not timeout values.
885 * For details on delays values, refer to descriptions in source code
886 * above each literal definition.
887 * @{
888 */
889
890 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
891 /* not timeout values. */
892 /* Timeout values for ADC operations are dependent to device clock */
893 /* configuration (system clock versus ADC clock), */
894 /* and therefore must be defined in user application. */
895 /* Indications for estimation of ADC timeout delays, for this */
896 /* STM32 series: */
897 /* - ADC calibration time: maximum delay is 82/fADC. */
898 /* (refer to device datasheet, parameter "tCAL") */
899 /* - ADC enable time: maximum delay is 1 conversion cycle. */
900 /* (refer to device datasheet, parameter "tSTAB") */
901 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
902 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
903 /* cycles */
904 /* - ADC conversion time: duration depending on ADC clock and ADC */
905 /* configuration. */
906 /* (refer to device reference manual, section "Timing") */
907
908 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
909 /* Delay set to maximum value (refer to device datasheet, */
910 /* parameter "tADCVREG_STUP"). */
911 /* Unit: us */
912 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
913
914 /* Delay for internal voltage reference stabilization time. */
915 /* Delay set to maximum value (refer to device datasheet, */
916 /* parameter "tstart_vrefint"). */
917 /* Unit: us */
918 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
919
920 /* Delay for temperature sensor stabilization time. */
921 /* Literal set to maximum value (refer to device datasheet, */
922 /* parameter "tSTART"). */
923 /* Unit: us */
924 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */
925 #define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */
926
927 /* Delay required between ADC end of calibration and ADC enable. */
928 /* Note: On this STM32 series, a minimum number of ADC clock cycles */
929 /* are required between ADC end of calibration and ADC enable. */
930 /* Wait time can be computed in user application by waiting for the */
931 /* equivalent number of CPU cycles, by taking into account */
932 /* ratio of CPU clock versus ADC clock prescalers. */
933 /* Unit: ADC clock cycles. */
934 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration and ADC enable */
935
936 /**
937 * @}
938 */
939
940 /**
941 * @}
942 */
943
944
945 /* Exported macro ------------------------------------------------------------*/
946 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
947 * @{
948 */
949
950 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
951 * @{
952 */
953
954 /**
955 * @brief Write a value in ADC register
956 * @param __INSTANCE__ ADC Instance
957 * @param __REG__ Register to be written
958 * @param __VALUE__ Value to be written in the register
959 * @retval None
960 */
961 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
962
963 /**
964 * @brief Read a value in ADC register
965 * @param __INSTANCE__ ADC Instance
966 * @param __REG__ Register to be read
967 * @retval Register value
968 */
969 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
970 /**
971 * @}
972 */
973
974 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
975 * @{
976 */
977
978 /**
979 * @brief Helper macro to get ADC channel number in decimal format
980 * from literals LL_ADC_CHANNEL_x.
981 * @note Example:
982 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
983 * will return decimal number "4".
984 * @note The input can be a value from functions where a channel
985 * number is returned, either defined with number
986 * or with bitfield (only one bit must be set).
987 * @param __CHANNEL__ This parameter can be one of the following values:
988 * @arg @ref LL_ADC_CHANNEL_0
989 * @arg @ref LL_ADC_CHANNEL_1
990 * @arg @ref LL_ADC_CHANNEL_2
991 * @arg @ref LL_ADC_CHANNEL_3
992 * @arg @ref LL_ADC_CHANNEL_4
993 * @arg @ref LL_ADC_CHANNEL_5
994 * @arg @ref LL_ADC_CHANNEL_6
995 * @arg @ref LL_ADC_CHANNEL_7
996 * @arg @ref LL_ADC_CHANNEL_8
997 * @arg @ref LL_ADC_CHANNEL_9
998 * @arg @ref LL_ADC_CHANNEL_10
999 * @arg @ref LL_ADC_CHANNEL_11
1000 * @arg @ref LL_ADC_CHANNEL_12
1001 * @arg @ref LL_ADC_CHANNEL_13
1002 * @arg @ref LL_ADC_CHANNEL_14
1003 * @arg @ref LL_ADC_CHANNEL_15 (1)
1004 * @arg @ref LL_ADC_CHANNEL_16 (1)
1005 * @arg @ref LL_ADC_CHANNEL_17 (1)
1006 * @arg @ref LL_ADC_CHANNEL_VREFINT
1007 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1008 * @arg @ref LL_ADC_CHANNEL_VBAT
1009 * @arg @ref LL_ADC_CHANNEL_DACCH1
1010 *
1011 * (1) On STM32WL, parameter can be set in ADC group sequencer
1012 * only if sequencer is set in mode "not fully configurable",
1013 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1014 * @retval Value between Min_Data=0 and Max_Data=18
1015 */
1016 #if defined(CORE_CM0PLUS)
1017 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1018 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1019 ( \
1020 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1021 ) \
1022 : \
1023 ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \
1024 ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \
1025 ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \
1026 ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \
1027 ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \
1028 ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \
1029 ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \
1030 ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \
1031 ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \
1032 ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \
1033 ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \
1034 ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \
1035 ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \
1036 ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \
1037 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \
1038 ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \
1039 ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \
1040 ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \
1041 (0UL))))))))))))))))))))
1042
1043 #else
1044 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1045 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
1046 ( \
1047 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1048 ) \
1049 : \
1050 ( \
1051 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1052 ) \
1053 )
1054 #endif /* CORE_CM0PLUS */
1055
1056 /**
1057 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1058 * from number in decimal format.
1059 * @note Example:
1060 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1061 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1062 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1063 * @retval Returned value can be one of the following values:
1064 * @arg @ref LL_ADC_CHANNEL_0
1065 * @arg @ref LL_ADC_CHANNEL_1
1066 * @arg @ref LL_ADC_CHANNEL_2
1067 * @arg @ref LL_ADC_CHANNEL_3
1068 * @arg @ref LL_ADC_CHANNEL_4
1069 * @arg @ref LL_ADC_CHANNEL_5
1070 * @arg @ref LL_ADC_CHANNEL_6
1071 * @arg @ref LL_ADC_CHANNEL_7
1072 * @arg @ref LL_ADC_CHANNEL_8
1073 * @arg @ref LL_ADC_CHANNEL_9
1074 * @arg @ref LL_ADC_CHANNEL_10
1075 * @arg @ref LL_ADC_CHANNEL_11
1076 * @arg @ref LL_ADC_CHANNEL_12
1077 * @arg @ref LL_ADC_CHANNEL_13
1078 * @arg @ref LL_ADC_CHANNEL_14
1079 * @arg @ref LL_ADC_CHANNEL_15 (1)
1080 * @arg @ref LL_ADC_CHANNEL_16 (1)
1081 * @arg @ref LL_ADC_CHANNEL_17 (1)
1082 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1083 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1084 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
1085 * @arg @ref LL_ADC_CHANNEL_DACCH1 (2)
1086 *
1087 * (1) On STM32WL, parameter can be set in ADC group sequencer
1088 * only if sequencer is set in mode "not fully configurable",
1089 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1090 * (2) For ADC channel read back from ADC register,
1091 * comparison with internal channel parameter to be done
1092 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1093 */
1094 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1095 (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1096 (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
1097
1098 /**
1099 * @brief Helper macro to determine whether the selected channel
1100 * corresponds to literal definitions of driver.
1101 * @note The different literal definitions of ADC channels are:
1102 * - ADC internal channel:
1103 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1104 * - ADC external channel (channel connected to a GPIO pin):
1105 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1106 * @note The channel parameter must be a value defined from literal
1107 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1108 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1109 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1110 * must not be a value from functions where a channel number is
1111 * returned from ADC registers,
1112 * because internal and external channels share the same channel
1113 * number in ADC registers. The differentiation is made only with
1114 * parameters definitions of driver.
1115 * @param __CHANNEL__ This parameter can be one of the following values:
1116 * @arg @ref LL_ADC_CHANNEL_0
1117 * @arg @ref LL_ADC_CHANNEL_1
1118 * @arg @ref LL_ADC_CHANNEL_2
1119 * @arg @ref LL_ADC_CHANNEL_3
1120 * @arg @ref LL_ADC_CHANNEL_4
1121 * @arg @ref LL_ADC_CHANNEL_5
1122 * @arg @ref LL_ADC_CHANNEL_6
1123 * @arg @ref LL_ADC_CHANNEL_7
1124 * @arg @ref LL_ADC_CHANNEL_8
1125 * @arg @ref LL_ADC_CHANNEL_9
1126 * @arg @ref LL_ADC_CHANNEL_10
1127 * @arg @ref LL_ADC_CHANNEL_11
1128 * @arg @ref LL_ADC_CHANNEL_12
1129 * @arg @ref LL_ADC_CHANNEL_13
1130 * @arg @ref LL_ADC_CHANNEL_14
1131 * @arg @ref LL_ADC_CHANNEL_15 (1)
1132 * @arg @ref LL_ADC_CHANNEL_16 (1)
1133 * @arg @ref LL_ADC_CHANNEL_17 (1)
1134 * @arg @ref LL_ADC_CHANNEL_VREFINT
1135 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1136 * @arg @ref LL_ADC_CHANNEL_VBAT
1137 * @arg @ref LL_ADC_CHANNEL_DACCH1
1138 *
1139 * (1) On STM32WL, parameter can be set in ADC group sequencer
1140 * only if sequencer is set in mode "not fully configurable",
1141 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1142 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
1143 connected to a GPIO pin).
1144 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1145 */
1146 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1147 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1148
1149 /**
1150 * @brief Helper macro to convert a channel defined from parameter
1151 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1152 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1153 * to its equivalent parameter definition of a ADC external channel
1154 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1155 * @note The channel parameter can be, additionally to a value
1156 * defined from parameter definition of a ADC internal channel
1157 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1158 * a value defined from parameter definition of
1159 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1160 * or a value from functions where a channel number is returned
1161 * from ADC registers.
1162 * @param __CHANNEL__ This parameter can be one of the following values:
1163 * @arg @ref LL_ADC_CHANNEL_0
1164 * @arg @ref LL_ADC_CHANNEL_1
1165 * @arg @ref LL_ADC_CHANNEL_2
1166 * @arg @ref LL_ADC_CHANNEL_3
1167 * @arg @ref LL_ADC_CHANNEL_4
1168 * @arg @ref LL_ADC_CHANNEL_5
1169 * @arg @ref LL_ADC_CHANNEL_6
1170 * @arg @ref LL_ADC_CHANNEL_7
1171 * @arg @ref LL_ADC_CHANNEL_8
1172 * @arg @ref LL_ADC_CHANNEL_9
1173 * @arg @ref LL_ADC_CHANNEL_10
1174 * @arg @ref LL_ADC_CHANNEL_11
1175 * @arg @ref LL_ADC_CHANNEL_12
1176 * @arg @ref LL_ADC_CHANNEL_13
1177 * @arg @ref LL_ADC_CHANNEL_14
1178 * @arg @ref LL_ADC_CHANNEL_15 (1)
1179 * @arg @ref LL_ADC_CHANNEL_16 (1)
1180 * @arg @ref LL_ADC_CHANNEL_17 (1)
1181 * @arg @ref LL_ADC_CHANNEL_VREFINT
1182 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1183 * @arg @ref LL_ADC_CHANNEL_VBAT
1184 * @arg @ref LL_ADC_CHANNEL_DACCH1
1185 *
1186 * (1) On STM32WL, parameter can be set in ADC group sequencer
1187 * only if sequencer is set in mode "not fully configurable",
1188 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
1189 * @retval Returned value can be one of the following values:
1190 * @arg @ref LL_ADC_CHANNEL_0
1191 * @arg @ref LL_ADC_CHANNEL_1
1192 * @arg @ref LL_ADC_CHANNEL_2
1193 * @arg @ref LL_ADC_CHANNEL_3
1194 * @arg @ref LL_ADC_CHANNEL_4
1195 * @arg @ref LL_ADC_CHANNEL_5
1196 * @arg @ref LL_ADC_CHANNEL_6
1197 * @arg @ref LL_ADC_CHANNEL_7
1198 * @arg @ref LL_ADC_CHANNEL_8
1199 * @arg @ref LL_ADC_CHANNEL_9
1200 * @arg @ref LL_ADC_CHANNEL_10
1201 * @arg @ref LL_ADC_CHANNEL_11
1202 * @arg @ref LL_ADC_CHANNEL_12
1203 * @arg @ref LL_ADC_CHANNEL_13
1204 * @arg @ref LL_ADC_CHANNEL_14
1205 * @arg @ref LL_ADC_CHANNEL_15
1206 * @arg @ref LL_ADC_CHANNEL_16
1207 * @arg @ref LL_ADC_CHANNEL_17
1208 */
1209 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1210 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1211
1212 /**
1213 * @brief Helper macro to determine whether the internal channel
1214 * selected is available on the ADC instance selected.
1215 * @note The channel parameter must be a value defined from parameter
1216 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1217 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1218 * must not be a value defined from parameter definition of
1219 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1220 * or a value from functions where a channel number is
1221 * returned from ADC registers,
1222 * because internal and external channels share the same channel
1223 * number in ADC registers. The differentiation is made only with
1224 * parameters definitions of driver.
1225 * @param __ADC_INSTANCE__ ADC instance
1226 * @param __CHANNEL__ This parameter can be one of the following values:
1227 * @arg @ref LL_ADC_CHANNEL_VREFINT
1228 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
1229 * @arg @ref LL_ADC_CHANNEL_VBAT
1230 * @arg @ref LL_ADC_CHANNEL_DACCH1
1231 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1232 * Value "1" if the internal channel selected is available on the ADC instance selected.
1233 */
1234 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1235 (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1236 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1237 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT))
1238
1239 /**
1240 * @brief Helper macro to define ADC analog watchdog parameter:
1241 * define a single channel to monitor with analog watchdog
1242 * from sequencer channel and groups definition.
1243 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1244 * Example:
1245 * LL_ADC_SetAnalogWDMonitChannels(
1246 * ADC1, LL_ADC_AWD1,
1247 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1248 * @param __CHANNEL__ This parameter can be one of the following values:
1249 * @arg @ref LL_ADC_CHANNEL_0
1250 * @arg @ref LL_ADC_CHANNEL_1
1251 * @arg @ref LL_ADC_CHANNEL_2
1252 * @arg @ref LL_ADC_CHANNEL_3
1253 * @arg @ref LL_ADC_CHANNEL_4
1254 * @arg @ref LL_ADC_CHANNEL_5
1255 * @arg @ref LL_ADC_CHANNEL_6
1256 * @arg @ref LL_ADC_CHANNEL_7
1257 * @arg @ref LL_ADC_CHANNEL_8
1258 * @arg @ref LL_ADC_CHANNEL_9
1259 * @arg @ref LL_ADC_CHANNEL_10
1260 * @arg @ref LL_ADC_CHANNEL_11
1261 * @arg @ref LL_ADC_CHANNEL_12
1262 * @arg @ref LL_ADC_CHANNEL_13
1263 * @arg @ref LL_ADC_CHANNEL_14
1264 * @arg @ref LL_ADC_CHANNEL_15 (1)
1265 * @arg @ref LL_ADC_CHANNEL_16 (1)
1266 * @arg @ref LL_ADC_CHANNEL_17 (1)
1267 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
1268 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
1269 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
1270 * @arg @ref LL_ADC_CHANNEL_DACCH1 (2)
1271 *
1272 * (1) On STM32WL, parameter can be set in ADC group sequencer
1273 * only if sequencer is set in mode "not fully configurable",
1274 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
1275 * (2) For ADC channel read back from ADC register,
1276 * comparison with internal channel parameter to be done
1277 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1278 * @param __GROUP__ This parameter can be one of the following values:
1279 * @arg @ref LL_ADC_GROUP_REGULAR
1280 * @retval Returned value can be one of the following values:
1281 * @arg @ref LL_ADC_AWD_DISABLE
1282 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1283 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1284 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1285 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1286 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1287 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1288 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1289 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1290 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1291 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1292 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1293 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1294 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1295 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1296 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1297 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1298 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1299 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1300 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1301 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
1302 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
1303 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
1304 * @arg @ref LL_ADC_AWD_CH_DACCH1_REG
1305 */
1306 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1307 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
1308
1309 /**
1310 * @brief Helper macro to set the value of ADC analog watchdog threshold high
1311 * or low in function of ADC resolution, when ADC resolution is
1312 * different of 12 bits.
1313 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
1314 * or @ref LL_ADC_SetAnalogWDThresholds().
1315 * Example, with a ADC resolution of 8 bits, to set the value of
1316 * analog watchdog threshold high (on 8 bits):
1317 * LL_ADC_SetAnalogWDThresholds
1318 * (< ADCx param >,
1319 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1320 * );
1321 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1322 * @arg @ref LL_ADC_RESOLUTION_12B
1323 * @arg @ref LL_ADC_RESOLUTION_10B
1324 * @arg @ref LL_ADC_RESOLUTION_8B
1325 * @arg @ref LL_ADC_RESOLUTION_6B
1326 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1327 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1328 */
1329 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1330 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1331
1332 /**
1333 * @brief Helper macro to get the value of ADC analog watchdog threshold high
1334 * or low in function of ADC resolution, when ADC resolution is
1335 * different of 12 bits.
1336 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1337 * Example, with a ADC resolution of 8 bits, to get the value of
1338 * analog watchdog threshold high (on 8 bits):
1339 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1340 * (LL_ADC_RESOLUTION_8B,
1341 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1342 * );
1343 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1344 * @arg @ref LL_ADC_RESOLUTION_12B
1345 * @arg @ref LL_ADC_RESOLUTION_10B
1346 * @arg @ref LL_ADC_RESOLUTION_8B
1347 * @arg @ref LL_ADC_RESOLUTION_6B
1348 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1349 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1350 */
1351 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1352 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
1353
1354 /**
1355 * @brief Helper macro to get the ADC analog watchdog threshold high
1356 * or low from raw value containing both thresholds concatenated.
1357 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1358 * Example, to get analog watchdog threshold high from the register raw value:
1359 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
1360 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
1361 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
1362 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
1363 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
1364 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1365 */
1366 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
1367 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
1368 & LL_ADC_AWD_THRESHOLD_LOW)
1369
1370 /**
1371 * @brief Helper macro to select the ADC common instance
1372 * to which is belonging the selected ADC instance.
1373 * @note ADC common register instance can be used for:
1374 * - Set parameters common to several ADC instances
1375 * - Multimode (for devices with several ADC instances)
1376 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1377 * @param __ADCx__ ADC instance
1378 * @retval ADC common register instance
1379 */
1380 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1381 (ADC_COMMON)
1382
1383 /**
1384 * @brief Helper macro to check if all ADC instances sharing the same
1385 * ADC common instance are disabled.
1386 * @note This check is required by functions with setting conditioned to
1387 * ADC state:
1388 * All ADC instances of the ADC common group must be disabled.
1389 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1390 * @note On devices with only 1 ADC common instance, parameter of this macro
1391 * is useless and can be ignored (parameter kept for compatibility
1392 * with devices featuring several ADC common instances).
1393 * @param __ADCXY_COMMON__ ADC common instance
1394 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1395 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1396 * are disabled.
1397 * Value "1" if at least one ADC instance sharing the same ADC common instance
1398 * is enabled.
1399 */
1400 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1401 LL_ADC_IsEnabled(ADC)
1402
1403 /**
1404 * @brief Helper macro to define the ADC conversion data full-scale digital
1405 * value corresponding to the selected ADC resolution.
1406 * @note ADC conversion data full-scale corresponds to voltage range
1407 * determined by analog voltage references Vref+ and Vref-
1408 * (refer to reference manual).
1409 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1410 * @arg @ref LL_ADC_RESOLUTION_12B
1411 * @arg @ref LL_ADC_RESOLUTION_10B
1412 * @arg @ref LL_ADC_RESOLUTION_8B
1413 * @arg @ref LL_ADC_RESOLUTION_6B
1414 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
1415 */
1416 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1417 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
1418
1419 /**
1420 * @brief Helper macro to convert the ADC conversion data from
1421 * a resolution to another resolution.
1422 * @param __DATA__ ADC conversion data to be converted
1423 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
1424 * This parameter can be one of the following values:
1425 * @arg @ref LL_ADC_RESOLUTION_12B
1426 * @arg @ref LL_ADC_RESOLUTION_10B
1427 * @arg @ref LL_ADC_RESOLUTION_8B
1428 * @arg @ref LL_ADC_RESOLUTION_6B
1429 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1430 * This parameter can be one of the following values:
1431 * @arg @ref LL_ADC_RESOLUTION_12B
1432 * @arg @ref LL_ADC_RESOLUTION_10B
1433 * @arg @ref LL_ADC_RESOLUTION_8B
1434 * @arg @ref LL_ADC_RESOLUTION_6B
1435 * @retval ADC conversion data to the requested resolution
1436 */
1437 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1438 __ADC_RESOLUTION_CURRENT__,\
1439 __ADC_RESOLUTION_TARGET__) \
1440 (((__DATA__) \
1441 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \
1442 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \
1443 )
1444
1445 /**
1446 * @brief Helper macro to calculate the voltage (unit: mVolt)
1447 * corresponding to a ADC conversion data (unit: digital value).
1448 * @note Analog reference voltage (Vref+) must be either known from
1449 * user board environment or can be calculated using ADC measurement
1450 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1451 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1452 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1453 * (unit: digital value).
1454 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1455 * @arg @ref LL_ADC_RESOLUTION_12B
1456 * @arg @ref LL_ADC_RESOLUTION_10B
1457 * @arg @ref LL_ADC_RESOLUTION_8B
1458 * @arg @ref LL_ADC_RESOLUTION_6B
1459 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1460 */
1461 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1462 __ADC_DATA__,\
1463 __ADC_RESOLUTION__) \
1464 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1465 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1466 )
1467
1468 /**
1469 * @brief Helper macro to calculate analog reference voltage (Vref+)
1470 * (unit: mVolt) from ADC conversion data of internal voltage
1471 * reference VrefInt.
1472 * @note Computation is using VrefInt calibration value
1473 * stored in system memory for each device during production.
1474 * @note This voltage depends on user board environment: voltage level
1475 * connected to pin Vref+.
1476 * On devices with small package, the pin Vref+ is not present
1477 * and internally bonded to pin Vdda.
1478 * @note On this STM32 series, calibration data of internal voltage reference
1479 * VrefInt corresponds to a resolution of 12 bits,
1480 * this is the recommended ADC resolution to convert voltage of
1481 * internal voltage reference VrefInt.
1482 * Otherwise, this macro performs the processing to scale
1483 * ADC conversion data to 12 bits.
1484 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1485 * of internal voltage reference VrefInt (unit: digital value).
1486 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1487 * @arg @ref LL_ADC_RESOLUTION_12B
1488 * @arg @ref LL_ADC_RESOLUTION_10B
1489 * @arg @ref LL_ADC_RESOLUTION_8B
1490 * @arg @ref LL_ADC_RESOLUTION_6B
1491 * @retval Analog reference voltage (unit: mV)
1492 */
1493 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1494 __ADC_RESOLUTION__) \
1495 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1496 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1497 (__ADC_RESOLUTION__), \
1498 LL_ADC_RESOLUTION_12B) \
1499 )
1500
1501 /**
1502 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1503 * from ADC conversion data of internal temperature sensor.
1504 * @note Computation is using temperature sensor calibration values
1505 * stored in system memory for each device during production.
1506 * @note Calculation formula:
1507 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1508 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1509 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1510 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1511 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1512 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1513 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1514 * TEMP_DEGC_CAL1 (calibrated in factory)
1515 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1516 * TEMP_DEGC_CAL2 (calibrated in factory)
1517 * Caution: Calculation relevancy under reserve that calibration
1518 * parameters are correct (address and data).
1519 * To calculate temperature using temperature sensor
1520 * datasheet typical values (generic values less, therefore
1521 * less accurate than calibrated values),
1522 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1523 * @note As calculation input, the analog reference voltage (Vref+) must be
1524 * defined as it impacts the ADC LSB equivalent voltage.
1525 * @note Analog reference voltage (Vref+) must be either known from
1526 * user board environment or can be calculated using ADC measurement
1527 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1528 * @note On this STM32 series, calibration data of temperature sensor
1529 * corresponds to a resolution of 12 bits,
1530 * this is the recommended ADC resolution to convert voltage of
1531 * temperature sensor.
1532 * Otherwise, this macro performs the processing to scale
1533 * ADC conversion data to 12 bits.
1534 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1535 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1536 * temperature sensor (unit: digital value).
1537 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1538 * sensor voltage has been measured.
1539 * This parameter can be one of the following values:
1540 * @arg @ref LL_ADC_RESOLUTION_12B
1541 * @arg @ref LL_ADC_RESOLUTION_10B
1542 * @arg @ref LL_ADC_RESOLUTION_8B
1543 * @arg @ref LL_ADC_RESOLUTION_6B
1544 * @retval Temperature (unit: degree Celsius)
1545 * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
1546 */
1547 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1548 __TEMPSENSOR_ADC_DATA__,\
1549 __ADC_RESOLUTION__)\
1550 ((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \
1551 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1552 (__ADC_RESOLUTION__), \
1553 LL_ADC_RESOLUTION_12B) \
1554 * (__VREFANALOG_VOLTAGE__)) \
1555 / TEMPSENSOR_CAL_VREFANALOG) \
1556 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1557 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1558 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1559 ) + TEMPSENSOR_CAL1_TEMP \
1560 ) \
1561 : \
1562 ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \
1563 )
1564
1565 /**
1566 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1567 * from ADC conversion data of internal temperature sensor.
1568 * @note Computation is using temperature sensor typical values
1569 * (refer to device datasheet).
1570 * @note Calculation formula:
1571 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1572 * / Avg_Slope + CALx_TEMP
1573 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1574 * (unit: digital value)
1575 * Avg_Slope = temperature sensor slope
1576 * (unit: uV/Degree Celsius)
1577 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1578 * temperature CALx_TEMP (unit: mV)
1579 * Caution: Calculation relevancy under reserve the temperature sensor
1580 * of the current device has characteristics in line with
1581 * datasheet typical values.
1582 * If temperature sensor calibration values are available on
1583 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1584 * temperature calculation will be more accurate using
1585 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1586 * @note As calculation input, the analog reference voltage (Vref+) must be
1587 * defined as it impacts the ADC LSB equivalent voltage.
1588 * @note Analog reference voltage (Vref+) must be either known from
1589 * user board environment or can be calculated using ADC measurement
1590 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1591 * @note ADC measurement data must correspond to a resolution of 12 bits
1592 * (full scale digital value 4095). If not the case, the data must be
1593 * preliminarily rescaled to an equivalent resolution of 12 bits.
1594 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value
1595 (unit: uV/DegCelsius).
1596 * On STM32WL, refer to device datasheet parameter "Avg_Slope".
1597 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value
1598 (at temperature and Vref+ defined in parameters below) (unit: mV).
1599 * On STM32WL, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
1600 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage
1601 (see parameter above) is corresponding (unit: mV)
1602 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV)
1603 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1604 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1605 * This parameter can be one of the following values:
1606 * @arg @ref LL_ADC_RESOLUTION_12B
1607 * @arg @ref LL_ADC_RESOLUTION_10B
1608 * @arg @ref LL_ADC_RESOLUTION_8B
1609 * @arg @ref LL_ADC_RESOLUTION_6B
1610 * @retval Temperature (unit: degree Celsius)
1611 */
1612 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1613 __TEMPSENSOR_TYP_CALX_V__,\
1614 __TEMPSENSOR_CALX_TEMP__,\
1615 __VREFANALOG_VOLTAGE__,\
1616 __TEMPSENSOR_ADC_DATA__,\
1617 __ADC_RESOLUTION__) \
1618 (((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1619 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1620 * 1000UL) \
1621 - \
1622 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1623 * 1000UL) \
1624 ) \
1625 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
1626 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
1627 )
1628
1629 /**
1630 * @}
1631 */
1632
1633 /**
1634 * @}
1635 */
1636
1637
1638 /* Exported functions --------------------------------------------------------*/
1639 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1640 * @{
1641 */
1642
1643 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1644 * @{
1645 */
1646 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1647 /* configuration of ADC instance, groups and multimode (if available): */
1648 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1649
1650 /**
1651 * @brief Function to help to configure DMA transfer from ADC: retrieve the
1652 * ADC register address from ADC instance and a list of ADC registers
1653 * intended to be used (most commonly) with DMA transfer.
1654 * @note These ADC registers are data registers:
1655 * when ADC conversion data is available in ADC data registers,
1656 * ADC generates a DMA transfer request.
1657 * @note This macro is intended to be used with LL DMA driver, refer to
1658 * function "LL_DMA_ConfigAddresses()".
1659 * Example:
1660 * LL_DMA_ConfigAddresses(DMA1,
1661 * LL_DMA_CHANNEL_1,
1662 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1663 * (uint32_t)&< array or variable >,
1664 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1665 * @note For devices with several ADC: in multimode, some devices
1666 * use a different data register outside of ADC instance scope
1667 * (common data register). This macro manages this register difference,
1668 * only ADC instance has to be set as parameter.
1669 * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1670 * @param ADCx ADC instance
1671 * @param Register This parameter can be one of the following values:
1672 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1673 * @retval ADC register address
1674 */
LL_ADC_DMA_GetRegAddr(ADC_TypeDef * ADCx,uint32_t Register)1675 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1676 {
1677 /* Prevent unused argument(s) compilation warning */
1678 (void)(Register);
1679
1680 /* Retrieve address of register DR */
1681 return (uint32_t) &(ADCx->DR);
1682 }
1683
1684 /**
1685 * @}
1686 */
1687
1688 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
1689 * ADC instances
1690 * @{
1691 */
1692
1693 /**
1694 * @brief Set parameter common to several ADC: Clock source and prescaler.
1695 * @note On this STM32 series, setting of this feature is conditioned to
1696 * ADC state:
1697 * All ADC instances of the ADC common group must be disabled.
1698 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1699 * ADC instance or by using helper macro helper macro
1700 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1701 * @rmtoll CCR PRESC LL_ADC_SetCommonClock
1702 * @param ADCxy_COMMON ADC common instance
1703 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1704 * @param CommonClock This parameter can be one of the following values:
1705 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1706 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1707 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1708 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1709 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1710 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1711 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1712 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1713 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1714 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1715 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1716 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1717 *
1718 * (1) ADC common clock asynchronous prescaler is applied to
1719 * each ADC instance if the corresponding ADC instance clock
1720 * is set to clock source asynchronous.
1721 * (refer to function @ref LL_ADC_SetClock() ).
1722 * @retval None
1723 */
LL_ADC_SetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t CommonClock)1724 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1725 {
1726 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
1727 }
1728
1729 /**
1730 * @brief Get parameter common to several ADC: Clock source and prescaler.
1731 * @rmtoll CCR PRESC LL_ADC_GetCommonClock
1732 * @param ADCxy_COMMON ADC common instance
1733 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1734 * @retval Returned value can be one of the following values:
1735 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1)
1736 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1)
1737 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1)
1738 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1)
1739 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1)
1740 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1)
1741 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1)
1742 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1)
1743 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1)
1744 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1)
1745 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
1746 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
1747 *
1748 * (1) ADC common clock asynchronous prescaler is applied to
1749 * each ADC instance if the corresponding ADC instance clock
1750 * is set to clock source asynchronous.
1751 * (refer to function @ref LL_ADC_SetClock() ).
1752 */
LL_ADC_GetCommonClock(ADC_Common_TypeDef * ADCxy_COMMON)1753 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
1754 {
1755 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
1756 }
1757
1758 /**
1759 * @brief Set parameter common to several ADC: measurement path to
1760 * internal channels (VrefInt, temperature sensor, ...).
1761 * Configure all paths (overwrite current configuration).
1762 * @note One or several values can be selected.
1763 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1764 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1765 * The values not selected are removed from configuration.
1766 * @note Stabilization time of measurement path to internal channel:
1767 * After enabling internal paths, before starting ADC conversion,
1768 * a delay is required for internal voltage reference and
1769 * temperature sensor stabilization time.
1770 * Refer to device datasheet.
1771 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1772 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1773 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1774 * @note ADC internal channel sampling time constraint:
1775 * For ADC conversion of internal channels,
1776 * a sampling time minimum value is required.
1777 * Refer to device datasheet.
1778 * @note On this STM32 series, setting of this feature is conditioned to
1779 * ADC state:
1780 * All ADC instances of the ADC common group must be disabled.
1781 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1782 * ADC instance or by using helper macro helper macro
1783 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1784 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
1785 * CCR TSEN LL_ADC_SetCommonPathInternalCh\n
1786 * CCR VBATEN LL_ADC_SetCommonPathInternalCh
1787 * @param ADCxy_COMMON ADC common instance
1788 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1789 * @param PathInternal This parameter can be a combination of the following values:
1790 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1791 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1792 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1793 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1794 * @retval None
1795 */
LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1796 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1797 {
1798 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
1799 }
1800
1801 /**
1802 * @brief Set parameter common to several ADC: measurement path to
1803 * internal channels (VrefInt, temperature sensor, ...).
1804 * Add paths to the current configuration.
1805 * @note One or several values can be selected.
1806 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1807 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1808 * @note Stabilization time of measurement path to internal channel:
1809 * After enabling internal paths, before starting ADC conversion,
1810 * a delay is required for internal voltage reference and
1811 * temperature sensor stabilization time.
1812 * Refer to device datasheet.
1813 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
1814 * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
1815 * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
1816 * @note ADC internal channel sampling time constraint:
1817 * For ADC conversion of internal channels,
1818 * a sampling time minimum value is required.
1819 * Refer to device datasheet.
1820 * @note On this STM32 series, setting of this feature is conditioned to
1821 * ADC state:
1822 * All ADC instances of the ADC common group must be disabled.
1823 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1824 * ADC instance or by using helper macro helper macro
1825 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1826 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
1827 * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n
1828 * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd
1829 * @param ADCxy_COMMON ADC common instance
1830 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1831 * @param PathInternal This parameter can be a combination of the following values:
1832 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1833 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1834 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1835 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1836 * @retval None
1837 */
LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1838 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1839 {
1840 SET_BIT(ADCxy_COMMON->CCR, PathInternal);
1841 }
1842
1843 /**
1844 * @brief Set parameter common to several ADC: measurement path to
1845 * internal channels (VrefInt, temperature sensor, ...).
1846 * Remove paths to the current configuration.
1847 * @note One or several values can be selected.
1848 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1849 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1850 * @note On this STM32 series, setting of this feature is conditioned to
1851 * ADC state:
1852 * All ADC instances of the ADC common group must be disabled.
1853 * This check can be done with function @ref LL_ADC_IsEnabled() for each
1854 * ADC instance or by using helper macro helper macro
1855 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
1856 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
1857 * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n
1858 * CCR VBATEN LL_ADC_SetCommonPathInternalChRem
1859 * @param ADCxy_COMMON ADC common instance
1860 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1861 * @param PathInternal This parameter can be a combination of the following values:
1862 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1863 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1864 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1865 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1866 * @retval None
1867 */
LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef * ADCxy_COMMON,uint32_t PathInternal)1868 __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1869 {
1870 CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
1871 }
1872
1873 /**
1874 * @brief Get parameter common to several ADC: measurement path to internal
1875 * channels (VrefInt, temperature sensor, ...).
1876 * @note One or several values can be selected.
1877 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1878 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1879 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
1880 * CCR TSEN LL_ADC_GetCommonPathInternalCh\n
1881 * CCR VBATEN LL_ADC_GetCommonPathInternalCh
1882 * @param ADCxy_COMMON ADC common instance
1883 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1884 * @retval Returned value can be a combination of the following values:
1885 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1886 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1887 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1888 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
1889 */
LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef * ADCxy_COMMON)1890 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1891 {
1892 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
1893 }
1894
1895 /**
1896 * @}
1897 */
1898
1899 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1900 * @{
1901 */
1902
1903 /**
1904 * @brief Set ADC instance clock source and prescaler.
1905 * @note On this STM32 series, setting of this feature is conditioned to
1906 * ADC state:
1907 * ADC must be disabled.
1908 * @rmtoll CFGR2 CKMODE LL_ADC_SetClock
1909 * @param ADCx ADC instance
1910 * @param ClockSource This parameter can be one of the following values:
1911 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1912 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1913 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1914 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1915 *
1916 * (1) Asynchronous clock prescaler can be configured using
1917 * function @ref LL_ADC_SetCommonClock().\n
1918 * (2) Caution: This parameter has some clock ratio constraints:
1919 * This configuration must be enabled only if PCLK has a 50%
1920 * duty clock cycle (APB prescaler configured inside the RCC
1921 * must be bypassed and the system clock must by 50% duty
1922 * cycle).
1923 * Refer to reference manual.
1924 * @retval None
1925 */
LL_ADC_SetClock(ADC_TypeDef * ADCx,uint32_t ClockSource)1926 __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
1927 {
1928 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
1929 }
1930
1931 /**
1932 * @brief Get ADC instance clock source and prescaler.
1933 * @rmtoll CFGR2 CKMODE LL_ADC_GetClock
1934 * @param ADCx ADC instance
1935 * @retval Returned value can be one of the following values:
1936 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
1937 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
1938 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
1939 * @arg @ref LL_ADC_CLOCK_ASYNC (1)
1940 *
1941 * (1) Asynchronous clock prescaler can be retrieved using
1942 * function @ref LL_ADC_GetCommonClock().\n
1943 * (2) Caution: This parameter has some clock ratio constraints:
1944 * This configuration must be enabled only if PCLK has a 50%
1945 * duty clock cycle (APB prescaler configured inside the RCC
1946 * must be bypassed and the system clock must by 50% duty
1947 * cycle).
1948 * Refer to reference manual.
1949 */
LL_ADC_GetClock(ADC_TypeDef * ADCx)1950 __STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
1951 {
1952 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
1953 }
1954
1955 /**
1956 * @brief Set ADC calibration factor in the mode single-ended
1957 * or differential (for devices with differential mode available).
1958 * @note This function is intended to set calibration parameters
1959 * without having to perform a new calibration using
1960 * @ref LL_ADC_StartCalibration().
1961 * @note On this STM32 series, setting of this feature is conditioned to
1962 * ADC state:
1963 * ADC must be enabled, without calibration on going, without conversion
1964 * on going on group regular.
1965 * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor
1966 * @param ADCx ADC instance
1967 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
1968 * @retval None
1969 */
LL_ADC_SetCalibrationFactor(ADC_TypeDef * ADCx,uint32_t CalibrationFactor)1970 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
1971 {
1972 MODIFY_REG(ADCx->CALFACT,
1973 ADC_CALFACT_CALFACT,
1974 CalibrationFactor);
1975 }
1976
1977 /**
1978 * @brief Get ADC calibration factor in the mode single-ended
1979 * or differential (for devices with differential mode available).
1980 * @note Calibration factors are set by hardware after performing
1981 * a calibration run using function @ref LL_ADC_StartCalibration().
1982 * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor
1983 * @param ADCx ADC instance
1984 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
1985 */
LL_ADC_GetCalibrationFactor(ADC_TypeDef * ADCx)1986 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
1987 {
1988 return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
1989 }
1990
1991 /**
1992 * @brief Set ADC resolution.
1993 * Refer to reference manual for alignments formats
1994 * dependencies to ADC resolutions.
1995 * @note On this STM32 series, setting of this feature is conditioned to
1996 * ADC state:
1997 * ADC must be disabled.
1998 * @rmtoll CFGR1 RES LL_ADC_SetResolution
1999 * @param ADCx ADC instance
2000 * @param Resolution This parameter can be one of the following values:
2001 * @arg @ref LL_ADC_RESOLUTION_12B
2002 * @arg @ref LL_ADC_RESOLUTION_10B
2003 * @arg @ref LL_ADC_RESOLUTION_8B
2004 * @arg @ref LL_ADC_RESOLUTION_6B
2005 * @retval None
2006 */
LL_ADC_SetResolution(ADC_TypeDef * ADCx,uint32_t Resolution)2007 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2008 {
2009 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
2010 }
2011
2012 /**
2013 * @brief Get ADC resolution.
2014 * Refer to reference manual for alignments formats
2015 * dependencies to ADC resolutions.
2016 * @rmtoll CFGR1 RES LL_ADC_GetResolution
2017 * @param ADCx ADC instance
2018 * @retval Returned value can be one of the following values:
2019 * @arg @ref LL_ADC_RESOLUTION_12B
2020 * @arg @ref LL_ADC_RESOLUTION_10B
2021 * @arg @ref LL_ADC_RESOLUTION_8B
2022 * @arg @ref LL_ADC_RESOLUTION_6B
2023 */
LL_ADC_GetResolution(ADC_TypeDef * ADCx)2024 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2025 {
2026 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
2027 }
2028
2029 /**
2030 * @brief Set ADC conversion data alignment.
2031 * @note Refer to reference manual for alignments formats
2032 * dependencies to ADC resolutions.
2033 * @note On this STM32 series, setting of this feature is conditioned to
2034 * ADC state:
2035 * ADC must be disabled.
2036 * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
2037 * @param ADCx ADC instance
2038 * @param DataAlignment This parameter can be one of the following values:
2039 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2040 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2041 * @retval None
2042 */
LL_ADC_SetDataAlignment(ADC_TypeDef * ADCx,uint32_t DataAlignment)2043 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2044 {
2045 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
2046 }
2047
2048 /**
2049 * @brief Get ADC conversion data alignment.
2050 * @note Refer to reference manual for alignments formats
2051 * dependencies to ADC resolutions.
2052 * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
2053 * @param ADCx ADC instance
2054 * @retval Returned value can be one of the following values:
2055 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2056 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2057 */
LL_ADC_GetDataAlignment(ADC_TypeDef * ADCx)2058 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2059 {
2060 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
2061 }
2062
2063 /**
2064 * @brief Set ADC low power mode.
2065 * @note Description of ADC low power modes:
2066 * - ADC low power mode "auto wait": Dynamic low power mode,
2067 * ADC conversions occurrences are limited to the minimum necessary
2068 * in order to reduce power consumption.
2069 * New ADC conversion starts only when the previous
2070 * unitary conversion data (for ADC group regular)
2071 * has been retrieved by user software.
2072 * In the meantime, ADC remains idle: does not performs any
2073 * other conversion.
2074 * This mode allows to automatically adapt the ADC conversions
2075 * triggers to the speed of the software that reads the data.
2076 * Moreover, this avoids risk of overrun for low frequency
2077 * applications.
2078 * How to use this low power mode:
2079 * - It is not recommended to use with interruption or DMA
2080 * since these modes have to clear immediately the EOC flag
2081 * (by CPU to free the IRQ pending event or by DMA).
2082 * Auto wait will work but fort a very short time, discarding
2083 * its intended benefit (except specific case of high load of CPU
2084 * or DMA transfers which can justify usage of auto wait).
2085 * - Do use with polling: 1. Start conversion,
2086 * 2. Later on, when conversion data is needed: poll for end of
2087 * conversion to ensure that conversion is completed and
2088 * retrieve ADC conversion data. This will trig another
2089 * ADC conversion start.
2090 * - ADC low power mode "auto power-off" (feature available on
2091 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2092 * the ADC automatically powers-off after a conversion and
2093 * automatically wakes up when a new conversion is triggered
2094 * (with startup time between trigger and start of sampling).
2095 * This feature can be combined with low power mode "auto wait".
2096 * @note With ADC low power mode "auto wait", the ADC conversion data read
2097 * is corresponding to previous ADC conversion start, independently
2098 * of delay during which ADC was idle.
2099 * Therefore, the ADC conversion data may be outdated: does not
2100 * correspond to the current voltage level on the selected
2101 * ADC channel.
2102 * @note On this STM32 series, setting of this feature is conditioned to
2103 * ADC state:
2104 * ADC must be disabled.
2105 * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
2106 * CFGR1 AUTOFF LL_ADC_SetLowPowerMode
2107 * @param ADCx ADC instance
2108 * @param LowPowerMode This parameter can be one of the following values:
2109 * @arg @ref LL_ADC_LP_MODE_NONE
2110 * @arg @ref LL_ADC_LP_AUTOWAIT
2111 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2112 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2113 * @retval None
2114 */
LL_ADC_SetLowPowerMode(ADC_TypeDef * ADCx,uint32_t LowPowerMode)2115 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2116 {
2117 MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
2118 }
2119
2120 /**
2121 * @brief Get ADC low power mode:
2122 * @note Description of ADC low power modes:
2123 * - ADC low power mode "auto wait": Dynamic low power mode,
2124 * ADC conversions occurrences are limited to the minimum necessary
2125 * in order to reduce power consumption.
2126 * New ADC conversion starts only when the previous
2127 * unitary conversion data (for ADC group regular)
2128 * has been retrieved by user software.
2129 * In the meantime, ADC remains idle: does not performs any
2130 * other conversion.
2131 * This mode allows to automatically adapt the ADC conversions
2132 * triggers to the speed of the software that reads the data.
2133 * Moreover, this avoids risk of overrun for low frequency
2134 * applications.
2135 * How to use this low power mode:
2136 * - It is not recommended to use with interruption or DMA
2137 * since these modes have to clear immediately the EOC flag
2138 * (by CPU to free the IRQ pending event or by DMA).
2139 * Auto wait will work but fort a very short time, discarding
2140 * its intended benefit (except specific case of high load of CPU
2141 * or DMA transfers which can justify usage of auto wait).
2142 * - Do use with polling: 1. Start conversion,
2143 * 2. Later on, when conversion data is needed: poll for end of
2144 * conversion to ensure that conversion is completed and
2145 * retrieve ADC conversion data. This will trig another
2146 * ADC conversion start.
2147 * - ADC low power mode "auto power-off" (feature available on
2148 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2149 * the ADC automatically powers-off after a conversion and
2150 * automatically wakes up when a new conversion is triggered
2151 * (with startup time between trigger and start of sampling).
2152 * This feature can be combined with low power mode "auto wait".
2153 * @note With ADC low power mode "auto wait", the ADC conversion data read
2154 * is corresponding to previous ADC conversion start, independently
2155 * of delay during which ADC was idle.
2156 * Therefore, the ADC conversion data may be outdated: does not
2157 * correspond to the current voltage level on the selected
2158 * ADC channel.
2159 * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
2160 * CFGR1 AUTOFF LL_ADC_GetLowPowerMode
2161 * @param ADCx ADC instance
2162 * @retval Returned value can be one of the following values:
2163 * @arg @ref LL_ADC_LP_MODE_NONE
2164 * @arg @ref LL_ADC_LP_AUTOWAIT
2165 * @arg @ref LL_ADC_LP_AUTOPOWEROFF
2166 * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
2167 */
LL_ADC_GetLowPowerMode(ADC_TypeDef * ADCx)2168 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2169 {
2170 return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
2171 }
2172
2173 /**
2174 * @brief Set ADC trigger frequency mode.
2175 * @note ADC trigger frequency mode must be set to low frequency when
2176 * a duration is exceeded before ADC conversion start trigger event
2177 * (between ADC enable and ADC conversion start trigger event
2178 * or between two ADC conversion start trigger event).
2179 * Duration value: Refer to device datasheet, parameter "tIdle".
2180 * @note When ADC trigger frequency mode is set to low frequency,
2181 * some rearm cycles are inserted before performing ADC conversion
2182 * start, inducing a delay of 2 ADC clock cycles.
2183 * @note Usage of ADC trigger frequency mode with ADC low power mode:
2184 * - Low power mode auto wait: Only the first ADC conversion
2185 * start trigger inserts the rearm delay.
2186 * - Low power mode auto power-off: ADC trigger frequency mode
2187 * is discarded.
2188 * @note On this STM32 series, setting of this feature is conditioned to
2189 * ADC state:
2190 * ADC must be disabled.
2191 * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode
2192 * @param ADCx ADC instance
2193 * @param TriggerFrequencyMode This parameter can be one of the following values:
2194 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2195 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2196 * @retval None
2197 */
LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef * ADCx,uint32_t TriggerFrequencyMode)2198 __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
2199 {
2200 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
2201 }
2202
2203 /**
2204 * @brief Get ADC trigger frequency mode.
2205 * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode
2206 * @param ADCx ADC instance
2207 * @retval Returned value can be one of the following values:
2208 * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
2209 * @arg @ref LL_ADC_TRIGGER_FREQ_LOW
2210 */
LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef * ADCx)2211 __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx)
2212 {
2213 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
2214 }
2215
2216 /**
2217 * @brief Set sampling time common to a group of channels.
2218 * @note Unit: ADC clock cycles.
2219 * @note On this STM32 series, sampling time scope is on ADC instance:
2220 * Sampling time common to all channels.
2221 * (on some other STM32 families, sampling time is channel wise)
2222 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2223 * converted:
2224 * sampling time constraints must be respected (sampling time can be
2225 * adjusted in function of ADC clock frequency and sampling time
2226 * setting).
2227 * Refer to device datasheet for timings values (parameters TS_vrefint,
2228 * TS_temp, ...).
2229 * @note Conversion time is the addition of sampling time and processing time.
2230 * On this STM32 series, ADC processing time is:
2231 * - 12.5 ADC clock cycles at ADC resolution 12 bits
2232 * - 10.5 ADC clock cycles at ADC resolution 10 bits
2233 * - 8.5 ADC clock cycles at ADC resolution 8 bits
2234 * - 6.5 ADC clock cycles at ADC resolution 6 bits
2235 * @note In case of ADC conversion of internal channel (VrefInt,
2236 * temperature sensor, ...), a sampling time minimum value
2237 * is required.
2238 * Refer to device datasheet.
2239 * @note On this STM32 series, setting of this feature is conditioned to
2240 * ADC state:
2241 * ADC must be disabled or enabled without conversion on going
2242 * on group regular.
2243 * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n
2244 * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels
2245 * @param ADCx ADC instance
2246 * @param SamplingTimeY This parameter can be one of the following values:
2247 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2248 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2249 * @param SamplingTime This parameter can be one of the following values:
2250 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2251 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2252 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2253 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2254 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2255 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2256 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2257 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2258 * @retval None
2259 */
LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY,uint32_t SamplingTime)2260 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
2261 uint32_t SamplingTime)
2262 {
2263 MODIFY_REG(ADCx->SMPR,
2264 ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
2265 SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2266 }
2267
2268 /**
2269 * @brief Get sampling time common to a group of channels.
2270 * @note Unit: ADC clock cycles.
2271 * @note On this STM32 series, sampling time scope is on ADC instance:
2272 * Sampling time common to all channels.
2273 * (on some other STM32 families, sampling time is channel wise)
2274 * @note Conversion time is the addition of sampling time and processing time.
2275 * Refer to reference manual for ADC processing time of
2276 * this STM32 series.
2277 * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n
2278 * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels
2279 * @param ADCx ADC instance
2280 * @param SamplingTimeY This parameter can be one of the following values:
2281 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
2282 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
2283 * @retval Returned value can be one of the following values:
2284 * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2285 * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
2286 * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2287 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
2288 * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
2289 * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
2290 * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
2291 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
2292 */
LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef * ADCx,uint32_t SamplingTimeY)2293 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
2294 {
2295 return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
2296 >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
2297 }
2298
2299 /**
2300 * @}
2301 */
2302
2303 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
2304 * @{
2305 */
2306
2307 /**
2308 * @brief Set ADC group regular conversion trigger source:
2309 * internal (SW start) or from external peripheral (timer event,
2310 * external interrupt line).
2311 * @note On this STM32 series, setting trigger source to external trigger
2312 * also set trigger polarity to rising edge
2313 * (default setting for compatibility with some ADC on other
2314 * STM32 families having this setting set by HW default value).
2315 * In case of need to modify trigger edge, use
2316 * function @ref LL_ADC_REG_SetTriggerEdge().
2317 * @note On this STM32 series, ADC trigger frequency mode must be set
2318 * in function of frequency of ADC group regular conversion trigger.
2319 * Refer to description of function
2320 * @ref LL_ADC_SetTriggerFrequencyMode().
2321 * @note Availability of parameters of trigger sources from timer
2322 * depends on timers availability on the selected device.
2323 * @note On this STM32 series, setting of this feature is conditioned to
2324 * ADC state:
2325 * ADC must be disabled.
2326 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
2327 * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
2328 * @param ADCx ADC instance
2329 * @param TriggerSource This parameter can be one of the following values:
2330 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2331 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2332 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2333 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2334 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2335 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2336 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2337 * @retval None
2338 */
LL_ADC_REG_SetTriggerSource(ADC_TypeDef * ADCx,uint32_t TriggerSource)2339 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2340 {
2341 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
2342 }
2343
2344 /**
2345 * @brief Get ADC group regular conversion trigger source:
2346 * internal (SW start) or from external peripheral (timer event,
2347 * external interrupt line).
2348 * @note To determine whether group regular trigger source is
2349 * internal (SW start) or external, without detail
2350 * of which peripheral is selected as external trigger,
2351 * (equivalent to
2352 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
2353 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
2354 * @note Availability of parameters of trigger sources from timer
2355 * depends on timers availability on the selected device.
2356 * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
2357 * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
2358 * @param ADCx ADC instance
2359 * @retval Returned value can be one of the following values:
2360 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
2361 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
2362 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
2363 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
2364 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3
2365 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4
2366 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
2367 */
LL_ADC_REG_GetTriggerSource(ADC_TypeDef * ADCx)2368 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
2369 {
2370 __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
2371
2372 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2373 /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
2374 uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2375
2376 /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
2377 /* to match with triggers literals definition. */
2378 return ((trigger_source
2379 & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL)
2380 | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN)
2381 );
2382 }
2383
2384 /**
2385 * @brief Get ADC group regular conversion trigger source internal (SW start)
2386 * or external.
2387 * @note In case of group regular trigger source set to external trigger,
2388 * to determine which peripheral is selected as external trigger,
2389 * use function @ref LL_ADC_REG_GetTriggerSource().
2390 * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
2391 * @param ADCx ADC instance
2392 * @retval Value "0" if trigger source external trigger
2393 * Value "1" if trigger source SW start.
2394 */
LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef * ADCx)2395 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2396 {
2397 return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
2398 }
2399
2400 /**
2401 * @brief Set ADC group regular conversion trigger polarity.
2402 * @note Applicable only for trigger source set to external trigger.
2403 * @note On this STM32 series, setting of this feature is conditioned to
2404 * ADC state:
2405 * ADC must be disabled.
2406 * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
2407 * @param ADCx ADC instance
2408 * @param ExternalTriggerEdge This parameter can be one of the following values:
2409 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2410 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2411 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2412 * @retval None
2413 */
LL_ADC_REG_SetTriggerEdge(ADC_TypeDef * ADCx,uint32_t ExternalTriggerEdge)2414 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
2415 {
2416 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
2417 }
2418
2419 /**
2420 * @brief Get ADC group regular conversion trigger polarity.
2421 * @note Applicable only for trigger source set to external trigger.
2422 * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
2423 * @param ADCx ADC instance
2424 * @retval Returned value can be one of the following values:
2425 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
2426 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
2427 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
2428 */
LL_ADC_REG_GetTriggerEdge(ADC_TypeDef * ADCx)2429 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
2430 {
2431 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
2432 }
2433
2434 /**
2435 * @brief Set ADC group regular sequencer configuration flexibility.
2436 * @note On this STM32 series, ADC group regular sequencer both modes
2437 * "fully configurable" or "not fully configurable" are
2438 * available:
2439 * - sequencer configured to fully configurable:
2440 * sequencer length and each rank
2441 * affectation to a channel are configurable.
2442 * Refer to description of function
2443 * @ref LL_ADC_REG_SetSequencerLength().
2444 * - sequencer configured to not fully configurable:
2445 * sequencer length and each rank affectation to a channel
2446 * are fixed by channel HW number.
2447 * Refer to description of function
2448 * @ref LL_ADC_REG_SetSequencerChannels().
2449 * @note On this STM32 series, after modifying sequencer (functions
2450 * @ref LL_ADC_REG_SetSequencerLength()
2451 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2452 * it is mandatory to wait for the assertion of CCRDY flag
2453 * Otherwise, some actions may be ignored.
2454 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2455 * for more details.
2456 * @note On this STM32 series, setting of this feature is conditioned to
2457 * ADC state:
2458 * ADC must be disabled.
2459 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2460 * @param ADCx ADC instance
2461 * @param Configurability This parameter can be one of the following values:
2462 * @arg @ref LL_ADC_REG_SEQ_FIXED
2463 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2464 * @retval None
2465 */
LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef * ADCx,uint32_t Configurability)2466 __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
2467 {
2468 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
2469 }
2470
2471 /**
2472 * @brief Get ADC group regular sequencer configuration flexibility.
2473 * @note On this STM32 series, ADC group regular sequencer both modes
2474 * "fully configurable" or "not fully configurable" are
2475 * available:
2476 * - sequencer configured to fully configurable:
2477 * sequencer length and each rank
2478 * affectation to a channel are configurable.
2479 * Refer to description of function
2480 * @ref LL_ADC_REG_SetSequencerLength().
2481 * - sequencer configured to not fully configurable:
2482 * sequencer length and each rank affectation to a channel
2483 * are fixed by channel HW number.
2484 * Refer to description of function
2485 * @ref LL_ADC_REG_SetSequencerChannels().
2486 * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable
2487 * @param ADCx ADC instance
2488 * @retval Returned value can be one of the following values:
2489 * @arg @ref LL_ADC_REG_SEQ_FIXED
2490 * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
2491 */
LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef * ADCx)2492 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx)
2493 {
2494 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
2495 }
2496
2497 /**
2498 * @brief Set ADC group regular sequencer length and scan direction.
2499 * @note Description of ADC group regular sequencer features:
2500 * - For devices with sequencer fully configurable
2501 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2502 * sequencer length and each rank affectation to a channel
2503 * are configurable.
2504 * This function performs configuration of:
2505 * - Sequence length: Number of ranks in the scan sequence.
2506 * - Sequence direction: Unless specified in parameters, sequencer
2507 * scan direction is forward (from rank 1 to rank n).
2508 * Sequencer ranks are selected using
2509 * function "LL_ADC_REG_SetSequencerRanks()".
2510 * - For devices with sequencer not fully configurable
2511 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2512 * sequencer length and each rank affectation to a channel
2513 * are defined by channel number.
2514 * This function performs configuration of:
2515 * - Sequence length: Number of ranks in the scan sequence is
2516 * defined by number of channels set in the sequence,
2517 * rank of each channel is fixed by channel HW number.
2518 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2519 * - Sequence direction: Unless specified in parameters, sequencer
2520 * scan direction is forward (from lowest channel number to
2521 * highest channel number).
2522 * Sequencer ranks are selected using
2523 * function "LL_ADC_REG_SetSequencerChannels()".
2524 * To set scan direction differently, refer to function
2525 * @ref LL_ADC_REG_SetSequencerScanDirection().
2526 * @note On this STM32 series, ADC group regular sequencer both modes
2527 * "fully configurable" or "not fully configurable"
2528 * are available, they can be chosen using
2529 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2530 * @note On this STM32 series, after modifying sequencer (functions
2531 * @ref LL_ADC_REG_SetSequencerLength()
2532 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2533 * it is mandatory to wait for the assertion of CCRDY flag
2534 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2535 * Otherwise, some actions may be ignored.
2536 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2537 * for more details.
2538 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2539 * ADC conversion on only 1 channel.
2540 * @note On this STM32 series, setting of this feature is conditioned to
2541 * ADC state:
2542 * ADC must be disabled or enabled without conversion on going
2543 * on group regular.
2544 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n
2545 * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n
2546 * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n
2547 * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n
2548 * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n
2549 * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n
2550 * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n
2551 * CHSELR SQ8 LL_ADC_REG_SetSequencerLength
2552 * @param ADCx ADC instance
2553 * @param SequencerNbRanks This parameter can be one of the following values:
2554 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2555 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2556 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2557 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2558 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2559 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2560 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2561 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2562 * @retval None
2563 */
LL_ADC_REG_SetSequencerLength(ADC_TypeDef * ADCx,uint32_t SequencerNbRanks)2564 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2565 {
2566 SET_BIT(ADCx->CHSELR, SequencerNbRanks);
2567 }
2568
2569 /**
2570 * @brief Get ADC group regular sequencer length and scan direction.
2571 * @note Description of ADC group regular sequencer features:
2572 * - For devices with sequencer fully configurable
2573 * (function "LL_ADC_REG_SetSequencerRanks()" available):
2574 * sequencer length and each rank affectation to a channel
2575 * are configurable.
2576 * This function retrieves:
2577 * - Sequence length: Number of ranks in the scan sequence.
2578 * - Sequence direction: Unless specified in parameters, sequencer
2579 * scan direction is forward (from rank 1 to rank n).
2580 * Sequencer ranks are selected using
2581 * function "LL_ADC_REG_SetSequencerRanks()".
2582 * - For devices with sequencer not fully configurable
2583 * (function "LL_ADC_REG_SetSequencerChannels()" available):
2584 * sequencer length and each rank affectation to a channel
2585 * are defined by channel number.
2586 * This function retrieves:
2587 * - Sequence length: Number of ranks in the scan sequence is
2588 * defined by number of channels set in the sequence,
2589 * rank of each channel is fixed by channel HW number.
2590 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2591 * - Sequence direction: Unless specified in parameters, sequencer
2592 * scan direction is forward (from lowest channel number to
2593 * highest channel number).
2594 * Sequencer ranks are selected using
2595 * function "LL_ADC_REG_SetSequencerChannels()".
2596 * To set scan direction differently, refer to function
2597 * @ref LL_ADC_REG_SetSequencerScanDirection().
2598 * @note On this STM32 series, ADC group regular sequencer both modes
2599 * "fully configurable" or "not fully configurable"
2600 * are available, they can be chosen using
2601 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2602 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2603 * ADC conversion on only 1 channel.
2604 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n
2605 * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n
2606 * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n
2607 * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n
2608 * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n
2609 * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n
2610 * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n
2611 * CHSELR SQ8 LL_ADC_REG_GetSequencerLength
2612 * @param ADCx ADC instance
2613 * @retval Returned value can be one of the following values:
2614 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
2615 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
2616 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
2617 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
2618 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
2619 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
2620 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
2621 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
2622 */
LL_ADC_REG_GetSequencerLength(ADC_TypeDef * ADCx)2623 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2624 {
2625 __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
2626 uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
2627 uint32_t rank_index;
2628 uint32_t rank_shifted;
2629
2630 /* Parse register for end of sequence identifier */
2631 /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank
2632 (ADC_CHSELR_SQ2), value "4" to length of end of sequence
2633 identifier (0xF) */
2634 for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U)
2635 {
2636 rank_shifted = (uint32_t)(0xF0UL << rank_index);
2637 if ((channels_ranks & rank_shifted) == rank_shifted)
2638 {
2639 sequencer_length = rank_shifted;
2640 break;
2641 }
2642 }
2643
2644 return sequencer_length;
2645 }
2646
2647 /**
2648 * @brief Set ADC group regular sequencer scan direction.
2649 * @note On this STM32 series, parameter relevant only is sequencer is set
2650 * to mode not fully configurable,
2651 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2652 * @note On some other STM32 series, this setting is not available and
2653 * the default scan direction is forward.
2654 * @note On this STM32 series, after modifying sequencer (functions
2655 * @ref LL_ADC_REG_SetSequencerLength()
2656 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2657 * it is mandatory to wait for the assertion of CCRDY flag
2658 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2659 * Otherwise, some actions may be ignored.
2660 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2661 * for more details.
2662 * @note On this STM32 series, setting of this feature is conditioned to
2663 * ADC state:
2664 * ADC must be disabled.
2665 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
2666 * @param ADCx ADC instance
2667 * @param ScanDirection This parameter can be one of the following values:
2668 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2669 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2670 * @retval None
2671 */
LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef * ADCx,uint32_t ScanDirection)2672 __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
2673 {
2674 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
2675 }
2676
2677 /**
2678 * @brief Get ADC group regular sequencer scan direction.
2679 * @note On this STM32 series, parameter relevant only is sequencer is set
2680 * to mode not fully configurable,
2681 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2682 * @note On some other STM32 families, this setting is not available and
2683 * the default scan direction is forward.
2684 * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
2685 * @param ADCx ADC instance
2686 * @retval Returned value can be one of the following values:
2687 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
2688 * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
2689 */
LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef * ADCx)2690 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
2691 {
2692 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
2693 }
2694
2695 /**
2696 * @brief Set ADC group regular sequencer discontinuous mode:
2697 * sequence subdivided and scan conversions interrupted every selected
2698 * number of ranks.
2699 * @note It is not possible to enable both ADC group regular
2700 * continuous mode and sequencer discontinuous mode.
2701 * @note On this STM32 series, setting of this feature is conditioned to
2702 * ADC state:
2703 * ADC must be disabled.
2704 * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2705 * @param ADCx ADC instance
2706 * @param SeqDiscont This parameter can be one of the following values:
2707 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2708 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2709 * @retval None
2710 */
LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef * ADCx,uint32_t SeqDiscont)2711 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2712 {
2713 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
2714 }
2715
2716 /**
2717 * @brief Get ADC group regular sequencer discontinuous mode:
2718 * sequence subdivided and scan conversions interrupted every selected
2719 * number of ranks.
2720 * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2721 * @param ADCx ADC instance
2722 * @retval Returned value can be one of the following values:
2723 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2724 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2725 */
LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef * ADCx)2726 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2727 {
2728 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
2729 }
2730
2731 /**
2732 * @brief Set ADC group regular sequence: channel on the selected
2733 * scan sequence rank.
2734 * @note This function performs configuration of:
2735 * - Channels ordering into each rank of scan sequence:
2736 * whatever channel can be placed into whatever rank.
2737 * @note On this STM32 series, ADC group regular sequencer is
2738 * fully configurable: sequencer length and each rank
2739 * affectation to a channel are configurable.
2740 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2741 * @note Depending on devices and packages, some channels may not be available.
2742 * Refer to device datasheet for channels availability.
2743 * @note On this STM32 series, to measure internal channels (VrefInt,
2744 * TempSensor, ...), measurement paths to internal channels must be
2745 * enabled separately.
2746 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2747 * @note On this STM32 series, after modifying sequencer (functions
2748 * @ref LL_ADC_REG_SetSequencerLength()
2749 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2750 * it is mandatory to wait for the assertion of CCRDY flag
2751 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2752 * Otherwise, some actions may be ignored.
2753 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2754 * for more details.
2755 * @note On this STM32 series, setting of this feature is conditioned to
2756 * ADC state:
2757 * ADC must be disabled or enabled without conversion on going
2758 * on group regular.
2759 * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n
2760 * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n
2761 * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n
2762 * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n
2763 * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n
2764 * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n
2765 * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n
2766 * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks
2767 * @param ADCx ADC instance
2768 * @param Rank This parameter can be one of the following values:
2769 * @arg @ref LL_ADC_REG_RANK_1
2770 * @arg @ref LL_ADC_REG_RANK_2
2771 * @arg @ref LL_ADC_REG_RANK_3
2772 * @arg @ref LL_ADC_REG_RANK_4
2773 * @arg @ref LL_ADC_REG_RANK_5
2774 * @arg @ref LL_ADC_REG_RANK_6
2775 * @arg @ref LL_ADC_REG_RANK_7
2776 * @arg @ref LL_ADC_REG_RANK_8
2777 * @param Channel This parameter can be one of the following values:
2778 * @arg @ref LL_ADC_CHANNEL_0
2779 * @arg @ref LL_ADC_CHANNEL_1
2780 * @arg @ref LL_ADC_CHANNEL_2
2781 * @arg @ref LL_ADC_CHANNEL_3
2782 * @arg @ref LL_ADC_CHANNEL_4
2783 * @arg @ref LL_ADC_CHANNEL_5
2784 * @arg @ref LL_ADC_CHANNEL_6
2785 * @arg @ref LL_ADC_CHANNEL_7
2786 * @arg @ref LL_ADC_CHANNEL_8
2787 * @arg @ref LL_ADC_CHANNEL_9
2788 * @arg @ref LL_ADC_CHANNEL_10
2789 * @arg @ref LL_ADC_CHANNEL_11
2790 * @arg @ref LL_ADC_CHANNEL_12
2791 * @arg @ref LL_ADC_CHANNEL_13
2792 * @arg @ref LL_ADC_CHANNEL_14
2793 * @arg @ref LL_ADC_CHANNEL_15 (1)
2794 * @arg @ref LL_ADC_CHANNEL_16 (1)
2795 * @arg @ref LL_ADC_CHANNEL_17 (1)
2796 * @arg @ref LL_ADC_CHANNEL_VREFINT
2797 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2798 * @arg @ref LL_ADC_CHANNEL_VBAT
2799 * @arg @ref LL_ADC_CHANNEL_DACCH1
2800 *
2801 * (1) On STM32WL, parameter can be set in ADC group sequencer
2802 * only if sequencer is set in mode "not fully configurable",
2803 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2804 * @retval None
2805 */
LL_ADC_REG_SetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank,uint32_t Channel)2806 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2807 {
2808 /* Set bits with content of parameter "Channel" with bits position */
2809 /* in register depending on parameter "Rank". */
2810 /* Parameters "Rank" and "Channel" are used with masks because containing */
2811 /* other bits reserved for other purpose. */
2812 MODIFY_REG(ADCx->CHSELR,
2813 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2814 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2815 << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2816 }
2817
2818 /**
2819 * @brief Get ADC group regular sequence: channel on the selected
2820 * scan sequence rank.
2821 * @note On this STM32 series, ADC group regular sequencer is
2822 * fully configurable: sequencer length and each rank
2823 * affectation to a channel are configurable.
2824 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2825 * @note Depending on devices and packages, some channels may not be available.
2826 * Refer to device datasheet for channels availability.
2827 * @note Usage of the returned channel number:
2828 * - To reinject this channel into another function LL_ADC_xxx:
2829 * the returned channel number is only partly formatted on definition
2830 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2831 * with parts of literals LL_ADC_CHANNEL_x or using
2832 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2833 * Then the selected literal LL_ADC_CHANNEL_x can be used
2834 * as parameter for another function.
2835 * - To get the channel number in decimal format:
2836 * process the returned value with the helper macro
2837 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2838 * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n
2839 * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n
2840 * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n
2841 * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n
2842 * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n
2843 * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n
2844 * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n
2845 * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks
2846 * @param ADCx ADC instance
2847 * @param Rank This parameter can be one of the following values:
2848 * @arg @ref LL_ADC_REG_RANK_1
2849 * @arg @ref LL_ADC_REG_RANK_2
2850 * @arg @ref LL_ADC_REG_RANK_3
2851 * @arg @ref LL_ADC_REG_RANK_4
2852 * @arg @ref LL_ADC_REG_RANK_5
2853 * @arg @ref LL_ADC_REG_RANK_6
2854 * @arg @ref LL_ADC_REG_RANK_7
2855 * @arg @ref LL_ADC_REG_RANK_8
2856 * @retval Returned value can be one of the following values:
2857 * @arg @ref LL_ADC_CHANNEL_0
2858 * @arg @ref LL_ADC_CHANNEL_1
2859 * @arg @ref LL_ADC_CHANNEL_2
2860 * @arg @ref LL_ADC_CHANNEL_3
2861 * @arg @ref LL_ADC_CHANNEL_4
2862 * @arg @ref LL_ADC_CHANNEL_5
2863 * @arg @ref LL_ADC_CHANNEL_6
2864 * @arg @ref LL_ADC_CHANNEL_7
2865 * @arg @ref LL_ADC_CHANNEL_8
2866 * @arg @ref LL_ADC_CHANNEL_9
2867 * @arg @ref LL_ADC_CHANNEL_10
2868 * @arg @ref LL_ADC_CHANNEL_11
2869 * @arg @ref LL_ADC_CHANNEL_12
2870 * @arg @ref LL_ADC_CHANNEL_13
2871 * @arg @ref LL_ADC_CHANNEL_14
2872 * @arg @ref LL_ADC_CHANNEL_15 (1)
2873 * @arg @ref LL_ADC_CHANNEL_16 (1)
2874 * @arg @ref LL_ADC_CHANNEL_17 (1)
2875 * @arg @ref LL_ADC_CHANNEL_VREFINT (2)
2876 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
2877 * @arg @ref LL_ADC_CHANNEL_VBAT (2)
2878 * @arg @ref LL_ADC_CHANNEL_DACCH1 (2)
2879 *
2880 * (1) On STM32WL, parameter can be set in ADC group sequencer
2881 * only if sequencer is set in mode "not fully configurable",
2882 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
2883 * (2) For ADC channel read back from ADC register,
2884 * comparison with internal channel parameter to be done
2885 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2886 */
LL_ADC_REG_GetSequencerRanks(ADC_TypeDef * ADCx,uint32_t Rank)2887 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2888 {
2889 return (uint32_t)((READ_BIT(ADCx->CHSELR,
2890 ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2891 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2892 ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
2893 );
2894 }
2895
2896 /**
2897 * @brief Set ADC group regular sequence: channel on rank corresponding to
2898 * channel number.
2899 * @note This function performs:
2900 * - Channels ordering into each rank of scan sequence:
2901 * rank of each channel is fixed by channel HW number
2902 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2903 * - Set channels selected by overwriting the current sequencer
2904 * configuration.
2905 * @note On this STM32 series, ADC group regular sequencer both modes
2906 * "fully configurable" or "not fully configurable"
2907 * are available, they can be chosen using
2908 * function @ref LL_ADC_REG_SetSequencerConfigurable().
2909 * This function can be used with setting "not fully configurable".
2910 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
2911 * and @ref LL_ADC_REG_SetSequencerLength().
2912 * @note On this STM32 series, after modifying sequencer (functions
2913 * @ref LL_ADC_REG_SetSequencerLength()
2914 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
2915 * it is mandatory to wait for the assertion of CCRDY flag
2916 * using @ref LL_ADC_IsActiveFlag_CCRDY().
2917 * Otherwise, some actions may be ignored.
2918 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
2919 * for more details.
2920 * @note Depending on devices and packages, some channels may not be available.
2921 * Refer to device datasheet for channels availability.
2922 * @note On this STM32 series, to measure internal channels (VrefInt,
2923 * TempSensor, ...), measurement paths to internal channels must be
2924 * enabled separately.
2925 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2926 * @note On this STM32 series, setting of this feature is conditioned to
2927 * ADC state:
2928 * ADC must be disabled or enabled without conversion on going
2929 * on group regular.
2930 * @note One or several values can be selected.
2931 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
2932 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
2933 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
2934 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
2935 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
2936 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
2937 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
2938 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
2939 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
2940 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
2941 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
2942 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
2943 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
2944 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
2945 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
2946 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
2947 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
2948 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
2949 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
2950 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
2951 * @param ADCx ADC instance
2952 * @param Channel This parameter can be a combination of the following values:
2953 * @arg @ref LL_ADC_CHANNEL_0
2954 * @arg @ref LL_ADC_CHANNEL_1
2955 * @arg @ref LL_ADC_CHANNEL_2
2956 * @arg @ref LL_ADC_CHANNEL_3
2957 * @arg @ref LL_ADC_CHANNEL_4
2958 * @arg @ref LL_ADC_CHANNEL_5
2959 * @arg @ref LL_ADC_CHANNEL_6
2960 * @arg @ref LL_ADC_CHANNEL_7
2961 * @arg @ref LL_ADC_CHANNEL_8
2962 * @arg @ref LL_ADC_CHANNEL_9
2963 * @arg @ref LL_ADC_CHANNEL_10
2964 * @arg @ref LL_ADC_CHANNEL_11
2965 * @arg @ref LL_ADC_CHANNEL_12
2966 * @arg @ref LL_ADC_CHANNEL_13
2967 * @arg @ref LL_ADC_CHANNEL_14
2968 * @arg @ref LL_ADC_CHANNEL_15 (1)
2969 * @arg @ref LL_ADC_CHANNEL_16 (1)
2970 * @arg @ref LL_ADC_CHANNEL_17 (1)
2971 * @arg @ref LL_ADC_CHANNEL_VREFINT
2972 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
2973 * @arg @ref LL_ADC_CHANNEL_VBAT
2974 * @arg @ref LL_ADC_CHANNEL_DACCH1
2975 *
2976 * (1) On STM32WL, parameter can be set in ADC group sequencer
2977 * only if sequencer is set in mode "not fully configurable",
2978 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
2979 * @retval None
2980 */
LL_ADC_REG_SetSequencerChannels(ADC_TypeDef * ADCx,uint32_t Channel)2981 __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
2982 {
2983 /* Parameter "Channel" is used with masks because containing */
2984 /* other bits reserved for other purpose. */
2985 WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
2986 }
2987
2988 /**
2989 * @brief Add channel to ADC group regular sequence: channel on rank corresponding to
2990 * channel number.
2991 * @note This function performs:
2992 * - Channels ordering into each rank of scan sequence:
2993 * rank of each channel is fixed by channel HW number
2994 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
2995 * - Set channels selected by adding them to the current sequencer
2996 * configuration.
2997 * @note On this STM32 series, ADC group regular sequencer both modes
2998 * "fully configurable" or "not fully configurable"
2999 * are available, they can be chosen using
3000 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3001 * This function can be used with setting "not fully configurable".
3002 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3003 * and @ref LL_ADC_REG_SetSequencerLength().
3004 * @note On this STM32 series, after modifying sequencer (functions
3005 * @ref LL_ADC_REG_SetSequencerLength()
3006 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3007 * it is mandatory to wait for the assertion of CCRDY flag
3008 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3009 * Otherwise, some actions may be ignored.
3010 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3011 * for more details.
3012 * @note Depending on devices and packages, some channels may not be available.
3013 * Refer to device datasheet for channels availability.
3014 * @note On this STM32 series, to measure internal channels (VrefInt,
3015 * TempSensor, ...), measurement paths to internal channels must be
3016 * enabled separately.
3017 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3018 * @note On this STM32 series, setting of this feature is conditioned to
3019 * ADC state:
3020 * ADC must be disabled or enabled without conversion on going
3021 * on group regular.
3022 * @note One or several values can be selected.
3023 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3024 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
3025 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
3026 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
3027 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
3028 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
3029 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
3030 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
3031 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
3032 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
3033 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
3034 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
3035 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
3036 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
3037 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
3038 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
3039 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
3040 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
3041 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
3042 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
3043 * @param ADCx ADC instance
3044 * @param Channel This parameter can be a combination of the following values:
3045 * @arg @ref LL_ADC_CHANNEL_0
3046 * @arg @ref LL_ADC_CHANNEL_1
3047 * @arg @ref LL_ADC_CHANNEL_2
3048 * @arg @ref LL_ADC_CHANNEL_3
3049 * @arg @ref LL_ADC_CHANNEL_4
3050 * @arg @ref LL_ADC_CHANNEL_5
3051 * @arg @ref LL_ADC_CHANNEL_6
3052 * @arg @ref LL_ADC_CHANNEL_7
3053 * @arg @ref LL_ADC_CHANNEL_8
3054 * @arg @ref LL_ADC_CHANNEL_9
3055 * @arg @ref LL_ADC_CHANNEL_10
3056 * @arg @ref LL_ADC_CHANNEL_11
3057 * @arg @ref LL_ADC_CHANNEL_12
3058 * @arg @ref LL_ADC_CHANNEL_13
3059 * @arg @ref LL_ADC_CHANNEL_14
3060 * @arg @ref LL_ADC_CHANNEL_15 (1)
3061 * @arg @ref LL_ADC_CHANNEL_16 (1)
3062 * @arg @ref LL_ADC_CHANNEL_17 (1)
3063 * @arg @ref LL_ADC_CHANNEL_VREFINT
3064 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3065 * @arg @ref LL_ADC_CHANNEL_VBAT
3066 * @arg @ref LL_ADC_CHANNEL_DACCH1
3067 *
3068 * (1) On STM32WL, parameter can be set in ADC group sequencer
3069 * only if sequencer is set in mode "not fully configurable",
3070 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3071 * @retval None
3072 */
LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef * ADCx,uint32_t Channel)3073 __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
3074 {
3075 /* Parameter "Channel" is used with masks because containing */
3076 /* other bits reserved for other purpose. */
3077 SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3078 }
3079
3080 /**
3081 * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
3082 * channel number.
3083 * @note This function performs:
3084 * - Channels ordering into each rank of scan sequence:
3085 * rank of each channel is fixed by channel HW number
3086 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3087 * - Set channels selected by removing them to the current sequencer
3088 * configuration.
3089 * @note On this STM32 series, ADC group regular sequencer both modes
3090 * "fully configurable" or "not fully configurable"
3091 * are available, they can be chosen using
3092 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3093 * This function can be used with setting "not fully configurable".
3094 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3095 * and @ref LL_ADC_REG_SetSequencerLength().
3096 * @note On this STM32 series, after modifying sequencer (functions
3097 * @ref LL_ADC_REG_SetSequencerLength()
3098 * @ref LL_ADC_REG_SetSequencerRanks(), ...)
3099 * it is mandatory to wait for the assertion of CCRDY flag
3100 * using @ref LL_ADC_IsActiveFlag_CCRDY().
3101 * Otherwise, some actions may be ignored.
3102 * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
3103 * for more details.
3104 * @note Depending on devices and packages, some channels may not be available.
3105 * Refer to device datasheet for channels availability.
3106 * @note On this STM32 series, to measure internal channels (VrefInt,
3107 * TempSensor, ...), measurement paths to internal channels must be
3108 * enabled separately.
3109 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3110 * @note On this STM32 series, setting of this feature is conditioned to
3111 * ADC state:
3112 * ADC must be disabled or enabled without conversion on going
3113 * on group regular.
3114 * @note One or several values can be selected.
3115 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3116 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
3117 * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
3118 * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
3119 * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
3120 * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
3121 * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
3122 * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
3123 * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
3124 * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
3125 * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
3126 * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
3127 * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
3128 * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
3129 * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
3130 * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
3131 * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
3132 * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
3133 * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
3134 * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
3135 * @param ADCx ADC instance
3136 * @param Channel This parameter can be a combination of the following values:
3137 * @arg @ref LL_ADC_CHANNEL_0
3138 * @arg @ref LL_ADC_CHANNEL_1
3139 * @arg @ref LL_ADC_CHANNEL_2
3140 * @arg @ref LL_ADC_CHANNEL_3
3141 * @arg @ref LL_ADC_CHANNEL_4
3142 * @arg @ref LL_ADC_CHANNEL_5
3143 * @arg @ref LL_ADC_CHANNEL_6
3144 * @arg @ref LL_ADC_CHANNEL_7
3145 * @arg @ref LL_ADC_CHANNEL_8
3146 * @arg @ref LL_ADC_CHANNEL_9
3147 * @arg @ref LL_ADC_CHANNEL_10
3148 * @arg @ref LL_ADC_CHANNEL_11
3149 * @arg @ref LL_ADC_CHANNEL_12
3150 * @arg @ref LL_ADC_CHANNEL_13
3151 * @arg @ref LL_ADC_CHANNEL_14
3152 * @arg @ref LL_ADC_CHANNEL_15 (1)
3153 * @arg @ref LL_ADC_CHANNEL_16 (1)
3154 * @arg @ref LL_ADC_CHANNEL_17 (1)
3155 * @arg @ref LL_ADC_CHANNEL_VREFINT
3156 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3157 * @arg @ref LL_ADC_CHANNEL_VBAT
3158 * @arg @ref LL_ADC_CHANNEL_DACCH1
3159 *
3160 * (1) On STM32WL, parameter can be set in ADC group sequencer
3161 * only if sequencer is set in mode "not fully configurable",
3162 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3163 * @retval None
3164 */
LL_ADC_REG_SetSequencerChRem(ADC_TypeDef * ADCx,uint32_t Channel)3165 __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
3166 {
3167 /* Parameter "Channel" is used with masks because containing */
3168 /* other bits reserved for other purpose. */
3169 CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
3170 }
3171
3172 /**
3173 * @brief Get ADC group regular sequence: channel on rank corresponding to
3174 * channel number.
3175 * @note This function performs:
3176 * - Channels order reading into each rank of scan sequence:
3177 * rank of each channel is fixed by channel HW number
3178 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3179 * @note On this STM32 series, ADC group regular sequencer both modes
3180 * "fully configurable" or "not fully configurable"
3181 * are available, they can be chosen using
3182 * function @ref LL_ADC_REG_SetSequencerConfigurable().
3183 * This function can be used with setting "not fully configurable".
3184 * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
3185 * and @ref LL_ADC_REG_SetSequencerLength().
3186 * @note Depending on devices and packages, some channels may not be available.
3187 * Refer to device datasheet for channels availability.
3188 * @note On this STM32 series, to measure internal channels (VrefInt,
3189 * TempSensor, ...), measurement paths to internal channels must be
3190 * enabled separately.
3191 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3192 * @note On this STM32 series, setting of this feature is conditioned to
3193 * ADC state:
3194 * ADC must be disabled or enabled without conversion on going
3195 * on group regular.
3196 * @note One or several values can be retrieved.
3197 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
3198 * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
3199 * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
3200 * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
3201 * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
3202 * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
3203 * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
3204 * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
3205 * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
3206 * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
3207 * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
3208 * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
3209 * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
3210 * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
3211 * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
3212 * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
3213 * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
3214 * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
3215 * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
3216 * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
3217 * @param ADCx ADC instance
3218 * @retval Returned value can be a combination of the following values:
3219 * @arg @ref LL_ADC_CHANNEL_0
3220 * @arg @ref LL_ADC_CHANNEL_1
3221 * @arg @ref LL_ADC_CHANNEL_2
3222 * @arg @ref LL_ADC_CHANNEL_3
3223 * @arg @ref LL_ADC_CHANNEL_4
3224 * @arg @ref LL_ADC_CHANNEL_5
3225 * @arg @ref LL_ADC_CHANNEL_6
3226 * @arg @ref LL_ADC_CHANNEL_7
3227 * @arg @ref LL_ADC_CHANNEL_8
3228 * @arg @ref LL_ADC_CHANNEL_9
3229 * @arg @ref LL_ADC_CHANNEL_10
3230 * @arg @ref LL_ADC_CHANNEL_11
3231 * @arg @ref LL_ADC_CHANNEL_12
3232 * @arg @ref LL_ADC_CHANNEL_13
3233 * @arg @ref LL_ADC_CHANNEL_14
3234 * @arg @ref LL_ADC_CHANNEL_15 (1)
3235 * @arg @ref LL_ADC_CHANNEL_16 (1)
3236 * @arg @ref LL_ADC_CHANNEL_17 (1)
3237 * @arg @ref LL_ADC_CHANNEL_VREFINT
3238 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3239 * @arg @ref LL_ADC_CHANNEL_VBAT
3240 * @arg @ref LL_ADC_CHANNEL_DACCH1
3241 *
3242 * (1) On STM32WL, parameter can be set in ADC group sequencer
3243 * only if sequencer is set in mode "not fully configurable",
3244 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3245 */
LL_ADC_REG_GetSequencerChannels(ADC_TypeDef * ADCx)3246 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
3247 {
3248 uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
3249
3250 return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
3251 | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
3252 | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
3253 | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
3254 | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
3255 | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
3256 | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
3257 | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
3258 | (((channels_bitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
3259 | (((channels_bitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
3260 | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
3261 | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
3262 | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
3263 | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
3264 | (((channels_bitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
3265 | (((channels_bitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
3266 | (((channels_bitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
3267 | (((channels_bitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
3268 );
3269 }
3270
3271 /**
3272 * @brief Set ADC continuous conversion mode on ADC group regular.
3273 * @note Description of ADC continuous conversion mode:
3274 * - single mode: one conversion per trigger
3275 * - continuous mode: after the first trigger, following
3276 * conversions launched successively automatically.
3277 * @note It is not possible to enable both ADC group regular
3278 * continuous mode and sequencer discontinuous mode.
3279 * @note On this STM32 series, setting of this feature is conditioned to
3280 * ADC state:
3281 * ADC must be disabled.
3282 * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
3283 * @param ADCx ADC instance
3284 * @param Continuous This parameter can be one of the following values:
3285 * @arg @ref LL_ADC_REG_CONV_SINGLE
3286 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3287 * @retval None
3288 */
LL_ADC_REG_SetContinuousMode(ADC_TypeDef * ADCx,uint32_t Continuous)3289 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
3290 {
3291 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
3292 }
3293
3294 /**
3295 * @brief Get ADC continuous conversion mode on ADC group regular.
3296 * @note Description of ADC continuous conversion mode:
3297 * - single mode: one conversion per trigger
3298 * - continuous mode: after the first trigger, following
3299 * conversions launched successively automatically.
3300 * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
3301 * @param ADCx ADC instance
3302 * @retval Returned value can be one of the following values:
3303 * @arg @ref LL_ADC_REG_CONV_SINGLE
3304 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
3305 */
LL_ADC_REG_GetContinuousMode(ADC_TypeDef * ADCx)3306 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
3307 {
3308 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
3309 }
3310
3311 /**
3312 * @brief Set ADC group regular conversion data transfer: no transfer or
3313 * transfer by DMA, and DMA requests mode.
3314 * @note If transfer by DMA selected, specifies the DMA requests
3315 * mode:
3316 * - Limited mode (One shot mode): DMA transfer requests are stopped
3317 * when number of DMA data transfers (number of
3318 * ADC conversions) is reached.
3319 * This ADC mode is intended to be used with DMA mode non-circular.
3320 * - Unlimited mode: DMA transfer requests are unlimited,
3321 * whatever number of DMA data transfers (number of
3322 * ADC conversions).
3323 * This ADC mode is intended to be used with DMA mode circular.
3324 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3325 * mode non-circular:
3326 * when DMA transfers size will be reached, DMA will stop transfers of
3327 * ADC conversions data ADC will raise an overrun error
3328 * (overrun flag and interruption if enabled).
3329 * @note To configure DMA source address (peripheral address),
3330 * use function @ref LL_ADC_DMA_GetRegAddr().
3331 * @note On this STM32 series, setting of this feature is conditioned to
3332 * ADC state:
3333 * ADC must be disabled.
3334 * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
3335 * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
3336 * @param ADCx ADC instance
3337 * @param DMATransfer This parameter can be one of the following values:
3338 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3339 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3340 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3341 * @retval None
3342 */
LL_ADC_REG_SetDMATransfer(ADC_TypeDef * ADCx,uint32_t DMATransfer)3343 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
3344 {
3345 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
3346 }
3347
3348 /**
3349 * @brief Get ADC group regular conversion data transfer: no transfer or
3350 * transfer by DMA, and DMA requests mode.
3351 * @note If transfer by DMA selected, specifies the DMA requests
3352 * mode:
3353 * - Limited mode (One shot mode): DMA transfer requests are stopped
3354 * when number of DMA data transfers (number of
3355 * ADC conversions) is reached.
3356 * This ADC mode is intended to be used with DMA mode non-circular.
3357 * - Unlimited mode: DMA transfer requests are unlimited,
3358 * whatever number of DMA data transfers (number of
3359 * ADC conversions).
3360 * This ADC mode is intended to be used with DMA mode circular.
3361 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
3362 * mode non-circular:
3363 * when DMA transfers size will be reached, DMA will stop transfers of
3364 * ADC conversions data ADC will raise an overrun error
3365 * (overrun flag and interruption if enabled).
3366 * @note To configure DMA source address (peripheral address),
3367 * use function @ref LL_ADC_DMA_GetRegAddr().
3368 * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
3369 * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
3370 * @param ADCx ADC instance
3371 * @retval Returned value can be one of the following values:
3372 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
3373 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
3374 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
3375 */
LL_ADC_REG_GetDMATransfer(ADC_TypeDef * ADCx)3376 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
3377 {
3378 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
3379 }
3380
3381 /**
3382 * @brief Set ADC group regular behavior in case of overrun:
3383 * data preserved or overwritten.
3384 * @note Compatibility with devices without feature overrun:
3385 * other devices without this feature have a behavior
3386 * equivalent to data overwritten.
3387 * The default setting of overrun is data preserved.
3388 * Therefore, for compatibility with all devices, parameter
3389 * overrun should be set to data overwritten.
3390 * @note On this STM32 series, setting of this feature is conditioned to
3391 * ADC state:
3392 * ADC must be disabled.
3393 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
3394 * @param ADCx ADC instance
3395 * @param Overrun This parameter can be one of the following values:
3396 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3397 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3398 * @retval None
3399 */
LL_ADC_REG_SetOverrun(ADC_TypeDef * ADCx,uint32_t Overrun)3400 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
3401 {
3402 MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
3403 }
3404
3405 /**
3406 * @brief Get ADC group regular behavior in case of overrun:
3407 * data preserved or overwritten.
3408 * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
3409 * @param ADCx ADC instance
3410 * @retval Returned value can be one of the following values:
3411 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
3412 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
3413 */
LL_ADC_REG_GetOverrun(ADC_TypeDef * ADCx)3414 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
3415 {
3416 return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
3417 }
3418
3419 /**
3420 * @}
3421 */
3422
3423 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
3424 * @{
3425 */
3426
3427 /**
3428 * @brief Set sampling time of the selected ADC channel
3429 * Unit: ADC clock cycles.
3430 * @note On this device, sampling time is on channel scope: independently
3431 * of channel mapped on ADC group regular or injected.
3432 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
3433 * converted:
3434 * sampling time constraints must be respected (sampling time can be
3435 * adjusted in function of ADC clock frequency and sampling time
3436 * setting).
3437 * Refer to device datasheet for timings values (parameters TS_vrefint,
3438 * TS_temp, ...).
3439 * @note Conversion time is the addition of sampling time and processing time.
3440 * Refer to reference manual for ADC processing time of
3441 * this STM32 series.
3442 * @note In case of ADC conversion of internal channel (VrefInt,
3443 * temperature sensor, ...), a sampling time minimum value
3444 * is required.
3445 * Refer to device datasheet.
3446 * @note On this STM32 series, setting of this feature is conditioned to
3447 * ADC state:
3448 * ADC must be disabled or enabled without conversion on going
3449 * on group regular.
3450 * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n
3451 * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n
3452 * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n
3453 * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n
3454 * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n
3455 * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n
3456 * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n
3457 * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n
3458 * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n
3459 * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n
3460 * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n
3461 * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n
3462 * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n
3463 * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n
3464 * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n
3465 * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n
3466 * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n
3467 * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n
3468 * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime
3469 * @param ADCx ADC instance
3470 * @param Channel This parameter can be a combination of the following values:
3471 * @arg @ref LL_ADC_CHANNEL_0
3472 * @arg @ref LL_ADC_CHANNEL_1
3473 * @arg @ref LL_ADC_CHANNEL_2
3474 * @arg @ref LL_ADC_CHANNEL_3
3475 * @arg @ref LL_ADC_CHANNEL_4
3476 * @arg @ref LL_ADC_CHANNEL_5
3477 * @arg @ref LL_ADC_CHANNEL_6
3478 * @arg @ref LL_ADC_CHANNEL_7
3479 * @arg @ref LL_ADC_CHANNEL_8
3480 * @arg @ref LL_ADC_CHANNEL_9
3481 * @arg @ref LL_ADC_CHANNEL_10
3482 * @arg @ref LL_ADC_CHANNEL_11
3483 * @arg @ref LL_ADC_CHANNEL_12
3484 * @arg @ref LL_ADC_CHANNEL_13
3485 * @arg @ref LL_ADC_CHANNEL_14
3486 * @arg @ref LL_ADC_CHANNEL_15 (1)
3487 * @arg @ref LL_ADC_CHANNEL_16 (1)
3488 * @arg @ref LL_ADC_CHANNEL_17 (1)
3489 * @arg @ref LL_ADC_CHANNEL_VREFINT
3490 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3491 * @arg @ref LL_ADC_CHANNEL_VBAT
3492 * @arg @ref LL_ADC_CHANNEL_DACCH1
3493 *
3494 * (1) On STM32WL, parameter can be set in ADC group sequencer
3495 * only if sequencer is set in mode "not fully configurable",
3496 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3497 * @param SamplingTimeY This parameter can be one of the following values:
3498 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3499 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3500 * @retval None
3501 */
LL_ADC_SetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel,uint32_t SamplingTimeY)3502 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
3503 {
3504 /* Parameter "Channel" is used with masks because containing */
3505 /* other bits reserved for other purpose. */
3506 MODIFY_REG(ADCx->SMPR,
3507 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
3508 (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
3509 );
3510 }
3511
3512 /**
3513 * @brief Get sampling time of the selected ADC channel
3514 * Unit: ADC clock cycles.
3515 * @note On this device, sampling time is on channel scope: independently
3516 * of channel mapped on ADC group regular or injected.
3517 * @note Conversion time is the addition of sampling time and processing time.
3518 * Refer to reference manual for ADC processing time of
3519 * this STM32 series.
3520 * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n
3521 * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n
3522 * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n
3523 * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n
3524 * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n
3525 * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n
3526 * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n
3527 * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n
3528 * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n
3529 * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n
3530 * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n
3531 * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n
3532 * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n
3533 * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n
3534 * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n
3535 * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n
3536 * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n
3537 * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n
3538 * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime
3539 * @param ADCx ADC instance
3540 * @param Channel This parameter can be one of the following values:
3541 * @arg @ref LL_ADC_CHANNEL_0
3542 * @arg @ref LL_ADC_CHANNEL_1
3543 * @arg @ref LL_ADC_CHANNEL_2
3544 * @arg @ref LL_ADC_CHANNEL_3
3545 * @arg @ref LL_ADC_CHANNEL_4
3546 * @arg @ref LL_ADC_CHANNEL_5
3547 * @arg @ref LL_ADC_CHANNEL_6
3548 * @arg @ref LL_ADC_CHANNEL_7
3549 * @arg @ref LL_ADC_CHANNEL_8
3550 * @arg @ref LL_ADC_CHANNEL_9
3551 * @arg @ref LL_ADC_CHANNEL_10
3552 * @arg @ref LL_ADC_CHANNEL_11
3553 * @arg @ref LL_ADC_CHANNEL_12
3554 * @arg @ref LL_ADC_CHANNEL_13
3555 * @arg @ref LL_ADC_CHANNEL_14
3556 * @arg @ref LL_ADC_CHANNEL_15 (1)
3557 * @arg @ref LL_ADC_CHANNEL_16 (1)
3558 * @arg @ref LL_ADC_CHANNEL_17 (1)
3559 * @arg @ref LL_ADC_CHANNEL_VREFINT
3560 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
3561 * @arg @ref LL_ADC_CHANNEL_VBAT
3562 * @arg @ref LL_ADC_CHANNEL_DACCH1
3563 *
3564 * (1) On STM32WL, parameter can be set in ADC group sequencer
3565 * only if sequencer is set in mode "not fully configurable",
3566 * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
3567 * @retval Returned value can be one of the following values:
3568 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
3569 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
3570 */
LL_ADC_GetChannelSamplingTime(ADC_TypeDef * ADCx,uint32_t Channel)3571 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
3572 {
3573 __IO uint32_t smpr = READ_REG(ADCx->SMPR);
3574
3575 /* Retrieve sampling time bit corresponding to the selected channel */
3576 /* and shift it to position 0. */
3577 uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
3578 >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
3579 + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
3580 & 0x1FUL));
3581
3582 /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */
3583 return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
3584 | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
3585 }
3586
3587 /**
3588 * @}
3589 */
3590
3591 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
3592 * @{
3593 */
3594
3595 /**
3596 * @brief Set ADC analog watchdog monitored channels:
3597 * a single channel, multiple channels or all channels,
3598 * on ADC group regular.
3599 * @note Once monitored channels are selected, analog watchdog
3600 * is enabled.
3601 * @note In case of need to define a single channel to monitor
3602 * with analog watchdog from sequencer channel definition,
3603 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
3604 * @note On this STM32 series, there are 2 kinds of analog watchdog
3605 * instance:
3606 * - AWD standard (instance AWD1):
3607 * - channels monitored: can monitor 1 channel or all channels.
3608 * - groups monitored: ADC group regular.
3609 * - resolution: resolution is not limited (corresponds to
3610 * ADC resolution configured).
3611 * - AWD flexible (instances AWD2, AWD3):
3612 * - channels monitored: flexible on channels monitored, selection is
3613 * channel wise, from from 1 to all channels.
3614 * Specificity of this analog watchdog: Multiple channels can
3615 * be selected. For example:
3616 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3617 * - groups monitored: not selection possible (monitoring on both
3618 * groups regular and injected).
3619 * Channels selected are monitored on groups regular and injected:
3620 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3621 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3622 * - resolution: resolution is not limited (corresponds to
3623 * ADC resolution configured).
3624 * @note On this STM32 series, setting of this feature is conditioned to
3625 * ADC state:
3626 * ADC must be disabled.
3627 * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
3628 * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
3629 * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
3630 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
3631 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
3632 * @param ADCx ADC instance
3633 * @param AWDy This parameter can be one of the following values:
3634 * @arg @ref LL_ADC_AWD1
3635 * @arg @ref LL_ADC_AWD2
3636 * @arg @ref LL_ADC_AWD3
3637 * @param AWDChannelGroup This parameter can be one of the following values:
3638 * @arg @ref LL_ADC_AWD_DISABLE
3639 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3640 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3641 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3642 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3643 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3644 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3645 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3646 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3647 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3648 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3649 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3650 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3651 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3652 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3653 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3654 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3655 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3656 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3657 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3658 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG
3659 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
3660 * @arg @ref LL_ADC_AWD_CH_VBAT_REG
3661 * @arg @ref LL_ADC_AWD_CH_DACCH1_REG
3662 * @retval None
3663 */
LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDChannelGroup)3664 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
3665 {
3666 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
3667 /* in register and register position depending on parameter "AWDy". */
3668 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
3669 /* containing other bits reserved for other purpose. */
3670 __IO uint32_t *preg;
3671
3672 if (AWDy == LL_ADC_AWD1)
3673 {
3674 preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
3675 }
3676 else
3677 {
3678 preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
3679 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
3680 }
3681
3682 MODIFY_REG(*preg,
3683 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
3684 AWDChannelGroup & AWDy);
3685 }
3686
3687 /**
3688 * @brief Get ADC analog watchdog monitored channel.
3689 * @note Usage of the returned channel number:
3690 * - To reinject this channel into another function LL_ADC_xxx:
3691 * the returned channel number is only partly formatted on definition
3692 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3693 * with parts of literals LL_ADC_CHANNEL_x or using
3694 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3695 * Then the selected literal LL_ADC_CHANNEL_x can be used
3696 * as parameter for another function.
3697 * - To get the channel number in decimal format:
3698 * process the returned value with the helper macro
3699 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3700 * Applicable only when the analog watchdog is set to monitor
3701 * one channel.
3702 * @note On this STM32 series, there are 2 kinds of analog watchdog
3703 * instance:
3704 * - AWD standard (instance AWD1):
3705 * - channels monitored: can monitor 1 channel or all channels.
3706 * - groups monitored: ADC group regular.
3707 * - resolution: resolution is not limited (corresponds to
3708 * ADC resolution configured).
3709 * - AWD flexible (instances AWD2, AWD3):
3710 * - channels monitored: flexible on channels monitored, selection is
3711 * channel wise, from from 1 to all channels.
3712 * Specificity of this analog watchdog: Multiple channels can
3713 * be selected. For example:
3714 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3715 * - groups monitored: not selection possible (monitoring on both
3716 * groups regular and injected).
3717 * Channels selected are monitored on groups regular and injected:
3718 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3719 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3720 * - resolution: resolution is not limited (corresponds to
3721 * ADC resolution configured).
3722 * @note On this STM32 series, setting of this feature is conditioned to
3723 * ADC state:
3724 * ADC must be disabled or enabled without conversion on going
3725 * on group regular.
3726 * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3727 * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3728 * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
3729 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
3730 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
3731 * @param ADCx ADC instance
3732 * @param AWDy This parameter can be one of the following values:
3733 * @arg @ref LL_ADC_AWD1
3734 * @arg @ref LL_ADC_AWD2 (1)
3735 * @arg @ref LL_ADC_AWD3 (1)
3736 *
3737 * (1) On this AWD number, monitored channel can be retrieved
3738 * if only 1 channel is programmed (or none or all channels).
3739 * This function cannot retrieve monitored channel if
3740 * multiple channels are programmed simultaneously
3741 * by bitfield.
3742 * @retval Returned value can be one of the following values:
3743 * @arg @ref LL_ADC_AWD_DISABLE
3744 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3745 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3746 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3747 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3748 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3749 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3750 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3751 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3752 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3753 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3754 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3755 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3756 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3757 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3758 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3759 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3760 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3761 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3762 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3763 */
LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef * ADCx,uint32_t AWDy)3764 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
3765 {
3766 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
3767 ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
3768 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
3769 * ADC_AWD_CR12_REGOFFSETGAP_VAL));
3770
3771 uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
3772
3773 /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */
3774 /* (parameter value LL_ADC_AWD_DISABLE). */
3775 /* Else, the selected AWD is enabled and is monitoring a group of channels */
3776 /* or a single channel. */
3777 if (analog_wd_monit_channels != 0UL)
3778 {
3779 if (AWDy == LL_ADC_AWD1)
3780 {
3781 if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL)
3782 {
3783 /* AWD monitoring a group of channels */
3784 analog_wd_monit_channels = ((analog_wd_monit_channels
3785 | (ADC_AWD_CR23_CHANNEL_MASK)
3786 )
3787 & (~(ADC_CFGR1_AWD1CH))
3788 );
3789 }
3790 else
3791 {
3792 /* AWD monitoring a single channel */
3793 analog_wd_monit_channels = (analog_wd_monit_channels
3794 | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos))
3795 );
3796 }
3797 }
3798 else
3799 {
3800 if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
3801 {
3802 /* AWD monitoring a group of channels */
3803 analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
3804 | (ADC_CFGR1_AWD1EN)
3805 );
3806 }
3807 else
3808 {
3809 /* AWD monitoring a single channel */
3810 /* AWD monitoring a group of channels */
3811 analog_wd_monit_channels = (analog_wd_monit_channels
3812 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
3813 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos)
3814 );
3815 }
3816 }
3817 }
3818
3819 return analog_wd_monit_channels;
3820 }
3821
3822 /**
3823 * @brief Set ADC analog watchdog thresholds value of both thresholds
3824 * high and low.
3825 * @note If value of only one threshold high or low must be set,
3826 * use function @ref LL_ADC_SetAnalogWDThresholds().
3827 * @note In case of ADC resolution different of 12 bits,
3828 * analog watchdog thresholds data require a specific shift.
3829 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3830 * @note On this STM32 series, there are 2 kinds of analog watchdog
3831 * instance:
3832 * - AWD standard (instance AWD1):
3833 * - channels monitored: can monitor 1 channel or all channels.
3834 * - groups monitored: ADC group regular.
3835 * - resolution: resolution is not limited (corresponds to
3836 * ADC resolution configured).
3837 * - AWD flexible (instances AWD2, AWD3):
3838 * - channels monitored: flexible on channels monitored, selection is
3839 * channel wise, from from 1 to all channels.
3840 * Specificity of this analog watchdog: Multiple channels can
3841 * be selected. For example:
3842 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3843 * - groups monitored: not selection possible (monitoring on both
3844 * groups regular and injected).
3845 * Channels selected are monitored on groups regular and injected:
3846 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3847 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3848 * - resolution: resolution is not limited (corresponds to
3849 * ADC resolution configured).
3850 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3851 * impacted: the comparison of analog watchdog thresholds is done on
3852 * oversampling final computation (after ratio and shift application):
3853 * ADC data register bitfield [15:4] (12 most significant bits).
3854 * Examples:
3855 * - Oversampling ratio and shift selected to have ADC conversion data
3856 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3857 * ADC analog watchdog thresholds must be divided by 16.
3858 * - Oversampling ratio and shift selected to have ADC conversion data
3859 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3860 * ADC analog watchdog thresholds must be divided by 4.
3861 * - Oversampling ratio and shift selected to have ADC conversion data
3862 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3863 * ADC analog watchdog thresholds match directly to ADC data register.
3864 * @note On this STM32 series, setting of this feature is conditioned to
3865 * ADC state:
3866 * ADC must be disabled or enabled without conversion on going
3867 * on group regular.
3868 * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n
3869 * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n
3870 * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n
3871 * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n
3872 * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n
3873 * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds
3874 * @param ADCx ADC instance
3875 * @param AWDy This parameter can be one of the following values:
3876 * @arg @ref LL_ADC_AWD1
3877 * @arg @ref LL_ADC_AWD2
3878 * @arg @ref LL_ADC_AWD3
3879 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
3880 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
3881 * @retval None
3882 */
LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdHighValue,uint32_t AWDThresholdLowValue)3883 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
3884 uint32_t AWDThresholdLowValue)
3885 {
3886 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
3887 /* position in register and register position depending on parameter */
3888 /* "AWDy". */
3889 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
3890 /* containing other bits reserved for other purpose. */
3891 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3892 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3893 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3894 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3895 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
3896 );
3897
3898 MODIFY_REG(*preg,
3899 ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
3900 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
3901 }
3902
3903 /**
3904 * @brief Set ADC analog watchdog threshold value of threshold
3905 * high or low.
3906 * @note If values of both thresholds high or low must be set,
3907 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
3908 * @note In case of ADC resolution different of 12 bits,
3909 * analog watchdog thresholds data require a specific shift.
3910 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
3911 * @note On this STM32 series, there are 2 kinds of analog watchdog
3912 * instance:
3913 * - AWD standard (instance AWD1):
3914 * - channels monitored: can monitor 1 channel or all channels.
3915 * - groups monitored: ADC group regular.
3916 * - resolution: resolution is not limited (corresponds to
3917 * ADC resolution configured).
3918 * - AWD flexible (instances AWD2, AWD3):
3919 * - channels monitored: flexible on channels monitored, selection is
3920 * channel wise, from from 1 to all channels.
3921 * Specificity of this analog watchdog: Multiple channels can
3922 * be selected. For example:
3923 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
3924 * - groups monitored: not selection possible (monitoring on both
3925 * groups regular and injected).
3926 * Channels selected are monitored on groups regular and injected:
3927 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
3928 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
3929 * - resolution: resolution is not limited (corresponds to
3930 * ADC resolution configured).
3931 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
3932 * impacted: the comparison of analog watchdog thresholds is done on
3933 * oversampling final computation (after ratio and shift application):
3934 * ADC data register bitfield [15:4] (12 most significant bits).
3935 * Examples:
3936 * - Oversampling ratio and shift selected to have ADC conversion data
3937 * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
3938 * ADC analog watchdog thresholds must be divided by 16.
3939 * - Oversampling ratio and shift selected to have ADC conversion data
3940 * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
3941 * ADC analog watchdog thresholds must be divided by 4.
3942 * - Oversampling ratio and shift selected to have ADC conversion data
3943 * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
3944 * ADC analog watchdog thresholds match directly to ADC data register.
3945 * @note On this STM32 series, setting of this feature is not conditioned to
3946 * ADC state:
3947 * ADC can be disabled, enabled with or without conversion on going
3948 * on ADC group regular.
3949 * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n
3950 * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n
3951 * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n
3952 * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n
3953 * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n
3954 * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds
3955 * @param ADCx ADC instance
3956 * @param AWDy This parameter can be one of the following values:
3957 * @arg @ref LL_ADC_AWD1
3958 * @arg @ref LL_ADC_AWD2
3959 * @arg @ref LL_ADC_AWD3
3960 * @param AWDThresholdsHighLow This parameter can be one of the following values:
3961 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3962 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3963 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
3964 * @retval None
3965 */
LL_ADC_SetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow,uint32_t AWDThresholdValue)3966 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
3967 uint32_t AWDThresholdValue)
3968 {
3969 /* Set bits with content of parameter "AWDThresholdValue" with bits */
3970 /* position in register and register position depending on parameters */
3971 /* "AWDThresholdsHighLow" and "AWDy". */
3972 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
3973 /* containing other bits reserved for other purpose. */
3974 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
3975 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
3976 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
3977 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
3978 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
3979
3980 MODIFY_REG(*preg,
3981 AWDThresholdsHighLow,
3982 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
3983 }
3984
3985 /**
3986 * @brief Get ADC analog watchdog threshold value of threshold high,
3987 * threshold low or raw data with ADC thresholds high and low
3988 * concatenated.
3989 * @note If raw data with ADC thresholds high and low is retrieved,
3990 * the data of each threshold high or low can be isolated
3991 * using helper macro:
3992 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
3993 * @note In case of ADC resolution different of 12 bits,
3994 * analog watchdog thresholds data require a specific shift.
3995 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3996 * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n
3997 * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n
3998 * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n
3999 * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n
4000 * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n
4001 * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds
4002 * @param ADCx ADC instance
4003 * @param AWDy This parameter can be one of the following values:
4004 * @arg @ref LL_ADC_AWD1
4005 * @arg @ref LL_ADC_AWD2
4006 * @arg @ref LL_ADC_AWD3
4007 * @param AWDThresholdsHighLow This parameter can be one of the following values:
4008 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
4009 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
4010 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
4011 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4012 */
LL_ADC_GetAnalogWDThresholds(ADC_TypeDef * ADCx,uint32_t AWDy,uint32_t AWDThresholdsHighLow)4013 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
4014 {
4015 /* Set bits with content of parameter "AWDThresholdValue" with bits */
4016 /* position in register and register position depending on parameters */
4017 /* "AWDThresholdsHighLow" and "AWDy". */
4018 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
4019 /* containing other bits reserved for other purpose. */
4020 const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
4021 (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
4022 >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
4023 + ((ADC_AWD_CR3_REGOFFSET & AWDy)
4024 >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
4025
4026 return (uint32_t)(READ_BIT(*preg,
4027 (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
4028 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
4029 & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1)));
4030 }
4031
4032 /**
4033 * @}
4034 */
4035
4036 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
4037 * @{
4038 */
4039
4040 /**
4041 * @brief Set ADC oversampling scope.
4042 * @note On this STM32 series, setting of this feature is conditioned to
4043 * ADC state:
4044 * ADC must be disabled.
4045 * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope
4046 * @param ADCx ADC instance
4047 * @param OvsScope This parameter can be one of the following values:
4048 * @arg @ref LL_ADC_OVS_DISABLE
4049 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4050 * @retval None
4051 */
LL_ADC_SetOverSamplingScope(ADC_TypeDef * ADCx,uint32_t OvsScope)4052 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
4053 {
4054 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
4055 }
4056
4057 /**
4058 * @brief Get ADC oversampling scope.
4059 * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope
4060 * @param ADCx ADC instance
4061 * @retval Returned value can be one of the following values:
4062 * @arg @ref LL_ADC_OVS_DISABLE
4063 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
4064 */
LL_ADC_GetOverSamplingScope(ADC_TypeDef * ADCx)4065 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
4066 {
4067 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
4068 }
4069
4070 /**
4071 * @brief Set ADC oversampling discontinuous mode (triggered mode)
4072 * on the selected ADC group.
4073 * @note Number of oversampled conversions are done either in:
4074 * - continuous mode (all conversions of oversampling ratio
4075 * are done from 1 trigger)
4076 * - discontinuous mode (each conversion of oversampling ratio
4077 * needs a trigger)
4078 * @note On this STM32 series, setting of this feature is conditioned to
4079 * ADC state:
4080 * ADC must be disabled.
4081 * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont
4082 * @param ADCx ADC instance
4083 * @param OverSamplingDiscont This parameter can be one of the following values:
4084 * @arg @ref LL_ADC_OVS_REG_CONT
4085 * @arg @ref LL_ADC_OVS_REG_DISCONT
4086 * @retval None
4087 */
LL_ADC_SetOverSamplingDiscont(ADC_TypeDef * ADCx,uint32_t OverSamplingDiscont)4088 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
4089 {
4090 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
4091 }
4092
4093 /**
4094 * @brief Get ADC oversampling discontinuous mode (triggered mode)
4095 * on the selected ADC group.
4096 * @note Number of oversampled conversions are done either in:
4097 * - continuous mode (all conversions of oversampling ratio
4098 * are done from 1 trigger)
4099 * - discontinuous mode (each conversion of oversampling ratio
4100 * needs a trigger)
4101 * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont
4102 * @param ADCx ADC instance
4103 * @retval Returned value can be one of the following values:
4104 * @arg @ref LL_ADC_OVS_REG_CONT
4105 * @arg @ref LL_ADC_OVS_REG_DISCONT
4106 */
LL_ADC_GetOverSamplingDiscont(ADC_TypeDef * ADCx)4107 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
4108 {
4109 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
4110 }
4111
4112 /**
4113 * @brief Set ADC oversampling
4114 * @note This function set the 2 items of oversampling configuration:
4115 * - ratio
4116 * - shift
4117 * @note On this STM32 series, setting of this feature is conditioned to
4118 * ADC state:
4119 * ADC must be disabled.
4120 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
4121 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
4122 * @param ADCx ADC instance
4123 * @param Ratio This parameter can be one of the following values:
4124 * @arg @ref LL_ADC_OVS_RATIO_2
4125 * @arg @ref LL_ADC_OVS_RATIO_4
4126 * @arg @ref LL_ADC_OVS_RATIO_8
4127 * @arg @ref LL_ADC_OVS_RATIO_16
4128 * @arg @ref LL_ADC_OVS_RATIO_32
4129 * @arg @ref LL_ADC_OVS_RATIO_64
4130 * @arg @ref LL_ADC_OVS_RATIO_128
4131 * @arg @ref LL_ADC_OVS_RATIO_256
4132 * @param Shift This parameter can be one of the following values:
4133 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4134 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4135 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4136 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4137 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4138 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4139 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4140 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4141 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4142 * @retval None
4143 */
LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef * ADCx,uint32_t Ratio,uint32_t Shift)4144 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
4145 {
4146 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
4147 }
4148
4149 /**
4150 * @brief Get ADC oversampling ratio
4151 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
4152 * @param ADCx ADC instance
4153 * @retval Ratio This parameter can be one of the following values:
4154 * @arg @ref LL_ADC_OVS_RATIO_2
4155 * @arg @ref LL_ADC_OVS_RATIO_4
4156 * @arg @ref LL_ADC_OVS_RATIO_8
4157 * @arg @ref LL_ADC_OVS_RATIO_16
4158 * @arg @ref LL_ADC_OVS_RATIO_32
4159 * @arg @ref LL_ADC_OVS_RATIO_64
4160 * @arg @ref LL_ADC_OVS_RATIO_128
4161 * @arg @ref LL_ADC_OVS_RATIO_256
4162 */
LL_ADC_GetOverSamplingRatio(ADC_TypeDef * ADCx)4163 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
4164 {
4165 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
4166 }
4167
4168 /**
4169 * @brief Get ADC oversampling shift
4170 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
4171 * @param ADCx ADC instance
4172 * @retval Shift This parameter can be one of the following values:
4173 * @arg @ref LL_ADC_OVS_SHIFT_NONE
4174 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
4175 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
4176 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
4177 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
4178 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
4179 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
4180 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
4181 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
4182 */
LL_ADC_GetOverSamplingShift(ADC_TypeDef * ADCx)4183 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
4184 {
4185 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
4186 }
4187
4188 /**
4189 * @}
4190 */
4191
4192 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
4193 * @{
4194 */
4195
4196 /**
4197 * @brief Enable ADC instance internal voltage regulator.
4198 * @note On this STM32 series, there are three possibilities to enable
4199 * the voltage regulator:
4200 * - by enabling it manually
4201 * using function @ref LL_ADC_EnableInternalRegulator().
4202 * - by launching a calibration
4203 * using function @ref LL_ADC_StartCalibration().
4204 * - by enabling the ADC
4205 * using function @ref LL_ADC_Enable().
4206 * @note On this STM32 series, after ADC internal voltage regulator enable,
4207 * a delay for ADC internal voltage regulator stabilization
4208 * is required before performing a ADC calibration or ADC enable.
4209 * Refer to device datasheet, parameter "tADCVREG_STUP".
4210 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
4211 * @note On this STM32 series, setting of this feature is conditioned to
4212 * ADC state:
4213 * ADC must be ADC disabled.
4214 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
4215 * @param ADCx ADC instance
4216 * @retval None
4217 */
LL_ADC_EnableInternalRegulator(ADC_TypeDef * ADCx)4218 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
4219 {
4220 /* Note: Write register with some additional bits forced to state reset */
4221 /* instead of modifying only the selected bit for this function, */
4222 /* to not interfere with bits with HW property "rs". */
4223 MODIFY_REG(ADCx->CR,
4224 ADC_CR_BITS_PROPERTY_RS,
4225 ADC_CR_ADVREGEN);
4226 }
4227
4228 /**
4229 * @brief Disable ADC internal voltage regulator.
4230 * @note On this STM32 series, setting of this feature is conditioned to
4231 * ADC state:
4232 * ADC must be ADC disabled.
4233 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
4234 * @param ADCx ADC instance
4235 * @retval None
4236 */
LL_ADC_DisableInternalRegulator(ADC_TypeDef * ADCx)4237 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
4238 {
4239 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
4240 }
4241
4242 /**
4243 * @brief Get the selected ADC instance internal voltage regulator state.
4244 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
4245 * @param ADCx ADC instance
4246 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
4247 */
LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef * ADCx)4248 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
4249 {
4250 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
4251 }
4252
4253 /**
4254 * @brief Enable the selected ADC instance.
4255 * @note On this STM32 series, after ADC enable, a delay for
4256 * ADC internal analog stabilization is required before performing a
4257 * ADC conversion start.
4258 * Refer to device datasheet, parameter tSTAB.
4259 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4260 * is enabled and when conversion clock is active.
4261 * (not only core clock: this ADC has a dual clock domain)
4262 * @note On this STM32 series, setting of this feature is conditioned to
4263 * ADC state:
4264 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
4265 * @rmtoll CR ADEN LL_ADC_Enable
4266 * @param ADCx ADC instance
4267 * @retval None
4268 */
LL_ADC_Enable(ADC_TypeDef * ADCx)4269 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
4270 {
4271 /* Note: Write register with some additional bits forced to state reset */
4272 /* instead of modifying only the selected bit for this function, */
4273 /* to not interfere with bits with HW property "rs". */
4274 MODIFY_REG(ADCx->CR,
4275 ADC_CR_BITS_PROPERTY_RS,
4276 ADC_CR_ADEN);
4277 }
4278
4279 /**
4280 * @brief Disable the selected ADC instance.
4281 * @note On this STM32 series, setting of this feature is conditioned to
4282 * ADC state:
4283 * ADC must be not disabled. Must be enabled without conversion on going
4284 * on group regular.
4285 * @rmtoll CR ADDIS LL_ADC_Disable
4286 * @param ADCx ADC instance
4287 * @retval None
4288 */
LL_ADC_Disable(ADC_TypeDef * ADCx)4289 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
4290 {
4291 /* Note: Write register with some additional bits forced to state reset */
4292 /* instead of modifying only the selected bit for this function, */
4293 /* to not interfere with bits with HW property "rs". */
4294 MODIFY_REG(ADCx->CR,
4295 ADC_CR_BITS_PROPERTY_RS,
4296 ADC_CR_ADDIS);
4297 }
4298
4299 /**
4300 * @brief Get the selected ADC instance enable state.
4301 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4302 * is enabled and when conversion clock is active.
4303 * (not only core clock: this ADC has a dual clock domain)
4304 * @rmtoll CR ADEN LL_ADC_IsEnabled
4305 * @param ADCx ADC instance
4306 * @retval 0: ADC is disabled, 1: ADC is enabled.
4307 */
LL_ADC_IsEnabled(ADC_TypeDef * ADCx)4308 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
4309 {
4310 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
4311 }
4312
4313 /**
4314 * @brief Get the selected ADC instance disable state.
4315 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
4316 * @param ADCx ADC instance
4317 * @retval 0: no ADC disable command on going.
4318 */
LL_ADC_IsDisableOngoing(ADC_TypeDef * ADCx)4319 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
4320 {
4321 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
4322 }
4323
4324 /**
4325 * @brief Start ADC calibration in the mode single-ended
4326 * or differential (for devices with differential mode available).
4327 * @note On this STM32 series, a minimum number of ADC clock cycles
4328 * are required between ADC end of calibration and ADC enable.
4329 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
4330 * @note In case of usage of ADC with DMA transfer:
4331 * On this STM32 series, ADC DMA transfer request should be disabled
4332 * during calibration:
4333 * Calibration factor is available in data register
4334 * and also transferred by DMA.
4335 * To not insert ADC calibration factor among ADC conversion data
4336 * in array variable, DMA transfer must be disabled during
4337 * calibration.
4338 * (DMA transfer setting backup and disable before calibration,
4339 * DMA transfer setting restore after calibration.
4340 * Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
4341 * @ref LL_ADC_REG_SetDMATransfer() ).
4342 * @note In case of usage of feature auto power-off:
4343 * This mode must be disabled during calibration
4344 * Refer to function @ref LL_ADC_SetLowPowerMode().
4345 * @note On this STM32 series, setting of this feature is conditioned to
4346 * ADC state:
4347 * ADC must be ADC disabled.
4348 * @rmtoll CR ADCAL LL_ADC_StartCalibration
4349 * @param ADCx ADC instance
4350 * @retval None
4351 */
LL_ADC_StartCalibration(ADC_TypeDef * ADCx)4352 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
4353 {
4354 /* Note: Write register with some additional bits forced to state reset */
4355 /* instead of modifying only the selected bit for this function, */
4356 /* to not interfere with bits with HW property "rs". */
4357 MODIFY_REG(ADCx->CR,
4358 ADC_CR_BITS_PROPERTY_RS,
4359 ADC_CR_ADCAL);
4360 }
4361
4362 /**
4363 * @brief Get ADC calibration state.
4364 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
4365 * @param ADCx ADC instance
4366 * @retval 0: calibration complete, 1: calibration in progress.
4367 */
LL_ADC_IsCalibrationOnGoing(ADC_TypeDef * ADCx)4368 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
4369 {
4370 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
4371 }
4372
4373 /**
4374 * @}
4375 */
4376
4377 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
4378 * @{
4379 */
4380
4381 /**
4382 * @brief Start ADC group regular conversion.
4383 * @note On this STM32 series, this function is relevant for both
4384 * internal trigger (SW start) and external trigger:
4385 * - If ADC trigger has been set to software start, ADC conversion
4386 * starts immediately.
4387 * - If ADC trigger has been set to external trigger, ADC conversion
4388 * will start at next trigger event (on the selected trigger edge)
4389 * following the ADC start conversion command.
4390 * @note On this STM32 series, setting of this feature is conditioned to
4391 * ADC state:
4392 * ADC must be enabled without conversion on going on group regular,
4393 * without conversion stop command on going on group regular,
4394 * without ADC disable command on going.
4395 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
4396 * @param ADCx ADC instance
4397 * @retval None
4398 */
LL_ADC_REG_StartConversion(ADC_TypeDef * ADCx)4399 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
4400 {
4401 /* Note: Write register with some additional bits forced to state reset */
4402 /* instead of modifying only the selected bit for this function, */
4403 /* to not interfere with bits with HW property "rs". */
4404 MODIFY_REG(ADCx->CR,
4405 ADC_CR_BITS_PROPERTY_RS,
4406 ADC_CR_ADSTART);
4407 }
4408
4409 /**
4410 * @brief Stop ADC group regular conversion.
4411 * @note On this STM32 series, setting of this feature is conditioned to
4412 * ADC state:
4413 * ADC must be enabled with conversion on going on group regular,
4414 * without ADC disable command on going.
4415 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
4416 * @param ADCx ADC instance
4417 * @retval None
4418 */
LL_ADC_REG_StopConversion(ADC_TypeDef * ADCx)4419 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
4420 {
4421 /* Note: Write register with some additional bits forced to state reset */
4422 /* instead of modifying only the selected bit for this function, */
4423 /* to not interfere with bits with HW property "rs". */
4424 MODIFY_REG(ADCx->CR,
4425 ADC_CR_BITS_PROPERTY_RS,
4426 ADC_CR_ADSTP);
4427 }
4428
4429 /**
4430 * @brief Get ADC group regular conversion state.
4431 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
4432 * @param ADCx ADC instance
4433 * @retval 0: no conversion is on going on ADC group regular.
4434 */
LL_ADC_REG_IsConversionOngoing(ADC_TypeDef * ADCx)4435 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
4436 {
4437 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
4438 }
4439
4440 /**
4441 * @brief Get ADC group regular command of conversion stop state
4442 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
4443 * @param ADCx ADC instance
4444 * @retval 0: no command of conversion stop is on going on ADC group regular.
4445 */
LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef * ADCx)4446 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
4447 {
4448 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
4449 }
4450
4451 /**
4452 * @brief Get ADC group regular conversion data, range fit for
4453 * all ADC configurations: all ADC resolutions and
4454 * all oversampling increased data width (for devices
4455 * with feature oversampling).
4456 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
4457 * @param ADCx ADC instance
4458 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
4459 */
LL_ADC_REG_ReadConversionData32(ADC_TypeDef * ADCx)4460 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
4461 {
4462 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4463 }
4464
4465 /**
4466 * @brief Get ADC group regular conversion data, range fit for
4467 * ADC resolution 12 bits.
4468 * @note For devices with feature oversampling: Oversampling
4469 * can increase data width, function for extended range
4470 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4471 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
4472 * @param ADCx ADC instance
4473 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
4474 */
LL_ADC_REG_ReadConversionData12(ADC_TypeDef * ADCx)4475 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
4476 {
4477 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4478 }
4479
4480 /**
4481 * @brief Get ADC group regular conversion data, range fit for
4482 * ADC resolution 10 bits.
4483 * @note For devices with feature oversampling: Oversampling
4484 * can increase data width, function for extended range
4485 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4486 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
4487 * @param ADCx ADC instance
4488 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
4489 */
LL_ADC_REG_ReadConversionData10(ADC_TypeDef * ADCx)4490 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
4491 {
4492 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4493 }
4494
4495 /**
4496 * @brief Get ADC group regular conversion data, range fit for
4497 * ADC resolution 8 bits.
4498 * @note For devices with feature oversampling: Oversampling
4499 * can increase data width, function for extended range
4500 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4501 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
4502 * @param ADCx ADC instance
4503 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
4504 */
LL_ADC_REG_ReadConversionData8(ADC_TypeDef * ADCx)4505 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
4506 {
4507 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4508 }
4509
4510 /**
4511 * @brief Get ADC group regular conversion data, range fit for
4512 * ADC resolution 6 bits.
4513 * @note For devices with feature oversampling: Oversampling
4514 * can increase data width, function for extended range
4515 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
4516 * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
4517 * @param ADCx ADC instance
4518 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
4519 */
LL_ADC_REG_ReadConversionData6(ADC_TypeDef * ADCx)4520 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
4521 {
4522 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4523 }
4524
4525 /**
4526 * @}
4527 */
4528
4529 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
4530 * @{
4531 */
4532
4533 /**
4534 * @brief Get flag ADC ready.
4535 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4536 * is enabled and when conversion clock is active.
4537 * (not only core clock: this ADC has a dual clock domain)
4538 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
4539 * @param ADCx ADC instance
4540 * @retval State of bit (1 or 0).
4541 */
LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef * ADCx)4542 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
4543 {
4544 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
4545 }
4546
4547 /**
4548 * @brief Get flag ADC channel configuration ready.
4549 * @note On this STM32 series, after modifying sequencer
4550 * it is mandatory to wait for the assertion of CCRDY flag
4551 * using @ref LL_ADC_IsActiveFlag_CCRDY().
4552 * Otherwise, performing some actions (configuration update,
4553 * ADC conversion start, ... ) will be ignored.
4554 * Functions requiring wait for CCRDY flag are:
4555 * @ref LL_ADC_REG_SetSequencerLength()
4556 * @ref LL_ADC_REG_SetSequencerRanks()
4557 * @ref LL_ADC_REG_SetSequencerChannels()
4558 * @ref LL_ADC_REG_SetSequencerChAdd()
4559 * @ref LL_ADC_REG_SetSequencerChRem()
4560 * @ref LL_ADC_REG_SetSequencerScanDirection()
4561 * @ref LL_ADC_REG_SetSequencerConfigurable()
4562 * @note Duration of ADC channel configuration ready: CCRDY handshake
4563 * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
4564 * has been changed.
4565 * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY
4566 * @param ADCx ADC instance
4567 * @retval State of bit (1 or 0).
4568 */
LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef * ADCx)4569 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
4570 {
4571 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
4572 }
4573
4574 /**
4575 * @brief Get flag ADC group regular end of unitary conversion.
4576 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
4577 * @param ADCx ADC instance
4578 * @retval State of bit (1 or 0).
4579 */
LL_ADC_IsActiveFlag_EOC(ADC_TypeDef * ADCx)4580 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
4581 {
4582 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
4583 }
4584
4585 /**
4586 * @brief Get flag ADC group regular end of sequence conversions.
4587 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
4588 * @param ADCx ADC instance
4589 * @retval State of bit (1 or 0).
4590 */
LL_ADC_IsActiveFlag_EOS(ADC_TypeDef * ADCx)4591 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
4592 {
4593 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
4594 }
4595
4596 /**
4597 * @brief Get flag ADC group regular overrun.
4598 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
4599 * @param ADCx ADC instance
4600 * @retval State of bit (1 or 0).
4601 */
LL_ADC_IsActiveFlag_OVR(ADC_TypeDef * ADCx)4602 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
4603 {
4604 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
4605 }
4606
4607 /**
4608 * @brief Get flag ADC group regular end of sampling phase.
4609 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
4610 * @param ADCx ADC instance
4611 * @retval State of bit (1 or 0).
4612 */
LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef * ADCx)4613 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
4614 {
4615 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
4616 }
4617
4618 /**
4619 * @brief Get flag ADC analog watchdog 1 flag
4620 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
4621 * @param ADCx ADC instance
4622 * @retval State of bit (1 or 0).
4623 */
LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef * ADCx)4624 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
4625 {
4626 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
4627 }
4628
4629 /**
4630 * @brief Get flag ADC analog watchdog 2.
4631 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
4632 * @param ADCx ADC instance
4633 * @retval State of bit (1 or 0).
4634 */
LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef * ADCx)4635 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
4636 {
4637 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
4638 }
4639
4640 /**
4641 * @brief Get flag ADC analog watchdog 3.
4642 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
4643 * @param ADCx ADC instance
4644 * @retval State of bit (1 or 0).
4645 */
LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef * ADCx)4646 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
4647 {
4648 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
4649 }
4650
4651 /**
4652 * @brief Get flag ADC end of calibration.
4653 * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
4654 * @param ADCx ADC instance
4655 * @retval State of bit (1 or 0).
4656 */
LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef * ADCx)4657 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
4658 {
4659 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
4660 }
4661
4662 /**
4663 * @brief Clear flag ADC ready.
4664 * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
4665 * is enabled and when conversion clock is active.
4666 * (not only core clock: this ADC has a dual clock domain)
4667 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
4668 * @param ADCx ADC instance
4669 * @retval None
4670 */
LL_ADC_ClearFlag_ADRDY(ADC_TypeDef * ADCx)4671 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
4672 {
4673 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
4674 }
4675
4676 /**
4677 * @brief Clear flag ADC channel configuration ready.
4678 * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
4679 * @param ADCx ADC instance
4680 * @retval State of bit (1 or 0).
4681 */
LL_ADC_ClearFlag_CCRDY(ADC_TypeDef * ADCx)4682 __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
4683 {
4684 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
4685 }
4686
4687 /**
4688 * @brief Clear flag ADC group regular end of unitary conversion.
4689 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
4690 * @param ADCx ADC instance
4691 * @retval None
4692 */
LL_ADC_ClearFlag_EOC(ADC_TypeDef * ADCx)4693 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
4694 {
4695 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
4696 }
4697
4698 /**
4699 * @brief Clear flag ADC group regular end of sequence conversions.
4700 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
4701 * @param ADCx ADC instance
4702 * @retval None
4703 */
LL_ADC_ClearFlag_EOS(ADC_TypeDef * ADCx)4704 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
4705 {
4706 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
4707 }
4708
4709 /**
4710 * @brief Clear flag ADC group regular overrun.
4711 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
4712 * @param ADCx ADC instance
4713 * @retval None
4714 */
LL_ADC_ClearFlag_OVR(ADC_TypeDef * ADCx)4715 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4716 {
4717 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
4718 }
4719
4720 /**
4721 * @brief Clear flag ADC group regular end of sampling phase.
4722 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
4723 * @param ADCx ADC instance
4724 * @retval None
4725 */
LL_ADC_ClearFlag_EOSMP(ADC_TypeDef * ADCx)4726 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
4727 {
4728 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
4729 }
4730
4731 /**
4732 * @brief Clear flag ADC analog watchdog 1.
4733 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
4734 * @param ADCx ADC instance
4735 * @retval None
4736 */
LL_ADC_ClearFlag_AWD1(ADC_TypeDef * ADCx)4737 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4738 {
4739 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
4740 }
4741
4742 /**
4743 * @brief Clear flag ADC analog watchdog 2.
4744 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
4745 * @param ADCx ADC instance
4746 * @retval None
4747 */
LL_ADC_ClearFlag_AWD2(ADC_TypeDef * ADCx)4748 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
4749 {
4750 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
4751 }
4752
4753 /**
4754 * @brief Clear flag ADC analog watchdog 3.
4755 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
4756 * @param ADCx ADC instance
4757 * @retval None
4758 */
LL_ADC_ClearFlag_AWD3(ADC_TypeDef * ADCx)4759 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
4760 {
4761 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
4762 }
4763
4764 /**
4765 * @brief Clear flag ADC end of calibration.
4766 * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
4767 * @param ADCx ADC instance
4768 * @retval None
4769 */
LL_ADC_ClearFlag_EOCAL(ADC_TypeDef * ADCx)4770 __STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
4771 {
4772 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
4773 }
4774
4775 /**
4776 * @}
4777 */
4778
4779 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
4780 * @{
4781 */
4782
4783 /**
4784 * @brief Enable ADC ready.
4785 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
4786 * @param ADCx ADC instance
4787 * @retval None
4788 */
LL_ADC_EnableIT_ADRDY(ADC_TypeDef * ADCx)4789 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
4790 {
4791 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4792 }
4793
4794 /**
4795 * @brief Enable interruption ADC channel configuration ready.
4796 * @rmtoll IER CCRDYIE LL_ADC_EnableIT_CCRDY
4797 * @param ADCx ADC instance
4798 * @retval State of bit (1 or 0).
4799 */
LL_ADC_EnableIT_CCRDY(ADC_TypeDef * ADCx)4800 __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
4801 {
4802 SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
4803 }
4804
4805 /**
4806 * @brief Enable interruption ADC group regular end of unitary conversion.
4807 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
4808 * @param ADCx ADC instance
4809 * @retval None
4810 */
LL_ADC_EnableIT_EOC(ADC_TypeDef * ADCx)4811 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
4812 {
4813 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
4814 }
4815
4816 /**
4817 * @brief Enable interruption ADC group regular end of sequence conversions.
4818 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
4819 * @param ADCx ADC instance
4820 * @retval None
4821 */
LL_ADC_EnableIT_EOS(ADC_TypeDef * ADCx)4822 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
4823 {
4824 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
4825 }
4826
4827 /**
4828 * @brief Enable ADC group regular interruption overrun.
4829 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
4830 * @param ADCx ADC instance
4831 * @retval None
4832 */
LL_ADC_EnableIT_OVR(ADC_TypeDef * ADCx)4833 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4834 {
4835 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
4836 }
4837
4838 /**
4839 * @brief Enable interruption ADC group regular end of sampling.
4840 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
4841 * @param ADCx ADC instance
4842 * @retval None
4843 */
LL_ADC_EnableIT_EOSMP(ADC_TypeDef * ADCx)4844 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
4845 {
4846 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4847 }
4848
4849 /**
4850 * @brief Enable interruption ADC analog watchdog 1.
4851 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
4852 * @param ADCx ADC instance
4853 * @retval None
4854 */
LL_ADC_EnableIT_AWD1(ADC_TypeDef * ADCx)4855 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4856 {
4857 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4858 }
4859
4860 /**
4861 * @brief Enable interruption ADC analog watchdog 2.
4862 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
4863 * @param ADCx ADC instance
4864 * @retval None
4865 */
LL_ADC_EnableIT_AWD2(ADC_TypeDef * ADCx)4866 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
4867 {
4868 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4869 }
4870
4871 /**
4872 * @brief Enable interruption ADC analog watchdog 3.
4873 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
4874 * @param ADCx ADC instance
4875 * @retval None
4876 */
LL_ADC_EnableIT_AWD3(ADC_TypeDef * ADCx)4877 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
4878 {
4879 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4880 }
4881
4882 /**
4883 * @brief Enable interruption ADC end of calibration.
4884 * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
4885 * @param ADCx ADC instance
4886 * @retval None
4887 */
LL_ADC_EnableIT_EOCAL(ADC_TypeDef * ADCx)4888 __STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
4889 {
4890 SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
4891 }
4892
4893 /**
4894 * @brief Disable interruption ADC ready.
4895 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
4896 * @param ADCx ADC instance
4897 * @retval None
4898 */
LL_ADC_DisableIT_ADRDY(ADC_TypeDef * ADCx)4899 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
4900 {
4901 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
4902 }
4903
4904 /**
4905 * @brief Disable interruption ADC channel configuration ready.
4906 * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY
4907 * @param ADCx ADC instance
4908 * @retval State of bit (1 or 0).
4909 */
LL_ADC_DisableIT_CCRDY(ADC_TypeDef * ADCx)4910 __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
4911 {
4912 CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
4913 }
4914
4915 /**
4916 * @brief Disable interruption ADC group regular end of unitary conversion.
4917 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
4918 * @param ADCx ADC instance
4919 * @retval None
4920 */
LL_ADC_DisableIT_EOC(ADC_TypeDef * ADCx)4921 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
4922 {
4923 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
4924 }
4925
4926 /**
4927 * @brief Disable interruption ADC group regular end of sequence conversions.
4928 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
4929 * @param ADCx ADC instance
4930 * @retval None
4931 */
LL_ADC_DisableIT_EOS(ADC_TypeDef * ADCx)4932 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
4933 {
4934 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
4935 }
4936
4937 /**
4938 * @brief Disable interruption ADC group regular overrun.
4939 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
4940 * @param ADCx ADC instance
4941 * @retval None
4942 */
LL_ADC_DisableIT_OVR(ADC_TypeDef * ADCx)4943 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4944 {
4945 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
4946 }
4947
4948 /**
4949 * @brief Disable interruption ADC group regular end of sampling.
4950 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
4951 * @param ADCx ADC instance
4952 * @retval None
4953 */
LL_ADC_DisableIT_EOSMP(ADC_TypeDef * ADCx)4954 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
4955 {
4956 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
4957 }
4958
4959 /**
4960 * @brief Disable interruption ADC analog watchdog 1.
4961 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
4962 * @param ADCx ADC instance
4963 * @retval None
4964 */
LL_ADC_DisableIT_AWD1(ADC_TypeDef * ADCx)4965 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4966 {
4967 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
4968 }
4969
4970 /**
4971 * @brief Disable interruption ADC analog watchdog 2.
4972 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
4973 * @param ADCx ADC instance
4974 * @retval None
4975 */
LL_ADC_DisableIT_AWD2(ADC_TypeDef * ADCx)4976 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
4977 {
4978 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
4979 }
4980
4981 /**
4982 * @brief Disable interruption ADC analog watchdog 3.
4983 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
4984 * @param ADCx ADC instance
4985 * @retval None
4986 */
LL_ADC_DisableIT_AWD3(ADC_TypeDef * ADCx)4987 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
4988 {
4989 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
4990 }
4991
4992 /**
4993 * @brief Disable interruption ADC end of calibration.
4994 * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
4995 * @param ADCx ADC instance
4996 * @retval None
4997 */
LL_ADC_DisableIT_EOCAL(ADC_TypeDef * ADCx)4998 __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
4999 {
5000 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
5001 }
5002
5003 /**
5004 * @brief Get state of interruption ADC ready
5005 * (0: interrupt disabled, 1: interrupt enabled).
5006 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
5007 * @param ADCx ADC instance
5008 * @retval State of bit (1 or 0).
5009 */
LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef * ADCx)5010 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
5011 {
5012 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
5013 }
5014
5015 /**
5016 * @brief Get state of interruption ADC channel configuration ready.
5017 * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY
5018 * @param ADCx ADC instance
5019 * @retval State of bit (1 or 0).
5020 */
LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef * ADCx)5021 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
5022 {
5023 return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
5024 }
5025
5026 /**
5027 * @brief Get state of interruption ADC group regular end of unitary conversion
5028 * (0: interrupt disabled, 1: interrupt enabled).
5029 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
5030 * @param ADCx ADC instance
5031 * @retval State of bit (1 or 0).
5032 */
LL_ADC_IsEnabledIT_EOC(ADC_TypeDef * ADCx)5033 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
5034 {
5035 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
5036 }
5037
5038 /**
5039 * @brief Get state of interruption ADC group regular end of sequence conversions
5040 * (0: interrupt disabled, 1: interrupt enabled).
5041 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
5042 * @param ADCx ADC instance
5043 * @retval State of bit (1 or 0).
5044 */
LL_ADC_IsEnabledIT_EOS(ADC_TypeDef * ADCx)5045 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
5046 {
5047 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
5048 }
5049
5050 /**
5051 * @brief Get state of interruption ADC group regular overrun
5052 * (0: interrupt disabled, 1: interrupt enabled).
5053 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
5054 * @param ADCx ADC instance
5055 * @retval State of bit (1 or 0).
5056 */
LL_ADC_IsEnabledIT_OVR(ADC_TypeDef * ADCx)5057 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
5058 {
5059 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
5060 }
5061
5062 /**
5063 * @brief Get state of interruption ADC group regular end of sampling
5064 * (0: interrupt disabled, 1: interrupt enabled).
5065 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
5066 * @param ADCx ADC instance
5067 * @retval State of bit (1 or 0).
5068 */
LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef * ADCx)5069 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
5070 {
5071 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
5072 }
5073
5074 /**
5075 * @brief Get state of interruption ADC analog watchdog 1
5076 * (0: interrupt disabled, 1: interrupt enabled).
5077 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
5078 * @param ADCx ADC instance
5079 * @retval State of bit (1 or 0).
5080 */
LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef * ADCx)5081 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
5082 {
5083 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
5084 }
5085
5086 /**
5087 * @brief Get state of interruption Get ADC analog watchdog 2
5088 * (0: interrupt disabled, 1: interrupt enabled).
5089 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
5090 * @param ADCx ADC instance
5091 * @retval State of bit (1 or 0).
5092 */
LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef * ADCx)5093 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
5094 {
5095 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
5096 }
5097
5098 /**
5099 * @brief Get state of interruption Get ADC analog watchdog 3
5100 * (0: interrupt disabled, 1: interrupt enabled).
5101 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
5102 * @param ADCx ADC instance
5103 * @retval State of bit (1 or 0).
5104 */
LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef * ADCx)5105 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
5106 {
5107 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
5108 }
5109
5110 /**
5111 * @brief Get state of interruption ADC end of calibration
5112 * (0: interrupt disabled, 1: interrupt enabled).
5113 * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL
5114 * @param ADCx ADC instance
5115 * @retval State of bit (1 or 0).
5116 */
LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef * ADCx)5117 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
5118 {
5119 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
5120 }
5121
5122 /**
5123 * @}
5124 */
5125
5126 #if defined(USE_FULL_LL_DRIVER)
5127 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
5128 * @{
5129 */
5130
5131 /* Initialization of some features of ADC common parameters and multimode */
5132 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
5133 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5134 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
5135
5136 /* De-initialization of ADC instance */
5137 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
5138
5139 /* Initialization of some features of ADC instance */
5140 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct);
5141 void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
5142
5143 /* Initialization of some features of ADC instance and ADC group regular */
5144 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5145 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
5146
5147 /**
5148 * @}
5149 */
5150 #endif /* USE_FULL_LL_DRIVER */
5151
5152 /**
5153 * @}
5154 */
5155
5156 /**
5157 * @}
5158 */
5159
5160 #endif /* ADC */
5161
5162 /**
5163 * @}
5164 */
5165
5166 #ifdef __cplusplus
5167 }
5168 #endif
5169
5170 #endif /* STM32WLxx_LL_ADC_H */
5171
